Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Support PCI/PCIe on PowerNV platforms |
| 3 | * |
| 4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 12 | #undef DEBUG |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/pci.h> |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 16 | #include <linux/crash_dump.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 17 | #include <linux/delay.h> |
| 18 | #include <linux/string.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/bootmem.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/msi.h> |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 24 | #include <linux/memblock.h> |
Alexey Kardashevskiy | ac9a588 | 2015-06-05 16:34:56 +1000 | [diff] [blame] | 25 | #include <linux/iommu.h> |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 26 | #include <linux/rculist.h> |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 27 | #include <linux/sizes.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 28 | |
| 29 | #include <asm/sections.h> |
| 30 | #include <asm/io.h> |
| 31 | #include <asm/prom.h> |
| 32 | #include <asm/pci-bridge.h> |
| 33 | #include <asm/machdep.h> |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 34 | #include <asm/msi_bitmap.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 35 | #include <asm/ppc-pci.h> |
| 36 | #include <asm/opal.h> |
| 37 | #include <asm/iommu.h> |
| 38 | #include <asm/tce.h> |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 39 | #include <asm/xics.h> |
Michael Ellerman | 7644d58 | 2017-02-10 12:04:56 +1100 | [diff] [blame] | 40 | #include <asm/debugfs.h> |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 41 | #include <asm/firmware.h> |
Ian Munsie | 80c49c7 | 2014-10-08 19:54:57 +1100 | [diff] [blame] | 42 | #include <asm/pnv-pci.h> |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 43 | #include <asm/mmzone.h> |
Ian Munsie | 80c49c7 | 2014-10-08 19:54:57 +1100 | [diff] [blame] | 44 | |
Michael Neuling | ec249dd | 2015-05-27 16:07:16 +1000 | [diff] [blame] | 45 | #include <misc/cxl-base.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 46 | |
| 47 | #include "powernv.h" |
| 48 | #include "pci.h" |
| 49 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 50 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
| 51 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 52 | #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 53 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 54 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
| 55 | #define POWERNV_IOMMU_MAX_LEVELS 5 |
| 56 | |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 57 | static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK", |
| 58 | "NPU_OCAPI" }; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 59 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
| 60 | |
Alexey Kardashevskiy | 7d623e4 | 2016-04-29 18:55:21 +1000 | [diff] [blame] | 61 | void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 62 | const char *fmt, ...) |
| 63 | { |
| 64 | struct va_format vaf; |
| 65 | va_list args; |
| 66 | char pfix[32]; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 67 | |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 68 | va_start(args, fmt); |
| 69 | |
| 70 | vaf.fmt = fmt; |
| 71 | vaf.va = &args; |
| 72 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 73 | if (pe->flags & PNV_IODA_PE_DEV) |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 74 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 75 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 76 | sprintf(pfix, "%04x:%02x ", |
| 77 | pci_domain_nr(pe->pbus), pe->pbus->number); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 78 | #ifdef CONFIG_PCI_IOV |
| 79 | else if (pe->flags & PNV_IODA_PE_VF) |
| 80 | sprintf(pfix, "%04x:%02x:%2x.%d", |
| 81 | pci_domain_nr(pe->parent_dev->bus), |
| 82 | (pe->rid & 0xff00) >> 8, |
| 83 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); |
| 84 | #endif /* CONFIG_PCI_IOV*/ |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 85 | |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 86 | printk("%spci %s: [PE# %.2x] %pV", |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 87 | level, pfix, pe->pe_number, &vaf); |
| 88 | |
| 89 | va_end(args); |
| 90 | } |
| 91 | |
Thadeu Lima de Souza Cascardo | 4e28784 | 2014-10-23 19:19:35 -0200 | [diff] [blame] | 92 | static bool pnv_iommu_bypass_disabled __read_mostly; |
Guilherme G. Piccoli | 45baee1 | 2017-11-17 16:58:59 -0200 | [diff] [blame] | 93 | static bool pci_reset_phbs __read_mostly; |
Thadeu Lima de Souza Cascardo | 4e28784 | 2014-10-23 19:19:35 -0200 | [diff] [blame] | 94 | |
| 95 | static int __init iommu_setup(char *str) |
| 96 | { |
| 97 | if (!str) |
| 98 | return -EINVAL; |
| 99 | |
| 100 | while (*str) { |
| 101 | if (!strncmp(str, "nobypass", 8)) { |
| 102 | pnv_iommu_bypass_disabled = true; |
| 103 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); |
| 104 | break; |
| 105 | } |
| 106 | str += strcspn(str, ","); |
| 107 | if (*str == ',') |
| 108 | str++; |
| 109 | } |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | early_param("iommu", iommu_setup); |
| 114 | |
Guilherme G. Piccoli | 45baee1 | 2017-11-17 16:58:59 -0200 | [diff] [blame] | 115 | static int __init pci_reset_phbs_setup(char *str) |
| 116 | { |
| 117 | pci_reset_phbs = true; |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup); |
| 122 | |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 123 | static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 124 | { |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 125 | /* |
| 126 | * WARNING: We cannot rely on the resource flags. The Linux PCI |
| 127 | * allocation code sometimes decides to put a 64-bit prefetchable |
| 128 | * BAR in the 32-bit window, so we have to compare the addresses. |
| 129 | * |
| 130 | * For simplicity we only test resource start. |
| 131 | */ |
| 132 | return (r->start >= phb->ioda.m64_base && |
| 133 | r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 134 | } |
| 135 | |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 136 | static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) |
| 137 | { |
| 138 | unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); |
| 139 | |
| 140 | return (resource_flags & flags) == flags; |
| 141 | } |
| 142 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 143 | static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) |
| 144 | { |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 145 | s64 rc; |
| 146 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 147 | phb->ioda.pe_array[pe_no].phb = phb; |
| 148 | phb->ioda.pe_array[pe_no].pe_number = pe_no; |
| 149 | |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 150 | /* |
| 151 | * Clear the PE frozen state as it might be put into frozen state |
| 152 | * in the last PCI remove path. It's not harmful to do so when the |
| 153 | * PE is already in unfrozen state. |
| 154 | */ |
| 155 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 156 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
Russell Currey | d4791db | 2016-11-16 12:12:26 +1100 | [diff] [blame] | 157 | if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 158 | pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 159 | __func__, rc, phb->hose->global_number, pe_no); |
| 160 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 161 | return &phb->ioda.pe_array[pe_no]; |
| 162 | } |
| 163 | |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 164 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
| 165 | { |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 166 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 167 | pr_warn("%s: Invalid PE %x on PHB#%x\n", |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 168 | __func__, pe_no, phb->hose->global_number); |
| 169 | return; |
| 170 | } |
| 171 | |
Gavin Shan | e9dc4d7 | 2015-06-19 12:26:16 +1000 | [diff] [blame] | 172 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 173 | pr_debug("%s: PE %x was reserved on PHB#%x\n", |
Gavin Shan | e9dc4d7 | 2015-06-19 12:26:16 +1000 | [diff] [blame] | 174 | __func__, pe_no, phb->hose->global_number); |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 175 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 176 | pnv_ioda_init_pe(phb, pe_no); |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 177 | } |
| 178 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 179 | static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 180 | { |
Andrzej Hajda | 6096481 | 2016-08-17 12:03:05 +0200 | [diff] [blame] | 181 | long pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 182 | |
Gavin Shan | 9fcd6f4 | 2016-05-20 16:41:30 +1000 | [diff] [blame] | 183 | for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { |
| 184 | if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) |
| 185 | return pnv_ioda_init_pe(phb, pe); |
| 186 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 187 | |
Gavin Shan | 9fcd6f4 | 2016-05-20 16:41:30 +1000 | [diff] [blame] | 188 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 189 | } |
| 190 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 191 | static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 192 | { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 193 | struct pnv_phb *phb = pe->phb; |
Gavin Shan | caa58f8 | 2016-09-06 14:17:18 +1000 | [diff] [blame] | 194 | unsigned int pe_num = pe->pe_number; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 195 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 196 | WARN_ON(pe->pdev); |
| 197 | |
| 198 | memset(pe, 0, sizeof(struct pnv_ioda_pe)); |
Gavin Shan | caa58f8 | 2016-09-06 14:17:18 +1000 | [diff] [blame] | 199 | clear_bit(pe_num, phb->ioda.pe_alloc); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 200 | } |
| 201 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 202 | /* The default M64 BAR is shared by all PEs */ |
| 203 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) |
| 204 | { |
| 205 | const char *desc; |
| 206 | struct resource *r; |
| 207 | s64 rc; |
| 208 | |
| 209 | /* Configure the default M64 BAR */ |
| 210 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
| 211 | OPAL_M64_WINDOW_TYPE, |
| 212 | phb->ioda.m64_bar_idx, |
| 213 | phb->ioda.m64_base, |
| 214 | 0, /* unused */ |
| 215 | phb->ioda.m64_size); |
| 216 | if (rc != OPAL_SUCCESS) { |
| 217 | desc = "configuring"; |
| 218 | goto fail; |
| 219 | } |
| 220 | |
| 221 | /* Enable the default M64 BAR */ |
| 222 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
| 223 | OPAL_M64_WINDOW_TYPE, |
| 224 | phb->ioda.m64_bar_idx, |
| 225 | OPAL_ENABLE_M64_SPLIT); |
| 226 | if (rc != OPAL_SUCCESS) { |
| 227 | desc = "enabling"; |
| 228 | goto fail; |
| 229 | } |
| 230 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 231 | /* |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 232 | * Exclude the segments for reserved and root bus PE, which |
| 233 | * are first or last two PEs. |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 234 | */ |
| 235 | r = &phb->hose->mem_resources[1]; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 236 | if (phb->ioda.reserved_pe_idx == 0) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 237 | r->start += (2 * phb->ioda.m64_segsize); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 238 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 239 | r->end -= (2 * phb->ioda.m64_segsize); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 240 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 241 | pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 242 | phb->ioda.reserved_pe_idx); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 243 | |
| 244 | return 0; |
| 245 | |
| 246 | fail: |
| 247 | pr_warn(" Failure %lld %s M64 BAR#%d\n", |
| 248 | rc, desc, phb->ioda.m64_bar_idx); |
| 249 | opal_pci_phb_mmio_enable(phb->opal_id, |
| 250 | OPAL_M64_WINDOW_TYPE, |
| 251 | phb->ioda.m64_bar_idx, |
| 252 | OPAL_DISABLE_M64); |
| 253 | return -EIO; |
| 254 | } |
| 255 | |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 256 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 257 | unsigned long *pe_bitmap) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 258 | { |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 259 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 260 | struct pnv_phb *phb = hose->private_data; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 261 | struct resource *r; |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 262 | resource_size_t base, sgsz, start, end; |
| 263 | int segno, i; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 264 | |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 265 | base = phb->ioda.m64_base; |
| 266 | sgsz = phb->ioda.m64_segsize; |
| 267 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 268 | r = &pdev->resource[i]; |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 269 | if (!r->parent || !pnv_pci_is_m64(phb, r)) |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 270 | continue; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 271 | |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 272 | start = _ALIGN_DOWN(r->start - base, sgsz); |
| 273 | end = _ALIGN_UP(r->end - base, sgsz); |
| 274 | for (segno = start / sgsz; segno < end / sgsz; segno++) { |
| 275 | if (pe_bitmap) |
| 276 | set_bit(segno, pe_bitmap); |
| 277 | else |
| 278 | pnv_ioda_reserve_pe(phb, segno); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 279 | } |
| 280 | } |
| 281 | } |
| 282 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 283 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
| 284 | { |
| 285 | struct resource *r; |
| 286 | int index; |
| 287 | |
| 288 | /* |
| 289 | * There are 16 M64 BARs, each of which has 8 segments. So |
| 290 | * there are as many M64 segments as the maximum number of |
| 291 | * PEs, which is 128. |
| 292 | */ |
| 293 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { |
| 294 | unsigned long base, segsz = phb->ioda.m64_segsize; |
| 295 | int64_t rc; |
| 296 | |
| 297 | base = phb->ioda.m64_base + |
| 298 | index * PNV_IODA1_M64_SEGS * segsz; |
| 299 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
| 300 | OPAL_M64_WINDOW_TYPE, index, base, 0, |
| 301 | PNV_IODA1_M64_SEGS * segsz); |
| 302 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 303 | pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 304 | rc, phb->hose->global_number, index); |
| 305 | goto fail; |
| 306 | } |
| 307 | |
| 308 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
| 309 | OPAL_M64_WINDOW_TYPE, index, |
| 310 | OPAL_ENABLE_M64_SPLIT); |
| 311 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 312 | pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 313 | rc, phb->hose->global_number, index); |
| 314 | goto fail; |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | /* |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 319 | * Exclude the segments for reserved and root bus PE, which |
| 320 | * are first or last two PEs. |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 321 | */ |
| 322 | r = &phb->hose->mem_resources[1]; |
| 323 | if (phb->ioda.reserved_pe_idx == 0) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 324 | r->start += (2 * phb->ioda.m64_segsize); |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 325 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 326 | r->end -= (2 * phb->ioda.m64_segsize); |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 327 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 328 | WARN(1, "Wrong reserved PE#%x on PHB#%x\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 329 | phb->ioda.reserved_pe_idx, phb->hose->global_number); |
| 330 | |
| 331 | return 0; |
| 332 | |
| 333 | fail: |
| 334 | for ( ; index >= 0; index--) |
| 335 | opal_pci_phb_mmio_enable(phb->opal_id, |
| 336 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); |
| 337 | |
| 338 | return -EIO; |
| 339 | } |
| 340 | |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 341 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
| 342 | unsigned long *pe_bitmap, |
| 343 | bool all) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 344 | { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 345 | struct pci_dev *pdev; |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 346 | |
| 347 | list_for_each_entry(pdev, &bus->devices, bus_list) { |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 348 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 349 | |
| 350 | if (all && pdev->subordinate) |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 351 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
| 352 | pe_bitmap, all); |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 353 | } |
| 354 | } |
| 355 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 356 | static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 357 | { |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 358 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 359 | struct pnv_phb *phb = hose->private_data; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 360 | struct pnv_ioda_pe *master_pe, *pe; |
| 361 | unsigned long size, *pe_alloc; |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 362 | int i; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 363 | |
| 364 | /* Root bus shouldn't use M64 */ |
| 365 | if (pci_is_root_bus(bus)) |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 366 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 367 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 368 | /* Allocate bitmap */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 369 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 370 | pe_alloc = kzalloc(size, GFP_KERNEL); |
| 371 | if (!pe_alloc) { |
| 372 | pr_warn("%s: Out of memory !\n", |
| 373 | __func__); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 374 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 375 | } |
| 376 | |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 377 | /* Figure out reserved PE numbers by the PE */ |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 378 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 379 | |
| 380 | /* |
| 381 | * the current bus might not own M64 window and that's all |
| 382 | * contributed by its child buses. For the case, we needn't |
| 383 | * pick M64 dependent PE#. |
| 384 | */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 385 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 386 | kfree(pe_alloc); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 387 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* |
| 391 | * Figure out the master PE and put all slave PEs to master |
| 392 | * PE's list to form compound PE. |
| 393 | */ |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 394 | master_pe = NULL; |
| 395 | i = -1; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 396 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
| 397 | phb->ioda.total_pe_num) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 398 | pe = &phb->ioda.pe_array[i]; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 399 | |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 400 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 401 | if (!master_pe) { |
| 402 | pe->flags |= PNV_IODA_PE_MASTER; |
| 403 | INIT_LIST_HEAD(&pe->slaves); |
| 404 | master_pe = pe; |
| 405 | } else { |
| 406 | pe->flags |= PNV_IODA_PE_SLAVE; |
| 407 | pe->master = master_pe; |
| 408 | list_add_tail(&pe->list, &master_pe->slaves); |
| 409 | } |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 410 | |
| 411 | /* |
| 412 | * P7IOC supports M64DT, which helps mapping M64 segment |
| 413 | * to one particular PE#. However, PHB3 has fixed mapping |
| 414 | * between M64 segment and PE#. In order to have same logic |
| 415 | * for P7IOC and PHB3, we enforce fixed mapping between M64 |
| 416 | * segment and PE# on P7IOC. |
| 417 | */ |
| 418 | if (phb->type == PNV_PHB_IODA1) { |
| 419 | int64_t rc; |
| 420 | |
| 421 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 422 | pe->pe_number, OPAL_M64_WINDOW_TYPE, |
| 423 | pe->pe_number / PNV_IODA1_M64_SEGS, |
| 424 | pe->pe_number % PNV_IODA1_M64_SEGS); |
| 425 | if (rc != OPAL_SUCCESS) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 426 | pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 427 | __func__, rc, phb->hose->global_number, |
| 428 | pe->pe_number); |
| 429 | } |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | kfree(pe_alloc); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 433 | return master_pe; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 434 | } |
| 435 | |
| 436 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) |
| 437 | { |
| 438 | struct pci_controller *hose = phb->hose; |
| 439 | struct device_node *dn = hose->dn; |
| 440 | struct resource *res; |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 441 | u32 m64_range[2], i; |
Gavin Shan | 0e7736c | 2016-08-02 14:10:35 +1000 | [diff] [blame] | 442 | const __be32 *r; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 443 | u64 pci_addr; |
| 444 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 445 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
Gavin Shan | 1665c4a | 2014-11-12 13:36:04 +1100 | [diff] [blame] | 446 | pr_info(" Not support M64 window\n"); |
| 447 | return; |
| 448 | } |
| 449 | |
Stewart Smith | e4d54f7 | 2015-12-09 17:18:20 +1100 | [diff] [blame] | 450 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 451 | pr_info(" Firmware too old to support M64 window\n"); |
| 452 | return; |
| 453 | } |
| 454 | |
| 455 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); |
| 456 | if (!r) { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 457 | pr_info(" No <ibm,opal-m64-window> on %pOF\n", |
| 458 | dn); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 459 | return; |
| 460 | } |
| 461 | |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 462 | /* |
| 463 | * Find the available M64 BAR range and pickup the last one for |
| 464 | * covering the whole 64-bits space. We support only one range. |
| 465 | */ |
| 466 | if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", |
| 467 | m64_range, 2)) { |
| 468 | /* In absence of the property, assume 0..15 */ |
| 469 | m64_range[0] = 0; |
| 470 | m64_range[1] = 16; |
| 471 | } |
| 472 | /* We only support 64 bits in our allocator */ |
| 473 | if (m64_range[1] > 63) { |
| 474 | pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", |
| 475 | __func__, m64_range[1], phb->hose->global_number); |
| 476 | m64_range[1] = 63; |
| 477 | } |
| 478 | /* Empty range, no m64 */ |
| 479 | if (m64_range[1] <= m64_range[0]) { |
| 480 | pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", |
| 481 | __func__, phb->hose->global_number); |
| 482 | return; |
| 483 | } |
| 484 | |
| 485 | /* Configure M64 informations */ |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 486 | res = &hose->mem_resources[1]; |
Gavin Shan | e80c4e7 | 2015-10-22 12:03:08 +1100 | [diff] [blame] | 487 | res->name = dn->full_name; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 488 | res->start = of_translate_address(dn, r + 2); |
| 489 | res->end = res->start + of_read_number(r + 4, 2) - 1; |
| 490 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); |
| 491 | pci_addr = of_read_number(r, 2); |
| 492 | hose->mem_offset[1] = res->start - pci_addr; |
| 493 | |
| 494 | phb->ioda.m64_size = resource_size(res); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 495 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 496 | phb->ioda.m64_base = pci_addr; |
| 497 | |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 498 | /* This lines up nicely with the display from processing OF ranges */ |
| 499 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", |
| 500 | res->start, res->end, pci_addr, m64_range[0], |
| 501 | m64_range[0] + m64_range[1] - 1); |
| 502 | |
| 503 | /* Mark all M64 used up by default */ |
| 504 | phb->ioda.m64_bar_alloc = (unsigned long)-1; |
Wei Yang | e9863e6 | 2014-12-12 12:39:37 +0800 | [diff] [blame] | 505 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 506 | /* Use last M64 BAR to cover M64 window */ |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 507 | m64_range[1]--; |
| 508 | phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; |
| 509 | |
| 510 | pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); |
| 511 | |
| 512 | /* Mark remaining ones free */ |
| 513 | for (i = m64_range[0]; i < m64_range[1]; i++) |
| 514 | clear_bit(i, &phb->ioda.m64_bar_alloc); |
| 515 | |
| 516 | /* |
| 517 | * Setup init functions for M64 based on IODA version, IODA3 uses |
| 518 | * the IODA2 code. |
| 519 | */ |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 520 | if (phb->type == PNV_PHB_IODA1) |
| 521 | phb->init_m64 = pnv_ioda1_init_m64; |
| 522 | else |
| 523 | phb->init_m64 = pnv_ioda2_init_m64; |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 524 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
| 525 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 526 | } |
| 527 | |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 528 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
| 529 | { |
| 530 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; |
| 531 | struct pnv_ioda_pe *slave; |
| 532 | s64 rc; |
| 533 | |
| 534 | /* Fetch master PE */ |
| 535 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 536 | pe = pe->master; |
Gavin Shan | ec8e4e9 | 2014-11-12 13:36:10 +1100 | [diff] [blame] | 537 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
| 538 | return; |
| 539 | |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 540 | pe_no = pe->pe_number; |
| 541 | } |
| 542 | |
| 543 | /* Freeze master PE */ |
| 544 | rc = opal_pci_eeh_freeze_set(phb->opal_id, |
| 545 | pe_no, |
| 546 | OPAL_EEH_ACTION_SET_FREEZE_ALL); |
| 547 | if (rc != OPAL_SUCCESS) { |
| 548 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", |
| 549 | __func__, rc, phb->hose->global_number, pe_no); |
| 550 | return; |
| 551 | } |
| 552 | |
| 553 | /* Freeze slave PEs */ |
| 554 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 555 | return; |
| 556 | |
| 557 | list_for_each_entry(slave, &pe->slaves, list) { |
| 558 | rc = opal_pci_eeh_freeze_set(phb->opal_id, |
| 559 | slave->pe_number, |
| 560 | OPAL_EEH_ACTION_SET_FREEZE_ALL); |
| 561 | if (rc != OPAL_SUCCESS) |
| 562 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", |
| 563 | __func__, rc, phb->hose->global_number, |
| 564 | slave->pe_number); |
| 565 | } |
| 566 | } |
| 567 | |
Anton Blanchard | e51df2c | 2014-08-20 08:55:18 +1000 | [diff] [blame] | 568 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 569 | { |
| 570 | struct pnv_ioda_pe *pe, *slave; |
| 571 | s64 rc; |
| 572 | |
| 573 | /* Find master PE */ |
| 574 | pe = &phb->ioda.pe_array[pe_no]; |
| 575 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 576 | pe = pe->master; |
| 577 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); |
| 578 | pe_no = pe->pe_number; |
| 579 | } |
| 580 | |
| 581 | /* Clear frozen state for master PE */ |
| 582 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); |
| 583 | if (rc != OPAL_SUCCESS) { |
| 584 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", |
| 585 | __func__, rc, opt, phb->hose->global_number, pe_no); |
| 586 | return -EIO; |
| 587 | } |
| 588 | |
| 589 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 590 | return 0; |
| 591 | |
| 592 | /* Clear frozen state for slave PEs */ |
| 593 | list_for_each_entry(slave, &pe->slaves, list) { |
| 594 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, |
| 595 | slave->pe_number, |
| 596 | opt); |
| 597 | if (rc != OPAL_SUCCESS) { |
| 598 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", |
| 599 | __func__, rc, opt, phb->hose->global_number, |
| 600 | slave->pe_number); |
| 601 | return -EIO; |
| 602 | } |
| 603 | } |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) |
| 609 | { |
| 610 | struct pnv_ioda_pe *slave, *pe; |
| 611 | u8 fstate, state; |
| 612 | __be16 pcierr; |
| 613 | s64 rc; |
| 614 | |
| 615 | /* Sanity check on PE number */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 616 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 617 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
| 618 | |
| 619 | /* |
| 620 | * Fetch the master PE and the PE instance might be |
| 621 | * not initialized yet. |
| 622 | */ |
| 623 | pe = &phb->ioda.pe_array[pe_no]; |
| 624 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 625 | pe = pe->master; |
| 626 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); |
| 627 | pe_no = pe->pe_number; |
| 628 | } |
| 629 | |
| 630 | /* Check the master PE */ |
| 631 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 632 | &state, &pcierr, NULL); |
| 633 | if (rc != OPAL_SUCCESS) { |
| 634 | pr_warn("%s: Failure %lld getting " |
| 635 | "PHB#%x-PE#%x state\n", |
| 636 | __func__, rc, |
| 637 | phb->hose->global_number, pe_no); |
| 638 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; |
| 639 | } |
| 640 | |
| 641 | /* Check the slave PE */ |
| 642 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 643 | return state; |
| 644 | |
| 645 | list_for_each_entry(slave, &pe->slaves, list) { |
| 646 | rc = opal_pci_eeh_freeze_status(phb->opal_id, |
| 647 | slave->pe_number, |
| 648 | &fstate, |
| 649 | &pcierr, |
| 650 | NULL); |
| 651 | if (rc != OPAL_SUCCESS) { |
| 652 | pr_warn("%s: Failure %lld getting " |
| 653 | "PHB#%x-PE#%x state\n", |
| 654 | __func__, rc, |
| 655 | phb->hose->global_number, slave->pe_number); |
| 656 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; |
| 657 | } |
| 658 | |
| 659 | /* |
| 660 | * Override the result based on the ascending |
| 661 | * priority. |
| 662 | */ |
| 663 | if (fstate > state) |
| 664 | state = fstate; |
| 665 | } |
| 666 | |
| 667 | return state; |
| 668 | } |
| 669 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 670 | /* Currently those 2 are only used when MSIs are enabled, this will change |
| 671 | * but in the meantime, we need to protect them to avoid warnings |
| 672 | */ |
| 673 | #ifdef CONFIG_PCI_MSI |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 674 | struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 675 | { |
| 676 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 677 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 678 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 679 | |
| 680 | if (!pdn) |
| 681 | return NULL; |
| 682 | if (pdn->pe_number == IODA_INVALID_PE) |
| 683 | return NULL; |
| 684 | return &phb->ioda.pe_array[pdn->pe_number]; |
| 685 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 686 | #endif /* CONFIG_PCI_MSI */ |
| 687 | |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 688 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
| 689 | struct pnv_ioda_pe *parent, |
| 690 | struct pnv_ioda_pe *child, |
| 691 | bool is_add) |
| 692 | { |
| 693 | const char *desc = is_add ? "adding" : "removing"; |
| 694 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : |
| 695 | OPAL_REMOVE_PE_FROM_DOMAIN; |
| 696 | struct pnv_ioda_pe *slave; |
| 697 | long rc; |
| 698 | |
| 699 | /* Parent PE affects child PE */ |
| 700 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, |
| 701 | child->pe_number, op); |
| 702 | if (rc != OPAL_SUCCESS) { |
| 703 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", |
| 704 | rc, desc); |
| 705 | return -ENXIO; |
| 706 | } |
| 707 | |
| 708 | if (!(child->flags & PNV_IODA_PE_MASTER)) |
| 709 | return 0; |
| 710 | |
| 711 | /* Compound case: parent PE affects slave PEs */ |
| 712 | list_for_each_entry(slave, &child->slaves, list) { |
| 713 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, |
| 714 | slave->pe_number, op); |
| 715 | if (rc != OPAL_SUCCESS) { |
| 716 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", |
| 717 | rc, desc); |
| 718 | return -ENXIO; |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, |
| 726 | struct pnv_ioda_pe *pe, |
| 727 | bool is_add) |
| 728 | { |
| 729 | struct pnv_ioda_pe *slave; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 730 | struct pci_dev *pdev = NULL; |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 731 | int ret; |
| 732 | |
| 733 | /* |
| 734 | * Clear PE frozen state. If it's master PE, we need |
| 735 | * clear slave PE frozen state as well. |
| 736 | */ |
| 737 | if (is_add) { |
| 738 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
| 739 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 740 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 741 | list_for_each_entry(slave, &pe->slaves, list) |
| 742 | opal_pci_eeh_freeze_clear(phb->opal_id, |
| 743 | slave->pe_number, |
| 744 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | /* |
| 749 | * Associate PE in PELT. We need add the PE into the |
| 750 | * corresponding PELT-V as well. Otherwise, the error |
| 751 | * originated from the PE might contribute to other |
| 752 | * PEs. |
| 753 | */ |
| 754 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); |
| 755 | if (ret) |
| 756 | return ret; |
| 757 | |
| 758 | /* For compound PEs, any one affects all of them */ |
| 759 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 760 | list_for_each_entry(slave, &pe->slaves, list) { |
| 761 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); |
| 762 | if (ret) |
| 763 | return ret; |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) |
| 768 | pdev = pe->pbus->self; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 769 | else if (pe->flags & PNV_IODA_PE_DEV) |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 770 | pdev = pe->pdev->bus->self; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 771 | #ifdef CONFIG_PCI_IOV |
| 772 | else if (pe->flags & PNV_IODA_PE_VF) |
Gavin Shan | 283e2d8 | 2015-06-22 13:45:47 +1000 | [diff] [blame] | 773 | pdev = pe->parent_dev; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 774 | #endif /* CONFIG_PCI_IOV */ |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 775 | while (pdev) { |
| 776 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 777 | struct pnv_ioda_pe *parent; |
| 778 | |
| 779 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
| 780 | parent = &phb->ioda.pe_array[pdn->pe_number]; |
| 781 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); |
| 782 | if (ret) |
| 783 | return ret; |
| 784 | } |
| 785 | |
| 786 | pdev = pdev->bus->self; |
| 787 | } |
| 788 | |
| 789 | return 0; |
| 790 | } |
| 791 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 792 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
| 793 | { |
| 794 | struct pci_dev *parent; |
| 795 | uint8_t bcomp, dcomp, fcomp; |
| 796 | int64_t rc; |
| 797 | long rid_end, rid; |
| 798 | |
| 799 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ |
| 800 | if (pe->pbus) { |
| 801 | int count; |
| 802 | |
| 803 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; |
| 804 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; |
| 805 | parent = pe->pbus->self; |
| 806 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
| 807 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; |
| 808 | else |
| 809 | count = 1; |
| 810 | |
| 811 | switch(count) { |
| 812 | case 1: bcomp = OpalPciBusAll; break; |
| 813 | case 2: bcomp = OpalPciBus7Bits; break; |
| 814 | case 4: bcomp = OpalPciBus6Bits; break; |
| 815 | case 8: bcomp = OpalPciBus5Bits; break; |
| 816 | case 16: bcomp = OpalPciBus4Bits; break; |
| 817 | case 32: bcomp = OpalPciBus3Bits; break; |
| 818 | default: |
| 819 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
| 820 | count); |
| 821 | /* Do an exact match only */ |
| 822 | bcomp = OpalPciBusAll; |
| 823 | } |
| 824 | rid_end = pe->rid + (count << 8); |
| 825 | } else { |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 826 | #ifdef CONFIG_PCI_IOV |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 827 | if (pe->flags & PNV_IODA_PE_VF) |
| 828 | parent = pe->parent_dev; |
| 829 | else |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 830 | #endif |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 831 | parent = pe->pdev->bus->self; |
| 832 | bcomp = OpalPciBusAll; |
| 833 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; |
| 834 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; |
| 835 | rid_end = pe->rid + 1; |
| 836 | } |
| 837 | |
| 838 | /* Clear the reverse map */ |
| 839 | for (rid = pe->rid; rid < rid_end; rid++) |
Gavin Shan | c127562 | 2016-05-20 16:41:29 +1000 | [diff] [blame] | 840 | phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 841 | |
| 842 | /* Release from all parents PELT-V */ |
| 843 | while (parent) { |
| 844 | struct pci_dn *pdn = pci_get_pdn(parent); |
| 845 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
| 846 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, |
| 847 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); |
| 848 | /* XXX What to do in case of error ? */ |
| 849 | } |
| 850 | parent = parent->bus->self; |
| 851 | } |
| 852 | |
Gavin Shan | f951e51 | 2015-06-23 17:01:13 +1000 | [diff] [blame] | 853 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 854 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 855 | |
| 856 | /* Disassociate PE in PELT */ |
| 857 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, |
| 858 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); |
| 859 | if (rc) |
| 860 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); |
| 861 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
| 862 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); |
| 863 | if (rc) |
| 864 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); |
| 865 | |
| 866 | pe->pbus = NULL; |
| 867 | pe->pdev = NULL; |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 868 | #ifdef CONFIG_PCI_IOV |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 869 | pe->parent_dev = NULL; |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 870 | #endif |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 871 | |
| 872 | return 0; |
| 873 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 874 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 875 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 876 | { |
| 877 | struct pci_dev *parent; |
| 878 | uint8_t bcomp, dcomp, fcomp; |
| 879 | long rc, rid_end, rid; |
| 880 | |
| 881 | /* Bus validation ? */ |
| 882 | if (pe->pbus) { |
| 883 | int count; |
| 884 | |
| 885 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; |
| 886 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; |
| 887 | parent = pe->pbus->self; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 888 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
| 889 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; |
| 890 | else |
| 891 | count = 1; |
| 892 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 893 | switch(count) { |
| 894 | case 1: bcomp = OpalPciBusAll; break; |
| 895 | case 2: bcomp = OpalPciBus7Bits; break; |
| 896 | case 4: bcomp = OpalPciBus6Bits; break; |
| 897 | case 8: bcomp = OpalPciBus5Bits; break; |
| 898 | case 16: bcomp = OpalPciBus4Bits; break; |
| 899 | case 32: bcomp = OpalPciBus3Bits; break; |
| 900 | default: |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 901 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
| 902 | count); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 903 | /* Do an exact match only */ |
| 904 | bcomp = OpalPciBusAll; |
| 905 | } |
| 906 | rid_end = pe->rid + (count << 8); |
| 907 | } else { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 908 | #ifdef CONFIG_PCI_IOV |
| 909 | if (pe->flags & PNV_IODA_PE_VF) |
| 910 | parent = pe->parent_dev; |
| 911 | else |
| 912 | #endif /* CONFIG_PCI_IOV */ |
| 913 | parent = pe->pdev->bus->self; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 914 | bcomp = OpalPciBusAll; |
| 915 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; |
| 916 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; |
| 917 | rid_end = pe->rid + 1; |
| 918 | } |
| 919 | |
Gavin Shan | 631ad69 | 2013-11-04 16:32:46 +0800 | [diff] [blame] | 920 | /* |
| 921 | * Associate PE in PELT. We need add the PE into the |
| 922 | * corresponding PELT-V as well. Otherwise, the error |
| 923 | * originated from the PE might contribute to other |
| 924 | * PEs. |
| 925 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 926 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
| 927 | bcomp, dcomp, fcomp, OPAL_MAP_PE); |
| 928 | if (rc) { |
| 929 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); |
| 930 | return -ENXIO; |
| 931 | } |
Gavin Shan | 631ad69 | 2013-11-04 16:32:46 +0800 | [diff] [blame] | 932 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 933 | /* |
| 934 | * Configure PELTV. NPUs don't have a PELTV table so skip |
| 935 | * configuration on them. |
| 936 | */ |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 937 | if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI) |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 938 | pnv_ioda_set_peltv(phb, pe, true); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 939 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 940 | /* Setup reverse map */ |
| 941 | for (rid = pe->rid; rid < rid_end; rid++) |
| 942 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
| 943 | |
| 944 | /* Setup one MVTs on IODA1 */ |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 945 | if (phb->type != PNV_PHB_IODA1) { |
| 946 | pe->mve_number = 0; |
| 947 | goto out; |
| 948 | } |
| 949 | |
| 950 | pe->mve_number = pe->pe_number; |
| 951 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); |
| 952 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 953 | pe_err(pe, "OPAL error %ld setting up MVE %x\n", |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 954 | rc, pe->mve_number); |
| 955 | pe->mve_number = -1; |
| 956 | } else { |
| 957 | rc = opal_pci_set_mve_enable(phb->opal_id, |
| 958 | pe->mve_number, OPAL_ENABLE_MVE); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 959 | if (rc) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 960 | pe_err(pe, "OPAL error %ld enabling MVE %x\n", |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 961 | rc, pe->mve_number); |
| 962 | pe->mve_number = -1; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 963 | } |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 964 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 965 | |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 966 | out: |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 967 | return 0; |
| 968 | } |
| 969 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 970 | #ifdef CONFIG_PCI_IOV |
| 971 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) |
| 972 | { |
| 973 | struct pci_dn *pdn = pci_get_pdn(dev); |
| 974 | int i; |
| 975 | struct resource *res, res2; |
| 976 | resource_size_t size; |
| 977 | u16 num_vfs; |
| 978 | |
| 979 | if (!dev->is_physfn) |
| 980 | return -EINVAL; |
| 981 | |
| 982 | /* |
| 983 | * "offset" is in VFs. The M64 windows are sized so that when they |
| 984 | * are segmented, each segment is the same size as the IOV BAR. |
| 985 | * Each segment is in a separate PE, and the high order bits of the |
| 986 | * address are the PE number. Therefore, each VF's BAR is in a |
| 987 | * separate PE, and changing the IOV BAR start address changes the |
| 988 | * range of PEs the VFs are in. |
| 989 | */ |
| 990 | num_vfs = pdn->num_vfs; |
| 991 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 992 | res = &dev->resource[i + PCI_IOV_RESOURCES]; |
| 993 | if (!res->flags || !res->parent) |
| 994 | continue; |
| 995 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 996 | /* |
| 997 | * The actual IOV BAR range is determined by the start address |
| 998 | * and the actual size for num_vfs VFs BAR. This check is to |
| 999 | * make sure that after shifting, the range will not overlap |
| 1000 | * with another device. |
| 1001 | */ |
| 1002 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
| 1003 | res2.flags = res->flags; |
| 1004 | res2.start = res->start + (size * offset); |
| 1005 | res2.end = res2.start + (size * num_vfs) - 1; |
| 1006 | |
| 1007 | if (res2.end > res->end) { |
| 1008 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", |
| 1009 | i, &res2, res, num_vfs, offset); |
| 1010 | return -EBUSY; |
| 1011 | } |
| 1012 | } |
| 1013 | |
| 1014 | /* |
Alexey Kardashevskiy | d6f934f | 2017-09-27 16:52:31 +1000 | [diff] [blame] | 1015 | * Since M64 BAR shares segments among all possible 256 PEs, |
| 1016 | * we have to shift the beginning of PF IOV BAR to make it start from |
| 1017 | * the segment which belongs to the PE number assigned to the first VF. |
| 1018 | * This creates a "hole" in the /proc/iomem which could be used for |
| 1019 | * allocating other resources so we reserve this area below and |
| 1020 | * release when IOV is released. |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1021 | */ |
| 1022 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 1023 | res = &dev->resource[i + PCI_IOV_RESOURCES]; |
| 1024 | if (!res->flags || !res->parent) |
| 1025 | continue; |
| 1026 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1027 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
| 1028 | res2 = *res; |
| 1029 | res->start += size * offset; |
| 1030 | |
Wei Yang | 74703cc | 2015-07-20 18:14:58 +0800 | [diff] [blame] | 1031 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
| 1032 | i, &res2, res, (offset > 0) ? "En" : "Dis", |
| 1033 | num_vfs, offset); |
Alexey Kardashevskiy | d6f934f | 2017-09-27 16:52:31 +1000 | [diff] [blame] | 1034 | |
| 1035 | if (offset < 0) { |
| 1036 | devm_release_resource(&dev->dev, &pdn->holes[i]); |
| 1037 | memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); |
| 1038 | } |
| 1039 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1040 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
Alexey Kardashevskiy | d6f934f | 2017-09-27 16:52:31 +1000 | [diff] [blame] | 1041 | |
| 1042 | if (offset > 0) { |
| 1043 | pdn->holes[i].start = res2.start; |
| 1044 | pdn->holes[i].end = res2.start + size * offset - 1; |
| 1045 | pdn->holes[i].flags = IORESOURCE_BUS; |
| 1046 | pdn->holes[i].name = "pnv_iov_reserved"; |
| 1047 | devm_request_resource(&dev->dev, res->parent, |
| 1048 | &pdn->holes[i]); |
| 1049 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1050 | } |
| 1051 | return 0; |
| 1052 | } |
| 1053 | #endif /* CONFIG_PCI_IOV */ |
| 1054 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 1055 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1056 | { |
| 1057 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 1058 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1059 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1060 | struct pnv_ioda_pe *pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1061 | |
| 1062 | if (!pdn) { |
| 1063 | pr_err("%s: Device tree node not associated properly\n", |
| 1064 | pci_name(dev)); |
| 1065 | return NULL; |
| 1066 | } |
| 1067 | if (pdn->pe_number != IODA_INVALID_PE) |
| 1068 | return NULL; |
| 1069 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1070 | pe = pnv_ioda_alloc_pe(phb); |
| 1071 | if (!pe) { |
Joe Perches | f2c2cbc | 2016-10-24 21:00:08 -0700 | [diff] [blame] | 1072 | pr_warn("%s: Not enough PE# available, disabling device\n", |
| 1073 | pci_name(dev)); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1074 | return NULL; |
| 1075 | } |
| 1076 | |
| 1077 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the |
| 1078 | * pointer in the PE data structure, both should be destroyed at the |
| 1079 | * same time. However, this needs to be looked at more closely again |
| 1080 | * once we actually start removing things (Hotplug, SR-IOV, ...) |
| 1081 | * |
| 1082 | * At some point we want to remove the PDN completely anyways |
| 1083 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1084 | pci_dev_get(dev); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1085 | pdn->pe_number = pe->pe_number; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1086 | pe->flags = PNV_IODA_PE_DEV; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1087 | pe->pdev = dev; |
| 1088 | pe->pbus = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1089 | pe->mve_number = -1; |
| 1090 | pe->rid = dev->bus->number << 8 | pdn->devfn; |
| 1091 | |
| 1092 | pe_info(pe, "Associated device to PE\n"); |
| 1093 | |
| 1094 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1095 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1096 | pnv_ioda_free_pe(pe); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1097 | pdn->pe_number = IODA_INVALID_PE; |
| 1098 | pe->pdev = NULL; |
| 1099 | pci_dev_put(dev); |
| 1100 | return NULL; |
| 1101 | } |
| 1102 | |
Alexey Kardashevskiy | 1d4e89c | 2016-05-12 15:47:10 +1000 | [diff] [blame] | 1103 | /* Put PE to the list */ |
| 1104 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
| 1105 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1106 | return pe; |
| 1107 | } |
| 1108 | |
| 1109 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) |
| 1110 | { |
| 1111 | struct pci_dev *dev; |
| 1112 | |
| 1113 | list_for_each_entry(dev, &bus->devices, bus_list) { |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1114 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1115 | |
| 1116 | if (pdn == NULL) { |
| 1117 | pr_warn("%s: No device node associated with device !\n", |
| 1118 | pci_name(dev)); |
| 1119 | continue; |
| 1120 | } |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1121 | |
| 1122 | /* |
| 1123 | * In partial hotplug case, the PCI device might be still |
| 1124 | * associated with the PE and needn't attach it to the PE |
| 1125 | * again. |
| 1126 | */ |
| 1127 | if (pdn->pe_number != IODA_INVALID_PE) |
| 1128 | continue; |
| 1129 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 1130 | pe->device_count++; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1131 | pdn->pe_number = pe->pe_number; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1132 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1133 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
| 1134 | } |
| 1135 | } |
| 1136 | |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1137 | /* |
| 1138 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of |
| 1139 | * single PCI bus. Another one that contains the primary PCI bus and its |
| 1140 | * subordinate PCI devices and buses. The second type of PE is normally |
| 1141 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. |
| 1142 | */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1143 | static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1144 | { |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1145 | struct pci_controller *hose = pci_bus_to_host(bus); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1146 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1147 | struct pnv_ioda_pe *pe = NULL; |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1148 | unsigned int pe_num; |
| 1149 | |
| 1150 | /* |
| 1151 | * In partial hotplug case, the PE instance might be still alive. |
| 1152 | * We should reuse it instead of allocating a new one. |
| 1153 | */ |
| 1154 | pe_num = phb->ioda.pe_rmap[bus->number << 8]; |
| 1155 | if (pe_num != IODA_INVALID_PE) { |
| 1156 | pe = &phb->ioda.pe_array[pe_num]; |
| 1157 | pnv_ioda_setup_same_PE(bus, pe); |
| 1158 | return NULL; |
| 1159 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1160 | |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 1161 | /* PE number for root bus should have been reserved */ |
| 1162 | if (pci_is_root_bus(bus) && |
| 1163 | phb->ioda.root_pe_idx != IODA_INVALID_PE) |
| 1164 | pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; |
| 1165 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1166 | /* Check if PE is determined by M64 */ |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 1167 | if (!pe && phb->pick_m64_pe) |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1168 | pe = phb->pick_m64_pe(bus, all); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1169 | |
| 1170 | /* The PE number isn't pinned by M64 */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1171 | if (!pe) |
| 1172 | pe = pnv_ioda_alloc_pe(phb); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1173 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1174 | if (!pe) { |
Joe Perches | f2c2cbc | 2016-10-24 21:00:08 -0700 | [diff] [blame] | 1175 | pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1176 | __func__, pci_domain_nr(bus), bus->number); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1177 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1178 | } |
| 1179 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1180 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1181 | pe->pbus = bus; |
| 1182 | pe->pdev = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1183 | pe->mve_number = -1; |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1184 | pe->rid = bus->busn_res.start << 8; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1185 | |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1186 | if (all) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1187 | pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1188 | bus->busn_res.start, bus->busn_res.end, pe->pe_number); |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1189 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1190 | pe_info(pe, "Secondary bus %d associated with PE#%x\n", |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1191 | bus->busn_res.start, pe->pe_number); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1192 | |
| 1193 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1194 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1195 | pnv_ioda_free_pe(pe); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1196 | pe->pbus = NULL; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1197 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1198 | } |
| 1199 | |
| 1200 | /* Associate it with all child devices */ |
| 1201 | pnv_ioda_setup_same_PE(bus, pe); |
| 1202 | |
Gavin Shan | 7ebdf95 | 2012-08-20 03:49:15 +0000 | [diff] [blame] | 1203 | /* Put PE to the list */ |
| 1204 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1205 | |
| 1206 | return pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1207 | } |
| 1208 | |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1209 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1210 | { |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1211 | int pe_num, found_pe = false, rc; |
| 1212 | long rid; |
| 1213 | struct pnv_ioda_pe *pe; |
| 1214 | struct pci_dev *gpu_pdev; |
| 1215 | struct pci_dn *npu_pdn; |
| 1216 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); |
| 1217 | struct pnv_phb *phb = hose->private_data; |
| 1218 | |
| 1219 | /* |
| 1220 | * Due to a hardware errata PE#0 on the NPU is reserved for |
| 1221 | * error handling. This means we only have three PEs remaining |
| 1222 | * which need to be assigned to four links, implying some |
| 1223 | * links must share PEs. |
| 1224 | * |
| 1225 | * To achieve this we assign PEs such that NPUs linking the |
| 1226 | * same GPU get assigned the same PE. |
| 1227 | */ |
| 1228 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1229 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1230 | pe = &phb->ioda.pe_array[pe_num]; |
| 1231 | if (!pe->pdev) |
| 1232 | continue; |
| 1233 | |
| 1234 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { |
| 1235 | /* |
| 1236 | * This device has the same peer GPU so should |
| 1237 | * be assigned the same PE as the existing |
| 1238 | * peer NPU. |
| 1239 | */ |
| 1240 | dev_info(&npu_pdev->dev, |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1241 | "Associating to existing PE %x\n", pe_num); |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1242 | pci_dev_get(npu_pdev); |
| 1243 | npu_pdn = pci_get_pdn(npu_pdev); |
| 1244 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1245 | npu_pdn->pe_number = pe_num; |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1246 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
| 1247 | |
| 1248 | /* Map the PE to this link */ |
| 1249 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, |
| 1250 | OpalPciBusAll, |
| 1251 | OPAL_COMPARE_RID_DEVICE_NUMBER, |
| 1252 | OPAL_COMPARE_RID_FUNCTION_NUMBER, |
| 1253 | OPAL_MAP_PE); |
| 1254 | WARN_ON(rc != OPAL_SUCCESS); |
| 1255 | found_pe = true; |
| 1256 | break; |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | if (!found_pe) |
| 1261 | /* |
| 1262 | * Could not find an existing PE so allocate a new |
| 1263 | * one. |
| 1264 | */ |
| 1265 | return pnv_ioda_setup_dev_PE(npu_pdev); |
| 1266 | else |
| 1267 | return pe; |
| 1268 | } |
| 1269 | |
| 1270 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) |
| 1271 | { |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1272 | struct pci_dev *pdev; |
| 1273 | |
| 1274 | list_for_each_entry(pdev, &bus->devices, bus_list) |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1275 | pnv_ioda_setup_npu_PE(pdev); |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1276 | } |
| 1277 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 1278 | static void pnv_pci_ioda_setup_PEs(void) |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1279 | { |
| 1280 | struct pci_controller *hose, *tmp; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1281 | struct pnv_phb *phb; |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 1282 | struct pci_bus *bus; |
| 1283 | struct pci_dev *pdev; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1284 | |
| 1285 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1286 | phb = hose->private_data; |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 1287 | if (phb->type == PNV_PHB_NPU_NVLINK) { |
Alistair Popple | 08f48f3 | 2016-01-11 16:53:50 +1100 | [diff] [blame] | 1288 | /* PE#0 is needed for error reporting */ |
| 1289 | pnv_ioda_reserve_pe(phb, 0); |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1290 | pnv_ioda_setup_npu_PEs(hose->bus); |
Alistair Popple | 1ab66d1 | 2017-04-03 19:51:44 +1000 | [diff] [blame] | 1291 | if (phb->model == PNV_PHB_MODEL_NPU2) |
| 1292 | pnv_npu2_init(phb); |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1293 | } |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 1294 | if (phb->type == PNV_PHB_NPU_OCAPI) { |
| 1295 | bus = hose->bus; |
| 1296 | list_for_each_entry(pdev, &bus->devices, bus_list) |
| 1297 | pnv_ioda_setup_dev_PE(pdev); |
| 1298 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1299 | } |
| 1300 | } |
| 1301 | |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1302 | #ifdef CONFIG_PCI_IOV |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1303 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1304 | { |
| 1305 | struct pci_bus *bus; |
| 1306 | struct pci_controller *hose; |
| 1307 | struct pnv_phb *phb; |
| 1308 | struct pci_dn *pdn; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1309 | int i, j; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1310 | int m64_bars; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1311 | |
| 1312 | bus = pdev->bus; |
| 1313 | hose = pci_bus_to_host(bus); |
| 1314 | phb = hose->private_data; |
| 1315 | pdn = pci_get_pdn(pdev); |
| 1316 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1317 | if (pdn->m64_single_mode) |
| 1318 | m64_bars = num_vfs; |
| 1319 | else |
| 1320 | m64_bars = 1; |
| 1321 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1322 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1323 | for (j = 0; j < m64_bars; j++) { |
| 1324 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1325 | continue; |
| 1326 | opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1327 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
| 1328 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); |
| 1329 | pdn->m64_map[j][i] = IODA_INVALID_M64; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1330 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1331 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1332 | kfree(pdn->m64_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1333 | return 0; |
| 1334 | } |
| 1335 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1336 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1337 | { |
| 1338 | struct pci_bus *bus; |
| 1339 | struct pci_controller *hose; |
| 1340 | struct pnv_phb *phb; |
| 1341 | struct pci_dn *pdn; |
| 1342 | unsigned int win; |
| 1343 | struct resource *res; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1344 | int i, j; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1345 | int64_t rc; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1346 | int total_vfs; |
| 1347 | resource_size_t size, start; |
| 1348 | int pe_num; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1349 | int m64_bars; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1350 | |
| 1351 | bus = pdev->bus; |
| 1352 | hose = pci_bus_to_host(bus); |
| 1353 | phb = hose->private_data; |
| 1354 | pdn = pci_get_pdn(pdev); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1355 | total_vfs = pci_sriov_get_totalvfs(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1356 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1357 | if (pdn->m64_single_mode) |
| 1358 | m64_bars = num_vfs; |
| 1359 | else |
| 1360 | m64_bars = 1; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1361 | |
Markus Elfring | fb37e12 | 2016-08-24 22:26:37 +0200 | [diff] [blame] | 1362 | pdn->m64_map = kmalloc_array(m64_bars, |
| 1363 | sizeof(*pdn->m64_map), |
| 1364 | GFP_KERNEL); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1365 | if (!pdn->m64_map) |
| 1366 | return -ENOMEM; |
| 1367 | /* Initialize the m64_map to IODA_INVALID_M64 */ |
| 1368 | for (i = 0; i < m64_bars ; i++) |
| 1369 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) |
| 1370 | pdn->m64_map[i][j] = IODA_INVALID_M64; |
| 1371 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1372 | |
| 1373 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 1374 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 1375 | if (!res->flags || !res->parent) |
| 1376 | continue; |
| 1377 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1378 | for (j = 0; j < m64_bars; j++) { |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1379 | do { |
| 1380 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, |
| 1381 | phb->ioda.m64_bar_idx + 1, 0); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1382 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1383 | if (win >= phb->ioda.m64_bar_idx + 1) |
| 1384 | goto m64_failed; |
| 1385 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1386 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1387 | pdn->m64_map[j][i] = win; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1388 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1389 | if (pdn->m64_single_mode) { |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1390 | size = pci_iov_resource_size(pdev, |
| 1391 | PCI_IOV_RESOURCES + i); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1392 | start = res->start + size * j; |
| 1393 | } else { |
| 1394 | size = resource_size(res); |
| 1395 | start = res->start; |
| 1396 | } |
| 1397 | |
| 1398 | /* Map the M64 here */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1399 | if (pdn->m64_single_mode) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1400 | pe_num = pdn->pe_num_map[j]; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1401 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 1402 | pe_num, OPAL_M64_WINDOW_TYPE, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1403 | pdn->m64_map[j][i], 0); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1404 | } |
| 1405 | |
| 1406 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1407 | OPAL_M64_WINDOW_TYPE, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1408 | pdn->m64_map[j][i], |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1409 | start, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1410 | 0, /* unused */ |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1411 | size); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1412 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1413 | |
| 1414 | if (rc != OPAL_SUCCESS) { |
| 1415 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", |
| 1416 | win, rc); |
| 1417 | goto m64_failed; |
| 1418 | } |
| 1419 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1420 | if (pdn->m64_single_mode) |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1421 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1422 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1423 | else |
| 1424 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1425 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1426 | |
| 1427 | if (rc != OPAL_SUCCESS) { |
| 1428 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", |
| 1429 | win, rc); |
| 1430 | goto m64_failed; |
| 1431 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1432 | } |
| 1433 | } |
| 1434 | return 0; |
| 1435 | |
| 1436 | m64_failed: |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1437 | pnv_pci_vf_release_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1438 | return -EBUSY; |
| 1439 | } |
| 1440 | |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1441 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
| 1442 | int num); |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1443 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1444 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
| 1445 | { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1446 | struct iommu_table *tbl; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1447 | int64_t rc; |
| 1448 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1449 | tbl = pe->table_group.tables[0]; |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1450 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1451 | if (rc) |
| 1452 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); |
| 1453 | |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1454 | pnv_pci_ioda2_set_bypass(pe, false); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 1455 | if (pe->table_group.group) { |
| 1456 | iommu_group_put(pe->table_group.group); |
| 1457 | BUG_ON(pe->table_group.group); |
Alexey Kardashevskiy | ac9a588 | 2015-06-05 16:34:56 +1000 | [diff] [blame] | 1458 | } |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 1459 | iommu_tce_table_put(tbl); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1460 | } |
| 1461 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1462 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1463 | { |
| 1464 | struct pci_bus *bus; |
| 1465 | struct pci_controller *hose; |
| 1466 | struct pnv_phb *phb; |
| 1467 | struct pnv_ioda_pe *pe, *pe_n; |
| 1468 | struct pci_dn *pdn; |
| 1469 | |
| 1470 | bus = pdev->bus; |
| 1471 | hose = pci_bus_to_host(bus); |
| 1472 | phb = hose->private_data; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1473 | pdn = pci_get_pdn(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1474 | |
| 1475 | if (!pdev->is_physfn) |
| 1476 | return; |
| 1477 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1478 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
| 1479 | if (pe->parent_dev != pdev) |
| 1480 | continue; |
| 1481 | |
| 1482 | pnv_pci_ioda2_release_dma_pe(pdev, pe); |
| 1483 | |
| 1484 | /* Remove from list */ |
| 1485 | mutex_lock(&phb->ioda.pe_list_mutex); |
| 1486 | list_del(&pe->list); |
| 1487 | mutex_unlock(&phb->ioda.pe_list_mutex); |
| 1488 | |
| 1489 | pnv_ioda_deconfigure_pe(phb, pe); |
| 1490 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1491 | pnv_ioda_free_pe(pe); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1492 | } |
| 1493 | } |
| 1494 | |
| 1495 | void pnv_pci_sriov_disable(struct pci_dev *pdev) |
| 1496 | { |
| 1497 | struct pci_bus *bus; |
| 1498 | struct pci_controller *hose; |
| 1499 | struct pnv_phb *phb; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1500 | struct pnv_ioda_pe *pe; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1501 | struct pci_dn *pdn; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1502 | u16 num_vfs, i; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1503 | |
| 1504 | bus = pdev->bus; |
| 1505 | hose = pci_bus_to_host(bus); |
| 1506 | phb = hose->private_data; |
| 1507 | pdn = pci_get_pdn(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1508 | num_vfs = pdn->num_vfs; |
| 1509 | |
| 1510 | /* Release VF PEs */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1511 | pnv_ioda_release_vf_PE(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1512 | |
| 1513 | if (phb->type == PNV_PHB_IODA2) { |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1514 | if (!pdn->m64_single_mode) |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1515 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1516 | |
| 1517 | /* Release M64 windows */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1518 | pnv_pci_vf_release_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1519 | |
| 1520 | /* Release PE numbers */ |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1521 | if (pdn->m64_single_mode) { |
| 1522 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1523 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
| 1524 | continue; |
| 1525 | |
| 1526 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; |
| 1527 | pnv_ioda_free_pe(pe); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1528 | } |
| 1529 | } else |
| 1530 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
| 1531 | /* Releasing pe_num_map */ |
| 1532 | kfree(pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
| 1537 | struct pnv_ioda_pe *pe); |
| 1538 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) |
| 1539 | { |
| 1540 | struct pci_bus *bus; |
| 1541 | struct pci_controller *hose; |
| 1542 | struct pnv_phb *phb; |
| 1543 | struct pnv_ioda_pe *pe; |
| 1544 | int pe_num; |
| 1545 | u16 vf_index; |
| 1546 | struct pci_dn *pdn; |
| 1547 | |
| 1548 | bus = pdev->bus; |
| 1549 | hose = pci_bus_to_host(bus); |
| 1550 | phb = hose->private_data; |
| 1551 | pdn = pci_get_pdn(pdev); |
| 1552 | |
| 1553 | if (!pdev->is_physfn) |
| 1554 | return; |
| 1555 | |
| 1556 | /* Reserve PE for each VF */ |
| 1557 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1558 | if (pdn->m64_single_mode) |
| 1559 | pe_num = pdn->pe_num_map[vf_index]; |
| 1560 | else |
| 1561 | pe_num = *pdn->pe_num_map + vf_index; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1562 | |
| 1563 | pe = &phb->ioda.pe_array[pe_num]; |
| 1564 | pe->pe_number = pe_num; |
| 1565 | pe->phb = phb; |
| 1566 | pe->flags = PNV_IODA_PE_VF; |
| 1567 | pe->pbus = NULL; |
| 1568 | pe->parent_dev = pdev; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1569 | pe->mve_number = -1; |
| 1570 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | |
| 1571 | pci_iov_virtfn_devfn(pdev, vf_index); |
| 1572 | |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1573 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1574 | hose->global_number, pdev->bus->number, |
| 1575 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), |
| 1576 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); |
| 1577 | |
| 1578 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1579 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1580 | pnv_ioda_free_pe(pe); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1581 | pe->pdev = NULL; |
| 1582 | continue; |
| 1583 | } |
| 1584 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1585 | /* Put PE to the list */ |
| 1586 | mutex_lock(&phb->ioda.pe_list_mutex); |
| 1587 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
| 1588 | mutex_unlock(&phb->ioda.pe_list_mutex); |
| 1589 | |
| 1590 | pnv_pci_ioda2_setup_dma_pe(phb, pe); |
| 1591 | } |
| 1592 | } |
| 1593 | |
| 1594 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
| 1595 | { |
| 1596 | struct pci_bus *bus; |
| 1597 | struct pci_controller *hose; |
| 1598 | struct pnv_phb *phb; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1599 | struct pnv_ioda_pe *pe; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1600 | struct pci_dn *pdn; |
| 1601 | int ret; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1602 | u16 i; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1603 | |
| 1604 | bus = pdev->bus; |
| 1605 | hose = pci_bus_to_host(bus); |
| 1606 | phb = hose->private_data; |
| 1607 | pdn = pci_get_pdn(pdev); |
| 1608 | |
| 1609 | if (phb->type == PNV_PHB_IODA2) { |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 1610 | if (!pdn->vfs_expanded) { |
| 1611 | dev_info(&pdev->dev, "don't support this SRIOV device" |
| 1612 | " with non 64bit-prefetchable IOV BAR\n"); |
| 1613 | return -ENOSPC; |
| 1614 | } |
| 1615 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1616 | /* |
| 1617 | * When M64 BARs functions in Single PE mode, the number of VFs |
| 1618 | * could be enabled must be less than the number of M64 BARs. |
| 1619 | */ |
| 1620 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { |
| 1621 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); |
| 1622 | return -EBUSY; |
| 1623 | } |
| 1624 | |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1625 | /* Allocating pe_num_map */ |
| 1626 | if (pdn->m64_single_mode) |
Markus Elfring | fb37e12 | 2016-08-24 22:26:37 +0200 | [diff] [blame] | 1627 | pdn->pe_num_map = kmalloc_array(num_vfs, |
| 1628 | sizeof(*pdn->pe_num_map), |
| 1629 | GFP_KERNEL); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1630 | else |
| 1631 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); |
| 1632 | |
| 1633 | if (!pdn->pe_num_map) |
| 1634 | return -ENOMEM; |
| 1635 | |
| 1636 | if (pdn->m64_single_mode) |
| 1637 | for (i = 0; i < num_vfs; i++) |
| 1638 | pdn->pe_num_map[i] = IODA_INVALID_PE; |
| 1639 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1640 | /* Calculate available PE for required VFs */ |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1641 | if (pdn->m64_single_mode) { |
| 1642 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1643 | pe = pnv_ioda_alloc_pe(phb); |
| 1644 | if (!pe) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1645 | ret = -EBUSY; |
| 1646 | goto m64_failed; |
| 1647 | } |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1648 | |
| 1649 | pdn->pe_num_map[i] = pe->pe_number; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1650 | } |
| 1651 | } else { |
| 1652 | mutex_lock(&phb->ioda.pe_alloc_mutex); |
| 1653 | *pdn->pe_num_map = bitmap_find_next_zero_area( |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1654 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1655 | 0, num_vfs, 0); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1656 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1657 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
| 1658 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); |
| 1659 | kfree(pdn->pe_num_map); |
| 1660 | return -EBUSY; |
| 1661 | } |
| 1662 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1663 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1664 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1665 | pdn->num_vfs = num_vfs; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1666 | |
| 1667 | /* Assign M64 window accordingly */ |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1668 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1669 | if (ret) { |
| 1670 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); |
| 1671 | goto m64_failed; |
| 1672 | } |
| 1673 | |
| 1674 | /* |
| 1675 | * When using one M64 BAR to map one IOV BAR, we need to shift |
| 1676 | * the IOV BAR according to the PE# allocated to the VFs. |
| 1677 | * Otherwise, the PE# for the VF will conflict with others. |
| 1678 | */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1679 | if (!pdn->m64_single_mode) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1680 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1681 | if (ret) |
| 1682 | goto m64_failed; |
| 1683 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1684 | } |
| 1685 | |
| 1686 | /* Setup VF PEs */ |
| 1687 | pnv_ioda_setup_vf_PE(pdev, num_vfs); |
| 1688 | |
| 1689 | return 0; |
| 1690 | |
| 1691 | m64_failed: |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1692 | if (pdn->m64_single_mode) { |
| 1693 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1694 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
| 1695 | continue; |
| 1696 | |
| 1697 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; |
| 1698 | pnv_ioda_free_pe(pe); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1699 | } |
| 1700 | } else |
| 1701 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
| 1702 | |
| 1703 | /* Releasing pe_num_map */ |
| 1704 | kfree(pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1705 | |
| 1706 | return ret; |
| 1707 | } |
| 1708 | |
Bryant G. Ly | 988fc3b | 2017-11-09 08:00:33 -0600 | [diff] [blame] | 1709 | int pnv_pcibios_sriov_disable(struct pci_dev *pdev) |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1710 | { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1711 | pnv_pci_sriov_disable(pdev); |
| 1712 | |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1713 | /* Release PCI data */ |
| 1714 | remove_dev_pci_data(pdev); |
| 1715 | return 0; |
| 1716 | } |
| 1717 | |
Bryant G. Ly | 988fc3b | 2017-11-09 08:00:33 -0600 | [diff] [blame] | 1718 | int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1719 | { |
| 1720 | /* Allocate PCI data */ |
| 1721 | add_dev_pci_data(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1722 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1723 | return pnv_pci_sriov_enable(pdev, num_vfs); |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1724 | } |
| 1725 | #endif /* CONFIG_PCI_IOV */ |
| 1726 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1727 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1728 | { |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1729 | struct pci_dn *pdn = pci_get_pdn(pdev); |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1730 | struct pnv_ioda_pe *pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1731 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1732 | /* |
| 1733 | * The function can be called while the PE# |
| 1734 | * hasn't been assigned. Do nothing for the |
| 1735 | * case. |
| 1736 | */ |
| 1737 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 1738 | return; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1739 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1740 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1741 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
Alexey Kardashevskiy | 0e1ffef | 2015-08-27 16:01:16 +1000 | [diff] [blame] | 1742 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1743 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
Alexey Kardashevskiy | 4617082 | 2015-06-05 16:34:54 +1000 | [diff] [blame] | 1744 | /* |
| 1745 | * Note: iommu_add_device() will fail here as |
| 1746 | * for physical PE: the device is already added by now; |
| 1747 | * for virtual PE: sysfs entries are not ready yet and |
| 1748 | * tce_iommu_bus_notifier will add the device to a group later. |
| 1749 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1750 | } |
| 1751 | |
Russell Currey | a0f9862 | 2017-06-21 17:18:03 +1000 | [diff] [blame] | 1752 | static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) |
| 1753 | { |
| 1754 | unsigned short vendor = 0; |
| 1755 | struct pci_dev *pdev; |
| 1756 | |
| 1757 | if (pe->device_count == 1) |
| 1758 | return true; |
| 1759 | |
| 1760 | /* pe->pdev should be set if it's a single device, pe->pbus if not */ |
| 1761 | if (!pe->pbus) |
| 1762 | return true; |
| 1763 | |
| 1764 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
| 1765 | if (!vendor) { |
| 1766 | vendor = pdev->vendor; |
| 1767 | continue; |
| 1768 | } |
| 1769 | |
| 1770 | if (pdev->vendor != vendor) |
| 1771 | return false; |
| 1772 | } |
| 1773 | |
| 1774 | return true; |
| 1775 | } |
| 1776 | |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1777 | /* |
| 1778 | * Reconfigure TVE#0 to be usable as 64-bit DMA space. |
| 1779 | * |
| 1780 | * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. |
| 1781 | * Devices can only access more than that if bit 59 of the PCI address is set |
| 1782 | * by hardware, which indicates TVE#1 should be used instead of TVE#0. |
| 1783 | * Many PCI devices are not capable of addressing that many bits, and as a |
| 1784 | * result are limited to the 4GB of virtual memory made available to 32-bit |
| 1785 | * devices in TVE#0. |
| 1786 | * |
| 1787 | * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit |
| 1788 | * devices by configuring the virtual memory past the first 4GB inaccessible |
| 1789 | * by 64-bit DMAs. This should only be used by devices that want more than |
| 1790 | * 4GB, and only on PEs that have no 32-bit devices. |
| 1791 | * |
| 1792 | * Currently this will only work on PHB3 (POWER8). |
| 1793 | */ |
| 1794 | static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) |
| 1795 | { |
| 1796 | u64 window_size, table_size, tce_count, addr; |
| 1797 | struct page *table_pages; |
| 1798 | u64 tce_order = 28; /* 256MB TCEs */ |
| 1799 | __be64 *tces; |
| 1800 | s64 rc; |
| 1801 | |
| 1802 | /* |
| 1803 | * Window size needs to be a power of two, but needs to account for |
| 1804 | * shifting memory by the 4GB offset required to skip 32bit space. |
| 1805 | */ |
| 1806 | window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); |
| 1807 | tce_count = window_size >> tce_order; |
| 1808 | table_size = tce_count << 3; |
| 1809 | |
| 1810 | if (table_size < PAGE_SIZE) |
| 1811 | table_size = PAGE_SIZE; |
| 1812 | |
| 1813 | table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, |
| 1814 | get_order(table_size)); |
| 1815 | if (!table_pages) |
| 1816 | goto err; |
| 1817 | |
| 1818 | tces = page_address(table_pages); |
| 1819 | if (!tces) |
| 1820 | goto err; |
| 1821 | |
| 1822 | memset(tces, 0, table_size); |
| 1823 | |
| 1824 | for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { |
| 1825 | tces[(addr + (1ULL << 32)) >> tce_order] = |
| 1826 | cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); |
| 1827 | } |
| 1828 | |
| 1829 | rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, |
| 1830 | pe->pe_number, |
| 1831 | /* reconfigure window 0 */ |
| 1832 | (pe->pe_number << 1) + 0, |
| 1833 | 1, |
| 1834 | __pa(tces), |
| 1835 | table_size, |
| 1836 | 1 << tce_order); |
| 1837 | if (rc == OPAL_SUCCESS) { |
| 1838 | pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); |
| 1839 | return 0; |
| 1840 | } |
| 1841 | err: |
| 1842 | pe_err(pe, "Error configuring 64-bit DMA bypass\n"); |
| 1843 | return -EIO; |
| 1844 | } |
| 1845 | |
Daniel Axtens | 763d2d8 | 2015-04-28 15:12:07 +1000 | [diff] [blame] | 1846 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1847 | { |
Daniel Axtens | 763d2d8 | 2015-04-28 15:12:07 +1000 | [diff] [blame] | 1848 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 1849 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1850 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 1851 | struct pnv_ioda_pe *pe; |
| 1852 | uint64_t top; |
| 1853 | bool bypass = false; |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1854 | s64 rc; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1855 | |
| 1856 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) |
Ingo Molnar | ed7158b | 2018-02-22 10:54:55 +0100 | [diff] [blame] | 1857 | return -ENODEV; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1858 | |
| 1859 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
| 1860 | if (pe->tce_bypass_enabled) { |
| 1861 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; |
| 1862 | bypass = (dma_mask >= top); |
| 1863 | } |
| 1864 | |
| 1865 | if (bypass) { |
| 1866 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); |
Christoph Hellwig | 2d9d6f6 | 2017-12-22 10:58:24 +0100 | [diff] [blame] | 1867 | set_dma_ops(&pdev->dev, &dma_nommu_ops); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1868 | } else { |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1869 | /* |
| 1870 | * If the device can't set the TCE bypass bit but still wants |
| 1871 | * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to |
| 1872 | * bypass the 32-bit region and be usable for 64-bit DMAs. |
| 1873 | * The device needs to be able to address all of this space. |
| 1874 | */ |
| 1875 | if (dma_mask >> 32 && |
| 1876 | dma_mask > (memory_hotplug_max() + (1ULL << 32)) && |
| 1877 | pnv_pci_ioda_pe_single_vendor(pe) && |
| 1878 | phb->model == PNV_PHB_MODEL_PHB3) { |
| 1879 | /* Configure the bypass mode */ |
| 1880 | rc = pnv_pci_ioda_dma_64bit_bypass(pe); |
| 1881 | if (rc) |
| 1882 | return rc; |
| 1883 | /* 4GB offset bypasses 32-bit space */ |
| 1884 | set_dma_offset(&pdev->dev, (1ULL << 32)); |
Christoph Hellwig | 2d9d6f6 | 2017-12-22 10:58:24 +0100 | [diff] [blame] | 1885 | set_dma_ops(&pdev->dev, &dma_nommu_ops); |
Alistair Popple | 253fd51 | 2017-07-26 15:26:40 +1000 | [diff] [blame] | 1886 | } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { |
| 1887 | /* |
| 1888 | * Fail the request if a DMA mask between 32 and 64 bits |
| 1889 | * was requested but couldn't be fulfilled. Ideally we |
| 1890 | * would do this for 64-bits but historically we have |
| 1891 | * always fallen back to 32-bits. |
| 1892 | */ |
| 1893 | return -ENOMEM; |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1894 | } else { |
| 1895 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); |
| 1896 | set_dma_ops(&pdev->dev, &dma_iommu_ops); |
| 1897 | } |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1898 | } |
Brian W Hart | a32305b | 2014-07-31 14:24:37 -0500 | [diff] [blame] | 1899 | *pdev->dev.dma_mask = dma_mask; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1900 | |
| 1901 | /* Update peer npu devices */ |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 1902 | pnv_npu_try_dma_set_bypass(pdev, bypass); |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1903 | |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1904 | return 0; |
| 1905 | } |
| 1906 | |
Andrew Donnellan | 53522982 | 2015-08-07 13:45:54 +1000 | [diff] [blame] | 1907 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
Gavin Shan | fe7e85c | 2014-09-30 12:39:10 +1000 | [diff] [blame] | 1908 | { |
Andrew Donnellan | 53522982 | 2015-08-07 13:45:54 +1000 | [diff] [blame] | 1909 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 1910 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | fe7e85c | 2014-09-30 12:39:10 +1000 | [diff] [blame] | 1911 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 1912 | struct pnv_ioda_pe *pe; |
| 1913 | u64 end, mask; |
| 1914 | |
| 1915 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) |
| 1916 | return 0; |
| 1917 | |
| 1918 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
| 1919 | if (!pe->tce_bypass_enabled) |
| 1920 | return __dma_get_required_mask(&pdev->dev); |
| 1921 | |
| 1922 | |
| 1923 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); |
| 1924 | mask = 1ULL << (fls64(end) - 1); |
| 1925 | mask += mask - 1; |
| 1926 | |
| 1927 | return mask; |
| 1928 | } |
| 1929 | |
Gavin Shan | dff4a39 | 2014-07-15 17:00:55 +1000 | [diff] [blame] | 1930 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1931 | struct pci_bus *bus, |
| 1932 | bool add_to_group) |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 1933 | { |
| 1934 | struct pci_dev *dev; |
| 1935 | |
| 1936 | list_for_each_entry(dev, &bus->devices, bus_list) { |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1937 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
Benjamin Herrenschmidt | e91c2511 | 2015-06-24 15:25:27 +1000 | [diff] [blame] | 1938 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1939 | if (add_to_group) |
| 1940 | iommu_add_device(&dev->dev); |
Gavin Shan | dff4a39 | 2014-07-15 17:00:55 +1000 | [diff] [blame] | 1941 | |
Alexey Kardashevskiy | 5c89a87 | 2015-06-18 11:41:36 +1000 | [diff] [blame] | 1942 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1943 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, |
| 1944 | add_to_group); |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 1945 | } |
| 1946 | } |
| 1947 | |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 1948 | static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, |
| 1949 | bool real_mode) |
| 1950 | { |
| 1951 | return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : |
| 1952 | (phb->regs + 0x210); |
| 1953 | } |
| 1954 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 1955 | static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1956 | unsigned long index, unsigned long npages, bool rm) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1957 | { |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 1958 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
| 1959 | &tbl->it_group_list, struct iommu_table_group_link, |
| 1960 | next); |
| 1961 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1962 | struct pnv_ioda_pe, table_group); |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 1963 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1964 | unsigned long start, end, inc; |
| 1965 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1966 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
| 1967 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + |
| 1968 | npages - 1); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1969 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 1970 | /* p7ioc-style invalidation, 2 TCEs per write */ |
| 1971 | start |= (1ull << 63); |
| 1972 | end |= (1ull << 63); |
| 1973 | inc = 16; |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1974 | end |= inc - 1; /* round up end to be different than start */ |
| 1975 | |
| 1976 | mb(); /* Ensure above stores are visible */ |
| 1977 | while (start <= end) { |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 1978 | if (rm) |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 1979 | __raw_rm_writeq_be(start, invalidate); |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 1980 | else |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 1981 | __raw_writeq_be(start, invalidate); |
| 1982 | |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1983 | start += inc; |
| 1984 | } |
| 1985 | |
| 1986 | /* |
| 1987 | * The iommu layer will do another mb() for us on build() |
| 1988 | * and we don't care on free() |
| 1989 | */ |
| 1990 | } |
| 1991 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1992 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
| 1993 | long npages, unsigned long uaddr, |
| 1994 | enum dma_data_direction direction, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 1995 | unsigned long attrs) |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1996 | { |
| 1997 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
| 1998 | attrs); |
| 1999 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2000 | if (!ret) |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2001 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2002 | |
| 2003 | return ret; |
| 2004 | } |
| 2005 | |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2006 | #ifdef CONFIG_IOMMU_API |
| 2007 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, |
| 2008 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2009 | { |
| 2010 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2011 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2012 | if (!ret) |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2013 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2014 | |
| 2015 | return ret; |
| 2016 | } |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2017 | |
| 2018 | static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, |
| 2019 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2020 | { |
| 2021 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2022 | |
| 2023 | if (!ret) |
| 2024 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); |
| 2025 | |
| 2026 | return ret; |
| 2027 | } |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2028 | #endif |
| 2029 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2030 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
| 2031 | long npages) |
| 2032 | { |
| 2033 | pnv_tce_free(tbl, index, npages); |
| 2034 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2035 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2036 | } |
| 2037 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2038 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2039 | .set = pnv_ioda1_tce_build, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2040 | #ifdef CONFIG_IOMMU_API |
| 2041 | .exchange = pnv_ioda1_tce_xchg, |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2042 | .exchange_rm = pnv_ioda1_tce_xchg_rm, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2043 | #endif |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2044 | .clear = pnv_ioda1_tce_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2045 | .get = pnv_tce_get, |
| 2046 | }; |
| 2047 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2048 | #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) |
| 2049 | #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) |
| 2050 | #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) |
Alexey Kardashevskiy | bef9253 | 2016-04-29 18:55:17 +1000 | [diff] [blame] | 2051 | |
Alistair Popple | 6b3d12a | 2017-05-03 13:24:08 +1000 | [diff] [blame] | 2052 | static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2053 | { |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2054 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2055 | const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2056 | |
| 2057 | mb(); /* Ensure previous TCE table stores are visible */ |
| 2058 | if (rm) |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 2059 | __raw_rm_writeq_be(val, invalidate); |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2060 | else |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 2061 | __raw_writeq_be(val, invalidate); |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2062 | } |
| 2063 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2064 | static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2065 | { |
| 2066 | /* 01xb - invalidate TCEs that match the specified PE# */ |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2067 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2068 | unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2069 | |
| 2070 | mb(); /* Ensure above stores are visible */ |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 2071 | __raw_writeq_be(val, invalidate); |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2072 | } |
| 2073 | |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2074 | static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, |
| 2075 | unsigned shift, unsigned long index, |
| 2076 | unsigned long npages) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2077 | { |
Alexey Kardashevskiy | 4d90219 | 2016-08-03 18:40:45 +1000 | [diff] [blame] | 2078 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2079 | unsigned long start, end, inc; |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2080 | |
| 2081 | /* We'll invalidate DMA address in PE scope */ |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2082 | start = PHB3_TCE_KILL_INVAL_ONE; |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2083 | start |= (pe->pe_number & 0xFF); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2084 | end = start; |
| 2085 | |
| 2086 | /* Figure out the start, end and step */ |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2087 | start |= (index << shift); |
| 2088 | end |= ((index + npages - 1) << shift); |
Alexey Kardashevskiy | b0376c9 | 2014-06-06 18:44:01 +1000 | [diff] [blame] | 2089 | inc = (0x1ull << shift); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2090 | mb(); |
| 2091 | |
| 2092 | while (start <= end) { |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 2093 | if (rm) |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 2094 | __raw_rm_writeq_be(start, invalidate); |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 2095 | else |
Michael Ellerman | 001ff2e | 2018-05-14 22:50:32 +1000 | [diff] [blame] | 2096 | __raw_writeq_be(start, invalidate); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2097 | start += inc; |
| 2098 | } |
| 2099 | } |
| 2100 | |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2101 | static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
| 2102 | { |
| 2103 | struct pnv_phb *phb = pe->phb; |
| 2104 | |
| 2105 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
| 2106 | pnv_pci_phb3_tce_invalidate_pe(pe); |
| 2107 | else |
| 2108 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, |
| 2109 | pe->pe_number, 0, 0, 0); |
| 2110 | } |
| 2111 | |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2112 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
| 2113 | unsigned long index, unsigned long npages, bool rm) |
| 2114 | { |
| 2115 | struct iommu_table_group_link *tgl; |
| 2116 | |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2117 | list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2118 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
| 2119 | struct pnv_ioda_pe, table_group); |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2120 | struct pnv_phb *phb = pe->phb; |
| 2121 | unsigned int shift = tbl->it_page_shift; |
| 2122 | |
Alistair Popple | 616badd | 2017-01-10 15:41:44 +1100 | [diff] [blame] | 2123 | /* |
| 2124 | * NVLink1 can use the TCE kill register directly as |
| 2125 | * it's the same as PHB3. NVLink2 is different and |
| 2126 | * should go via the OPAL call. |
| 2127 | */ |
| 2128 | if (phb->model == PNV_PHB_MODEL_NPU) { |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2129 | /* |
| 2130 | * The NVLink hardware does not support TCE kill |
| 2131 | * per TCE entry so we have to invalidate |
| 2132 | * the entire cache for it. |
| 2133 | */ |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2134 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
Alexey Kardashevskiy | 8567486 | 2016-04-29 18:55:23 +1000 | [diff] [blame] | 2135 | continue; |
| 2136 | } |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2137 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
| 2138 | pnv_pci_phb3_tce_invalidate(pe, rm, shift, |
| 2139 | index, npages); |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2140 | else |
| 2141 | opal_pci_tce_kill(phb->opal_id, |
| 2142 | OPAL_PCI_TCE_KILL_PAGES, |
| 2143 | pe->pe_number, 1u << shift, |
| 2144 | index << shift, npages); |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2145 | } |
| 2146 | } |
| 2147 | |
Alistair Popple | 6b3d12a | 2017-05-03 13:24:08 +1000 | [diff] [blame] | 2148 | void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
| 2149 | { |
| 2150 | if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) |
| 2151 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
| 2152 | else |
| 2153 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); |
| 2154 | } |
| 2155 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2156 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
| 2157 | long npages, unsigned long uaddr, |
| 2158 | enum dma_data_direction direction, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2159 | unsigned long attrs) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2160 | { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2161 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
| 2162 | attrs); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2163 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2164 | if (!ret) |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2165 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
| 2166 | |
| 2167 | return ret; |
| 2168 | } |
| 2169 | |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2170 | #ifdef CONFIG_IOMMU_API |
| 2171 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, |
| 2172 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2173 | { |
| 2174 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2175 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2176 | if (!ret) |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2177 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); |
| 2178 | |
| 2179 | return ret; |
| 2180 | } |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2181 | |
| 2182 | static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, |
| 2183 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2184 | { |
| 2185 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2186 | |
| 2187 | if (!ret) |
| 2188 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); |
| 2189 | |
| 2190 | return ret; |
| 2191 | } |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2192 | #endif |
| 2193 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2194 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
| 2195 | long npages) |
| 2196 | { |
| 2197 | pnv_tce_free(tbl, index, npages); |
| 2198 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2199 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2200 | } |
| 2201 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2202 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
| 2203 | { |
| 2204 | pnv_pci_ioda2_table_free_pages(tbl); |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2205 | } |
| 2206 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2207 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2208 | .set = pnv_ioda2_tce_build, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2209 | #ifdef CONFIG_IOMMU_API |
| 2210 | .exchange = pnv_ioda2_tce_xchg, |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2211 | .exchange_rm = pnv_ioda2_tce_xchg_rm, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2212 | #endif |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2213 | .clear = pnv_ioda2_tce_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2214 | .get = pnv_tce_get, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2215 | .free = pnv_ioda2_table_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2216 | }; |
| 2217 | |
Gavin Shan | 801846d | 2016-05-03 15:41:34 +1000 | [diff] [blame] | 2218 | static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) |
| 2219 | { |
| 2220 | unsigned int *weight = (unsigned int *)data; |
| 2221 | |
| 2222 | /* This is quite simplistic. The "base" weight of a device |
| 2223 | * is 10. 0 means no DMA is to be accounted for it. |
| 2224 | */ |
| 2225 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) |
| 2226 | return 0; |
| 2227 | |
| 2228 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || |
| 2229 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || |
| 2230 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) |
| 2231 | *weight += 3; |
| 2232 | else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) |
| 2233 | *weight += 15; |
| 2234 | else |
| 2235 | *weight += 10; |
| 2236 | |
| 2237 | return 0; |
| 2238 | } |
| 2239 | |
| 2240 | static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) |
| 2241 | { |
| 2242 | unsigned int weight = 0; |
| 2243 | |
| 2244 | /* SRIOV VF has same DMA32 weight as its PF */ |
| 2245 | #ifdef CONFIG_PCI_IOV |
| 2246 | if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { |
| 2247 | pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); |
| 2248 | return weight; |
| 2249 | } |
| 2250 | #endif |
| 2251 | |
| 2252 | if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { |
| 2253 | pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); |
| 2254 | } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { |
| 2255 | struct pci_dev *pdev; |
| 2256 | |
| 2257 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) |
| 2258 | pnv_pci_ioda_dev_dma_weight(pdev, &weight); |
| 2259 | } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { |
| 2260 | pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); |
| 2261 | } |
| 2262 | |
| 2263 | return weight; |
| 2264 | } |
| 2265 | |
Gavin Shan | b30d936 | 2016-05-03 15:41:32 +1000 | [diff] [blame] | 2266 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2267 | struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2268 | { |
| 2269 | |
| 2270 | struct page *tce_mem = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2271 | struct iommu_table *tbl; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2272 | unsigned int weight, total_weight = 0; |
| 2273 | unsigned int tce32_segsz, base, segs, avail, i; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2274 | int64_t rc; |
| 2275 | void *addr; |
| 2276 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2277 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
| 2278 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ |
| 2279 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2280 | weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 2281 | if (!weight) |
| 2282 | return; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2283 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2284 | pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, |
| 2285 | &total_weight); |
| 2286 | segs = (weight * phb->ioda.dma32_count) / total_weight; |
| 2287 | if (!segs) |
| 2288 | segs = 1; |
| 2289 | |
| 2290 | /* |
| 2291 | * Allocate contiguous DMA32 segments. We begin with the expected |
| 2292 | * number of segments. With one more attempt, the number of DMA32 |
| 2293 | * segments to be allocated is decreased by one until one segment |
| 2294 | * is allocated successfully. |
| 2295 | */ |
| 2296 | do { |
| 2297 | for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { |
| 2298 | for (avail = 0, i = base; i < base + segs; i++) { |
| 2299 | if (phb->ioda.dma32_segmap[i] == |
| 2300 | IODA_INVALID_PE) |
| 2301 | avail++; |
| 2302 | } |
| 2303 | |
| 2304 | if (avail == segs) |
| 2305 | goto found; |
| 2306 | } |
| 2307 | } while (--segs); |
| 2308 | |
| 2309 | if (!segs) { |
| 2310 | pe_warn(pe, "No available DMA32 segments\n"); |
| 2311 | return; |
| 2312 | } |
| 2313 | |
| 2314 | found: |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2315 | tbl = pnv_pci_table_alloc(phb->hose->node); |
Alexey Kardashevskiy | 82eae1a | 2017-03-27 19:27:37 +1100 | [diff] [blame] | 2316 | if (WARN_ON(!tbl)) |
| 2317 | return; |
| 2318 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 2319 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
| 2320 | pe->pe_number); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2321 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2322 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2323 | /* Grab a 32-bit TCE table */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2324 | pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", |
| 2325 | weight, total_weight, base, segs); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2326 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2327 | base * PNV_IODA1_DMA32_SEGSIZE, |
| 2328 | (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2329 | |
| 2330 | /* XXX Currently, we allocate one big contiguous table for the |
| 2331 | * TCEs. We only really need one chunk per 256M of TCE space |
| 2332 | * (ie per segment) but that's an optimization for later, it |
| 2333 | * requires some added smarts with our get/put_tce implementation |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2334 | * |
| 2335 | * Each TCE page is 4KB in size and each TCE entry occupies 8 |
| 2336 | * bytes |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2337 | */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2338 | tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2339 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2340 | get_order(tce32_segsz * segs)); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2341 | if (!tce_mem) { |
| 2342 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); |
| 2343 | goto fail; |
| 2344 | } |
| 2345 | addr = page_address(tce_mem); |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2346 | memset(addr, 0, tce32_segsz * segs); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2347 | |
| 2348 | /* Configure HW */ |
| 2349 | for (i = 0; i < segs; i++) { |
| 2350 | rc = opal_pci_map_pe_dma_window(phb->opal_id, |
| 2351 | pe->pe_number, |
| 2352 | base + i, 1, |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2353 | __pa(addr) + tce32_segsz * i, |
| 2354 | tce32_segsz, IOMMU_PAGE_SIZE_4K); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2355 | if (rc) { |
| 2356 | pe_err(pe, " Failed to configure 32-bit TCE table," |
| 2357 | " err %ld\n", rc); |
| 2358 | goto fail; |
| 2359 | } |
| 2360 | } |
| 2361 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2362 | /* Setup DMA32 segment mapping */ |
| 2363 | for (i = base; i < base + segs; i++) |
| 2364 | phb->ioda.dma32_segmap[i] = pe->pe_number; |
| 2365 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2366 | /* Setup linux iommu table */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2367 | pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, |
| 2368 | base * PNV_IODA1_DMA32_SEGSIZE, |
| 2369 | IOMMU_PAGE_SHIFT_4K); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2370 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2371 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2372 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
| 2373 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2374 | iommu_init_table(tbl, phb->hose->node); |
| 2375 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 2376 | if (pe->flags & PNV_IODA_PE_DEV) { |
Alexey Kardashevskiy | 4617082 | 2015-06-05 16:34:54 +1000 | [diff] [blame] | 2377 | /* |
| 2378 | * Setting table base here only for carrying iommu_group |
| 2379 | * further down to let iommu_add_device() do the job. |
| 2380 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. |
| 2381 | */ |
| 2382 | set_iommu_table_base(&pe->pdev->dev, tbl); |
| 2383 | iommu_add_device(&pe->pdev->dev); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2384 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2385 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 2386 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2387 | return; |
| 2388 | fail: |
| 2389 | /* XXX Failure: Try to fallback to 64-bit only ? */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2390 | if (tce_mem) |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2391 | __free_pages(tce_mem, get_order(tce32_segsz * segs)); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2392 | if (tbl) { |
| 2393 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2394 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2395 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2396 | } |
| 2397 | |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2398 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
| 2399 | int num, struct iommu_table *tbl) |
| 2400 | { |
| 2401 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2402 | table_group); |
| 2403 | struct pnv_phb *phb = pe->phb; |
| 2404 | int64_t rc; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2405 | const unsigned long size = tbl->it_indirect_levels ? |
| 2406 | tbl->it_level_size : tbl->it_size; |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2407 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
| 2408 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; |
| 2409 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2410 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2411 | start_addr, start_addr + win_size - 1, |
| 2412 | IOMMU_PAGE_SIZE(tbl)); |
| 2413 | |
| 2414 | /* |
| 2415 | * Map TCE table through TVT. The TVE index is the PE number |
| 2416 | * shifted by 1 bit for 32-bits DMA space. |
| 2417 | */ |
| 2418 | rc = opal_pci_map_pe_dma_window(phb->opal_id, |
| 2419 | pe->pe_number, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2420 | (pe->pe_number << 1) + num, |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2421 | tbl->it_indirect_levels + 1, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2422 | __pa(tbl->it_base), |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2423 | size << 3, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2424 | IOMMU_PAGE_SIZE(tbl)); |
| 2425 | if (rc) { |
| 2426 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); |
| 2427 | return rc; |
| 2428 | } |
| 2429 | |
| 2430 | pnv_pci_link_table_and_group(phb->hose->node, num, |
| 2431 | tbl, &pe->table_group); |
Michael Ellerman | ed7d9a1 | 2016-09-15 17:03:06 +1000 | [diff] [blame] | 2432 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2433 | |
| 2434 | return 0; |
| 2435 | } |
| 2436 | |
Frederic Barrat | 2552910 | 2017-08-04 11:55:14 +0200 | [diff] [blame] | 2437 | void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2438 | { |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2439 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
| 2440 | int64_t rc; |
| 2441 | |
| 2442 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); |
| 2443 | if (enable) { |
| 2444 | phys_addr_t top = memblock_end_of_DRAM(); |
| 2445 | |
| 2446 | top = roundup_pow_of_two(top); |
| 2447 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, |
| 2448 | pe->pe_number, |
| 2449 | window_id, |
| 2450 | pe->tce_bypass_base, |
| 2451 | top); |
| 2452 | } else { |
| 2453 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, |
| 2454 | pe->pe_number, |
| 2455 | window_id, |
| 2456 | pe->tce_bypass_base, |
| 2457 | 0); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2458 | } |
| 2459 | if (rc) |
| 2460 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); |
| 2461 | else |
| 2462 | pe->tce_bypass_enabled = enable; |
| 2463 | } |
| 2464 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2465 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
| 2466 | __u32 page_shift, __u64 window_size, __u32 levels, |
| 2467 | struct iommu_table *tbl); |
| 2468 | |
| 2469 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, |
| 2470 | int num, __u32 page_shift, __u64 window_size, __u32 levels, |
| 2471 | struct iommu_table **ptbl) |
| 2472 | { |
| 2473 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2474 | table_group); |
| 2475 | int nid = pe->phb->hose->node; |
| 2476 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; |
| 2477 | long ret; |
| 2478 | struct iommu_table *tbl; |
| 2479 | |
| 2480 | tbl = pnv_pci_table_alloc(nid); |
| 2481 | if (!tbl) |
| 2482 | return -ENOMEM; |
| 2483 | |
Alexey Kardashevskiy | 11edf11 | 2017-03-22 15:21:49 +1100 | [diff] [blame] | 2484 | tbl->it_ops = &pnv_ioda2_iommu_ops; |
| 2485 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2486 | ret = pnv_pci_ioda2_table_alloc_pages(nid, |
| 2487 | bus_offset, page_shift, window_size, |
| 2488 | levels, tbl); |
| 2489 | if (ret) { |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2490 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2491 | return ret; |
| 2492 | } |
| 2493 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2494 | *ptbl = tbl; |
| 2495 | |
| 2496 | return 0; |
| 2497 | } |
| 2498 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2499 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
| 2500 | { |
| 2501 | struct iommu_table *tbl = NULL; |
| 2502 | long rc; |
| 2503 | |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2504 | /* |
Nishanth Aravamudan | fa14486 | 2015-09-04 11:22:52 -0700 | [diff] [blame] | 2505 | * crashkernel= specifies the kdump kernel's maximum memory at |
| 2506 | * some offset and there is no guaranteed the result is a power |
| 2507 | * of 2, which will cause errors later. |
| 2508 | */ |
| 2509 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); |
| 2510 | |
| 2511 | /* |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2512 | * In memory constrained environments, e.g. kdump kernel, the |
| 2513 | * DMA window can be larger than available memory, which will |
| 2514 | * cause errors later. |
| 2515 | */ |
Nishanth Aravamudan | fa14486 | 2015-09-04 11:22:52 -0700 | [diff] [blame] | 2516 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2517 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2518 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
| 2519 | IOMMU_PAGE_SHIFT_4K, |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2520 | window_size, |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2521 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
| 2522 | if (rc) { |
| 2523 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", |
| 2524 | rc); |
| 2525 | return rc; |
| 2526 | } |
| 2527 | |
| 2528 | iommu_init_table(tbl, pe->phb->hose->node); |
| 2529 | |
| 2530 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); |
| 2531 | if (rc) { |
| 2532 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", |
| 2533 | rc); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2534 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2535 | return rc; |
| 2536 | } |
| 2537 | |
| 2538 | if (!pnv_iommu_bypass_disabled) |
| 2539 | pnv_pci_ioda2_set_bypass(pe, true); |
| 2540 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2541 | /* |
| 2542 | * Setting table base here only for carrying iommu_group |
| 2543 | * further down to let iommu_add_device() do the job. |
| 2544 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. |
| 2545 | */ |
| 2546 | if (pe->flags & PNV_IODA_PE_DEV) |
| 2547 | set_iommu_table_base(&pe->pdev->dev, tbl); |
| 2548 | |
| 2549 | return 0; |
| 2550 | } |
| 2551 | |
Alexey Kardashevskiy | b592643 | 2015-06-15 17:49:59 +1000 | [diff] [blame] | 2552 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
| 2553 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
| 2554 | int num) |
| 2555 | { |
| 2556 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2557 | table_group); |
| 2558 | struct pnv_phb *phb = pe->phb; |
| 2559 | long ret; |
| 2560 | |
| 2561 | pe_info(pe, "Removing DMA window #%d\n", num); |
| 2562 | |
| 2563 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, |
| 2564 | (pe->pe_number << 1) + num, |
| 2565 | 0/* levels */, 0/* table address */, |
| 2566 | 0/* table size */, 0/* page size */); |
| 2567 | if (ret) |
| 2568 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); |
| 2569 | else |
Michael Ellerman | ed7d9a1 | 2016-09-15 17:03:06 +1000 | [diff] [blame] | 2570 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
Alexey Kardashevskiy | b592643 | 2015-06-15 17:49:59 +1000 | [diff] [blame] | 2571 | |
| 2572 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); |
| 2573 | |
| 2574 | return ret; |
| 2575 | } |
| 2576 | #endif |
| 2577 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2578 | #ifdef CONFIG_IOMMU_API |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2579 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
| 2580 | __u64 window_size, __u32 levels) |
| 2581 | { |
| 2582 | unsigned long bytes = 0; |
| 2583 | const unsigned window_shift = ilog2(window_size); |
| 2584 | unsigned entries_shift = window_shift - page_shift; |
| 2585 | unsigned table_shift = entries_shift + 3; |
| 2586 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); |
| 2587 | unsigned long direct_table_size; |
| 2588 | |
| 2589 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2590 | !is_power_of_2(window_size)) |
| 2591 | return 0; |
| 2592 | |
| 2593 | /* Calculate a direct table size from window_size and levels */ |
| 2594 | entries_shift = (entries_shift + levels - 1) / levels; |
| 2595 | table_shift = entries_shift + 3; |
| 2596 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); |
| 2597 | direct_table_size = 1UL << table_shift; |
| 2598 | |
| 2599 | for ( ; levels; --levels) { |
| 2600 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); |
| 2601 | |
| 2602 | tce_table_size /= direct_table_size; |
| 2603 | tce_table_size <<= 3; |
Alexey Kardashevskiy | e49a6a2 | 2017-04-13 17:05:27 +1000 | [diff] [blame] | 2604 | tce_table_size = max_t(unsigned long, |
| 2605 | tce_table_size, direct_table_size); |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2606 | } |
| 2607 | |
| 2608 | return bytes; |
| 2609 | } |
| 2610 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2611 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2612 | { |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2613 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2614 | table_group); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2615 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
| 2616 | struct iommu_table *tbl = pe->table_group.tables[0]; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2617 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2618 | pnv_pci_ioda2_set_bypass(pe, false); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2619 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2620 | if (pe->pbus) |
| 2621 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2622 | iommu_tce_table_put(tbl); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2623 | } |
| 2624 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2625 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
| 2626 | { |
| 2627 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2628 | table_group); |
| 2629 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2630 | pnv_pci_ioda2_setup_default_config(pe); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2631 | if (pe->pbus) |
| 2632 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2633 | } |
| 2634 | |
| 2635 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2636 | .get_table_size = pnv_pci_ioda2_get_table_size, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2637 | .create_table = pnv_pci_ioda2_create_table, |
| 2638 | .set_window = pnv_pci_ioda2_set_window, |
| 2639 | .unset_window = pnv_pci_ioda2_unset_window, |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2640 | .take_ownership = pnv_ioda2_take_ownership, |
| 2641 | .release_ownership = pnv_ioda2_release_ownership, |
| 2642 | }; |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2643 | |
| 2644 | static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) |
| 2645 | { |
| 2646 | struct pci_controller *hose; |
| 2647 | struct pnv_phb *phb; |
| 2648 | struct pnv_ioda_pe **ptmppe = opaque; |
| 2649 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); |
| 2650 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 2651 | |
| 2652 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 2653 | return 0; |
| 2654 | |
| 2655 | hose = pci_bus_to_host(pdev->bus); |
| 2656 | phb = hose->private_data; |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 2657 | if (phb->type != PNV_PHB_NPU_NVLINK) |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2658 | return 0; |
| 2659 | |
| 2660 | *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; |
| 2661 | |
| 2662 | return 1; |
| 2663 | } |
| 2664 | |
| 2665 | /* |
| 2666 | * This returns PE of associated NPU. |
| 2667 | * This assumes that NPU is in the same IOMMU group with GPU and there is |
| 2668 | * no other PEs. |
| 2669 | */ |
| 2670 | static struct pnv_ioda_pe *gpe_table_group_to_npe( |
| 2671 | struct iommu_table_group *table_group) |
| 2672 | { |
| 2673 | struct pnv_ioda_pe *npe = NULL; |
| 2674 | int ret = iommu_group_for_each_dev(table_group->group, &npe, |
| 2675 | gpe_table_group_to_npe_cb); |
| 2676 | |
| 2677 | BUG_ON(!ret || !npe); |
| 2678 | |
| 2679 | return npe; |
| 2680 | } |
| 2681 | |
| 2682 | static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, |
| 2683 | int num, struct iommu_table *tbl) |
| 2684 | { |
Alexey Kardashevskiy | d41ce7b | 2018-02-13 16:51:35 +1100 | [diff] [blame] | 2685 | struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); |
| 2686 | int num2 = (num == 0) ? 1 : 0; |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2687 | long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); |
| 2688 | |
| 2689 | if (ret) |
| 2690 | return ret; |
| 2691 | |
Alexey Kardashevskiy | d41ce7b | 2018-02-13 16:51:35 +1100 | [diff] [blame] | 2692 | if (table_group->tables[num2]) |
| 2693 | pnv_npu_unset_window(npe, num2); |
| 2694 | |
| 2695 | ret = pnv_npu_set_window(npe, num, tbl); |
| 2696 | if (ret) { |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2697 | pnv_pci_ioda2_unset_window(table_group, num); |
Alexey Kardashevskiy | d41ce7b | 2018-02-13 16:51:35 +1100 | [diff] [blame] | 2698 | if (table_group->tables[num2]) |
| 2699 | pnv_npu_set_window(npe, num2, |
| 2700 | table_group->tables[num2]); |
| 2701 | } |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2702 | |
| 2703 | return ret; |
| 2704 | } |
| 2705 | |
| 2706 | static long pnv_pci_ioda2_npu_unset_window( |
| 2707 | struct iommu_table_group *table_group, |
| 2708 | int num) |
| 2709 | { |
Alexey Kardashevskiy | d41ce7b | 2018-02-13 16:51:35 +1100 | [diff] [blame] | 2710 | struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group); |
| 2711 | int num2 = (num == 0) ? 1 : 0; |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2712 | long ret = pnv_pci_ioda2_unset_window(table_group, num); |
| 2713 | |
| 2714 | if (ret) |
| 2715 | return ret; |
| 2716 | |
Alexey Kardashevskiy | d41ce7b | 2018-02-13 16:51:35 +1100 | [diff] [blame] | 2717 | if (!npe->table_group.tables[num]) |
| 2718 | return 0; |
| 2719 | |
| 2720 | ret = pnv_npu_unset_window(npe, num); |
| 2721 | if (ret) |
| 2722 | return ret; |
| 2723 | |
| 2724 | if (table_group->tables[num2]) |
| 2725 | ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]); |
| 2726 | |
| 2727 | return ret; |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2728 | } |
| 2729 | |
| 2730 | static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) |
| 2731 | { |
| 2732 | /* |
| 2733 | * Detach NPU first as pnv_ioda2_take_ownership() will destroy |
| 2734 | * the iommu_table if 32bit DMA is enabled. |
| 2735 | */ |
| 2736 | pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); |
| 2737 | pnv_ioda2_take_ownership(table_group); |
| 2738 | } |
| 2739 | |
| 2740 | static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { |
| 2741 | .get_table_size = pnv_pci_ioda2_get_table_size, |
| 2742 | .create_table = pnv_pci_ioda2_create_table, |
| 2743 | .set_window = pnv_pci_ioda2_npu_set_window, |
| 2744 | .unset_window = pnv_pci_ioda2_npu_unset_window, |
| 2745 | .take_ownership = pnv_ioda2_npu_take_ownership, |
| 2746 | .release_ownership = pnv_ioda2_release_ownership, |
| 2747 | }; |
| 2748 | |
| 2749 | static void pnv_pci_ioda_setup_iommu_api(void) |
| 2750 | { |
| 2751 | struct pci_controller *hose, *tmp; |
| 2752 | struct pnv_phb *phb; |
| 2753 | struct pnv_ioda_pe *pe, *gpe; |
| 2754 | |
| 2755 | /* |
| 2756 | * Now we have all PHBs discovered, time to add NPU devices to |
| 2757 | * the corresponding IOMMU groups. |
| 2758 | */ |
| 2759 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
| 2760 | phb = hose->private_data; |
| 2761 | |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 2762 | if (phb->type != PNV_PHB_NPU_NVLINK) |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2763 | continue; |
| 2764 | |
| 2765 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
| 2766 | gpe = pnv_pci_npu_setup_iommu(pe); |
| 2767 | if (gpe) |
| 2768 | gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; |
| 2769 | } |
| 2770 | } |
| 2771 | } |
| 2772 | #else /* !CONFIG_IOMMU_API */ |
| 2773 | static void pnv_pci_ioda_setup_iommu_api(void) { }; |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2774 | #endif |
| 2775 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2776 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
| 2777 | unsigned levels, unsigned long limit, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2778 | unsigned long *current_offset, unsigned long *total_allocated) |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2779 | { |
| 2780 | struct page *tce_mem = NULL; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2781 | __be64 *addr, *tmp; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2782 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2783 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
| 2784 | unsigned entries = 1UL << (shift - 3); |
| 2785 | long i; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2786 | |
| 2787 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); |
| 2788 | if (!tce_mem) { |
| 2789 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); |
| 2790 | return NULL; |
| 2791 | } |
| 2792 | addr = page_address(tce_mem); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2793 | memset(addr, 0, allocated); |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2794 | *total_allocated += allocated; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2795 | |
| 2796 | --levels; |
| 2797 | if (!levels) { |
| 2798 | *current_offset += allocated; |
| 2799 | return addr; |
| 2800 | } |
| 2801 | |
| 2802 | for (i = 0; i < entries; ++i) { |
| 2803 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2804 | levels, limit, current_offset, total_allocated); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2805 | if (!tmp) |
| 2806 | break; |
| 2807 | |
| 2808 | addr[i] = cpu_to_be64(__pa(tmp) | |
| 2809 | TCE_PCI_READ | TCE_PCI_WRITE); |
| 2810 | |
| 2811 | if (*current_offset >= limit) |
| 2812 | break; |
| 2813 | } |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2814 | |
| 2815 | return addr; |
| 2816 | } |
| 2817 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2818 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
| 2819 | unsigned long size, unsigned level); |
| 2820 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2821 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2822 | __u32 page_shift, __u64 window_size, __u32 levels, |
| 2823 | struct iommu_table *tbl) |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2824 | { |
| 2825 | void *addr; |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2826 | unsigned long offset = 0, level_shift, total_allocated = 0; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2827 | const unsigned window_shift = ilog2(window_size); |
| 2828 | unsigned entries_shift = window_shift - page_shift; |
| 2829 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); |
| 2830 | const unsigned long tce_table_size = 1UL << table_shift; |
| 2831 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2832 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
| 2833 | return -EINVAL; |
| 2834 | |
Alexey Kardashevskiy | 9003a24 | 2017-11-07 14:43:01 +1100 | [diff] [blame] | 2835 | if (!is_power_of_2(window_size)) |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2836 | return -EINVAL; |
| 2837 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2838 | /* Adjust direct table size from window_size and levels */ |
| 2839 | entries_shift = (entries_shift + levels - 1) / levels; |
| 2840 | level_shift = entries_shift + 3; |
| 2841 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); |
| 2842 | |
Alexey Kardashevskiy | 7aafac1 | 2017-02-22 15:43:59 +1100 | [diff] [blame] | 2843 | if ((level_shift - 3) * levels + page_shift >= 60) |
| 2844 | return -EINVAL; |
| 2845 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2846 | /* Allocate TCE table */ |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2847 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2848 | levels, tce_table_size, &offset, &total_allocated); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2849 | |
| 2850 | /* addr==NULL means that the first level allocation failed */ |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2851 | if (!addr) |
| 2852 | return -ENOMEM; |
| 2853 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2854 | /* |
| 2855 | * First level was allocated but some lower level failed as |
| 2856 | * we did not allocate as much as we wanted, |
| 2857 | * release partially allocated table. |
| 2858 | */ |
| 2859 | if (offset < tce_table_size) { |
| 2860 | pnv_pci_ioda2_table_do_free_pages(addr, |
| 2861 | 1ULL << (level_shift - 3), levels - 1); |
| 2862 | return -ENOMEM; |
| 2863 | } |
| 2864 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2865 | /* Setup linux iommu table */ |
| 2866 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, |
| 2867 | page_shift); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2868 | tbl->it_level_size = 1ULL << (level_shift - 3); |
| 2869 | tbl->it_indirect_levels = levels - 1; |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2870 | tbl->it_allocated_size = total_allocated; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2871 | |
| 2872 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", |
| 2873 | window_size, tce_table_size, bus_offset); |
| 2874 | |
| 2875 | return 0; |
| 2876 | } |
| 2877 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2878 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
| 2879 | unsigned long size, unsigned level) |
| 2880 | { |
| 2881 | const unsigned long addr_ul = (unsigned long) addr & |
| 2882 | ~(TCE_PCI_READ | TCE_PCI_WRITE); |
| 2883 | |
| 2884 | if (level) { |
| 2885 | long i; |
| 2886 | u64 *tmp = (u64 *) addr_ul; |
| 2887 | |
| 2888 | for (i = 0; i < size; ++i) { |
| 2889 | unsigned long hpa = be64_to_cpu(tmp[i]); |
| 2890 | |
| 2891 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) |
| 2892 | continue; |
| 2893 | |
| 2894 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, |
| 2895 | level - 1); |
| 2896 | } |
| 2897 | } |
| 2898 | |
| 2899 | free_pages(addr_ul, get_order(size << 3)); |
| 2900 | } |
| 2901 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2902 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
| 2903 | { |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2904 | const unsigned long size = tbl->it_indirect_levels ? |
| 2905 | tbl->it_level_size : tbl->it_size; |
| 2906 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2907 | if (!tbl->it_size) |
| 2908 | return; |
| 2909 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2910 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
| 2911 | tbl->it_indirect_levels); |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2912 | } |
| 2913 | |
Alexey Kardashevskiy | 7ef73cd | 2018-05-14 19:39:22 +1000 | [diff] [blame] | 2914 | static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb) |
| 2915 | { |
| 2916 | struct pci_controller *hose = phb->hose; |
| 2917 | struct device_node *dn = hose->dn; |
| 2918 | unsigned long mask = 0; |
| 2919 | int i, rc, count; |
| 2920 | u32 val; |
| 2921 | |
| 2922 | count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); |
| 2923 | if (count <= 0) { |
| 2924 | mask = SZ_4K | SZ_64K; |
| 2925 | /* Add 16M for POWER8 by default */ |
| 2926 | if (cpu_has_feature(CPU_FTR_ARCH_207S) && |
| 2927 | !cpu_has_feature(CPU_FTR_ARCH_300)) |
| 2928 | mask |= SZ_16M; |
| 2929 | return mask; |
| 2930 | } |
| 2931 | |
| 2932 | for (i = 0; i < count; i++) { |
| 2933 | rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", |
| 2934 | i, &val); |
| 2935 | if (rc == 0) |
| 2936 | mask |= 1ULL << val; |
| 2937 | } |
| 2938 | |
| 2939 | return mask; |
| 2940 | } |
| 2941 | |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2942 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
| 2943 | struct pnv_ioda_pe *pe) |
| 2944 | { |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2945 | int64_t rc; |
| 2946 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 2947 | if (!pnv_pci_ioda_pe_dma_weight(pe)) |
| 2948 | return; |
| 2949 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2950 | /* TVE #1 is selected by PCI address bit 59 */ |
| 2951 | pe->tce_bypass_base = 1ull << 59; |
| 2952 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 2953 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
| 2954 | pe->pe_number); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2955 | |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2956 | /* The PE will reserve all possible 32-bits space */ |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2957 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2958 | phb->ioda.m32_pci_base); |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2959 | |
Alexey Kardashevskiy | e5aad1e | 2015-06-05 16:35:16 +1000 | [diff] [blame] | 2960 | /* Setup linux iommu table */ |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2961 | pe->table_group.tce32_start = 0; |
| 2962 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; |
| 2963 | pe->table_group.max_dynamic_windows_supported = |
| 2964 | IOMMU_TABLE_GROUP_MAX_TABLES; |
| 2965 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; |
Alexey Kardashevskiy | 7ef73cd | 2018-05-14 19:39:22 +1000 | [diff] [blame] | 2966 | pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); |
Alexey Kardashevskiy | e5aad1e | 2015-06-05 16:35:16 +1000 | [diff] [blame] | 2967 | #ifdef CONFIG_IOMMU_API |
| 2968 | pe->table_group.ops = &pnv_pci_ioda2_ops; |
| 2969 | #endif |
| 2970 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2971 | rc = pnv_pci_ioda2_setup_default_config(pe); |
Gavin Shan | 801846d | 2016-05-03 15:41:34 +1000 | [diff] [blame] | 2972 | if (rc) |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2973 | return; |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2974 | |
Alexey Kardashevskiy | 20f13b9 | 2017-02-21 13:40:20 +1100 | [diff] [blame] | 2975 | if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2976 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2977 | } |
| 2978 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2979 | #ifdef CONFIG_PCI_MSI |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 2980 | int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2981 | { |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2982 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, |
| 2983 | ioda.irq_chip); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2984 | |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 2985 | return opal_pci_msi_eoi(phb->opal_id, hw_irq); |
| 2986 | } |
| 2987 | |
| 2988 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
| 2989 | { |
| 2990 | int64_t rc; |
| 2991 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); |
| 2992 | struct irq_chip *chip = irq_data_get_irq_chip(d); |
| 2993 | |
| 2994 | rc = pnv_opal_pci_msi_eoi(chip, hw_irq); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2995 | WARN_ON_ONCE(rc); |
| 2996 | |
| 2997 | icp_native_eoi(d); |
| 2998 | } |
| 2999 | |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 3000 | |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 3001 | void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 3002 | { |
| 3003 | struct irq_data *idata; |
| 3004 | struct irq_chip *ichip; |
| 3005 | |
Benjamin Herrenschmidt | fb11133 | 2016-07-08 16:37:09 +1000 | [diff] [blame] | 3006 | /* The MSI EOI OPAL call is only needed on PHB3 */ |
| 3007 | if (phb->model != PNV_PHB_MODEL_PHB3) |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 3008 | return; |
| 3009 | |
| 3010 | if (!phb->ioda.irq_chip_init) { |
| 3011 | /* |
| 3012 | * First time we setup an MSI IRQ, we need to setup the |
| 3013 | * corresponding IRQ chip to route correctly. |
| 3014 | */ |
| 3015 | idata = irq_get_irq_data(virq); |
| 3016 | ichip = irq_data_get_irq_chip(idata); |
| 3017 | phb->ioda.irq_chip_init = 1; |
| 3018 | phb->ioda.irq_chip = *ichip; |
| 3019 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; |
| 3020 | } |
| 3021 | irq_set_chip(virq, &phb->ioda.irq_chip); |
| 3022 | } |
| 3023 | |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 3024 | /* |
| 3025 | * Returns true iff chip is something that we could call |
| 3026 | * pnv_opal_pci_msi_eoi for. |
| 3027 | */ |
| 3028 | bool is_pnv_opal_msi(struct irq_chip *chip) |
| 3029 | { |
| 3030 | return chip->irq_eoi == pnv_ioda2_msi_eoi; |
| 3031 | } |
| 3032 | EXPORT_SYMBOL_GPL(is_pnv_opal_msi); |
| 3033 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3034 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 3035 | unsigned int hwirq, unsigned int virq, |
| 3036 | unsigned int is_64, struct msi_msg *msg) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3037 | { |
| 3038 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); |
| 3039 | unsigned int xive_num = hwirq - phb->msi_base; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3040 | __be32 data; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3041 | int rc; |
| 3042 | |
| 3043 | /* No PE assigned ? bail out ... no MSI for you ! */ |
| 3044 | if (pe == NULL) |
| 3045 | return -ENXIO; |
| 3046 | |
| 3047 | /* Check if we have an MVE */ |
| 3048 | if (pe->mve_number < 0) |
| 3049 | return -ENXIO; |
| 3050 | |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 3051 | /* Force 32-bit MSI on some broken devices */ |
Benjamin Herrenschmidt | 3607438 | 2014-10-07 16:12:36 +1100 | [diff] [blame] | 3052 | if (dev->no_64bit_msi) |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 3053 | is_64 = 0; |
| 3054 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3055 | /* Assign XIVE to PE */ |
| 3056 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); |
| 3057 | if (rc) { |
| 3058 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", |
| 3059 | pci_name(dev), rc, xive_num); |
| 3060 | return -EIO; |
| 3061 | } |
| 3062 | |
| 3063 | if (is_64) { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3064 | __be64 addr64; |
| 3065 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3066 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
| 3067 | &addr64, &data); |
| 3068 | if (rc) { |
| 3069 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", |
| 3070 | pci_name(dev), rc); |
| 3071 | return -EIO; |
| 3072 | } |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3073 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
| 3074 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3075 | } else { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3076 | __be32 addr32; |
| 3077 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3078 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
| 3079 | &addr32, &data); |
| 3080 | if (rc) { |
| 3081 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", |
| 3082 | pci_name(dev), rc); |
| 3083 | return -EIO; |
| 3084 | } |
| 3085 | msg->address_hi = 0; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3086 | msg->address_lo = be32_to_cpu(addr32); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3087 | } |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3088 | msg->data = be32_to_cpu(data); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3089 | |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 3090 | pnv_set_msi_irq_chip(phb, virq); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 3091 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3092 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3093 | " address=%x_%08x data=%x PE# %x\n", |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3094 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, |
| 3095 | msg->address_hi, msg->address_lo, data, pe->pe_number); |
| 3096 | |
| 3097 | return 0; |
| 3098 | } |
| 3099 | |
| 3100 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) |
| 3101 | { |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3102 | unsigned int count; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3103 | const __be32 *prop = of_get_property(phb->hose->dn, |
| 3104 | "ibm,opal-msi-ranges", NULL); |
| 3105 | if (!prop) { |
| 3106 | /* BML Fallback */ |
| 3107 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); |
| 3108 | } |
| 3109 | if (!prop) |
| 3110 | return; |
| 3111 | |
| 3112 | phb->msi_base = be32_to_cpup(prop); |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3113 | count = be32_to_cpup(prop + 1); |
| 3114 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3115 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
| 3116 | phb->hose->global_number); |
| 3117 | return; |
| 3118 | } |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3119 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3120 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
| 3121 | phb->msi32_support = 1; |
| 3122 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3123 | count, phb->msi_base); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3124 | } |
| 3125 | #else |
| 3126 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } |
| 3127 | #endif /* CONFIG_PCI_MSI */ |
| 3128 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3129 | #ifdef CONFIG_PCI_IOV |
| 3130 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) |
| 3131 | { |
Wei Yang | f2dd0af | 2015-10-22 09:22:17 +0800 | [diff] [blame] | 3132 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3133 | struct pnv_phb *phb = hose->private_data; |
| 3134 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3135 | struct resource *res; |
| 3136 | int i; |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3137 | resource_size_t size, total_vf_bar_sz; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3138 | struct pci_dn *pdn; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3139 | int mul, total_vfs; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3140 | |
| 3141 | if (!pdev->is_physfn || pdev->is_added) |
| 3142 | return; |
| 3143 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3144 | pdn = pci_get_pdn(pdev); |
| 3145 | pdn->vfs_expanded = 0; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3146 | pdn->m64_single_mode = false; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3147 | |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3148 | total_vfs = pci_sriov_get_totalvfs(pdev); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3149 | mul = phb->ioda.total_pe_num; |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3150 | total_vf_bar_sz = 0; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3151 | |
| 3152 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3153 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3154 | if (!res->flags || res->parent) |
| 3155 | continue; |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 3156 | if (!pnv_pci_is_m64_flags(res->flags)) { |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3157 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
| 3158 | " non M64 VF BAR%d: %pR. \n", |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3159 | i, res); |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3160 | goto truncate_iov; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3161 | } |
| 3162 | |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3163 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
| 3164 | i + PCI_IOV_RESOURCES); |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3165 | |
Wei Yang | f2dd0af | 2015-10-22 09:22:17 +0800 | [diff] [blame] | 3166 | /* |
| 3167 | * If bigger than quarter of M64 segment size, just round up |
| 3168 | * power of two. |
| 3169 | * |
| 3170 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict |
| 3171 | * with other devices, IOV BAR size is expanded to be |
| 3172 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 |
| 3173 | * segment size , the expanded size would equal to half of the |
| 3174 | * whole M64 space size, which will exhaust the M64 Space and |
| 3175 | * limit the system flexibility. This is a design decision to |
| 3176 | * set the boundary to quarter of the M64 segment size. |
| 3177 | */ |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3178 | if (total_vf_bar_sz > gate) { |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3179 | mul = roundup_pow_of_two(total_vfs); |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3180 | dev_info(&pdev->dev, |
| 3181 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", |
| 3182 | total_vf_bar_sz, gate, mul); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3183 | pdn->m64_single_mode = true; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3184 | break; |
| 3185 | } |
| 3186 | } |
| 3187 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3188 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3189 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3190 | if (!res->flags || res->parent) |
| 3191 | continue; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3192 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3193 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3194 | /* |
| 3195 | * On PHB3, the minimum size alignment of M64 BAR in single |
| 3196 | * mode is 32MB. |
| 3197 | */ |
| 3198 | if (pdn->m64_single_mode && (size < SZ_32M)) |
| 3199 | goto truncate_iov; |
| 3200 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3201 | res->end = res->start + size * mul - 1; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3202 | dev_dbg(&pdev->dev, " %pR\n", res); |
| 3203 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3204 | i, res, mul); |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3205 | } |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3206 | pdn->vfs_expanded = mul; |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3207 | |
| 3208 | return; |
| 3209 | |
| 3210 | truncate_iov: |
| 3211 | /* To save MMIO space, IOV BAR is truncated. */ |
| 3212 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3213 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3214 | res->flags = 0; |
| 3215 | res->end = res->start - 1; |
| 3216 | } |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3217 | } |
| 3218 | #endif /* CONFIG_PCI_IOV */ |
| 3219 | |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3220 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
| 3221 | struct resource *res) |
| 3222 | { |
| 3223 | struct pnv_phb *phb = pe->phb; |
| 3224 | struct pci_bus_region region; |
| 3225 | int index; |
| 3226 | int64_t rc; |
| 3227 | |
| 3228 | if (!res || !res->flags || res->start > res->end) |
| 3229 | return; |
| 3230 | |
| 3231 | if (res->flags & IORESOURCE_IO) { |
| 3232 | region.start = res->start - phb->ioda.io_pci_base; |
| 3233 | region.end = res->end - phb->ioda.io_pci_base; |
| 3234 | index = region.start / phb->ioda.io_segsize; |
| 3235 | |
| 3236 | while (index < phb->ioda.total_pe_num && |
| 3237 | region.start <= region.end) { |
| 3238 | phb->ioda.io_segmap[index] = pe->pe_number; |
| 3239 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3240 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); |
| 3241 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3242 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3243 | __func__, rc, index, pe->pe_number); |
| 3244 | break; |
| 3245 | } |
| 3246 | |
| 3247 | region.start += phb->ioda.io_segsize; |
| 3248 | index++; |
| 3249 | } |
| 3250 | } else if ((res->flags & IORESOURCE_MEM) && |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3251 | !pnv_pci_is_m64(phb, res)) { |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3252 | region.start = res->start - |
| 3253 | phb->hose->mem_offset[0] - |
| 3254 | phb->ioda.m32_pci_base; |
| 3255 | region.end = res->end - |
| 3256 | phb->hose->mem_offset[0] - |
| 3257 | phb->ioda.m32_pci_base; |
| 3258 | index = region.start / phb->ioda.m32_segsize; |
| 3259 | |
| 3260 | while (index < phb->ioda.total_pe_num && |
| 3261 | region.start <= region.end) { |
| 3262 | phb->ioda.m32_segmap[index] = pe->pe_number; |
| 3263 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3264 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); |
| 3265 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3266 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3267 | __func__, rc, index, pe->pe_number); |
| 3268 | break; |
| 3269 | } |
| 3270 | |
| 3271 | region.start += phb->ioda.m32_segsize; |
| 3272 | index++; |
| 3273 | } |
| 3274 | } |
| 3275 | } |
| 3276 | |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3277 | /* |
| 3278 | * This function is supposed to be called on basis of PE from top |
| 3279 | * to bottom style. So the the I/O or MMIO segment assigned to |
Masahiro Yamada | 0367105 | 2017-02-27 14:29:28 -0800 | [diff] [blame] | 3280 | * parent PE could be overridden by its child PEs if necessary. |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3281 | */ |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3282 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3283 | { |
Gavin Shan | 69d733e | 2016-05-03 15:41:28 +1000 | [diff] [blame] | 3284 | struct pci_dev *pdev; |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3285 | int i; |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3286 | |
| 3287 | /* |
| 3288 | * NOTE: We only care PCI bus based PE for now. For PCI |
| 3289 | * device based PE, for example SRIOV sensitive VF should |
| 3290 | * be figured out later. |
| 3291 | */ |
| 3292 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); |
| 3293 | |
Gavin Shan | 69d733e | 2016-05-03 15:41:28 +1000 | [diff] [blame] | 3294 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
| 3295 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
| 3296 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); |
| 3297 | |
| 3298 | /* |
| 3299 | * If the PE contains all subordinate PCI buses, the |
| 3300 | * windows of the child bridges should be mapped to |
| 3301 | * the PE as well. |
| 3302 | */ |
| 3303 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) |
| 3304 | continue; |
| 3305 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
| 3306 | pnv_ioda_setup_pe_res(pe, |
| 3307 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); |
| 3308 | } |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3309 | } |
| 3310 | |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3311 | #ifdef CONFIG_DEBUG_FS |
| 3312 | static int pnv_pci_diag_data_set(void *data, u64 val) |
| 3313 | { |
| 3314 | struct pci_controller *hose; |
| 3315 | struct pnv_phb *phb; |
| 3316 | s64 ret; |
| 3317 | |
| 3318 | if (val != 1ULL) |
| 3319 | return -EINVAL; |
| 3320 | |
| 3321 | hose = (struct pci_controller *)data; |
| 3322 | if (!hose || !hose->private_data) |
| 3323 | return -ENODEV; |
| 3324 | |
| 3325 | phb = hose->private_data; |
| 3326 | |
| 3327 | /* Retrieve the diag data from firmware */ |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3328 | ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, |
| 3329 | phb->diag_data_size); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3330 | if (ret != OPAL_SUCCESS) |
| 3331 | return -EIO; |
| 3332 | |
| 3333 | /* Print the diag data to the kernel log */ |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3334 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3335 | return 0; |
| 3336 | } |
| 3337 | |
| 3338 | DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, |
| 3339 | pnv_pci_diag_data_set, "%llu\n"); |
| 3340 | |
| 3341 | #endif /* CONFIG_DEBUG_FS */ |
| 3342 | |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3343 | static void pnv_pci_ioda_create_dbgfs(void) |
| 3344 | { |
| 3345 | #ifdef CONFIG_DEBUG_FS |
| 3346 | struct pci_controller *hose, *tmp; |
| 3347 | struct pnv_phb *phb; |
| 3348 | char name[16]; |
| 3349 | |
| 3350 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
| 3351 | phb = hose->private_data; |
| 3352 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3353 | /* Notify initialization of PHB done */ |
| 3354 | phb->initialized = 1; |
| 3355 | |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3356 | sprintf(name, "PCI%04x", hose->global_number); |
| 3357 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3358 | if (!phb->dbgfs) { |
Joe Perches | f2c2cbc | 2016-10-24 21:00:08 -0700 | [diff] [blame] | 3359 | pr_warn("%s: Error on creating debugfs on PHB#%x\n", |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3360 | __func__, hose->global_number); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3361 | continue; |
| 3362 | } |
| 3363 | |
| 3364 | debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, |
| 3365 | &pnv_pci_diag_data_fops); |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3366 | } |
| 3367 | #endif /* CONFIG_DEBUG_FS */ |
| 3368 | } |
| 3369 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 3370 | static void pnv_pci_ioda_fixup(void) |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 3371 | { |
| 3372 | pnv_pci_ioda_setup_PEs(); |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3373 | pnv_pci_ioda_setup_iommu_api(); |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3374 | pnv_pci_ioda_create_dbgfs(); |
| 3375 | |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3376 | #ifdef CONFIG_EEH |
Benjamin Herrenschmidt | b9fde58 | 2017-09-07 16:35:44 +1000 | [diff] [blame] | 3377 | pnv_eeh_post_init(); |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3378 | #endif |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 3379 | } |
| 3380 | |
Gavin Shan | 271fd03 | 2012-09-11 16:59:47 -0600 | [diff] [blame] | 3381 | /* |
| 3382 | * Returns the alignment for I/O or memory windows for P2P |
| 3383 | * bridges. That actually depends on how PEs are segmented. |
| 3384 | * For now, we return I/O or M32 segment size for PE sensitive |
| 3385 | * P2P bridges. Otherwise, the default values (4KiB for I/O, |
| 3386 | * 1MiB for memory) will be returned. |
| 3387 | * |
| 3388 | * The current PCI bus might be put into one PE, which was |
| 3389 | * create against the parent PCI bridge. For that case, we |
| 3390 | * needn't enlarge the alignment so that we can save some |
| 3391 | * resources. |
| 3392 | */ |
| 3393 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, |
| 3394 | unsigned long type) |
| 3395 | { |
| 3396 | struct pci_dev *bridge; |
| 3397 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3398 | struct pnv_phb *phb = hose->private_data; |
| 3399 | int num_pci_bridges = 0; |
| 3400 | |
| 3401 | bridge = bus->self; |
| 3402 | while (bridge) { |
| 3403 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { |
| 3404 | num_pci_bridges++; |
| 3405 | if (num_pci_bridges >= 2) |
| 3406 | return 1; |
| 3407 | } |
| 3408 | |
| 3409 | bridge = bridge->bus->self; |
| 3410 | } |
| 3411 | |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3412 | /* |
| 3413 | * We fall back to M32 if M64 isn't supported. We enforce the M64 |
| 3414 | * alignment for any 64-bit resource, PCIe doesn't care and |
| 3415 | * bridges only do 64-bit prefetchable anyway. |
| 3416 | */ |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 3417 | if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3418 | return phb->ioda.m64_segsize; |
Gavin Shan | 271fd03 | 2012-09-11 16:59:47 -0600 | [diff] [blame] | 3419 | if (type & IORESOURCE_MEM) |
| 3420 | return phb->ioda.m32_segsize; |
| 3421 | |
| 3422 | return phb->ioda.io_segsize; |
| 3423 | } |
| 3424 | |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3425 | /* |
| 3426 | * We are updating root port or the upstream port of the |
| 3427 | * bridge behind the root port with PHB's windows in order |
| 3428 | * to accommodate the changes on required resources during |
| 3429 | * PCI (slot) hotplug, which is connected to either root |
| 3430 | * port or the downstream ports of PCIe switch behind the |
| 3431 | * root port. |
| 3432 | */ |
| 3433 | static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, |
| 3434 | unsigned long type) |
| 3435 | { |
| 3436 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3437 | struct pnv_phb *phb = hose->private_data; |
| 3438 | struct pci_dev *bridge = bus->self; |
| 3439 | struct resource *r, *w; |
| 3440 | bool msi_region = false; |
| 3441 | int i; |
| 3442 | |
| 3443 | /* Check if we need apply fixup to the bridge's windows */ |
| 3444 | if (!pci_is_root_bus(bridge->bus) && |
| 3445 | !pci_is_root_bus(bridge->bus->self->bus)) |
| 3446 | return; |
| 3447 | |
| 3448 | /* Fixup the resources */ |
| 3449 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
| 3450 | r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; |
| 3451 | if (!r->flags || !r->parent) |
| 3452 | continue; |
| 3453 | |
| 3454 | w = NULL; |
| 3455 | if (r->flags & type & IORESOURCE_IO) |
| 3456 | w = &hose->io_resource; |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3457 | else if (pnv_pci_is_m64(phb, r) && |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3458 | (type & IORESOURCE_PREFETCH) && |
| 3459 | phb->ioda.m64_segsize) |
| 3460 | w = &hose->mem_resources[1]; |
| 3461 | else if (r->flags & type & IORESOURCE_MEM) { |
| 3462 | w = &hose->mem_resources[0]; |
| 3463 | msi_region = true; |
| 3464 | } |
| 3465 | |
| 3466 | r->start = w->start; |
| 3467 | r->end = w->end; |
| 3468 | |
| 3469 | /* The 64KB 32-bits MSI region shouldn't be included in |
| 3470 | * the 32-bits bridge window. Otherwise, we can see strange |
| 3471 | * issues. One of them is EEH error observed on Garrison. |
| 3472 | * |
| 3473 | * Exclude top 1MB region which is the minimal alignment of |
| 3474 | * 32-bits bridge window. |
| 3475 | */ |
| 3476 | if (msi_region) { |
| 3477 | r->end += 0x10000; |
| 3478 | r->end -= 0x100000; |
| 3479 | } |
| 3480 | } |
| 3481 | } |
| 3482 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3483 | static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
| 3484 | { |
| 3485 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3486 | struct pnv_phb *phb = hose->private_data; |
| 3487 | struct pci_dev *bridge = bus->self; |
| 3488 | struct pnv_ioda_pe *pe; |
| 3489 | bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); |
| 3490 | |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3491 | /* Extend bridge's windows if necessary */ |
| 3492 | pnv_pci_fixup_bridge_resources(bus, type); |
| 3493 | |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 3494 | /* The PE for root bus should be realized before any one else */ |
| 3495 | if (!phb->ioda.root_pe_populated) { |
| 3496 | pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); |
| 3497 | if (pe) { |
| 3498 | phb->ioda.root_pe_idx = pe->pe_number; |
| 3499 | phb->ioda.root_pe_populated = true; |
| 3500 | } |
| 3501 | } |
| 3502 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3503 | /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ |
| 3504 | if (list_empty(&bus->devices)) |
| 3505 | return; |
| 3506 | |
| 3507 | /* Reserve PEs according to used M64 resources */ |
| 3508 | if (phb->reserve_m64_pe) |
| 3509 | phb->reserve_m64_pe(bus, NULL, all); |
| 3510 | |
| 3511 | /* |
| 3512 | * Assign PE. We might run here because of partial hotplug. |
| 3513 | * For the case, we just pick up the existing PE and should |
| 3514 | * not allocate resources again. |
| 3515 | */ |
| 3516 | pe = pnv_ioda_setup_bus_PE(bus, all); |
| 3517 | if (!pe) |
| 3518 | return; |
| 3519 | |
| 3520 | pnv_ioda_setup_pe_seg(pe); |
| 3521 | switch (phb->type) { |
| 3522 | case PNV_PHB_IODA1: |
| 3523 | pnv_pci_ioda1_setup_dma_pe(phb, pe); |
| 3524 | break; |
| 3525 | case PNV_PHB_IODA2: |
| 3526 | pnv_pci_ioda2_setup_dma_pe(phb, pe); |
| 3527 | break; |
| 3528 | default: |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3529 | pr_warn("%s: No DMA for PHB#%x (type %d)\n", |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3530 | __func__, phb->hose->global_number, phb->type); |
| 3531 | } |
| 3532 | } |
| 3533 | |
Yongji Xie | 3827463 | 2017-04-10 19:58:13 +0800 | [diff] [blame] | 3534 | static resource_size_t pnv_pci_default_alignment(void) |
| 3535 | { |
| 3536 | return PAGE_SIZE; |
| 3537 | } |
| 3538 | |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3539 | #ifdef CONFIG_PCI_IOV |
| 3540 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, |
| 3541 | int resno) |
| 3542 | { |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3543 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3544 | struct pnv_phb *phb = hose->private_data; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3545 | struct pci_dn *pdn = pci_get_pdn(pdev); |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3546 | resource_size_t align; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3547 | |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3548 | /* |
| 3549 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the |
| 3550 | * SR-IOV. While from hardware perspective, the range mapped by M64 |
| 3551 | * BAR should be size aligned. |
| 3552 | * |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3553 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
| 3554 | * powernv-specific hardware restriction is gone. But if just use the |
| 3555 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with |
| 3556 | * in one segment of M64 #15, which introduces the PE conflict between |
| 3557 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is |
| 3558 | * m64_segsize. |
| 3559 | * |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3560 | * This function returns the total IOV BAR size if M64 BAR is in |
| 3561 | * Shared PE mode or just VF BAR size if not. |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3562 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
| 3563 | * M64 segment size if IOV BAR size is less. |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3564 | */ |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3565 | align = pci_iov_resource_size(pdev, resno); |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3566 | if (!pdn->vfs_expanded) |
| 3567 | return align; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3568 | if (pdn->m64_single_mode) |
| 3569 | return max(align, (resource_size_t)phb->ioda.m64_segsize); |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3570 | |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3571 | return pdn->vfs_expanded * align; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3572 | } |
| 3573 | #endif /* CONFIG_PCI_IOV */ |
| 3574 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3575 | /* Prevent enabling devices for which we couldn't properly |
| 3576 | * assign a PE |
| 3577 | */ |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3578 | bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3579 | { |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3580 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 3581 | struct pnv_phb *phb = hose->private_data; |
| 3582 | struct pci_dn *pdn; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3583 | |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3584 | /* The function is probably called while the PEs have |
| 3585 | * not be created yet. For example, resource reassignment |
| 3586 | * during PCI probe period. We just skip the check if |
| 3587 | * PEs isn't ready. |
| 3588 | */ |
| 3589 | if (!phb->initialized) |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3590 | return true; |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3591 | |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 3592 | pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3593 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3594 | return false; |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3595 | |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3596 | return true; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3597 | } |
| 3598 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3599 | static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, |
| 3600 | int num) |
| 3601 | { |
| 3602 | struct pnv_ioda_pe *pe = container_of(table_group, |
| 3603 | struct pnv_ioda_pe, table_group); |
| 3604 | struct pnv_phb *phb = pe->phb; |
| 3605 | unsigned int idx; |
| 3606 | long rc; |
| 3607 | |
| 3608 | pe_info(pe, "Removing DMA window #%d\n", num); |
| 3609 | for (idx = 0; idx < phb->ioda.dma32_count; idx++) { |
| 3610 | if (phb->ioda.dma32_segmap[idx] != pe->pe_number) |
| 3611 | continue; |
| 3612 | |
| 3613 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, |
| 3614 | idx, 0, 0ul, 0ul, 0ul); |
| 3615 | if (rc != OPAL_SUCCESS) { |
| 3616 | pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", |
| 3617 | rc, idx); |
| 3618 | return rc; |
| 3619 | } |
| 3620 | |
| 3621 | phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; |
| 3622 | } |
| 3623 | |
| 3624 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); |
| 3625 | return OPAL_SUCCESS; |
| 3626 | } |
| 3627 | |
| 3628 | static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) |
| 3629 | { |
| 3630 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 3631 | struct iommu_table *tbl = pe->table_group.tables[0]; |
| 3632 | int64_t rc; |
| 3633 | |
| 3634 | if (!weight) |
| 3635 | return; |
| 3636 | |
| 3637 | rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); |
| 3638 | if (rc != OPAL_SUCCESS) |
| 3639 | return; |
| 3640 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 3641 | pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3642 | if (pe->table_group.group) { |
| 3643 | iommu_group_put(pe->table_group.group); |
| 3644 | WARN_ON(pe->table_group.group); |
| 3645 | } |
| 3646 | |
| 3647 | free_pages(tbl->it_base, get_order(tbl->it_size << 3)); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 3648 | iommu_tce_table_put(tbl); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3649 | } |
| 3650 | |
| 3651 | static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) |
| 3652 | { |
| 3653 | struct iommu_table *tbl = pe->table_group.tables[0]; |
| 3654 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 3655 | #ifdef CONFIG_IOMMU_API |
| 3656 | int64_t rc; |
| 3657 | #endif |
| 3658 | |
| 3659 | if (!weight) |
| 3660 | return; |
| 3661 | |
| 3662 | #ifdef CONFIG_IOMMU_API |
| 3663 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
| 3664 | if (rc) |
| 3665 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); |
| 3666 | #endif |
| 3667 | |
| 3668 | pnv_pci_ioda2_set_bypass(pe, false); |
| 3669 | if (pe->table_group.group) { |
| 3670 | iommu_group_put(pe->table_group.group); |
| 3671 | WARN_ON(pe->table_group.group); |
| 3672 | } |
| 3673 | |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 3674 | iommu_tce_table_put(tbl); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3675 | } |
| 3676 | |
| 3677 | static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, |
| 3678 | unsigned short win, |
| 3679 | unsigned int *map) |
| 3680 | { |
| 3681 | struct pnv_phb *phb = pe->phb; |
| 3682 | int idx; |
| 3683 | int64_t rc; |
| 3684 | |
| 3685 | for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { |
| 3686 | if (map[idx] != pe->pe_number) |
| 3687 | continue; |
| 3688 | |
| 3689 | if (win == OPAL_M64_WINDOW_TYPE) |
| 3690 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3691 | phb->ioda.reserved_pe_idx, win, |
| 3692 | idx / PNV_IODA1_M64_SEGS, |
| 3693 | idx % PNV_IODA1_M64_SEGS); |
| 3694 | else |
| 3695 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3696 | phb->ioda.reserved_pe_idx, win, 0, idx); |
| 3697 | |
| 3698 | if (rc != OPAL_SUCCESS) |
| 3699 | pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", |
| 3700 | rc, win, idx); |
| 3701 | |
| 3702 | map[idx] = IODA_INVALID_PE; |
| 3703 | } |
| 3704 | } |
| 3705 | |
| 3706 | static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) |
| 3707 | { |
| 3708 | struct pnv_phb *phb = pe->phb; |
| 3709 | |
| 3710 | if (phb->type == PNV_PHB_IODA1) { |
| 3711 | pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, |
| 3712 | phb->ioda.io_segmap); |
| 3713 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, |
| 3714 | phb->ioda.m32_segmap); |
| 3715 | pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, |
| 3716 | phb->ioda.m64_segmap); |
| 3717 | } else if (phb->type == PNV_PHB_IODA2) { |
| 3718 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, |
| 3719 | phb->ioda.m32_segmap); |
| 3720 | } |
| 3721 | } |
| 3722 | |
| 3723 | static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) |
| 3724 | { |
| 3725 | struct pnv_phb *phb = pe->phb; |
| 3726 | struct pnv_ioda_pe *slave, *tmp; |
| 3727 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3728 | list_del(&pe->list); |
| 3729 | switch (phb->type) { |
| 3730 | case PNV_PHB_IODA1: |
| 3731 | pnv_pci_ioda1_release_pe_dma(pe); |
| 3732 | break; |
| 3733 | case PNV_PHB_IODA2: |
| 3734 | pnv_pci_ioda2_release_pe_dma(pe); |
| 3735 | break; |
| 3736 | default: |
| 3737 | WARN_ON(1); |
| 3738 | } |
| 3739 | |
| 3740 | pnv_ioda_release_pe_seg(pe); |
| 3741 | pnv_ioda_deconfigure_pe(pe->phb, pe); |
Gavin Shan | b314427 | 2016-09-06 14:16:44 +1000 | [diff] [blame] | 3742 | |
| 3743 | /* Release slave PEs in the compound PE */ |
| 3744 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 3745 | list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { |
| 3746 | list_del(&slave->list); |
| 3747 | pnv_ioda_free_pe(slave); |
| 3748 | } |
| 3749 | } |
| 3750 | |
Gavin Shan | 6eaed16 | 2016-09-13 16:40:24 +1000 | [diff] [blame] | 3751 | /* |
| 3752 | * The PE for root bus can be removed because of hotplug in EEH |
| 3753 | * recovery for fenced PHB error. We need to mark the PE dead so |
| 3754 | * that it can be populated again in PCI hot add path. The PE |
| 3755 | * shouldn't be destroyed as it's the global reserved resource. |
| 3756 | */ |
| 3757 | if (phb->ioda.root_pe_populated && |
| 3758 | phb->ioda.root_pe_idx == pe->pe_number) |
| 3759 | phb->ioda.root_pe_populated = false; |
| 3760 | else |
| 3761 | pnv_ioda_free_pe(pe); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3762 | } |
| 3763 | |
| 3764 | static void pnv_pci_release_device(struct pci_dev *pdev) |
| 3765 | { |
| 3766 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3767 | struct pnv_phb *phb = hose->private_data; |
| 3768 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 3769 | struct pnv_ioda_pe *pe; |
| 3770 | |
| 3771 | if (pdev->is_virtfn) |
| 3772 | return; |
| 3773 | |
| 3774 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 3775 | return; |
| 3776 | |
Gavin Shan | 29bf282 | 2016-09-06 16:34:01 +1000 | [diff] [blame] | 3777 | /* |
| 3778 | * PCI hotplug can happen as part of EEH error recovery. The @pdn |
| 3779 | * isn't removed and added afterwards in this scenario. We should |
| 3780 | * set the PE number in @pdn to an invalid one. Otherwise, the PE's |
| 3781 | * device count is decreased on removing devices while failing to |
| 3782 | * be increased on adding devices. It leads to unbalanced PE's device |
| 3783 | * count and eventually make normal PCI hotplug path broken. |
| 3784 | */ |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3785 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
Gavin Shan | 29bf282 | 2016-09-06 16:34:01 +1000 | [diff] [blame] | 3786 | pdn->pe_number = IODA_INVALID_PE; |
| 3787 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3788 | WARN_ON(--pe->device_count < 0); |
| 3789 | if (pe->device_count == 0) |
| 3790 | pnv_ioda_release_pe(pe); |
| 3791 | } |
| 3792 | |
Michael Neuling | 7a8e6bb | 2015-05-27 16:06:59 +1000 | [diff] [blame] | 3793 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
Benjamin Herrenschmidt | 73ed148 | 2013-05-10 16:59:18 +1000 | [diff] [blame] | 3794 | { |
Michael Neuling | 7a8e6bb | 2015-05-27 16:06:59 +1000 | [diff] [blame] | 3795 | struct pnv_phb *phb = hose->private_data; |
| 3796 | |
Gavin Shan | d1a85ee | 2014-09-30 12:39:05 +1000 | [diff] [blame] | 3797 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
Benjamin Herrenschmidt | 73ed148 | 2013-05-10 16:59:18 +1000 | [diff] [blame] | 3798 | OPAL_ASSERT_RESET); |
| 3799 | } |
| 3800 | |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3801 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3802 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
| 3803 | .dma_bus_setup = pnv_pci_dma_bus_setup, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3804 | #ifdef CONFIG_PCI_MSI |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3805 | .setup_msi_irqs = pnv_setup_msi_irqs, |
| 3806 | .teardown_msi_irqs = pnv_teardown_msi_irqs, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3807 | #endif |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3808 | .enable_device_hook = pnv_pci_enable_device_hook, |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3809 | .release_device = pnv_pci_release_device, |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3810 | .window_alignment = pnv_pci_window_alignment, |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3811 | .setup_bridge = pnv_pci_setup_bridge, |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3812 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3813 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, |
| 3814 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, |
| 3815 | .shutdown = pnv_pci_ioda_shutdown, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3816 | }; |
| 3817 | |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 3818 | static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) |
| 3819 | { |
| 3820 | dev_err_once(&npdev->dev, |
| 3821 | "%s operation unsupported for NVLink devices\n", |
| 3822 | __func__); |
| 3823 | return -EPERM; |
| 3824 | } |
| 3825 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3826 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3827 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3828 | #ifdef CONFIG_PCI_MSI |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3829 | .setup_msi_irqs = pnv_setup_msi_irqs, |
| 3830 | .teardown_msi_irqs = pnv_teardown_msi_irqs, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3831 | #endif |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3832 | .enable_device_hook = pnv_pci_enable_device_hook, |
| 3833 | .window_alignment = pnv_pci_window_alignment, |
| 3834 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3835 | .dma_set_mask = pnv_npu_dma_set_mask, |
| 3836 | .shutdown = pnv_pci_ioda_shutdown, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3837 | }; |
| 3838 | |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 3839 | static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = { |
| 3840 | .enable_device_hook = pnv_pci_enable_device_hook, |
| 3841 | .window_alignment = pnv_pci_window_alignment, |
| 3842 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3843 | .shutdown = pnv_pci_ioda_shutdown, |
| 3844 | }; |
| 3845 | |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3846 | #ifdef CONFIG_CXL_BASE |
| 3847 | const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { |
| 3848 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
| 3849 | .dma_bus_setup = pnv_pci_dma_bus_setup, |
Ian Munsie | a2f67d5 | 2016-07-14 07:17:10 +1000 | [diff] [blame] | 3850 | #ifdef CONFIG_PCI_MSI |
| 3851 | .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, |
| 3852 | .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, |
| 3853 | #endif |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3854 | .enable_device_hook = pnv_cxl_enable_device_hook, |
| 3855 | .disable_device = pnv_cxl_disable_device, |
| 3856 | .release_device = pnv_pci_release_device, |
| 3857 | .window_alignment = pnv_pci_window_alignment, |
| 3858 | .setup_bridge = pnv_pci_setup_bridge, |
| 3859 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3860 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, |
| 3861 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, |
| 3862 | .shutdown = pnv_pci_ioda_shutdown, |
| 3863 | }; |
| 3864 | #endif |
| 3865 | |
Anton Blanchard | e51df2c | 2014-08-20 08:55:18 +1000 | [diff] [blame] | 3866 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
| 3867 | u64 hub_id, int ioda_type) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3868 | { |
| 3869 | struct pci_controller *hose; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3870 | struct pnv_phb *phb; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3871 | unsigned long size, m64map_off, m32map_off, pemap_off; |
| 3872 | unsigned long iomap_off = 0, dma32map_off = 0; |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 3873 | struct resource r; |
Alistair Popple | c681b93 | 2013-09-23 12:04:57 +1000 | [diff] [blame] | 3874 | const __be64 *prop64; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3875 | const __be32 *prop32; |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3876 | int len; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3877 | unsigned int segno; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3878 | u64 phb_id; |
| 3879 | void *aux; |
| 3880 | long rc; |
| 3881 | |
Benjamin Herrenschmidt | 08a45b3 | 2016-07-08 16:37:17 +1000 | [diff] [blame] | 3882 | if (!of_device_is_available(np)) |
| 3883 | return; |
| 3884 | |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3885 | pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3886 | |
| 3887 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); |
| 3888 | if (!prop64) { |
| 3889 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); |
| 3890 | return; |
| 3891 | } |
| 3892 | phb_id = be64_to_cpup(prop64); |
| 3893 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); |
| 3894 | |
Markus Elfring | a0828cf | 2017-01-19 17:15:30 +0100 | [diff] [blame] | 3895 | phb = memblock_virt_alloc(sizeof(*phb), 0); |
Gavin Shan | 58d714e | 2013-07-31 16:47:00 +0800 | [diff] [blame] | 3896 | |
| 3897 | /* Allocate PCI controller */ |
Gavin Shan | 58d714e | 2013-07-31 16:47:00 +0800 | [diff] [blame] | 3898 | phb->hose = hose = pcibios_alloc_controller(np); |
| 3899 | if (!phb->hose) { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3900 | pr_err(" Can't allocate PCI controller for %pOF\n", |
| 3901 | np); |
Michael Ellerman | e39f223f | 2014-11-18 16:47:35 +1100 | [diff] [blame] | 3902 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3903 | return; |
| 3904 | } |
| 3905 | |
| 3906 | spin_lock_init(&phb->lock); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3907 | prop32 = of_get_property(np, "bus-range", &len); |
| 3908 | if (prop32 && len == 8) { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3909 | hose->first_busno = be32_to_cpu(prop32[0]); |
| 3910 | hose->last_busno = be32_to_cpu(prop32[1]); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3911 | } else { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3912 | pr_warn(" Broken <bus-range> on %pOF\n", np); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3913 | hose->first_busno = 0; |
| 3914 | hose->last_busno = 0xff; |
| 3915 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3916 | hose->private_data = phb; |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3917 | phb->hub_id = hub_id; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3918 | phb->opal_id = phb_id; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3919 | phb->type = ioda_type; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 3920 | mutex_init(&phb->ioda.pe_alloc_mutex); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3921 | |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 3922 | /* Detect specific models for error handling */ |
| 3923 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) |
| 3924 | phb->model = PNV_PHB_MODEL_P7IOC; |
Benjamin Herrenschmidt | f3d40c2 | 2013-05-04 14:24:32 +0000 | [diff] [blame] | 3925 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3926 | phb->model = PNV_PHB_MODEL_PHB3; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3927 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
| 3928 | phb->model = PNV_PHB_MODEL_NPU; |
Alistair Popple | 616badd | 2017-01-10 15:41:44 +1100 | [diff] [blame] | 3929 | else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) |
| 3930 | phb->model = PNV_PHB_MODEL_NPU2; |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 3931 | else |
| 3932 | phb->model = PNV_PHB_MODEL_UNKNOWN; |
| 3933 | |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3934 | /* Initialize diagnostic data buffer */ |
| 3935 | prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); |
| 3936 | if (prop32) |
| 3937 | phb->diag_data_size = be32_to_cpup(prop32); |
| 3938 | else |
| 3939 | phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; |
| 3940 | |
| 3941 | phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); |
| 3942 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3943 | /* Parse 32-bit and IO ranges (if any) */ |
Gavin Shan | 2f1ec02 | 2013-07-31 16:47:02 +0800 | [diff] [blame] | 3944 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3945 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3946 | /* Get registers */ |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 3947 | if (!of_address_to_resource(np, 0, &r)) { |
| 3948 | phb->regs_phys = r.start; |
| 3949 | phb->regs = ioremap(r.start, resource_size(&r)); |
| 3950 | if (phb->regs == NULL) |
| 3951 | pr_err(" Failed to map registers !\n"); |
| 3952 | } |
Gavin Shan | 577c8c8 | 2016-05-20 16:41:28 +1000 | [diff] [blame] | 3953 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3954 | /* Initialize more IODA stuff */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3955 | phb->ioda.total_pe_num = 1; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3956 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
Gavin Shan | 36954dc | 2013-11-04 16:32:47 +0800 | [diff] [blame] | 3957 | if (prop32) |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3958 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
Gavin Shan | 36954dc | 2013-11-04 16:32:47 +0800 | [diff] [blame] | 3959 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
| 3960 | if (prop32) |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3961 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3962 | |
Gavin Shan | c127562 | 2016-05-20 16:41:29 +1000 | [diff] [blame] | 3963 | /* Invalidate RID to PE# mapping */ |
| 3964 | for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) |
| 3965 | phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; |
| 3966 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3967 | /* Parse 64-bit MMIO range */ |
| 3968 | pnv_ioda_parse_m64_window(phb); |
| 3969 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3970 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3971 | /* FW Has already off top 64k of M32 space (MSI space) */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3972 | phb->ioda.m32_size += 0x10000; |
| 3973 | |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3974 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
Benjamin Herrenschmidt | 3fd47f0 | 2013-05-06 13:40:40 +1000 | [diff] [blame] | 3975 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3976 | phb->ioda.io_size = hose->pci_io_size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3977 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3978 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
| 3979 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3980 | /* Calculate how many 32-bit TCE segments we have */ |
| 3981 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
| 3982 | PNV_IODA1_DMA32_SEGSIZE; |
| 3983 | |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3984 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
Alexey Kardashevskiy | 92a8675 | 2016-05-12 15:47:09 +1000 | [diff] [blame] | 3985 | size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, |
| 3986 | sizeof(unsigned long)); |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 3987 | m64map_off = size; |
| 3988 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3989 | m32map_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3990 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3991 | if (phb->type == PNV_PHB_IODA1) { |
| 3992 | iomap_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3993 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3994 | dma32map_off = size; |
| 3995 | size += phb->ioda.dma32_count * |
| 3996 | sizeof(phb->ioda.dma32_segmap[0]); |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3997 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3998 | pemap_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3999 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
Michael Ellerman | e39f223f | 2014-11-18 16:47:35 +1100 | [diff] [blame] | 4000 | aux = memblock_virt_alloc(size, 0); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4001 | phb->ioda.pe_alloc = aux; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 4002 | phb->ioda.m64_segmap = aux + m64map_off; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4003 | phb->ioda.m32_segmap = aux + m32map_off; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 4004 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
| 4005 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 4006 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 4007 | } |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 4008 | if (phb->type == PNV_PHB_IODA1) { |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 4009 | phb->ioda.io_segmap = aux + iomap_off; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 4010 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
| 4011 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 4012 | |
| 4013 | phb->ioda.dma32_segmap = aux + dma32map_off; |
| 4014 | for (segno = 0; segno < phb->ioda.dma32_count; segno++) |
| 4015 | phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 4016 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4017 | phb->ioda.pe_array = aux + pemap_off; |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 4018 | |
| 4019 | /* |
| 4020 | * Choose PE number for root bus, which shouldn't have |
| 4021 | * M64 resources consumed by its child devices. To pick |
| 4022 | * the PE number adjacent to the reserved one if possible. |
| 4023 | */ |
| 4024 | pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); |
| 4025 | if (phb->ioda.reserved_pe_idx == 0) { |
| 4026 | phb->ioda.root_pe_idx = 1; |
| 4027 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); |
| 4028 | } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { |
| 4029 | phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; |
| 4030 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); |
| 4031 | } else { |
| 4032 | phb->ioda.root_pe_idx = IODA_INVALID_PE; |
| 4033 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4034 | |
| 4035 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 4036 | mutex_init(&phb->ioda.pe_list_mutex); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4037 | |
| 4038 | /* Calculate how many 32-bit TCE segments we have */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 4039 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 4040 | PNV_IODA1_DMA32_SEGSIZE; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4041 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4042 | #if 0 /* We should really do that ... */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4043 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
| 4044 | window_type, |
| 4045 | window_num, |
| 4046 | starting_real_address, |
| 4047 | starting_pci_address, |
| 4048 | segment_size); |
| 4049 | #endif |
| 4050 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4051 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 4052 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4053 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
| 4054 | if (phb->ioda.m64_size) |
| 4055 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", |
| 4056 | phb->ioda.m64_size, phb->ioda.m64_segsize); |
| 4057 | if (phb->ioda.io_size) |
| 4058 | pr_info(" IO: 0x%x [segment=0x%x]\n", |
| 4059 | phb->ioda.io_size, phb->ioda.io_segsize); |
| 4060 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4061 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4062 | phb->hose->ops = &pnv_pci_ops; |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 4063 | phb->get_pe_state = pnv_ioda_get_pe_state; |
| 4064 | phb->freeze_pe = pnv_ioda_freeze_pe; |
| 4065 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4066 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4067 | /* Setup MSI support */ |
| 4068 | pnv_pci_init_ioda_msis(phb); |
| 4069 | |
Gavin Shan | c40a421 | 2012-08-20 03:49:20 +0000 | [diff] [blame] | 4070 | /* |
| 4071 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here |
| 4072 | * to let the PCI core do resource assignment. It's supposed |
| 4073 | * that the PCI core will do correct I/O and MMIO alignment |
| 4074 | * for the P2P bridge bars so that each PCI bus (excluding |
| 4075 | * the child P2P bridges) can form individual PE. |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4076 | */ |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 4077 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4078 | |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 4079 | switch (phb->type) { |
| 4080 | case PNV_PHB_NPU_NVLINK: |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4081 | hose->controller_ops = pnv_npu_ioda_controller_ops; |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 4082 | break; |
| 4083 | case PNV_PHB_NPU_OCAPI: |
| 4084 | hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; |
| 4085 | break; |
| 4086 | default: |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 4087 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4088 | hose->controller_ops = pnv_pci_ioda_controller_ops; |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 4089 | } |
Michael Ellerman | ad30cb9 | 2015-04-14 09:29:23 +1000 | [diff] [blame] | 4090 | |
Yongji Xie | 3827463 | 2017-04-10 19:58:13 +0800 | [diff] [blame] | 4091 | ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; |
| 4092 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 4093 | #ifdef CONFIG_PCI_IOV |
| 4094 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 4095 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
Bryant G. Ly | 988fc3b | 2017-11-09 08:00:33 -0600 | [diff] [blame] | 4096 | ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable; |
| 4097 | ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable; |
Michael Ellerman | ad30cb9 | 2015-04-14 09:29:23 +1000 | [diff] [blame] | 4098 | #endif |
| 4099 | |
Gavin Shan | c40a421 | 2012-08-20 03:49:20 +0000 | [diff] [blame] | 4100 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4101 | |
| 4102 | /* Reset IODA tables to a clean state */ |
Gavin Shan | d1a85ee | 2014-09-30 12:39:05 +1000 | [diff] [blame] | 4103 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4104 | if (rc) |
Joe Perches | f2c2cbc | 2016-10-24 21:00:08 -0700 | [diff] [blame] | 4105 | pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc); |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4106 | |
Andrew Donnellan | 6060e9e | 2016-09-16 20:39:44 +1000 | [diff] [blame] | 4107 | /* |
| 4108 | * If we're running in kdump kernel, the previous kernel never |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4109 | * shutdown PCI devices correctly. We already got IODA table |
| 4110 | * cleaned out. So we have to issue PHB reset to stop all PCI |
Guilherme G. Piccoli | 45baee1 | 2017-11-17 16:58:59 -0200 | [diff] [blame] | 4111 | * transactions from previous kernel. The ppc_pci_reset_phbs |
| 4112 | * kernel parameter will force this reset too. |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4113 | */ |
Guilherme G. Piccoli | 45baee1 | 2017-11-17 16:58:59 -0200 | [diff] [blame] | 4114 | if (is_kdump_kernel() || pci_reset_phbs) { |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4115 | pr_info(" Issue PHB reset ...\n"); |
Gavin Shan | cadf364 | 2015-02-16 14:45:47 +1100 | [diff] [blame] | 4116 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
| 4117 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4118 | } |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4119 | |
Gavin Shan | 9e9e893 | 2014-11-12 13:36:05 +1100 | [diff] [blame] | 4120 | /* Remove M64 resource if we can't configure it successfully */ |
| 4121 | if (!phb->init_m64 || phb->init_m64(phb)) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4122 | hose->mem_resources[1].flags = 0; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4123 | } |
| 4124 | |
Bjorn Helgaas | 6797500 | 2013-07-02 12:20:03 -0600 | [diff] [blame] | 4125 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4126 | { |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 4127 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4128 | } |
| 4129 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4130 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
| 4131 | { |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 4132 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK); |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4133 | } |
| 4134 | |
Frederic Barrat | 7f2c39e | 2018-01-23 12:31:36 +0100 | [diff] [blame] | 4135 | void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np) |
| 4136 | { |
| 4137 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4138 | } |
| 4139 | |
Andrew Donnellan | 228c2f4 | 2018-01-23 12:31:37 +0100 | [diff] [blame] | 4140 | static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev) |
| 4141 | { |
| 4142 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 4143 | struct pnv_phb *phb = hose->private_data; |
| 4144 | |
| 4145 | if (!machine_is(powernv)) |
| 4146 | return; |
| 4147 | |
| 4148 | if (phb->type == PNV_PHB_NPU_OCAPI) |
| 4149 | dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; |
| 4150 | } |
| 4151 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup); |
| 4152 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4153 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
| 4154 | { |
| 4155 | struct device_node *phbn; |
| 4156 | const __be64 *prop64; |
| 4157 | u64 hub_id; |
| 4158 | |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 4159 | pr_info("Probing IODA IO-Hub %pOF\n", np); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4160 | |
| 4161 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); |
| 4162 | if (!prop64) { |
| 4163 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); |
| 4164 | return; |
| 4165 | } |
| 4166 | hub_id = be64_to_cpup(prop64); |
| 4167 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); |
| 4168 | |
| 4169 | /* Count child PHBs */ |
| 4170 | for_each_child_of_node(np, phbn) { |
| 4171 | /* Look for IODA1 PHBs */ |
| 4172 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) |
| 4173 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
| 4174 | } |
| 4175 | } |