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Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040019#include <linux/module.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070020#include <asm/unaligned.h>
21
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070022#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040023#include "hw-ops.h"
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070024#include "rc.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040025#include "ar9003_mac.h"
Sujith Manoharanf4701b52012-02-22 12:41:18 +053026#include "ar9003_mci.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070027
Sujithcbe61d82009-02-09 13:27:12 +053028static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070029
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040030MODULE_AUTHOR("Atheros Communications");
31MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33MODULE_LICENSE("Dual BSD/GPL");
34
35static int __init ath9k_init(void)
36{
37 return 0;
38}
39module_init(ath9k_init);
40
41static void __exit ath9k_exit(void)
42{
43 return;
44}
45module_exit(ath9k_exit);
46
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040047/* Private hardware callbacks */
48
49static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50{
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52}
53
54static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57}
58
Luis R. Rodriguez64773962010-04-15 17:38:17 -040059static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
60 struct ath9k_channel *chan)
61{
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63}
64
Luis R. Rodriguez991312d2010-04-15 17:39:05 -040065static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66{
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 return;
69
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71}
72
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040073static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74{
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80}
81
Sujithf1dc5602008-10-29 10:16:30 +053082/********************/
83/* Helper Functions */
84/********************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070085
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020086static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +053087{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070088 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020089 struct ath_common *common = ath9k_hw_common(ah);
90 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +053091
Felix Fietkau087b6ff2011-07-09 11:12:49 +070092 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
93 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
94 clockrate = 117;
95 else if (!ah->curchan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020096 clockrate = ATH9K_CLOCK_RATE_CCK;
97 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
99 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
100 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -0400101 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200102 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
103
104 if (conf_is_ht40(conf))
105 clockrate *= 2;
106
Felix Fietkau906c7202011-07-09 11:12:48 +0700107 if (ah->curchan) {
108 if (IS_CHAN_HALF_RATE(ah->curchan))
109 clockrate /= 2;
110 if (IS_CHAN_QUARTER_RATE(ah->curchan))
111 clockrate /= 4;
112 }
113
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200114 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530115}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700116
Sujithcbe61d82009-02-09 13:27:12 +0530117static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +0530118{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200119 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +0530120
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200121 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530122}
123
Sujith0caa7b12009-02-16 13:23:20 +0530124bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700125{
126 int i;
127
Sujith0caa7b12009-02-16 13:23:20 +0530128 BUG_ON(timeout < AH_TIME_QUANTUM);
129
130 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700131 if ((REG_READ(ah, reg) & mask) == val)
132 return true;
133
134 udelay(AH_TIME_QUANTUM);
135 }
Sujith04bd46382008-11-28 22:18:05 +0530136
Joe Perchesd2182b62011-12-15 14:55:53 -0800137 ath_dbg(ath9k_hw_common(ah), ANY,
Joe Perches226afe62010-12-02 19:12:37 -0800138 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
139 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +0530140
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700141 return false;
142}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400143EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700144
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100145void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
146 int column, unsigned int *writecnt)
147{
148 int r;
149
150 ENABLE_REGWRITE_BUFFER(ah);
151 for (r = 0; r < array->ia_rows; r++) {
152 REG_WRITE(ah, INI_RA(array, r, 0),
153 INI_RA(array, r, column));
154 DO_DELAY(*writecnt);
155 }
156 REGWRITE_BUFFER_FLUSH(ah);
157}
158
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700159u32 ath9k_hw_reverse_bits(u32 val, u32 n)
160{
161 u32 retval;
162 int i;
163
164 for (i = 0, retval = 0; i < n; i++) {
165 retval = (retval << 1) | (val & 1);
166 val >>= 1;
167 }
168 return retval;
169}
170
Sujithcbe61d82009-02-09 13:27:12 +0530171u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100172 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530173 u32 frameLen, u16 rateix,
174 bool shortPreamble)
175{
176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530177
178 if (kbps == 0)
179 return 0;
180
Felix Fietkau545750d2009-11-23 22:21:01 +0100181 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530182 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100184 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
Sujith46d14a52008-11-18 09:08:13 +0530189 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
Joe Perches38002762010-12-02 19:12:36 -0800214 ath_err(ath9k_hw_common(ah),
215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530216 txTime = 0;
217 break;
218 }
219
220 return txTime;
221}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400222EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530223
Sujithcbe61d82009-02-09 13:27:12 +0530224void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
227{
228 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530229
230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
234 }
235
236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
246
247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700249 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530250 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530252}
253
254/******************/
255/* Chip Revisions */
256/******************/
257
Sujithcbe61d82009-02-09 13:27:12 +0530258static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530259{
260 u32 val;
261
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530262 switch (ah->hw_version.devid) {
263 case AR5416_AR9100_DEVID:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
265 break;
Gabor Juhos37625612011-06-21 11:23:23 +0200266 case AR9300_DEVID_AR9330:
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
268 if (ah->get_mac_revision) {
269 ah->hw_version.macRev = ah->get_mac_revision();
270 } else {
271 val = REG_READ(ah, AR_SREV);
272 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
273 }
274 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530275 case AR9300_DEVID_AR9340:
276 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
277 val = REG_READ(ah, AR_SREV);
278 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
279 return;
280 }
281
Sujithf1dc5602008-10-29 10:16:30 +0530282 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
283
284 if (val == 0xFF) {
285 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530286 ah->hw_version.macVersion =
287 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
288 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530289
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530290 if (AR_SREV_9462(ah))
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530291 ah->is_pciexpress = true;
292 else
293 ah->is_pciexpress = (val &
294 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530295 } else {
296 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530297 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530298
Sujithd535a422009-02-09 13:27:06 +0530299 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530300
Sujithd535a422009-02-09 13:27:06 +0530301 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530302 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530303 }
304}
305
Sujithf1dc5602008-10-29 10:16:30 +0530306/************************************/
307/* HW Attach, Detach, Init Routines */
308/************************************/
309
Sujithcbe61d82009-02-09 13:27:12 +0530310static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530311{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100312 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530313 return;
314
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
324
325 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
326}
327
Stanislaw Gruszkad4930082011-07-29 15:59:08 +0200328static void ath9k_hw_aspm_init(struct ath_hw *ah)
329{
330 struct ath_common *common = ath9k_hw_common(ah);
331
332 if (common->bus_ops->aspm_init)
333 common->bus_ops->aspm_init(common);
334}
335
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400336/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530337static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530338{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700339 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400340 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530341 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800342 static const u32 patternData[4] = {
343 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
344 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400345 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530346
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400347 if (!AR_SREV_9300_20_OR_LATER(ah)) {
348 loop_max = 2;
349 regAddr[1] = AR_PHY_BASE + (8 << 2);
350 } else
351 loop_max = 1;
352
353 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530354 u32 addr = regAddr[i];
355 u32 wrData, rdData;
356
357 regHold[i] = REG_READ(ah, addr);
358 for (j = 0; j < 0x100; j++) {
359 wrData = (j << 16) | j;
360 REG_WRITE(ah, addr, wrData);
361 rdData = REG_READ(ah, addr);
362 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800363 ath_err(common,
364 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
365 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530366 return false;
367 }
368 }
369 for (j = 0; j < 4; j++) {
370 wrData = patternData[j];
371 REG_WRITE(ah, addr, wrData);
372 rdData = REG_READ(ah, addr);
373 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800374 ath_err(common,
375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
376 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530377 return false;
378 }
379 }
380 REG_WRITE(ah, regAddr[i], regHold[i]);
381 }
382 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530383
Sujithf1dc5602008-10-29 10:16:30 +0530384 return true;
385}
386
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700387static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700388{
389 int i;
390
Sujith2660b812009-02-09 13:27:26 +0530391 ah->config.dma_beacon_response_time = 2;
392 ah->config.sw_beacon_response_time = 10;
393 ah->config.additional_swba_backoff = 0;
394 ah->config.ack_6mb = 0x0;
395 ah->config.cwm_ignore_extcca = 0;
Sujith2660b812009-02-09 13:27:26 +0530396 ah->config.pcie_clock_req = 0;
Sujith2660b812009-02-09 13:27:26 +0530397 ah->config.pcie_waen = 0;
398 ah->config.analog_shiftreg = 1;
Luis R. Rodriguez03c72512010-06-12 00:33:46 -0400399 ah->config.enable_ani = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700400
401 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530402 ah->config.spurchans[i][0] = AR_NO_SPUR;
403 ah->config.spurchans[i][1] = AR_NO_SPUR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700404 }
405
Luis R. Rodriguez6f481012011-01-20 17:47:39 -0800406 /* PAPRD needs some more work to be enabled */
407 ah->config.paprd_disable = 1;
408
Sujith0ce024c2009-12-14 14:57:00 +0530409 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez6a0ec302010-06-21 18:38:49 -0400410 ah->config.pcieSerDesWrite = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400411
412 /*
413 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
414 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
415 * This means we use it for all AR5416 devices, and the few
416 * minor PCI AR9280 devices out there.
417 *
418 * Serialization is required because these devices do not handle
419 * well the case of two concurrent reads/writes due to the latency
420 * involved. During one read/write another read/write can be issued
421 * on another CPU while the previous read/write may still be working
422 * on our hardware, if we hit this case the hardware poops in a loop.
423 * We prevent this by serializing reads and writes.
424 *
425 * This issue is not present on PCI-Express devices or pre-AR5416
426 * devices (legacy, 802.11abg).
427 */
428 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700429 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700430}
431
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700432static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700433{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700434 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
435
436 regulatory->country_code = CTRY_DEFAULT;
437 regulatory->power_limit = MAX_RATE_POWER;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700438
Sujithd535a422009-02-09 13:27:06 +0530439 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530440 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700441
Sujith2660b812009-02-09 13:27:26 +0530442 ah->atim_window = 0;
Felix Fietkau16f24112010-06-12 17:22:32 +0200443 ah->sta_id1_defaults =
444 AR_STA_ID1_CRPT_MIC_ENABLE |
445 AR_STA_ID1_MCAST_KSRCH;
Felix Fietkauf1717602011-03-19 13:55:41 +0100446 if (AR_SREV_9100(ah))
447 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
Sujith2660b812009-02-09 13:27:26 +0530448 ah->enable_32kHz_clock = DONT_USE_32KHZ;
Rajkumar Manoharane3f2acc2011-08-27 11:22:59 +0530449 ah->slottime = ATH9K_SLOT_TIME_9;
Sujith2660b812009-02-09 13:27:26 +0530450 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200451 ah->power_mode = ATH9K_PM_UNDEFINED;
Felix Fietkau8efa7a82012-03-14 16:40:23 +0100452 ah->htc_reset_init = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700453}
454
Sujithcbe61d82009-02-09 13:27:12 +0530455static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700456{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700457 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530458 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700459 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530460 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800461 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700462
Sujithf1dc5602008-10-29 10:16:30 +0530463 sum = 0;
464 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400465 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530466 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700467 common->macaddr[2 * i] = eeval >> 8;
468 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700469 }
Sujithd8baa932009-03-30 15:28:25 +0530470 if (sum == 0 || sum == 0xffff * 3)
Sujithf1dc5602008-10-29 10:16:30 +0530471 return -EADDRNOTAVAIL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700472
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700473 return 0;
474}
475
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700476static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700477{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530478 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700479 int ecode;
480
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530481 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530482 if (!ath9k_hw_chip_test(ah))
483 return -ENODEV;
484 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700485
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400486 if (!AR_SREV_9300_20_OR_LATER(ah)) {
487 ecode = ar9002_hw_rf_claim(ah);
488 if (ecode != 0)
489 return ecode;
490 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700491
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700492 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700493 if (ecode != 0)
494 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530495
Joe Perchesd2182b62011-12-15 14:55:53 -0800496 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800497 ah->eep_ops->get_eeprom_ver(ah),
498 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530499
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400500 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
501 if (ecode) {
Joe Perches38002762010-12-02 19:12:36 -0800502 ath_err(ath9k_hw_common(ah),
503 "Failed allocating banks for external radio\n");
Rajkumar Manoharan48a7c3d2010-11-08 20:40:53 +0530504 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400505 return ecode;
Luis R. Rodriguez574d6b12009-10-19 02:33:37 -0400506 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700507
Nikolay Martynov42794252011-12-02 22:39:16 -0500508 if (ah->config.enable_ani) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700509 ath9k_hw_ani_setup(ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700510 ath9k_hw_ani_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700511 }
Sujithf1dc5602008-10-29 10:16:30 +0530512
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700513 return 0;
514}
515
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400516static void ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700517{
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400518 if (AR_SREV_9300_20_OR_LATER(ah))
519 ar9003_hw_attach_ops(ah);
520 else
521 ar9002_hw_attach_ops(ah);
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700522}
523
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400524/* Called for all hardware families */
525static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700526{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700527 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700528 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700529
Senthil Balasubramanianac45c122010-12-22 21:14:20 +0530530 ath9k_hw_read_revisions(ah);
531
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530532 /*
533 * Read back AR_WA into a permanent copy and set bits 14 and 17.
534 * We need to do this to avoid RMW of this register. We cannot
535 * read the reg when chip is asleep.
536 */
537 ah->WARegVal = REG_READ(ah, AR_WA);
538 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
539 AR_WA_ASPM_TIMER_BASED_DISABLE);
540
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700541 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800542 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700543 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700544 }
545
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530546 if (AR_SREV_9462(ah))
Rajkumar Manoharaneec353c2011-10-13 10:49:13 +0530547 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
548
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400549 ath9k_hw_init_defaults(ah);
550 ath9k_hw_init_config(ah);
551
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400552 ath9k_hw_attach_ops(ah);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400553
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700554 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800555 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700556 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700557 }
558
559 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
560 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
John W. Linville4c85ab12010-07-28 10:06:35 -0400561 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
562 !ah->is_pciexpress)) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700563 ah->config.serialize_regmode =
564 SER_REG_MODE_ON;
565 } else {
566 ah->config.serialize_regmode =
567 SER_REG_MODE_OFF;
568 }
569 }
570
Joe Perchesd2182b62011-12-15 14:55:53 -0800571 ath_dbg(common, RESET, "serialize_regmode is %d\n",
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700572 ah->config.serialize_regmode);
573
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500574 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
576 else
577 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
578
Felix Fietkau6da5a722010-12-12 00:51:12 +0100579 switch (ah->hw_version.macVersion) {
580 case AR_SREV_VERSION_5416_PCI:
581 case AR_SREV_VERSION_5416_PCIE:
582 case AR_SREV_VERSION_9160:
583 case AR_SREV_VERSION_9100:
584 case AR_SREV_VERSION_9280:
585 case AR_SREV_VERSION_9285:
586 case AR_SREV_VERSION_9287:
587 case AR_SREV_VERSION_9271:
588 case AR_SREV_VERSION_9300:
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200589 case AR_SREV_VERSION_9330:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100590 case AR_SREV_VERSION_9485:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530591 case AR_SREV_VERSION_9340:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530592 case AR_SREV_VERSION_9462:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100593 break;
594 default:
Joe Perches38002762010-12-02 19:12:36 -0800595 ath_err(common,
596 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
597 ah->hw_version.macVersion, ah->hw_version.macRev);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700598 return -EOPNOTSUPP;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700599 }
600
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200601 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
602 AR_SREV_9330(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400603 ah->is_pciexpress = false;
604
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700605 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700606 ath9k_hw_init_cal_settings(ah);
607
608 ah->ani_function = ATH9K_ANI_ALL;
Felix Fietkau7a370812010-09-22 12:34:52 +0200609 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700610 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400611 if (!AR_SREV_9300_20_OR_LATER(ah))
612 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700613
Nikolay Martynov4f17c482011-12-06 21:57:17 -0500614 /* disable ANI for 9340 */
615 if (AR_SREV_9340(ah))
Nikolay Martynov42794252011-12-02 22:39:16 -0500616 ah->config.enable_ani = false;
617
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700618 ath9k_hw_init_mode_regs(ah);
619
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200620 if (!ah->is_pciexpress)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700621 ath9k_hw_disablepcie(ah);
622
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400623 if (!AR_SREV_9300_20_OR_LATER(ah))
624 ar9002_hw_cck_chan14_spread(ah);
Sujith193cd452009-09-18 15:04:07 +0530625
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700626 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700627 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700628 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700629
630 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100631 r = ath9k_hw_fill_cap_info(ah);
632 if (r)
633 return r;
634
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200635 if (ah->is_pciexpress)
636 ath9k_hw_aspm_init(ah);
637
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700638 r = ath9k_hw_init_macaddr(ah);
639 if (r) {
Joe Perches38002762010-12-02 19:12:36 -0800640 ath_err(common, "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700641 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700642 }
643
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400644 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith2660b812009-02-09 13:27:26 +0530645 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700646 else
Sujith2660b812009-02-09 13:27:26 +0530647 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700648
Gabor Juhos88e641d2011-06-21 11:23:30 +0200649 if (AR_SREV_9330(ah))
650 ah->bb_watchdog_timeout_ms = 85;
651 else
652 ah->bb_watchdog_timeout_ms = 25;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700653
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400654 common->state = ATH_HW_INITIALIZED;
655
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700656 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700657}
658
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400659int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530660{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400661 int ret;
662 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530663
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400664 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
665 switch (ah->hw_version.devid) {
666 case AR5416_DEVID_PCI:
667 case AR5416_DEVID_PCIE:
668 case AR5416_AR9100_DEVID:
669 case AR9160_DEVID_PCI:
670 case AR9280_DEVID_PCI:
671 case AR9280_DEVID_PCIE:
672 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400673 case AR9287_DEVID_PCI:
674 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400675 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400676 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800677 case AR9300_DEVID_AR9485_PCIE:
Gabor Juhos999a7a82011-06-21 11:23:52 +0200678 case AR9300_DEVID_AR9330:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530679 case AR9300_DEVID_AR9340:
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -0700680 case AR9300_DEVID_AR9580:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530681 case AR9300_DEVID_AR9462:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400682 break;
683 default:
684 if (common->bus_ops->ath_bus_type == ATH_USB)
685 break;
Joe Perches38002762010-12-02 19:12:36 -0800686 ath_err(common, "Hardware device ID 0x%04x not supported\n",
687 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400688 return -EOPNOTSUPP;
689 }
Sujithf1dc5602008-10-29 10:16:30 +0530690
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400691 ret = __ath9k_hw_init(ah);
692 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800693 ath_err(common,
694 "Unable to initialize hardware; initialization status: %d\n",
695 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400696 return ret;
697 }
Sujithf1dc5602008-10-29 10:16:30 +0530698
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400699 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530700}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400701EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530702
Sujithcbe61d82009-02-09 13:27:12 +0530703static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530704{
Sujith7d0d0df2010-04-16 11:53:57 +0530705 ENABLE_REGWRITE_BUFFER(ah);
706
Sujithf1dc5602008-10-29 10:16:30 +0530707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
709
710 REG_WRITE(ah, AR_QOS_NO_ACK,
711 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
712 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
713 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
714
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530720
721 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530722}
723
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530724u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530725{
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100726 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
727 udelay(100);
728 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
729
730 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530731 udelay(100);
Vivek Natarajanb1415812011-01-27 14:45:07 +0530732
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100733 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
Vivek Natarajanb1415812011-01-27 14:45:07 +0530734}
735EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
736
Sujithcbe61d82009-02-09 13:27:12 +0530737static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530738 struct ath9k_channel *chan)
739{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800740 u32 pll;
741
Vivek Natarajan22983c32011-01-27 14:45:09 +0530742 if (AR_SREV_9485(ah)) {
Vivek Natarajan22983c32011-01-27 14:45:09 +0530743
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530744 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
746 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
748 AR_CH0_DPLL2_KD, 0x40);
749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
750 AR_CH0_DPLL2_KI, 0x4);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530751
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
753 AR_CH0_BB_DPLL1_REFDIV, 0x5);
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
755 AR_CH0_BB_DPLL1_NINI, 0x58);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
757 AR_CH0_BB_DPLL1_NFRAC, 0x0);
758
759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
760 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
762 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
764 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
765
766 /* program BB PLL phase_shift to 0x6 */
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
768 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
769
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
Vivek Natarajan75e03512011-03-10 11:05:42 +0530772 udelay(1000);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200773 } else if (AR_SREV_9330(ah)) {
774 u32 ddr_dpll2, pll_control2, kd;
775
776 if (ah->is_clk_25mhz) {
777 ddr_dpll2 = 0x18e82f01;
778 pll_control2 = 0xe04a3d;
779 kd = 0x1d;
780 } else {
781 ddr_dpll2 = 0x19e82f01;
782 pll_control2 = 0x886666;
783 kd = 0x3d;
784 }
785
786 /* program DDR PLL ki and kd value */
787 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
788
789 /* program DDR PLL phase_shift */
790 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
791 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
792
793 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
794 udelay(1000);
795
796 /* program refdiv, nint, frac to RTC register */
797 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
798
799 /* program BB PLL kd and ki value */
800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
802
803 /* program BB PLL phase_shift */
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
805 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530806 } else if (AR_SREV_9340(ah)) {
807 u32 regval, pll2_divint, pll2_divfrac, refdiv;
808
809 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
810 udelay(1000);
811
812 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
813 udelay(100);
814
815 if (ah->is_clk_25mhz) {
816 pll2_divint = 0x54;
817 pll2_divfrac = 0x1eb85;
818 refdiv = 3;
819 } else {
820 pll2_divint = 88;
821 pll2_divfrac = 0;
822 refdiv = 5;
823 }
824
825 regval = REG_READ(ah, AR_PHY_PLL_MODE);
826 regval |= (0x1 << 16);
827 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
828 udelay(100);
829
830 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
831 (pll2_divint << 18) | pll2_divfrac);
832 udelay(100);
833
834 regval = REG_READ(ah, AR_PHY_PLL_MODE);
835 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
836 (0x4 << 26) | (0x18 << 19);
837 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
838 REG_WRITE(ah, AR_PHY_PLL_MODE,
839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
840 udelay(1000);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530841 }
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800842
843 pll = ath9k_hw_compute_pll_control(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +0530844
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100845 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530846
Gabor Juhosa5415d62011-06-21 11:23:29 +0200847 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530848 udelay(1000);
849
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400850 /* Switch the core clock for ar9271 to 117Mhz */
851 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530852 udelay(500);
853 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400854 }
855
Sujithf1dc5602008-10-29 10:16:30 +0530856 udelay(RTC_PLL_SETTLE_DELAY);
857
858 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530859
860 if (AR_SREV_9340(ah)) {
861 if (ah->is_clk_25mhz) {
862 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
863 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
864 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
865 } else {
866 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
867 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
868 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
869 }
870 udelay(100);
871 }
Sujithf1dc5602008-10-29 10:16:30 +0530872}
873
Sujithcbe61d82009-02-09 13:27:12 +0530874static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800875 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530876{
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530877 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Pavel Roskin152d5302010-03-31 18:05:37 -0400878 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530879 AR_IMR_TXURN |
880 AR_IMR_RXERR |
881 AR_IMR_RXORN |
882 AR_IMR_BCNMISC;
883
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530884 if (AR_SREV_9340(ah))
885 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
886
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400887 if (AR_SREV_9300_20_OR_LATER(ah)) {
888 imr_reg |= AR_IMR_RXOK_HP;
889 if (ah->config.rx_intr_mitigation)
890 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
891 else
892 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530893
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400894 } else {
895 if (ah->config.rx_intr_mitigation)
896 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
897 else
898 imr_reg |= AR_IMR_RXOK;
899 }
900
901 if (ah->config.tx_intr_mitigation)
902 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
903 else
904 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530905
Colin McCabed97809d2008-12-01 13:38:55 -0800906 if (opmode == NL80211_IFTYPE_AP)
Pavel Roskin152d5302010-03-31 18:05:37 -0400907 imr_reg |= AR_IMR_MIB;
Sujithf1dc5602008-10-29 10:16:30 +0530908
Sujith7d0d0df2010-04-16 11:53:57 +0530909 ENABLE_REGWRITE_BUFFER(ah);
910
Pavel Roskin152d5302010-03-31 18:05:37 -0400911 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500912 ah->imrs2_reg |= AR_IMR_S2_GTT;
913 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530914
915 if (!AR_SREV_9100(ah)) {
916 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530917 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
Sujithf1dc5602008-10-29 10:16:30 +0530918 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
919 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400920
Sujith7d0d0df2010-04-16 11:53:57 +0530921 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530922
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400923 if (AR_SREV_9300_20_OR_LATER(ah)) {
924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
927 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
928 }
Sujithf1dc5602008-10-29 10:16:30 +0530929}
930
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700931static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
932{
933 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
934 val = min(val, (u32) 0xFFFF);
935 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
936}
937
Felix Fietkau0005baf2010-01-15 02:33:40 +0100938static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530939{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100940 u32 val = ath9k_hw_mac_to_clks(ah, us);
941 val = min(val, (u32) 0xFFFF);
942 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +0530943}
944
Felix Fietkau0005baf2010-01-15 02:33:40 +0100945static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530946{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100947 u32 val = ath9k_hw_mac_to_clks(ah, us);
948 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
949 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
950}
951
952static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
953{
954 u32 val = ath9k_hw_mac_to_clks(ah, us);
955 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
956 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +0530957}
958
Sujithcbe61d82009-02-09 13:27:12 +0530959static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +0530960{
Sujithf1dc5602008-10-29 10:16:30 +0530961 if (tu > 0xFFFF) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800962 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
963 tu);
Sujith2660b812009-02-09 13:27:26 +0530964 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +0530965 return false;
966 } else {
967 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +0530968 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +0530969 return true;
970 }
971}
972
Felix Fietkau0005baf2010-01-15 02:33:40 +0100973void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530974{
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700975 struct ath_common *common = ath9k_hw_common(ah);
976 struct ieee80211_conf *conf = &common->hw->conf;
977 const struct ath9k_channel *chan = ah->curchan;
Felix Fietkauadb50662011-08-28 01:52:10 +0200978 int acktimeout, ctstimeout;
Felix Fietkaue239d852010-01-15 02:34:58 +0100979 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100980 int sifstime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700981 int rx_lat = 0, tx_lat = 0, eifs = 0;
982 u32 reg;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100983
Joe Perchesd2182b62011-12-15 14:55:53 -0800984 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -0800985 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +0530986
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700987 if (!chan)
988 return;
989
Sujith2660b812009-02-09 13:27:26 +0530990 if (ah->misc_mode != 0)
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100991 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100992
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +0530993 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
994 rx_lat = 41;
995 else
996 rx_lat = 37;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700997 tx_lat = 54;
998
999 if (IS_CHAN_HALF_RATE(chan)) {
1000 eifs = 175;
1001 rx_lat *= 2;
1002 tx_lat *= 2;
1003 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1004 tx_lat += 11;
1005
1006 slottime = 13;
1007 sifstime = 32;
1008 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1009 eifs = 340;
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301010 rx_lat = (rx_lat * 4) - 1;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001011 tx_lat *= 4;
1012 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1013 tx_lat += 22;
1014
1015 slottime = 21;
1016 sifstime = 64;
1017 } else {
Rajkumar Manoharana7be0392011-08-27 12:13:21 +05301018 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1019 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1020 reg = AR_USEC_ASYNC_FIFO;
1021 } else {
1022 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1023 common->clockrate;
1024 reg = REG_READ(ah, AR_USEC);
1025 }
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001026 rx_lat = MS(reg, AR_USEC_RX_LAT);
1027 tx_lat = MS(reg, AR_USEC_TX_LAT);
1028
1029 slottime = ah->slottime;
1030 if (IS_CHAN_5GHZ(chan))
1031 sifstime = 16;
1032 else
1033 sifstime = 10;
1034 }
Felix Fietkau0005baf2010-01-15 02:33:40 +01001035
Felix Fietkaue239d852010-01-15 02:34:58 +01001036 /* As defined by IEEE 802.11-2007 17.3.8.6 */
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001037 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
Felix Fietkauadb50662011-08-28 01:52:10 +02001038 ctstimeout = acktimeout;
Felix Fietkau42c45682010-02-11 18:07:19 +01001039
1040 /*
1041 * Workaround for early ACK timeouts, add an offset to match the
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001042 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
Felix Fietkau42c45682010-02-11 18:07:19 +01001043 * This was initially only meant to work around an issue with delayed
1044 * BA frames in some implementations, but it has been found to fix ACK
1045 * timeout issues in other cases as well.
1046 */
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001047 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
Felix Fietkau42c45682010-02-11 18:07:19 +01001048 acktimeout += 64 - sifstime - ah->slottime;
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001049 ctstimeout += 48 - sifstime - ah->slottime;
1050 }
1051
Felix Fietkau42c45682010-02-11 18:07:19 +01001052
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001053 ath9k_hw_set_sifs_time(ah, sifstime);
1054 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001055 ath9k_hw_set_ack_timeout(ah, acktimeout);
Felix Fietkauadb50662011-08-28 01:52:10 +02001056 ath9k_hw_set_cts_timeout(ah, ctstimeout);
Sujith2660b812009-02-09 13:27:26 +05301057 if (ah->globaltxtimeout != (u32) -1)
1058 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001059
1060 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1061 REG_RMW(ah, AR_USEC,
1062 (common->clockrate - 1) |
1063 SM(rx_lat, AR_USEC_RX_LAT) |
1064 SM(tx_lat, AR_USEC_TX_LAT),
1065 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1066
Sujithf1dc5602008-10-29 10:16:30 +05301067}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001068EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301069
Sujith285f2dd2010-01-08 10:36:07 +05301070void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001071{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001072 struct ath_common *common = ath9k_hw_common(ah);
1073
Sujith736b3a22010-03-17 14:25:24 +05301074 if (common->state < ATH_HW_INITIALIZED)
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001075 goto free_hw;
1076
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001077 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001078
1079free_hw:
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001080 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001081}
Sujith285f2dd2010-01-08 10:36:07 +05301082EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001083
Sujithf1dc5602008-10-29 10:16:30 +05301084/*******/
1085/* INI */
1086/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001087
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001088u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -04001089{
1090 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1091
1092 if (IS_CHAN_B(chan))
1093 ctl |= CTL_11B;
1094 else if (IS_CHAN_G(chan))
1095 ctl |= CTL_11G;
1096 else
1097 ctl |= CTL_11A;
1098
1099 return ctl;
1100}
1101
Sujithf1dc5602008-10-29 10:16:30 +05301102/****************************************/
1103/* Reset and Channel Switching Routines */
1104/****************************************/
1105
Sujithcbe61d82009-02-09 13:27:12 +05301106static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301107{
Felix Fietkau57b32222010-04-15 17:39:22 -04001108 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301109
Sujith7d0d0df2010-04-16 11:53:57 +05301110 ENABLE_REGWRITE_BUFFER(ah);
1111
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001112 /*
1113 * set AHB_MODE not to do cacheline prefetches
1114 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001115 if (!AR_SREV_9300_20_OR_LATER(ah))
1116 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301117
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001118 /*
1119 * let mac dma reads be in 128 byte chunks
1120 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001121 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301122
Sujith7d0d0df2010-04-16 11:53:57 +05301123 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301124
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001125 /*
1126 * Restore TX Trigger Level to its pre-reset value.
1127 * The initial value depends on whether aggregation is enabled, and is
1128 * adjusted whenever underruns are detected.
1129 */
Felix Fietkau57b32222010-04-15 17:39:22 -04001130 if (!AR_SREV_9300_20_OR_LATER(ah))
1131 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301132
Sujith7d0d0df2010-04-16 11:53:57 +05301133 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301134
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001135 /*
1136 * let mac dma writes be in 128 byte chunks
1137 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001138 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301139
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001140 /*
1141 * Setup receive FIFO threshold to hold off TX activities
1142 */
Sujithf1dc5602008-10-29 10:16:30 +05301143 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1144
Felix Fietkau57b32222010-04-15 17:39:22 -04001145 if (AR_SREV_9300_20_OR_LATER(ah)) {
1146 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1147 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1148
1149 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1150 ah->caps.rx_status_len);
1151 }
1152
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001153 /*
1154 * reduce the number of usable entries in PCU TXBUF to avoid
1155 * wrap around issues.
1156 */
Sujithf1dc5602008-10-29 10:16:30 +05301157 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001158 /* For AR9285 the number of Fifos are reduced to half.
1159 * So set the usable tx buf size also to half to
1160 * avoid data/delimiter underruns
1161 */
Sujithf1dc5602008-10-29 10:16:30 +05301162 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1163 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001164 } else if (!AR_SREV_9271(ah)) {
Sujithf1dc5602008-10-29 10:16:30 +05301165 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1166 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1167 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001168
Sujith7d0d0df2010-04-16 11:53:57 +05301169 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301170
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001171 if (AR_SREV_9300_20_OR_LATER(ah))
1172 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301173}
1174
Sujithcbe61d82009-02-09 13:27:12 +05301175static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301176{
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001177 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1178 u32 set = AR_STA_ID1_KSRCH_MODE;
Sujithf1dc5602008-10-29 10:16:30 +05301179
Sujithf1dc5602008-10-29 10:16:30 +05301180 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001181 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04001182 case NL80211_IFTYPE_MESH_POINT:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001183 set |= AR_STA_ID1_ADHOC;
Sujithf1dc5602008-10-29 10:16:30 +05301184 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1185 break;
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001186 case NL80211_IFTYPE_AP:
1187 set |= AR_STA_ID1_STA_AP;
1188 /* fall through */
Colin McCabed97809d2008-12-01 13:38:55 -08001189 case NL80211_IFTYPE_STATION:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001190 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
Sujithf1dc5602008-10-29 10:16:30 +05301191 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301192 default:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001193 if (!ah->is_monitoring)
1194 set = 0;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301195 break;
Sujithf1dc5602008-10-29 10:16:30 +05301196 }
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001197 REG_RMW(ah, AR_STA_ID1, set, mask);
Sujithf1dc5602008-10-29 10:16:30 +05301198}
1199
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001200void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1201 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001202{
1203 u32 coef_exp, coef_man;
1204
1205 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1206 if ((coef_scaled >> coef_exp) & 0x1)
1207 break;
1208
1209 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1210
1211 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1212
1213 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1214 *coef_exponent = coef_exp - 16;
1215}
1216
Sujithcbe61d82009-02-09 13:27:12 +05301217static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301218{
1219 u32 rst_flags;
1220 u32 tmpReg;
1221
Sujith70768492009-02-16 13:23:12 +05301222 if (AR_SREV_9100(ah)) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001223 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1224 AR_RTC_DERIVED_CLK_PERIOD, 1);
Sujith70768492009-02-16 13:23:12 +05301225 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1226 }
1227
Sujith7d0d0df2010-04-16 11:53:57 +05301228 ENABLE_REGWRITE_BUFFER(ah);
1229
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001230 if (AR_SREV_9300_20_OR_LATER(ah)) {
1231 REG_WRITE(ah, AR_WA, ah->WARegVal);
1232 udelay(10);
1233 }
1234
Sujithf1dc5602008-10-29 10:16:30 +05301235 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1236 AR_RTC_FORCE_WAKE_ON_INT);
1237
1238 if (AR_SREV_9100(ah)) {
1239 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1240 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1241 } else {
1242 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1243 if (tmpReg &
1244 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1245 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001246 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301247 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001248
1249 val = AR_RC_HOSTIF;
1250 if (!AR_SREV_9300_20_OR_LATER(ah))
1251 val |= AR_RC_AHB;
1252 REG_WRITE(ah, AR_RC, val);
1253
1254 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301255 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301256
1257 rst_flags = AR_RTC_RC_MAC_WARM;
1258 if (type == ATH9K_RESET_COLD)
1259 rst_flags |= AR_RTC_RC_MAC_COLD;
1260 }
1261
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001262 if (AR_SREV_9330(ah)) {
1263 int npend = 0;
1264 int i;
1265
1266 /* AR9330 WAR:
1267 * call external reset function to reset WMAC if:
1268 * - doing a cold reset
1269 * - we have pending frames in the TX queues
1270 */
1271
1272 for (i = 0; i < AR_NUM_QCU; i++) {
1273 npend = ath9k_hw_numtxpending(ah, i);
1274 if (npend)
1275 break;
1276 }
1277
1278 if (ah->external_reset &&
1279 (npend || type == ATH9K_RESET_COLD)) {
1280 int reset_err = 0;
1281
Joe Perchesd2182b62011-12-15 14:55:53 -08001282 ath_dbg(ath9k_hw_common(ah), RESET,
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001283 "reset MAC via external reset\n");
1284
1285 reset_err = ah->external_reset();
1286 if (reset_err) {
1287 ath_err(ath9k_hw_common(ah),
1288 "External reset failed, err=%d\n",
1289 reset_err);
1290 return false;
1291 }
1292
1293 REG_WRITE(ah, AR_RTC_RESET, 1);
1294 }
1295 }
1296
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001297 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301298
1299 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301300
Sujithf1dc5602008-10-29 10:16:30 +05301301 udelay(50);
1302
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001303 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301304 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001305 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301306 return false;
1307 }
1308
1309 if (!AR_SREV_9100(ah))
1310 REG_WRITE(ah, AR_RC, 0);
1311
Sujithf1dc5602008-10-29 10:16:30 +05301312 if (AR_SREV_9100(ah))
1313 udelay(50);
1314
1315 return true;
1316}
1317
Sujithcbe61d82009-02-09 13:27:12 +05301318static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301319{
Sujith7d0d0df2010-04-16 11:53:57 +05301320 ENABLE_REGWRITE_BUFFER(ah);
1321
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001322 if (AR_SREV_9300_20_OR_LATER(ah)) {
1323 REG_WRITE(ah, AR_WA, ah->WARegVal);
1324 udelay(10);
1325 }
1326
Sujithf1dc5602008-10-29 10:16:30 +05301327 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1328 AR_RTC_FORCE_WAKE_ON_INT);
1329
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001330 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301331 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1332
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001333 REG_WRITE(ah, AR_RTC_RESET, 0);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301334
Sujith7d0d0df2010-04-16 11:53:57 +05301335 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301336
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001337 if (!AR_SREV_9300_20_OR_LATER(ah))
1338 udelay(2);
1339
1340 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301341 REG_WRITE(ah, AR_RC, 0);
1342
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001343 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301344
1345 if (!ath9k_hw_wait(ah,
1346 AR_RTC_STATUS,
1347 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301348 AR_RTC_STATUS_ON,
1349 AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001350 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301351 return false;
1352 }
1353
Sujithf1dc5602008-10-29 10:16:30 +05301354 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1355}
1356
Sujithcbe61d82009-02-09 13:27:12 +05301357static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301358{
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301359 bool ret = false;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301360
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001361 if (AR_SREV_9300_20_OR_LATER(ah)) {
1362 REG_WRITE(ah, AR_WA, ah->WARegVal);
1363 udelay(10);
1364 }
1365
Sujithf1dc5602008-10-29 10:16:30 +05301366 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1367 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1368
1369 switch (type) {
1370 case ATH9K_RESET_POWER_ON:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301371 ret = ath9k_hw_set_reset_power_on(ah);
1372 break;
Sujithf1dc5602008-10-29 10:16:30 +05301373 case ATH9K_RESET_WARM:
1374 case ATH9K_RESET_COLD:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301375 ret = ath9k_hw_set_reset(ah, type);
1376 break;
Sujithf1dc5602008-10-29 10:16:30 +05301377 default:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301378 break;
Sujithf1dc5602008-10-29 10:16:30 +05301379 }
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301380
1381 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1382 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1383
1384 return ret;
Sujithf1dc5602008-10-29 10:16:30 +05301385}
1386
Sujithcbe61d82009-02-09 13:27:12 +05301387static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301388 struct ath9k_channel *chan)
1389{
Felix Fietkau9c083af2012-03-03 15:17:02 +01001390 int reset_type = ATH9K_RESET_WARM;
1391
1392 if (AR_SREV_9280(ah)) {
1393 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1394 reset_type = ATH9K_RESET_POWER_ON;
1395 else
1396 reset_type = ATH9K_RESET_COLD;
1397 }
1398
1399 if (!ath9k_hw_set_reset_reg(ah, reset_type))
Sujithf1dc5602008-10-29 10:16:30 +05301400 return false;
1401
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001402 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301403 return false;
1404
Sujith2660b812009-02-09 13:27:26 +05301405 ah->chip_fullsleep = false;
Sujithf1dc5602008-10-29 10:16:30 +05301406 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301407 ath9k_hw_set_rfmode(ah, chan);
1408
1409 return true;
1410}
1411
Sujithcbe61d82009-02-09 13:27:12 +05301412static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001413 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301414{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001415 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001416 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001417 int r;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301418 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1419 bool band_switch, mode_diff;
1420 u8 ini_reloaded;
1421
1422 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1423 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1424 CHANNEL_5GHZ));
1425 mode_diff = (chan->chanmode != ah->curchan->chanmode);
Sujithf1dc5602008-10-29 10:16:30 +05301426
1427 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1428 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001429 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -08001430 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301431 return false;
1432 }
1433 }
1434
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001435 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001436 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301437 return false;
1438 }
1439
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301440 if (edma && (band_switch || mode_diff)) {
1441 ath9k_hw_mark_phy_inactive(ah);
1442 udelay(5);
1443
1444 ath9k_hw_init_pll(ah, NULL);
1445
1446 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1447 ath_err(common, "Failed to do fast channel change\n");
1448 return false;
1449 }
1450 }
1451
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001452 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301453
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001454 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001455 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001456 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001457 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301458 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001459 ath9k_hw_set_clockrate(ah);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02001460 ath9k_hw_apply_txpower(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001461 ath9k_hw_rfbus_done(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301462
1463 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1464 ath9k_hw_set_delta_slope(ah, chan);
1465
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001466 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301467
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301468 if (edma && (band_switch || mode_diff)) {
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301469 ah->ah_flags |= AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301470 if (band_switch || ini_reloaded)
1471 ah->eep_ops->set_board_values(ah, chan);
1472
1473 ath9k_hw_init_bb(ah, chan);
1474
1475 if (band_switch || ini_reloaded)
1476 ath9k_hw_init_cal(ah, chan);
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301477 ah->ah_flags &= ~AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301478 }
1479
Sujithf1dc5602008-10-29 10:16:30 +05301480 return true;
1481}
1482
Felix Fietkau691680b2011-03-19 13:55:38 +01001483static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1484{
1485 u32 gpio_mask = ah->gpio_mask;
1486 int i;
1487
1488 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1489 if (!(gpio_mask & 1))
1490 continue;
1491
1492 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1493 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1494 }
1495}
1496
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001497bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301498{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001499 int count = 50;
1500 u32 reg;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301501
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001502 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001503 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301504
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001505 do {
1506 reg = REG_READ(ah, AR_OBS_BUS_1);
1507
1508 if ((reg & 0x7E7FFFEF) == 0x00702400)
1509 continue;
1510
1511 switch (reg & 0x7E000B00) {
1512 case 0x1E000000:
1513 case 0x52000B00:
1514 case 0x18000B00:
1515 continue;
1516 default:
1517 return true;
1518 }
1519 } while (count-- > 0);
1520
1521 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301522}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001523EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301524
Sujith Manoharancaed6572012-03-14 14:40:46 +05301525/*
1526 * Fast channel change:
1527 * (Change synthesizer based on channel freq without resetting chip)
1528 *
1529 * Don't do FCC when
1530 * - Flag is not set
1531 * - Chip is just coming out of full sleep
1532 * - Channel to be set is same as current channel
1533 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1534 */
1535static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1536{
1537 struct ath_common *common = ath9k_hw_common(ah);
1538 int ret;
1539
1540 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1541 goto fail;
1542
1543 if (ah->chip_fullsleep)
1544 goto fail;
1545
1546 if (!ah->curchan)
1547 goto fail;
1548
1549 if (chan->channel == ah->curchan->channel)
1550 goto fail;
1551
1552 if ((chan->channelFlags & CHANNEL_ALL) !=
1553 (ah->curchan->channelFlags & CHANNEL_ALL))
1554 goto fail;
1555
1556 if (!ath9k_hw_check_alive(ah))
1557 goto fail;
1558
1559 /*
1560 * For AR9462, make sure that calibration data for
1561 * re-using are present.
1562 */
1563 if (AR_SREV_9462(ah) && (!ah->caldata ||
1564 !ah->caldata->done_txiqcal_once ||
1565 !ah->caldata->done_txclcal_once ||
1566 !ah->caldata->rtt_hist.num_readings))
1567 goto fail;
1568
1569 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1570 ah->curchan->channel, chan->channel);
1571
1572 ret = ath9k_hw_channel_change(ah, chan);
1573 if (!ret)
1574 goto fail;
1575
1576 ath9k_hw_loadnf(ah, ah->curchan);
1577 ath9k_hw_start_nfcal(ah, true);
1578
1579 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1580 ar9003_mci_2g5g_switch(ah, true);
1581
1582 if (AR_SREV_9271(ah))
1583 ar9002_hw_load_ani_reg(ah, chan);
1584
1585 return 0;
1586fail:
1587 return -EINVAL;
1588}
1589
Sujithcbe61d82009-02-09 13:27:12 +05301590int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith Manoharancaed6572012-03-14 14:40:46 +05301591 struct ath9k_hw_cal_data *caldata, bool fastcc)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001592{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001593 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001594 u32 saveLedState;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001595 u32 saveDefAntenna;
1596 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301597 u64 tsf = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001598 int i, r;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301599 bool start_mci_reset = false;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301600 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1601 bool save_fullsleep = ah->chip_fullsleep;
1602
1603 if (mci) {
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301604 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1605 if (start_mci_reset)
1606 return 0;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301607 }
1608
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001609 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001610 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001611
Sujith Manoharancaed6572012-03-14 14:40:46 +05301612 if (ah->curchan && !ah->chip_fullsleep)
1613 ath9k_hw_getnf(ah, ah->curchan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001614
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001615 ah->caldata = caldata;
1616 if (caldata &&
1617 (chan->channel != caldata->channel ||
1618 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1619 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1620 /* Operating channel changed, reset channel calibration data */
1621 memset(caldata, 0, sizeof(*caldata));
1622 ath9k_init_nfcal_hist_buffer(ah, chan);
1623 }
Felix Fietkauf23fba42011-07-28 14:08:56 +02001624 ah->noise = ath9k_hw_getchan_noise(ah, chan);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001625
Sujith Manoharancaed6572012-03-14 14:40:46 +05301626 if (fastcc) {
1627 r = ath9k_hw_do_fastcc(ah, chan);
1628 if (!r)
1629 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001630 }
1631
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301632 if (mci)
1633 ar9003_mci_stop_bt(ah, save_fullsleep);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301634
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001635 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1636 if (saveDefAntenna == 0)
1637 saveDefAntenna = 1;
1638
1639 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1640
Sujith46fe7822009-09-17 09:25:25 +05301641 /* For chips on which RTC reset is done, save TSF before it gets cleared */
Felix Fietkauf860d522010-06-30 02:07:48 +02001642 if (AR_SREV_9100(ah) ||
1643 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
Sujith46fe7822009-09-17 09:25:25 +05301644 tsf = ath9k_hw_gettsf64(ah);
1645
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001646 saveLedState = REG_READ(ah, AR_CFG_LED) &
1647 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1648 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1649
1650 ath9k_hw_mark_phy_inactive(ah);
1651
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -08001652 ah->paprd_table_write_done = false;
1653
Sujith05020d22010-03-17 14:25:23 +05301654 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001655 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1656 REG_WRITE(ah,
1657 AR9271_RESET_POWER_DOWN_CONTROL,
1658 AR9271_RADIO_RF_RST);
1659 udelay(50);
1660 }
1661
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001662 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001663 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001664 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001665 }
1666
Sujith05020d22010-03-17 14:25:23 +05301667 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001668 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1669 ah->htc_reset_init = false;
1670 REG_WRITE(ah,
1671 AR9271_RESET_POWER_DOWN_CONTROL,
1672 AR9271_GATE_MAC_CTL);
1673 udelay(50);
1674 }
1675
Sujith46fe7822009-09-17 09:25:25 +05301676 /* Restore TSF */
Felix Fietkauf860d522010-06-30 02:07:48 +02001677 if (tsf)
Sujith46fe7822009-09-17 09:25:25 +05301678 ath9k_hw_settsf64(ah, tsf);
1679
Felix Fietkau7a370812010-09-22 12:34:52 +02001680 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301681 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001682
Sujithe9141f72010-06-01 15:14:10 +05301683 if (!AR_SREV_9300_20_OR_LATER(ah))
1684 ar9002_hw_enable_async_fifo(ah);
1685
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001686 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001687 if (r)
1688 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001689
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301690 if (mci)
1691 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1692
Felix Fietkauf860d522010-06-30 02:07:48 +02001693 /*
1694 * Some AR91xx SoC devices frequently fail to accept TSF writes
1695 * right after the chip reset. When that happens, write a new
1696 * value after the initvals have been applied, with an offset
1697 * based on measured time difference
1698 */
1699 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1700 tsf += 1500;
1701 ath9k_hw_settsf64(ah, tsf);
1702 }
1703
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001704 /* Setup MFP options for CCMP */
1705 if (AR_SREV_9280_20_OR_LATER(ah)) {
1706 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1707 * frames when constructing CCMP AAD. */
1708 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1709 0xc7ff);
1710 ah->sw_mgmt_crypto = false;
1711 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1712 /* Disable hardware crypto for management frames */
1713 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1714 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1715 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1716 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1717 ah->sw_mgmt_crypto = true;
1718 } else
1719 ah->sw_mgmt_crypto = true;
1720
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001721 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1722 ath9k_hw_set_delta_slope(ah, chan);
1723
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001724 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301725 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001726
Sujith7d0d0df2010-04-16 11:53:57 +05301727 ENABLE_REGWRITE_BUFFER(ah);
1728
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001729 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1730 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001731 | macStaId1
1732 | AR_STA_ID1_RTS_USE_DEF
Sujith2660b812009-02-09 13:27:26 +05301733 | (ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301734 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
Sujith2660b812009-02-09 13:27:26 +05301735 | ah->sta_id1_defaults);
Luis R. Rodriguez13b81552009-09-10 17:52:45 -07001736 ath_hw_setbssidmask(common);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
Luis R. Rodriguez3453ad82009-09-10 08:57:00 -07001738 ath9k_hw_write_associd(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001739 REG_WRITE(ah, AR_ISR, ~0);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1741
Sujith7d0d0df2010-04-16 11:53:57 +05301742 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301743
Sujith Manoharan00e00032011-01-26 21:59:05 +05301744 ath9k_hw_set_operating_mode(ah, ah->opmode);
1745
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001746 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001747 if (r)
1748 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001749
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001750 ath9k_hw_set_clockrate(ah);
1751
Sujith7d0d0df2010-04-16 11:53:57 +05301752 ENABLE_REGWRITE_BUFFER(ah);
1753
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001754 for (i = 0; i < AR_NUM_DCU; i++)
1755 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1756
Sujith7d0d0df2010-04-16 11:53:57 +05301757 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301758
Sujith2660b812009-02-09 13:27:26 +05301759 ah->intr_txqs = 0;
Felix Fietkauf4c607d2011-03-23 20:57:28 +01001760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001761 ath9k_hw_resettxqueue(ah, i);
1762
Sujith2660b812009-02-09 13:27:26 +05301763 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001764 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001765 ath9k_hw_init_qos(ah);
1766
Sujith2660b812009-02-09 13:27:26 +05301767 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Felix Fietkau55821322010-12-17 00:57:01 +01001768 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301769
Felix Fietkau0005baf2010-01-15 02:33:40 +01001770 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001771
Felix Fietkaufe2b6af2011-07-09 11:12:51 +07001772 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1773 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1774 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1775 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1776 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1777 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1778 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301779 }
1780
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001781 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001782
1783 ath9k_hw_set_dma(ah);
1784
1785 REG_WRITE(ah, AR_OBS, 8);
1786
Sujith0ce024c2009-12-14 14:57:00 +05301787 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001788 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1789 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1790 }
1791
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001792 if (ah->config.tx_intr_mitigation) {
1793 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1794 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1795 }
1796
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001797 ath9k_hw_init_bb(ah, chan);
1798
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301799 if (caldata) {
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301800 caldata->done_txiqcal_once = false;
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301801 caldata->done_txclcal_once = false;
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +05301802 caldata->rtt_hist.num_readings = 0;
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301803 }
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001804 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001805 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001806
Rajkumar Manoharan93348922011-10-25 16:47:36 +05301807 ath9k_hw_loadnf(ah, chan);
1808 ath9k_hw_start_nfcal(ah, true);
1809
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301810 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1811 return -EIO;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301812
Sujith7d0d0df2010-04-16 11:53:57 +05301813 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001814
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001815 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001816 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1817
Sujith7d0d0df2010-04-16 11:53:57 +05301818 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301819
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001820 /*
1821 * For big endian systems turn on swapping for descriptors
1822 */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001823 if (AR_SREV_9100(ah)) {
1824 u32 mask;
1825 mask = REG_READ(ah, AR_CFG);
1826 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001827 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1828 mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001829 } else {
1830 mask =
1831 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1832 REG_WRITE(ah, AR_CFG, mask);
Joe Perchesd2182b62011-12-15 14:55:53 -08001833 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1834 REG_READ(ah, AR_CFG));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001835 }
1836 } else {
Sujithcbba8cd2010-06-02 15:53:31 +05301837 if (common->bus_ops->ath_bus_type == ATH_USB) {
1838 /* Configure AR9271 target WLAN */
1839 if (AR_SREV_9271(ah))
1840 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1841 else
1842 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1843 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001844#ifdef __BIG_ENDIAN
Gabor Juhos4033bda2011-06-21 11:23:35 +02001845 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan2be7bfe2011-04-19 19:29:14 +05301846 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1847 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001848 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001849#endif
1850 }
1851
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301852 if (ath9k_hw_btcoex_is_enabled(ah))
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05301853 ath9k_hw_btcoex_enable(ah);
1854
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301855 if (mci)
1856 ar9003_mci_check_bt(ah);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301857
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301858 if (AR_SREV_9300_20_OR_LATER(ah)) {
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001859 ar9003_hw_bb_watchdog_config(ah);
Vasanthakumar Thiagarajand8903a52010-04-15 17:39:25 -04001860
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301861 ar9003_hw_disable_phy_restart(ah);
1862 }
1863
Felix Fietkau691680b2011-03-19 13:55:38 +01001864 ath9k_hw_apply_gpio_override(ah);
1865
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001866 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001867}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001868EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001869
Sujithf1dc5602008-10-29 10:16:30 +05301870/******************************/
1871/* Power Management (Chipset) */
1872/******************************/
1873
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001874/*
1875 * Notify Power Mgt is disabled in self-generated frames.
1876 * If requested, force chip to sleep.
1877 */
Sujithcbe61d82009-02-09 13:27:12 +05301878static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05301879{
1880 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1881 if (setChip) {
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301882 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301883 REG_WRITE(ah, AR_TIMER_MODE,
1884 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1885 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1886 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1887 REG_WRITE(ah, AR_SLP32_INC,
1888 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1889 /* xxx Required for WLAN only case ? */
1890 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1891 udelay(100);
1892 }
1893
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001894 /*
1895 * Clear the RTC force wake bit to allow the
1896 * mac to go to sleep.
1897 */
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301898 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1899
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301900 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301901 udelay(100);
1902
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001903 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301904 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1905
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001906 /* Shutdown chip. Active low */
Sujith Manoharanc91ec462012-02-22 12:40:03 +05301907 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301908 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1909 udelay(2);
1910 }
Sujithf1dc5602008-10-29 10:16:30 +05301911 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001912
1913 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
Rafael J. Wysockia7322812011-11-26 23:37:43 +01001914 if (AR_SREV_9300_20_OR_LATER(ah))
1915 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001916}
1917
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001918/*
1919 * Notify Power Management is enabled in self-generating
1920 * frames. If request, set power mode of chip to
1921 * auto/normal. Duration in units of 128us (1/8 TU).
1922 */
Sujithcbe61d82009-02-09 13:27:12 +05301923static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001924{
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301925 u32 val;
1926
Sujithf1dc5602008-10-29 10:16:30 +05301927 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1928 if (setChip) {
Sujith2660b812009-02-09 13:27:26 +05301929 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001930
Sujithf1dc5602008-10-29 10:16:30 +05301931 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001932 /* Set WakeOnInterrupt bit; clear ForceWake bit */
Sujithf1dc5602008-10-29 10:16:30 +05301933 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1934 AR_RTC_FORCE_WAKE_ON_INT);
1935 } else {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301936
1937 /* When chip goes into network sleep, it could be waken
1938 * up by MCI_INT interrupt caused by BT's HW messages
1939 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1940 * rate (~100us). This will cause chip to leave and
1941 * re-enter network sleep mode frequently, which in
1942 * consequence will have WLAN MCI HW to generate lots of
1943 * SYS_WAKING and SYS_SLEEPING messages which will make
1944 * BT CPU to busy to process.
1945 */
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301946 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301947 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1948 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1949 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1950 }
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001951 /*
1952 * Clear the RTC force wake bit to allow the
1953 * mac to go to sleep.
1954 */
Sujithf1dc5602008-10-29 10:16:30 +05301955 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1956 AR_RTC_FORCE_WAKE_EN);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301957
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301958 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301959 udelay(30);
Sujithf1dc5602008-10-29 10:16:30 +05301960 }
1961 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001962
1963 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1964 if (AR_SREV_9300_20_OR_LATER(ah))
1965 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05301966}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001967
Sujithcbe61d82009-02-09 13:27:12 +05301968static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05301969{
1970 u32 val;
1971 int i;
1972
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001973 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1974 if (AR_SREV_9300_20_OR_LATER(ah)) {
1975 REG_WRITE(ah, AR_WA, ah->WARegVal);
1976 udelay(10);
1977 }
1978
Sujithf1dc5602008-10-29 10:16:30 +05301979 if (setChip) {
1980 if ((REG_READ(ah, AR_RTC_STATUS) &
1981 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1982 if (ath9k_hw_set_reset_reg(ah,
1983 ATH9K_RESET_POWER_ON) != true) {
1984 return false;
1985 }
Luis R. Rodrigueze0412282010-04-15 17:38:15 -04001986 if (!AR_SREV_9300_20_OR_LATER(ah))
1987 ath9k_hw_init_pll(ah, NULL);
Sujithf1dc5602008-10-29 10:16:30 +05301988 }
1989 if (AR_SREV_9100(ah))
1990 REG_SET_BIT(ah, AR_RTC_RESET,
1991 AR_RTC_RESET_EN);
1992
1993 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1994 AR_RTC_FORCE_WAKE_EN);
1995 udelay(50);
1996
1997 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1998 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1999 if (val == AR_RTC_STATUS_ON)
2000 break;
2001 udelay(50);
2002 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2003 AR_RTC_FORCE_WAKE_EN);
2004 }
2005 if (i == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002006 ath_err(ath9k_hw_common(ah),
2007 "Failed to wakeup in %uus\n",
2008 POWER_UP_TIME / 20);
Sujithf1dc5602008-10-29 10:16:30 +05302009 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002010 }
2011 }
2012
Sujithf1dc5602008-10-29 10:16:30 +05302013 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2014
2015 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002016}
2017
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002018bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302019{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002020 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +05302021 int status = true, setChip = true;
Sujithf1dc5602008-10-29 10:16:30 +05302022 static const char *modes[] = {
2023 "AWAKE",
2024 "FULL-SLEEP",
2025 "NETWORK SLEEP",
2026 "UNDEFINED"
2027 };
Sujithf1dc5602008-10-29 10:16:30 +05302028
Gabor Juhoscbdec972009-07-24 17:27:22 +02002029 if (ah->power_mode == mode)
2030 return status;
2031
Joe Perchesd2182b62011-12-15 14:55:53 -08002032 ath_dbg(common, RESET, "%s -> %s\n",
Joe Perches226afe62010-12-02 19:12:37 -08002033 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302034
2035 switch (mode) {
2036 case ATH9K_PM_AWAKE:
2037 status = ath9k_hw_set_power_awake(ah, setChip);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302038
2039 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2040 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2041
Sujithf1dc5602008-10-29 10:16:30 +05302042 break;
2043 case ATH9K_PM_FULL_SLEEP:
Sujith Manoharand1ca8b82012-02-22 12:41:01 +05302044 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2045 ar9003_mci_set_full_sleep(ah);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302046
Sujithf1dc5602008-10-29 10:16:30 +05302047 ath9k_set_power_sleep(ah, setChip);
Sujith2660b812009-02-09 13:27:26 +05302048 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302049 break;
2050 case ATH9K_PM_NETWORK_SLEEP:
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302051
2052 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2053 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2054
Sujithf1dc5602008-10-29 10:16:30 +05302055 ath9k_set_power_network_sleep(ah, setChip);
2056 break;
2057 default:
Joe Perches38002762010-12-02 19:12:36 -08002058 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302059 return false;
2060 }
Sujith2660b812009-02-09 13:27:26 +05302061 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302062
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002063 /*
2064 * XXX: If this warning never comes up after a while then
2065 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2066 * ath9k_hw_setpower() return type void.
2067 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05302068
2069 if (!(ah->ah_flags & AH_UNPLUGGED))
2070 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002071
Sujithf1dc5602008-10-29 10:16:30 +05302072 return status;
2073}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002074EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302075
Sujithf1dc5602008-10-29 10:16:30 +05302076/*******************/
2077/* Beacon Handling */
2078/*******************/
2079
Sujithcbe61d82009-02-09 13:27:12 +05302080void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002081{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002082 int flags = 0;
2083
Sujith7d0d0df2010-04-16 11:53:57 +05302084 ENABLE_REGWRITE_BUFFER(ah);
2085
Sujith2660b812009-02-09 13:27:26 +05302086 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002087 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04002088 case NL80211_IFTYPE_MESH_POINT:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002089 REG_SET_BIT(ah, AR_TXCFG,
2090 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
Felix Fietkaudd347f22011-03-22 21:54:17 +01002091 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2092 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002093 flags |= AR_NDP_TIMER_EN;
Colin McCabed97809d2008-12-01 13:38:55 -08002094 case NL80211_IFTYPE_AP:
Felix Fietkaudd347f22011-03-22 21:54:17 +01002095 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2096 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2097 TU_TO_USEC(ah->config.dma_beacon_response_time));
2098 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2099 TU_TO_USEC(ah->config.sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002100 flags |=
2101 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2102 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002103 default:
Joe Perchesd2182b62011-12-15 14:55:53 -08002104 ath_dbg(ath9k_hw_common(ah), BEACON,
2105 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002106 return;
2107 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002108 }
2109
Felix Fietkaudd347f22011-03-22 21:54:17 +01002110 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2111 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2112 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2113 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002114
Sujith7d0d0df2010-04-16 11:53:57 +05302115 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302116
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002117 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2118}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002119EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002120
Sujithcbe61d82009-02-09 13:27:12 +05302121void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302122 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002123{
2124 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302125 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002126 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002127
Sujith7d0d0df2010-04-16 11:53:57 +05302128 ENABLE_REGWRITE_BUFFER(ah);
2129
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002130 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2131
2132 REG_WRITE(ah, AR_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302133 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002134 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302135 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002136
Sujith7d0d0df2010-04-16 11:53:57 +05302137 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302138
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002139 REG_RMW_FIELD(ah, AR_RSSI_THR,
2140 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2141
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302142 beaconintval = bs->bs_intval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002143
2144 if (bs->bs_sleepduration > beaconintval)
2145 beaconintval = bs->bs_sleepduration;
2146
2147 dtimperiod = bs->bs_dtimperiod;
2148 if (bs->bs_sleepduration > dtimperiod)
2149 dtimperiod = bs->bs_sleepduration;
2150
2151 if (beaconintval == dtimperiod)
2152 nextTbtt = bs->bs_nextdtim;
2153 else
2154 nextTbtt = bs->bs_nexttbtt;
2155
Joe Perchesd2182b62011-12-15 14:55:53 -08002156 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2157 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2158 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2159 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002160
Sujith7d0d0df2010-04-16 11:53:57 +05302161 ENABLE_REGWRITE_BUFFER(ah);
2162
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002163 REG_WRITE(ah, AR_NEXT_DTIM,
2164 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2165 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2166
2167 REG_WRITE(ah, AR_SLEEP1,
2168 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2169 | AR_SLEEP1_ASSUME_DTIM);
2170
Sujith60b67f52008-08-07 10:52:38 +05302171 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002172 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2173 else
2174 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2175
2176 REG_WRITE(ah, AR_SLEEP2,
2177 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2178
2179 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2180 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2181
Sujith7d0d0df2010-04-16 11:53:57 +05302182 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302183
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002184 REG_SET_BIT(ah, AR_TIMER_MODE,
2185 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2186 AR_DTIM_TIMER_EN);
2187
Sujith4af9cf42009-02-12 10:06:47 +05302188 /* TSF Out of Range Threshold */
2189 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002190}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002191EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002192
Sujithf1dc5602008-10-29 10:16:30 +05302193/*******************/
2194/* HW Capabilities */
2195/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002196
Felix Fietkau60540692011-07-19 08:46:44 +02002197static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2198{
2199 eeprom_chainmask &= chip_chainmask;
2200 if (eeprom_chainmask)
2201 return eeprom_chainmask;
2202 else
2203 return chip_chainmask;
2204}
2205
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002206/**
2207 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2208 * @ah: the atheros hardware data structure
2209 *
2210 * We enable DFS support upstream on chipsets which have passed a series
2211 * of tests. The testing requirements are going to be documented. Desired
2212 * test requirements are documented at:
2213 *
2214 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2215 *
2216 * Once a new chipset gets properly tested an individual commit can be used
2217 * to document the testing for DFS for that chipset.
2218 */
2219static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2220{
2221
2222 switch (ah->hw_version.macVersion) {
2223 /* AR9580 will likely be our first target to get testing on */
2224 case AR_SREV_VERSION_9580:
2225 default:
2226 return false;
2227 }
2228}
2229
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002230int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002231{
Sujith2660b812009-02-09 13:27:26 +05302232 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002233 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002234 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau60540692011-07-19 08:46:44 +02002235 unsigned int chip_chainmask;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002236
Sujith Manoharan0ff2b5c2011-04-20 11:00:34 +05302237 u16 eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002238 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002239
Sujithf74df6f2009-02-09 13:27:24 +05302240 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002241 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05302242
Sujith2660b812009-02-09 13:27:26 +05302243 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05302244 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002245 if (regulatory->current_rd == 0x64 ||
2246 regulatory->current_rd == 0x65)
2247 regulatory->current_rd += 5;
2248 else if (regulatory->current_rd == 0x41)
2249 regulatory->current_rd = 0x43;
Joe Perchesd2182b62011-12-15 14:55:53 -08002250 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2251 regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002252 }
Sujithdc2222a2008-08-14 13:26:55 +05302253
Sujithf74df6f2009-02-09 13:27:24 +05302254 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002255 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002256 ath_err(common,
2257 "no band has been marked as supported in EEPROM\n");
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002258 return -EINVAL;
2259 }
2260
Felix Fietkaud4659912010-10-14 16:02:39 +02002261 if (eeval & AR5416_OPFLAGS_11A)
2262 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002263
Felix Fietkaud4659912010-10-14 16:02:39 +02002264 if (eeval & AR5416_OPFLAGS_11G)
2265 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
Sujithf1dc5602008-10-29 10:16:30 +05302266
Felix Fietkau60540692011-07-19 08:46:44 +02002267 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2268 chip_chainmask = 1;
Mohammed Shafi Shajakhanba5736a2011-11-30 21:10:52 +05302269 else if (AR_SREV_9462(ah))
2270 chip_chainmask = 3;
Felix Fietkau60540692011-07-19 08:46:44 +02002271 else if (!AR_SREV_9280_20_OR_LATER(ah))
2272 chip_chainmask = 7;
2273 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2274 chip_chainmask = 3;
2275 else
2276 chip_chainmask = 7;
2277
Sujithf74df6f2009-02-09 13:27:24 +05302278 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002279 /*
2280 * For AR9271 we will temporarilly uses the rx chainmax as read from
2281 * the EEPROM.
2282 */
Sujith8147f5d2009-02-20 15:13:23 +05302283 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002284 !(eeval & AR5416_OPFLAGS_11A) &&
2285 !(AR_SREV_9271(ah)))
2286 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05302287 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
Felix Fietkau598cdd52011-03-19 13:55:42 +01002288 else if (AR_SREV_9100(ah))
2289 pCap->rx_chainmask = 0x7;
Sujith8147f5d2009-02-20 15:13:23 +05302290 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002291 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05302292 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05302293
Felix Fietkau60540692011-07-19 08:46:44 +02002294 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2295 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
Felix Fietkau82b2d332011-09-03 01:40:23 +02002296 ah->txchainmask = pCap->tx_chainmask;
2297 ah->rxchainmask = pCap->rx_chainmask;
Felix Fietkau60540692011-07-19 08:46:44 +02002298
Felix Fietkau7a370812010-09-22 12:34:52 +02002299 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05302300
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01002301 /* enable key search for every frame in an aggregate */
2302 if (AR_SREV_9300_20_OR_LATER(ah))
2303 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2304
Bruno Randolfce2220d2010-09-17 11:36:25 +09002305 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2306
Felix Fietkau0db156e2011-03-23 20:57:29 +01002307 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
Sujithf1dc5602008-10-29 10:16:30 +05302308 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2309 else
2310 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2311
Sujith5b5fa352010-03-17 14:25:15 +05302312 if (AR_SREV_9271(ah))
2313 pCap->num_gpio_pins = AR9271_NUM_GPIO;
Sujith88c1f4f2010-06-30 14:46:31 +05302314 else if (AR_DEVID_7010(ah))
2315 pCap->num_gpio_pins = AR7010_NUM_GPIO;
Mohammed Shafi Shajakhan6321eb02011-09-30 11:31:27 +05302316 else if (AR_SREV_9300_20_OR_LATER(ah))
2317 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2318 else if (AR_SREV_9287_11_OR_LATER(ah))
2319 pCap->num_gpio_pins = AR9287_NUM_GPIO;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002320 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302321 pCap->num_gpio_pins = AR9285_NUM_GPIO;
Felix Fietkau7a370812010-09-22 12:34:52 +02002322 else if (AR_SREV_9280_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302323 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2324 else
2325 pCap->num_gpio_pins = AR_NUM_GPIO;
2326
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302327 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302328 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302329 else
Sujithf1dc5602008-10-29 10:16:30 +05302330 pCap->rts_aggr_limit = (8 * 1024);
Sujithf1dc5602008-10-29 10:16:30 +05302331
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302332#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05302333 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2334 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2335 ah->rfkill_gpio =
2336 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2337 ah->rfkill_polarity =
2338 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05302339
2340 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2341 }
2342#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07002343 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05302344 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2345 else
2346 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05302347
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05302348 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302349 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2350 else
2351 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2352
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002353 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002354 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
Gabor Juhos0e707a92011-06-21 11:23:31 +02002355 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002356 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2357
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002358 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2359 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2360 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002361 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04002362 pCap->txs_len = sizeof(struct ar9003_txs);
Luis R. Rodriguez6f481012011-01-20 17:47:39 -08002363 if (!ah->config.paprd_disable &&
2364 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
Felix Fietkau49352502010-06-12 00:33:59 -04002365 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002366 } else {
2367 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkaua949b172011-07-09 11:12:47 +07002368 if (AR_SREV_9280_20(ah))
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04002369 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002370 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04002371
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04002372 if (AR_SREV_9300_20_OR_LATER(ah))
2373 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2374
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08002375 if (AR_SREV_9300_20_OR_LATER(ah))
2376 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2377
Felix Fietkaua42acef2010-09-22 12:34:54 +02002378 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07002379 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2380
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002381 if (AR_SREV_9285(ah))
2382 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2383 ant_div_ctl1 =
2384 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2385 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2386 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2387 }
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05302388 if (AR_SREV_9300_20_OR_LATER(ah)) {
2389 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2390 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2391 }
2392
2393
Gabor Juhos431da562011-06-21 11:23:41 +02002394 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302395 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2396 /*
2397 * enable the diversity-combining algorithm only when
2398 * both enable_lna_div and enable_fast_div are set
2399 * Table for Diversity
2400 * ant_div_alt_lnaconf bit 0-1
2401 * ant_div_main_lnaconf bit 2-3
2402 * ant_div_alt_gaintb bit 4
2403 * ant_div_main_gaintb bit 5
2404 * enable_ant_div_lnadiv bit 6
2405 * enable_ant_fast_div bit 7
2406 */
2407 if ((ant_div_ctl1 >> 0x6) == 0x3)
2408 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2409 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002410
Vasanthakumar Thiagarajan8060e162010-12-06 04:27:42 -08002411 if (AR_SREV_9485_10(ah)) {
2412 pCap->pcie_lcr_extsync_en = true;
2413 pCap->pcie_lcr_offset = 0x80;
2414 }
2415
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002416 if (ath9k_hw_dfs_tested(ah))
2417 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2418
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002419 tx_chainmask = pCap->tx_chainmask;
2420 rx_chainmask = pCap->rx_chainmask;
2421 while (tx_chainmask || rx_chainmask) {
2422 if (tx_chainmask & BIT(0))
2423 pCap->max_txchains++;
2424 if (rx_chainmask & BIT(0))
2425 pCap->max_rxchains++;
2426
2427 tx_chainmask >>= 1;
2428 rx_chainmask >>= 1;
2429 }
2430
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302431 if (AR_SREV_9300_20_OR_LATER(ah)) {
2432 ah->enabled_cals |= TX_IQ_CAL;
Mohammed Shafi Shajakhan6fea5932011-11-30 21:01:31 +05302433 if (AR_SREV_9485_OR_LATER(ah))
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302434 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2435 }
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302436
2437 if (AR_SREV_9462(ah)) {
2438
2439 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2440 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2441
2442 if (AR_SREV_9462_20(ah))
2443 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2444
2445 }
2446
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +05302447
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002448 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002449}
2450
Sujithf1dc5602008-10-29 10:16:30 +05302451/****************************/
2452/* GPIO / RFKILL / Antennae */
2453/****************************/
2454
Sujithcbe61d82009-02-09 13:27:12 +05302455static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302456 u32 gpio, u32 type)
2457{
2458 int addr;
2459 u32 gpio_shift, tmp;
2460
2461 if (gpio > 11)
2462 addr = AR_GPIO_OUTPUT_MUX3;
2463 else if (gpio > 5)
2464 addr = AR_GPIO_OUTPUT_MUX2;
2465 else
2466 addr = AR_GPIO_OUTPUT_MUX1;
2467
2468 gpio_shift = (gpio % 6) * 5;
2469
2470 if (AR_SREV_9280_20_OR_LATER(ah)
2471 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2472 REG_RMW(ah, addr, (type << gpio_shift),
2473 (0x1f << gpio_shift));
2474 } else {
2475 tmp = REG_READ(ah, addr);
2476 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2477 tmp &= ~(0x1f << gpio_shift);
2478 tmp |= (type << gpio_shift);
2479 REG_WRITE(ah, addr, tmp);
2480 }
2481}
2482
Sujithcbe61d82009-02-09 13:27:12 +05302483void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302484{
2485 u32 gpio_shift;
2486
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07002487 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302488
Sujith88c1f4f2010-06-30 14:46:31 +05302489 if (AR_DEVID_7010(ah)) {
2490 gpio_shift = gpio;
2491 REG_RMW(ah, AR7010_GPIO_OE,
2492 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2493 (AR7010_GPIO_OE_MASK << gpio_shift));
2494 return;
2495 }
Sujithf1dc5602008-10-29 10:16:30 +05302496
Sujith88c1f4f2010-06-30 14:46:31 +05302497 gpio_shift = gpio << 1;
Sujithf1dc5602008-10-29 10:16:30 +05302498 REG_RMW(ah,
2499 AR_GPIO_OE_OUT,
2500 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2501 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2502}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002503EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05302504
Sujithcbe61d82009-02-09 13:27:12 +05302505u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302506{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302507#define MS_REG_READ(x, y) \
2508 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2509
Sujith2660b812009-02-09 13:27:26 +05302510 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05302511 return 0xffffffff;
2512
Sujith88c1f4f2010-06-30 14:46:31 +05302513 if (AR_DEVID_7010(ah)) {
2514 u32 val;
2515 val = REG_READ(ah, AR7010_GPIO_IN);
2516 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2517 } else if (AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan93069902010-11-30 23:24:09 -08002518 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2519 AR_GPIO_BIT(gpio)) != 0;
Felix Fietkau783dfca2010-04-15 17:38:11 -04002520 else if (AR_SREV_9271(ah))
Sujith5b5fa352010-03-17 14:25:15 +05302521 return MS_REG_READ(AR9271, gpio) != 0;
Felix Fietkaua42acef2010-09-22 12:34:54 +02002522 else if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302523 return MS_REG_READ(AR9287, gpio) != 0;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002524 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302525 return MS_REG_READ(AR9285, gpio) != 0;
Felix Fietkau7a370812010-09-22 12:34:52 +02002526 else if (AR_SREV_9280_20_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302527 return MS_REG_READ(AR928X, gpio) != 0;
2528 else
2529 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05302530}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002531EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302532
Sujithcbe61d82009-02-09 13:27:12 +05302533void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05302534 u32 ah_signal_type)
2535{
2536 u32 gpio_shift;
2537
Sujith88c1f4f2010-06-30 14:46:31 +05302538 if (AR_DEVID_7010(ah)) {
2539 gpio_shift = gpio;
2540 REG_RMW(ah, AR7010_GPIO_OE,
2541 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2542 (AR7010_GPIO_OE_MASK << gpio_shift));
2543 return;
2544 }
2545
Sujithf1dc5602008-10-29 10:16:30 +05302546 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
Sujithf1dc5602008-10-29 10:16:30 +05302547 gpio_shift = 2 * gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302548 REG_RMW(ah,
2549 AR_GPIO_OE_OUT,
2550 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2551 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2552}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002553EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05302554
Sujithcbe61d82009-02-09 13:27:12 +05302555void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302556{
Sujith88c1f4f2010-06-30 14:46:31 +05302557 if (AR_DEVID_7010(ah)) {
2558 val = val ? 0 : 1;
2559 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2560 AR_GPIO_BIT(gpio));
2561 return;
2562 }
2563
Sujith5b5fa352010-03-17 14:25:15 +05302564 if (AR_SREV_9271(ah))
2565 val = ~val;
2566
Sujithf1dc5602008-10-29 10:16:30 +05302567 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2568 AR_GPIO_BIT(gpio));
2569}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002570EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302571
Sujithcbe61d82009-02-09 13:27:12 +05302572u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302573{
2574 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2575}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002576EXPORT_SYMBOL(ath9k_hw_getdefantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302577
Sujithcbe61d82009-02-09 13:27:12 +05302578void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302579{
2580 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2581}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002582EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302583
Sujithf1dc5602008-10-29 10:16:30 +05302584/*********************/
2585/* General Operation */
2586/*********************/
2587
Sujithcbe61d82009-02-09 13:27:12 +05302588u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302589{
2590 u32 bits = REG_READ(ah, AR_RX_FILTER);
2591 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2592
2593 if (phybits & AR_PHY_ERR_RADAR)
2594 bits |= ATH9K_RX_FILTER_PHYRADAR;
2595 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2596 bits |= ATH9K_RX_FILTER_PHYERR;
2597
2598 return bits;
2599}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002600EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302601
Sujithcbe61d82009-02-09 13:27:12 +05302602void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302603{
2604 u32 phybits;
2605
Sujith7d0d0df2010-04-16 11:53:57 +05302606 ENABLE_REGWRITE_BUFFER(ah);
2607
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302608 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302609 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2610
Sujith7ea310b2009-09-03 12:08:43 +05302611 REG_WRITE(ah, AR_RX_FILTER, bits);
2612
Sujithf1dc5602008-10-29 10:16:30 +05302613 phybits = 0;
2614 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2615 phybits |= AR_PHY_ERR_RADAR;
2616 if (bits & ATH9K_RX_FILTER_PHYERR)
2617 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2618 REG_WRITE(ah, AR_PHY_ERR, phybits);
2619
2620 if (phybits)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002621 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujithf1dc5602008-10-29 10:16:30 +05302622 else
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002623 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302624
2625 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302626}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002627EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302628
Sujithcbe61d82009-02-09 13:27:12 +05302629bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302630{
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302631 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2632 return false;
2633
2634 ath9k_hw_init_pll(ah, NULL);
Felix Fietkau8efa7a82012-03-14 16:40:23 +01002635 ah->htc_reset_init = true;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302636 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302637}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002638EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302639
Sujithcbe61d82009-02-09 13:27:12 +05302640bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302641{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002642 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302643 return false;
2644
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302645 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2646 return false;
2647
2648 ath9k_hw_init_pll(ah, NULL);
2649 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302650}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002651EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302652
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002653static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05302654{
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002655 enum eeprom_param gain_param;
Felix Fietkau9c204b42011-07-27 15:01:05 +02002656
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002657 if (IS_CHAN_2GHZ(chan))
2658 gain_param = EEP_ANTENNA_GAIN_2G;
2659 else
2660 gain_param = EEP_ANTENNA_GAIN_5G;
Sujithf1dc5602008-10-29 10:16:30 +05302661
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002662 return ah->eep_ops->get_eeprom(ah, gain_param);
2663}
2664
2665void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2666{
2667 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2668 struct ieee80211_channel *channel;
2669 int chan_pwr, new_pwr, max_gain;
2670 int ant_gain, ant_reduction = 0;
2671
2672 if (!chan)
2673 return;
2674
2675 channel = chan->chan;
2676 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2677 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2678 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2679
2680 ant_gain = get_antenna_gain(ah, chan);
2681 if (ant_gain > max_gain)
2682 ant_reduction = ant_gain - max_gain;
Sujithf1dc5602008-10-29 10:16:30 +05302683
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002684 ah->eep_ops->set_txpower(ah, chan,
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002685 ath9k_regd_get_ctl(reg, chan),
2686 ant_reduction, new_pwr, false);
2687}
2688
2689void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2690{
2691 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2692 struct ath9k_channel *chan = ah->curchan;
2693 struct ieee80211_channel *channel = chan->chan;
2694
Dan Carpenter48ef5c42011-10-17 10:28:23 +03002695 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002696 if (test)
2697 channel->max_power = MAX_RATE_POWER / 2;
2698
2699 ath9k_hw_apply_txpower(ah, chan);
2700
2701 if (test)
2702 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
Sujithf1dc5602008-10-29 10:16:30 +05302703}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002704EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302705
Sujithcbe61d82009-02-09 13:27:12 +05302706void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302707{
Sujith2660b812009-02-09 13:27:26 +05302708 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302709}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002710EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302711
Sujithcbe61d82009-02-09 13:27:12 +05302712void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302713{
2714 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2715 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2716}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002717EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302718
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002719void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302720{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002721 struct ath_common *common = ath9k_hw_common(ah);
2722
2723 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2724 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2725 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302726}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002727EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302728
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002729#define ATH9K_MAX_TSF_READ 10
2730
Sujithcbe61d82009-02-09 13:27:12 +05302731u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302732{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002733 u32 tsf_lower, tsf_upper1, tsf_upper2;
2734 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302735
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002736 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2737 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2738 tsf_lower = REG_READ(ah, AR_TSF_L32);
2739 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2740 if (tsf_upper2 == tsf_upper1)
2741 break;
2742 tsf_upper1 = tsf_upper2;
2743 }
Sujithf1dc5602008-10-29 10:16:30 +05302744
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002745 WARN_ON( i == ATH9K_MAX_TSF_READ );
2746
2747 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302748}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002749EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302750
Sujithcbe61d82009-02-09 13:27:12 +05302751void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002752{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002753 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002754 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002755}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002756EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002757
Sujithcbe61d82009-02-09 13:27:12 +05302758void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302759{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002760 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2761 AH_TSF_WRITE_TIMEOUT))
Joe Perchesd2182b62011-12-15 14:55:53 -08002762 ath_dbg(ath9k_hw_common(ah), RESET,
Joe Perches226afe62010-12-02 19:12:37 -08002763 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002764
Sujithf1dc5602008-10-29 10:16:30 +05302765 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002766}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002767EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002768
Sujith54e4cec2009-08-07 09:45:09 +05302769void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002770{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002771 if (setting)
Sujith2660b812009-02-09 13:27:26 +05302772 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002773 else
Sujith2660b812009-02-09 13:27:26 +05302774 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002775}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002776EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002777
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002778void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002779{
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002780 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +05302781 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002782
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002783 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05302784 macmode = AR_2040_JOINED_RX_CLEAR;
2785 else
2786 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002787
Sujithf1dc5602008-10-29 10:16:30 +05302788 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002789}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302790
2791/* HW Generic timers configuration */
2792
2793static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2794{
2795 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2796 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2797 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2798 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2799 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2800 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2801 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2802 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2803 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2804 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2805 AR_NDP2_TIMER_MODE, 0x0002},
2806 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2807 AR_NDP2_TIMER_MODE, 0x0004},
2808 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2809 AR_NDP2_TIMER_MODE, 0x0008},
2810 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2811 AR_NDP2_TIMER_MODE, 0x0010},
2812 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2813 AR_NDP2_TIMER_MODE, 0x0020},
2814 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2815 AR_NDP2_TIMER_MODE, 0x0040},
2816 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2817 AR_NDP2_TIMER_MODE, 0x0080}
2818};
2819
2820/* HW generic timer primitives */
2821
2822/* compute and clear index of rightmost 1 */
2823static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2824{
2825 u32 b;
2826
2827 b = *mask;
2828 b &= (0-b);
2829 *mask &= ~b;
2830 b *= debruijn32;
2831 b >>= 27;
2832
2833 return timer_table->gen_timer_index[b];
2834}
2835
Felix Fietkaudd347f22011-03-22 21:54:17 +01002836u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302837{
2838 return REG_READ(ah, AR_TSF_L32);
2839}
Felix Fietkaudd347f22011-03-22 21:54:17 +01002840EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302841
2842struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2843 void (*trigger)(void *),
2844 void (*overflow)(void *),
2845 void *arg,
2846 u8 timer_index)
2847{
2848 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2849 struct ath_gen_timer *timer;
2850
2851 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2852
2853 if (timer == NULL) {
Joe Perches38002762010-12-02 19:12:36 -08002854 ath_err(ath9k_hw_common(ah),
2855 "Failed to allocate memory for hw timer[%d]\n",
2856 timer_index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302857 return NULL;
2858 }
2859
2860 /* allocate a hardware generic timer slot */
2861 timer_table->timers[timer_index] = timer;
2862 timer->index = timer_index;
2863 timer->trigger = trigger;
2864 timer->overflow = overflow;
2865 timer->arg = arg;
2866
2867 return timer;
2868}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002869EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302870
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002871void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2872 struct ath_gen_timer *timer,
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302873 u32 trig_timeout,
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002874 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302875{
2876 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302877 u32 tsf, timer_next;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302878
2879 BUG_ON(!timer_period);
2880
2881 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2882
2883 tsf = ath9k_hw_gettsf32(ah);
2884
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302885 timer_next = tsf + trig_timeout;
2886
Joe Perchesd2182b62011-12-15 14:55:53 -08002887 ath_dbg(ath9k_hw_common(ah), HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08002888 "current tsf %x period %x timer_next %x\n",
2889 tsf, timer_period, timer_next);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302890
2891 /*
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302892 * Program generic timer registers
2893 */
2894 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2895 timer_next);
2896 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2897 timer_period);
2898 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2899 gen_tmr_configuration[timer->index].mode_mask);
2900
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302901 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302902 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302903 * Starting from AR9462, each generic timer can select which tsf
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302904 * to use. But we still follow the old rule, 0 - 7 use tsf and
2905 * 8 - 15 use tsf2.
2906 */
2907 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2908 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2909 (1 << timer->index));
2910 else
2911 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2912 (1 << timer->index));
2913 }
2914
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302915 /* Enable both trigger and thresh interrupt masks */
2916 REG_SET_BIT(ah, AR_IMR_S5,
2917 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2918 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302919}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002920EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302921
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002922void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302923{
2924 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2925
2926 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2927 (timer->index >= ATH_MAX_GEN_TIMER)) {
2928 return;
2929 }
2930
2931 /* Clear generic timer enable bits. */
2932 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2933 gen_tmr_configuration[timer->index].mode_mask);
2934
2935 /* Disable both trigger and thresh interrupt masks */
2936 REG_CLR_BIT(ah, AR_IMR_S5,
2937 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2938 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2939
2940 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302941}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002942EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302943
2944void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2945{
2946 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2947
2948 /* free the hardware generic timer slot */
2949 timer_table->timers[timer->index] = NULL;
2950 kfree(timer);
2951}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002952EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302953
2954/*
2955 * Generic Timer Interrupts handling
2956 */
2957void ath_gen_timer_isr(struct ath_hw *ah)
2958{
2959 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2960 struct ath_gen_timer *timer;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002961 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302962 u32 trigger_mask, thresh_mask, index;
2963
2964 /* get hardware generic timer interrupt status */
2965 trigger_mask = ah->intr_gen_timer_trigger;
2966 thresh_mask = ah->intr_gen_timer_thresh;
2967 trigger_mask &= timer_table->timer_mask.val;
2968 thresh_mask &= timer_table->timer_mask.val;
2969
2970 trigger_mask &= ~thresh_mask;
2971
2972 while (thresh_mask) {
2973 index = rightmost_index(timer_table, &thresh_mask);
2974 timer = timer_table->timers[index];
2975 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08002976 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
2977 index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302978 timer->overflow(timer->arg);
2979 }
2980
2981 while (trigger_mask) {
2982 index = rightmost_index(timer_table, &trigger_mask);
2983 timer = timer_table->timers[index];
2984 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08002985 ath_dbg(common, HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08002986 "Gen timer[%d] trigger\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302987 timer->trigger(timer->arg);
2988 }
2989}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002990EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002991
Sujith05020d22010-03-17 14:25:23 +05302992/********/
2993/* HTC */
2994/********/
2995
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002996static struct {
2997 u32 version;
2998 const char * name;
2999} ath_mac_bb_names[] = {
3000 /* Devices with external radios */
3001 { AR_SREV_VERSION_5416_PCI, "5416" },
3002 { AR_SREV_VERSION_5416_PCIE, "5418" },
3003 { AR_SREV_VERSION_9100, "9100" },
3004 { AR_SREV_VERSION_9160, "9160" },
3005 /* Single-chip solutions */
3006 { AR_SREV_VERSION_9280, "9280" },
3007 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003008 { AR_SREV_VERSION_9287, "9287" },
3009 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04003010 { AR_SREV_VERSION_9300, "9300" },
Gabor Juhos2c8e5932011-06-21 11:23:21 +02003011 { AR_SREV_VERSION_9330, "9330" },
Florian Fainelli397e5d52011-08-25 21:33:48 +02003012 { AR_SREV_VERSION_9340, "9340" },
Senthil Balasubramanian8f06ca22011-04-01 17:16:33 +05303013 { AR_SREV_VERSION_9485, "9485" },
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303014 { AR_SREV_VERSION_9462, "9462" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003015};
3016
3017/* For devices with external radios */
3018static struct {
3019 u16 version;
3020 const char * name;
3021} ath_rf_names[] = {
3022 { 0, "5133" },
3023 { AR_RAD5133_SREV_MAJOR, "5133" },
3024 { AR_RAD5122_SREV_MAJOR, "5122" },
3025 { AR_RAD2133_SREV_MAJOR, "2133" },
3026 { AR_RAD2122_SREV_MAJOR, "2122" }
3027};
3028
3029/*
3030 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3031 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003032static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003033{
3034 int i;
3035
3036 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3037 if (ath_mac_bb_names[i].version == mac_bb_version) {
3038 return ath_mac_bb_names[i].name;
3039 }
3040 }
3041
3042 return "????";
3043}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003044
3045/*
3046 * Return the RF name. "????" is returned if the RF is unknown.
3047 * Used for devices with external radios.
3048 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003049static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003050{
3051 int i;
3052
3053 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3054 if (ath_rf_names[i].version == rf_version) {
3055 return ath_rf_names[i].name;
3056 }
3057 }
3058
3059 return "????";
3060}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003061
3062void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3063{
3064 int used;
3065
3066 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02003067 if (AR_SREV_9280_20_OR_LATER(ah)) {
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003068 used = snprintf(hw_name, len,
3069 "Atheros AR%s Rev:%x",
3070 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3071 ah->hw_version.macRev);
3072 }
3073 else {
3074 used = snprintf(hw_name, len,
3075 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3076 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3077 ah->hw_version.macRev,
3078 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3079 AR_RADIO_SREV_MAJOR)),
3080 ah->hw_version.phyRev);
3081 }
3082
3083 hw_name[used] = '\0';
3084}
3085EXPORT_SYMBOL(ath9k_hw_name);