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gerrit-public.fairphone.software / kernel / msm-4.19 / e3bc5358e0977b95652625f9329ba68f1ebb1a42 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 21fcc440fc1a9d886d408701a705ad4daabd2325 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]106 prcm: prcm@200000 {
107 compatible = "ti,am3-prcm";
108 reg = <0x200000 0x4000>;
109
110 prcm_clocks: clocks {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 };
114
115 prcm_clockdomains: clockdomains {
116 };
117 };
118
119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]122 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]149 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]150 };
151
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]152 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]153 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]154 interrupt-controller;
155 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 reg = <0x48200000 0x1000>;
157 };
158
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]159 edma: edma@49000000 {
160 compatible = "ti,edma3";
161 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
162 reg = <0x49000000 0x10000>,
Thomas Gleixnercf7eb972014-04-13 20:44:46 +0200[diff] [blame]163 <0x44e10f90 0x40>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]164 interrupts = <12 13 14>;
165 #dma-cells = <1>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]166 };
167
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]168 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]169 compatible = "ti,omap4-gpio";
170 ti,hwmods = "gpio1";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]174 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]176 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 };
178
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]179 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 compatible = "ti,omap4-gpio";
181 ti,hwmods = "gpio2";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]185 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]186 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]187 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]188 };
189
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]190 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]191 compatible = "ti,omap4-gpio";
192 ti,hwmods = "gpio3";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]196 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]198 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]199 };
200
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]201 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]202 compatible = "ti,omap4-gpio";
203 ti,hwmods = "gpio4";
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]207 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]208 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]210 };
211
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]212 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]213 compatible = "ti,omap3-uart";
214 ti,hwmods = "uart1";
215 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]216 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]218 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]219 dmas = <&edma 26>, <&edma 27>;
220 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]221 };
222
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]223 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]224 compatible = "ti,omap3-uart";
225 ti,hwmods = "uart2";
226 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]228 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]229 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]230 dmas = <&edma 28>, <&edma 29>;
231 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]232 };
233
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]234 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]235 compatible = "ti,omap3-uart";
236 ti,hwmods = "uart3";
237 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]238 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]239 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]240 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]241 dmas = <&edma 30>, <&edma 31>;
242 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]243 };
244
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]245 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]246 compatible = "ti,omap3-uart";
247 ti,hwmods = "uart4";
248 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]249 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]250 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]251 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]252 };
253
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]254 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]255 compatible = "ti,omap3-uart";
256 ti,hwmods = "uart5";
257 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]258 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]259 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]260 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]261 };
262
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]263 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]264 compatible = "ti,omap3-uart";
265 ti,hwmods = "uart6";
266 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]267 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]268 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]269 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]270 };
271
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]272 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]273 compatible = "ti,omap4-i2c";
274 #address-cells = <1>;
275 #size-cells = <0>;
276 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]277 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]278 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]279 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]280 };
281
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]282 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]283 compatible = "ti,omap4-i2c";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]287 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]288 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]289 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]290 };
291
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]292 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]293 compatible = "ti,omap4-i2c";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]297 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]298 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]299 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]300 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]301
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]302 mmc1: mmc@48060000 {
303 compatible = "ti,omap4-hsmmc";
304 ti,hwmods = "mmc1";
305 ti,dual-volt;
306 ti,needs-special-reset;
307 ti,needs-special-hs-handling;
308 dmas = <&edma 24
309 &edma 25>;
310 dma-names = "tx", "rx";
311 interrupts = <64>;
312 interrupt-parent = <&intc>;
313 reg = <0x48060000 0x1000>;
314 status = "disabled";
315 };
316
317 mmc2: mmc@481d8000 {
318 compatible = "ti,omap4-hsmmc";
319 ti,hwmods = "mmc2";
320 ti,needs-special-reset;
321 dmas = <&edma 2
322 &edma 3>;
323 dma-names = "tx", "rx";
324 interrupts = <28>;
325 interrupt-parent = <&intc>;
326 reg = <0x481d8000 0x1000>;
327 status = "disabled";
328 };
329
330 mmc3: mmc@47810000 {
331 compatible = "ti,omap4-hsmmc";
332 ti,hwmods = "mmc3";
333 ti,needs-special-reset;
334 interrupts = <29>;
335 interrupt-parent = <&intc>;
336 reg = <0x47810000 0x1000>;
337 status = "disabled";
338 };
339
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]340 hwspinlock: spinlock@480ca000 {
341 compatible = "ti,omap4-hwspinlock";
342 reg = <0x480ca000 0x1000>;
343 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]344 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]345 };
346
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]347 wdt2: wdt@44e35000 {
348 compatible = "ti,omap3-wdt";
349 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]350 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]351 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]352 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]353
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]354 dcan0: can@481cc000 {
355 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]356 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]357 reg = <0x481cc000 0x2000>;
358 clocks = <&dcan0_fck>;
359 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]360 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]361 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]362 status = "disabled";
363 };
364
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]365 dcan1: can@481d0000 {
366 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]367 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]368 reg = <0x481d0000 0x2000>;
369 clocks = <&dcan1_fck>;
370 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]371 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]372 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]373 status = "disabled";
374 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]375
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]376 mailbox: mailbox@480C8000 {
377 compatible = "ti,omap4-mailbox";
378 reg = <0x480C8000 0x200>;
379 interrupts = <77>;
380 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]381 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]382 ti,mbox-num-users = <4>;
383 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]384 mbox_wkupm3: wkup_m3 {
385 ti,mbox-tx = <0 0 0>;
386 ti,mbox-rx = <0 0 3>;
387 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]388 };
389
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]390 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]391 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]392 reg = <0x44e31000 0x400>;
393 interrupts = <67>;
394 ti,hwmods = "timer1";
395 ti,timer-alwon;
396 };
397
398 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]399 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]400 reg = <0x48040000 0x400>;
401 interrupts = <68>;
402 ti,hwmods = "timer2";
403 };
404
405 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]406 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]407 reg = <0x48042000 0x400>;
408 interrupts = <69>;
409 ti,hwmods = "timer3";
410 };
411
412 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]413 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]414 reg = <0x48044000 0x400>;
415 interrupts = <92>;
416 ti,hwmods = "timer4";
417 ti,timer-pwm;
418 };
419
420 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]421 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]422 reg = <0x48046000 0x400>;
423 interrupts = <93>;
424 ti,hwmods = "timer5";
425 ti,timer-pwm;
426 };
427
428 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]429 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]430 reg = <0x48048000 0x400>;
431 interrupts = <94>;
432 ti,hwmods = "timer6";
433 ti,timer-pwm;
434 };
435
436 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]437 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]438 reg = <0x4804a000 0x400>;
439 interrupts = <95>;
440 ti,hwmods = "timer7";
441 ti,timer-pwm;
442 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]443
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]444 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]445 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]446 reg = <0x44e3e000 0x1000>;
447 interrupts = <75
448 76>;
449 ti,hwmods = "rtc";
450 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]451
452 spi0: spi@48030000 {
453 compatible = "ti,omap4-mcspi";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]457 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]458 ti,spi-num-cs = <2>;
459 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]460 dmas = <&edma 16
461 &edma 17
462 &edma 18
463 &edma 19>;
464 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]465 status = "disabled";
466 };
467
468 spi1: spi@481a0000 {
469 compatible = "ti,omap4-mcspi";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]473 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]474 ti,spi-num-cs = <2>;
475 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]476 dmas = <&edma 42
477 &edma 43
478 &edma 44
479 &edma 45>;
480 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]481 status = "disabled";
482 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]483
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]484 usb: usb@47400000 {
485 compatible = "ti,am33xx-usb";
486 reg = <0x47400000 0x1000>;
487 ranges;
488 #address-cells = <1>;
489 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]490 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]491 status = "disabled";
492
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]493 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]494 compatible = "ti,am335x-usb-ctrl-module";
495 reg = <0x44e10620 0x10
496 0x44e10648 0x4>;
497 reg-names = "phy_ctrl", "wakeup";
498 status = "disabled";
499 };
500
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]501 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]502 compatible = "ti,am335x-usb-phy";
503 reg = <0x47401300 0x100>;
504 reg-names = "phy";
505 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]506 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]507 };
508
509 usb0: usb@47401000 {
510 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]511 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]512 reg = <0x47401400 0x400
513 0x47401000 0x200>;
514 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]515
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]516 interrupts = <18>;
517 interrupt-names = "mc";
518 dr_mode = "otg";
519 mentor,multipoint = <1>;
520 mentor,num-eps = <16>;
521 mentor,ram-bits = <12>;
522 mentor,power = <500>;
523 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]524
525 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
526 &cppi41dma 2 0 &cppi41dma 3 0
527 &cppi41dma 4 0 &cppi41dma 5 0
528 &cppi41dma 6 0 &cppi41dma 7 0
529 &cppi41dma 8 0 &cppi41dma 9 0
530 &cppi41dma 10 0 &cppi41dma 11 0
531 &cppi41dma 12 0 &cppi41dma 13 0
532 &cppi41dma 14 0 &cppi41dma 0 1
533 &cppi41dma 1 1 &cppi41dma 2 1
534 &cppi41dma 3 1 &cppi41dma 4 1
535 &cppi41dma 5 1 &cppi41dma 6 1
536 &cppi41dma 7 1 &cppi41dma 8 1
537 &cppi41dma 9 1 &cppi41dma 10 1
538 &cppi41dma 11 1 &cppi41dma 12 1
539 &cppi41dma 13 1 &cppi41dma 14 1>;
540 dma-names =
541 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
542 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
543 "rx14", "rx15",
544 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
545 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
546 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]547 };
548
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]549 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]550 compatible = "ti,am335x-usb-phy";
551 reg = <0x47401b00 0x100>;
552 reg-names = "phy";
553 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]554 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]555 };
556
557 usb1: usb@47401800 {
558 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]559 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]560 reg = <0x47401c00 0x400
561 0x47401800 0x200>;
562 reg-names = "mc", "control";
563 interrupts = <19>;
564 interrupt-names = "mc";
565 dr_mode = "otg";
566 mentor,multipoint = <1>;
567 mentor,num-eps = <16>;
568 mentor,ram-bits = <12>;
569 mentor,power = <500>;
570 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]571
572 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
573 &cppi41dma 17 0 &cppi41dma 18 0
574 &cppi41dma 19 0 &cppi41dma 20 0
575 &cppi41dma 21 0 &cppi41dma 22 0
576 &cppi41dma 23 0 &cppi41dma 24 0
577 &cppi41dma 25 0 &cppi41dma 26 0
578 &cppi41dma 27 0 &cppi41dma 28 0
579 &cppi41dma 29 0 &cppi41dma 15 1
580 &cppi41dma 16 1 &cppi41dma 17 1
581 &cppi41dma 18 1 &cppi41dma 19 1
582 &cppi41dma 20 1 &cppi41dma 21 1
583 &cppi41dma 22 1 &cppi41dma 23 1
584 &cppi41dma 24 1 &cppi41dma 25 1
585 &cppi41dma 26 1 &cppi41dma 27 1
586 &cppi41dma 28 1 &cppi41dma 29 1>;
587 dma-names =
588 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
589 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
590 "rx14", "rx15",
591 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
592 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
593 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]594 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]595
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]596 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]597 compatible = "ti,am3359-cppi41";
598 reg = <0x47400000 0x1000
599 0x47402000 0x1000
600 0x47403000 0x1000
601 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]602 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]603 interrupts = <17>;
604 interrupt-names = "glue";
605 #dma-cells = <2>;
606 #dma-channels = <30>;
607 #dma-requests = <256>;
608 status = "disabled";
609 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]610 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]611
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]612 epwmss0: epwmss@48300000 {
613 compatible = "ti,am33xx-pwmss";
614 reg = <0x48300000 0x10>;
615 ti,hwmods = "epwmss0";
616 #address-cells = <1>;
617 #size-cells = <1>;
618 status = "disabled";
619 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
620 0x48300180 0x48300180 0x80 /* EQEP */
621 0x48300200 0x48300200 0x80>; /* EHRPWM */
622
623 ecap0: ecap@48300100 {
624 compatible = "ti,am33xx-ecap";
625 #pwm-cells = <3>;
626 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]627 interrupts = <31>;
628 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]629 ti,hwmods = "ecap0";
630 status = "disabled";
631 };
632
633 ehrpwm0: ehrpwm@48300200 {
634 compatible = "ti,am33xx-ehrpwm";
635 #pwm-cells = <3>;
636 reg = <0x48300200 0x80>;
637 ti,hwmods = "ehrpwm0";
638 status = "disabled";
639 };
640 };
641
642 epwmss1: epwmss@48302000 {
643 compatible = "ti,am33xx-pwmss";
644 reg = <0x48302000 0x10>;
645 ti,hwmods = "epwmss1";
646 #address-cells = <1>;
647 #size-cells = <1>;
648 status = "disabled";
649 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
650 0x48302180 0x48302180 0x80 /* EQEP */
651 0x48302200 0x48302200 0x80>; /* EHRPWM */
652
653 ecap1: ecap@48302100 {
654 compatible = "ti,am33xx-ecap";
655 #pwm-cells = <3>;
656 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]657 interrupts = <47>;
658 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]659 ti,hwmods = "ecap1";
660 status = "disabled";
661 };
662
663 ehrpwm1: ehrpwm@48302200 {
664 compatible = "ti,am33xx-ehrpwm";
665 #pwm-cells = <3>;
666 reg = <0x48302200 0x80>;
667 ti,hwmods = "ehrpwm1";
668 status = "disabled";
669 };
670 };
671
672 epwmss2: epwmss@48304000 {
673 compatible = "ti,am33xx-pwmss";
674 reg = <0x48304000 0x10>;
675 ti,hwmods = "epwmss2";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 status = "disabled";
679 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
680 0x48304180 0x48304180 0x80 /* EQEP */
681 0x48304200 0x48304200 0x80>; /* EHRPWM */
682
683 ecap2: ecap@48304100 {
684 compatible = "ti,am33xx-ecap";
685 #pwm-cells = <3>;
686 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]687 interrupts = <61>;
688 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]689 ti,hwmods = "ecap2";
690 status = "disabled";
691 };
692
693 ehrpwm2: ehrpwm@48304200 {
694 compatible = "ti,am33xx-ehrpwm";
695 #pwm-cells = <3>;
696 reg = <0x48304200 0x80>;
697 ti,hwmods = "ehrpwm2";
698 status = "disabled";
699 };
700 };
701
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]702 mac: ethernet@4a100000 {
703 compatible = "ti,cpsw";
704 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]705 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
706 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]707 cpdma_channels = <8>;
708 ale_entries = <1024>;
709 bd_ram_size = <0x2000>;
710 no_bd_ram = <0>;
711 rx_descs = <64>;
712 mac_control = <0x20>;
713 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]714 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]715 cpts_clock_mult = <0x80000000>;
716 cpts_clock_shift = <29>;
717 reg = <0x4a100000 0x800
718 0x4a101200 0x100>;
719 #address-cells = <1>;
720 #size-cells = <1>;
721 interrupt-parent = <&intc>;
722 /*
723 * c0_rx_thresh_pend
724 * c0_rx_pend
725 * c0_tx_pend
726 * c0_misc_pend
727 */
728 interrupts = <40 41 42 43>;
729 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame^]730 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]731 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]732
733 davinci_mdio: mdio@4a101000 {
734 compatible = "ti,davinci_mdio";
735 #address-cells = <1>;
736 #size-cells = <0>;
737 ti,hwmods = "davinci_mdio";
738 bus_freq = <1000000>;
739 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]740 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]741 };
742
743 cpsw_emac0: slave@4a100200 {
744 /* Filled in by U-Boot */
745 mac-address = [ 00 00 00 00 00 00 ];
746 };
747
748 cpsw_emac1: slave@4a100300 {
749 /* Filled in by U-Boot */
750 mac-address = [ 00 00 00 00 00 00 ];
751 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]752
753 phy_sel: cpsw-phy-sel@44e10650 {
754 compatible = "ti,am3352-cpsw-phy-sel";
755 reg= <0x44e10650 0x4>;
756 reg-names = "gmii-sel";
757 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]758 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]759
760 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]761 compatible = "mmio-sram";
762 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]763 };
764
765 wkup_m3: wkup_m3@44d00000 {
766 compatible = "ti,am3353-wkup-m3";
767 reg = <0x44d00000 0x4000 /* M3 UMEM */
768 0x44d80000 0x2000>; /* M3 DMEM */
769 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]770 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]771 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]772
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]773 elm: elm@48080000 {
774 compatible = "ti,am3352-elm";
775 reg = <0x48080000 0x2000>;
776 interrupts = <4>;
777 ti,hwmods = "elm";
778 status = "disabled";
779 };
780
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]781 lcdc: lcdc@4830e000 {
782 compatible = "ti,am33xx-tilcdc";
783 reg = <0x4830e000 0x1000>;
784 interrupt-parent = <&intc>;
785 interrupts = <36>;
786 ti,hwmods = "lcdc";
787 status = "disabled";
788 };
789
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]790 tscadc: tscadc@44e0d000 {
791 compatible = "ti,am3359-tscadc";
792 reg = <0x44e0d000 0x1000>;
793 interrupt-parent = <&intc>;
794 interrupts = <16>;
795 ti,hwmods = "adc_tsc";
796 status = "disabled";
797
798 tsc {
799 compatible = "ti,am3359-tsc";
800 };
801 am335x_adc: adc {
802 #io-channel-cells = <1>;
803 compatible = "ti,am3359-adc";
804 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]805 };
806
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]807 gpmc: gpmc@50000000 {
808 compatible = "ti,am3352-gpmc";
809 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]810 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]811 reg = <0x50000000 0x2000>;
812 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]813 gpmc,num-cs = <7>;
814 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]815 #address-cells = <2>;
816 #size-cells = <1>;
817 status = "disabled";
818 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]819
820 sham: sham@53100000 {
821 compatible = "ti,omap4-sham";
822 ti,hwmods = "sham";
823 reg = <0x53100000 0x200>;
824 interrupts = <109>;
825 dmas = <&edma 36>;
826 dma-names = "rx";
827 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]828
829 aes: aes@53500000 {
830 compatible = "ti,omap4-aes";
831 ti,hwmods = "aes";
832 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]833 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]834 dmas = <&edma 6>,
835 <&edma 5>;
836 dma-names = "tx", "rx";
837 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]838
839 mcasp0: mcasp@48038000 {
840 compatible = "ti,am33xx-mcasp-audio";
841 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]842 reg = <0x48038000 0x2000>,
843 <0x46000000 0x400000>;
844 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]845 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]846 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]847 status = "disabled";
848 dmas = <&edma 8>,
849 <&edma 9>;
850 dma-names = "tx", "rx";
851 };
852
853 mcasp1: mcasp@4803C000 {
854 compatible = "ti,am33xx-mcasp-audio";
855 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]856 reg = <0x4803C000 0x2000>,
857 <0x46400000 0x400000>;
858 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]859 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]860 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]861 status = "disabled";
862 dmas = <&edma 10>,
863 <&edma 11>;
864 dma-names = "tx", "rx";
865 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]866
867 rng: rng@48310000 {
868 compatible = "ti,omap4-rng";
869 ti,hwmods = "rng";
870 reg = <0x48310000 0x2000>;
871 interrupts = <111>;
872 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]873 };
874};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]875
876/include/ "am33xx-clocks.dtsi"