blob: 8c3f0802686dbbbba9bc38692681368095db662a [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Jesse Barnes63eeaf32009-06-18 16:56:52 -070029#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010035#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define MAX_NOPID ((u32)~0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Keith Packard7c463582008-11-04 02:03:27 -080040/**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050047#define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Keith Packard7c463582008-11-04 02:03:27 -080054
55/** Interrupts that we mask and unmask at runtime. */
56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
57
Jesse Barnes79e53942008-11-07 14:24:08 -080058#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +010067void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050068ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080069{
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75}
76
77static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050078ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080079{
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85}
86
87/* For display hotplug interrupt */
88void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050089ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080090{
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96}
97
98static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050099ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800100{
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106}
107
108void
Eric Anholted4cb412008-07-29 12:10:39 -0700109i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110{
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116}
117
118static inline void
119i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120{
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126}
127
Keith Packard7c463582008-11-04 02:03:27 -0800128static inline u32
129i915_pipestat(int pipe)
130{
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
Andrew Morton9c84ba42008-12-01 13:14:08 -0800135 BUG();
Keith Packard7c463582008-11-04 02:03:27 -0800136}
137
138void
139i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140{
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149}
150
151void
152i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153{
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161}
162
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000163/**
Zhao Yakui01c66882009-10-28 05:10:00 +0000164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166void intel_enable_asle (struct drm_device *dev)
167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
Eric Anholtc619eed2010-01-28 16:45:52 -0800170 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500171 ironlake_enable_display_irq(dev_priv, DE_GSE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800172 else {
Zhao Yakui01c66882009-10-28 05:10:00 +0000173 i915_enable_pipestat(dev_priv, 1,
174 I915_LEGACY_BLC_EVENT_ENABLE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800175 if (IS_I965G(dev))
176 i915_enable_pipestat(dev_priv, 0,
177 I915_LEGACY_BLC_EVENT_ENABLE);
178 }
Zhao Yakui01c66882009-10-28 05:10:00 +0000179}
180
181/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190static int
191i915_pipe_enabled(struct drm_device *dev, int pipe)
192{
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
195
196 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
197 return 1;
198
199 return 0;
200}
201
Keith Packard42f52ef2008-10-18 19:39:29 -0700202/* Called from drm generic code, passed a 'crtc', which
203 * we use as a pipe index
204 */
205u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700206{
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208 unsigned long high_frame;
209 unsigned long low_frame;
210 u32 high1, high2, low, count;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700211
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700212 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
213 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
214
215 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800216 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
217 "pipe %d\n", pipe);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700218 return 0;
219 }
220
221 /*
222 * High & low register fields aren't synchronized, so make sure
223 * we get a low value that's stable across two reads of the high
224 * register.
225 */
226 do {
227 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228 PIPE_FRAME_HIGH_SHIFT);
229 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
230 PIPE_FRAME_LOW_SHIFT);
231 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
232 PIPE_FRAME_HIGH_SHIFT);
233 } while (high1 != high2);
234
235 count = (high1 << 8) | low;
236
237 return count;
238}
239
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800240u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
241{
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
244
245 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800246 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
247 "pipe %d\n", pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800248 return 0;
249 }
250
251 return I915_READ(reg);
252}
253
Jesse Barnes5ca58282009-03-31 14:11:15 -0700254/*
255 * Handle hotplug events outside the interrupt handler proper.
256 */
257static void i915_hotplug_work_func(struct work_struct *work)
258{
259 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
260 hotplug_work);
261 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700262 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wang5bf4c9c2010-03-30 14:39:26 +0800263 struct drm_encoder *encoder;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700264
Zhenyu Wang5bf4c9c2010-03-30 14:39:26 +0800265 if (mode_config->num_encoder) {
266 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
267 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700268
Eric Anholt21d40d32010-03-25 11:11:14 -0700269 if (intel_encoder->hot_plug)
270 (*intel_encoder->hot_plug) (intel_encoder);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700271 }
272 }
Jesse Barnes5ca58282009-03-31 14:11:15 -0700273 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000274 drm_helper_hpd_irq_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700275}
276
Jesse Barnesf97108d2010-01-29 11:27:07 -0800277static void i915_handle_rps_change(struct drm_device *dev)
278{
279 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000280 u32 busy_up, busy_down, max_avg, min_avg;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800281 u16 rgvswctl;
282 u8 new_delay = dev_priv->cur_delay;
283
284 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000285 busy_up = I915_READ(RCPREVBSYTUPAVG);
286 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800287 max_avg = I915_READ(RCBMAXAVG);
288 min_avg = I915_READ(RCBMINAVG);
289
290 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000291 if (busy_up > max_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800292 if (dev_priv->cur_delay != dev_priv->max_delay)
293 new_delay = dev_priv->cur_delay - 1;
294 if (new_delay < dev_priv->max_delay)
295 new_delay = dev_priv->max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000296 } else if (busy_down < min_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800297 if (dev_priv->cur_delay != dev_priv->min_delay)
298 new_delay = dev_priv->cur_delay + 1;
299 if (new_delay > dev_priv->min_delay)
300 new_delay = dev_priv->min_delay;
301 }
302
303 DRM_DEBUG("rps change requested: %d -> %d\n",
304 dev_priv->cur_delay, new_delay);
305
306 rgvswctl = I915_READ(MEMSWCTL);
307 if (rgvswctl & MEMCTL_CMD_STS) {
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000308 DRM_ERROR("gpu busy, RCS change rejected\n");
309 return; /* still busy with another command */
Jesse Barnesf97108d2010-01-29 11:27:07 -0800310 }
311
312 /* Program the new state */
313 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
314 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
315 I915_WRITE(MEMSWCTL, rgvswctl);
316 POSTING_READ(MEMSWCTL);
317
318 rgvswctl |= MEMCTL_CMD_STS;
319 I915_WRITE(MEMSWCTL, rgvswctl);
320
321 dev_priv->cur_delay = new_delay;
322
323 DRM_DEBUG("rps changed\n");
324
325 return;
326}
327
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500328irqreturn_t ironlake_irq_handler(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800329{
330 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
331 int ret = IRQ_NONE;
Dave Airlie3ff99162009-12-08 14:03:47 +1000332 u32 de_iir, gt_iir, de_ier, pch_iir;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800333 struct drm_i915_master_private *master_priv;
334
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000335 /* disable master interrupt before clearing iir */
336 de_ier = I915_READ(DEIER);
337 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
338 (void)I915_READ(DEIER);
339
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800340 de_iir = I915_READ(DEIIR);
341 gt_iir = I915_READ(GTIIR);
Zhenyu Wangc6501562009-11-03 18:57:21 +0000342 pch_iir = I915_READ(SDEIIR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800343
Zou Nan haic7c85102010-01-15 10:29:06 +0800344 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
345 goto done;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800346
Zou Nan haic7c85102010-01-15 10:29:06 +0800347 ret = IRQ_HANDLED;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800348
Zou Nan haic7c85102010-01-15 10:29:06 +0800349 if (dev->primary->master) {
350 master_priv = dev->primary->master->driver_priv;
351 if (master_priv->sarea_priv)
352 master_priv->sarea_priv->last_dispatch =
353 READ_BREADCRUMB(dev_priv);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800354 }
355
Jesse Barnese552eb72010-04-21 11:39:23 -0700356 if (gt_iir & GT_PIPE_NOTIFY) {
Zou Nan haic7c85102010-01-15 10:29:06 +0800357 u32 seqno = i915_get_gem_seqno(dev);
358 dev_priv->mm.irq_gem_seqno = seqno;
359 trace_i915_gem_request_complete(dev, seqno);
360 DRM_WAKEUP(&dev_priv->irq_queue);
361 dev_priv->hangcheck_count = 0;
362 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
363 }
364
365 if (de_iir & DE_GSE)
366 ironlake_opregion_gse_intr(dev);
367
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800368 if (de_iir & DE_PLANEA_FLIP_DONE) {
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800369 intel_prepare_page_flip(dev, 0);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800370 intel_finish_page_flip(dev, 0);
371 }
372
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800373 if (de_iir & DE_PLANEB_FLIP_DONE) {
374 intel_prepare_page_flip(dev, 1);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800375 intel_finish_page_flip(dev, 1);
376 }
Li Pengc062df62010-01-23 00:12:58 +0800377
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800378 if (de_iir & DE_PIPEA_VBLANK)
379 drm_handle_vblank(dev, 0);
380
381 if (de_iir & DE_PIPEB_VBLANK)
382 drm_handle_vblank(dev, 1);
383
Zou Nan haic7c85102010-01-15 10:29:06 +0800384 /* check event from PCH */
385 if ((de_iir & DE_PCH_EVENT) &&
386 (pch_iir & SDE_HOTPLUG_MASK)) {
387 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
388 }
389
Jesse Barnesf97108d2010-01-29 11:27:07 -0800390 if (de_iir & DE_PCU_EVENT) {
391 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
392 i915_handle_rps_change(dev);
393 }
394
Zou Nan haic7c85102010-01-15 10:29:06 +0800395 /* should clear PCH hotplug event before clear CPU irq */
396 I915_WRITE(SDEIIR, pch_iir);
397 I915_WRITE(GTIIR, gt_iir);
398 I915_WRITE(DEIIR, de_iir);
399
400done:
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000401 I915_WRITE(DEIER, de_ier);
402 (void)I915_READ(DEIER);
403
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800404 return ret;
405}
406
Jesse Barnes8a905232009-07-11 16:48:03 -0400407/**
408 * i915_error_work_func - do process context error handling work
409 * @work: work struct
410 *
411 * Fire an error uevent so userspace can see that a hang or error
412 * was detected.
413 */
414static void i915_error_work_func(struct work_struct *work)
415{
416 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
417 error_work);
418 struct drm_device *dev = dev_priv->dev;
Ben Gamarif316a422009-09-14 17:48:46 -0400419 char *error_event[] = { "ERROR=1", NULL };
420 char *reset_event[] = { "RESET=1", NULL };
421 char *reset_done_event[] = { "ERROR=0", NULL };
Jesse Barnes8a905232009-07-11 16:48:03 -0400422
Zhao Yakui44d98a62009-10-09 11:39:40 +0800423 DRM_DEBUG_DRIVER("generating error event\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400424 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -0400425
Ben Gamariba1234d2009-09-14 17:48:47 -0400426 if (atomic_read(&dev_priv->mm.wedged)) {
Ben Gamarif316a422009-09-14 17:48:46 -0400427 if (IS_I965G(dev)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800428 DRM_DEBUG_DRIVER("resetting chip\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400429 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
430 if (!i965_reset(dev, GDRST_RENDER)) {
Ben Gamariba1234d2009-09-14 17:48:47 -0400431 atomic_set(&dev_priv->mm.wedged, 0);
Ben Gamarif316a422009-09-14 17:48:46 -0400432 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
433 }
434 } else {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800435 DRM_DEBUG_DRIVER("reboot required\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400436 }
437 }
Jesse Barnes8a905232009-07-11 16:48:03 -0400438}
439
Chris Wilson9df30792010-02-18 10:24:56 +0000440static struct drm_i915_error_object *
441i915_error_object_create(struct drm_device *dev,
442 struct drm_gem_object *src)
443{
444 struct drm_i915_error_object *dst;
445 struct drm_i915_gem_object *src_priv;
446 int page, page_count;
447
448 if (src == NULL)
449 return NULL;
450
Daniel Vetter23010e42010-03-08 13:35:02 +0100451 src_priv = to_intel_bo(src);
Chris Wilson9df30792010-02-18 10:24:56 +0000452 if (src_priv->pages == NULL)
453 return NULL;
454
455 page_count = src->size / PAGE_SIZE;
456
457 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
458 if (dst == NULL)
459 return NULL;
460
461 for (page = 0; page < page_count; page++) {
462 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
Andrew Morton788885a2010-05-11 14:07:05 -0700463 unsigned long flags;
464
Chris Wilson9df30792010-02-18 10:24:56 +0000465 if (d == NULL)
466 goto unwind;
Andrew Morton788885a2010-05-11 14:07:05 -0700467 local_irq_save(flags);
468 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
Chris Wilson9df30792010-02-18 10:24:56 +0000469 memcpy(d, s, PAGE_SIZE);
Andrew Morton788885a2010-05-11 14:07:05 -0700470 kunmap_atomic(s, KM_IRQ0);
471 local_irq_restore(flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000472 dst->pages[page] = d;
473 }
474 dst->page_count = page_count;
475 dst->gtt_offset = src_priv->gtt_offset;
476
477 return dst;
478
479unwind:
480 while (page--)
481 kfree(dst->pages[page]);
482 kfree(dst);
483 return NULL;
484}
485
486static void
487i915_error_object_free(struct drm_i915_error_object *obj)
488{
489 int page;
490
491 if (obj == NULL)
492 return;
493
494 for (page = 0; page < obj->page_count; page++)
495 kfree(obj->pages[page]);
496
497 kfree(obj);
498}
499
500static void
501i915_error_state_free(struct drm_device *dev,
502 struct drm_i915_error_state *error)
503{
504 i915_error_object_free(error->batchbuffer[0]);
505 i915_error_object_free(error->batchbuffer[1]);
506 i915_error_object_free(error->ringbuffer);
507 kfree(error->active_bo);
508 kfree(error);
509}
510
511static u32
512i915_get_bbaddr(struct drm_device *dev, u32 *ring)
513{
514 u32 cmd;
515
516 if (IS_I830(dev) || IS_845G(dev))
517 cmd = MI_BATCH_BUFFER;
518 else if (IS_I965G(dev))
519 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
520 MI_BATCH_NON_SECURE_I965);
521 else
522 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
523
524 return ring[0] == cmd ? ring[1] : 0;
525}
526
527static u32
528i915_ringbuffer_last_batch(struct drm_device *dev)
529{
530 struct drm_i915_private *dev_priv = dev->dev_private;
531 u32 head, bbaddr;
532 u32 *ring;
533
534 /* Locate the current position in the ringbuffer and walk back
535 * to find the most recently dispatched batch buffer.
536 */
537 bbaddr = 0;
538 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
539 ring = (u32 *)(dev_priv->ring.virtual_start + head);
540
541 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
542 bbaddr = i915_get_bbaddr(dev, ring);
543 if (bbaddr)
544 break;
545 }
546
547 if (bbaddr == 0) {
548 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
549 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
550 bbaddr = i915_get_bbaddr(dev, ring);
551 if (bbaddr)
552 break;
553 }
554 }
555
556 return bbaddr;
557}
558
Jesse Barnes8a905232009-07-11 16:48:03 -0400559/**
560 * i915_capture_error_state - capture an error record for later analysis
561 * @dev: drm device
562 *
563 * Should be called when an error is detected (either a hang or an error
564 * interrupt) to capture error state from the time of the error. Fills
565 * out a structure which becomes available in debugfs for user level tools
566 * to pick up.
567 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700568static void i915_capture_error_state(struct drm_device *dev)
569{
570 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9df30792010-02-18 10:24:56 +0000571 struct drm_i915_gem_object *obj_priv;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700572 struct drm_i915_error_state *error;
Chris Wilson9df30792010-02-18 10:24:56 +0000573 struct drm_gem_object *batchbuffer[2];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700574 unsigned long flags;
Chris Wilson9df30792010-02-18 10:24:56 +0000575 u32 bbaddr;
576 int count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700577
578 spin_lock_irqsave(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000579 error = dev_priv->first_error;
580 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
581 if (error)
582 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700583
584 error = kmalloc(sizeof(*error), GFP_ATOMIC);
585 if (!error) {
Chris Wilson9df30792010-02-18 10:24:56 +0000586 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
587 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700588 }
589
Chris Wilson9df30792010-02-18 10:24:56 +0000590 error->seqno = i915_get_gem_seqno(dev);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700591 error->eir = I915_READ(EIR);
592 error->pgtbl_er = I915_READ(PGTBL_ER);
593 error->pipeastat = I915_READ(PIPEASTAT);
594 error->pipebstat = I915_READ(PIPEBSTAT);
595 error->instpm = I915_READ(INSTPM);
596 if (!IS_I965G(dev)) {
597 error->ipeir = I915_READ(IPEIR);
598 error->ipehr = I915_READ(IPEHR);
599 error->instdone = I915_READ(INSTDONE);
600 error->acthd = I915_READ(ACTHD);
Chris Wilson9df30792010-02-18 10:24:56 +0000601 error->bbaddr = 0;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700602 } else {
603 error->ipeir = I915_READ(IPEIR_I965);
604 error->ipehr = I915_READ(IPEHR_I965);
605 error->instdone = I915_READ(INSTDONE_I965);
606 error->instps = I915_READ(INSTPS);
607 error->instdone1 = I915_READ(INSTDONE1);
608 error->acthd = I915_READ(ACTHD_I965);
Chris Wilson9df30792010-02-18 10:24:56 +0000609 error->bbaddr = I915_READ64(BB_ADDR);
610 }
611
612 bbaddr = i915_ringbuffer_last_batch(dev);
613
614 /* Grab the current batchbuffer, most likely to have crashed. */
615 batchbuffer[0] = NULL;
616 batchbuffer[1] = NULL;
617 count = 0;
618 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
Daniel Vettera8089e82010-04-09 19:05:09 +0000619 struct drm_gem_object *obj = &obj_priv->base;
Chris Wilson9df30792010-02-18 10:24:56 +0000620
621 if (batchbuffer[0] == NULL &&
622 bbaddr >= obj_priv->gtt_offset &&
623 bbaddr < obj_priv->gtt_offset + obj->size)
624 batchbuffer[0] = obj;
625
626 if (batchbuffer[1] == NULL &&
627 error->acthd >= obj_priv->gtt_offset &&
628 error->acthd < obj_priv->gtt_offset + obj->size &&
629 batchbuffer[0] != obj)
630 batchbuffer[1] = obj;
631
632 count++;
633 }
634
635 /* We need to copy these to an anonymous buffer as the simplest
636 * method to avoid being overwritten by userpace.
637 */
638 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
639 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
640
641 /* Record the ringbuffer */
642 error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
643
644 /* Record buffers on the active list. */
645 error->active_bo = NULL;
646 error->active_bo_count = 0;
647
648 if (count)
649 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
650 GFP_ATOMIC);
651
652 if (error->active_bo) {
653 int i = 0;
654 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
Daniel Vettera8089e82010-04-09 19:05:09 +0000655 struct drm_gem_object *obj = &obj_priv->base;
Chris Wilson9df30792010-02-18 10:24:56 +0000656
657 error->active_bo[i].size = obj->size;
658 error->active_bo[i].name = obj->name;
659 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
660 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
661 error->active_bo[i].read_domains = obj->read_domains;
662 error->active_bo[i].write_domain = obj->write_domain;
663 error->active_bo[i].fence_reg = obj_priv->fence_reg;
664 error->active_bo[i].pinned = 0;
665 if (obj_priv->pin_count > 0)
666 error->active_bo[i].pinned = 1;
667 if (obj_priv->user_pin_count > 0)
668 error->active_bo[i].pinned = -1;
669 error->active_bo[i].tiling = obj_priv->tiling_mode;
670 error->active_bo[i].dirty = obj_priv->dirty;
671 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
672
673 if (++i == count)
674 break;
675 }
676 error->active_bo_count = i;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700677 }
678
Jesse Barnes8a905232009-07-11 16:48:03 -0400679 do_gettimeofday(&error->time);
680
Chris Wilson9df30792010-02-18 10:24:56 +0000681 spin_lock_irqsave(&dev_priv->error_lock, flags);
682 if (dev_priv->first_error == NULL) {
683 dev_priv->first_error = error;
684 error = NULL;
685 }
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700686 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000687
688 if (error)
689 i915_error_state_free(dev, error);
690}
691
692void i915_destroy_error_state(struct drm_device *dev)
693{
694 struct drm_i915_private *dev_priv = dev->dev_private;
695 struct drm_i915_error_state *error;
696
697 spin_lock(&dev_priv->error_lock);
698 error = dev_priv->first_error;
699 dev_priv->first_error = NULL;
700 spin_unlock(&dev_priv->error_lock);
701
702 if (error)
703 i915_error_state_free(dev, error);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700704}
705
Jesse Barnes8a905232009-07-11 16:48:03 -0400706/**
707 * i915_handle_error - handle an error interrupt
708 * @dev: drm device
709 *
710 * Do some basic checking of regsiter state at error interrupt time and
711 * dump it to the syslog. Also call i915_capture_error_state() to make
712 * sure we get a record and make it available in debugfs. Fire a uevent
713 * so userspace knows something bad happened (should trigger collection
714 * of a ring dump etc.).
715 */
Ben Gamariba1234d2009-09-14 17:48:47 -0400716static void i915_handle_error(struct drm_device *dev, bool wedged)
Jesse Barnes8a905232009-07-11 16:48:03 -0400717{
718 struct drm_i915_private *dev_priv = dev->dev_private;
719 u32 eir = I915_READ(EIR);
720 u32 pipea_stats = I915_READ(PIPEASTAT);
721 u32 pipeb_stats = I915_READ(PIPEBSTAT);
722
723 i915_capture_error_state(dev);
724
725 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
726 eir);
727
728 if (IS_G4X(dev)) {
729 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
730 u32 ipeir = I915_READ(IPEIR_I965);
731
732 printk(KERN_ERR " IPEIR: 0x%08x\n",
733 I915_READ(IPEIR_I965));
734 printk(KERN_ERR " IPEHR: 0x%08x\n",
735 I915_READ(IPEHR_I965));
736 printk(KERN_ERR " INSTDONE: 0x%08x\n",
737 I915_READ(INSTDONE_I965));
738 printk(KERN_ERR " INSTPS: 0x%08x\n",
739 I915_READ(INSTPS));
740 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
741 I915_READ(INSTDONE1));
742 printk(KERN_ERR " ACTHD: 0x%08x\n",
743 I915_READ(ACTHD_I965));
744 I915_WRITE(IPEIR_I965, ipeir);
745 (void)I915_READ(IPEIR_I965);
746 }
747 if (eir & GM45_ERROR_PAGE_TABLE) {
748 u32 pgtbl_err = I915_READ(PGTBL_ER);
749 printk(KERN_ERR "page table error\n");
750 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
751 pgtbl_err);
752 I915_WRITE(PGTBL_ER, pgtbl_err);
753 (void)I915_READ(PGTBL_ER);
754 }
755 }
756
757 if (IS_I9XX(dev)) {
758 if (eir & I915_ERROR_PAGE_TABLE) {
759 u32 pgtbl_err = I915_READ(PGTBL_ER);
760 printk(KERN_ERR "page table error\n");
761 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
762 pgtbl_err);
763 I915_WRITE(PGTBL_ER, pgtbl_err);
764 (void)I915_READ(PGTBL_ER);
765 }
766 }
767
768 if (eir & I915_ERROR_MEMORY_REFRESH) {
769 printk(KERN_ERR "memory refresh error\n");
770 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
771 pipea_stats);
772 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
773 pipeb_stats);
774 /* pipestat has already been acked */
775 }
776 if (eir & I915_ERROR_INSTRUCTION) {
777 printk(KERN_ERR "instruction error\n");
778 printk(KERN_ERR " INSTPM: 0x%08x\n",
779 I915_READ(INSTPM));
780 if (!IS_I965G(dev)) {
781 u32 ipeir = I915_READ(IPEIR);
782
783 printk(KERN_ERR " IPEIR: 0x%08x\n",
784 I915_READ(IPEIR));
785 printk(KERN_ERR " IPEHR: 0x%08x\n",
786 I915_READ(IPEHR));
787 printk(KERN_ERR " INSTDONE: 0x%08x\n",
788 I915_READ(INSTDONE));
789 printk(KERN_ERR " ACTHD: 0x%08x\n",
790 I915_READ(ACTHD));
791 I915_WRITE(IPEIR, ipeir);
792 (void)I915_READ(IPEIR);
793 } else {
794 u32 ipeir = I915_READ(IPEIR_I965);
795
796 printk(KERN_ERR " IPEIR: 0x%08x\n",
797 I915_READ(IPEIR_I965));
798 printk(KERN_ERR " IPEHR: 0x%08x\n",
799 I915_READ(IPEHR_I965));
800 printk(KERN_ERR " INSTDONE: 0x%08x\n",
801 I915_READ(INSTDONE_I965));
802 printk(KERN_ERR " INSTPS: 0x%08x\n",
803 I915_READ(INSTPS));
804 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
805 I915_READ(INSTDONE1));
806 printk(KERN_ERR " ACTHD: 0x%08x\n",
807 I915_READ(ACTHD_I965));
808 I915_WRITE(IPEIR_I965, ipeir);
809 (void)I915_READ(IPEIR_I965);
810 }
811 }
812
813 I915_WRITE(EIR, eir);
814 (void)I915_READ(EIR);
815 eir = I915_READ(EIR);
816 if (eir) {
817 /*
818 * some errors might have become stuck,
819 * mask them.
820 */
821 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
822 I915_WRITE(EMR, I915_READ(EMR) | eir);
823 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
824 }
825
Ben Gamariba1234d2009-09-14 17:48:47 -0400826 if (wedged) {
827 atomic_set(&dev_priv->mm.wedged, 1);
828
Ben Gamari11ed50e2009-09-14 17:48:45 -0400829 /*
830 * Wakeup waiting processes so they don't hang
831 */
Ben Gamari11ed50e2009-09-14 17:48:45 -0400832 DRM_WAKEUP(&dev_priv->irq_queue);
833 }
834
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700835 queue_work(dev_priv->wq, &dev_priv->error_work);
Jesse Barnes8a905232009-07-11 16:48:03 -0400836}
837
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
839{
Dave Airlie84b1fd12007-07-11 15:53:27 +1000840 struct drm_device *dev = (struct drm_device *) arg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000842 struct drm_i915_master_private *master_priv;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800843 u32 iir, new_iir;
844 u32 pipea_stats, pipeb_stats;
Keith Packard05eff842008-11-19 14:03:05 -0800845 u32 vblank_status;
846 u32 vblank_enable;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700847 int vblank = 0;
Keith Packard7c463582008-11-04 02:03:27 -0800848 unsigned long irqflags;
Keith Packard05eff842008-11-19 14:03:05 -0800849 int irq_received;
850 int ret = IRQ_NONE;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000851
Eric Anholt630681d2008-10-06 15:14:12 -0700852 atomic_inc(&dev_priv->irq_received);
853
Eric Anholtbad720f2009-10-22 16:11:14 -0700854 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500855 return ironlake_irq_handler(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800856
Eric Anholted4cb412008-07-29 12:10:39 -0700857 iir = I915_READ(IIR);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000858
Keith Packard05eff842008-11-19 14:03:05 -0800859 if (IS_I965G(dev)) {
860 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
861 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
862 } else {
863 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
864 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
865 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866
Keith Packard05eff842008-11-19 14:03:05 -0800867 for (;;) {
868 irq_received = iir != 0;
869
870 /* Can't rely on pipestat interrupt bit in iir as it might
871 * have been cleared after the pipestat interrupt was received.
872 * It doesn't set the bit in iir again, but it still produces
873 * interrupts (for non-MSI).
874 */
875 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
876 pipea_stats = I915_READ(PIPEASTAT);
877 pipeb_stats = I915_READ(PIPEBSTAT);
Jesse Barnes79e53942008-11-07 14:24:08 -0800878
Jesse Barnes8a905232009-07-11 16:48:03 -0400879 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Ben Gamariba1234d2009-09-14 17:48:47 -0400880 i915_handle_error(dev, false);
Jesse Barnes8a905232009-07-11 16:48:03 -0400881
Eric Anholtcdfbc412008-11-04 15:50:30 -0800882 /*
883 * Clear the PIPE(A|B)STAT regs before the IIR
884 */
Keith Packard05eff842008-11-19 14:03:05 -0800885 if (pipea_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800886 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800887 DRM_DEBUG_DRIVER("pipe a underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800888 I915_WRITE(PIPEASTAT, pipea_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800889 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800890 }
Keith Packard7c463582008-11-04 02:03:27 -0800891
Keith Packard05eff842008-11-19 14:03:05 -0800892 if (pipeb_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800893 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800894 DRM_DEBUG_DRIVER("pipe b underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800895 I915_WRITE(PIPEBSTAT, pipeb_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800896 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800897 }
Keith Packard05eff842008-11-19 14:03:05 -0800898 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
899
900 if (!irq_received)
901 break;
902
903 ret = IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904
Jesse Barnes5ca58282009-03-31 14:11:15 -0700905 /* Consume port. Then clear IIR or we'll miss events */
906 if ((I915_HAS_HOTPLUG(dev)) &&
907 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
908 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
909
Zhao Yakui44d98a62009-10-09 11:39:40 +0800910 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
Jesse Barnes5ca58282009-03-31 14:11:15 -0700911 hotplug_status);
912 if (hotplug_status & dev_priv->hotplug_supported_mask)
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700913 queue_work(dev_priv->wq,
914 &dev_priv->hotplug_work);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700915
916 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
917 I915_READ(PORT_HOTPLUG_STAT);
918 }
919
Eric Anholtcdfbc412008-11-04 15:50:30 -0800920 I915_WRITE(IIR, iir);
921 new_iir = I915_READ(IIR); /* Flush posted writes */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100922
Dave Airlie7c1c2872008-11-28 14:22:24 +1000923 if (dev->primary->master) {
924 master_priv = dev->primary->master->driver_priv;
925 if (master_priv->sarea_priv)
926 master_priv->sarea_priv->last_dispatch =
927 READ_BREADCRUMB(dev_priv);
928 }
Keith Packard7c463582008-11-04 02:03:27 -0800929
Eric Anholtcdfbc412008-11-04 15:50:30 -0800930 if (iir & I915_USER_INTERRUPT) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +0100931 u32 seqno = i915_get_gem_seqno(dev);
932 dev_priv->mm.irq_gem_seqno = seqno;
933 trace_i915_gem_request_complete(dev, seqno);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800934 DRM_WAKEUP(&dev_priv->irq_queue);
Ben Gamarif65d9422009-09-14 17:48:44 -0400935 dev_priv->hangcheck_count = 0;
936 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800937 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700938
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500939 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
940 intel_prepare_page_flip(dev, 0);
941
942 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
943 intel_prepare_page_flip(dev, 1);
944
Keith Packard05eff842008-11-19 14:03:05 -0800945 if (pipea_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800946 vblank++;
947 drm_handle_vblank(dev, 0);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500948 intel_finish_page_flip(dev, 0);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800949 }
Eric Anholt673a3942008-07-30 12:06:12 -0700950
Keith Packard05eff842008-11-19 14:03:05 -0800951 if (pipeb_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800952 vblank++;
953 drm_handle_vblank(dev, 1);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500954 intel_finish_page_flip(dev, 1);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800955 }
Keith Packard7c463582008-11-04 02:03:27 -0800956
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800957 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
958 (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
Eric Anholtcdfbc412008-11-04 15:50:30 -0800959 (iir & I915_ASLE_INTERRUPT))
960 opregion_asle_intr(dev);
Keith Packard7c463582008-11-04 02:03:27 -0800961
Eric Anholtcdfbc412008-11-04 15:50:30 -0800962 /* With MSI, interrupts are only generated when iir
963 * transitions from zero to nonzero. If another bit got
964 * set while we were handling the existing iir bits, then
965 * we would never get another interrupt.
966 *
967 * This is fine on non-MSI as well, as if we hit this path
968 * we avoid exiting the interrupt handler only to generate
969 * another one.
970 *
971 * Note that for MSI this could cause a stray interrupt report
972 * if an interrupt landed in the time between writing IIR and
973 * the posting read. This should be rare enough to never
974 * trigger the 99% of 100,000 interrupts test for disabling
975 * stray interrupts.
976 */
977 iir = new_iir;
Keith Packard05eff842008-11-19 14:03:05 -0800978 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700979
Keith Packard05eff842008-11-19 14:03:05 -0800980 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981}
982
Dave Airlieaf6061a2008-05-07 12:15:39 +1000983static int i915_emit_irq(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984{
985 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000986 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 RING_LOCALS;
988
989 i915_kernel_lost_context(dev);
990
Zhao Yakui44d98a62009-10-09 11:39:40 +0800991 DRM_DEBUG_DRIVER("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400993 dev_priv->counter++;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000994 if (dev_priv->counter > 0x7FFFFFFFUL)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400995 dev_priv->counter = 1;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000996 if (master_priv->sarea_priv)
997 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000998
Keith Packard0baf8232008-11-08 11:44:14 +1000999 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -07001000 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +10001001 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Alan Hourihanec29b6692006-08-12 16:29:24 +10001002 OUT_RING(dev_priv->counter);
Jesse Barnes585fb112008-07-29 11:54:06 -07001003 OUT_RING(MI_USER_INTERRUPT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 ADVANCE_LP_RING();
Dave Airliebc5f4522007-11-05 12:50:58 +10001005
Alan Hourihanec29b6692006-08-12 16:29:24 +10001006 return dev_priv->counter;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007}
1008
Eric Anholt673a3942008-07-30 12:06:12 -07001009void i915_user_irq_get(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -07001010{
1011 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001012 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -07001013
Keith Packarde9d21d72008-10-16 11:31:38 -07001014 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001015 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001016 if (HAS_PCH_SPLIT(dev))
Jesse Barnese552eb72010-04-21 11:39:23 -07001017 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001018 else
1019 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1020 }
Keith Packarde9d21d72008-10-16 11:31:38 -07001021 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001022}
1023
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001024void i915_user_irq_put(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -07001025{
1026 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001027 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -07001028
Keith Packarde9d21d72008-10-16 11:31:38 -07001029 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001030 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001031 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001032 if (HAS_PCH_SPLIT(dev))
Jesse Barnese552eb72010-04-21 11:39:23 -07001033 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001034 else
1035 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1036 }
Keith Packarde9d21d72008-10-16 11:31:38 -07001037 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001038}
1039
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001040void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1041{
1042 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1043
1044 if (dev_priv->trace_irq_seqno == 0)
1045 i915_user_irq_get(dev);
1046
1047 dev_priv->trace_irq_seqno = seqno;
1048}
1049
Dave Airlie84b1fd12007-07-11 15:53:27 +10001050static int i915_wait_irq(struct drm_device * dev, int irq_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051{
1052 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001053 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 int ret = 0;
1055
Zhao Yakui44d98a62009-10-09 11:39:40 +08001056 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 READ_BREADCRUMB(dev_priv));
1058
Eric Anholted4cb412008-07-29 12:10:39 -07001059 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10001060 if (master_priv->sarea_priv)
1061 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062 return 0;
Eric Anholted4cb412008-07-29 12:10:39 -07001063 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064
Dave Airlie7c1c2872008-11-28 14:22:24 +10001065 if (master_priv->sarea_priv)
1066 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067
Eric Anholted4cb412008-07-29 12:10:39 -07001068 i915_user_irq_get(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1070 READ_BREADCRUMB(dev_priv) >= irq_nr);
Eric Anholted4cb412008-07-29 12:10:39 -07001071 i915_user_irq_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
Eric Anholt20caafa2007-08-25 19:22:43 +10001073 if (ret == -EBUSY) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001074 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1076 }
1077
Dave Airlieaf6061a2008-05-07 12:15:39 +10001078 return ret;
1079}
1080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081/* Needs the lock as it touches the ring.
1082 */
Eric Anholtc153f452007-09-03 12:06:45 +10001083int i915_irq_emit(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001087 drm_i915_irq_emit_t *emit = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 int result;
1089
Eric Anholt07f4f8b2009-04-16 13:46:12 -07001090 if (!dev_priv || !dev_priv->ring.virtual_start) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001091 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001092 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 }
Eric Anholt299eb932009-02-24 22:14:12 -08001094
1095 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1096
Eric Anholt546b0972008-09-01 16:45:29 -07001097 mutex_lock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098 result = i915_emit_irq(dev);
Eric Anholt546b0972008-09-01 16:45:29 -07001099 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100
Eric Anholtc153f452007-09-03 12:06:45 +10001101 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001103 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 }
1105
1106 return 0;
1107}
1108
1109/* Doesn't need the hardware lock.
1110 */
Eric Anholtc153f452007-09-03 12:06:45 +10001111int i915_irq_wait(struct drm_device *dev, void *data,
1112 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001115 drm_i915_irq_wait_t *irqwait = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116
1117 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001118 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001119 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 }
1121
Eric Anholtc153f452007-09-03 12:06:45 +10001122 return i915_wait_irq(dev, irqwait->irq_seq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123}
1124
Keith Packard42f52ef2008-10-18 19:39:29 -07001125/* Called from drm generic code, passed 'crtc' which
1126 * we use as a pipe index
1127 */
1128int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001129{
1130 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001131 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001132 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1133 u32 pipeconf;
1134
1135 pipeconf = I915_READ(pipeconf_reg);
1136 if (!(pipeconf & PIPEACONF_ENABLE))
1137 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001138
Keith Packarde9d21d72008-10-16 11:31:38 -07001139 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001140 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001141 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1142 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1143 else if (IS_I965G(dev))
Keith Packard7c463582008-11-04 02:03:27 -08001144 i915_enable_pipestat(dev_priv, pipe,
1145 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001146 else
Keith Packard7c463582008-11-04 02:03:27 -08001147 i915_enable_pipestat(dev_priv, pipe,
1148 PIPE_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001149 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001150 return 0;
1151}
1152
Keith Packard42f52ef2008-10-18 19:39:29 -07001153/* Called from drm generic code, passed 'crtc' which
1154 * we use as a pipe index
1155 */
1156void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001157{
1158 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001159 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001160
Keith Packarde9d21d72008-10-16 11:31:38 -07001161 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001162 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001163 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1164 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1165 else
1166 i915_disable_pipestat(dev_priv, pipe,
1167 PIPE_VBLANK_INTERRUPT_ENABLE |
1168 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001169 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001170}
1171
Jesse Barnes79e53942008-11-07 14:24:08 -08001172void i915_enable_interrupt (struct drm_device *dev)
1173{
1174 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wange170b032009-06-05 15:38:40 +08001175
Eric Anholtbad720f2009-10-22 16:11:14 -07001176 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wange170b032009-06-05 15:38:40 +08001177 opregion_enable_asle(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001178 dev_priv->irq_enabled = 1;
1179}
1180
1181
Dave Airlie702880f2006-06-24 17:07:34 +10001182/* Set the vblank monitor pipe
1183 */
Eric Anholtc153f452007-09-03 12:06:45 +10001184int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1185 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001186{
Dave Airlie702880f2006-06-24 17:07:34 +10001187 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie702880f2006-06-24 17:07:34 +10001188
1189 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001190 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001191 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001192 }
1193
=?utf-8?q?Michel_D=C3=A4nzer?=5b516942006-10-25 00:08:23 +10001194 return 0;
Dave Airlie702880f2006-06-24 17:07:34 +10001195}
1196
Eric Anholtc153f452007-09-03 12:06:45 +10001197int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1198 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001199{
Dave Airlie702880f2006-06-24 17:07:34 +10001200 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001201 drm_i915_vblank_pipe_t *pipe = data;
Dave Airlie702880f2006-06-24 17:07:34 +10001202
1203 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001204 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001205 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001206 }
1207
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001208 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Eric Anholtc153f452007-09-03 12:06:45 +10001209
Dave Airlie702880f2006-06-24 17:07:34 +10001210 return 0;
1211}
1212
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001213/**
1214 * Schedule buffer swap at given vertical blank.
1215 */
Eric Anholtc153f452007-09-03 12:06:45 +10001216int i915_vblank_swap(struct drm_device *dev, void *data,
1217 struct drm_file *file_priv)
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001218{
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001219 /* The delayed swap mechanism was fundamentally racy, and has been
1220 * removed. The model was that the client requested a delayed flip/swap
1221 * from the kernel, then waited for vblank before continuing to perform
1222 * rendering. The problem was that the kernel might wake the client
1223 * up before it dispatched the vblank swap (since the lock has to be
1224 * held while touching the ringbuffer), in which case the client would
1225 * clear and start the next frame before the swap occurred, and
1226 * flicker would occur in addition to likely missing the vblank.
1227 *
1228 * In the absence of this ioctl, userland falls back to a correct path
1229 * of waiting for a vblank, then dispatching the swap on its own.
1230 * Context switching to userland and back is plenty fast enough for
1231 * meeting the requirements of vblank swapping.
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001232 */
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001233 return -EINVAL;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001234}
1235
Ben Gamarif65d9422009-09-14 17:48:44 -04001236struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1237 drm_i915_private_t *dev_priv = dev->dev_private;
1238 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1239}
1240
1241/**
1242 * This is called when the chip hasn't reported back with completed
1243 * batchbuffers in a long time. The first time this is called we simply record
1244 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1245 * again, we assume the chip is wedged and try to fix it.
1246 */
1247void i915_hangcheck_elapsed(unsigned long data)
1248{
1249 struct drm_device *dev = (struct drm_device *)data;
1250 drm_i915_private_t *dev_priv = dev->dev_private;
1251 uint32_t acthd;
Eric Anholtb9201c12010-01-08 14:25:16 -08001252
1253 /* No reset support on this chip yet. */
1254 if (IS_GEN6(dev))
1255 return;
1256
Ben Gamarif65d9422009-09-14 17:48:44 -04001257 if (!IS_I965G(dev))
1258 acthd = I915_READ(ACTHD);
1259 else
1260 acthd = I915_READ(ACTHD_I965);
1261
1262 /* If all work is done then ACTHD clearly hasn't advanced. */
1263 if (list_empty(&dev_priv->mm.request_list) ||
1264 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1265 dev_priv->hangcheck_count = 0;
1266 return;
1267 }
1268
1269 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1270 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04001271 i915_handle_error(dev, true);
Ben Gamarif65d9422009-09-14 17:48:44 -04001272 return;
1273 }
1274
1275 /* Reset timer case chip hangs without another request being added */
1276 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1277
1278 if (acthd != dev_priv->last_acthd)
1279 dev_priv->hangcheck_count = 0;
1280 else
1281 dev_priv->hangcheck_count++;
1282
1283 dev_priv->last_acthd = acthd;
1284}
1285
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286/* drm_dma.h hooks
1287*/
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001288static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001289{
1290 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1291
1292 I915_WRITE(HWSTAM, 0xeffe);
1293
1294 /* XXX hotplug from PCH */
1295
1296 I915_WRITE(DEIMR, 0xffffffff);
1297 I915_WRITE(DEIER, 0x0);
1298 (void) I915_READ(DEIER);
1299
1300 /* and GT */
1301 I915_WRITE(GTIMR, 0xffffffff);
1302 I915_WRITE(GTIER, 0x0);
1303 (void) I915_READ(GTIER);
Zhenyu Wangc6501562009-11-03 18:57:21 +00001304
1305 /* south display irq */
1306 I915_WRITE(SDEIMR, 0xffffffff);
1307 I915_WRITE(SDEIER, 0x0);
1308 (void) I915_READ(SDEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001309}
1310
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001311static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001312{
1313 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1314 /* enable kind of interrupts always enabled */
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001315 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1316 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
Jesse Barnese552eb72010-04-21 11:39:23 -07001317 u32 render_mask = GT_PIPE_NOTIFY;
Zhenyu Wangc6501562009-11-03 18:57:21 +00001318 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1319 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001320
1321 dev_priv->irq_mask_reg = ~display_mask;
Li Peng643ced92010-01-28 01:05:09 +08001322 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001323
1324 /* should always can generate irq */
1325 I915_WRITE(DEIIR, I915_READ(DEIIR));
1326 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1327 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1328 (void) I915_READ(DEIER);
1329
1330 /* user interrupt should be enabled, but masked initial */
1331 dev_priv->gt_irq_mask_reg = 0xffffffff;
1332 dev_priv->gt_irq_enable_reg = render_mask;
1333
1334 I915_WRITE(GTIIR, I915_READ(GTIIR));
1335 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1336 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1337 (void) I915_READ(GTIER);
1338
Zhenyu Wangc6501562009-11-03 18:57:21 +00001339 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1340 dev_priv->pch_irq_enable_reg = hotplug_mask;
1341
1342 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1343 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1344 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1345 (void) I915_READ(SDEIER);
1346
Jesse Barnesf97108d2010-01-29 11:27:07 -08001347 if (IS_IRONLAKE_M(dev)) {
1348 /* Clear & enable PCU event interrupts */
1349 I915_WRITE(DEIIR, DE_PCU_EVENT);
1350 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1351 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1352 }
1353
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001354 return 0;
1355}
1356
Dave Airlie84b1fd12007-07-11 15:53:27 +10001357void i915_driver_irq_preinstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358{
1359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1360
Jesse Barnes79e53942008-11-07 14:24:08 -08001361 atomic_set(&dev_priv->irq_received, 0);
1362
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001363 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Jesse Barnes8a905232009-07-11 16:48:03 -04001364 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001365
Eric Anholtbad720f2009-10-22 16:11:14 -07001366 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001367 ironlake_irq_preinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001368 return;
1369 }
1370
Jesse Barnes5ca58282009-03-31 14:11:15 -07001371 if (I915_HAS_HOTPLUG(dev)) {
1372 I915_WRITE(PORT_HOTPLUG_EN, 0);
1373 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1374 }
1375
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001376 I915_WRITE(HWSTAM, 0xeffe);
Keith Packard7c463582008-11-04 02:03:27 -08001377 I915_WRITE(PIPEASTAT, 0);
1378 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001379 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001380 I915_WRITE(IER, 0x0);
Keith Packard7c463582008-11-04 02:03:27 -08001381 (void) I915_READ(IER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382}
1383
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001384/*
1385 * Must be called after intel_modeset_init or hotplug interrupts won't be
1386 * enabled correctly.
1387 */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001388int i915_driver_irq_postinstall(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389{
1390 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes5ca58282009-03-31 14:11:15 -07001391 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001392 u32 error_mask;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001393
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001394 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1395
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001396 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001397
Eric Anholtbad720f2009-10-22 16:11:14 -07001398 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001399 return ironlake_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001400
Keith Packard7c463582008-11-04 02:03:27 -08001401 /* Unmask the interrupts that we always want on. */
1402 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001403
Keith Packard7c463582008-11-04 02:03:27 -08001404 dev_priv->pipestat[0] = 0;
1405 dev_priv->pipestat[1] = 0;
1406
Jesse Barnes5ca58282009-03-31 14:11:15 -07001407 if (I915_HAS_HOTPLUG(dev)) {
1408 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1409
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001410 /* Note HDMI and DP share bits */
1411 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1412 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1413 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1414 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1415 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1416 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1417 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1418 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1419 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1420 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1421 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1422 hotplug_en |= CRT_HOTPLUG_INT_EN;
1423 /* Ignore TV since it's buggy */
1424
Jesse Barnes5ca58282009-03-31 14:11:15 -07001425 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1426
Jesse Barnes5ca58282009-03-31 14:11:15 -07001427 /* Enable in IER... */
1428 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1429 /* and unmask in IMR */
1430 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1431 }
1432
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001433 /*
1434 * Enable some error detection, note the instruction error mask
1435 * bit is reserved, so we leave it masked.
1436 */
1437 if (IS_G4X(dev)) {
1438 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1439 GM45_ERROR_MEM_PRIV |
1440 GM45_ERROR_CP_PRIV |
1441 I915_ERROR_MEMORY_REFRESH);
1442 } else {
1443 error_mask = ~(I915_ERROR_PAGE_TABLE |
1444 I915_ERROR_MEMORY_REFRESH);
1445 }
1446 I915_WRITE(EMR, error_mask);
1447
Keith Packard7c463582008-11-04 02:03:27 -08001448 /* Disable pipe interrupt enables, clear pending pipe status */
1449 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1450 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1451 /* Clear pending interrupt status */
1452 I915_WRITE(IIR, I915_READ(IIR));
1453
Jesse Barnes5ca58282009-03-31 14:11:15 -07001454 I915_WRITE(IER, enable_mask);
Keith Packard7c463582008-11-04 02:03:27 -08001455 I915_WRITE(IMR, dev_priv->irq_mask_reg);
Eric Anholted4cb412008-07-29 12:10:39 -07001456 (void) I915_READ(IER);
1457
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001458 opregion_enable_asle(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001459
1460 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461}
1462
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001463static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001464{
1465 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1466 I915_WRITE(HWSTAM, 0xffffffff);
1467
1468 I915_WRITE(DEIMR, 0xffffffff);
1469 I915_WRITE(DEIER, 0x0);
1470 I915_WRITE(DEIIR, I915_READ(DEIIR));
1471
1472 I915_WRITE(GTIMR, 0xffffffff);
1473 I915_WRITE(GTIER, 0x0);
1474 I915_WRITE(GTIIR, I915_READ(GTIIR));
1475}
1476
Dave Airlie84b1fd12007-07-11 15:53:27 +10001477void i915_driver_irq_uninstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478{
1479 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie91e37382006-02-18 15:17:04 +11001480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 if (!dev_priv)
1482 return;
1483
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001484 dev_priv->vblank_pipe = 0;
1485
Eric Anholtbad720f2009-10-22 16:11:14 -07001486 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001487 ironlake_irq_uninstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001488 return;
1489 }
1490
Jesse Barnes5ca58282009-03-31 14:11:15 -07001491 if (I915_HAS_HOTPLUG(dev)) {
1492 I915_WRITE(PORT_HOTPLUG_EN, 0);
1493 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1494 }
1495
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001496 I915_WRITE(HWSTAM, 0xffffffff);
Keith Packard7c463582008-11-04 02:03:27 -08001497 I915_WRITE(PIPEASTAT, 0);
1498 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001499 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001500 I915_WRITE(IER, 0x0);
Dave Airlie91e37382006-02-18 15:17:04 +11001501
Keith Packard7c463582008-11-04 02:03:27 -08001502 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1503 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1504 I915_WRITE(IIR, I915_READ(IIR));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505}