Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 33 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 34 | /** |
| 35 | * RC6 is a special power stage which allows the GPU to enter an very |
| 36 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 37 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 39 | * |
| 40 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 41 | * among each other with the latency required to enter and leave RC6 and |
| 42 | * voltage consumed by the GPU in different states. |
| 43 | * |
| 44 | * The combination of the following flags define which states GPU is allowed |
| 45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 46 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 48 | * which brings the most power savings; deeper states save more power, but |
| 49 | * require higher latency to switch to and wake up. |
| 50 | */ |
| 51 | #define INTEL_RC6_ENABLE (1<<0) |
| 52 | #define INTEL_RC6p_ENABLE (1<<1) |
| 53 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 54 | |
Damien Lespiau | da2078c | 2013-02-13 15:27:27 +0000 | [diff] [blame] | 55 | static void gen9_init_clock_gating(struct drm_device *dev) |
| 56 | { |
Damien Lespiau | acd5c34 | 2014-03-26 16:55:46 +0000 | [diff] [blame] | 57 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 58 | |
| 59 | /* |
| 60 | * WaDisableSDEUnitClockGating:skl |
| 61 | * This seems to be a pre-production w/a. |
| 62 | */ |
| 63 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 64 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Damien Lespiau | 91e41d1 | 2014-03-26 17:42:50 +0000 | [diff] [blame] | 65 | |
Damien Lespiau | 3ca5da4 | 2014-03-26 18:18:01 +0000 | [diff] [blame] | 66 | /* |
| 67 | * WaDisableDgMirrorFixInHalfSliceChicken5:skl |
| 68 | * This is a pre-production w/a. |
| 69 | */ |
| 70 | I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, |
| 71 | I915_READ(GEN9_HALF_SLICE_CHICKEN5) & |
| 72 | ~GEN9_DG_MIRROR_FIX_ENABLE); |
| 73 | |
Damien Lespiau | 91e41d1 | 2014-03-26 17:42:50 +0000 | [diff] [blame] | 74 | /* Wa4x4STCOptimizationDisable:skl */ |
| 75 | I915_WRITE(CACHE_MODE_1, |
| 76 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); |
Damien Lespiau | da2078c | 2013-02-13 15:27:27 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 79 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 80 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 81 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 82 | u32 tmp; |
| 83 | |
| 84 | tmp = I915_READ(CLKCFG); |
| 85 | |
| 86 | switch (tmp & CLKCFG_FSB_MASK) { |
| 87 | case CLKCFG_FSB_533: |
| 88 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 89 | break; |
| 90 | case CLKCFG_FSB_800: |
| 91 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 92 | break; |
| 93 | case CLKCFG_FSB_667: |
| 94 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 95 | break; |
| 96 | case CLKCFG_FSB_400: |
| 97 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 98 | break; |
| 99 | } |
| 100 | |
| 101 | switch (tmp & CLKCFG_MEM_MASK) { |
| 102 | case CLKCFG_MEM_533: |
| 103 | dev_priv->mem_freq = 533; |
| 104 | break; |
| 105 | case CLKCFG_MEM_667: |
| 106 | dev_priv->mem_freq = 667; |
| 107 | break; |
| 108 | case CLKCFG_MEM_800: |
| 109 | dev_priv->mem_freq = 800; |
| 110 | break; |
| 111 | } |
| 112 | |
| 113 | /* detect pineview DDR3 setting */ |
| 114 | tmp = I915_READ(CSHRDDR3CTL); |
| 115 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 116 | } |
| 117 | |
| 118 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 119 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 120 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 121 | u16 ddrpll, csipll; |
| 122 | |
| 123 | ddrpll = I915_READ16(DDRMPLL1); |
| 124 | csipll = I915_READ16(CSIPLL0); |
| 125 | |
| 126 | switch (ddrpll & 0xff) { |
| 127 | case 0xc: |
| 128 | dev_priv->mem_freq = 800; |
| 129 | break; |
| 130 | case 0x10: |
| 131 | dev_priv->mem_freq = 1066; |
| 132 | break; |
| 133 | case 0x14: |
| 134 | dev_priv->mem_freq = 1333; |
| 135 | break; |
| 136 | case 0x18: |
| 137 | dev_priv->mem_freq = 1600; |
| 138 | break; |
| 139 | default: |
| 140 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 141 | ddrpll & 0xff); |
| 142 | dev_priv->mem_freq = 0; |
| 143 | break; |
| 144 | } |
| 145 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 146 | dev_priv->ips.r_t = dev_priv->mem_freq; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 147 | |
| 148 | switch (csipll & 0x3ff) { |
| 149 | case 0x00c: |
| 150 | dev_priv->fsb_freq = 3200; |
| 151 | break; |
| 152 | case 0x00e: |
| 153 | dev_priv->fsb_freq = 3733; |
| 154 | break; |
| 155 | case 0x010: |
| 156 | dev_priv->fsb_freq = 4266; |
| 157 | break; |
| 158 | case 0x012: |
| 159 | dev_priv->fsb_freq = 4800; |
| 160 | break; |
| 161 | case 0x014: |
| 162 | dev_priv->fsb_freq = 5333; |
| 163 | break; |
| 164 | case 0x016: |
| 165 | dev_priv->fsb_freq = 5866; |
| 166 | break; |
| 167 | case 0x018: |
| 168 | dev_priv->fsb_freq = 6400; |
| 169 | break; |
| 170 | default: |
| 171 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 172 | csipll & 0x3ff); |
| 173 | dev_priv->fsb_freq = 0; |
| 174 | break; |
| 175 | } |
| 176 | |
| 177 | if (dev_priv->fsb_freq == 3200) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 178 | dev_priv->ips.c_m = 0; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 179 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 180 | dev_priv->ips.c_m = 1; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 181 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 182 | dev_priv->ips.c_m = 2; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 183 | } |
| 184 | } |
| 185 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 186 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 187 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 188 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 189 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 190 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 191 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 192 | |
| 193 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 194 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 195 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 196 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 197 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 198 | |
| 199 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 200 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 201 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 202 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 203 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 204 | |
| 205 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 206 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 207 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 208 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 209 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 210 | |
| 211 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 212 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 213 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 214 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 215 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 216 | |
| 217 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 218 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 219 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 220 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 221 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 222 | }; |
| 223 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 224 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 225 | int is_ddr3, |
| 226 | int fsb, |
| 227 | int mem) |
| 228 | { |
| 229 | const struct cxsr_latency *latency; |
| 230 | int i; |
| 231 | |
| 232 | if (fsb == 0 || mem == 0) |
| 233 | return NULL; |
| 234 | |
| 235 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 236 | latency = &cxsr_latency_table[i]; |
| 237 | if (is_desktop == latency->is_desktop && |
| 238 | is_ddr3 == latency->is_ddr3 && |
| 239 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 240 | return latency; |
| 241 | } |
| 242 | |
| 243 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 244 | |
| 245 | return NULL; |
| 246 | } |
| 247 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 248 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 249 | { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 250 | struct drm_device *dev = dev_priv->dev; |
| 251 | u32 val; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 252 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 253 | if (IS_VALLEYVIEW(dev)) { |
| 254 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
| 255 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
| 256 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
| 257 | } else if (IS_PINEVIEW(dev)) { |
| 258 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; |
| 259 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; |
| 260 | I915_WRITE(DSPFW3, val); |
| 261 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 262 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
| 263 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); |
| 264 | I915_WRITE(FW_BLC_SELF, val); |
| 265 | } else if (IS_I915GM(dev)) { |
| 266 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
| 267 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); |
| 268 | I915_WRITE(INSTPM, val); |
| 269 | } else { |
| 270 | return; |
| 271 | } |
| 272 | |
| 273 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
| 274 | enable ? "enabled" : "disabled"); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | /* |
| 278 | * Latency for FIFO fetches is dependent on several factors: |
| 279 | * - memory configuration (speed, channels) |
| 280 | * - chipset |
| 281 | * - current MCH state |
| 282 | * It can be fairly high in some situations, so here we assume a fairly |
| 283 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 284 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 285 | * and power consumption (set it too low to save power and we might see |
| 286 | * FIFO underruns and display "flicker"). |
| 287 | * |
| 288 | * A value of 5us seems to be a good balance; safe for very low end |
| 289 | * platforms but not overly aggressive on lower latency configs. |
| 290 | */ |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 291 | static const int pessimal_latency_ns = 5000; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 292 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 293 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 294 | { |
| 295 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 296 | uint32_t dsparb = I915_READ(DSPARB); |
| 297 | int size; |
| 298 | |
| 299 | size = dsparb & 0x7f; |
| 300 | if (plane) |
| 301 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 302 | |
| 303 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 304 | plane ? "B" : "A", size); |
| 305 | |
| 306 | return size; |
| 307 | } |
| 308 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 309 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 310 | { |
| 311 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 312 | uint32_t dsparb = I915_READ(DSPARB); |
| 313 | int size; |
| 314 | |
| 315 | size = dsparb & 0x1ff; |
| 316 | if (plane) |
| 317 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 318 | size >>= 1; /* Convert to cachelines */ |
| 319 | |
| 320 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 321 | plane ? "B" : "A", size); |
| 322 | |
| 323 | return size; |
| 324 | } |
| 325 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 326 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 327 | { |
| 328 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 329 | uint32_t dsparb = I915_READ(DSPARB); |
| 330 | int size; |
| 331 | |
| 332 | size = dsparb & 0x7f; |
| 333 | size >>= 2; /* Convert to cachelines */ |
| 334 | |
| 335 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 336 | plane ? "B" : "A", |
| 337 | size); |
| 338 | |
| 339 | return size; |
| 340 | } |
| 341 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 342 | /* Pineview has different values for various configs */ |
| 343 | static const struct intel_watermark_params pineview_display_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 344 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 345 | .max_wm = PINEVIEW_MAX_WM, |
| 346 | .default_wm = PINEVIEW_DFT_WM, |
| 347 | .guard_size = PINEVIEW_GUARD_WM, |
| 348 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 349 | }; |
| 350 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 351 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 352 | .max_wm = PINEVIEW_MAX_WM, |
| 353 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, |
| 354 | .guard_size = PINEVIEW_GUARD_WM, |
| 355 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 356 | }; |
| 357 | static const struct intel_watermark_params pineview_cursor_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 358 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 359 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 360 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 361 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 362 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 363 | }; |
| 364 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 365 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 366 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 367 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 368 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 369 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 370 | }; |
| 371 | static const struct intel_watermark_params g4x_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 372 | .fifo_size = G4X_FIFO_SIZE, |
| 373 | .max_wm = G4X_MAX_WM, |
| 374 | .default_wm = G4X_MAX_WM, |
| 375 | .guard_size = 2, |
| 376 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 377 | }; |
| 378 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 379 | .fifo_size = I965_CURSOR_FIFO, |
| 380 | .max_wm = I965_CURSOR_MAX_WM, |
| 381 | .default_wm = I965_CURSOR_DFT_WM, |
| 382 | .guard_size = 2, |
| 383 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 384 | }; |
| 385 | static const struct intel_watermark_params valleyview_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 386 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
| 387 | .max_wm = VALLEYVIEW_MAX_WM, |
| 388 | .default_wm = VALLEYVIEW_MAX_WM, |
| 389 | .guard_size = 2, |
| 390 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 391 | }; |
| 392 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 393 | .fifo_size = I965_CURSOR_FIFO, |
| 394 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, |
| 395 | .default_wm = I965_CURSOR_DFT_WM, |
| 396 | .guard_size = 2, |
| 397 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 398 | }; |
| 399 | static const struct intel_watermark_params i965_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 400 | .fifo_size = I965_CURSOR_FIFO, |
| 401 | .max_wm = I965_CURSOR_MAX_WM, |
| 402 | .default_wm = I965_CURSOR_DFT_WM, |
| 403 | .guard_size = 2, |
| 404 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 405 | }; |
| 406 | static const struct intel_watermark_params i945_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 407 | .fifo_size = I945_FIFO_SIZE, |
| 408 | .max_wm = I915_MAX_WM, |
| 409 | .default_wm = 1, |
| 410 | .guard_size = 2, |
| 411 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 412 | }; |
| 413 | static const struct intel_watermark_params i915_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 414 | .fifo_size = I915_FIFO_SIZE, |
| 415 | .max_wm = I915_MAX_WM, |
| 416 | .default_wm = 1, |
| 417 | .guard_size = 2, |
| 418 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 419 | }; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 420 | static const struct intel_watermark_params i830_a_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 421 | .fifo_size = I855GM_FIFO_SIZE, |
| 422 | .max_wm = I915_MAX_WM, |
| 423 | .default_wm = 1, |
| 424 | .guard_size = 2, |
| 425 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 426 | }; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 427 | static const struct intel_watermark_params i830_bc_wm_info = { |
| 428 | .fifo_size = I855GM_FIFO_SIZE, |
| 429 | .max_wm = I915_MAX_WM/2, |
| 430 | .default_wm = 1, |
| 431 | .guard_size = 2, |
| 432 | .cacheline_size = I830_FIFO_LINE_SIZE, |
| 433 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 434 | static const struct intel_watermark_params i845_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 435 | .fifo_size = I830_FIFO_SIZE, |
| 436 | .max_wm = I915_MAX_WM, |
| 437 | .default_wm = 1, |
| 438 | .guard_size = 2, |
| 439 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 440 | }; |
| 441 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 442 | /** |
| 443 | * intel_calculate_wm - calculate watermark level |
| 444 | * @clock_in_khz: pixel clock |
| 445 | * @wm: chip FIFO params |
| 446 | * @pixel_size: display pixel size |
| 447 | * @latency_ns: memory latency for the platform |
| 448 | * |
| 449 | * Calculate the watermark level (the level at which the display plane will |
| 450 | * start fetching from memory again). Each chip has a different display |
| 451 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 452 | * in the correct intel_watermark_params structure. |
| 453 | * |
| 454 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 455 | * on the pixel size. When it reaches the watermark level, it'll start |
| 456 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 457 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 458 | * will occur, and a display engine hang could result. |
| 459 | */ |
| 460 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 461 | const struct intel_watermark_params *wm, |
| 462 | int fifo_size, |
| 463 | int pixel_size, |
| 464 | unsigned long latency_ns) |
| 465 | { |
| 466 | long entries_required, wm_size; |
| 467 | |
| 468 | /* |
| 469 | * Note: we need to make sure we don't overflow for various clock & |
| 470 | * latency values. |
| 471 | * clocks go from a few thousand to several hundred thousand. |
| 472 | * latency is usually a few thousand |
| 473 | */ |
| 474 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 475 | 1000; |
| 476 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 477 | |
| 478 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 479 | |
| 480 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 481 | |
| 482 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 483 | |
| 484 | /* Don't promote wm_size to unsigned... */ |
| 485 | if (wm_size > (long)wm->max_wm) |
| 486 | wm_size = wm->max_wm; |
| 487 | if (wm_size <= 0) |
| 488 | wm_size = wm->default_wm; |
Ville Syrjälä | d6feb19 | 2014-09-05 21:54:13 +0300 | [diff] [blame] | 489 | |
| 490 | /* |
| 491 | * Bspec seems to indicate that the value shouldn't be lower than |
| 492 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. |
| 493 | * Lets go for 8 which is the burst size since certain platforms |
| 494 | * already use a hardcoded 8 (which is what the spec says should be |
| 495 | * done). |
| 496 | */ |
| 497 | if (wm_size <= 8) |
| 498 | wm_size = 8; |
| 499 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 500 | return wm_size; |
| 501 | } |
| 502 | |
| 503 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 504 | { |
| 505 | struct drm_crtc *crtc, *enabled = NULL; |
| 506 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 507 | for_each_crtc(dev, crtc) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 508 | if (intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 509 | if (enabled) |
| 510 | return NULL; |
| 511 | enabled = crtc; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | return enabled; |
| 516 | } |
| 517 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 518 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 519 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 520 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 521 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 522 | struct drm_crtc *crtc; |
| 523 | const struct cxsr_latency *latency; |
| 524 | u32 reg; |
| 525 | unsigned long wm; |
| 526 | |
| 527 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 528 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 529 | if (!latency) { |
| 530 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 531 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 532 | return; |
| 533 | } |
| 534 | |
| 535 | crtc = single_enabled_crtc(dev); |
| 536 | if (crtc) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 537 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 538 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 539 | int clock; |
| 540 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 541 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 542 | clock = adjusted_mode->crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 543 | |
| 544 | /* Display SR */ |
| 545 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 546 | pineview_display_wm.fifo_size, |
| 547 | pixel_size, latency->display_sr); |
| 548 | reg = I915_READ(DSPFW1); |
| 549 | reg &= ~DSPFW_SR_MASK; |
| 550 | reg |= wm << DSPFW_SR_SHIFT; |
| 551 | I915_WRITE(DSPFW1, reg); |
| 552 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 553 | |
| 554 | /* cursor SR */ |
| 555 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 556 | pineview_display_wm.fifo_size, |
| 557 | pixel_size, latency->cursor_sr); |
| 558 | reg = I915_READ(DSPFW3); |
| 559 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 560 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 561 | I915_WRITE(DSPFW3, reg); |
| 562 | |
| 563 | /* Display HPLL off SR */ |
| 564 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 565 | pineview_display_hplloff_wm.fifo_size, |
| 566 | pixel_size, latency->display_hpll_disable); |
| 567 | reg = I915_READ(DSPFW3); |
| 568 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 569 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 570 | I915_WRITE(DSPFW3, reg); |
| 571 | |
| 572 | /* cursor HPLL off SR */ |
| 573 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 574 | pineview_display_hplloff_wm.fifo_size, |
| 575 | pixel_size, latency->cursor_hpll_disable); |
| 576 | reg = I915_READ(DSPFW3); |
| 577 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 578 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 579 | I915_WRITE(DSPFW3, reg); |
| 580 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 581 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 582 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 583 | } else { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 584 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 585 | } |
| 586 | } |
| 587 | |
| 588 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 589 | int plane, |
| 590 | const struct intel_watermark_params *display, |
| 591 | int display_latency_ns, |
| 592 | const struct intel_watermark_params *cursor, |
| 593 | int cursor_latency_ns, |
| 594 | int *plane_wm, |
| 595 | int *cursor_wm) |
| 596 | { |
| 597 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 598 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 599 | int htotal, hdisplay, clock, pixel_size; |
| 600 | int line_time_us, line_count; |
| 601 | int entries, tlb_miss; |
| 602 | |
| 603 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 604 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 605 | *cursor_wm = cursor->guard_size; |
| 606 | *plane_wm = display->guard_size; |
| 607 | return false; |
| 608 | } |
| 609 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 610 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 611 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 612 | htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 613 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 614 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 615 | |
| 616 | /* Use the small buffer method to calculate plane watermark */ |
| 617 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 618 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 619 | if (tlb_miss > 0) |
| 620 | entries += tlb_miss; |
| 621 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 622 | *plane_wm = entries + display->guard_size; |
| 623 | if (*plane_wm > (int)display->max_wm) |
| 624 | *plane_wm = display->max_wm; |
| 625 | |
| 626 | /* Use the large buffer method to calculate cursor watermark */ |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 627 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 628 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 629 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 630 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 631 | if (tlb_miss > 0) |
| 632 | entries += tlb_miss; |
| 633 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 634 | *cursor_wm = entries + cursor->guard_size; |
| 635 | if (*cursor_wm > (int)cursor->max_wm) |
| 636 | *cursor_wm = (int)cursor->max_wm; |
| 637 | |
| 638 | return true; |
| 639 | } |
| 640 | |
| 641 | /* |
| 642 | * Check the wm result. |
| 643 | * |
| 644 | * If any calculated watermark values is larger than the maximum value that |
| 645 | * can be programmed into the associated watermark register, that watermark |
| 646 | * must be disabled. |
| 647 | */ |
| 648 | static bool g4x_check_srwm(struct drm_device *dev, |
| 649 | int display_wm, int cursor_wm, |
| 650 | const struct intel_watermark_params *display, |
| 651 | const struct intel_watermark_params *cursor) |
| 652 | { |
| 653 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 654 | display_wm, cursor_wm); |
| 655 | |
| 656 | if (display_wm > display->max_wm) { |
| 657 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 658 | display_wm, display->max_wm); |
| 659 | return false; |
| 660 | } |
| 661 | |
| 662 | if (cursor_wm > cursor->max_wm) { |
| 663 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 664 | cursor_wm, cursor->max_wm); |
| 665 | return false; |
| 666 | } |
| 667 | |
| 668 | if (!(display_wm || cursor_wm)) { |
| 669 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 670 | return false; |
| 671 | } |
| 672 | |
| 673 | return true; |
| 674 | } |
| 675 | |
| 676 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 677 | int plane, |
| 678 | int latency_ns, |
| 679 | const struct intel_watermark_params *display, |
| 680 | const struct intel_watermark_params *cursor, |
| 681 | int *display_wm, int *cursor_wm) |
| 682 | { |
| 683 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 684 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 685 | int hdisplay, htotal, pixel_size, clock; |
| 686 | unsigned long line_time_us; |
| 687 | int line_count, line_size; |
| 688 | int small, large; |
| 689 | int entries; |
| 690 | |
| 691 | if (!latency_ns) { |
| 692 | *display_wm = *cursor_wm = 0; |
| 693 | return false; |
| 694 | } |
| 695 | |
| 696 | crtc = intel_get_crtc_for_plane(dev, plane); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 697 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 698 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 699 | htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 700 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 701 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 702 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 703 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 704 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 705 | line_size = hdisplay * pixel_size; |
| 706 | |
| 707 | /* Use the minimum of the small and large buffer method for primary */ |
| 708 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 709 | large = line_count * line_size; |
| 710 | |
| 711 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 712 | *display_wm = entries + display->guard_size; |
| 713 | |
| 714 | /* calculate the self-refresh watermark for display cursor */ |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 715 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 716 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 717 | *cursor_wm = entries + cursor->guard_size; |
| 718 | |
| 719 | return g4x_check_srwm(dev, |
| 720 | *display_wm, *cursor_wm, |
| 721 | display, cursor); |
| 722 | } |
| 723 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 724 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, |
| 725 | int pixel_size, |
| 726 | int *prec_mult, |
| 727 | int *drain_latency) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 728 | { |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 729 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 730 | int entries; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 731 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 732 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 733 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 734 | return false; |
| 735 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 736 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
| 737 | return false; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 738 | |
Gajanan Bhat | a398e9c | 2014-08-05 23:15:54 +0530 | [diff] [blame] | 739 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 740 | if (IS_CHERRYVIEW(dev)) |
| 741 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 : |
| 742 | DRAIN_LATENCY_PRECISION_16; |
| 743 | else |
| 744 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : |
| 745 | DRAIN_LATENCY_PRECISION_32; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 746 | *drain_latency = (64 * (*prec_mult) * 4) / entries; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 747 | |
Gajanan Bhat | a398e9c | 2014-08-05 23:15:54 +0530 | [diff] [blame] | 748 | if (*drain_latency > DRAIN_LATENCY_MASK) |
| 749 | *drain_latency = DRAIN_LATENCY_MASK; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 750 | |
| 751 | return true; |
| 752 | } |
| 753 | |
| 754 | /* |
| 755 | * Update drain latency registers of memory arbiter |
| 756 | * |
| 757 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
| 758 | * to be programmed. Each plane has a drain latency multiplier and a drain |
| 759 | * latency value. |
| 760 | */ |
| 761 | |
Gajanan Bhat | 41aad81 | 2014-07-16 18:24:03 +0530 | [diff] [blame] | 762 | static void vlv_update_drain_latency(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 763 | { |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 764 | struct drm_device *dev = crtc->dev; |
| 765 | struct drm_i915_private *dev_priv = dev->dev_private; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 767 | int pixel_size; |
| 768 | int drain_latency; |
| 769 | enum pipe pipe = intel_crtc->pipe; |
| 770 | int plane_prec, prec_mult, plane_dl; |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 771 | const int high_precision = IS_CHERRYVIEW(dev) ? |
| 772 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 773 | |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 774 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH | |
| 775 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 776 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 777 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 778 | if (!intel_crtc_active(crtc)) { |
| 779 | I915_WRITE(VLV_DDL(pipe), plane_dl); |
| 780 | return; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 781 | } |
| 782 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 783 | /* Primary plane Drain Latency */ |
| 784 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ |
| 785 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 786 | plane_prec = (prec_mult == high_precision) ? |
| 787 | DDL_PLANE_PRECISION_HIGH : |
| 788 | DDL_PLANE_PRECISION_LOW; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 789 | plane_dl |= plane_prec | drain_latency; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 790 | } |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 791 | |
| 792 | /* Cursor Drain Latency |
| 793 | * BPP is always 4 for cursor |
| 794 | */ |
| 795 | pixel_size = 4; |
| 796 | |
| 797 | /* Program cursor DL only if it is enabled */ |
| 798 | if (intel_crtc->cursor_base && |
| 799 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 800 | plane_prec = (prec_mult == high_precision) ? |
| 801 | DDL_CURSOR_PRECISION_HIGH : |
| 802 | DDL_CURSOR_PRECISION_LOW; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 803 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); |
| 804 | } |
| 805 | |
| 806 | I915_WRITE(VLV_DDL(pipe), plane_dl); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 810 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 811 | static void valleyview_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 812 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 813 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 814 | static const int sr_latency_ns = 12000; |
| 815 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 816 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 817 | int plane_sr, cursor_sr; |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 818 | int ignore_plane_sr, ignore_cursor_sr; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 819 | unsigned int enabled = 0; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 820 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 821 | |
Gajanan Bhat | 41aad81 | 2014-07-16 18:24:03 +0530 | [diff] [blame] | 822 | vlv_update_drain_latency(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 823 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 824 | if (g4x_compute_wm0(dev, PIPE_A, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 825 | &valleyview_wm_info, pessimal_latency_ns, |
| 826 | &valleyview_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 827 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 828 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 829 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 830 | if (g4x_compute_wm0(dev, PIPE_B, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 831 | &valleyview_wm_info, pessimal_latency_ns, |
| 832 | &valleyview_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 833 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 834 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 835 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 836 | if (single_plane_enabled(enabled) && |
| 837 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 838 | sr_latency_ns, |
| 839 | &valleyview_wm_info, |
| 840 | &valleyview_cursor_wm_info, |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 841 | &plane_sr, &ignore_cursor_sr) && |
| 842 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 843 | 2*sr_latency_ns, |
| 844 | &valleyview_wm_info, |
| 845 | &valleyview_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 846 | &ignore_plane_sr, &cursor_sr)) { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 847 | cxsr_enabled = true; |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 848 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 849 | cxsr_enabled = false; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 850 | intel_set_memory_cxsr(dev_priv, false); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 851 | plane_sr = cursor_sr = 0; |
| 852 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 853 | |
Ville Syrjälä | a504345 | 2014-06-28 02:04:18 +0300 | [diff] [blame] | 854 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 855 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 856 | planea_wm, cursora_wm, |
| 857 | planeb_wm, cursorb_wm, |
| 858 | plane_sr, cursor_sr); |
| 859 | |
| 860 | I915_WRITE(DSPFW1, |
| 861 | (plane_sr << DSPFW_SR_SHIFT) | |
| 862 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 863 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 864 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 865 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 866 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 867 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 868 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 869 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 870 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 871 | |
| 872 | if (cxsr_enabled) |
| 873 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 874 | } |
| 875 | |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 876 | static void cherryview_update_wm(struct drm_crtc *crtc) |
| 877 | { |
| 878 | struct drm_device *dev = crtc->dev; |
| 879 | static const int sr_latency_ns = 12000; |
| 880 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 881 | int planea_wm, planeb_wm, planec_wm; |
| 882 | int cursora_wm, cursorb_wm, cursorc_wm; |
| 883 | int plane_sr, cursor_sr; |
| 884 | int ignore_plane_sr, ignore_cursor_sr; |
| 885 | unsigned int enabled = 0; |
| 886 | bool cxsr_enabled; |
| 887 | |
| 888 | vlv_update_drain_latency(crtc); |
| 889 | |
| 890 | if (g4x_compute_wm0(dev, PIPE_A, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 891 | &valleyview_wm_info, pessimal_latency_ns, |
| 892 | &valleyview_cursor_wm_info, pessimal_latency_ns, |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 893 | &planea_wm, &cursora_wm)) |
| 894 | enabled |= 1 << PIPE_A; |
| 895 | |
| 896 | if (g4x_compute_wm0(dev, PIPE_B, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 897 | &valleyview_wm_info, pessimal_latency_ns, |
| 898 | &valleyview_cursor_wm_info, pessimal_latency_ns, |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 899 | &planeb_wm, &cursorb_wm)) |
| 900 | enabled |= 1 << PIPE_B; |
| 901 | |
| 902 | if (g4x_compute_wm0(dev, PIPE_C, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 903 | &valleyview_wm_info, pessimal_latency_ns, |
| 904 | &valleyview_cursor_wm_info, pessimal_latency_ns, |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 905 | &planec_wm, &cursorc_wm)) |
| 906 | enabled |= 1 << PIPE_C; |
| 907 | |
| 908 | if (single_plane_enabled(enabled) && |
| 909 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 910 | sr_latency_ns, |
| 911 | &valleyview_wm_info, |
| 912 | &valleyview_cursor_wm_info, |
| 913 | &plane_sr, &ignore_cursor_sr) && |
| 914 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 915 | 2*sr_latency_ns, |
| 916 | &valleyview_wm_info, |
| 917 | &valleyview_cursor_wm_info, |
| 918 | &ignore_plane_sr, &cursor_sr)) { |
| 919 | cxsr_enabled = true; |
| 920 | } else { |
| 921 | cxsr_enabled = false; |
| 922 | intel_set_memory_cxsr(dev_priv, false); |
| 923 | plane_sr = cursor_sr = 0; |
| 924 | } |
| 925 | |
| 926 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 927 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " |
| 928 | "SR: plane=%d, cursor=%d\n", |
| 929 | planea_wm, cursora_wm, |
| 930 | planeb_wm, cursorb_wm, |
| 931 | planec_wm, cursorc_wm, |
| 932 | plane_sr, cursor_sr); |
| 933 | |
| 934 | I915_WRITE(DSPFW1, |
| 935 | (plane_sr << DSPFW_SR_SHIFT) | |
| 936 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 937 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 938 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
| 939 | I915_WRITE(DSPFW2, |
| 940 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
| 941 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 942 | I915_WRITE(DSPFW3, |
| 943 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 944 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 945 | I915_WRITE(DSPFW9_CHV, |
| 946 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | |
| 947 | DSPFW_CURSORC_MASK)) | |
| 948 | (planec_wm << DSPFW_PLANEC_SHIFT) | |
| 949 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); |
| 950 | |
| 951 | if (cxsr_enabled) |
| 952 | intel_set_memory_cxsr(dev_priv, true); |
| 953 | } |
| 954 | |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 955 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
| 956 | struct drm_crtc *crtc, |
| 957 | uint32_t sprite_width, |
| 958 | uint32_t sprite_height, |
| 959 | int pixel_size, |
| 960 | bool enabled, bool scaled) |
| 961 | { |
| 962 | struct drm_device *dev = crtc->dev; |
| 963 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 964 | int pipe = to_intel_plane(plane)->pipe; |
| 965 | int sprite = to_intel_plane(plane)->plane; |
| 966 | int drain_latency; |
| 967 | int plane_prec; |
| 968 | int sprite_dl; |
| 969 | int prec_mult; |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 970 | const int high_precision = IS_CHERRYVIEW(dev) ? |
| 971 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 972 | |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 973 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) | |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 974 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); |
| 975 | |
| 976 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, |
| 977 | &drain_latency)) { |
Rodrigo Vivi | 5e56ba4 | 2014-10-17 08:05:08 -0700 | [diff] [blame] | 978 | plane_prec = (prec_mult == high_precision) ? |
| 979 | DDL_SPRITE_PRECISION_HIGH(sprite) : |
| 980 | DDL_SPRITE_PRECISION_LOW(sprite); |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 981 | sprite_dl |= plane_prec | |
| 982 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); |
| 983 | } |
| 984 | |
| 985 | I915_WRITE(VLV_DDL(pipe), sprite_dl); |
| 986 | } |
| 987 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 988 | static void g4x_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 989 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 990 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 991 | static const int sr_latency_ns = 12000; |
| 992 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 993 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 994 | int plane_sr, cursor_sr; |
| 995 | unsigned int enabled = 0; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 996 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 997 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 998 | if (g4x_compute_wm0(dev, PIPE_A, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 999 | &g4x_wm_info, pessimal_latency_ns, |
| 1000 | &g4x_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1001 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1002 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1003 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1004 | if (g4x_compute_wm0(dev, PIPE_B, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1005 | &g4x_wm_info, pessimal_latency_ns, |
| 1006 | &g4x_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1007 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1008 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1009 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1010 | if (single_plane_enabled(enabled) && |
| 1011 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1012 | sr_latency_ns, |
| 1013 | &g4x_wm_info, |
| 1014 | &g4x_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1015 | &plane_sr, &cursor_sr)) { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1016 | cxsr_enabled = true; |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1017 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1018 | cxsr_enabled = false; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1019 | intel_set_memory_cxsr(dev_priv, false); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1020 | plane_sr = cursor_sr = 0; |
| 1021 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1022 | |
Ville Syrjälä | a504345 | 2014-06-28 02:04:18 +0300 | [diff] [blame] | 1023 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 1024 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1025 | planea_wm, cursora_wm, |
| 1026 | planeb_wm, cursorb_wm, |
| 1027 | plane_sr, cursor_sr); |
| 1028 | |
| 1029 | I915_WRITE(DSPFW1, |
| 1030 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1031 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1032 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 1033 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1034 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1035 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1036 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1037 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1038 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1039 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1040 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1041 | |
| 1042 | if (cxsr_enabled) |
| 1043 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1044 | } |
| 1045 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1046 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1047 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1048 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1049 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1050 | struct drm_crtc *crtc; |
| 1051 | int srwm = 1; |
| 1052 | int cursor_sr = 16; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1053 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1054 | |
| 1055 | /* Calc sr entries for one plane configs */ |
| 1056 | crtc = single_enabled_crtc(dev); |
| 1057 | if (crtc) { |
| 1058 | /* self-refresh has much higher latency */ |
| 1059 | static const int sr_latency_ns = 12000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1060 | const struct drm_display_mode *adjusted_mode = |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1061 | &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1062 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1063 | int htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1064 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1065 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1066 | unsigned long line_time_us; |
| 1067 | int entries; |
| 1068 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1069 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1070 | |
| 1071 | /* Use ns/us then divide to preserve precision */ |
| 1072 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1073 | pixel_size * hdisplay; |
| 1074 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1075 | srwm = I965_FIFO_SIZE - entries; |
| 1076 | if (srwm < 0) |
| 1077 | srwm = 1; |
| 1078 | srwm &= 0x1ff; |
| 1079 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1080 | entries, srwm); |
| 1081 | |
| 1082 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1083 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1084 | entries = DIV_ROUND_UP(entries, |
| 1085 | i965_cursor_wm_info.cacheline_size); |
| 1086 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1087 | (entries + i965_cursor_wm_info.guard_size); |
| 1088 | |
| 1089 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1090 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1091 | |
| 1092 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1093 | "cursor %d\n", srwm, cursor_sr); |
| 1094 | |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1095 | cxsr_enabled = true; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1096 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1097 | cxsr_enabled = false; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1098 | /* Turn off self refresh if both pipes are enabled */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1099 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1100 | } |
| 1101 | |
| 1102 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1103 | srwm); |
| 1104 | |
| 1105 | /* 965 has limitations... */ |
| 1106 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 1107 | (8 << DSPFW_CURSORB_SHIFT) | |
| 1108 | (8 << DSPFW_PLANEB_SHIFT) | |
| 1109 | (8 << DSPFW_PLANEA_SHIFT)); |
| 1110 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | |
| 1111 | (8 << DSPFW_PLANEC_SHIFT_OLD)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1112 | /* update cursor SR watermark */ |
| 1113 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1114 | |
| 1115 | if (cxsr_enabled) |
| 1116 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1117 | } |
| 1118 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1119 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1120 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1121 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1122 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1123 | const struct intel_watermark_params *wm_info; |
| 1124 | uint32_t fwater_lo; |
| 1125 | uint32_t fwater_hi; |
| 1126 | int cwm, srwm = 1; |
| 1127 | int fifo_size; |
| 1128 | int planea_wm, planeb_wm; |
| 1129 | struct drm_crtc *crtc, *enabled = NULL; |
| 1130 | |
| 1131 | if (IS_I945GM(dev)) |
| 1132 | wm_info = &i945_wm_info; |
| 1133 | else if (!IS_GEN2(dev)) |
| 1134 | wm_info = &i915_wm_info; |
| 1135 | else |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1136 | wm_info = &i830_a_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1137 | |
| 1138 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1139 | crtc = intel_get_crtc_for_plane(dev, 0); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1140 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1141 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1142 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1143 | if (IS_GEN2(dev)) |
| 1144 | cpp = 4; |
| 1145 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1146 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1147 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1148 | wm_info, fifo_size, cpp, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1149 | pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1150 | enabled = crtc; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1151 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1152 | planea_wm = fifo_size - wm_info->guard_size; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1153 | if (planea_wm > (long)wm_info->max_wm) |
| 1154 | planea_wm = wm_info->max_wm; |
| 1155 | } |
| 1156 | |
| 1157 | if (IS_GEN2(dev)) |
| 1158 | wm_info = &i830_bc_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1159 | |
| 1160 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1161 | crtc = intel_get_crtc_for_plane(dev, 1); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1162 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1163 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1164 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1165 | if (IS_GEN2(dev)) |
| 1166 | cpp = 4; |
| 1167 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1168 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1169 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1170 | wm_info, fifo_size, cpp, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1171 | pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1172 | if (enabled == NULL) |
| 1173 | enabled = crtc; |
| 1174 | else |
| 1175 | enabled = NULL; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1176 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1177 | planeb_wm = fifo_size - wm_info->guard_size; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1178 | if (planeb_wm > (long)wm_info->max_wm) |
| 1179 | planeb_wm = wm_info->max_wm; |
| 1180 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1181 | |
| 1182 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1183 | |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1184 | if (IS_I915GM(dev) && enabled) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1185 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1186 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1187 | obj = intel_fb_obj(enabled->primary->fb); |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1188 | |
| 1189 | /* self-refresh seems busted with untiled */ |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1190 | if (obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1191 | enabled = NULL; |
| 1192 | } |
| 1193 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1194 | /* |
| 1195 | * Overlay gets an aggressive default since video jitter is bad. |
| 1196 | */ |
| 1197 | cwm = 2; |
| 1198 | |
| 1199 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1200 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1201 | |
| 1202 | /* Calc sr entries for one plane configs */ |
| 1203 | if (HAS_FW_BLC(dev) && enabled) { |
| 1204 | /* self-refresh has much higher latency */ |
| 1205 | static const int sr_latency_ns = 6000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1206 | const struct drm_display_mode *adjusted_mode = |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1207 | &to_intel_crtc(enabled)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1208 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1209 | int htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1210 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1211 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1212 | unsigned long line_time_us; |
| 1213 | int entries; |
| 1214 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1215 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1216 | |
| 1217 | /* Use ns/us then divide to preserve precision */ |
| 1218 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1219 | pixel_size * hdisplay; |
| 1220 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1221 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1222 | srwm = wm_info->fifo_size - entries; |
| 1223 | if (srwm < 0) |
| 1224 | srwm = 1; |
| 1225 | |
| 1226 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1227 | I915_WRITE(FW_BLC_SELF, |
| 1228 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1229 | else if (IS_I915GM(dev)) |
| 1230 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1231 | } |
| 1232 | |
| 1233 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1234 | planea_wm, planeb_wm, cwm, srwm); |
| 1235 | |
| 1236 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1237 | fwater_hi = (cwm & 0x1f); |
| 1238 | |
| 1239 | /* Set request length to 8 cachelines per fetch */ |
| 1240 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1241 | fwater_hi = fwater_hi | (1 << 8); |
| 1242 | |
| 1243 | I915_WRITE(FW_BLC, fwater_lo); |
| 1244 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1245 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1246 | if (enabled) |
| 1247 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1248 | } |
| 1249 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1250 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1251 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1252 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1253 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1254 | struct drm_crtc *crtc; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1255 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1256 | uint32_t fwater_lo; |
| 1257 | int planea_wm; |
| 1258 | |
| 1259 | crtc = single_enabled_crtc(dev); |
| 1260 | if (crtc == NULL) |
| 1261 | return; |
| 1262 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1263 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1264 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1265 | &i845_wm_info, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1266 | dev_priv->display.get_fifo_size(dev, 0), |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1267 | 4, pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1268 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1269 | fwater_lo |= (3<<8) | planea_wm; |
| 1270 | |
| 1271 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1272 | |
| 1273 | I915_WRITE(FW_BLC, fwater_lo); |
| 1274 | } |
| 1275 | |
Ville Syrjälä | 3658729 | 2013-07-05 11:57:16 +0300 | [diff] [blame] | 1276 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
| 1277 | struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1278 | { |
| 1279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1280 | uint32_t pixel_rate; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1281 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1282 | pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1283 | |
| 1284 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
| 1285 | * adjust the pixel_rate here. */ |
| 1286 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1287 | if (intel_crtc->config->pch_pfit.enabled) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1288 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1289 | uint32_t pfit_size = intel_crtc->config->pch_pfit.size; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1290 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1291 | pipe_w = intel_crtc->config->pipe_src_w; |
| 1292 | pipe_h = intel_crtc->config->pipe_src_h; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1293 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
| 1294 | pfit_h = pfit_size & 0xFFFF; |
| 1295 | if (pipe_w < pfit_w) |
| 1296 | pipe_w = pfit_w; |
| 1297 | if (pipe_h < pfit_h) |
| 1298 | pipe_h = pfit_h; |
| 1299 | |
| 1300 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
| 1301 | pfit_w * pfit_h); |
| 1302 | } |
| 1303 | |
| 1304 | return pixel_rate; |
| 1305 | } |
| 1306 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1307 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1308 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1309 | uint32_t latency) |
| 1310 | { |
| 1311 | uint64_t ret; |
| 1312 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1313 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1314 | return UINT_MAX; |
| 1315 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1316 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
| 1317 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
| 1318 | |
| 1319 | return ret; |
| 1320 | } |
| 1321 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1322 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1323 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1324 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 1325 | uint32_t latency) |
| 1326 | { |
| 1327 | uint32_t ret; |
| 1328 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1329 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1330 | return UINT_MAX; |
| 1331 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1332 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 1333 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 1334 | ret = DIV_ROUND_UP(ret, 64) + 2; |
| 1335 | return ret; |
| 1336 | } |
| 1337 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1338 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1339 | uint8_t bytes_per_pixel) |
| 1340 | { |
| 1341 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
| 1342 | } |
| 1343 | |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 1344 | struct skl_pipe_wm_parameters { |
| 1345 | bool active; |
| 1346 | uint32_t pipe_htotal; |
| 1347 | uint32_t pixel_rate; /* in KHz */ |
| 1348 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; |
| 1349 | struct intel_plane_wm_parameters cursor; |
| 1350 | }; |
| 1351 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1352 | struct ilk_pipe_wm_parameters { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1353 | bool active; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1354 | uint32_t pipe_htotal; |
| 1355 | uint32_t pixel_rate; |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1356 | struct intel_plane_wm_parameters pri; |
| 1357 | struct intel_plane_wm_parameters spr; |
| 1358 | struct intel_plane_wm_parameters cur; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1359 | }; |
| 1360 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1361 | struct ilk_wm_maximums { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1362 | uint16_t pri; |
| 1363 | uint16_t spr; |
| 1364 | uint16_t cur; |
| 1365 | uint16_t fbc; |
| 1366 | }; |
| 1367 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1368 | /* used in computing the new watermarks state */ |
| 1369 | struct intel_wm_config { |
| 1370 | unsigned int num_pipes_active; |
| 1371 | bool sprites_enabled; |
| 1372 | bool sprites_scaled; |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1373 | }; |
| 1374 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1375 | /* |
| 1376 | * For both WM_PIPE and WM_LP. |
| 1377 | * mem_value must be in 0.1us units. |
| 1378 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1379 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1380 | uint32_t mem_value, |
| 1381 | bool is_lp) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1382 | { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1383 | uint32_t method1, method2; |
| 1384 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1385 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1386 | return 0; |
| 1387 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1388 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1389 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1390 | mem_value); |
| 1391 | |
| 1392 | if (!is_lp) |
| 1393 | return method1; |
| 1394 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1395 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1396 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1397 | params->pri.horiz_pixels, |
| 1398 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1399 | mem_value); |
| 1400 | |
| 1401 | return min(method1, method2); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1402 | } |
| 1403 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1404 | /* |
| 1405 | * For both WM_PIPE and WM_LP. |
| 1406 | * mem_value must be in 0.1us units. |
| 1407 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1408 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1409 | uint32_t mem_value) |
| 1410 | { |
| 1411 | uint32_t method1, method2; |
| 1412 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1413 | if (!params->active || !params->spr.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1414 | return 0; |
| 1415 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1416 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1417 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1418 | mem_value); |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1419 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1420 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1421 | params->spr.horiz_pixels, |
| 1422 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1423 | mem_value); |
| 1424 | return min(method1, method2); |
| 1425 | } |
| 1426 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1427 | /* |
| 1428 | * For both WM_PIPE and WM_LP. |
| 1429 | * mem_value must be in 0.1us units. |
| 1430 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1431 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1432 | uint32_t mem_value) |
| 1433 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1434 | if (!params->active || !params->cur.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1435 | return 0; |
| 1436 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1437 | return ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1438 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1439 | params->cur.horiz_pixels, |
| 1440 | params->cur.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1441 | mem_value); |
| 1442 | } |
| 1443 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1444 | /* Only for WM_LP. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1445 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 1fda988 | 2013-07-05 11:57:19 +0300 | [diff] [blame] | 1446 | uint32_t pri_val) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1447 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1448 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1449 | return 0; |
| 1450 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1451 | return ilk_wm_fbc(pri_val, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1452 | params->pri.horiz_pixels, |
| 1453 | params->pri.bytes_per_pixel); |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1454 | } |
| 1455 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1456 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
| 1457 | { |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 1458 | if (INTEL_INFO(dev)->gen >= 8) |
| 1459 | return 3072; |
| 1460 | else if (INTEL_INFO(dev)->gen >= 7) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1461 | return 768; |
| 1462 | else |
| 1463 | return 512; |
| 1464 | } |
| 1465 | |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1466 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
| 1467 | int level, bool is_sprite) |
| 1468 | { |
| 1469 | if (INTEL_INFO(dev)->gen >= 8) |
| 1470 | /* BDW primary/sprite plane watermarks */ |
| 1471 | return level == 0 ? 255 : 2047; |
| 1472 | else if (INTEL_INFO(dev)->gen >= 7) |
| 1473 | /* IVB/HSW primary/sprite plane watermarks */ |
| 1474 | return level == 0 ? 127 : 1023; |
| 1475 | else if (!is_sprite) |
| 1476 | /* ILK/SNB primary plane watermarks */ |
| 1477 | return level == 0 ? 127 : 511; |
| 1478 | else |
| 1479 | /* ILK/SNB sprite plane watermarks */ |
| 1480 | return level == 0 ? 63 : 255; |
| 1481 | } |
| 1482 | |
| 1483 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
| 1484 | int level) |
| 1485 | { |
| 1486 | if (INTEL_INFO(dev)->gen >= 7) |
| 1487 | return level == 0 ? 63 : 255; |
| 1488 | else |
| 1489 | return level == 0 ? 31 : 63; |
| 1490 | } |
| 1491 | |
| 1492 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
| 1493 | { |
| 1494 | if (INTEL_INFO(dev)->gen >= 8) |
| 1495 | return 31; |
| 1496 | else |
| 1497 | return 15; |
| 1498 | } |
| 1499 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1500 | /* Calculate the maximum primary/sprite plane watermark */ |
| 1501 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
| 1502 | int level, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1503 | const struct intel_wm_config *config, |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1504 | enum intel_ddb_partitioning ddb_partitioning, |
| 1505 | bool is_sprite) |
| 1506 | { |
| 1507 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1508 | |
| 1509 | /* if sprites aren't enabled, sprites get nothing */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1510 | if (is_sprite && !config->sprites_enabled) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1511 | return 0; |
| 1512 | |
| 1513 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1514 | if (level == 0 || config->num_pipes_active > 1) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1515 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
| 1516 | |
| 1517 | /* |
| 1518 | * For some reason the non self refresh |
| 1519 | * FIFO size is only half of the self |
| 1520 | * refresh FIFO size on ILK/SNB. |
| 1521 | */ |
| 1522 | if (INTEL_INFO(dev)->gen <= 6) |
| 1523 | fifo_size /= 2; |
| 1524 | } |
| 1525 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1526 | if (config->sprites_enabled) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1527 | /* level 0 is always calculated with 1:1 split */ |
| 1528 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
| 1529 | if (is_sprite) |
| 1530 | fifo_size *= 5; |
| 1531 | fifo_size /= 6; |
| 1532 | } else { |
| 1533 | fifo_size /= 2; |
| 1534 | } |
| 1535 | } |
| 1536 | |
| 1537 | /* clamp to max that the registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1538 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1539 | } |
| 1540 | |
| 1541 | /* Calculate the maximum cursor plane watermark */ |
| 1542 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1543 | int level, |
| 1544 | const struct intel_wm_config *config) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1545 | { |
| 1546 | /* HSW LP1+ watermarks w/ multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1547 | if (level > 0 && config->num_pipes_active > 1) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1548 | return 64; |
| 1549 | |
| 1550 | /* otherwise just report max that registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1551 | return ilk_cursor_wm_reg_max(dev, level); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1552 | } |
| 1553 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1554 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 1555 | int level, |
| 1556 | const struct intel_wm_config *config, |
| 1557 | enum intel_ddb_partitioning ddb_partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1558 | struct ilk_wm_maximums *max) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1559 | { |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1560 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
| 1561 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
| 1562 | max->cur = ilk_cursor_wm_max(dev, level, config); |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1563 | max->fbc = ilk_fbc_wm_reg_max(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1564 | } |
| 1565 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1566 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
| 1567 | int level, |
| 1568 | struct ilk_wm_maximums *max) |
| 1569 | { |
| 1570 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
| 1571 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
| 1572 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
| 1573 | max->fbc = ilk_fbc_wm_reg_max(dev); |
| 1574 | } |
| 1575 | |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1576 | static bool ilk_validate_wm_level(int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1577 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1578 | struct intel_wm_level *result) |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 1579 | { |
| 1580 | bool ret; |
| 1581 | |
| 1582 | /* already determined to be invalid? */ |
| 1583 | if (!result->enable) |
| 1584 | return false; |
| 1585 | |
| 1586 | result->enable = result->pri_val <= max->pri && |
| 1587 | result->spr_val <= max->spr && |
| 1588 | result->cur_val <= max->cur; |
| 1589 | |
| 1590 | ret = result->enable; |
| 1591 | |
| 1592 | /* |
| 1593 | * HACK until we can pre-compute everything, |
| 1594 | * and thus fail gracefully if LP0 watermarks |
| 1595 | * are exceeded... |
| 1596 | */ |
| 1597 | if (level == 0 && !result->enable) { |
| 1598 | if (result->pri_val > max->pri) |
| 1599 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
| 1600 | level, result->pri_val, max->pri); |
| 1601 | if (result->spr_val > max->spr) |
| 1602 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
| 1603 | level, result->spr_val, max->spr); |
| 1604 | if (result->cur_val > max->cur) |
| 1605 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
| 1606 | level, result->cur_val, max->cur); |
| 1607 | |
| 1608 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
| 1609 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
| 1610 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
| 1611 | result->enable = true; |
| 1612 | } |
| 1613 | |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 1614 | return ret; |
| 1615 | } |
| 1616 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1617 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 1618 | int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1619 | const struct ilk_pipe_wm_parameters *p, |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1620 | struct intel_wm_level *result) |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 1621 | { |
| 1622 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
| 1623 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
| 1624 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
| 1625 | |
| 1626 | /* WM1+ latency values stored in 0.5us units */ |
| 1627 | if (level > 0) { |
| 1628 | pri_latency *= 5; |
| 1629 | spr_latency *= 5; |
| 1630 | cur_latency *= 5; |
| 1631 | } |
| 1632 | |
| 1633 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); |
| 1634 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); |
| 1635 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); |
| 1636 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); |
| 1637 | result->enable = true; |
| 1638 | } |
| 1639 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1640 | static uint32_t |
| 1641 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1642 | { |
| 1643 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 1644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1645 | struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 1646 | u32 linetime, ips_linetime; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1647 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1648 | if (!intel_crtc_active(crtc)) |
| 1649 | return 0; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 1650 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1651 | /* The WM are computed with base on how long it takes to fill a single |
| 1652 | * row at the given clock rate, multiplied by 8. |
| 1653 | * */ |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1654 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
| 1655 | mode->crtc_clock); |
| 1656 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 1657 | intel_ddi_get_cdclk_freq(dev_priv)); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1658 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1659 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
| 1660 | PIPE_WM_LINETIME_TIME(linetime); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 1661 | } |
| 1662 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1663 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 1664 | { |
| 1665 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1666 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1667 | if (IS_GEN9(dev)) { |
| 1668 | uint32_t val; |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 1669 | int ret, i; |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 1670 | int level, max_level = ilk_wm_max_level(dev); |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1671 | |
| 1672 | /* read the first set of memory latencies[0:3] */ |
| 1673 | val = 0; /* data0 to be programmed to 0 for first set */ |
| 1674 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1675 | ret = sandybridge_pcode_read(dev_priv, |
| 1676 | GEN9_PCODE_READ_MEM_LATENCY, |
| 1677 | &val); |
| 1678 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1679 | |
| 1680 | if (ret) { |
| 1681 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
| 1682 | return; |
| 1683 | } |
| 1684 | |
| 1685 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1686 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
| 1687 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1688 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
| 1689 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1690 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
| 1691 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1692 | |
| 1693 | /* read the second set of memory latencies[4:7] */ |
| 1694 | val = 1; /* data0 to be programmed to 1 for second set */ |
| 1695 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1696 | ret = sandybridge_pcode_read(dev_priv, |
| 1697 | GEN9_PCODE_READ_MEM_LATENCY, |
| 1698 | &val); |
| 1699 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1700 | if (ret) { |
| 1701 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
| 1702 | return; |
| 1703 | } |
| 1704 | |
| 1705 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1706 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
| 1707 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1708 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
| 1709 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1710 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
| 1711 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 1712 | |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 1713 | /* |
| 1714 | * punit doesn't take into account the read latency so we need |
| 1715 | * to add 2us to the various latency levels we retrieve from |
| 1716 | * the punit. |
| 1717 | * - W0 is a bit special in that it's the only level that |
| 1718 | * can't be disabled if we want to have display working, so |
| 1719 | * we always add 2us there. |
| 1720 | * - For levels >=1, punit returns 0us latency when they are |
| 1721 | * disabled, so we respect that and don't add 2us then |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 1722 | * |
| 1723 | * Additionally, if a level n (n > 1) has a 0us latency, all |
| 1724 | * levels m (m >= n) need to be disabled. We make sure to |
| 1725 | * sanitize the values out of the punit to satisfy this |
| 1726 | * requirement. |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 1727 | */ |
| 1728 | wm[0] += 2; |
| 1729 | for (level = 1; level <= max_level; level++) |
| 1730 | if (wm[level] != 0) |
| 1731 | wm[level] += 2; |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 1732 | else { |
| 1733 | for (i = level + 1; i <= max_level; i++) |
| 1734 | wm[i] = 0; |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 1735 | |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 1736 | break; |
| 1737 | } |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1738 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 1739 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
| 1740 | |
| 1741 | wm[0] = (sskpd >> 56) & 0xFF; |
| 1742 | if (wm[0] == 0) |
| 1743 | wm[0] = sskpd & 0xF; |
Ville Syrjälä | e5d5019 | 2013-07-05 11:57:22 +0300 | [diff] [blame] | 1744 | wm[1] = (sskpd >> 4) & 0xFF; |
| 1745 | wm[2] = (sskpd >> 12) & 0xFF; |
| 1746 | wm[3] = (sskpd >> 20) & 0x1FF; |
| 1747 | wm[4] = (sskpd >> 32) & 0x1FF; |
Ville Syrjälä | 63cf9a1 | 2013-07-05 11:57:23 +0300 | [diff] [blame] | 1748 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 1749 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
| 1750 | |
| 1751 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
| 1752 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
| 1753 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
| 1754 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
Ville Syrjälä | 3a88d0a | 2013-08-01 16:18:49 +0300 | [diff] [blame] | 1755 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 1756 | uint32_t mltr = I915_READ(MLTR_ILK); |
| 1757 | |
| 1758 | /* ILK primary LP0 latency is 700 ns */ |
| 1759 | wm[0] = 7; |
| 1760 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
| 1761 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 1762 | } |
| 1763 | } |
| 1764 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1765 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 1766 | { |
| 1767 | /* ILK sprite LP0 latency is 1300 ns */ |
| 1768 | if (INTEL_INFO(dev)->gen == 5) |
| 1769 | wm[0] = 13; |
| 1770 | } |
| 1771 | |
| 1772 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 1773 | { |
| 1774 | /* ILK cursor LP0 latency is 1300 ns */ |
| 1775 | if (INTEL_INFO(dev)->gen == 5) |
| 1776 | wm[0] = 13; |
| 1777 | |
| 1778 | /* WaDoubleCursorLP3Latency:ivb */ |
| 1779 | if (IS_IVYBRIDGE(dev)) |
| 1780 | wm[3] *= 2; |
| 1781 | } |
| 1782 | |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 1783 | int ilk_wm_max_level(const struct drm_device *dev) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 1784 | { |
| 1785 | /* how many WM levels are we expecting */ |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1786 | if (IS_GEN9(dev)) |
| 1787 | return 7; |
| 1788 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 1789 | return 4; |
| 1790 | else if (INTEL_INFO(dev)->gen >= 6) |
| 1791 | return 3; |
| 1792 | else |
| 1793 | return 2; |
| 1794 | } |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 1795 | |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 1796 | static void intel_print_wm_latency(struct drm_device *dev, |
| 1797 | const char *name, |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1798 | const uint16_t wm[8]) |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 1799 | { |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 1800 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 1801 | |
| 1802 | for (level = 0; level <= max_level; level++) { |
| 1803 | unsigned int latency = wm[level]; |
| 1804 | |
| 1805 | if (latency == 0) { |
| 1806 | DRM_ERROR("%s WM%d latency not provided\n", |
| 1807 | name, level); |
| 1808 | continue; |
| 1809 | } |
| 1810 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1811 | /* |
| 1812 | * - latencies are in us on gen9. |
| 1813 | * - before then, WM1+ latency values are in 0.5us units |
| 1814 | */ |
| 1815 | if (IS_GEN9(dev)) |
| 1816 | latency *= 10; |
| 1817 | else if (level > 0) |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 1818 | latency *= 5; |
| 1819 | |
| 1820 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
| 1821 | name, level, wm[level], |
| 1822 | latency / 10, latency % 10); |
| 1823 | } |
| 1824 | } |
| 1825 | |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 1826 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
| 1827 | uint16_t wm[5], uint16_t min) |
| 1828 | { |
| 1829 | int level, max_level = ilk_wm_max_level(dev_priv->dev); |
| 1830 | |
| 1831 | if (wm[0] >= min) |
| 1832 | return false; |
| 1833 | |
| 1834 | wm[0] = max(wm[0], min); |
| 1835 | for (level = 1; level <= max_level; level++) |
| 1836 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); |
| 1837 | |
| 1838 | return true; |
| 1839 | } |
| 1840 | |
| 1841 | static void snb_wm_latency_quirk(struct drm_device *dev) |
| 1842 | { |
| 1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1844 | bool changed; |
| 1845 | |
| 1846 | /* |
| 1847 | * The BIOS provided WM memory latency values are often |
| 1848 | * inadequate for high resolution displays. Adjust them. |
| 1849 | */ |
| 1850 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | |
| 1851 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | |
| 1852 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); |
| 1853 | |
| 1854 | if (!changed) |
| 1855 | return; |
| 1856 | |
| 1857 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); |
| 1858 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 1859 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 1860 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
| 1861 | } |
| 1862 | |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 1863 | static void ilk_setup_wm_latency(struct drm_device *dev) |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1864 | { |
| 1865 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1866 | |
| 1867 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
| 1868 | |
| 1869 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
| 1870 | sizeof(dev_priv->wm.pri_latency)); |
| 1871 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
| 1872 | sizeof(dev_priv->wm.pri_latency)); |
| 1873 | |
| 1874 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
| 1875 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 1876 | |
| 1877 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 1878 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 1879 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 1880 | |
| 1881 | if (IS_GEN6(dev)) |
| 1882 | snb_wm_latency_quirk(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1883 | } |
| 1884 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 1885 | static void skl_setup_wm_latency(struct drm_device *dev) |
| 1886 | { |
| 1887 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1888 | |
| 1889 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); |
| 1890 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); |
| 1891 | } |
| 1892 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1893 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1894 | struct ilk_pipe_wm_parameters *p) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1895 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 1896 | struct drm_device *dev = crtc->dev; |
| 1897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1898 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 1899 | struct drm_plane *plane; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1900 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1901 | if (!intel_crtc_active(crtc)) |
| 1902 | return; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1903 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1904 | p->active = true; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1905 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1906 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
| 1907 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; |
| 1908 | p->cur.bytes_per_pixel = 4; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1909 | p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1910 | p->cur.horiz_pixels = intel_crtc->cursor_width; |
| 1911 | /* TODO: for now, assume primary and cursor planes are always enabled. */ |
| 1912 | p->pri.enabled = true; |
| 1913 | p->cur.enabled = true; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 1914 | |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 1915 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1916 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1917 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1918 | if (intel_plane->pipe == pipe) { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 1919 | p->spr = intel_plane->wm; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1920 | break; |
| 1921 | } |
| 1922 | } |
| 1923 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1924 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1925 | static void ilk_compute_wm_config(struct drm_device *dev, |
| 1926 | struct intel_wm_config *config) |
| 1927 | { |
| 1928 | struct intel_crtc *intel_crtc; |
| 1929 | |
| 1930 | /* Compute the currently _active_ config */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 1931 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1932 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
| 1933 | |
| 1934 | if (!wm->pipe_enabled) |
| 1935 | continue; |
| 1936 | |
| 1937 | config->sprites_enabled |= wm->sprites_enabled; |
| 1938 | config->sprites_scaled |= wm->sprites_scaled; |
| 1939 | config->num_pipes_active++; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1940 | } |
| 1941 | } |
| 1942 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1943 | /* Compute new watermarks for the pipe */ |
| 1944 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1945 | const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1946 | struct intel_pipe_wm *pipe_wm) |
| 1947 | { |
| 1948 | struct drm_device *dev = crtc->dev; |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1949 | const struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1950 | int level, max_level = ilk_wm_max_level(dev); |
| 1951 | /* LP0 watermark maximums depend on this pipe alone */ |
| 1952 | struct intel_wm_config config = { |
| 1953 | .num_pipes_active = 1, |
| 1954 | .sprites_enabled = params->spr.enabled, |
| 1955 | .sprites_scaled = params->spr.scaled, |
| 1956 | }; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1957 | struct ilk_wm_maximums max; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1958 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 1959 | pipe_wm->pipe_enabled = params->active; |
| 1960 | pipe_wm->sprites_enabled = params->spr.enabled; |
| 1961 | pipe_wm->sprites_scaled = params->spr.scaled; |
| 1962 | |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 1963 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
| 1964 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) |
| 1965 | max_level = 1; |
| 1966 | |
| 1967 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
| 1968 | if (params->spr.scaled) |
| 1969 | max_level = 0; |
| 1970 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1971 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1972 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 1973 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 1974 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1975 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1976 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
| 1977 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
| 1978 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 1979 | /* At least LP0 must be valid */ |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1980 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
| 1981 | return false; |
| 1982 | |
| 1983 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
| 1984 | |
| 1985 | for (level = 1; level <= max_level; level++) { |
| 1986 | struct intel_wm_level wm = {}; |
| 1987 | |
| 1988 | ilk_compute_wm_level(dev_priv, level, params, &wm); |
| 1989 | |
| 1990 | /* |
| 1991 | * Disable any watermark level that exceeds the |
| 1992 | * register maximums since such watermarks are |
| 1993 | * always invalid. |
| 1994 | */ |
| 1995 | if (!ilk_validate_wm_level(level, &max, &wm)) |
| 1996 | break; |
| 1997 | |
| 1998 | pipe_wm->wm[level] = wm; |
| 1999 | } |
| 2000 | |
| 2001 | return true; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2002 | } |
| 2003 | |
| 2004 | /* |
| 2005 | * Merge the watermarks from all active pipes for a specific level. |
| 2006 | */ |
| 2007 | static void ilk_merge_wm_level(struct drm_device *dev, |
| 2008 | int level, |
| 2009 | struct intel_wm_level *ret_wm) |
| 2010 | { |
| 2011 | const struct intel_crtc *intel_crtc; |
| 2012 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2013 | ret_wm->enable = true; |
| 2014 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2015 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | fe392ef | 2014-03-07 18:32:10 +0200 | [diff] [blame] | 2016 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 2017 | const struct intel_wm_level *wm = &active->wm[level]; |
| 2018 | |
| 2019 | if (!active->pipe_enabled) |
| 2020 | continue; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2021 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2022 | /* |
| 2023 | * The watermark values may have been used in the past, |
| 2024 | * so we must maintain them in the registers for some |
| 2025 | * time even if the level is now disabled. |
| 2026 | */ |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2027 | if (!wm->enable) |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2028 | ret_wm->enable = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2029 | |
| 2030 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
| 2031 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
| 2032 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
| 2033 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
| 2034 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2035 | } |
| 2036 | |
| 2037 | /* |
| 2038 | * Merge all low power watermarks for all active pipes. |
| 2039 | */ |
| 2040 | static void ilk_wm_merge(struct drm_device *dev, |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2041 | const struct intel_wm_config *config, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2042 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2043 | struct intel_pipe_wm *merged) |
| 2044 | { |
| 2045 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2046 | int last_enabled_level = max_level; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2047 | |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2048 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
| 2049 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
| 2050 | config->num_pipes_active > 1) |
| 2051 | return; |
| 2052 | |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2053 | /* ILK: FBC WM must be disabled always */ |
| 2054 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2055 | |
| 2056 | /* merge each WM1+ level */ |
| 2057 | for (level = 1; level <= max_level; level++) { |
| 2058 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2059 | |
| 2060 | ilk_merge_wm_level(dev, level, wm); |
| 2061 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2062 | if (level > last_enabled_level) |
| 2063 | wm->enable = false; |
| 2064 | else if (!ilk_validate_wm_level(level, max, wm)) |
| 2065 | /* make sure all following levels get disabled */ |
| 2066 | last_enabled_level = level - 1; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2067 | |
| 2068 | /* |
| 2069 | * The spec says it is preferred to disable |
| 2070 | * FBC WMs instead of disabling a WM level. |
| 2071 | */ |
| 2072 | if (wm->fbc_val > max->fbc) { |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2073 | if (wm->enable) |
| 2074 | merged->fbc_wm_enabled = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2075 | wm->fbc_val = 0; |
| 2076 | } |
| 2077 | } |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2078 | |
| 2079 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
| 2080 | /* |
| 2081 | * FIXME this is racy. FBC might get enabled later. |
| 2082 | * What we should check here is whether FBC can be |
| 2083 | * enabled sometime later. |
| 2084 | */ |
| 2085 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { |
| 2086 | for (level = 2; level <= max_level; level++) { |
| 2087 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2088 | |
| 2089 | wm->enable = false; |
| 2090 | } |
| 2091 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2092 | } |
| 2093 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2094 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
| 2095 | { |
| 2096 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
| 2097 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
| 2098 | } |
| 2099 | |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2100 | /* The value we need to program into the WM_LPx latency field */ |
| 2101 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
| 2102 | { |
| 2103 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2104 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2105 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2106 | return 2 * level; |
| 2107 | else |
| 2108 | return dev_priv->wm.pri_latency[level]; |
| 2109 | } |
| 2110 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2111 | static void ilk_compute_wm_results(struct drm_device *dev, |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2112 | const struct intel_pipe_wm *merged, |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2113 | enum intel_ddb_partitioning partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2114 | struct ilk_wm_values *results) |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2115 | { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2116 | struct intel_crtc *intel_crtc; |
| 2117 | int level, wm_lp; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2118 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2119 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2120 | results->partitioning = partitioning; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2121 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2122 | /* LP1+ register values */ |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2123 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2124 | const struct intel_wm_level *r; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2125 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2126 | level = ilk_wm_lp_to_level(wm_lp, merged); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2127 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2128 | r = &merged->wm[level]; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2129 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2130 | /* |
| 2131 | * Maintain the watermark values even if the level is |
| 2132 | * disabled. Doing otherwise could cause underruns. |
| 2133 | */ |
| 2134 | results->wm_lp[wm_lp - 1] = |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2135 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2136 | (r->pri_val << WM1_LP_SR_SHIFT) | |
| 2137 | r->cur_val; |
| 2138 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2139 | if (r->enable) |
| 2140 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
| 2141 | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2142 | if (INTEL_INFO(dev)->gen >= 8) |
| 2143 | results->wm_lp[wm_lp - 1] |= |
| 2144 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
| 2145 | else |
| 2146 | results->wm_lp[wm_lp - 1] |= |
| 2147 | r->fbc_val << WM1_LP_FBC_SHIFT; |
| 2148 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2149 | /* |
| 2150 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
| 2151 | * level is disabled. Doing otherwise could cause underruns. |
| 2152 | */ |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2153 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
| 2154 | WARN_ON(wm_lp != 1); |
| 2155 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
| 2156 | } else |
| 2157 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2158 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2159 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2160 | /* LP0 register values */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2161 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2162 | enum pipe pipe = intel_crtc->pipe; |
| 2163 | const struct intel_wm_level *r = |
| 2164 | &intel_crtc->wm.active.wm[0]; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2165 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2166 | if (WARN_ON(!r->enable)) |
| 2167 | continue; |
| 2168 | |
| 2169 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
| 2170 | |
| 2171 | results->wm_pipe[pipe] = |
| 2172 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
| 2173 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
| 2174 | r->cur_val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2175 | } |
| 2176 | } |
| 2177 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2178 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
| 2179 | * case both are at the same level. Prefer r1 in case they're the same. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2180 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2181 | struct intel_pipe_wm *r1, |
| 2182 | struct intel_pipe_wm *r2) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2183 | { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2184 | int level, max_level = ilk_wm_max_level(dev); |
| 2185 | int level1 = 0, level2 = 0; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2186 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2187 | for (level = 1; level <= max_level; level++) { |
| 2188 | if (r1->wm[level].enable) |
| 2189 | level1 = level; |
| 2190 | if (r2->wm[level].enable) |
| 2191 | level2 = level; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2192 | } |
| 2193 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2194 | if (level1 == level2) { |
| 2195 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2196 | return r2; |
| 2197 | else |
| 2198 | return r1; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2199 | } else if (level1 > level2) { |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2200 | return r1; |
| 2201 | } else { |
| 2202 | return r2; |
| 2203 | } |
| 2204 | } |
| 2205 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2206 | /* dirty bits used to track which watermarks need changes */ |
| 2207 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
| 2208 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
| 2209 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
| 2210 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
| 2211 | #define WM_DIRTY_FBC (1 << 24) |
| 2212 | #define WM_DIRTY_DDB (1 << 25) |
| 2213 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2214 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2215 | const struct ilk_wm_values *old, |
| 2216 | const struct ilk_wm_values *new) |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2217 | { |
| 2218 | unsigned int dirty = 0; |
| 2219 | enum pipe pipe; |
| 2220 | int wm_lp; |
| 2221 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2222 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2223 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
| 2224 | dirty |= WM_DIRTY_LINETIME(pipe); |
| 2225 | /* Must disable LP1+ watermarks too */ |
| 2226 | dirty |= WM_DIRTY_LP_ALL; |
| 2227 | } |
| 2228 | |
| 2229 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
| 2230 | dirty |= WM_DIRTY_PIPE(pipe); |
| 2231 | /* Must disable LP1+ watermarks too */ |
| 2232 | dirty |= WM_DIRTY_LP_ALL; |
| 2233 | } |
| 2234 | } |
| 2235 | |
| 2236 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
| 2237 | dirty |= WM_DIRTY_FBC; |
| 2238 | /* Must disable LP1+ watermarks too */ |
| 2239 | dirty |= WM_DIRTY_LP_ALL; |
| 2240 | } |
| 2241 | |
| 2242 | if (old->partitioning != new->partitioning) { |
| 2243 | dirty |= WM_DIRTY_DDB; |
| 2244 | /* Must disable LP1+ watermarks too */ |
| 2245 | dirty |= WM_DIRTY_LP_ALL; |
| 2246 | } |
| 2247 | |
| 2248 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
| 2249 | if (dirty & WM_DIRTY_LP_ALL) |
| 2250 | return dirty; |
| 2251 | |
| 2252 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
| 2253 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
| 2254 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
| 2255 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
| 2256 | break; |
| 2257 | } |
| 2258 | |
| 2259 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
| 2260 | for (; wm_lp <= 3; wm_lp++) |
| 2261 | dirty |= WM_DIRTY_LP(wm_lp); |
| 2262 | |
| 2263 | return dirty; |
| 2264 | } |
| 2265 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2266 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
| 2267 | unsigned int dirty) |
| 2268 | { |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2269 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2270 | bool changed = false; |
| 2271 | |
| 2272 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
| 2273 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
| 2274 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
| 2275 | changed = true; |
| 2276 | } |
| 2277 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
| 2278 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
| 2279 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
| 2280 | changed = true; |
| 2281 | } |
| 2282 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
| 2283 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
| 2284 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
| 2285 | changed = true; |
| 2286 | } |
| 2287 | |
| 2288 | /* |
| 2289 | * Don't touch WM1S_LP_EN here. |
| 2290 | * Doing so could cause underruns. |
| 2291 | */ |
| 2292 | |
| 2293 | return changed; |
| 2294 | } |
| 2295 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2296 | /* |
| 2297 | * The spec says we shouldn't write when we don't need, because every write |
| 2298 | * causes WMs to be re-evaluated, expending some power. |
| 2299 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2300 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
| 2301 | struct ilk_wm_values *results) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2302 | { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2303 | struct drm_device *dev = dev_priv->dev; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2304 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2305 | unsigned int dirty; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2306 | uint32_t val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2307 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2308 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2309 | if (!dirty) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2310 | return; |
| 2311 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2312 | _ilk_disable_lp_wm(dev_priv, dirty); |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2313 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2314 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2315 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2316 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2317 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2318 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2319 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
| 2320 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2321 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2322 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2323 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2324 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2325 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2326 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
| 2327 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2328 | if (dirty & WM_DIRTY_DDB) { |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2329 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2330 | val = I915_READ(WM_MISC); |
| 2331 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2332 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
| 2333 | else |
| 2334 | val |= WM_MISC_DATA_PARTITION_5_6; |
| 2335 | I915_WRITE(WM_MISC, val); |
| 2336 | } else { |
| 2337 | val = I915_READ(DISP_ARB_CTL2); |
| 2338 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2339 | val &= ~DISP_DATA_PARTITION_5_6; |
| 2340 | else |
| 2341 | val |= DISP_DATA_PARTITION_5_6; |
| 2342 | I915_WRITE(DISP_ARB_CTL2, val); |
| 2343 | } |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2344 | } |
| 2345 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2346 | if (dirty & WM_DIRTY_FBC) { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2347 | val = I915_READ(DISP_ARB_CTL); |
| 2348 | if (results->enable_fbc_wm) |
| 2349 | val &= ~DISP_FBC_WM_DIS; |
| 2350 | else |
| 2351 | val |= DISP_FBC_WM_DIS; |
| 2352 | I915_WRITE(DISP_ARB_CTL, val); |
| 2353 | } |
| 2354 | |
Imre Deak | 954911e | 2013-12-17 14:46:34 +0200 | [diff] [blame] | 2355 | if (dirty & WM_DIRTY_LP(1) && |
| 2356 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
| 2357 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
| 2358 | |
| 2359 | if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2360 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
| 2361 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
| 2362 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
| 2363 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
| 2364 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2365 | |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2366 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2367 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2368 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2369 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2370 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2371 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2372 | |
| 2373 | dev_priv->wm.hw = *results; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2374 | } |
| 2375 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2376 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
| 2377 | { |
| 2378 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2379 | |
| 2380 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
| 2381 | } |
| 2382 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2383 | /* |
| 2384 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the |
| 2385 | * different active planes. |
| 2386 | */ |
| 2387 | |
| 2388 | #define SKL_DDB_SIZE 896 /* in blocks */ |
| 2389 | |
| 2390 | static void |
| 2391 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, |
| 2392 | struct drm_crtc *for_crtc, |
| 2393 | const struct intel_wm_config *config, |
| 2394 | const struct skl_pipe_wm_parameters *params, |
| 2395 | struct skl_ddb_entry *alloc /* out */) |
| 2396 | { |
| 2397 | struct drm_crtc *crtc; |
| 2398 | unsigned int pipe_size, ddb_size; |
| 2399 | int nth_active_pipe; |
| 2400 | |
| 2401 | if (!params->active) { |
| 2402 | alloc->start = 0; |
| 2403 | alloc->end = 0; |
| 2404 | return; |
| 2405 | } |
| 2406 | |
| 2407 | ddb_size = SKL_DDB_SIZE; |
| 2408 | |
| 2409 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ |
| 2410 | |
| 2411 | nth_active_pipe = 0; |
| 2412 | for_each_crtc(dev, crtc) { |
| 2413 | if (!intel_crtc_active(crtc)) |
| 2414 | continue; |
| 2415 | |
| 2416 | if (crtc == for_crtc) |
| 2417 | break; |
| 2418 | |
| 2419 | nth_active_pipe++; |
| 2420 | } |
| 2421 | |
| 2422 | pipe_size = ddb_size / config->num_pipes_active; |
| 2423 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2424 | alloc->end = alloc->start + pipe_size; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2425 | } |
| 2426 | |
| 2427 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) |
| 2428 | { |
| 2429 | if (config->num_pipes_active == 1) |
| 2430 | return 32; |
| 2431 | |
| 2432 | return 8; |
| 2433 | } |
| 2434 | |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2435 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
| 2436 | { |
| 2437 | entry->start = reg & 0x3ff; |
| 2438 | entry->end = (reg >> 16) & 0x3ff; |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2439 | if (entry->end) |
| 2440 | entry->end += 1; |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2441 | } |
| 2442 | |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 2443 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
| 2444 | struct skl_ddb_allocation *ddb /* out */) |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2445 | { |
| 2446 | struct drm_device *dev = dev_priv->dev; |
| 2447 | enum pipe pipe; |
| 2448 | int plane; |
| 2449 | u32 val; |
| 2450 | |
| 2451 | for_each_pipe(dev_priv, pipe) { |
| 2452 | for_each_plane(pipe, plane) { |
| 2453 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
| 2454 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], |
| 2455 | val); |
| 2456 | } |
| 2457 | |
| 2458 | val = I915_READ(CUR_BUF_CFG(pipe)); |
| 2459 | skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); |
| 2460 | } |
| 2461 | } |
| 2462 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2463 | static unsigned int |
| 2464 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) |
| 2465 | { |
| 2466 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; |
| 2467 | } |
| 2468 | |
| 2469 | /* |
| 2470 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching |
| 2471 | * a 8192x4096@32bpp framebuffer: |
| 2472 | * 3 * 4096 * 8192 * 4 < 2^32 |
| 2473 | */ |
| 2474 | static unsigned int |
| 2475 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, |
| 2476 | const struct skl_pipe_wm_parameters *params) |
| 2477 | { |
| 2478 | unsigned int total_data_rate = 0; |
| 2479 | int plane; |
| 2480 | |
| 2481 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
| 2482 | const struct intel_plane_wm_parameters *p; |
| 2483 | |
| 2484 | p = ¶ms->plane[plane]; |
| 2485 | if (!p->enabled) |
| 2486 | continue; |
| 2487 | |
| 2488 | total_data_rate += skl_plane_relative_data_rate(p); |
| 2489 | } |
| 2490 | |
| 2491 | return total_data_rate; |
| 2492 | } |
| 2493 | |
| 2494 | static void |
| 2495 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, |
| 2496 | const struct intel_wm_config *config, |
| 2497 | const struct skl_pipe_wm_parameters *params, |
| 2498 | struct skl_ddb_allocation *ddb /* out */) |
| 2499 | { |
| 2500 | struct drm_device *dev = crtc->dev; |
| 2501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2502 | enum pipe pipe = intel_crtc->pipe; |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2503 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2504 | uint16_t alloc_size, start, cursor_blocks; |
| 2505 | unsigned int total_data_rate; |
| 2506 | int plane; |
| 2507 | |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2508 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
| 2509 | alloc_size = skl_ddb_entry_size(alloc); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2510 | if (alloc_size == 0) { |
| 2511 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); |
| 2512 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); |
| 2513 | return; |
| 2514 | } |
| 2515 | |
| 2516 | cursor_blocks = skl_cursor_allocation(config); |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2517 | ddb->cursor[pipe].start = alloc->end - cursor_blocks; |
| 2518 | ddb->cursor[pipe].end = alloc->end; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2519 | |
| 2520 | alloc_size -= cursor_blocks; |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2521 | alloc->end -= cursor_blocks; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2522 | |
| 2523 | /* |
| 2524 | * Each active plane get a portion of the remaining space, in |
| 2525 | * proportion to the amount of data they need to fetch from memory. |
| 2526 | * |
| 2527 | * FIXME: we may not allocate every single block here. |
| 2528 | */ |
| 2529 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); |
| 2530 | |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2531 | start = alloc->start; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2532 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
| 2533 | const struct intel_plane_wm_parameters *p; |
| 2534 | unsigned int data_rate; |
| 2535 | uint16_t plane_blocks; |
| 2536 | |
| 2537 | p = ¶ms->plane[plane]; |
| 2538 | if (!p->enabled) |
| 2539 | continue; |
| 2540 | |
| 2541 | data_rate = skl_plane_relative_data_rate(p); |
| 2542 | |
| 2543 | /* |
| 2544 | * promote the expression to 64 bits to avoid overflowing, the |
| 2545 | * result is < available as data_rate / total_data_rate < 1 |
| 2546 | */ |
| 2547 | plane_blocks = div_u64((uint64_t)alloc_size * data_rate, |
| 2548 | total_data_rate); |
| 2549 | |
| 2550 | ddb->plane[pipe][plane].start = start; |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2551 | ddb->plane[pipe][plane].end = start + plane_blocks; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2552 | |
| 2553 | start += plane_blocks; |
| 2554 | } |
| 2555 | |
| 2556 | } |
| 2557 | |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2558 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2559 | { |
| 2560 | /* TODO: Take into account the scalers once we support them */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2561 | return config->base.adjusted_mode.crtc_clock; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2562 | } |
| 2563 | |
| 2564 | /* |
| 2565 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
| 2566 | * for the read latency) and bytes_per_pixel should always be <= 8, so that |
| 2567 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
| 2568 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
| 2569 | */ |
| 2570 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
| 2571 | uint32_t latency) |
| 2572 | { |
| 2573 | uint32_t wm_intermediate_val, ret; |
| 2574 | |
| 2575 | if (latency == 0) |
| 2576 | return UINT_MAX; |
| 2577 | |
| 2578 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel; |
| 2579 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
| 2580 | |
| 2581 | return ret; |
| 2582 | } |
| 2583 | |
| 2584 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
| 2585 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 2586 | uint32_t latency) |
| 2587 | { |
| 2588 | uint32_t ret, plane_bytes_per_line, wm_intermediate_val; |
| 2589 | |
| 2590 | if (latency == 0) |
| 2591 | return UINT_MAX; |
| 2592 | |
| 2593 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; |
| 2594 | wm_intermediate_val = latency * pixel_rate; |
| 2595 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * |
| 2596 | plane_bytes_per_line; |
| 2597 | |
| 2598 | return ret; |
| 2599 | } |
| 2600 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2601 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
| 2602 | const struct intel_crtc *intel_crtc) |
| 2603 | { |
| 2604 | struct drm_device *dev = intel_crtc->base.dev; |
| 2605 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2606 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; |
| 2607 | enum pipe pipe = intel_crtc->pipe; |
| 2608 | |
| 2609 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], |
| 2610 | sizeof(new_ddb->plane[pipe]))) |
| 2611 | return true; |
| 2612 | |
| 2613 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], |
| 2614 | sizeof(new_ddb->cursor[pipe]))) |
| 2615 | return true; |
| 2616 | |
| 2617 | return false; |
| 2618 | } |
| 2619 | |
| 2620 | static void skl_compute_wm_global_parameters(struct drm_device *dev, |
| 2621 | struct intel_wm_config *config) |
| 2622 | { |
| 2623 | struct drm_crtc *crtc; |
| 2624 | struct drm_plane *plane; |
| 2625 | |
| 2626 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 2627 | config->num_pipes_active += intel_crtc_active(crtc); |
| 2628 | |
| 2629 | /* FIXME: I don't think we need those two global parameters on SKL */ |
| 2630 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 2631 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 2632 | |
| 2633 | config->sprites_enabled |= intel_plane->wm.enabled; |
| 2634 | config->sprites_scaled |= intel_plane->wm.scaled; |
| 2635 | } |
| 2636 | } |
| 2637 | |
| 2638 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, |
| 2639 | struct skl_pipe_wm_parameters *p) |
| 2640 | { |
| 2641 | struct drm_device *dev = crtc->dev; |
| 2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2643 | enum pipe pipe = intel_crtc->pipe; |
| 2644 | struct drm_plane *plane; |
| 2645 | int i = 1; /* Index for sprite planes start */ |
| 2646 | |
| 2647 | p->active = intel_crtc_active(crtc); |
| 2648 | if (p->active) { |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2649 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
| 2650 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2651 | |
| 2652 | /* |
| 2653 | * For now, assume primary and cursor planes are always enabled. |
| 2654 | */ |
| 2655 | p->plane[0].enabled = true; |
| 2656 | p->plane[0].bytes_per_pixel = |
| 2657 | crtc->primary->fb->bits_per_pixel / 8; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2658 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; |
| 2659 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2660 | |
| 2661 | p->cursor.enabled = true; |
| 2662 | p->cursor.bytes_per_pixel = 4; |
| 2663 | p->cursor.horiz_pixels = intel_crtc->cursor_width ? |
| 2664 | intel_crtc->cursor_width : 64; |
| 2665 | } |
| 2666 | |
| 2667 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 2668 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 2669 | |
Sonika Jindal | a712f8e | 2014-12-09 10:59:15 +0530 | [diff] [blame] | 2670 | if (intel_plane->pipe == pipe && |
| 2671 | plane->type == DRM_PLANE_TYPE_OVERLAY) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2672 | p->plane[i++] = intel_plane->wm; |
| 2673 | } |
| 2674 | } |
| 2675 | |
| 2676 | static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p, |
Damien Lespiau | afb024a | 2014-11-04 17:06:59 +0000 | [diff] [blame] | 2677 | struct intel_plane_wm_parameters *p_params, |
| 2678 | uint16_t ddb_allocation, |
| 2679 | uint32_t mem_value, |
| 2680 | uint16_t *out_blocks, /* out */ |
| 2681 | uint8_t *out_lines /* out */) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2682 | { |
Damien Lespiau | e6d6617 | 2014-11-04 17:06:55 +0000 | [diff] [blame] | 2683 | uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2684 | uint32_t result_bytes; |
| 2685 | |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 2686 | if (mem_value == 0 || !p->active || !p_params->enabled) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2687 | return false; |
| 2688 | |
| 2689 | method1 = skl_wm_method1(p->pixel_rate, |
| 2690 | p_params->bytes_per_pixel, |
| 2691 | mem_value); |
| 2692 | method2 = skl_wm_method2(p->pixel_rate, |
| 2693 | p->pipe_htotal, |
| 2694 | p_params->horiz_pixels, |
| 2695 | p_params->bytes_per_pixel, |
| 2696 | mem_value); |
| 2697 | |
| 2698 | plane_bytes_per_line = p_params->horiz_pixels * |
| 2699 | p_params->bytes_per_pixel; |
| 2700 | |
| 2701 | /* For now xtile and linear */ |
Damien Lespiau | 21fca25 | 2014-11-04 17:06:54 +0000 | [diff] [blame] | 2702 | if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2703 | result_bytes = min(method1, method2); |
| 2704 | else |
| 2705 | result_bytes = method1; |
| 2706 | |
Damien Lespiau | e6d6617 | 2014-11-04 17:06:55 +0000 | [diff] [blame] | 2707 | res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1; |
| 2708 | res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line); |
| 2709 | |
| 2710 | if (res_blocks > ddb_allocation || res_lines > 31) |
| 2711 | return false; |
| 2712 | |
| 2713 | *out_blocks = res_blocks; |
| 2714 | *out_lines = res_lines; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2715 | |
| 2716 | return true; |
| 2717 | } |
| 2718 | |
| 2719 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, |
| 2720 | struct skl_ddb_allocation *ddb, |
| 2721 | struct skl_pipe_wm_parameters *p, |
| 2722 | enum pipe pipe, |
| 2723 | int level, |
| 2724 | int num_planes, |
| 2725 | struct skl_wm_level *result) |
| 2726 | { |
| 2727 | uint16_t latency = dev_priv->wm.skl_latency[level]; |
| 2728 | uint16_t ddb_blocks; |
| 2729 | int i; |
| 2730 | |
| 2731 | for (i = 0; i < num_planes; i++) { |
| 2732 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
| 2733 | |
| 2734 | result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i], |
| 2735 | ddb_blocks, |
| 2736 | latency, |
| 2737 | &result->plane_res_b[i], |
| 2738 | &result->plane_res_l[i]); |
| 2739 | } |
| 2740 | |
| 2741 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); |
| 2742 | result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks, |
| 2743 | latency, &result->cursor_res_b, |
| 2744 | &result->cursor_res_l); |
| 2745 | } |
| 2746 | |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 2747 | static uint32_t |
| 2748 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) |
| 2749 | { |
| 2750 | if (!intel_crtc_active(crtc)) |
| 2751 | return 0; |
| 2752 | |
| 2753 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); |
| 2754 | |
| 2755 | } |
| 2756 | |
| 2757 | static void skl_compute_transition_wm(struct drm_crtc *crtc, |
| 2758 | struct skl_pipe_wm_parameters *params, |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2759 | struct skl_wm_level *trans_wm /* out */) |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 2760 | { |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2762 | int i; |
| 2763 | |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 2764 | if (!params->active) |
| 2765 | return; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2766 | |
| 2767 | /* Until we know more, just disable transition WMs */ |
| 2768 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
| 2769 | trans_wm->plane_en[i] = false; |
| 2770 | trans_wm->cursor_en = false; |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 2771 | } |
| 2772 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2773 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
| 2774 | struct skl_ddb_allocation *ddb, |
| 2775 | struct skl_pipe_wm_parameters *params, |
| 2776 | struct skl_pipe_wm *pipe_wm) |
| 2777 | { |
| 2778 | struct drm_device *dev = crtc->dev; |
| 2779 | const struct drm_i915_private *dev_priv = dev->dev_private; |
| 2780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2781 | int level, max_level = ilk_wm_max_level(dev); |
| 2782 | |
| 2783 | for (level = 0; level <= max_level; level++) { |
| 2784 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, |
| 2785 | level, intel_num_planes(intel_crtc), |
| 2786 | &pipe_wm->wm[level]); |
| 2787 | } |
| 2788 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); |
| 2789 | |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2790 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2791 | } |
| 2792 | |
| 2793 | static void skl_compute_wm_results(struct drm_device *dev, |
| 2794 | struct skl_pipe_wm_parameters *p, |
| 2795 | struct skl_pipe_wm *p_wm, |
| 2796 | struct skl_wm_values *r, |
| 2797 | struct intel_crtc *intel_crtc) |
| 2798 | { |
| 2799 | int level, max_level = ilk_wm_max_level(dev); |
| 2800 | enum pipe pipe = intel_crtc->pipe; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2801 | uint32_t temp; |
| 2802 | int i; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2803 | |
| 2804 | for (level = 0; level <= max_level; level++) { |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2805 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 2806 | temp = 0; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2807 | |
| 2808 | temp |= p_wm->wm[level].plane_res_l[i] << |
| 2809 | PLANE_WM_LINES_SHIFT; |
| 2810 | temp |= p_wm->wm[level].plane_res_b[i]; |
| 2811 | if (p_wm->wm[level].plane_en[i]) |
| 2812 | temp |= PLANE_WM_EN; |
| 2813 | |
| 2814 | r->plane[pipe][i][level] = temp; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2815 | } |
| 2816 | |
| 2817 | temp = 0; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2818 | |
| 2819 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; |
| 2820 | temp |= p_wm->wm[level].cursor_res_b; |
| 2821 | |
| 2822 | if (p_wm->wm[level].cursor_en) |
| 2823 | temp |= PLANE_WM_EN; |
| 2824 | |
| 2825 | r->cursor[pipe][level] = temp; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2826 | |
| 2827 | } |
| 2828 | |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 2829 | /* transition WMs */ |
| 2830 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 2831 | temp = 0; |
| 2832 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; |
| 2833 | temp |= p_wm->trans_wm.plane_res_b[i]; |
| 2834 | if (p_wm->trans_wm.plane_en[i]) |
| 2835 | temp |= PLANE_WM_EN; |
| 2836 | |
| 2837 | r->plane_trans[pipe][i] = temp; |
| 2838 | } |
| 2839 | |
| 2840 | temp = 0; |
| 2841 | temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; |
| 2842 | temp |= p_wm->trans_wm.cursor_res_b; |
| 2843 | if (p_wm->trans_wm.cursor_en) |
| 2844 | temp |= PLANE_WM_EN; |
| 2845 | |
| 2846 | r->cursor_trans[pipe] = temp; |
| 2847 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2848 | r->wm_linetime[pipe] = p_wm->linetime; |
| 2849 | } |
| 2850 | |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2851 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
| 2852 | const struct skl_ddb_entry *entry) |
| 2853 | { |
| 2854 | if (entry->end) |
| 2855 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); |
| 2856 | else |
| 2857 | I915_WRITE(reg, 0); |
| 2858 | } |
| 2859 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2860 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
| 2861 | const struct skl_wm_values *new) |
| 2862 | { |
| 2863 | struct drm_device *dev = dev_priv->dev; |
| 2864 | struct intel_crtc *crtc; |
| 2865 | |
| 2866 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 2867 | int i, level, max_level = ilk_wm_max_level(dev); |
| 2868 | enum pipe pipe = crtc->pipe; |
| 2869 | |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 2870 | if (!new->dirty[pipe]) |
| 2871 | continue; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2872 | |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 2873 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
| 2874 | |
| 2875 | for (level = 0; level <= max_level; level++) { |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2876 | for (i = 0; i < intel_num_planes(crtc); i++) |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 2877 | I915_WRITE(PLANE_WM(pipe, i, level), |
| 2878 | new->plane[pipe][i][level]); |
| 2879 | I915_WRITE(CUR_WM(pipe, level), |
| 2880 | new->cursor[pipe][level]); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2881 | } |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 2882 | for (i = 0; i < intel_num_planes(crtc); i++) |
| 2883 | I915_WRITE(PLANE_WM_TRANS(pipe, i), |
| 2884 | new->plane_trans[pipe][i]); |
| 2885 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); |
| 2886 | |
| 2887 | for (i = 0; i < intel_num_planes(crtc); i++) |
| 2888 | skl_ddb_entry_write(dev_priv, |
| 2889 | PLANE_BUF_CFG(pipe, i), |
| 2890 | &new->ddb.plane[pipe][i]); |
| 2891 | |
| 2892 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
| 2893 | &new->ddb.cursor[pipe]); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2894 | } |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 2895 | } |
| 2896 | |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 2897 | /* |
| 2898 | * When setting up a new DDB allocation arrangement, we need to correctly |
| 2899 | * sequence the times at which the new allocations for the pipes are taken into |
| 2900 | * account or we'll have pipes fetching from space previously allocated to |
| 2901 | * another pipe. |
| 2902 | * |
| 2903 | * Roughly the sequence looks like: |
| 2904 | * 1. re-allocate the pipe(s) with the allocation being reduced and not |
| 2905 | * overlapping with a previous light-up pipe (another way to put it is: |
| 2906 | * pipes with their new allocation strickly included into their old ones). |
| 2907 | * 2. re-allocate the other pipes that get their allocation reduced |
| 2908 | * 3. allocate the pipes having their allocation increased |
| 2909 | * |
| 2910 | * Steps 1. and 2. are here to take care of the following case: |
| 2911 | * - Initially DDB looks like this: |
| 2912 | * | B | C | |
| 2913 | * - enable pipe A. |
| 2914 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C |
| 2915 | * allocation |
| 2916 | * | A | B | C | |
| 2917 | * |
| 2918 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). |
| 2919 | */ |
| 2920 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 2921 | static void |
| 2922 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 2923 | { |
| 2924 | struct drm_device *dev = dev_priv->dev; |
| 2925 | int plane; |
| 2926 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 2927 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
| 2928 | |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 2929 | for_each_plane(pipe, plane) { |
| 2930 | I915_WRITE(PLANE_SURF(pipe, plane), |
| 2931 | I915_READ(PLANE_SURF(pipe, plane))); |
| 2932 | } |
| 2933 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
| 2934 | } |
| 2935 | |
| 2936 | static bool |
| 2937 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, |
| 2938 | const struct skl_ddb_allocation *new, |
| 2939 | enum pipe pipe) |
| 2940 | { |
| 2941 | uint16_t old_size, new_size; |
| 2942 | |
| 2943 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); |
| 2944 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); |
| 2945 | |
| 2946 | return old_size != new_size && |
| 2947 | new->pipe[pipe].start >= old->pipe[pipe].start && |
| 2948 | new->pipe[pipe].end <= old->pipe[pipe].end; |
| 2949 | } |
| 2950 | |
| 2951 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, |
| 2952 | struct skl_wm_values *new_values) |
| 2953 | { |
| 2954 | struct drm_device *dev = dev_priv->dev; |
| 2955 | struct skl_ddb_allocation *cur_ddb, *new_ddb; |
| 2956 | bool reallocated[I915_MAX_PIPES] = {false, false, false}; |
| 2957 | struct intel_crtc *crtc; |
| 2958 | enum pipe pipe; |
| 2959 | |
| 2960 | new_ddb = &new_values->ddb; |
| 2961 | cur_ddb = &dev_priv->wm.skl_hw.ddb; |
| 2962 | |
| 2963 | /* |
| 2964 | * First pass: flush the pipes with the new allocation contained into |
| 2965 | * the old space. |
| 2966 | * |
| 2967 | * We'll wait for the vblank on those pipes to ensure we can safely |
| 2968 | * re-allocate the freed space without this pipe fetching from it. |
| 2969 | */ |
| 2970 | for_each_intel_crtc(dev, crtc) { |
| 2971 | if (!crtc->active) |
| 2972 | continue; |
| 2973 | |
| 2974 | pipe = crtc->pipe; |
| 2975 | |
| 2976 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) |
| 2977 | continue; |
| 2978 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 2979 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 2980 | intel_wait_for_vblank(dev, pipe); |
| 2981 | |
| 2982 | reallocated[pipe] = true; |
| 2983 | } |
| 2984 | |
| 2985 | |
| 2986 | /* |
| 2987 | * Second pass: flush the pipes that are having their allocation |
| 2988 | * reduced, but overlapping with a previous allocation. |
| 2989 | * |
| 2990 | * Here as well we need to wait for the vblank to make sure the freed |
| 2991 | * space is not used anymore. |
| 2992 | */ |
| 2993 | for_each_intel_crtc(dev, crtc) { |
| 2994 | if (!crtc->active) |
| 2995 | continue; |
| 2996 | |
| 2997 | pipe = crtc->pipe; |
| 2998 | |
| 2999 | if (reallocated[pipe]) |
| 3000 | continue; |
| 3001 | |
| 3002 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < |
| 3003 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3004 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3005 | intel_wait_for_vblank(dev, pipe); |
Sonika Jindal | d9d8e6b | 2014-12-11 17:58:15 +0530 | [diff] [blame] | 3006 | reallocated[pipe] = true; |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3007 | } |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3008 | } |
| 3009 | |
| 3010 | /* |
| 3011 | * Third pass: flush the pipes that got more space allocated. |
| 3012 | * |
| 3013 | * We don't need to actively wait for the update here, next vblank |
| 3014 | * will just get more DDB space with the correct WM values. |
| 3015 | */ |
| 3016 | for_each_intel_crtc(dev, crtc) { |
| 3017 | if (!crtc->active) |
| 3018 | continue; |
| 3019 | |
| 3020 | pipe = crtc->pipe; |
| 3021 | |
| 3022 | /* |
| 3023 | * At this point, only the pipes more space than before are |
| 3024 | * left to re-allocate. |
| 3025 | */ |
| 3026 | if (reallocated[pipe]) |
| 3027 | continue; |
| 3028 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3029 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3030 | } |
| 3031 | } |
| 3032 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3033 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
| 3034 | struct skl_pipe_wm_parameters *params, |
| 3035 | struct intel_wm_config *config, |
| 3036 | struct skl_ddb_allocation *ddb, /* out */ |
| 3037 | struct skl_pipe_wm *pipe_wm /* out */) |
| 3038 | { |
| 3039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3040 | |
| 3041 | skl_compute_wm_pipe_parameters(crtc, params); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3042 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3043 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
| 3044 | |
| 3045 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) |
| 3046 | return false; |
| 3047 | |
| 3048 | intel_crtc->wm.skl_active = *pipe_wm; |
| 3049 | return true; |
| 3050 | } |
| 3051 | |
| 3052 | static void skl_update_other_pipe_wm(struct drm_device *dev, |
| 3053 | struct drm_crtc *crtc, |
| 3054 | struct intel_wm_config *config, |
| 3055 | struct skl_wm_values *r) |
| 3056 | { |
| 3057 | struct intel_crtc *intel_crtc; |
| 3058 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); |
| 3059 | |
| 3060 | /* |
| 3061 | * If the WM update hasn't changed the allocation for this_crtc (the |
| 3062 | * crtc we are currently computing the new WM values for), other |
| 3063 | * enabled crtcs will keep the same allocation and we don't need to |
| 3064 | * recompute anything for them. |
| 3065 | */ |
| 3066 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) |
| 3067 | return; |
| 3068 | |
| 3069 | /* |
| 3070 | * Otherwise, because of this_crtc being freshly enabled/disabled, the |
| 3071 | * other active pipes need new DDB allocation and WM values. |
| 3072 | */ |
| 3073 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 3074 | base.head) { |
| 3075 | struct skl_pipe_wm_parameters params = {}; |
| 3076 | struct skl_pipe_wm pipe_wm = {}; |
| 3077 | bool wm_changed; |
| 3078 | |
| 3079 | if (this_crtc->pipe == intel_crtc->pipe) |
| 3080 | continue; |
| 3081 | |
| 3082 | if (!intel_crtc->active) |
| 3083 | continue; |
| 3084 | |
| 3085 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, |
| 3086 | ¶ms, config, |
| 3087 | &r->ddb, &pipe_wm); |
| 3088 | |
| 3089 | /* |
| 3090 | * If we end up re-computing the other pipe WM values, it's |
| 3091 | * because it was really needed, so we expect the WM values to |
| 3092 | * be different. |
| 3093 | */ |
| 3094 | WARN_ON(!wm_changed); |
| 3095 | |
| 3096 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); |
| 3097 | r->dirty[intel_crtc->pipe] = true; |
| 3098 | } |
| 3099 | } |
| 3100 | |
| 3101 | static void skl_update_wm(struct drm_crtc *crtc) |
| 3102 | { |
| 3103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3104 | struct drm_device *dev = crtc->dev; |
| 3105 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3106 | struct skl_pipe_wm_parameters params = {}; |
| 3107 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
| 3108 | struct skl_pipe_wm pipe_wm = {}; |
| 3109 | struct intel_wm_config config = {}; |
| 3110 | |
| 3111 | memset(results, 0, sizeof(*results)); |
| 3112 | |
| 3113 | skl_compute_wm_global_parameters(dev, &config); |
| 3114 | |
| 3115 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, |
| 3116 | &results->ddb, &pipe_wm)) |
| 3117 | return; |
| 3118 | |
| 3119 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); |
| 3120 | results->dirty[intel_crtc->pipe] = true; |
| 3121 | |
| 3122 | skl_update_other_pipe_wm(dev, crtc, &config, results); |
| 3123 | skl_write_wm_values(dev_priv, results); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3124 | skl_flush_wm_values(dev_priv, results); |
Damien Lespiau | 53b0deb | 2014-11-04 17:06:48 +0000 | [diff] [blame] | 3125 | |
| 3126 | /* store the new configuration */ |
| 3127 | dev_priv->wm.skl_hw = *results; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3128 | } |
| 3129 | |
| 3130 | static void |
| 3131 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, |
| 3132 | uint32_t sprite_width, uint32_t sprite_height, |
| 3133 | int pixel_size, bool enabled, bool scaled) |
| 3134 | { |
| 3135 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 3136 | |
| 3137 | intel_plane->wm.enabled = enabled; |
| 3138 | intel_plane->wm.scaled = scaled; |
| 3139 | intel_plane->wm.horiz_pixels = sprite_width; |
| 3140 | intel_plane->wm.vert_pixels = sprite_height; |
| 3141 | intel_plane->wm.bytes_per_pixel = pixel_size; |
| 3142 | |
| 3143 | skl_update_wm(crtc); |
| 3144 | } |
| 3145 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3146 | static void ilk_update_wm(struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 3147 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 3148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3149 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 3150 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3151 | struct ilk_wm_maximums max; |
| 3152 | struct ilk_pipe_wm_parameters params = {}; |
| 3153 | struct ilk_wm_values results = {}; |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 3154 | enum intel_ddb_partitioning partitioning; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 3155 | struct intel_pipe_wm pipe_wm = {}; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 3156 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 3157 | struct intel_wm_config config = {}; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 3158 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 3159 | ilk_compute_wm_parameters(crtc, ¶ms); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3160 | |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 3161 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); |
| 3162 | |
| 3163 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) |
| 3164 | return; |
| 3165 | |
| 3166 | intel_crtc->wm.active = pipe_wm; |
| 3167 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 3168 | ilk_compute_wm_config(dev, &config); |
| 3169 | |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 3170 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 3171 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 3172 | |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 3173 | /* 5/6 split only in single pipe config on IVB+ */ |
Ville Syrjälä | ec98c8d | 2013-10-11 15:26:26 +0300 | [diff] [blame] | 3174 | if (INTEL_INFO(dev)->gen >= 7 && |
| 3175 | config.num_pipes_active == 1 && config.sprites_enabled) { |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 3176 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 3177 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 3178 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3179 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3180 | } else { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 3181 | best_lp_wm = &lp_wm_1_2; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3182 | } |
| 3183 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 3184 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 3185 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3186 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3187 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 3188 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3189 | ilk_write_wm_values(dev_priv, &results); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 3190 | } |
| 3191 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3192 | static void |
| 3193 | ilk_update_sprite_wm(struct drm_plane *plane, |
| 3194 | struct drm_crtc *crtc, |
| 3195 | uint32_t sprite_width, uint32_t sprite_height, |
| 3196 | int pixel_size, bool enabled, bool scaled) |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 3197 | { |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 3198 | struct drm_device *dev = plane->dev; |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3199 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 3200 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3201 | intel_plane->wm.enabled = enabled; |
| 3202 | intel_plane->wm.scaled = scaled; |
| 3203 | intel_plane->wm.horiz_pixels = sprite_width; |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3204 | intel_plane->wm.vert_pixels = sprite_width; |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3205 | intel_plane->wm.bytes_per_pixel = pixel_size; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 3206 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 3207 | /* |
| 3208 | * IVB workaround: must disable low power watermarks for at least |
| 3209 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 3210 | * when scaling is disabled. |
| 3211 | * |
| 3212 | * WaCxSRDisabledForSpriteScaling:ivb |
| 3213 | */ |
| 3214 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) |
| 3215 | intel_wait_for_vblank(dev, intel_plane->pipe); |
| 3216 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3217 | ilk_update_wm(crtc); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 3218 | } |
| 3219 | |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3220 | static void skl_pipe_wm_active_state(uint32_t val, |
| 3221 | struct skl_pipe_wm *active, |
| 3222 | bool is_transwm, |
| 3223 | bool is_cursor, |
| 3224 | int i, |
| 3225 | int level) |
| 3226 | { |
| 3227 | bool is_enabled = (val & PLANE_WM_EN) != 0; |
| 3228 | |
| 3229 | if (!is_transwm) { |
| 3230 | if (!is_cursor) { |
| 3231 | active->wm[level].plane_en[i] = is_enabled; |
| 3232 | active->wm[level].plane_res_b[i] = |
| 3233 | val & PLANE_WM_BLOCKS_MASK; |
| 3234 | active->wm[level].plane_res_l[i] = |
| 3235 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3236 | PLANE_WM_LINES_MASK; |
| 3237 | } else { |
| 3238 | active->wm[level].cursor_en = is_enabled; |
| 3239 | active->wm[level].cursor_res_b = |
| 3240 | val & PLANE_WM_BLOCKS_MASK; |
| 3241 | active->wm[level].cursor_res_l = |
| 3242 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3243 | PLANE_WM_LINES_MASK; |
| 3244 | } |
| 3245 | } else { |
| 3246 | if (!is_cursor) { |
| 3247 | active->trans_wm.plane_en[i] = is_enabled; |
| 3248 | active->trans_wm.plane_res_b[i] = |
| 3249 | val & PLANE_WM_BLOCKS_MASK; |
| 3250 | active->trans_wm.plane_res_l[i] = |
| 3251 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3252 | PLANE_WM_LINES_MASK; |
| 3253 | } else { |
| 3254 | active->trans_wm.cursor_en = is_enabled; |
| 3255 | active->trans_wm.cursor_res_b = |
| 3256 | val & PLANE_WM_BLOCKS_MASK; |
| 3257 | active->trans_wm.cursor_res_l = |
| 3258 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3259 | PLANE_WM_LINES_MASK; |
| 3260 | } |
| 3261 | } |
| 3262 | } |
| 3263 | |
| 3264 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 3265 | { |
| 3266 | struct drm_device *dev = crtc->dev; |
| 3267 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3268 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
| 3269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3270 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; |
| 3271 | enum pipe pipe = intel_crtc->pipe; |
| 3272 | int level, i, max_level; |
| 3273 | uint32_t temp; |
| 3274 | |
| 3275 | max_level = ilk_wm_max_level(dev); |
| 3276 | |
| 3277 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
| 3278 | |
| 3279 | for (level = 0; level <= max_level; level++) { |
| 3280 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
| 3281 | hw->plane[pipe][i][level] = |
| 3282 | I915_READ(PLANE_WM(pipe, i, level)); |
| 3283 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); |
| 3284 | } |
| 3285 | |
| 3286 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
| 3287 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); |
| 3288 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); |
| 3289 | |
| 3290 | if (!intel_crtc_active(crtc)) |
| 3291 | return; |
| 3292 | |
| 3293 | hw->dirty[pipe] = true; |
| 3294 | |
| 3295 | active->linetime = hw->wm_linetime[pipe]; |
| 3296 | |
| 3297 | for (level = 0; level <= max_level; level++) { |
| 3298 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3299 | temp = hw->plane[pipe][i][level]; |
| 3300 | skl_pipe_wm_active_state(temp, active, false, |
| 3301 | false, i, level); |
| 3302 | } |
| 3303 | temp = hw->cursor[pipe][level]; |
| 3304 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
| 3305 | } |
| 3306 | |
| 3307 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3308 | temp = hw->plane_trans[pipe][i]; |
| 3309 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); |
| 3310 | } |
| 3311 | |
| 3312 | temp = hw->cursor_trans[pipe]; |
| 3313 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
| 3314 | } |
| 3315 | |
| 3316 | void skl_wm_get_hw_state(struct drm_device *dev) |
| 3317 | { |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 3318 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3319 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3320 | struct drm_crtc *crtc; |
| 3321 | |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 3322 | skl_ddb_get_hw_state(dev_priv, ddb); |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3323 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 3324 | skl_pipe_wm_get_hw_state(crtc); |
| 3325 | } |
| 3326 | |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3327 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 3328 | { |
| 3329 | struct drm_device *dev = crtc->dev; |
| 3330 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3331 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3333 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 3334 | enum pipe pipe = intel_crtc->pipe; |
| 3335 | static const unsigned int wm0_pipe_reg[] = { |
| 3336 | [PIPE_A] = WM0_PIPEA_ILK, |
| 3337 | [PIPE_B] = WM0_PIPEB_ILK, |
| 3338 | [PIPE_C] = WM0_PIPEC_IVB, |
| 3339 | }; |
| 3340 | |
| 3341 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 3342 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 3343 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3344 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 3345 | active->pipe_enabled = intel_crtc_active(crtc); |
| 3346 | |
| 3347 | if (active->pipe_enabled) { |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3348 | u32 tmp = hw->wm_pipe[pipe]; |
| 3349 | |
| 3350 | /* |
| 3351 | * For active pipes LP0 watermark is marked as |
| 3352 | * enabled, and LP1+ watermaks as disabled since |
| 3353 | * we can't really reverse compute them in case |
| 3354 | * multiple pipes are active. |
| 3355 | */ |
| 3356 | active->wm[0].enable = true; |
| 3357 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
| 3358 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
| 3359 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
| 3360 | active->linetime = hw->wm_linetime[pipe]; |
| 3361 | } else { |
| 3362 | int level, max_level = ilk_wm_max_level(dev); |
| 3363 | |
| 3364 | /* |
| 3365 | * For inactive pipes, all watermark levels |
| 3366 | * should be marked as enabled but zeroed, |
| 3367 | * which is what we'd compute them to. |
| 3368 | */ |
| 3369 | for (level = 0; level <= max_level; level++) |
| 3370 | active->wm[level].enable = true; |
| 3371 | } |
| 3372 | } |
| 3373 | |
| 3374 | void ilk_wm_get_hw_state(struct drm_device *dev) |
| 3375 | { |
| 3376 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3377 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3378 | struct drm_crtc *crtc; |
| 3379 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 3380 | for_each_crtc(dev, crtc) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3381 | ilk_pipe_wm_get_hw_state(crtc); |
| 3382 | |
| 3383 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
| 3384 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
| 3385 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
| 3386 | |
| 3387 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
Ville Syrjälä | cfa7698 | 2014-03-07 18:32:08 +0200 | [diff] [blame] | 3388 | if (INTEL_INFO(dev)->gen >= 7) { |
| 3389 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
| 3390 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
| 3391 | } |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3392 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 3393 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 3394 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
| 3395 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
| 3396 | else if (IS_IVYBRIDGE(dev)) |
| 3397 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
| 3398 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3399 | |
| 3400 | hw->enable_fbc_wm = |
| 3401 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
| 3402 | } |
| 3403 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3404 | /** |
| 3405 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 3406 | * |
| 3407 | * Calculate watermark values for the various WM regs based on current mode |
| 3408 | * and plane configuration. |
| 3409 | * |
| 3410 | * There are several cases to deal with here: |
| 3411 | * - normal (i.e. non-self-refresh) |
| 3412 | * - self-refresh (SR) mode |
| 3413 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 3414 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 3415 | * lines), so need to account for TLB latency |
| 3416 | * |
| 3417 | * The normal calculation is: |
| 3418 | * watermark = dotclock * bytes per pixel * latency |
| 3419 | * where latency is platform & configuration dependent (we assume pessimal |
| 3420 | * values here). |
| 3421 | * |
| 3422 | * The SR calculation is: |
| 3423 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 3424 | * bytes per pixel |
| 3425 | * where |
| 3426 | * line time = htotal / dotclock |
| 3427 | * surface width = hdisplay for normal plane and 64 for cursor |
| 3428 | * and latency is assumed to be high, as above. |
| 3429 | * |
| 3430 | * The final value programmed to the register should always be rounded up, |
| 3431 | * and include an extra 2 entries to account for clock crossings. |
| 3432 | * |
| 3433 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 3434 | * to set the non-SR watermarks to 8. |
| 3435 | */ |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3436 | void intel_update_watermarks(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3437 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3438 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3439 | |
| 3440 | if (dev_priv->display.update_wm) |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3441 | dev_priv->display.update_wm(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3442 | } |
| 3443 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3444 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 3445 | struct drm_crtc *crtc, |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3446 | uint32_t sprite_width, |
| 3447 | uint32_t sprite_height, |
| 3448 | int pixel_size, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 3449 | bool enabled, bool scaled) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3450 | { |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3451 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3452 | |
| 3453 | if (dev_priv->display.update_sprite_wm) |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3454 | dev_priv->display.update_sprite_wm(plane, crtc, |
| 3455 | sprite_width, sprite_height, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 3456 | pixel_size, enabled, scaled); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3457 | } |
| 3458 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3459 | static struct drm_i915_gem_object * |
| 3460 | intel_alloc_context_page(struct drm_device *dev) |
| 3461 | { |
| 3462 | struct drm_i915_gem_object *ctx; |
| 3463 | int ret; |
| 3464 | |
| 3465 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 3466 | |
| 3467 | ctx = i915_gem_alloc_object(dev, 4096); |
| 3468 | if (!ctx) { |
| 3469 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 3470 | return NULL; |
| 3471 | } |
| 3472 | |
Daniel Vetter | c69766f | 2014-02-14 14:01:17 +0100 | [diff] [blame] | 3473 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3474 | if (ret) { |
| 3475 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 3476 | goto err_unref; |
| 3477 | } |
| 3478 | |
| 3479 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
| 3480 | if (ret) { |
| 3481 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 3482 | goto err_unpin; |
| 3483 | } |
| 3484 | |
| 3485 | return ctx; |
| 3486 | |
| 3487 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3488 | i915_gem_object_ggtt_unpin(ctx); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3489 | err_unref: |
| 3490 | drm_gem_object_unreference(&ctx->base); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3491 | return NULL; |
| 3492 | } |
| 3493 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3494 | /** |
| 3495 | * Lock protecting IPS related data structures |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3496 | */ |
| 3497 | DEFINE_SPINLOCK(mchdev_lock); |
| 3498 | |
| 3499 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 3500 | * mchdev_lock. */ |
| 3501 | static struct drm_i915_private *i915_mch_dev; |
| 3502 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3503 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 3504 | { |
| 3505 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3506 | u16 rgvswctl; |
| 3507 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3508 | assert_spin_locked(&mchdev_lock); |
| 3509 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3510 | rgvswctl = I915_READ16(MEMSWCTL); |
| 3511 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 3512 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 3513 | return false; /* still busy with another command */ |
| 3514 | } |
| 3515 | |
| 3516 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 3517 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 3518 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 3519 | POSTING_READ16(MEMSWCTL); |
| 3520 | |
| 3521 | rgvswctl |= MEMCTL_CMD_STS; |
| 3522 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 3523 | |
| 3524 | return true; |
| 3525 | } |
| 3526 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3527 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3528 | { |
| 3529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3530 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 3531 | u8 fmax, fmin, fstart, vstart; |
| 3532 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3533 | spin_lock_irq(&mchdev_lock); |
| 3534 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3535 | /* Enable temp reporting */ |
| 3536 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 3537 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 3538 | |
| 3539 | /* 100ms RC evaluation intervals */ |
| 3540 | I915_WRITE(RCUPEI, 100000); |
| 3541 | I915_WRITE(RCDNEI, 100000); |
| 3542 | |
| 3543 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 3544 | I915_WRITE(RCBMAXAVG, 90000); |
| 3545 | I915_WRITE(RCBMINAVG, 80000); |
| 3546 | |
| 3547 | I915_WRITE(MEMIHYST, 1); |
| 3548 | |
| 3549 | /* Set up min, max, and cur for interrupt handling */ |
| 3550 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 3551 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 3552 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 3553 | MEMMODE_FSTART_SHIFT; |
| 3554 | |
| 3555 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 3556 | PXVFREQ_PX_SHIFT; |
| 3557 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3558 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
| 3559 | dev_priv->ips.fstart = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3560 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3561 | dev_priv->ips.max_delay = fstart; |
| 3562 | dev_priv->ips.min_delay = fmin; |
| 3563 | dev_priv->ips.cur_delay = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3564 | |
| 3565 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 3566 | fmax, fmin, fstart); |
| 3567 | |
| 3568 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 3569 | |
| 3570 | /* |
| 3571 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 3572 | */ |
| 3573 | |
| 3574 | I915_WRITE(VIDSTART, vstart); |
| 3575 | POSTING_READ(VIDSTART); |
| 3576 | |
| 3577 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 3578 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 3579 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3580 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3581 | DRM_ERROR("stuck trying to change perf mode\n"); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3582 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3583 | |
| 3584 | ironlake_set_drps(dev, fstart); |
| 3585 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3586 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3587 | I915_READ(0x112e0); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3588 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
| 3589 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 3590 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3591 | |
| 3592 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3593 | } |
| 3594 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3595 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3596 | { |
| 3597 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3598 | u16 rgvswctl; |
| 3599 | |
| 3600 | spin_lock_irq(&mchdev_lock); |
| 3601 | |
| 3602 | rgvswctl = I915_READ16(MEMSWCTL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3603 | |
| 3604 | /* Ack interrupts, disable EFC interrupt */ |
| 3605 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 3606 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 3607 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 3608 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 3609 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 3610 | |
| 3611 | /* Go back to the starting frequency */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3612 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3613 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3614 | rgvswctl |= MEMCTL_CMD_STS; |
| 3615 | I915_WRITE(MEMSWCTL, rgvswctl); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3616 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3617 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3618 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3619 | } |
| 3620 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 3621 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 3622 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 3623 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 3624 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 3625 | */ |
Chris Wilson | 6917c7b | 2013-11-06 13:56:26 -0200 | [diff] [blame] | 3626 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3627 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3628 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3629 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3630 | /* Only set the down limit when we've reached the lowest level to avoid |
| 3631 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 3632 | * race in the hw when coming out of rc6: There's a tiny window where |
| 3633 | * the hw runs at the minimal clock before selecting the desired |
| 3634 | * frequency, if the down threshold expires in that window we will not |
| 3635 | * receive a down interrupt. */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3636 | limits = dev_priv->rps.max_freq_softlimit << 24; |
| 3637 | if (val <= dev_priv->rps.min_freq_softlimit) |
| 3638 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3639 | |
| 3640 | return limits; |
| 3641 | } |
| 3642 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3643 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
| 3644 | { |
| 3645 | int new_power; |
| 3646 | |
| 3647 | new_power = dev_priv->rps.power; |
| 3648 | switch (dev_priv->rps.power) { |
| 3649 | case LOW_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3650 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3651 | new_power = BETWEEN; |
| 3652 | break; |
| 3653 | |
| 3654 | case BETWEEN: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3655 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3656 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3657 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3658 | new_power = HIGH_POWER; |
| 3659 | break; |
| 3660 | |
| 3661 | case HIGH_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3662 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3663 | new_power = BETWEEN; |
| 3664 | break; |
| 3665 | } |
| 3666 | /* Max/min bins are special */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3667 | if (val == dev_priv->rps.min_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3668 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3669 | if (val == dev_priv->rps.max_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3670 | new_power = HIGH_POWER; |
| 3671 | if (new_power == dev_priv->rps.power) |
| 3672 | return; |
| 3673 | |
| 3674 | /* Note the units here are not exactly 1us, but 1280ns. */ |
| 3675 | switch (new_power) { |
| 3676 | case LOW_POWER: |
| 3677 | /* Upclock if more than 95% busy over 16ms */ |
| 3678 | I915_WRITE(GEN6_RP_UP_EI, 12500); |
| 3679 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); |
| 3680 | |
| 3681 | /* Downclock if less than 85% busy over 32ms */ |
| 3682 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3683 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); |
| 3684 | |
| 3685 | I915_WRITE(GEN6_RP_CONTROL, |
| 3686 | GEN6_RP_MEDIA_TURBO | |
| 3687 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3688 | GEN6_RP_MEDIA_IS_GFX | |
| 3689 | GEN6_RP_ENABLE | |
| 3690 | GEN6_RP_UP_BUSY_AVG | |
| 3691 | GEN6_RP_DOWN_IDLE_AVG); |
| 3692 | break; |
| 3693 | |
| 3694 | case BETWEEN: |
| 3695 | /* Upclock if more than 90% busy over 13ms */ |
| 3696 | I915_WRITE(GEN6_RP_UP_EI, 10250); |
| 3697 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); |
| 3698 | |
| 3699 | /* Downclock if less than 75% busy over 32ms */ |
| 3700 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3701 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); |
| 3702 | |
| 3703 | I915_WRITE(GEN6_RP_CONTROL, |
| 3704 | GEN6_RP_MEDIA_TURBO | |
| 3705 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3706 | GEN6_RP_MEDIA_IS_GFX | |
| 3707 | GEN6_RP_ENABLE | |
| 3708 | GEN6_RP_UP_BUSY_AVG | |
| 3709 | GEN6_RP_DOWN_IDLE_AVG); |
| 3710 | break; |
| 3711 | |
| 3712 | case HIGH_POWER: |
| 3713 | /* Upclock if more than 85% busy over 10ms */ |
| 3714 | I915_WRITE(GEN6_RP_UP_EI, 8000); |
| 3715 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); |
| 3716 | |
| 3717 | /* Downclock if less than 60% busy over 32ms */ |
| 3718 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3719 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); |
| 3720 | |
| 3721 | I915_WRITE(GEN6_RP_CONTROL, |
| 3722 | GEN6_RP_MEDIA_TURBO | |
| 3723 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3724 | GEN6_RP_MEDIA_IS_GFX | |
| 3725 | GEN6_RP_ENABLE | |
| 3726 | GEN6_RP_UP_BUSY_AVG | |
| 3727 | GEN6_RP_DOWN_IDLE_AVG); |
| 3728 | break; |
| 3729 | } |
| 3730 | |
| 3731 | dev_priv->rps.power = new_power; |
| 3732 | dev_priv->rps.last_adj = 0; |
| 3733 | } |
| 3734 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3735 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
| 3736 | { |
| 3737 | u32 mask = 0; |
| 3738 | |
| 3739 | if (val > dev_priv->rps.min_freq_softlimit) |
| 3740 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
| 3741 | if (val < dev_priv->rps.max_freq_softlimit) |
| 3742 | mask |= GEN6_PM_RP_UP_THRESHOLD; |
| 3743 | |
Chris Wilson | 7b3c29f | 2014-07-10 20:31:19 +0100 | [diff] [blame] | 3744 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
| 3745 | mask &= dev_priv->pm_rps_events; |
| 3746 | |
Imre Deak | 59d02a1 | 2014-12-19 19:33:26 +0200 | [diff] [blame] | 3747 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3748 | } |
| 3749 | |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3750 | /* gen6_set_rps is called to update the frequency request, but should also be |
| 3751 | * called when the range (min_delay and max_delay) is modified so that we can |
| 3752 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3753 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 3754 | { |
| 3755 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3756 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3757 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3758 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3759 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3760 | |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3761 | /* min/max delay may still have been modified so be sure to |
| 3762 | * write the limits value. |
| 3763 | */ |
| 3764 | if (val != dev_priv->rps.cur_freq) { |
| 3765 | gen6_set_rps_thresholds(dev_priv, val); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3766 | |
Ben Widawsky | 50e6a2a | 2014-03-31 17:16:43 -0700 | [diff] [blame] | 3767 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3768 | I915_WRITE(GEN6_RPNSWREQ, |
| 3769 | HSW_FREQUENCY(val)); |
| 3770 | else |
| 3771 | I915_WRITE(GEN6_RPNSWREQ, |
| 3772 | GEN6_FREQUENCY(val) | |
| 3773 | GEN6_OFFSET(0) | |
| 3774 | GEN6_AGGRESSIVE_TURBO); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3775 | } |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3776 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3777 | /* Make sure we continue to get interrupts |
| 3778 | * until we hit the minimum or maximum frequencies. |
| 3779 | */ |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3780 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3781 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3782 | |
Ben Widawsky | d5570a7 | 2012-09-07 19:43:41 -0700 | [diff] [blame] | 3783 | POSTING_READ(GEN6_RPNSWREQ); |
| 3784 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3785 | dev_priv->rps.cur_freq = val; |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 3786 | trace_intel_gpu_freq_change(val * 50); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3787 | } |
| 3788 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3789 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
| 3790 | * |
| 3791 | * * If Gfx is Idle, then |
| 3792 | * 1. Mask Turbo interrupts |
| 3793 | * 2. Bring up Gfx clock |
| 3794 | * 3. Change the freq to Rpn and wait till P-Unit updates freq |
| 3795 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down |
| 3796 | * 5. Unmask Turbo interrupts |
| 3797 | */ |
| 3798 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
| 3799 | { |
Deepak S | 5549d25 | 2014-06-28 11:26:11 +0530 | [diff] [blame] | 3800 | struct drm_device *dev = dev_priv->dev; |
| 3801 | |
Ville Syrjälä | 21a11ff | 2015-01-27 16:36:15 +0200 | [diff] [blame] | 3802 | /* CHV and latest VLV don't need to force the gfx clock */ |
| 3803 | if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) { |
Deepak S | 5549d25 | 2014-06-28 11:26:11 +0530 | [diff] [blame] | 3804 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
| 3805 | return; |
| 3806 | } |
| 3807 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3808 | /* |
| 3809 | * When we are idle. Drop to min voltage state. |
| 3810 | */ |
| 3811 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3812 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3813 | return; |
| 3814 | |
| 3815 | /* Mask turbo interrupt so that they will not come in between */ |
Imre Deak | f24eeb1 | 2014-12-19 19:33:27 +0200 | [diff] [blame] | 3816 | I915_WRITE(GEN6_PMINTRMSK, |
| 3817 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3818 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3819 | vlv_force_gfx_clock(dev_priv, true); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3820 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3821 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3822 | |
| 3823 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3824 | dev_priv->rps.min_freq_softlimit); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3825 | |
| 3826 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) |
Imre Deak | 2837ac4 | 2014-11-19 16:25:38 +0200 | [diff] [blame] | 3827 | & GENFREQSTATUS) == 0, 100)) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3828 | DRM_ERROR("timed out waiting for Punit\n"); |
| 3829 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3830 | vlv_force_gfx_clock(dev_priv, false); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3831 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3832 | I915_WRITE(GEN6_PMINTRMSK, |
| 3833 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3834 | } |
| 3835 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3836 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
| 3837 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3838 | struct drm_device *dev = dev_priv->dev; |
| 3839 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3840 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3841 | if (dev_priv->rps.enabled) { |
Ville Syrjälä | 21a11ff | 2015-01-27 16:36:15 +0200 | [diff] [blame] | 3842 | if (IS_VALLEYVIEW(dev)) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3843 | vlv_set_rps_idle(dev_priv); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 3844 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3845 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3846 | dev_priv->rps.last_adj = 0; |
| 3847 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3848 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3849 | } |
| 3850 | |
| 3851 | void gen6_rps_boost(struct drm_i915_private *dev_priv) |
| 3852 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3853 | struct drm_device *dev = dev_priv->dev; |
| 3854 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3855 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3856 | if (dev_priv->rps.enabled) { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3857 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3858 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 3859 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3860 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3861 | dev_priv->rps.last_adj = 0; |
| 3862 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3863 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3864 | } |
| 3865 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3866 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
| 3867 | { |
| 3868 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 7a67092 | 2013-06-25 19:21:06 +0300 | [diff] [blame] | 3869 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3870 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3871 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3872 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3873 | |
Ville Syrjälä | 1c14762 | 2014-08-18 14:42:43 +0300 | [diff] [blame] | 3874 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
| 3875 | "Odd GPU freq value\n")) |
| 3876 | val &= ~1; |
| 3877 | |
Ville Syrjälä | 9a3b9c7 | 2014-11-07 21:33:42 +0200 | [diff] [blame] | 3878 | if (val != dev_priv->rps.cur_freq) |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3879 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3880 | |
Imre Deak | 09c87db | 2014-04-03 20:02:42 +0300 | [diff] [blame] | 3881 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3882 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3883 | dev_priv->rps.cur_freq = val; |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 3884 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3885 | } |
| 3886 | |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 3887 | static void gen9_disable_rps(struct drm_device *dev) |
| 3888 | { |
| 3889 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3890 | |
| 3891 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 3892 | I915_WRITE(GEN9_PG_ENABLE, 0); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 3893 | } |
| 3894 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3895 | static void gen6_disable_rps(struct drm_device *dev) |
| 3896 | { |
| 3897 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3898 | |
| 3899 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3900 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3901 | } |
| 3902 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 3903 | static void cherryview_disable_rps(struct drm_device *dev) |
| 3904 | { |
| 3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3906 | |
| 3907 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3908 | } |
| 3909 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3910 | static void valleyview_disable_rps(struct drm_device *dev) |
| 3911 | { |
| 3912 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3913 | |
Deepak S | 98a2e5f | 2014-08-18 10:35:27 -0700 | [diff] [blame] | 3914 | /* we're doing forcewake before Disabling RC6, |
| 3915 | * This what the BIOS expects when going into suspend */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 3916 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Deepak S | 98a2e5f | 2014-08-18 10:35:27 -0700 | [diff] [blame] | 3917 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3918 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3919 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 3920 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3921 | } |
| 3922 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3923 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
| 3924 | { |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 3925 | if (IS_VALLEYVIEW(dev)) { |
| 3926 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
| 3927 | mode = GEN6_RC_CTL_RC6_ENABLE; |
| 3928 | else |
| 3929 | mode = 0; |
| 3930 | } |
Rodrigo Vivi | 58abf1d | 2014-10-07 07:06:50 -0700 | [diff] [blame] | 3931 | if (HAS_RC6p(dev)) |
| 3932 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
| 3933 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 3934 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 3935 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
| 3936 | |
| 3937 | else |
| 3938 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
| 3939 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3940 | } |
| 3941 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3942 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3943 | { |
Damien Lespiau | eb4926e | 2013-06-07 17:41:14 +0100 | [diff] [blame] | 3944 | /* No RC6 before Ironlake */ |
| 3945 | if (INTEL_INFO(dev)->gen < 5) |
| 3946 | return 0; |
| 3947 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3948 | /* RC6 is only on Ironlake mobile not on desktop */ |
| 3949 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) |
| 3950 | return 0; |
| 3951 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3952 | /* Respect the kernel parameter if it is set */ |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3953 | if (enable_rc6 >= 0) { |
| 3954 | int mask; |
| 3955 | |
Rodrigo Vivi | 58abf1d | 2014-10-07 07:06:50 -0700 | [diff] [blame] | 3956 | if (HAS_RC6p(dev)) |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3957 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
| 3958 | INTEL_RC6pp_ENABLE; |
| 3959 | else |
| 3960 | mask = INTEL_RC6_ENABLE; |
| 3961 | |
| 3962 | if ((enable_rc6 & mask) != enable_rc6) |
Daniel Vetter | 8dfd1f0 | 2014-08-04 11:15:56 +0200 | [diff] [blame] | 3963 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
| 3964 | enable_rc6 & mask, enable_rc6, mask); |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3965 | |
| 3966 | return enable_rc6 & mask; |
| 3967 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3968 | |
Chris Wilson | 6567d74 | 2012-11-10 10:00:06 +0000 | [diff] [blame] | 3969 | /* Disable RC6 on Ironlake */ |
| 3970 | if (INTEL_INFO(dev)->gen == 5) |
| 3971 | return 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3972 | |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3973 | if (IS_IVYBRIDGE(dev)) |
Ben Widawsky | cca84a1 | 2014-01-28 20:25:38 -0800 | [diff] [blame] | 3974 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3975 | |
| 3976 | return INTEL_RC6_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3977 | } |
| 3978 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3979 | int intel_enable_rc6(const struct drm_device *dev) |
| 3980 | { |
| 3981 | return i915.enable_rc6; |
| 3982 | } |
| 3983 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 3984 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3985 | { |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 3986 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3987 | uint32_t rp_state_cap; |
| 3988 | u32 ddcc_status = 0; |
| 3989 | int ret; |
| 3990 | |
| 3991 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3992 | /* All of these values are in units of 50MHz */ |
| 3993 | dev_priv->rps.cur_freq = 0; |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 3994 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3995 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 3996 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3997 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3998 | /* hw_max = RP0 until we check for overclocking */ |
| 3999 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
| 4000 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4001 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
| 4002 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 4003 | ret = sandybridge_pcode_read(dev_priv, |
| 4004 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, |
| 4005 | &ddcc_status); |
| 4006 | if (0 == ret) |
| 4007 | dev_priv->rps.efficient_freq = |
| 4008 | (ddcc_status >> 8) & 0xff; |
| 4009 | } |
| 4010 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4011 | /* Preserve min/max settings in case of re-init */ |
| 4012 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4013 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4014 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4015 | if (dev_priv->rps.min_freq_softlimit == 0) { |
| 4016 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 4017 | dev_priv->rps.min_freq_softlimit = |
Tom O'Rourke | f4ab408 | 2014-11-19 14:21:53 -0800 | [diff] [blame] | 4018 | /* max(RPe, 450 MHz) */ |
| 4019 | max(dev_priv->rps.efficient_freq, (u8) 9); |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4020 | else |
| 4021 | dev_priv->rps.min_freq_softlimit = |
| 4022 | dev_priv->rps.min_freq; |
| 4023 | } |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4024 | } |
| 4025 | |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4026 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4027 | static void gen9_enable_rps(struct drm_device *dev) |
| 4028 | { |
| 4029 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4030 | |
| 4031 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4032 | |
Damien Lespiau | ba1c554 | 2015-01-16 18:07:26 +0000 | [diff] [blame] | 4033 | gen6_init_rps_frequencies(dev); |
| 4034 | |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4035 | I915_WRITE(GEN6_RPNSWREQ, 0xc800000); |
| 4036 | I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); |
| 4037 | |
| 4038 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); |
| 4039 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); |
| 4040 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); |
| 4041 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); |
| 4042 | I915_WRITE(GEN6_RP_UP_EI, 0x101d0); |
| 4043 | I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); |
| 4044 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
| 4045 | I915_WRITE(GEN6_PMINTRMSK, 0x6); |
| 4046 | I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | |
| 4047 | GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | |
| 4048 | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | |
| 4049 | GEN6_RP_DOWN_IDLE_AVG); |
| 4050 | |
| 4051 | gen6_enable_rps_interrupts(dev); |
| 4052 | |
| 4053 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 4054 | } |
| 4055 | |
| 4056 | static void gen9_enable_rc6(struct drm_device *dev) |
| 4057 | { |
| 4058 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4059 | struct intel_engine_cs *ring; |
| 4060 | uint32_t rc6_mask = 0; |
| 4061 | int unused; |
| 4062 | |
| 4063 | /* 1a: Software RC state - RC0 */ |
| 4064 | I915_WRITE(GEN6_RC_STATE, 0); |
| 4065 | |
| 4066 | /* 1b: Get forcewake during program sequence. Although the driver |
| 4067 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4068 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4069 | |
| 4070 | /* 2a: Disable RC states. */ |
| 4071 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4072 | |
| 4073 | /* 2b: Program RC6 thresholds.*/ |
| 4074 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); |
| 4075 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4076 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4077 | for_each_ring(ring, dev_priv, unused) |
| 4078 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4079 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 4080 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
| 4081 | |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 4082 | /* 2c: Program Coarse Power Gating Policies. */ |
| 4083 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); |
| 4084 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
| 4085 | |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4086 | /* 3a: Enable RC6 */ |
| 4087 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 4088 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
| 4089 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
| 4090 | "on" : "off"); |
| 4091 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4092 | GEN6_RC_CTL_EI_MODE(1) | |
| 4093 | rc6_mask); |
| 4094 | |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 4095 | /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ |
| 4096 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); |
| 4097 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4098 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4099 | |
| 4100 | } |
| 4101 | |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4102 | static void gen8_enable_rps(struct drm_device *dev) |
| 4103 | { |
| 4104 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4105 | struct intel_engine_cs *ring; |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4106 | uint32_t rc6_mask = 0; |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4107 | int unused; |
| 4108 | |
| 4109 | /* 1a: Software RC state - RC0 */ |
| 4110 | I915_WRITE(GEN6_RC_STATE, 0); |
| 4111 | |
| 4112 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
| 4113 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4114 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4115 | |
| 4116 | /* 2a: Disable RC states. */ |
| 4117 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4118 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4119 | /* Initialize rps frequencies */ |
| 4120 | gen6_init_rps_frequencies(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4121 | |
| 4122 | /* 2b: Program RC6 thresholds.*/ |
| 4123 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 4124 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4125 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4126 | for_each_ring(ring, dev_priv, unused) |
| 4127 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4128 | I915_WRITE(GEN6_RC_SLEEP, 0); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 4129 | if (IS_BROADWELL(dev)) |
| 4130 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
| 4131 | else |
| 4132 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4133 | |
| 4134 | /* 3: Enable RC6 */ |
| 4135 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 4136 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
Ben Widawsky | abbf9d2 | 2014-01-28 20:25:41 -0800 | [diff] [blame] | 4137 | intel_print_rc6_info(dev, rc6_mask); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 4138 | if (IS_BROADWELL(dev)) |
| 4139 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4140 | GEN7_RC_CTL_TO_MODE | |
| 4141 | rc6_mask); |
| 4142 | else |
| 4143 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4144 | GEN6_RC_CTL_EI_MODE(1) | |
| 4145 | rc6_mask); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4146 | |
| 4147 | /* 4 Program defaults and thresholds for RPS*/ |
Ben Widawsky | f9bdc58 | 2014-03-31 17:16:41 -0700 | [diff] [blame] | 4148 | I915_WRITE(GEN6_RPNSWREQ, |
| 4149 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
| 4150 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 4151 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4152 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
| 4153 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4154 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4155 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
| 4156 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 4157 | dev_priv->rps.max_freq_softlimit << 24 | |
| 4158 | dev_priv->rps.min_freq_softlimit << 16); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4159 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4160 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
| 4161 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
| 4162 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
| 4163 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4164 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4165 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4166 | |
| 4167 | /* 5: Enable RPS */ |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4168 | I915_WRITE(GEN6_RP_CONTROL, |
| 4169 | GEN6_RP_MEDIA_TURBO | |
| 4170 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 4171 | GEN6_RP_MEDIA_IS_GFX | |
| 4172 | GEN6_RP_ENABLE | |
| 4173 | GEN6_RP_UP_BUSY_AVG | |
| 4174 | GEN6_RP_DOWN_IDLE_AVG); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4175 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4176 | /* 6: Ring frequency + overclocking (our driver does this later */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4177 | |
Tom O'Rourke | c7f3153 | 2014-11-19 14:21:54 -0800 | [diff] [blame] | 4178 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
| 4179 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4180 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4181 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4182 | } |
| 4183 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4184 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4185 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4186 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4187 | struct intel_engine_cs *ring; |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4188 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4189 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4190 | int rc6_mode; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4191 | int i, ret; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4192 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4193 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4194 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4195 | /* Here begins a magic sequence of register writes to enable |
| 4196 | * auto-downclocking. |
| 4197 | * |
| 4198 | * Perhaps there might be some value in exposing these to |
| 4199 | * userspace... |
| 4200 | */ |
| 4201 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4202 | |
| 4203 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 4204 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 4205 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 4206 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4207 | } |
| 4208 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4209 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4210 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4211 | /* Initialize rps frequencies */ |
| 4212 | gen6_init_rps_frequencies(dev); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4213 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4214 | /* disable the counters and set deterministic thresholds */ |
| 4215 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4216 | |
| 4217 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 4218 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 4219 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 4220 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 4221 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 4222 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4223 | for_each_ring(ring, dev_priv, i) |
| 4224 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4225 | |
| 4226 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 4227 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
Daniel Vetter | 29c78f6 | 2013-11-16 16:04:26 +0100 | [diff] [blame] | 4228 | if (IS_IVYBRIDGE(dev)) |
Stéphane Marchesin | 351aa56 | 2013-08-13 11:55:17 -0700 | [diff] [blame] | 4229 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
| 4230 | else |
| 4231 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
Stéphane Marchesin | 0920a48 | 2013-01-29 19:41:59 -0800 | [diff] [blame] | 4232 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4233 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 4234 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4235 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4236 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 4237 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 4238 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 4239 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4240 | /* We don't use those on Haswell */ |
| 4241 | if (!IS_HASWELL(dev)) { |
| 4242 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 4243 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4244 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4245 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 4246 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 4247 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4248 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4249 | intel_print_rc6_info(dev, rc6_mask); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4250 | |
| 4251 | I915_WRITE(GEN6_RC_CONTROL, |
| 4252 | rc6_mask | |
| 4253 | GEN6_RC_CTL_EI_MODE(1) | |
| 4254 | GEN6_RC_CTL_HW_ENABLE); |
| 4255 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4256 | /* Power down if completely idle for over 50ms */ |
| 4257 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4258 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4259 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4260 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4261 | if (ret) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4262 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4263 | |
| 4264 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
| 4265 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
| 4266 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4267 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4268 | (pcu_mbox & 0xff) * 50); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4269 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4270 | } |
| 4271 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4272 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4273 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4274 | |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 4275 | rc6vids = 0; |
| 4276 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 4277 | if (IS_GEN6(dev) && ret) { |
| 4278 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
| 4279 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
| 4280 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
| 4281 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
| 4282 | rc6vids &= 0xffff00; |
| 4283 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
| 4284 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
| 4285 | if (ret) |
| 4286 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
| 4287 | } |
| 4288 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4289 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4290 | } |
| 4291 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 4292 | static void __gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4293 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4294 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4295 | int min_freq = 15; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4296 | unsigned int gpu_freq; |
| 4297 | unsigned int max_ia_freq, min_ring_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4298 | int scaling_factor = 180; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 4299 | struct cpufreq_policy *policy; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4300 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4301 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4302 | |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 4303 | policy = cpufreq_cpu_get(0); |
| 4304 | if (policy) { |
| 4305 | max_ia_freq = policy->cpuinfo.max_freq; |
| 4306 | cpufreq_cpu_put(policy); |
| 4307 | } else { |
| 4308 | /* |
| 4309 | * Default to measured freq if none found, PCU will ensure we |
| 4310 | * don't go over |
| 4311 | */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4312 | max_ia_freq = tsc_khz; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 4313 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4314 | |
| 4315 | /* Convert from kHz to MHz */ |
| 4316 | max_ia_freq /= 1000; |
| 4317 | |
Ben Widawsky | 153b4b95 | 2013-10-22 22:05:09 -0700 | [diff] [blame] | 4318 | min_ring_freq = I915_READ(DCLK) & 0xf; |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 4319 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
| 4320 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4321 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4322 | /* |
| 4323 | * For each potential GPU frequency, load a ring frequency we'd like |
| 4324 | * to use for memory access. We do this by specifying the IA frequency |
| 4325 | * the PCU should use as a reference to determine the ring frequency. |
| 4326 | */ |
Tom O'Rourke | 6985b35 | 2014-11-19 14:21:55 -0800 | [diff] [blame] | 4327 | for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4328 | gpu_freq--) { |
Tom O'Rourke | 6985b35 | 2014-11-19 14:21:55 -0800 | [diff] [blame] | 4329 | int diff = dev_priv->rps.max_freq - gpu_freq; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4330 | unsigned int ia_freq = 0, ring_freq = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4331 | |
Ben Widawsky | 46c764d | 2013-11-02 21:07:49 -0700 | [diff] [blame] | 4332 | if (INTEL_INFO(dev)->gen >= 8) { |
| 4333 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
| 4334 | ring_freq = max(min_ring_freq, gpu_freq); |
| 4335 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 4336 | ring_freq = mult_frac(gpu_freq, 5, 4); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4337 | ring_freq = max(min_ring_freq, ring_freq); |
| 4338 | /* leave ia_freq as the default, chosen by cpufreq */ |
| 4339 | } else { |
| 4340 | /* On older processors, there is no separate ring |
| 4341 | * clock domain, so in order to boost the bandwidth |
| 4342 | * of the ring, we need to upclock the CPU (ia_freq). |
| 4343 | * |
| 4344 | * For GPU frequencies less than 750MHz, |
| 4345 | * just use the lowest ring freq. |
| 4346 | */ |
| 4347 | if (gpu_freq < min_freq) |
| 4348 | ia_freq = 800; |
| 4349 | else |
| 4350 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 4351 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 4352 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4353 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4354 | sandybridge_pcode_write(dev_priv, |
| 4355 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4356 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
| 4357 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
| 4358 | gpu_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4359 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4360 | } |
| 4361 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 4362 | void gen6_update_ring_freq(struct drm_device *dev) |
| 4363 | { |
| 4364 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4365 | |
| 4366 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) |
| 4367 | return; |
| 4368 | |
| 4369 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4370 | __gen6_update_ring_freq(dev); |
| 4371 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4372 | } |
| 4373 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4374 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4375 | { |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4376 | struct drm_device *dev = dev_priv->dev; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4377 | u32 val, rp0; |
| 4378 | |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4379 | if (dev->pdev->revision >= 0x20) { |
| 4380 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4381 | |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4382 | switch (INTEL_INFO(dev)->eu_total) { |
| 4383 | case 8: |
| 4384 | /* (2 * 4) config */ |
| 4385 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); |
| 4386 | break; |
| 4387 | case 12: |
| 4388 | /* (2 * 6) config */ |
| 4389 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); |
| 4390 | break; |
| 4391 | case 16: |
| 4392 | /* (2 * 8) config */ |
| 4393 | default: |
| 4394 | /* Setting (2 * 8) Min RP0 for any other combination */ |
| 4395 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); |
| 4396 | break; |
| 4397 | } |
| 4398 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); |
| 4399 | } else { |
| 4400 | /* For pre-production hardware */ |
| 4401 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); |
| 4402 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & |
| 4403 | PUNIT_GPU_STATUS_MAX_FREQ_MASK; |
| 4404 | } |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4405 | return rp0; |
| 4406 | } |
| 4407 | |
| 4408 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 4409 | { |
| 4410 | u32 val, rpe; |
| 4411 | |
| 4412 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); |
| 4413 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; |
| 4414 | |
| 4415 | return rpe; |
| 4416 | } |
| 4417 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4418 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 4419 | { |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4420 | struct drm_device *dev = dev_priv->dev; |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4421 | u32 val, rp1; |
| 4422 | |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4423 | if (dev->pdev->revision >= 0x20) { |
| 4424 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
| 4425 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); |
| 4426 | } else { |
| 4427 | /* For pre-production hardware */ |
| 4428 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 4429 | rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & |
| 4430 | PUNIT_GPU_STATUS_MAX_FREQ_MASK); |
| 4431 | } |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4432 | return rp1; |
| 4433 | } |
| 4434 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4435 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4436 | { |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4437 | struct drm_device *dev = dev_priv->dev; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4438 | u32 val, rpn; |
| 4439 | |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 4440 | if (dev->pdev->revision >= 0x20) { |
| 4441 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); |
| 4442 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & |
| 4443 | FB_GFX_FREQ_FUSE_MASK); |
| 4444 | } else { /* For pre-production hardware */ |
| 4445 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); |
| 4446 | rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & |
| 4447 | PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK); |
| 4448 | } |
| 4449 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4450 | return rpn; |
| 4451 | } |
| 4452 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 4453 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 4454 | { |
| 4455 | u32 val, rp1; |
| 4456 | |
| 4457 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
| 4458 | |
| 4459 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; |
| 4460 | |
| 4461 | return rp1; |
| 4462 | } |
| 4463 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4464 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4465 | { |
| 4466 | u32 val, rp0; |
| 4467 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4468 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4469 | |
| 4470 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
| 4471 | /* Clamp to max */ |
| 4472 | rp0 = min_t(u32, rp0, 0xea); |
| 4473 | |
| 4474 | return rp0; |
| 4475 | } |
| 4476 | |
| 4477 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 4478 | { |
| 4479 | u32 val, rpe; |
| 4480 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4481 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4482 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4483 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4484 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
| 4485 | |
| 4486 | return rpe; |
| 4487 | } |
| 4488 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4489 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4490 | { |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4491 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4492 | } |
| 4493 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4494 | /* Check that the pctx buffer wasn't move under us. */ |
| 4495 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
| 4496 | { |
| 4497 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 4498 | |
| 4499 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
| 4500 | dev_priv->vlv_pctx->stolen->start); |
| 4501 | } |
| 4502 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4503 | |
| 4504 | /* Check that the pcbr address is not empty. */ |
| 4505 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) |
| 4506 | { |
| 4507 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 4508 | |
| 4509 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); |
| 4510 | } |
| 4511 | |
| 4512 | static void cherryview_setup_pctx(struct drm_device *dev) |
| 4513 | { |
| 4514 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4515 | unsigned long pctx_paddr, paddr; |
| 4516 | struct i915_gtt *gtt = &dev_priv->gtt; |
| 4517 | u32 pcbr; |
| 4518 | int pctx_size = 32*1024; |
| 4519 | |
| 4520 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4521 | |
| 4522 | pcbr = I915_READ(VLV_PCBR); |
| 4523 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 4524 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4525 | paddr = (dev_priv->mm.stolen_base + |
| 4526 | (gtt->stolen_size - pctx_size)); |
| 4527 | |
| 4528 | pctx_paddr = (paddr & (~4095)); |
| 4529 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 4530 | } |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 4531 | |
| 4532 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4533 | } |
| 4534 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4535 | static void valleyview_setup_pctx(struct drm_device *dev) |
| 4536 | { |
| 4537 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4538 | struct drm_i915_gem_object *pctx; |
| 4539 | unsigned long pctx_paddr; |
| 4540 | u32 pcbr; |
| 4541 | int pctx_size = 24*1024; |
| 4542 | |
Imre Deak | 17b0c1f | 2014-02-11 21:39:06 +0200 | [diff] [blame] | 4543 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4544 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4545 | pcbr = I915_READ(VLV_PCBR); |
| 4546 | if (pcbr) { |
| 4547 | /* BIOS set it up already, grab the pre-alloc'd space */ |
| 4548 | int pcbr_offset; |
| 4549 | |
| 4550 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
| 4551 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
| 4552 | pcbr_offset, |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 4553 | I915_GTT_OFFSET_NONE, |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4554 | pctx_size); |
| 4555 | goto out; |
| 4556 | } |
| 4557 | |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 4558 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
| 4559 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4560 | /* |
| 4561 | * From the Gunit register HAS: |
| 4562 | * The Gfx driver is expected to program this register and ensure |
| 4563 | * proper allocation within Gfx stolen memory. For example, this |
| 4564 | * register should be programmed such than the PCBR range does not |
| 4565 | * overlap with other ranges, such as the frame buffer, protected |
| 4566 | * memory, or any other relevant ranges. |
| 4567 | */ |
| 4568 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
| 4569 | if (!pctx) { |
| 4570 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
| 4571 | return; |
| 4572 | } |
| 4573 | |
| 4574 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
| 4575 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 4576 | |
| 4577 | out: |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 4578 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4579 | dev_priv->vlv_pctx = pctx; |
| 4580 | } |
| 4581 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4582 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
| 4583 | { |
| 4584 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4585 | |
| 4586 | if (WARN_ON(!dev_priv->vlv_pctx)) |
| 4587 | return; |
| 4588 | |
| 4589 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
| 4590 | dev_priv->vlv_pctx = NULL; |
| 4591 | } |
| 4592 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4593 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
| 4594 | { |
| 4595 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4596 | u32 val; |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4597 | |
| 4598 | valleyview_setup_pctx(dev); |
| 4599 | |
| 4600 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4601 | |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4602 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 4603 | switch ((val >> 6) & 3) { |
| 4604 | case 0: |
| 4605 | case 1: |
| 4606 | dev_priv->mem_freq = 800; |
| 4607 | break; |
| 4608 | case 2: |
| 4609 | dev_priv->mem_freq = 1066; |
| 4610 | break; |
| 4611 | case 3: |
| 4612 | dev_priv->mem_freq = 1333; |
| 4613 | break; |
| 4614 | } |
Ville Syrjälä | 80b83b6 | 2014-11-10 22:55:14 +0200 | [diff] [blame] | 4615 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4616 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4617 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
| 4618 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 4619 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4620 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4621 | dev_priv->rps.max_freq); |
| 4622 | |
| 4623 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
| 4624 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4625 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4626 | dev_priv->rps.efficient_freq); |
| 4627 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 4628 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
| 4629 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4630 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 4631 | dev_priv->rps.rp1_freq); |
| 4632 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4633 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
| 4634 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4635 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4636 | dev_priv->rps.min_freq); |
| 4637 | |
| 4638 | /* Preserve min/max settings in case of re-init */ |
| 4639 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4640 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4641 | |
| 4642 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 4643 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 4644 | |
| 4645 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4646 | } |
| 4647 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4648 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
| 4649 | { |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4650 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4651 | u32 val; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4652 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4653 | cherryview_setup_pctx(dev); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4654 | |
| 4655 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4656 | |
Ville Syrjälä | c6e8f39 | 2014-11-07 21:33:43 +0200 | [diff] [blame] | 4657 | mutex_lock(&dev_priv->dpio_lock); |
| 4658 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
| 4659 | mutex_unlock(&dev_priv->dpio_lock); |
| 4660 | |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4661 | switch ((val >> 2) & 0x7) { |
| 4662 | case 0: |
| 4663 | case 1: |
| 4664 | dev_priv->rps.cz_freq = 200; |
| 4665 | dev_priv->mem_freq = 1600; |
| 4666 | break; |
| 4667 | case 2: |
| 4668 | dev_priv->rps.cz_freq = 267; |
| 4669 | dev_priv->mem_freq = 1600; |
| 4670 | break; |
| 4671 | case 3: |
| 4672 | dev_priv->rps.cz_freq = 333; |
| 4673 | dev_priv->mem_freq = 2000; |
| 4674 | break; |
| 4675 | case 4: |
| 4676 | dev_priv->rps.cz_freq = 320; |
| 4677 | dev_priv->mem_freq = 1600; |
| 4678 | break; |
| 4679 | case 5: |
| 4680 | dev_priv->rps.cz_freq = 400; |
| 4681 | dev_priv->mem_freq = 1600; |
| 4682 | break; |
| 4683 | } |
Ville Syrjälä | 80b83b6 | 2014-11-10 22:55:14 +0200 | [diff] [blame] | 4684 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 4685 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4686 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
| 4687 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 4688 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4689 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4690 | dev_priv->rps.max_freq); |
| 4691 | |
| 4692 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); |
| 4693 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4694 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4695 | dev_priv->rps.efficient_freq); |
| 4696 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4697 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
| 4698 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4699 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4700 | dev_priv->rps.rp1_freq); |
| 4701 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4702 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
| 4703 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4704 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4705 | dev_priv->rps.min_freq); |
| 4706 | |
Ville Syrjälä | 1c14762 | 2014-08-18 14:42:43 +0300 | [diff] [blame] | 4707 | WARN_ONCE((dev_priv->rps.max_freq | |
| 4708 | dev_priv->rps.efficient_freq | |
| 4709 | dev_priv->rps.rp1_freq | |
| 4710 | dev_priv->rps.min_freq) & 1, |
| 4711 | "Odd GPU freq values\n"); |
| 4712 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4713 | /* Preserve min/max settings in case of re-init */ |
| 4714 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4715 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4716 | |
| 4717 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 4718 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 4719 | |
| 4720 | mutex_unlock(&dev_priv->rps.hw_lock); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4721 | } |
| 4722 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4723 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
| 4724 | { |
| 4725 | valleyview_cleanup_pctx(dev); |
| 4726 | } |
| 4727 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4728 | static void cherryview_enable_rps(struct drm_device *dev) |
| 4729 | { |
| 4730 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4731 | struct intel_engine_cs *ring; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4732 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4733 | int i; |
| 4734 | |
| 4735 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 4736 | |
| 4737 | gtfifodbg = I915_READ(GTFIFODBG); |
| 4738 | if (gtfifodbg) { |
| 4739 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 4740 | gtfifodbg); |
| 4741 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4742 | } |
| 4743 | |
| 4744 | cherryview_check_pctx(dev_priv); |
| 4745 | |
| 4746 | /* 1a & 1b: Get forcewake during program sequence. Although the driver |
| 4747 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4748 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4749 | |
Ville Syrjälä | 160614a | 2015-01-19 13:50:47 +0200 | [diff] [blame] | 4750 | /* Disable RC states. */ |
| 4751 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4752 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4753 | /* 2a: Program RC6 thresholds.*/ |
| 4754 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 4755 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4756 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4757 | |
| 4758 | for_each_ring(ring, dev_priv, i) |
| 4759 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4760 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 4761 | |
Ville Syrjälä | af5a75a | 2015-01-19 13:50:50 +0200 | [diff] [blame] | 4762 | /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ |
| 4763 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4764 | |
| 4765 | /* allows RC6 residency counter to work */ |
| 4766 | I915_WRITE(VLV_COUNTER_CONTROL, |
| 4767 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
| 4768 | VLV_MEDIA_RC6_COUNT_EN | |
| 4769 | VLV_RENDER_RC6_COUNT_EN)); |
| 4770 | |
| 4771 | /* For now we assume BIOS is allocating and populating the PCBR */ |
| 4772 | pcbr = I915_READ(VLV_PCBR); |
| 4773 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4774 | /* 3: Enable RC6 */ |
| 4775 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && |
| 4776 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) |
Ville Syrjälä | af5a75a | 2015-01-19 13:50:50 +0200 | [diff] [blame] | 4777 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4778 | |
| 4779 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
| 4780 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4781 | /* 4 Program defaults and thresholds for RPS*/ |
Ville Syrjälä | 3cbdb48 | 2015-01-19 13:50:49 +0200 | [diff] [blame] | 4782 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4783 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 4784 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 4785 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 4786 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 4787 | |
| 4788 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 4789 | |
| 4790 | /* 5: Enable RPS */ |
| 4791 | I915_WRITE(GEN6_RP_CONTROL, |
| 4792 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Ville Syrjälä | eb973a5 | 2015-01-21 19:37:59 +0200 | [diff] [blame] | 4793 | GEN6_RP_MEDIA_IS_GFX | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4794 | GEN6_RP_ENABLE | |
| 4795 | GEN6_RP_UP_BUSY_AVG | |
| 4796 | GEN6_RP_DOWN_IDLE_AVG); |
| 4797 | |
| 4798 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 4799 | |
Ville Syrjälä | 8d40c3a | 2014-11-07 21:33:45 +0200 | [diff] [blame] | 4800 | /* RPS code assumes GPLL is used */ |
| 4801 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
| 4802 | |
Ville Syrjälä | c8e9627 | 2014-11-07 21:33:44 +0200 | [diff] [blame] | 4803 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4804 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 4805 | |
| 4806 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
| 4807 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4808 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4809 | dev_priv->rps.cur_freq); |
| 4810 | |
| 4811 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4812 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4813 | dev_priv->rps.efficient_freq); |
| 4814 | |
| 4815 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
| 4816 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4817 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4818 | } |
| 4819 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4820 | static void valleyview_enable_rps(struct drm_device *dev) |
| 4821 | { |
| 4822 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4823 | struct intel_engine_cs *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 4824 | u32 gtfifodbg, val, rc6_mode = 0; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4825 | int i; |
| 4826 | |
| 4827 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 4828 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4829 | valleyview_check_pctx(dev_priv); |
| 4830 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4831 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
Jesse Barnes | f7d85c1 | 2013-09-27 10:40:54 -0700 | [diff] [blame] | 4832 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 4833 | gtfifodbg); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4834 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4835 | } |
| 4836 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4837 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4838 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4839 | |
Ville Syrjälä | 160614a | 2015-01-19 13:50:47 +0200 | [diff] [blame] | 4840 | /* Disable RC states. */ |
| 4841 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4842 | |
Ville Syrjälä | cad725f | 2015-01-19 13:50:48 +0200 | [diff] [blame] | 4843 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4844 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 4845 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 4846 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 4847 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 4848 | |
| 4849 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 4850 | |
| 4851 | I915_WRITE(GEN6_RP_CONTROL, |
| 4852 | GEN6_RP_MEDIA_TURBO | |
| 4853 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 4854 | GEN6_RP_MEDIA_IS_GFX | |
| 4855 | GEN6_RP_ENABLE | |
| 4856 | GEN6_RP_UP_BUSY_AVG | |
| 4857 | GEN6_RP_DOWN_IDLE_CONT); |
| 4858 | |
| 4859 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
| 4860 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 4861 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 4862 | |
| 4863 | for_each_ring(ring, dev_priv, i) |
| 4864 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4865 | |
Jesse Barnes | 2f0aa304 | 2013-11-15 09:32:11 -0800 | [diff] [blame] | 4866 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4867 | |
| 4868 | /* allows RC6 residency counter to work */ |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 4869 | I915_WRITE(VLV_COUNTER_CONTROL, |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4870 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
| 4871 | VLV_RENDER_RC0_COUNT_EN | |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 4872 | VLV_MEDIA_RC6_COUNT_EN | |
| 4873 | VLV_RENDER_RC6_COUNT_EN)); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4874 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 4875 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
Jesse Barnes | 6b88f29 | 2013-11-15 09:32:12 -0800 | [diff] [blame] | 4876 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4877 | |
| 4878 | intel_print_rc6_info(dev, rc6_mode); |
| 4879 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 4880 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4881 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4882 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4883 | |
Ville Syrjälä | 8d40c3a | 2014-11-07 21:33:45 +0200 | [diff] [blame] | 4884 | /* RPS code assumes GPLL is used */ |
| 4885 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
| 4886 | |
Ville Syrjälä | c8e9627 | 2014-11-07 21:33:44 +0200 | [diff] [blame] | 4887 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4888 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 4889 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4890 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 4891 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4892 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4893 | dev_priv->rps.cur_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4894 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 4895 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4896 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4897 | dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4898 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4899 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4900 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4901 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4902 | } |
| 4903 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4904 | void ironlake_teardown_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4905 | { |
| 4906 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4907 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4908 | if (dev_priv->ips.renderctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4909 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4910 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
| 4911 | dev_priv->ips.renderctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4912 | } |
| 4913 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4914 | if (dev_priv->ips.pwrctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4915 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4916 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
| 4917 | dev_priv->ips.pwrctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4918 | } |
| 4919 | } |
| 4920 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4921 | static void ironlake_disable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4922 | { |
| 4923 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4924 | |
| 4925 | if (I915_READ(PWRCTXA)) { |
| 4926 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 4927 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 4928 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 4929 | 50); |
| 4930 | |
| 4931 | I915_WRITE(PWRCTXA, 0); |
| 4932 | POSTING_READ(PWRCTXA); |
| 4933 | |
| 4934 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 4935 | POSTING_READ(RSTDBYCTL); |
| 4936 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4937 | } |
| 4938 | |
| 4939 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 4940 | { |
| 4941 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4942 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4943 | if (dev_priv->ips.renderctx == NULL) |
| 4944 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
| 4945 | if (!dev_priv->ips.renderctx) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4946 | return -ENOMEM; |
| 4947 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4948 | if (dev_priv->ips.pwrctx == NULL) |
| 4949 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
| 4950 | if (!dev_priv->ips.pwrctx) { |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4951 | ironlake_teardown_rc6(dev); |
| 4952 | return -ENOMEM; |
| 4953 | } |
| 4954 | |
| 4955 | return 0; |
| 4956 | } |
| 4957 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4958 | static void ironlake_enable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4959 | { |
| 4960 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4961 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4962 | bool was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4963 | int ret; |
| 4964 | |
| 4965 | /* rc6 disabled by default due to repeated reports of hanging during |
| 4966 | * boot and resume. |
| 4967 | */ |
| 4968 | if (!intel_enable_rc6(dev)) |
| 4969 | return; |
| 4970 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4971 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4972 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4973 | ret = ironlake_setup_rc6(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4974 | if (ret) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4975 | return; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4976 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4977 | was_interruptible = dev_priv->mm.interruptible; |
| 4978 | dev_priv->mm.interruptible = false; |
| 4979 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4980 | /* |
| 4981 | * GPU can automatically power down the render unit if given a page |
| 4982 | * to save state. |
| 4983 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4984 | ret = intel_ring_begin(ring, 6); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4985 | if (ret) { |
| 4986 | ironlake_teardown_rc6(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4987 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4988 | return; |
| 4989 | } |
| 4990 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4991 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 4992 | intel_ring_emit(ring, MI_SET_CONTEXT); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4993 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4994 | MI_MM_SPACE_GTT | |
| 4995 | MI_SAVE_EXT_STATE_EN | |
| 4996 | MI_RESTORE_EXT_STATE_EN | |
| 4997 | MI_RESTORE_INHIBIT); |
| 4998 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
| 4999 | intel_ring_emit(ring, MI_NOOP); |
| 5000 | intel_ring_emit(ring, MI_FLUSH); |
| 5001 | intel_ring_advance(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5002 | |
| 5003 | /* |
| 5004 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 5005 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 5006 | * safe to assume that renderctx is valid |
| 5007 | */ |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 5008 | ret = intel_ring_idle(ring); |
| 5009 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5010 | if (ret) { |
Jani Nikula | def27a5 | 2013-03-12 10:49:19 +0200 | [diff] [blame] | 5011 | DRM_ERROR("failed to enable ironlake power savings\n"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5012 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5013 | return; |
| 5014 | } |
| 5015 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 5016 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5017 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 5018 | |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 5019 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5020 | } |
| 5021 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 5022 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 5023 | { |
| 5024 | unsigned long freq; |
| 5025 | int div = (vidfreq & 0x3f0000) >> 16; |
| 5026 | int post = (vidfreq & 0x3000) >> 12; |
| 5027 | int pre = (vidfreq & 0x7); |
| 5028 | |
| 5029 | if (!pre) |
| 5030 | return 0; |
| 5031 | |
| 5032 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 5033 | |
| 5034 | return freq; |
| 5035 | } |
| 5036 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5037 | static const struct cparams { |
| 5038 | u16 i; |
| 5039 | u16 t; |
| 5040 | u16 m; |
| 5041 | u16 c; |
| 5042 | } cparams[] = { |
| 5043 | { 1, 1333, 301, 28664 }, |
| 5044 | { 1, 1066, 294, 24460 }, |
| 5045 | { 1, 800, 294, 25192 }, |
| 5046 | { 0, 1333, 276, 27605 }, |
| 5047 | { 0, 1066, 276, 27605 }, |
| 5048 | { 0, 800, 231, 23784 }, |
| 5049 | }; |
| 5050 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5051 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5052 | { |
| 5053 | u64 total_count, diff, ret; |
| 5054 | u32 count1, count2, count3, m = 0, c = 0; |
| 5055 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 5056 | int i; |
| 5057 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5058 | assert_spin_locked(&mchdev_lock); |
| 5059 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5060 | diff1 = now - dev_priv->ips.last_time1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5061 | |
| 5062 | /* Prevent division-by-zero if we are asking too fast. |
| 5063 | * Also, we don't get interesting results if we are polling |
| 5064 | * faster than once in 10ms, so just return the saved value |
| 5065 | * in such cases. |
| 5066 | */ |
| 5067 | if (diff1 <= 10) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5068 | return dev_priv->ips.chipset_power; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5069 | |
| 5070 | count1 = I915_READ(DMIEC); |
| 5071 | count2 = I915_READ(DDREC); |
| 5072 | count3 = I915_READ(CSIEC); |
| 5073 | |
| 5074 | total_count = count1 + count2 + count3; |
| 5075 | |
| 5076 | /* FIXME: handle per-counter overflow */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5077 | if (total_count < dev_priv->ips.last_count1) { |
| 5078 | diff = ~0UL - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5079 | diff += total_count; |
| 5080 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5081 | diff = total_count - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5082 | } |
| 5083 | |
| 5084 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5085 | if (cparams[i].i == dev_priv->ips.c_m && |
| 5086 | cparams[i].t == dev_priv->ips.r_t) { |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5087 | m = cparams[i].m; |
| 5088 | c = cparams[i].c; |
| 5089 | break; |
| 5090 | } |
| 5091 | } |
| 5092 | |
| 5093 | diff = div_u64(diff, diff1); |
| 5094 | ret = ((m * diff) + c); |
| 5095 | ret = div_u64(ret, 10); |
| 5096 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5097 | dev_priv->ips.last_count1 = total_count; |
| 5098 | dev_priv->ips.last_time1 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5099 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5100 | dev_priv->ips.chipset_power = ret; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5101 | |
| 5102 | return ret; |
| 5103 | } |
| 5104 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5105 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 5106 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5107 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5108 | unsigned long val; |
| 5109 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5110 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5111 | return 0; |
| 5112 | |
| 5113 | spin_lock_irq(&mchdev_lock); |
| 5114 | |
| 5115 | val = __i915_chipset_val(dev_priv); |
| 5116 | |
| 5117 | spin_unlock_irq(&mchdev_lock); |
| 5118 | |
| 5119 | return val; |
| 5120 | } |
| 5121 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5122 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 5123 | { |
| 5124 | unsigned long m, x, b; |
| 5125 | u32 tsfs; |
| 5126 | |
| 5127 | tsfs = I915_READ(TSFS); |
| 5128 | |
| 5129 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 5130 | x = I915_READ8(TR1); |
| 5131 | |
| 5132 | b = tsfs & TSFS_INTR_MASK; |
| 5133 | |
| 5134 | return ((m * x) / 127) - b; |
| 5135 | } |
| 5136 | |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5137 | static int _pxvid_to_vd(u8 pxvid) |
| 5138 | { |
| 5139 | if (pxvid == 0) |
| 5140 | return 0; |
| 5141 | |
| 5142 | if (pxvid >= 8 && pxvid < 31) |
| 5143 | pxvid = 31; |
| 5144 | |
| 5145 | return (pxvid + 2) * 125; |
| 5146 | } |
| 5147 | |
| 5148 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5149 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5150 | struct drm_device *dev = dev_priv->dev; |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5151 | const int vd = _pxvid_to_vd(pxvid); |
| 5152 | const int vm = vd - 1125; |
| 5153 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5154 | if (INTEL_INFO(dev)->is_mobile) |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5155 | return vm > 0 ? vm : 0; |
| 5156 | |
| 5157 | return vd; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5158 | } |
| 5159 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5160 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5161 | { |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 5162 | u64 now, diff, diffms; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5163 | u32 count; |
| 5164 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5165 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5166 | |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 5167 | now = ktime_get_raw_ns(); |
| 5168 | diffms = now - dev_priv->ips.last_time2; |
| 5169 | do_div(diffms, NSEC_PER_MSEC); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5170 | |
| 5171 | /* Don't divide by 0 */ |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5172 | if (!diffms) |
| 5173 | return; |
| 5174 | |
| 5175 | count = I915_READ(GFXEC); |
| 5176 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5177 | if (count < dev_priv->ips.last_count2) { |
| 5178 | diff = ~0UL - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5179 | diff += count; |
| 5180 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5181 | diff = count - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5182 | } |
| 5183 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5184 | dev_priv->ips.last_count2 = count; |
| 5185 | dev_priv->ips.last_time2 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5186 | |
| 5187 | /* More magic constants... */ |
| 5188 | diff = diff * 1181; |
| 5189 | diff = div_u64(diff, diffms * 10); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5190 | dev_priv->ips.gfx_power = diff; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5191 | } |
| 5192 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5193 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 5194 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5195 | struct drm_device *dev = dev_priv->dev; |
| 5196 | |
| 5197 | if (INTEL_INFO(dev)->gen != 5) |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5198 | return; |
| 5199 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5200 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5201 | |
| 5202 | __i915_update_gfx_val(dev_priv); |
| 5203 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5204 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5205 | } |
| 5206 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5207 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5208 | { |
| 5209 | unsigned long t, corr, state1, corr2, state2; |
| 5210 | u32 pxvid, ext_v; |
| 5211 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5212 | assert_spin_locked(&mchdev_lock); |
| 5213 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5214 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5215 | pxvid = (pxvid >> 24) & 0x7f; |
| 5216 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 5217 | |
| 5218 | state1 = ext_v; |
| 5219 | |
| 5220 | t = i915_mch_val(dev_priv); |
| 5221 | |
| 5222 | /* Revel in the empirically derived constants */ |
| 5223 | |
| 5224 | /* Correction factor in 1/100000 units */ |
| 5225 | if (t > 80) |
| 5226 | corr = ((t * 2349) + 135940); |
| 5227 | else if (t >= 50) |
| 5228 | corr = ((t * 964) + 29317); |
| 5229 | else /* < 50 */ |
| 5230 | corr = ((t * 301) + 1004); |
| 5231 | |
| 5232 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 5233 | corr /= 100000; |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5234 | corr2 = (corr * dev_priv->ips.corr); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5235 | |
| 5236 | state2 = (corr2 * state1) / 10000; |
| 5237 | state2 /= 100; /* convert to mW */ |
| 5238 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5239 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5240 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5241 | return dev_priv->ips.gfx_power + state2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5242 | } |
| 5243 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5244 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 5245 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5246 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5247 | unsigned long val; |
| 5248 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5249 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5250 | return 0; |
| 5251 | |
| 5252 | spin_lock_irq(&mchdev_lock); |
| 5253 | |
| 5254 | val = __i915_gfx_val(dev_priv); |
| 5255 | |
| 5256 | spin_unlock_irq(&mchdev_lock); |
| 5257 | |
| 5258 | return val; |
| 5259 | } |
| 5260 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5261 | /** |
| 5262 | * i915_read_mch_val - return value for IPS use |
| 5263 | * |
| 5264 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 5265 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 5266 | */ |
| 5267 | unsigned long i915_read_mch_val(void) |
| 5268 | { |
| 5269 | struct drm_i915_private *dev_priv; |
| 5270 | unsigned long chipset_val, graphics_val, ret = 0; |
| 5271 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5272 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5273 | if (!i915_mch_dev) |
| 5274 | goto out_unlock; |
| 5275 | dev_priv = i915_mch_dev; |
| 5276 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5277 | chipset_val = __i915_chipset_val(dev_priv); |
| 5278 | graphics_val = __i915_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5279 | |
| 5280 | ret = chipset_val + graphics_val; |
| 5281 | |
| 5282 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5283 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5284 | |
| 5285 | return ret; |
| 5286 | } |
| 5287 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 5288 | |
| 5289 | /** |
| 5290 | * i915_gpu_raise - raise GPU frequency limit |
| 5291 | * |
| 5292 | * Raise the limit; IPS indicates we have thermal headroom. |
| 5293 | */ |
| 5294 | bool i915_gpu_raise(void) |
| 5295 | { |
| 5296 | struct drm_i915_private *dev_priv; |
| 5297 | bool ret = true; |
| 5298 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5299 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5300 | if (!i915_mch_dev) { |
| 5301 | ret = false; |
| 5302 | goto out_unlock; |
| 5303 | } |
| 5304 | dev_priv = i915_mch_dev; |
| 5305 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5306 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
| 5307 | dev_priv->ips.max_delay--; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5308 | |
| 5309 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5310 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5311 | |
| 5312 | return ret; |
| 5313 | } |
| 5314 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 5315 | |
| 5316 | /** |
| 5317 | * i915_gpu_lower - lower GPU frequency limit |
| 5318 | * |
| 5319 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 5320 | * frequency maximum. |
| 5321 | */ |
| 5322 | bool i915_gpu_lower(void) |
| 5323 | { |
| 5324 | struct drm_i915_private *dev_priv; |
| 5325 | bool ret = true; |
| 5326 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5327 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5328 | if (!i915_mch_dev) { |
| 5329 | ret = false; |
| 5330 | goto out_unlock; |
| 5331 | } |
| 5332 | dev_priv = i915_mch_dev; |
| 5333 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5334 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
| 5335 | dev_priv->ips.max_delay++; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5336 | |
| 5337 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5338 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5339 | |
| 5340 | return ret; |
| 5341 | } |
| 5342 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 5343 | |
| 5344 | /** |
| 5345 | * i915_gpu_busy - indicate GPU business to IPS |
| 5346 | * |
| 5347 | * Tell the IPS driver whether or not the GPU is busy. |
| 5348 | */ |
| 5349 | bool i915_gpu_busy(void) |
| 5350 | { |
| 5351 | struct drm_i915_private *dev_priv; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 5352 | struct intel_engine_cs *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5353 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 5354 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5355 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5356 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5357 | if (!i915_mch_dev) |
| 5358 | goto out_unlock; |
| 5359 | dev_priv = i915_mch_dev; |
| 5360 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 5361 | for_each_ring(ring, dev_priv, i) |
| 5362 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5363 | |
| 5364 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5365 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5366 | |
| 5367 | return ret; |
| 5368 | } |
| 5369 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 5370 | |
| 5371 | /** |
| 5372 | * i915_gpu_turbo_disable - disable graphics turbo |
| 5373 | * |
| 5374 | * Disable graphics turbo by resetting the max frequency and setting the |
| 5375 | * current frequency to the default. |
| 5376 | */ |
| 5377 | bool i915_gpu_turbo_disable(void) |
| 5378 | { |
| 5379 | struct drm_i915_private *dev_priv; |
| 5380 | bool ret = true; |
| 5381 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5382 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5383 | if (!i915_mch_dev) { |
| 5384 | ret = false; |
| 5385 | goto out_unlock; |
| 5386 | } |
| 5387 | dev_priv = i915_mch_dev; |
| 5388 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5389 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5390 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5391 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5392 | ret = false; |
| 5393 | |
| 5394 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5395 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5396 | |
| 5397 | return ret; |
| 5398 | } |
| 5399 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 5400 | |
| 5401 | /** |
| 5402 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 5403 | * IPS got loaded first. |
| 5404 | * |
| 5405 | * This awkward dance is so that neither module has to depend on the |
| 5406 | * other in order for IPS to do the appropriate communication of |
| 5407 | * GPU turbo limits to i915. |
| 5408 | */ |
| 5409 | static void |
| 5410 | ips_ping_for_i915_load(void) |
| 5411 | { |
| 5412 | void (*link)(void); |
| 5413 | |
| 5414 | link = symbol_get(ips_link_to_i915_driver); |
| 5415 | if (link) { |
| 5416 | link(); |
| 5417 | symbol_put(ips_link_to_i915_driver); |
| 5418 | } |
| 5419 | } |
| 5420 | |
| 5421 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 5422 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5423 | /* We only register the i915 ips part with intel-ips once everything is |
| 5424 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5425 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5426 | i915_mch_dev = dev_priv; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5427 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5428 | |
| 5429 | ips_ping_for_i915_load(); |
| 5430 | } |
| 5431 | |
| 5432 | void intel_gpu_ips_teardown(void) |
| 5433 | { |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5434 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5435 | i915_mch_dev = NULL; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5436 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5437 | } |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 5438 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5439 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 5440 | { |
| 5441 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5442 | u32 lcfuse; |
| 5443 | u8 pxw[16]; |
| 5444 | int i; |
| 5445 | |
| 5446 | /* Disable to program */ |
| 5447 | I915_WRITE(ECR, 0); |
| 5448 | POSTING_READ(ECR); |
| 5449 | |
| 5450 | /* Program energy weights for various events */ |
| 5451 | I915_WRITE(SDEW, 0x15040d00); |
| 5452 | I915_WRITE(CSIEW0, 0x007f0000); |
| 5453 | I915_WRITE(CSIEW1, 0x1e220004); |
| 5454 | I915_WRITE(CSIEW2, 0x04000004); |
| 5455 | |
| 5456 | for (i = 0; i < 5; i++) |
| 5457 | I915_WRITE(PEW + (i * 4), 0); |
| 5458 | for (i = 0; i < 3; i++) |
| 5459 | I915_WRITE(DEW + (i * 4), 0); |
| 5460 | |
| 5461 | /* Program P-state weights to account for frequency power adjustment */ |
| 5462 | for (i = 0; i < 16; i++) { |
| 5463 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 5464 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 5465 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 5466 | PXVFREQ_PX_SHIFT; |
| 5467 | unsigned long val; |
| 5468 | |
| 5469 | val = vid * vid; |
| 5470 | val *= (freq / 1000); |
| 5471 | val *= 255; |
| 5472 | val /= (127*127*900); |
| 5473 | if (val > 0xff) |
| 5474 | DRM_ERROR("bad pxval: %ld\n", val); |
| 5475 | pxw[i] = val; |
| 5476 | } |
| 5477 | /* Render standby states get 0 weight */ |
| 5478 | pxw[14] = 0; |
| 5479 | pxw[15] = 0; |
| 5480 | |
| 5481 | for (i = 0; i < 4; i++) { |
| 5482 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 5483 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 5484 | I915_WRITE(PXW + (i * 4), val); |
| 5485 | } |
| 5486 | |
| 5487 | /* Adjust magic regs to magic values (more experimental results) */ |
| 5488 | I915_WRITE(OGW0, 0); |
| 5489 | I915_WRITE(OGW1, 0); |
| 5490 | I915_WRITE(EG0, 0x00007f00); |
| 5491 | I915_WRITE(EG1, 0x0000000e); |
| 5492 | I915_WRITE(EG2, 0x000e0000); |
| 5493 | I915_WRITE(EG3, 0x68000300); |
| 5494 | I915_WRITE(EG4, 0x42000000); |
| 5495 | I915_WRITE(EG5, 0x00140031); |
| 5496 | I915_WRITE(EG6, 0); |
| 5497 | I915_WRITE(EG7, 0); |
| 5498 | |
| 5499 | for (i = 0; i < 8; i++) |
| 5500 | I915_WRITE(PXWL + (i * 4), 0); |
| 5501 | |
| 5502 | /* Enable PMON + select events */ |
| 5503 | I915_WRITE(ECR, 0x80000019); |
| 5504 | |
| 5505 | lcfuse = I915_READ(LCFUSE02); |
| 5506 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5507 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 5508 | } |
| 5509 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5510 | void intel_init_gt_powersave(struct drm_device *dev) |
| 5511 | { |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 5512 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
| 5513 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5514 | if (IS_CHERRYVIEW(dev)) |
| 5515 | cherryview_init_gt_powersave(dev); |
| 5516 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5517 | valleyview_init_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5518 | } |
| 5519 | |
| 5520 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
| 5521 | { |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5522 | if (IS_CHERRYVIEW(dev)) |
| 5523 | return; |
| 5524 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5525 | valleyview_cleanup_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5526 | } |
| 5527 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 5528 | static void gen6_suspend_rps(struct drm_device *dev) |
| 5529 | { |
| 5530 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5531 | |
| 5532 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 5533 | |
| 5534 | /* |
| 5535 | * TODO: disable RPS interrupts on GEN9+ too once RPS support |
| 5536 | * is added for it. |
| 5537 | */ |
| 5538 | if (INTEL_INFO(dev)->gen < 9) |
| 5539 | gen6_disable_rps_interrupts(dev); |
| 5540 | } |
| 5541 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 5542 | /** |
| 5543 | * intel_suspend_gt_powersave - suspend PM work and helper threads |
| 5544 | * @dev: drm device |
| 5545 | * |
| 5546 | * We don't want to disable RC6 or other features here, we just want |
| 5547 | * to make sure any work we've queued has finished and won't bother |
| 5548 | * us while we're suspended. |
| 5549 | */ |
| 5550 | void intel_suspend_gt_powersave(struct drm_device *dev) |
| 5551 | { |
| 5552 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5553 | |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 5554 | if (INTEL_INFO(dev)->gen < 6) |
| 5555 | return; |
| 5556 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 5557 | gen6_suspend_rps(dev); |
Deepak S | b47adc1 | 2014-06-20 20:03:02 +0530 | [diff] [blame] | 5558 | |
| 5559 | /* Force GPU to min freq during suspend */ |
| 5560 | gen6_rps_idle(dev_priv); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 5561 | } |
| 5562 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5563 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 5564 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5565 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5566 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5567 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5568 | ironlake_disable_drps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5569 | ironlake_disable_rc6(dev); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5570 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 10d8d36 | 2014-06-12 17:48:52 +0200 | [diff] [blame] | 5571 | intel_suspend_gt_powersave(dev); |
Imre Deak | e494837 | 2014-05-12 18:35:04 +0300 | [diff] [blame] | 5572 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5573 | mutex_lock(&dev_priv->rps.hw_lock); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 5574 | if (INTEL_INFO(dev)->gen >= 9) |
| 5575 | gen9_disable_rps(dev); |
| 5576 | else if (IS_CHERRYVIEW(dev)) |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5577 | cherryview_disable_rps(dev); |
| 5578 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 5579 | valleyview_disable_rps(dev); |
| 5580 | else |
| 5581 | gen6_disable_rps(dev); |
Imre Deak | e534770 | 2014-11-19 15:30:02 +0200 | [diff] [blame] | 5582 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 5583 | dev_priv->rps.enabled = false; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5584 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5585 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5586 | } |
| 5587 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5588 | static void intel_gen6_powersave_work(struct work_struct *work) |
| 5589 | { |
| 5590 | struct drm_i915_private *dev_priv = |
| 5591 | container_of(work, struct drm_i915_private, |
| 5592 | rps.delayed_resume_work.work); |
| 5593 | struct drm_device *dev = dev_priv->dev; |
| 5594 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5595 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5596 | |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 5597 | /* |
| 5598 | * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is |
| 5599 | * added for it. |
| 5600 | */ |
| 5601 | if (INTEL_INFO(dev)->gen < 9) |
| 5602 | gen6_reset_rps_interrupts(dev); |
| 5603 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5604 | if (IS_CHERRYVIEW(dev)) { |
| 5605 | cherryview_enable_rps(dev); |
| 5606 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5607 | valleyview_enable_rps(dev); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 5608 | } else if (INTEL_INFO(dev)->gen >= 9) { |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 5609 | gen9_enable_rc6(dev); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 5610 | gen9_enable_rps(dev); |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 5611 | __gen6_update_ring_freq(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 5612 | } else if (IS_BROADWELL(dev)) { |
| 5613 | gen8_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5614 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5615 | } else { |
| 5616 | gen6_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5617 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5618 | } |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 5619 | dev_priv->rps.enabled = true; |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 5620 | |
| 5621 | if (INTEL_INFO(dev)->gen < 9) |
| 5622 | gen6_enable_rps_interrupts(dev); |
| 5623 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5624 | mutex_unlock(&dev_priv->rps.hw_lock); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5625 | |
| 5626 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5627 | } |
| 5628 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5629 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 5630 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5631 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5632 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5633 | if (IS_IRONLAKE_M(dev)) { |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 5634 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5635 | ironlake_enable_drps(dev); |
| 5636 | ironlake_enable_rc6(dev); |
| 5637 | intel_init_emon(dev); |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 5638 | mutex_unlock(&dev->struct_mutex); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5639 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5640 | /* |
| 5641 | * PCU communication is slow and this doesn't need to be |
| 5642 | * done at any specific time, so do this out of our fast path |
| 5643 | * to make resume and init faster. |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5644 | * |
| 5645 | * We depend on the HW RC6 power context save/restore |
| 5646 | * mechanism when entering D3 through runtime PM suspend. So |
| 5647 | * disable RPM until RPS/RC6 is properly setup. We can only |
| 5648 | * get here via the driver load/system resume/runtime resume |
| 5649 | * paths, so the _noresume version is enough (and in case of |
| 5650 | * runtime resume it's necessary). |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5651 | */ |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5652 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
| 5653 | round_jiffies_up_relative(HZ))) |
| 5654 | intel_runtime_pm_get_noresume(dev_priv); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5655 | } |
| 5656 | } |
| 5657 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5658 | void intel_reset_gt_powersave(struct drm_device *dev) |
| 5659 | { |
| 5660 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5661 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 5662 | if (INTEL_INFO(dev)->gen < 6) |
| 5663 | return; |
| 5664 | |
| 5665 | gen6_suspend_rps(dev); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5666 | dev_priv->rps.enabled = false; |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5667 | } |
| 5668 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5669 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 5670 | { |
| 5671 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5672 | |
| 5673 | /* |
| 5674 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 5675 | * gating for the panel power sequencer or it will fail to |
| 5676 | * start up when no ports are active. |
| 5677 | */ |
| 5678 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 5679 | } |
| 5680 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5681 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
| 5682 | { |
| 5683 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5684 | int pipe; |
| 5685 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 5686 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5687 | I915_WRITE(DSPCNTR(pipe), |
| 5688 | I915_READ(DSPCNTR(pipe)) | |
| 5689 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 5690 | intel_flush_primary_plane(dev_priv, pipe); |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5691 | } |
| 5692 | } |
| 5693 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5694 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
| 5695 | { |
| 5696 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5697 | |
| 5698 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
| 5699 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
| 5700 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
| 5701 | |
| 5702 | /* |
| 5703 | * Don't touch WM1S_LP_EN here. |
| 5704 | * Doing so could cause underruns. |
| 5705 | */ |
| 5706 | } |
| 5707 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5708 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5709 | { |
| 5710 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5711 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5712 | |
Damien Lespiau | f1e8fa5 | 2013-06-07 17:41:09 +0100 | [diff] [blame] | 5713 | /* |
| 5714 | * Required for FBC |
| 5715 | * WaFbcDisableDpfcClockGating:ilk |
| 5716 | */ |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5717 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 5718 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
| 5719 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5720 | |
| 5721 | I915_WRITE(PCH_3DCGDIS0, |
| 5722 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 5723 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 5724 | I915_WRITE(PCH_3DCGDIS1, |
| 5725 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 5726 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5727 | /* |
| 5728 | * According to the spec the following bits should be set in |
| 5729 | * order to enable memory self-refresh |
| 5730 | * The bit 22/21 of 0x42004 |
| 5731 | * The bit 5 of 0x42020 |
| 5732 | * The bit 15 of 0x45000 |
| 5733 | */ |
| 5734 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5735 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5736 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5737 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5738 | I915_WRITE(DISP_ARB_CTL, |
| 5739 | (I915_READ(DISP_ARB_CTL) | |
| 5740 | DISP_FBC_WM_DIS)); |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5741 | |
| 5742 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5743 | |
| 5744 | /* |
| 5745 | * Based on the document from hardware guys the following bits |
| 5746 | * should be set unconditionally in order to enable FBC. |
| 5747 | * The bit 22 of 0x42000 |
| 5748 | * The bit 22 of 0x42004 |
| 5749 | * The bit 7,8,9 of 0x42020. |
| 5750 | */ |
| 5751 | if (IS_IRONLAKE_M(dev)) { |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 5752 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5753 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5754 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5755 | ILK_FBCQ_DIS); |
| 5756 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5757 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5758 | ILK_DPARB_GATE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5759 | } |
| 5760 | |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5761 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
| 5762 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5763 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5764 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5765 | ILK_ELPIN_409_SELECT); |
| 5766 | I915_WRITE(_3D_CHICKEN2, |
| 5767 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 5768 | _3D_CHICKEN2_WM_READ_PIPELINED); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5769 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5770 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5771 | I915_WRITE(CACHE_MODE_0, |
| 5772 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5773 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5774 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
| 5775 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5776 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5777 | g4x_disable_trickle_feed(dev); |
Ville Syrjälä | bdad2b2 | 2013-06-07 10:47:03 +0300 | [diff] [blame] | 5778 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5779 | ibx_init_clock_gating(dev); |
| 5780 | } |
| 5781 | |
| 5782 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 5783 | { |
| 5784 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5785 | int pipe; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5786 | uint32_t val; |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5787 | |
| 5788 | /* |
| 5789 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 5790 | * gating for the panel power sequencer or it will fail to |
| 5791 | * start up when no ports are active. |
| 5792 | */ |
Jesse Barnes | cd66407 | 2013-10-02 10:34:19 -0700 | [diff] [blame] | 5793 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
| 5794 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
| 5795 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5796 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 5797 | DPLS_EDP_PPS_FIX_DIS); |
Takashi Iwai | 335c07b | 2012-12-11 11:46:29 +0100 | [diff] [blame] | 5798 | /* The below fixes the weird display corruption, a few pixels shifted |
| 5799 | * downward, on (only) LVDS of some HP laptops with IVY. |
| 5800 | */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 5801 | for_each_pipe(dev_priv, pipe) { |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 5802 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
| 5803 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 5804 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5805 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5806 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 5807 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
| 5808 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
| 5809 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5810 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
| 5811 | } |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5812 | /* WADP0ClockGatingDisable */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 5813 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5814 | I915_WRITE(TRANS_CHICKEN1(pipe), |
| 5815 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
| 5816 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5817 | } |
| 5818 | |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5819 | static void gen6_check_mch_setup(struct drm_device *dev) |
| 5820 | { |
| 5821 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5822 | uint32_t tmp; |
| 5823 | |
| 5824 | tmp = I915_READ(MCH_SSKPD); |
Daniel Vetter | df662a2 | 2014-08-04 11:17:25 +0200 | [diff] [blame] | 5825 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
| 5826 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", |
| 5827 | tmp); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5828 | } |
| 5829 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5830 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5831 | { |
| 5832 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5833 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5834 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5835 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5836 | |
| 5837 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5838 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5839 | ILK_ELPIN_409_SELECT); |
| 5840 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5841 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
Daniel Vetter | 4283908 | 2012-12-14 23:38:28 +0100 | [diff] [blame] | 5842 | I915_WRITE(_3D_CHICKEN, |
| 5843 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
| 5844 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5845 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
| 5846 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5847 | |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 5848 | /* |
| 5849 | * BSpec recoomends 8x4 when MSAA is used, |
| 5850 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5851 | * |
| 5852 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5853 | * disable bit, which we don't touch here, but it's good |
| 5854 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 5855 | */ |
| 5856 | I915_WRITE(GEN6_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 5857 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 5858 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5859 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5860 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5861 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 5862 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5863 | |
| 5864 | I915_WRITE(GEN6_UCGCTL1, |
| 5865 | I915_READ(GEN6_UCGCTL1) | |
| 5866 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 5867 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 5868 | |
| 5869 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 5870 | * gating disable must be set. Failure to set it results in |
| 5871 | * flickering pixels due to Z write ordering failures after |
| 5872 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 5873 | * Sanctuary and Tropics, and apparently anything else with |
| 5874 | * alpha test or pixel discard. |
| 5875 | * |
| 5876 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 5877 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5878 | * |
Ville Syrjälä | ef59318 | 2014-01-22 21:32:47 +0200 | [diff] [blame] | 5879 | * WaDisableRCCUnitClockGating:snb |
| 5880 | * WaDisableRCPBUnitClockGating:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5881 | */ |
| 5882 | I915_WRITE(GEN6_UCGCTL2, |
| 5883 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 5884 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 5885 | |
Ville Syrjälä | 5eb146d | 2014-02-04 21:59:16 +0200 | [diff] [blame] | 5886 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
Ville Syrjälä | 743b57d | 2014-02-04 21:59:17 +0200 | [diff] [blame] | 5887 | I915_WRITE(_3D_CHICKEN3, |
| 5888 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5889 | |
| 5890 | /* |
Ville Syrjälä | e927ecd | 2014-02-04 21:59:18 +0200 | [diff] [blame] | 5891 | * Bspec says: |
| 5892 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
| 5893 | * 3DSTATE_SF number of SF output attributes is more than 16." |
| 5894 | */ |
| 5895 | I915_WRITE(_3D_CHICKEN3, |
| 5896 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
| 5897 | |
| 5898 | /* |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5899 | * According to the spec the following bits should be |
| 5900 | * set in order to enable memory self-refresh and fbc: |
| 5901 | * The bit21 and bit22 of 0x42000 |
| 5902 | * The bit21 and bit22 of 0x42004 |
| 5903 | * The bit5 and bit7 of 0x42020 |
| 5904 | * The bit14 of 0x70180 |
| 5905 | * The bit14 of 0x71180 |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 5906 | * |
| 5907 | * WaFbcAsynchFlipDisableFbcQueue:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5908 | */ |
| 5909 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5910 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5911 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 5912 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5913 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5914 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5915 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 5916 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 5917 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
| 5918 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5919 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5920 | g4x_disable_trickle_feed(dev); |
Ben Widawsky | f8f2ac9 | 2012-10-03 19:34:24 -0700 | [diff] [blame] | 5921 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5922 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5923 | |
| 5924 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5925 | } |
| 5926 | |
| 5927 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 5928 | { |
| 5929 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 5930 | |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 5931 | /* |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 5932 | * WaVSThreadDispatchOverride:ivb,vlv |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 5933 | * |
| 5934 | * This actually overrides the dispatch |
| 5935 | * mode for all thread types. |
| 5936 | */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5937 | reg &= ~GEN7_FF_SCHED_MASK; |
| 5938 | reg |= GEN7_FF_TS_SCHED_HW; |
| 5939 | reg |= GEN7_FF_VS_SCHED_HW; |
| 5940 | reg |= GEN7_FF_DS_SCHED_HW; |
| 5941 | |
| 5942 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 5943 | } |
| 5944 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5945 | static void lpt_init_clock_gating(struct drm_device *dev) |
| 5946 | { |
| 5947 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5948 | |
| 5949 | /* |
| 5950 | * TODO: this bit should only be enabled when really needed, then |
| 5951 | * disabled when not needed anymore in order to save power. |
| 5952 | */ |
| 5953 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
| 5954 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
| 5955 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
| 5956 | PCH_LP_PARTITION_LEVEL_DISABLE); |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 5957 | |
| 5958 | /* WADPOClockGatingDisable:hsw */ |
| 5959 | I915_WRITE(_TRANSA_CHICKEN1, |
| 5960 | I915_READ(_TRANSA_CHICKEN1) | |
| 5961 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5962 | } |
| 5963 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 5964 | static void lpt_suspend_hw(struct drm_device *dev) |
| 5965 | { |
| 5966 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5967 | |
| 5968 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 5969 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 5970 | |
| 5971 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 5972 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 5973 | } |
| 5974 | } |
| 5975 | |
Paulo Zanoni | 47c2bd9 | 2014-08-21 17:09:37 -0300 | [diff] [blame] | 5976 | static void broadwell_init_clock_gating(struct drm_device *dev) |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5977 | { |
| 5978 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5979 | enum pipe pipe; |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5980 | |
| 5981 | I915_WRITE(WM3_LP_ILK, 0); |
| 5982 | I915_WRITE(WM2_LP_ILK, 0); |
| 5983 | I915_WRITE(WM1_LP_ILK, 0); |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5984 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5985 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5986 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5987 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5988 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5989 | I915_WRITE(CHICKEN_PAR1_1, |
| 5990 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
| 5991 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5992 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 5993 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5994 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
Ville Syrjälä | c7c6562 | 2014-03-05 13:05:45 +0200 | [diff] [blame] | 5995 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 5996 | BDW_DPRS_MASK_VBLANK_SRD); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5997 | } |
Ben Widawsky | 63801f2 | 2013-12-12 17:26:03 -0800 | [diff] [blame] | 5998 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5999 | /* WaVSRefCountFullforceMissDisable:bdw */ |
| 6000 | /* WaDSRefCountFullforceMissDisable:bdw */ |
| 6001 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6002 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 6003 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 6004 | |
Ville Syrjälä | 295e8bb | 2014-02-27 21:59:01 +0200 | [diff] [blame] | 6005 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 6006 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 4f1ca9e | 2014-02-27 21:59:02 +0200 | [diff] [blame] | 6007 | |
| 6008 | /* WaDisableSDEUnitClockGating:bdw */ |
| 6009 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 6010 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Damien Lespiau | 5d70868 | 2014-03-26 18:41:51 +0000 | [diff] [blame] | 6011 | |
Paulo Zanoni | 89d6b2b | 2014-08-21 17:09:36 -0300 | [diff] [blame] | 6012 | lpt_init_clock_gating(dev); |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 6013 | } |
| 6014 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6015 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 6016 | { |
| 6017 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6018 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6019 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6020 | |
Francisco Jerez | f3fc488 | 2013-10-02 15:53:16 -0700 | [diff] [blame] | 6021 | /* L3 caching of data atomics doesn't work -- disable it. */ |
| 6022 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
| 6023 | I915_WRITE(HSW_ROW_CHICKEN3, |
| 6024 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
| 6025 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6026 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6027 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6028 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6029 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6030 | |
Ville Syrjälä | e36ea7f | 2014-01-22 21:33:00 +0200 | [diff] [blame] | 6031 | /* WaVSRefCountFullforceMissDisable:hsw */ |
| 6032 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6033 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6034 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6035 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
| 6036 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6037 | |
Chia-I Wu | fe27c60 | 2014-01-28 13:29:33 +0800 | [diff] [blame] | 6038 | /* enable HiZ Raw Stall Optimization */ |
| 6039 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 6040 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 6041 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6042 | /* WaDisable4x2SubspanOptimization:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6043 | I915_WRITE(CACHE_MODE_1, |
| 6044 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 6045 | |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6046 | /* |
| 6047 | * BSpec recommends 8x4 when MSAA is used, |
| 6048 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 6049 | * |
| 6050 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6051 | * disable bit, which we don't touch here, but it's good |
| 6052 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6053 | */ |
| 6054 | I915_WRITE(GEN7_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 6055 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6056 | |
Kenneth Graunke | 9441159 | 2014-12-31 16:23:00 -0800 | [diff] [blame] | 6057 | /* WaSampleCChickenBitEnable:hsw */ |
| 6058 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 6059 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); |
| 6060 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6061 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
Ben Widawsky | e3dff58 | 2013-03-20 14:49:14 -0700 | [diff] [blame] | 6062 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| 6063 | |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 6064 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
| 6065 | I915_WRITE(CHICKEN_PAR1_1, |
| 6066 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 6067 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 6068 | lpt_init_clock_gating(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6069 | } |
| 6070 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6071 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6072 | { |
| 6073 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6074 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6075 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6076 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6077 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6078 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6079 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6080 | /* WaDisableEarlyCull:ivb */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 6081 | I915_WRITE(_3D_CHICKEN3, |
| 6082 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 6083 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6084 | /* WaDisableBackToBackFlipFix:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6085 | I915_WRITE(IVB_CHICKEN3, |
| 6086 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 6087 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 6088 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6089 | /* WaDisablePSDDualDispatchEnable:ivb */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6090 | if (IS_IVB_GT1(dev)) |
| 6091 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 6092 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6093 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6094 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
| 6095 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6096 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6097 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6098 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 6099 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 6100 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6101 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6102 | I915_WRITE(GEN7_L3CNTLREG1, |
| 6103 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 6104 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6105 | GEN7_WA_L3_CHICKEN_MODE); |
| 6106 | if (IS_IVB_GT1(dev)) |
| 6107 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6108 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 6109 | else { |
| 6110 | /* must write both registers */ |
| 6111 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6112 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6113 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
| 6114 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 6115 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6116 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6117 | /* WaForceL3Serialization:ivb */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 6118 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 6119 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 6120 | |
Ville Syrjälä | 1b80a19a | 2014-01-22 21:32:53 +0200 | [diff] [blame] | 6121 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6122 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6123 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6124 | */ |
| 6125 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 28acf3b | 2014-01-22 21:32:48 +0200 | [diff] [blame] | 6126 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6127 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6128 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6129 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6130 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6131 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6132 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6133 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6134 | |
| 6135 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 6136 | |
Chris Wilson | 2272134 | 2014-03-04 09:41:43 +0000 | [diff] [blame] | 6137 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
| 6138 | /* enable HiZ Raw Stall Optimization */ |
| 6139 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 6140 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 6141 | } |
Chia-I Wu | 116f2b6 | 2014-01-28 13:29:34 +0800 | [diff] [blame] | 6142 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6143 | /* WaDisable4x2SubspanOptimization:ivb */ |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 6144 | I915_WRITE(CACHE_MODE_1, |
| 6145 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6146 | |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6147 | /* |
| 6148 | * BSpec recommends 8x4 when MSAA is used, |
| 6149 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 6150 | * |
| 6151 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6152 | * disable bit, which we don't touch here, but it's good |
| 6153 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6154 | */ |
| 6155 | I915_WRITE(GEN7_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 6156 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6157 | |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6158 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 6159 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 6160 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 6161 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6162 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 6163 | if (!HAS_PCH_NOP(dev)) |
| 6164 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 6165 | |
| 6166 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6167 | } |
| 6168 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6169 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6170 | { |
| 6171 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6172 | |
Ville Syrjälä | d7fe0cc | 2013-05-21 18:01:50 +0300 | [diff] [blame] | 6173 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6174 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6175 | /* WaDisableEarlyCull:vlv */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 6176 | I915_WRITE(_3D_CHICKEN3, |
| 6177 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 6178 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6179 | /* WaDisableBackToBackFlipFix:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6180 | I915_WRITE(IVB_CHICKEN3, |
| 6181 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 6182 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 6183 | |
Ville Syrjälä | fad7d36 | 2014-01-22 21:32:39 +0200 | [diff] [blame] | 6184 | /* WaPsdDispatchEnable:vlv */ |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6185 | /* WaDisablePSDDualDispatchEnable:vlv */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6186 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
Jesse Barnes | d3bc030 | 2013-03-08 10:45:51 -0800 | [diff] [blame] | 6187 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
| 6188 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6189 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6190 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
| 6191 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6192 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6193 | /* WaForceL3Serialization:vlv */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 6194 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 6195 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 6196 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6197 | /* WaDisableDopClockGating:vlv */ |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6198 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6199 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 6200 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6201 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6202 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6203 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6204 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6205 | |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 6206 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 6207 | |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 6208 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6209 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6210 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6211 | */ |
| 6212 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 6213 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6214 | |
Akash Goel | c98f506 | 2014-03-24 23:00:07 +0530 | [diff] [blame] | 6215 | /* WaDisableL3Bank2xClockGate:vlv |
| 6216 | * Disabling L3 clock gating- MMIO 940c[25] = 1 |
| 6217 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ |
| 6218 | I915_WRITE(GEN7_UCGCTL4, |
| 6219 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 6220 | |
Ville Syrjälä | e0d8d59 | 2013-06-12 22:11:18 +0300 | [diff] [blame] | 6221 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6222 | |
Ville Syrjälä | afd58e7 | 2014-01-22 21:33:03 +0200 | [diff] [blame] | 6223 | /* |
| 6224 | * BSpec says this must be set, even though |
| 6225 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
| 6226 | */ |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 6227 | I915_WRITE(CACHE_MODE_1, |
| 6228 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 6229 | |
| 6230 | /* |
Ville Syrjälä | da2518f | 2015-01-21 19:38:01 +0200 | [diff] [blame] | 6231 | * BSpec recommends 8x4 when MSAA is used, |
| 6232 | * however in practice 16x4 seems fastest. |
| 6233 | * |
| 6234 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6235 | * disable bit, which we don't touch here, but it's good |
| 6236 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 6237 | */ |
| 6238 | I915_WRITE(GEN7_GT_MODE, |
| 6239 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
| 6240 | |
| 6241 | /* |
Ville Syrjälä | 031994e | 2014-01-22 21:32:46 +0200 | [diff] [blame] | 6242 | * WaIncreaseL3CreditsForVLVB0:vlv |
| 6243 | * This is the hardware default actually. |
| 6244 | */ |
| 6245 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
| 6246 | |
| 6247 | /* |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6248 | * WaDisableVLVClockGating_VBIIssue:vlv |
Jesse Barnes | 2d80957 | 2012-10-25 12:15:44 -0700 | [diff] [blame] | 6249 | * Disable clock gating on th GCFG unit to prevent a delay |
| 6250 | * in the reporting of vblank events. |
| 6251 | */ |
Ville Syrjälä | 7a0d1ee | 2014-01-22 21:33:04 +0200 | [diff] [blame] | 6252 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6253 | } |
| 6254 | |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6255 | static void cherryview_init_clock_gating(struct drm_device *dev) |
| 6256 | { |
| 6257 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6258 | |
| 6259 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| 6260 | |
| 6261 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | dd811e7 | 2014-04-09 13:28:33 +0300 | [diff] [blame] | 6262 | |
Ville Syrjälä | 232ce33 | 2014-04-09 13:28:35 +0300 | [diff] [blame] | 6263 | /* WaVSRefCountFullforceMissDisable:chv */ |
| 6264 | /* WaDSRefCountFullforceMissDisable:chv */ |
| 6265 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6266 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 6267 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | acea6f9 | 2014-04-09 13:28:36 +0300 | [diff] [blame] | 6268 | |
| 6269 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ |
| 6270 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 6271 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 0846697 | 2014-04-09 13:28:37 +0300 | [diff] [blame] | 6272 | |
| 6273 | /* WaDisableCSUnitClockGating:chv */ |
| 6274 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
| 6275 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | c631780 | 2014-04-09 13:28:38 +0300 | [diff] [blame] | 6276 | |
| 6277 | /* WaDisableSDEUnitClockGating:chv */ |
| 6278 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 6279 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6280 | } |
| 6281 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6282 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6283 | { |
| 6284 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6285 | uint32_t dspclk_gate; |
| 6286 | |
| 6287 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 6288 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 6289 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 6290 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 6291 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 6292 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 6293 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 6294 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 6295 | if (IS_GM45(dev)) |
| 6296 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 6297 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 6298 | |
| 6299 | /* WaDisableRenderCachePipelinedFlush */ |
| 6300 | I915_WRITE(CACHE_MODE_0, |
| 6301 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 6302 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6303 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
| 6304 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6305 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6306 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6307 | } |
| 6308 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6309 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6310 | { |
| 6311 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6312 | |
| 6313 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 6314 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 6315 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 6316 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 6317 | I915_WRITE16(DEUC, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 6318 | I915_WRITE(MI_ARB_STATE, |
| 6319 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6320 | |
| 6321 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 6322 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6323 | } |
| 6324 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6325 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6326 | { |
| 6327 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6328 | |
| 6329 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 6330 | I965_RCC_CLOCK_GATE_DISABLE | |
| 6331 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 6332 | I965_ISC_CLOCK_GATE_DISABLE | |
| 6333 | I965_FBC_CLOCK_GATE_DISABLE); |
| 6334 | I915_WRITE(RENCLK_GATE_D2, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 6335 | I915_WRITE(MI_ARB_STATE, |
| 6336 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6337 | |
| 6338 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 6339 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6340 | } |
| 6341 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6342 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6343 | { |
| 6344 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6345 | u32 dstate = I915_READ(D_STATE); |
| 6346 | |
| 6347 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 6348 | DSTATE_DOT_CLOCK_GATING; |
| 6349 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 6350 | |
| 6351 | if (IS_PINEVIEW(dev)) |
| 6352 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Daniel Vetter | 974a3b0 | 2012-09-09 11:54:16 +0200 | [diff] [blame] | 6353 | |
| 6354 | /* IIR "flip pending" means done if this bit is set */ |
| 6355 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
Ville Syrjälä | 12fabbcb9 | 2014-02-25 15:13:38 +0200 | [diff] [blame] | 6356 | |
| 6357 | /* interrupts should cause a wake up from C3 */ |
Ville Syrjälä | 3299254 | 2014-02-25 15:13:39 +0200 | [diff] [blame] | 6358 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
Ville Syrjälä | dbb4274 | 2014-02-25 15:13:41 +0200 | [diff] [blame] | 6359 | |
| 6360 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 6361 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6362 | |
| 6363 | I915_WRITE(MI_ARB_STATE, |
| 6364 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6365 | } |
| 6366 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6367 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6368 | { |
| 6369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6370 | |
| 6371 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 54e472a | 2014-02-25 15:13:40 +0200 | [diff] [blame] | 6372 | |
| 6373 | /* interrupts should cause a wake up from C3 */ |
| 6374 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | |
| 6375 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6376 | |
| 6377 | I915_WRITE(MEM_MODE, |
| 6378 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6379 | } |
| 6380 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6381 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6382 | { |
| 6383 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6384 | |
| 6385 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6386 | |
| 6387 | I915_WRITE(MEM_MODE, |
| 6388 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | |
| 6389 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6390 | } |
| 6391 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6392 | void intel_init_clock_gating(struct drm_device *dev) |
| 6393 | { |
| 6394 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6395 | |
| 6396 | dev_priv->display.init_clock_gating(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6397 | } |
| 6398 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 6399 | void intel_suspend_hw(struct drm_device *dev) |
| 6400 | { |
| 6401 | if (HAS_PCH_LPT(dev)) |
| 6402 | lpt_suspend_hw(dev); |
| 6403 | } |
| 6404 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6405 | /* Set up chip specific power management-related functions */ |
| 6406 | void intel_init_pm(struct drm_device *dev) |
| 6407 | { |
| 6408 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6409 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 6410 | intel_fbc_init(dev_priv); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6411 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 6412 | /* For cxsr */ |
| 6413 | if (IS_PINEVIEW(dev)) |
| 6414 | i915_pineview_get_mem_freq(dev); |
| 6415 | else if (IS_GEN5(dev)) |
| 6416 | i915_ironlake_get_mem_freq(dev); |
| 6417 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6418 | /* For FIFO watermark updates */ |
Damien Lespiau | f5ed50c | 2014-11-13 17:51:52 +0000 | [diff] [blame] | 6419 | if (INTEL_INFO(dev)->gen >= 9) { |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 6420 | skl_setup_wm_latency(dev); |
| 6421 | |
Damien Lespiau | c83155a | 2014-03-28 00:18:35 +0530 | [diff] [blame] | 6422 | dev_priv->display.init_clock_gating = gen9_init_clock_gating; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 6423 | dev_priv->display.update_wm = skl_update_wm; |
| 6424 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; |
Damien Lespiau | c83155a | 2014-03-28 00:18:35 +0530 | [diff] [blame] | 6425 | } else if (HAS_PCH_SPLIT(dev)) { |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 6426 | ilk_setup_wm_latency(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 6427 | |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6428 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
| 6429 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
| 6430 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
| 6431 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
| 6432 | dev_priv->display.update_wm = ilk_update_wm; |
| 6433 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; |
| 6434 | } else { |
| 6435 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 6436 | "Disable CxSR\n"); |
| 6437 | } |
| 6438 | |
| 6439 | if (IS_GEN5(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6440 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6441 | else if (IS_GEN6(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6442 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6443 | else if (IS_IVYBRIDGE(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6444 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6445 | else if (IS_HASWELL(dev)) |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6446 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6447 | else if (INTEL_INFO(dev)->gen == 8) |
Paulo Zanoni | 47c2bd9 | 2014-08-21 17:09:37 -0300 | [diff] [blame] | 6448 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6449 | } else if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 6450 | dev_priv->display.update_wm = cherryview_update_wm; |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 6451 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6452 | dev_priv->display.init_clock_gating = |
| 6453 | cherryview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6454 | } else if (IS_VALLEYVIEW(dev)) { |
| 6455 | dev_priv->display.update_wm = valleyview_update_wm; |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame] | 6456 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6457 | dev_priv->display.init_clock_gating = |
| 6458 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6459 | } else if (IS_PINEVIEW(dev)) { |
| 6460 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 6461 | dev_priv->is_ddr3, |
| 6462 | dev_priv->fsb_freq, |
| 6463 | dev_priv->mem_freq)) { |
| 6464 | DRM_INFO("failed to find known CxSR latency " |
| 6465 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 6466 | "disabling CxSR\n", |
| 6467 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 6468 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 6469 | /* Disable CxSR and never update its watermark again */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 6470 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6471 | dev_priv->display.update_wm = NULL; |
| 6472 | } else |
| 6473 | dev_priv->display.update_wm = pineview_update_wm; |
| 6474 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 6475 | } else if (IS_G4X(dev)) { |
| 6476 | dev_priv->display.update_wm = g4x_update_wm; |
| 6477 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 6478 | } else if (IS_GEN4(dev)) { |
| 6479 | dev_priv->display.update_wm = i965_update_wm; |
| 6480 | if (IS_CRESTLINE(dev)) |
| 6481 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 6482 | else if (IS_BROADWATER(dev)) |
| 6483 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 6484 | } else if (IS_GEN3(dev)) { |
| 6485 | dev_priv->display.update_wm = i9xx_update_wm; |
| 6486 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 6487 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6488 | } else if (IS_GEN2(dev)) { |
| 6489 | if (INTEL_INFO(dev)->num_pipes == 1) { |
| 6490 | dev_priv->display.update_wm = i845_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6491 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6492 | } else { |
| 6493 | dev_priv->display.update_wm = i9xx_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6494 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6495 | } |
| 6496 | |
| 6497 | if (IS_I85X(dev) || IS_I865G(dev)) |
| 6498 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 6499 | else |
| 6500 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 6501 | } else { |
| 6502 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6503 | } |
| 6504 | } |
| 6505 | |
Tom O'Rourke | 151a49d | 2014-11-13 18:50:10 -0800 | [diff] [blame] | 6506 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6507 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6508 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6509 | |
| 6510 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 6511 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
| 6512 | return -EAGAIN; |
| 6513 | } |
| 6514 | |
| 6515 | I915_WRITE(GEN6_PCODE_DATA, *val); |
Damien Lespiau | dddab34 | 2014-11-13 17:51:50 +0000 | [diff] [blame] | 6516 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6517 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 6518 | |
| 6519 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 6520 | 500)) { |
| 6521 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
| 6522 | return -ETIMEDOUT; |
| 6523 | } |
| 6524 | |
| 6525 | *val = I915_READ(GEN6_PCODE_DATA); |
| 6526 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 6527 | |
| 6528 | return 0; |
| 6529 | } |
| 6530 | |
Tom O'Rourke | 151a49d | 2014-11-13 18:50:10 -0800 | [diff] [blame] | 6531 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6532 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6533 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6534 | |
| 6535 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 6536 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
| 6537 | return -EAGAIN; |
| 6538 | } |
| 6539 | |
| 6540 | I915_WRITE(GEN6_PCODE_DATA, val); |
| 6541 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 6542 | |
| 6543 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 6544 | 500)) { |
| 6545 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
| 6546 | return -ETIMEDOUT; |
| 6547 | } |
| 6548 | |
| 6549 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 6550 | |
| 6551 | return 0; |
| 6552 | } |
Jesse Barnes | a0e4e19 | 2013-04-02 11:23:05 -0700 | [diff] [blame] | 6553 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6554 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6555 | { |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6556 | switch (czclk_freq) { |
| 6557 | case 200: |
| 6558 | return 10; |
| 6559 | case 267: |
| 6560 | return 12; |
| 6561 | case 320: |
| 6562 | case 333: |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6563 | return 16; |
Ville Syrjälä | ab3fb15 | 2014-11-10 22:55:15 +0200 | [diff] [blame] | 6564 | case 400: |
| 6565 | return 20; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6566 | default: |
| 6567 | return -1; |
| 6568 | } |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6569 | } |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6570 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6571 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
| 6572 | { |
| 6573 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); |
| 6574 | |
| 6575 | div = vlv_gpu_freq_div(czclk_freq); |
| 6576 | if (div < 0) |
| 6577 | return div; |
| 6578 | |
| 6579 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6580 | } |
| 6581 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 6582 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6583 | { |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6584 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6585 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6586 | mul = vlv_gpu_freq_div(czclk_freq); |
| 6587 | if (mul < 0) |
| 6588 | return mul; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6589 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6590 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6591 | } |
| 6592 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 6593 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6594 | { |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6595 | int div, czclk_freq = dev_priv->rps.cz_freq; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6596 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6597 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
| 6598 | if (div < 0) |
| 6599 | return div; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6600 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6601 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6602 | } |
| 6603 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 6604 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6605 | { |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6606 | int mul, czclk_freq = dev_priv->rps.cz_freq; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6607 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6608 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
| 6609 | if (mul < 0) |
| 6610 | return mul; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6611 | |
Ville Syrjälä | 1c14762 | 2014-08-18 14:42:43 +0300 | [diff] [blame] | 6612 | /* CHV needs even values */ |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 6613 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6614 | } |
| 6615 | |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 6616 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
| 6617 | { |
| 6618 | if (IS_CHERRYVIEW(dev_priv->dev)) |
| 6619 | return chv_gpu_freq(dev_priv, val); |
| 6620 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
| 6621 | return byt_gpu_freq(dev_priv, val); |
| 6622 | else |
| 6623 | return val * GT_FREQUENCY_MULTIPLIER; |
| 6624 | } |
| 6625 | |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 6626 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
| 6627 | { |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6628 | if (IS_CHERRYVIEW(dev_priv->dev)) |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 6629 | return chv_freq_opcode(dev_priv, val); |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6630 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 6631 | return byt_freq_opcode(dev_priv, val); |
| 6632 | else |
| 6633 | return val / GT_FREQUENCY_MULTIPLIER; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 6634 | } |
| 6635 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 6636 | void intel_pm_setup(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6637 | { |
| 6638 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6639 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 6640 | mutex_init(&dev_priv->rps.hw_lock); |
| 6641 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6642 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
| 6643 | intel_gen6_powersave_work); |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 6644 | |
Paulo Zanoni | 33688d9 | 2014-03-07 20:08:19 -0300 | [diff] [blame] | 6645 | dev_priv->pm.suspended = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6646 | } |