blob: 057c272259446efcdf26cb1278dea69cb2d9c49a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070035#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040038#include <linux/module.h>
Zhao Yakui354ff962009-07-08 14:13:12 +080039#include "drm_crtc_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080040
Ben Widawskya35d9d32011-07-13 14:38:17 -070041static int i915_modeset __read_mostly = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -080042module_param_named(modeset, i915_modeset, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070043MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
Jesse Barnes79e53942008-11-07 14:24:08 -080046
Ben Widawskya35d9d32011-07-13 14:38:17 -070047unsigned int i915_fbpercrtc __always_unused = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080048module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
Ben Widawskya35d9d32011-07-13 14:38:17 -070050int i915_panel_ignore_lid __read_mostly = 0;
Chris Wilsonfca87402011-02-17 13:44:48 +000051module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070052MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
Chris Wilsonfca87402011-02-17 13:44:48 +000055
Ben Widawskya35d9d32011-07-13 14:38:17 -070056unsigned int i915_powersave __read_mostly = 1;
Chris Wilson0aa99272010-11-02 09:20:50 +000057module_param_named(powersave, i915_powersave, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070058MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
Jesse Barnes652c3932009-08-17 13:31:43 -070060
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080061int i915_semaphores __read_mostly = -1;
Chris Wilsona1656b92011-03-04 18:48:03 +000062module_param_named(semaphores, i915_semaphores, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070063MODULE_PARM_DESC(semaphores,
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080064 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
Chris Wilsona1656b92011-03-04 18:48:03 +000065
Keith Packardc0f372b32011-11-16 22:24:52 -080066int i915_enable_rc6 __read_mostly = -1;
Chris Wilsonac668082011-02-09 16:15:32 +000067module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070068MODULE_PARM_DESC(i915_enable_rc6,
Keith Packardc0f372b32011-11-16 22:24:52 -080069 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
Chris Wilsonac668082011-02-09 16:15:32 +000070
Keith Packard4415e632011-11-09 09:57:50 -080071int i915_enable_fbc __read_mostly = -1;
Jesse Barnesc1a9f042011-05-05 15:24:21 -070072module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070073MODULE_PARM_DESC(i915_enable_fbc,
74 "Enable frame buffer compression for power savings "
Keith Packardcd0de032011-09-19 21:34:19 -070075 "(default: -1 (use per-chip default))");
Jesse Barnesc1a9f042011-05-05 15:24:21 -070076
Ben Widawskya35d9d32011-07-13 14:38:17 -070077unsigned int i915_lvds_downclock __read_mostly = 0;
Jesse Barnes33814342010-01-14 20:48:02 +000078module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070079MODULE_PARM_DESC(lvds_downclock,
80 "Use panel (LVDS/eDP) downclocking for power savings "
81 "(default: false)");
Jesse Barnes33814342010-01-14 20:48:02 +000082
Keith Packard4415e632011-11-09 09:57:50 -080083int i915_panel_use_ssc __read_mostly = -1;
Chris Wilsona7615032011-01-12 17:04:08 +000084module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070085MODULE_PARM_DESC(lvds_use_ssc,
86 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
Keith Packard72bbe582011-09-26 16:09:45 -070087 "(default: auto from VBT)");
Chris Wilsona7615032011-01-12 17:04:08 +000088
Ben Widawskya35d9d32011-07-13 14:38:17 -070089int i915_vbt_sdvo_panel_type __read_mostly = -1;
Chris Wilson5a1e5b62011-01-29 16:50:25 +000090module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070091MODULE_PARM_DESC(vbt_sdvo_panel_type,
92 "Override selection of SDVO panel mode in the VBT "
93 "(default: auto)");
Chris Wilson5a1e5b62011-01-29 16:50:25 +000094
Ben Widawskya35d9d32011-07-13 14:38:17 -070095static bool i915_try_reset __read_mostly = true;
Chris Wilsond78cb502010-12-23 13:33:15 +000096module_param_named(reset, i915_try_reset, bool, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070097MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
Chris Wilsond78cb502010-12-23 13:33:15 +000098
Ben Widawskya35d9d32011-07-13 14:38:17 -070099bool i915_enable_hangcheck __read_mostly = true;
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700100module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700101MODULE_PARM_DESC(enable_hangcheck,
102 "Periodically check GPU activity for detecting hangs. "
103 "WARNING: Disabling this can cause system wide hangs. "
104 "(default: true)");
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700105
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500106static struct drm_driver driver;
Zhenyu Wang1f7a6e32010-02-23 14:05:24 +0800107extern int intel_agp_enabled;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500108
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500109#define INTEL_VGA_DEVICE(id, info) { \
Daniel Vetter80a29012011-10-11 10:59:05 +0200110 .class = PCI_BASE_CLASS_DISPLAY << 16, \
Chris Wilson934f9922011-01-20 13:09:12 +0000111 .class_mask = 0xff0000, \
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500112 .vendor = 0x8086, \
113 .device = id, \
114 .subvendor = PCI_ANY_ID, \
115 .subdevice = PCI_ANY_ID, \
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500116 .driver_data = (unsigned long) info }
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500117
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200118static const struct intel_device_info intel_i830_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100119 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100120 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500121};
122
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200123static const struct intel_device_info intel_845g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100124 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100125 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500126};
127
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200128static const struct intel_device_info intel_i85x_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100129 .gen = 2, .is_i85x = 1, .is_mobile = 1,
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400130 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100131 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500132};
133
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200134static const struct intel_device_info intel_i865g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100135 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100136 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500137};
138
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200139static const struct intel_device_info intel_i915g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100140 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100141 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500142};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200143static const struct intel_device_info intel_i915gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100144 .gen = 3, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500145 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100146 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100147 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500148};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200149static const struct intel_device_info intel_i945g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100150 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100151 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500152};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200153static const struct intel_device_info intel_i945gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100154 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500155 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100156 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100157 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500158};
159
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200160static const struct intel_device_info intel_i965g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100161 .gen = 4, .is_broadwater = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100162 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100163 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500164};
165
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200166static const struct intel_device_info intel_i965gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100167 .gen = 4, .is_crestline = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000168 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100169 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100170 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500171};
172
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200173static const struct intel_device_info intel_g33_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100174 .gen = 3, .is_g33 = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100175 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100176 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500177};
178
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200179static const struct intel_device_info intel_g45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100180 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100181 .has_pipe_cxsr = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800182 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500183};
184
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200185static const struct intel_device_info intel_gm45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100186 .gen = 4, .is_g4x = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000187 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100188 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100189 .supports_tv = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800190 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500191};
192
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200193static const struct intel_device_info intel_pineview_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100194 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100195 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100196 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500197};
198
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200199static const struct intel_device_info intel_ironlake_d_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100200 .gen = 5,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200201 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800202 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500203};
204
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200205static const struct intel_device_info intel_ironlake_m_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100206 .gen = 5, .is_mobile = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000207 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700208 .has_fbc = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800209 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500210};
211
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200212static const struct intel_device_info intel_sandybridge_d_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100213 .gen = 6,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100214 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100215 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100216 .has_blt_ring = 1,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800217};
218
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200219static const struct intel_device_info intel_sandybridge_m_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100220 .gen = 6, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100221 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800222 .has_fbc = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100223 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100224 .has_blt_ring = 1,
Eric Anholta13e4092010-01-07 15:08:18 -0800225};
226
Jesse Barnesc76b6152011-04-28 14:32:07 -0700227static const struct intel_device_info intel_ivybridge_d_info = {
228 .is_ivybridge = 1, .gen = 7,
229 .need_gfx_hws = 1, .has_hotplug = 1,
230 .has_bsd_ring = 1,
231 .has_blt_ring = 1,
232};
233
234static const struct intel_device_info intel_ivybridge_m_info = {
235 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
236 .need_gfx_hws = 1, .has_hotplug = 1,
237 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
238 .has_bsd_ring = 1,
239 .has_blt_ring = 1,
240};
241
Chris Wilson6103da02010-07-05 18:01:47 +0100242static const struct pci_device_id pciidlist[] = { /* aka */
243 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
244 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
245 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400246 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
Chris Wilson6103da02010-07-05 18:01:47 +0100247 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
248 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
249 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
250 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
251 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
252 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
253 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
254 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
255 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
256 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
257 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
258 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
259 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
260 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
261 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
262 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
263 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
264 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
265 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
266 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
267 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
268 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
Chris Wilson41a51422010-09-17 08:22:30 +0100269 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500270 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
271 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
272 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
273 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
Eric Anholtf6e450a2009-11-02 12:08:22 -0800274 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800275 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
276 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
Eric Anholta13e4092010-01-07 15:08:18 -0800277 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800278 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
Zhenyu Wang4fefe432010-08-19 09:46:16 +0800279 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800280 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
Jesse Barnesc76b6152011-04-28 14:32:07 -0700281 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
282 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
283 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
284 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
285 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500286 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287};
288
Jesse Barnes79e53942008-11-07 14:24:08 -0800289#if defined(CONFIG_DRM_I915_KMS)
290MODULE_DEVICE_TABLE(pci, pciidlist);
291#endif
292
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800293#define INTEL_PCH_DEVICE_ID_MASK 0xff00
Jesse Barnes90711d52011-04-28 14:48:02 -0700294#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800295#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
Jesse Barnesc7925132011-04-07 12:33:56 -0700296#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800297
Akshay Joshi0206e352011-08-16 15:34:10 -0400298void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800299{
300 struct drm_i915_private *dev_priv = dev->dev_private;
301 struct pci_dev *pch;
302
303 /*
304 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
305 * make graphics device passthrough work easy for VMM, that only
306 * need to expose ISA bridge to let driver know the real hardware
307 * underneath. This is a requirement from virtualization team.
308 */
309 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
310 if (pch) {
311 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
312 int id;
313 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
314
Jesse Barnes90711d52011-04-28 14:48:02 -0700315 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
316 dev_priv->pch_type = PCH_IBX;
317 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
318 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800319 dev_priv->pch_type = PCH_CPT;
320 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Jesse Barnesc7925132011-04-07 12:33:56 -0700321 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
322 /* PantherPoint is CPT compatible */
323 dev_priv->pch_type = PCH_CPT;
324 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800325 }
326 }
327 pci_dev_put(pch);
328 }
329}
330
Keith Packard8d715f02011-11-18 20:39:01 -0800331void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
Chris Wilsoneb43f4a2010-12-08 17:32:24 +0000332{
333 int count;
334
335 count = 0;
336 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
337 udelay(10);
338
339 I915_WRITE_NOTRACE(FORCEWAKE, 1);
340 POSTING_READ(FORCEWAKE);
341
342 count = 0;
343 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
344 udelay(10);
345}
346
Keith Packard8d715f02011-11-18 20:39:01 -0800347void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
348{
349 int count;
350
351 count = 0;
352 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
353 udelay(10);
354
355 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
356 POSTING_READ(FORCEWAKE_MT);
357
358 count = 0;
359 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
360 udelay(10);
361}
362
Ben Widawskyfcca7922011-04-25 11:23:07 -0700363/*
364 * Generally this is called implicitly by the register read function. However,
365 * if some sequence requires the GT to not power down then this function should
366 * be called at the beginning of the sequence followed by a call to
367 * gen6_gt_force_wake_put() at the end of the sequence.
368 */
369void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
370{
371 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
372
373 /* Forcewake is atomic in case we get in here without the lock */
374 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
Keith Packard8d715f02011-11-18 20:39:01 -0800375 dev_priv->display.force_wake_get(dev_priv);
Ben Widawskyfcca7922011-04-25 11:23:07 -0700376}
377
Keith Packard8d715f02011-11-18 20:39:01 -0800378void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
Chris Wilsoneb43f4a2010-12-08 17:32:24 +0000379{
380 I915_WRITE_NOTRACE(FORCEWAKE, 0);
381 POSTING_READ(FORCEWAKE);
382}
383
Keith Packard8d715f02011-11-18 20:39:01 -0800384void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
385{
386 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
387 POSTING_READ(FORCEWAKE_MT);
388}
389
Ben Widawskyfcca7922011-04-25 11:23:07 -0700390/*
391 * see gen6_gt_force_wake_get()
392 */
393void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
394{
395 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
396
397 if (atomic_dec_and_test(&dev_priv->forcewake_count))
Keith Packard8d715f02011-11-18 20:39:01 -0800398 dev_priv->display.force_wake_put(dev_priv);
Ben Widawskyfcca7922011-04-25 11:23:07 -0700399}
400
Chris Wilson91355832011-03-04 19:22:40 +0000401void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
402{
Akshay Joshi0206e352011-08-16 15:34:10 -0400403 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
Chris Wilson957367202011-05-12 22:17:09 +0100404 int loop = 500;
405 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
406 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
407 udelay(10);
408 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
409 }
410 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
411 dev_priv->gt_fifo_count = fifo;
Chris Wilson91355832011-03-04 19:22:40 +0000412 }
Chris Wilson957367202011-05-12 22:17:09 +0100413 dev_priv->gt_fifo_count--;
Chris Wilson91355832011-03-04 19:22:40 +0000414}
415
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100416static int i915_drm_freeze(struct drm_device *dev)
417{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100418 struct drm_i915_private *dev_priv = dev->dev_private;
419
Dave Airlie5bcf7192010-12-07 09:20:40 +1000420 drm_kms_helper_poll_disable(dev);
421
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100422 pci_save_state(dev->pdev);
423
424 /* If KMS is active, we do the leavevt stuff here */
425 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
426 int error = i915_gem_idle(dev);
427 if (error) {
428 dev_err(&dev->pdev->dev,
429 "GEM idle failed, resume might fail\n");
430 return error;
431 }
432 drm_irq_uninstall(dev);
433 }
434
435 i915_save_state(dev);
436
Chris Wilson44834a62010-08-19 16:09:23 +0100437 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100438
439 /* Modeset on resume, not lid events */
440 dev_priv->modeset_on_lid = 0;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100441
442 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100443}
444
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000445int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100446{
447 int error;
448
449 if (!dev || !dev->dev_private) {
450 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700451 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000452 return -ENODEV;
453 }
454
Dave Airlieb932ccb2008-02-20 10:02:20 +1000455 if (state.event == PM_EVENT_PRETHAW)
456 return 0;
457
Dave Airlie5bcf7192010-12-07 09:20:40 +1000458
459 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
460 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100461
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100462 error = i915_drm_freeze(dev);
463 if (error)
464 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000465
Dave Airlieb932ccb2008-02-20 10:02:20 +1000466 if (state.event == PM_EVENT_SUSPEND) {
467 /* Shut down the device */
468 pci_disable_device(dev->pdev);
469 pci_set_power_state(dev->pdev, PCI_D3hot);
470 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000471
472 return 0;
473}
474
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100475static int i915_drm_thaw(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000476{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800477 struct drm_i915_private *dev_priv = dev->dev_private;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100478 int error = 0;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100479
Chris Wilsond1c3b172010-12-08 14:26:19 +0000480 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
481 mutex_lock(&dev->struct_mutex);
482 i915_gem_restore_gtt_mappings(dev);
483 mutex_unlock(&dev->struct_mutex);
484 }
485
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100486 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100487 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100488
Jesse Barnes5669fca2009-02-17 15:13:31 -0800489 /* KMS EnterVT equivalent */
490 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
491 mutex_lock(&dev->struct_mutex);
492 dev_priv->mm.suspended = 0;
493
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100494 error = i915_gem_init_ringbuffer(dev);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800495 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800496
Keith Packard9fb526d2011-09-26 22:24:57 -0700497 if (HAS_PCH_SPLIT(dev))
498 ironlake_init_pch_refclk(dev);
499
Chris Wilson500f7142011-01-24 15:14:41 +0000500 drm_mode_config_reset(dev);
Jesse Barnes226485e2009-02-23 15:41:09 -0800501 drm_irq_install(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100502
Zhao Yakui354ff962009-07-08 14:13:12 +0800503 /* Resume the modeset for every activated CRTC */
504 drm_helper_resume_force_mode(dev);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800505
Chris Wilsonac668082011-02-09 16:15:32 +0000506 if (IS_IRONLAKE_M(dev))
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800507 ironlake_enable_rc6(dev);
508 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800509
Chris Wilson44834a62010-08-19 16:09:23 +0100510 intel_opregion_init(dev);
511
Linus Torvaldsc9354c82009-11-02 09:29:55 -0800512 dev_priv->modeset_on_lid = 0;
Jesse Barnes06891e22009-09-14 10:58:48 -0700513
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100514 return error;
515}
516
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000517int i915_resume(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100518{
Chris Wilson6eecba32010-09-08 09:45:11 +0100519 int ret;
520
Dave Airlie5bcf7192010-12-07 09:20:40 +1000521 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
522 return 0;
523
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100524 if (pci_enable_device(dev->pdev))
525 return -EIO;
526
527 pci_set_master(dev->pdev);
528
Chris Wilson6eecba32010-09-08 09:45:11 +0100529 ret = i915_drm_thaw(dev);
530 if (ret)
531 return ret;
532
533 drm_kms_helper_poll_enable(dev);
534 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000535}
536
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100537static int i8xx_do_reset(struct drm_device *dev, u8 flags)
538{
539 struct drm_i915_private *dev_priv = dev->dev_private;
540
541 if (IS_I85X(dev))
542 return -ENODEV;
543
544 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
545 POSTING_READ(D_STATE);
546
547 if (IS_I830(dev) || IS_845G(dev)) {
548 I915_WRITE(DEBUG_RESET_I830,
549 DEBUG_RESET_DISPLAY |
550 DEBUG_RESET_RENDER |
551 DEBUG_RESET_FULL);
552 POSTING_READ(DEBUG_RESET_I830);
553 msleep(1);
554
555 I915_WRITE(DEBUG_RESET_I830, 0);
556 POSTING_READ(DEBUG_RESET_I830);
557 }
558
559 msleep(1);
560
561 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
562 POSTING_READ(D_STATE);
563
564 return 0;
565}
566
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700567static int i965_reset_complete(struct drm_device *dev)
568{
569 u8 gdrst;
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700570 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700571 return gdrst & 0x1;
572}
573
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700574static int i965_do_reset(struct drm_device *dev, u8 flags)
575{
576 u8 gdrst;
577
Chris Wilsonae681d92010-10-01 14:57:56 +0100578 /*
579 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
580 * well as the reset bit (GR/bit 0). Setting the GR bit
581 * triggers the reset; when done, the hardware will clear it.
582 */
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700583 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
584 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
585
586 return wait_for(i965_reset_complete(dev), 500);
587}
588
589static int ironlake_do_reset(struct drm_device *dev, u8 flags)
590{
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
593 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
594 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595}
596
Eric Anholtcff458c2010-11-18 09:31:14 +0800597static int gen6_do_reset(struct drm_device *dev, u8 flags)
598{
599 struct drm_i915_private *dev_priv = dev->dev_private;
600
601 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
602 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
603}
604
Ben Gamari11ed50e2009-09-14 17:48:45 -0400605/**
606 * i965_reset - reset chip after a hang
607 * @dev: drm device to reset
608 * @flags: reset domains
609 *
610 * Reset the chip. Useful if a hang is detected. Returns zero on successful
611 * reset or otherwise an error code.
612 *
613 * Procedure is fairly simple:
614 * - reset the chip using the reset reg
615 * - re-init context state
616 * - re-init hardware status page
617 * - re-init ring buffer
618 * - re-init interrupt state
619 * - re-init display
620 */
Chris Wilsonf803aa52010-09-19 12:38:26 +0100621int i915_reset(struct drm_device *dev, u8 flags)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400622{
623 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400624 /*
625 * We really should only reset the display subsystem if we actually
626 * need to
627 */
628 bool need_display = true;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700629 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400630
Chris Wilsond78cb502010-12-23 13:33:15 +0000631 if (!i915_try_reset)
632 return 0;
633
Chris Wilson340479a2010-12-04 18:17:15 +0000634 if (!mutex_trylock(&dev->struct_mutex))
635 return -EBUSY;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400636
Chris Wilson069efc12010-09-30 16:53:18 +0100637 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400638
Chris Wilsonf803aa52010-09-19 12:38:26 +0100639 ret = -ENODEV;
Chris Wilsonae681d92010-10-01 14:57:56 +0100640 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
641 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
642 } else switch (INTEL_INFO(dev)->gen) {
Kenneth Graunke10836942011-07-07 15:33:26 -0700643 case 7:
Eric Anholtcff458c2010-11-18 09:31:14 +0800644 case 6:
645 ret = gen6_do_reset(dev, flags);
Ben Widawsky25732822011-06-24 14:31:47 -0700646 /* If reset with a user forcewake, try to restore */
647 if (atomic_read(&dev_priv->forcewake_count))
648 __gen6_gt_force_wake_get(dev_priv);
Eric Anholtcff458c2010-11-18 09:31:14 +0800649 break;
Chris Wilsonf803aa52010-09-19 12:38:26 +0100650 case 5:
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700651 ret = ironlake_do_reset(dev, flags);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100652 break;
653 case 4:
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700654 ret = i965_do_reset(dev, flags);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100655 break;
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100656 case 2:
657 ret = i8xx_do_reset(dev, flags);
658 break;
Chris Wilsonf803aa52010-09-19 12:38:26 +0100659 }
Chris Wilsonae681d92010-10-01 14:57:56 +0100660 dev_priv->last_gpu_reset = get_seconds();
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700661 if (ret) {
Chris Wilsonf803aa52010-09-19 12:38:26 +0100662 DRM_ERROR("Failed to reset chip.\n");
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100663 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100664 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400665 }
666
667 /* Ok, now get things going again... */
668
669 /*
670 * Everything depends on having the GTT running, so we need to start
671 * there. Fortunately we don't need to do this unless we reset the
672 * chip at a PCI level.
673 *
674 * Next we need to restore the context, but we don't use those
675 * yet either...
676 *
677 * Ring buffer needs to be re-initialized in the KMS case, or if X
678 * was running at the time of the reset (i.e. we weren't VT
679 * switched away).
680 */
681 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800682 !dev_priv->mm.suspended) {
Ben Gamari11ed50e2009-09-14 17:48:45 -0400683 dev_priv->mm.suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800684
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000685 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
Eric Anholt75a68982010-11-18 09:31:13 +0800686 if (HAS_BSD(dev))
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000687 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
Eric Anholt75a68982010-11-18 09:31:13 +0800688 if (HAS_BLT(dev))
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000689 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
Eric Anholt75a68982010-11-18 09:31:13 +0800690
Ben Gamari11ed50e2009-09-14 17:48:45 -0400691 mutex_unlock(&dev->struct_mutex);
692 drm_irq_uninstall(dev);
Chris Wilson500f7142011-01-24 15:14:41 +0000693 drm_mode_config_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400694 drm_irq_install(dev);
695 mutex_lock(&dev->struct_mutex);
696 }
697
Ben Gamari11ed50e2009-09-14 17:48:45 -0400698 mutex_unlock(&dev->struct_mutex);
Chris Wilson9fd98142010-09-18 08:08:06 +0100699
700 /*
701 * Perform a full modeset as on later generations, e.g. Ironlake, we may
702 * need to retrain the display link and cannot just restore the register
703 * values.
704 */
705 if (need_display) {
706 mutex_lock(&dev->mode_config.mutex);
707 drm_helper_resume_force_mode(dev);
708 mutex_unlock(&dev->mode_config.mutex);
709 }
710
Ben Gamari11ed50e2009-09-14 17:48:45 -0400711 return 0;
712}
713
714
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500715static int __devinit
716i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
717{
Chris Wilson5fe49d82011-02-01 19:43:02 +0000718 /* Only bind to function 0 of the device. Early generations
719 * used function 1 as a placeholder for multi-head. This causes
720 * us confusion instead, especially on the systems where both
721 * functions have the same PCI-ID!
722 */
723 if (PCI_FUNC(pdev->devfn))
724 return -ENODEV;
725
Jordan Crousedcdb1672010-05-27 13:40:25 -0600726 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500727}
728
729static void
730i915_pci_remove(struct pci_dev *pdev)
731{
732 struct drm_device *dev = pci_get_drvdata(pdev);
733
734 drm_put_dev(dev);
735}
736
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100737static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500738{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100739 struct pci_dev *pdev = to_pci_dev(dev);
740 struct drm_device *drm_dev = pci_get_drvdata(pdev);
741 int error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500742
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100743 if (!drm_dev || !drm_dev->dev_private) {
744 dev_err(dev, "DRM not initialized, aborting suspend.\n");
745 return -ENODEV;
746 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500747
Dave Airlie5bcf7192010-12-07 09:20:40 +1000748 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
749 return 0;
750
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100751 error = i915_drm_freeze(drm_dev);
752 if (error)
753 return error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500754
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100755 pci_disable_device(pdev);
756 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800757
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800758 return 0;
759}
760
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100761static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800762{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100763 struct pci_dev *pdev = to_pci_dev(dev);
764 struct drm_device *drm_dev = pci_get_drvdata(pdev);
765
766 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800767}
768
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100769static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800770{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100771 struct pci_dev *pdev = to_pci_dev(dev);
772 struct drm_device *drm_dev = pci_get_drvdata(pdev);
773
774 if (!drm_dev || !drm_dev->dev_private) {
775 dev_err(dev, "DRM not initialized, aborting suspend.\n");
776 return -ENODEV;
777 }
778
779 return i915_drm_freeze(drm_dev);
780}
781
782static int i915_pm_thaw(struct device *dev)
783{
784 struct pci_dev *pdev = to_pci_dev(dev);
785 struct drm_device *drm_dev = pci_get_drvdata(pdev);
786
787 return i915_drm_thaw(drm_dev);
788}
789
790static int i915_pm_poweroff(struct device *dev)
791{
792 struct pci_dev *pdev = to_pci_dev(dev);
793 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100794
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100795 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800796}
797
Chris Wilsonb4b78d12010-06-06 15:40:20 +0100798static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400799 .suspend = i915_pm_suspend,
800 .resume = i915_pm_resume,
801 .freeze = i915_pm_freeze,
802 .thaw = i915_pm_thaw,
803 .poweroff = i915_pm_poweroff,
804 .restore = i915_pm_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800805};
806
Jesse Barnesde151cf2008-11-12 10:03:55 -0800807static struct vm_operations_struct i915_gem_vm_ops = {
808 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -0800809 .open = drm_gem_vm_open,
810 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -0800811};
812
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700813static const struct file_operations i915_driver_fops = {
814 .owner = THIS_MODULE,
815 .open = drm_open,
816 .release = drm_release,
817 .unlocked_ioctl = drm_ioctl,
818 .mmap = drm_gem_mmap,
819 .poll = drm_poll,
820 .fasync = drm_fasync,
821 .read = drm_read,
822#ifdef CONFIG_COMPAT
823 .compat_ioctl = i915_compat_ioctl,
824#endif
825 .llseek = noop_llseek,
826};
827
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +0000829 /* Don't use MTRRs here; the Xserver or userspace app should
830 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +1100831 */
Eric Anholt673a3942008-07-30 12:06:12 -0700832 .driver_features =
833 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
834 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
Dave Airlie22eae942005-11-10 22:16:34 +1100835 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000836 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -0700837 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +1100838 .lastclose = i915_driver_lastclose,
839 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -0700840 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +0100841
842 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
843 .suspend = i915_suspend,
844 .resume = i915_resume,
845
Dave Airliecda17382005-07-10 17:31:26 +1000846 .device_is_agp = i915_driver_device_is_agp,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 .reclaim_buffers = drm_core_reclaim_buffers,
Dave Airlie7c1c2872008-11-28 14:22:24 +1000848 .master_create = i915_master_create,
849 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -0500850#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -0400851 .debugfs_init = i915_debugfs_init,
852 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -0500853#endif
Eric Anholt673a3942008-07-30 12:06:12 -0700854 .gem_init_object = i915_gem_init_object,
855 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -0800856 .gem_vm_ops = &i915_gem_vm_ops,
Dave Airlieff72145b2011-02-07 12:16:14 +1000857 .dumb_create = i915_gem_dumb_create,
858 .dumb_map_offset = i915_gem_mmap_gtt,
859 .dumb_destroy = i915_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700861 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +1100862 .name = DRIVER_NAME,
863 .desc = DRIVER_DESC,
864 .date = DRIVER_DATE,
865 .major = DRIVER_MAJOR,
866 .minor = DRIVER_MINOR,
867 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868};
869
Dave Airlie8410ea32010-12-15 03:16:38 +1000870static struct pci_driver i915_pci_driver = {
871 .name = DRIVER_NAME,
872 .id_table = pciidlist,
873 .probe = i915_pci_probe,
874 .remove = i915_pci_remove,
875 .driver.pm = &i915_pm_ops,
876};
877
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878static int __init i915_init(void)
879{
Zhenyu Wang1f7a6e32010-02-23 14:05:24 +0800880 if (!intel_agp_enabled) {
881 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
882 return -ENODEV;
883 }
884
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800886
887 /*
888 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
889 * explicitly disabled with the module pararmeter.
890 *
891 * Otherwise, just follow the parameter (defaulting to off).
892 *
893 * Allow optional vga_text_mode_force boot option to override
894 * the default behavior.
895 */
896#if defined(CONFIG_DRM_I915_KMS)
897 if (i915_modeset != 0)
898 driver.driver_features |= DRIVER_MODESET;
899#endif
900 if (i915_modeset == 1)
901 driver.driver_features |= DRIVER_MODESET;
902
903#ifdef CONFIG_VGA_CONSOLE
904 if (vgacon_text_force() && i915_modeset == -1)
905 driver.driver_features &= ~DRIVER_MODESET;
906#endif
907
Chris Wilson3885c6b2011-01-23 10:45:14 +0000908 if (!(driver.driver_features & DRIVER_MODESET))
909 driver.get_vblank_timestamp = NULL;
910
Dave Airlie8410ea32010-12-15 03:16:38 +1000911 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912}
913
914static void __exit i915_exit(void)
915{
Dave Airlie8410ea32010-12-15 03:16:38 +1000916 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917}
918
919module_init(i915_init);
920module_exit(i915_exit);
921
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000922MODULE_AUTHOR(DRIVER_AUTHOR);
923MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924MODULE_LICENSE("GPL and additional rights");
Andi Kleenf7000882011-10-13 16:08:51 -0700925
Andi Kleenf7000882011-10-13 16:08:51 -0700926#define __i915_read(x, y) \
927u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
928 u##x val = 0; \
929 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
930 gen6_gt_force_wake_get(dev_priv); \
931 val = read##y(dev_priv->regs + reg); \
932 gen6_gt_force_wake_put(dev_priv); \
933 } else { \
934 val = read##y(dev_priv->regs + reg); \
935 } \
936 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
937 return val; \
938}
939
940__i915_read(8, b)
941__i915_read(16, w)
942__i915_read(32, l)
943__i915_read(64, q)
944#undef __i915_read
945
946#define __i915_write(x, y) \
947void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
948 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
949 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
950 __gen6_gt_wait_for_fifo(dev_priv); \
951 } \
952 write##y(val, dev_priv->regs + reg); \
953}
954__i915_write(8, b)
955__i915_write(16, w)
956__i915_write(32, l)
957__i915_write(64, q)
958#undef __i915_write