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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Damien Lespiau70d21f02013-07-03 21:06:04 +010029#define _PLANE(plane, a, b) _PIPE(plane, a, b)
Paulo Zanonia5c961d2012-10-24 15:59:34 -020030#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030031#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Ville Syrjälä2d401b12014-04-09 13:29:08 +030032#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
Jani Nikulae7d7cad2014-11-14 16:54:21 +020034#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35 (port) == PORT_B ? (b) : (c))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030036
Damien Lespiau98533252014-12-08 17:33:51 +000037#define _MASKED_FIELD(mask, value) ({ \
38 if (__builtin_constant_p(mask)) \
39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40 if (__builtin_constant_p(value)) \
41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
43 BUILD_BUG_ON_MSG((value) & ~(mask), \
44 "Incorrect value for mask"); \
45 (mask) << 16 | (value); })
46#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
48
49
Daniel Vetter6b26c862012-04-24 14:04:12 +020050
Jesse Barnes585fb112008-07-29 11:54:06 -070051/* PCI config space */
52
53#define HPLLCC 0xc0 /* 855 only */
Jesse Barnes652c3932009-08-17 13:31:43 -070054#define GC_CLOCK_CONTROL_MASK (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070055#define GC_CLOCK_133_200 (0 << 0)
56#define GC_CLOCK_100_200 (1 << 0)
57#define GC_CLOCK_100_133 (2 << 0)
58#define GC_CLOCK_166_250 (3 << 0)
Jesse Barnesf97108d2010-01-29 11:27:07 -080059#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070060#define GCFGC 0xf0 /* 915+ only */
61#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
62#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
63#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +020064#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
65#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
66#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
67#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
68#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
69#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070070#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070071#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
72#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
73#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
74#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
75#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
76#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
77#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
78#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
79#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
80#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
81#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
82#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
83#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
84#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
85#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
86#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
87#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Jesse Barnes9f49c372014-12-10 12:16:05 -080090#define GCDGMBUS 0xcc
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +010091#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
92
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070093
94/* Graphics reset regs */
Ville Syrjälä59ea9052014-11-21 21:54:27 +020095#define I915_GDRST 0xc0 /* PCI config register */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070096#define GRDOM_FULL (0<<2)
97#define GRDOM_RENDER (1<<2)
98#define GRDOM_MEDIA (3<<2)
Jesse Barnes8a5c2ae2013-03-28 13:57:19 -070099#define GRDOM_MASK (3<<2)
Ville Syrjälä73bbf6b2014-11-21 21:54:25 +0200100#define GRDOM_RESET_STATUS (1<<1)
Daniel Vetter5ccce182012-04-27 15:17:45 +0200101#define GRDOM_RESET_ENABLE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700102
Ville Syrjäläb3a3f032014-05-19 19:23:24 +0300103#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
104#define ILK_GRDOM_FULL (0<<1)
105#define ILK_GRDOM_RENDER (1<<1)
106#define ILK_GRDOM_MEDIA (3<<1)
107#define ILK_GRDOM_MASK (3<<1)
108#define ILK_GRDOM_RESET_ENABLE (1<<0)
109
Jesse Barnes07b7ddd2011-08-03 11:28:44 -0700110#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
111#define GEN6_MBC_SNPCR_SHIFT 21
112#define GEN6_MBC_SNPCR_MASK (3<<21)
113#define GEN6_MBC_SNPCR_MAX (0<<21)
114#define GEN6_MBC_SNPCR_MED (1<<21)
115#define GEN6_MBC_SNPCR_LOW (2<<21)
116#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
117
Imre Deak9e72b462014-05-05 15:13:55 +0300118#define VLV_G3DCTL 0x9024
119#define VLV_GSCKGCTL 0x9028
120
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100121#define GEN6_MBCTL 0x0907c
122#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
123#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
124#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
125#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
126#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
127
Eric Anholtcff458c2010-11-18 09:31:14 +0800128#define GEN6_GDRST 0x941c
129#define GEN6_GRDOM_FULL (1 << 0)
130#define GEN6_GRDOM_RENDER (1 << 1)
131#define GEN6_GRDOM_MEDIA (1 << 2)
132#define GEN6_GRDOM_BLT (1 << 3)
133
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100134#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
135#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
136#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
137#define PP_DIR_DCLV_2G 0xffffffff
138
Ben Widawsky94e409c2013-11-04 22:29:36 -0800139#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
140#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
141
Jeff McGee0cea6502015-02-13 10:27:56 -0600142#define GEN8_R_PWR_CLK_STATE 0x20C8
143#define GEN8_RPCS_ENABLE (1 << 31)
144#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
145#define GEN8_RPCS_S_CNT_SHIFT 15
146#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
147#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
148#define GEN8_RPCS_SS_CNT_SHIFT 8
149#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
150#define GEN8_RPCS_EU_MAX_SHIFT 4
151#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
152#define GEN8_RPCS_EU_MIN_SHIFT 0
153#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
154
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100155#define GAM_ECOCHK 0x4090
Damien Lespiau81e231a2015-02-09 19:33:19 +0000156#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100157#define ECOCHK_SNB_BIT (1<<10)
Ben Widawskye3dff582013-03-20 14:49:14 -0700158#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100159#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
160#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300161#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
162#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
163#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
164#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
165#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100166
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200167#define GAC_ECO_BITS 0x14090
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300168#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200169#define ECOBITS_PPGTT_CACHE64B (3<<8)
170#define ECOBITS_PPGTT_CACHE4B (0<<8)
171
Daniel Vetterbe901a52012-04-11 20:42:39 +0200172#define GAB_CTL 0x24000
173#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
174
Daniel Vetter40bae732014-09-11 13:28:08 +0200175#define GEN7_BIOS_RESERVED 0x1082C0
176#define GEN7_BIOS_RESERVED_1M (0 << 5)
177#define GEN7_BIOS_RESERVED_256K (1 << 5)
178#define GEN8_BIOS_RESERVED_SHIFT 7
179#define GEN7_BIOS_RESERVED_MASK 0x1
180#define GEN8_BIOS_RESERVED_MASK 0x3
181
182
Jesse Barnes585fb112008-07-29 11:54:06 -0700183/* VGA stuff */
184
185#define VGA_ST01_MDA 0x3ba
186#define VGA_ST01_CGA 0x3da
187
188#define VGA_MSR_WRITE 0x3c2
189#define VGA_MSR_READ 0x3cc
190#define VGA_MSR_MEM_EN (1<<1)
191#define VGA_MSR_CGA_MODE (1<<0)
192
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300193#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100194#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300195#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700196
197#define VGA_AR_INDEX 0x3c0
198#define VGA_AR_VID_EN (1<<5)
199#define VGA_AR_DATA_WRITE 0x3c0
200#define VGA_AR_DATA_READ 0x3c1
201
202#define VGA_GR_INDEX 0x3ce
203#define VGA_GR_DATA 0x3cf
204/* GR05 */
205#define VGA_GR_MEM_READ_MODE_SHIFT 3
206#define VGA_GR_MEM_READ_MODE_PLANE 1
207/* GR06 */
208#define VGA_GR_MEM_MODE_MASK 0xc
209#define VGA_GR_MEM_MODE_SHIFT 2
210#define VGA_GR_MEM_A0000_AFFFF 0
211#define VGA_GR_MEM_A0000_BFFFF 1
212#define VGA_GR_MEM_B0000_B7FFF 2
213#define VGA_GR_MEM_B0000_BFFFF 3
214
215#define VGA_DACMASK 0x3c6
216#define VGA_DACRX 0x3c7
217#define VGA_DACWX 0x3c8
218#define VGA_DACDATA 0x3c9
219
220#define VGA_CR_INDEX_MDA 0x3b4
221#define VGA_CR_DATA_MDA 0x3b5
222#define VGA_CR_INDEX_CGA 0x3d4
223#define VGA_CR_DATA_CGA 0x3d5
224
225/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800226 * Instruction field definitions used by the command parser
227 */
228#define INSTR_CLIENT_SHIFT 29
229#define INSTR_CLIENT_MASK 0xE0000000
230#define INSTR_MI_CLIENT 0x0
231#define INSTR_BC_CLIENT 0x2
232#define INSTR_RC_CLIENT 0x3
233#define INSTR_SUBCLIENT_SHIFT 27
234#define INSTR_SUBCLIENT_MASK 0x18000000
235#define INSTR_MEDIA_SUBCLIENT 0x2
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800236#define INSTR_26_TO_24_MASK 0x7000000
237#define INSTR_26_TO_24_SHIFT 24
Brad Volkin351e3db2014-02-18 10:15:46 -0800238
239/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700240 * Memory interface instructions used by the kernel
241 */
242#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800243/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
244#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700245
246#define MI_NOOP MI_INSTR(0, 0)
247#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
248#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200249#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700250#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
251#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
252#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
253#define MI_FLUSH MI_INSTR(0x04, 0)
254#define MI_READ_FLUSH (1 << 0)
255#define MI_EXE_FLUSH (1 << 1)
256#define MI_NO_WRITE_FLUSH (1 << 2)
257#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
258#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800259#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800260#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
261#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
262#define MI_ARB_ENABLE (1<<0)
263#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700264#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800265#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
266#define MI_SUSPEND_FLUSH_EN (1<<0)
Michael H. Nguyen86ef6302014-11-21 09:35:36 -0800267#define MI_SET_APPID MI_INSTR(0x0e, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400268#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200269#define MI_OVERLAY_CONTINUE (0x0<<21)
270#define MI_OVERLAY_ON (0x1<<21)
271#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700272#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500273#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700274#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500275#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200276/* IVB has funny definitions for which plane to flip. */
277#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
278#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
279#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
280#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
281#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
282#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Damien Lespiau830c81d2014-11-13 17:51:46 +0000283/* SKL ones */
284#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
285#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
286#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
287#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
288#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
289#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
290#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
291#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
292#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700293#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
Ben Widawsky0e792842013-12-16 20:50:37 -0800294#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
295#define MI_SEMAPHORE_UPDATE (1<<21)
296#define MI_SEMAPHORE_COMPARE (1<<20)
297#define MI_SEMAPHORE_REGISTER (1<<18)
298#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
299#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
300#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
301#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
302#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
303#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
304#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
305#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
306#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
307#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
308#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
309#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100310#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
311#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800312#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
313#define MI_MM_SPACE_GTT (1<<8)
314#define MI_MM_SPACE_PHYSICAL (0<<8)
315#define MI_SAVE_EXT_STATE_EN (1<<3)
316#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800317#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800318#define MI_RESTORE_INHIBIT (1<<0)
Ben Widawsky3e789982014-06-30 09:53:37 -0700319#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
320#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
Ben Widawsky5ee426c2014-06-30 09:53:38 -0700321#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
322#define MI_SEMAPHORE_POLL (1<<15)
323#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
Jesse Barnes585fb112008-07-29 11:54:06 -0700324#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
Ville Syrjälä8edfbb82014-11-14 18:16:56 +0200325#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
326#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
327#define MI_USE_GGTT (1 << 22) /* g4x+ */
Jesse Barnes585fb112008-07-29 11:54:06 -0700328#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
329#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000330/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
331 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
332 * simply ignores the register load under certain conditions.
333 * - One can actually load arbitrary many arbitrary registers: Simply issue x
334 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
335 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100336#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100337#define MI_LRI_FORCE_POSTED (1<<12)
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100338#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
Damien Lespiaub76bfeb2014-04-07 20:24:33 +0100339#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800340#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000341#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700342#define MI_FLUSH_DW_STORE_INDEX (1<<21)
343#define MI_INVALIDATE_TLB (1<<18)
344#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800345#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800346#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700347#define MI_INVALIDATE_BSD (1<<7)
348#define MI_FLUSH_DW_USE_GTT (1<<2)
349#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700350#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100351#define MI_BATCH_NON_SECURE (1)
352/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800353#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100354#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800355#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700356#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100357#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700358#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800359
Neil Robertsf1f55cc2014-11-07 19:00:26 +0000360#define MI_PREDICATE_SRC0 (0x2400)
361#define MI_PREDICATE_SRC1 (0x2408)
Rodrigo Vivi94353732013-08-28 16:45:46 -0300362
363#define MI_PREDICATE_RESULT_2 (0x2214)
364#define LOWER_SLICE_ENABLED (1<<0)
365#define LOWER_SLICE_DISABLED (0<<0)
366
Jesse Barnes585fb112008-07-29 11:54:06 -0700367/*
368 * 3D instructions used by the kernel
369 */
370#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
371
372#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
373#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
374#define SC_UPDATE_SCISSOR (0x1<<1)
375#define SC_ENABLE_MASK (0x1<<0)
376#define SC_ENABLE (0x1<<0)
377#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
378#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
379#define SCI_YMIN_MASK (0xffff<<16)
380#define SCI_XMIN_MASK (0xffff<<0)
381#define SCI_YMAX_MASK (0xffff<<16)
382#define SCI_XMAX_MASK (0xffff<<0)
383#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
384#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
385#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
386#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
387#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
388#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
389#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
390#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
391#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100392
393#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
394#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700395#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
396#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100397#define BLT_WRITE_A (2<<20)
398#define BLT_WRITE_RGB (1<<20)
399#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
Jesse Barnes585fb112008-07-29 11:54:06 -0700400#define BLT_DEPTH_8 (0<<24)
401#define BLT_DEPTH_16_565 (1<<24)
402#define BLT_DEPTH_16_1555 (2<<24)
403#define BLT_DEPTH_32 (3<<24)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100404#define BLT_ROP_SRC_COPY (0xcc<<16)
405#define BLT_ROP_COLOR_COPY (0xf0<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700406#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
407#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
408#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
409#define ASYNC_FLIP (1<<22)
410#define DISPLAY_PLANE_A (0<<20)
411#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200412#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200413#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800414#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800415#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200416#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700417#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Chris Wilson148b83d2014-12-16 08:44:31 +0000418#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200419#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800420#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200421#define PIPE_CONTROL_DEPTH_STALL (1<<13)
422#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200423#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200424#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
425#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
426#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
427#define PIPE_CONTROL_NOTIFY (1<<8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700428#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
Jesse Barnes8d315282011-10-16 10:23:31 +0200429#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
430#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
431#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200432#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200433#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700434#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700435
Brad Volkin3a6fa982014-02-18 10:15:47 -0800436/*
437 * Commands used only by the command parser
438 */
439#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
440#define MI_ARB_CHECK MI_INSTR(0x05, 0)
441#define MI_RS_CONTROL MI_INSTR(0x06, 0)
442#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
443#define MI_PREDICATE MI_INSTR(0x0C, 0)
444#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
445#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800446#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800447#define MI_URB_CLEAR MI_INSTR(0x19, 0)
448#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
449#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800450#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
451#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800452#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
453#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
454#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
455#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
456#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
457#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
458
459#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
460#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800461#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
462#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800463#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
464#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
465#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
466 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
467#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
468 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
469#define GFX_OP_3DSTATE_SO_DECL_LIST \
470 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
471
472#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
473 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
474#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
475 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
476#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
477 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
478#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
479 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
480#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
481 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
482
483#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
484
485#define COLOR_BLT ((0x2<<29)|(0x40<<22))
486#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100487
488/*
Brad Volkin5947de92014-02-18 10:15:50 -0800489 * Registers used only by the command parser
490 */
491#define BCS_SWCTRL 0x22200
492
Jordan Justenc61200c2014-12-11 13:28:09 -0800493#define GPGPU_THREADS_DISPATCHED 0x2290
494#define HS_INVOCATION_COUNT 0x2300
495#define DS_INVOCATION_COUNT 0x2308
496#define IA_VERTICES_COUNT 0x2310
497#define IA_PRIMITIVES_COUNT 0x2318
498#define VS_INVOCATION_COUNT 0x2320
499#define GS_INVOCATION_COUNT 0x2328
500#define GS_PRIMITIVES_COUNT 0x2330
501#define CL_INVOCATION_COUNT 0x2338
502#define CL_PRIMITIVES_COUNT 0x2340
503#define PS_INVOCATION_COUNT 0x2348
504#define PS_DEPTH_COUNT 0x2350
Brad Volkin5947de92014-02-18 10:15:50 -0800505
506/* There are the 4 64-bit counter registers, one for each stream output */
507#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
508
Brad Volkin113a0472014-04-08 14:18:58 -0700509#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
510
511#define GEN7_3DPRIM_END_OFFSET 0x2420
512#define GEN7_3DPRIM_START_VERTEX 0x2430
513#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
514#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
515#define GEN7_3DPRIM_START_INSTANCE 0x243C
516#define GEN7_3DPRIM_BASE_VERTEX 0x2440
517
Kenneth Graunke180b8132014-03-25 22:52:03 -0700518#define OACONTROL 0x2360
519
Brad Volkin220375a2014-02-18 10:15:51 -0800520#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
521#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
522#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
523 _GEN7_PIPEA_DE_LOAD_SL, \
524 _GEN7_PIPEB_DE_LOAD_SL)
525
Brad Volkin5947de92014-02-18 10:15:50 -0800526/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100527 * Reset registers
528 */
529#define DEBUG_RESET_I830 0x6070
530#define DEBUG_RESET_FULL (1<<7)
531#define DEBUG_RESET_RENDER (1<<8)
532#define DEBUG_RESET_DISPLAY (1<<9)
533
Jesse Barnes57f350b2012-03-28 13:39:25 -0700534/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300535 * IOSF sideband
536 */
537#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
538#define IOSF_DEVFN_SHIFT 24
539#define IOSF_OPCODE_SHIFT 16
540#define IOSF_PORT_SHIFT 8
541#define IOSF_BYTE_ENABLES_SHIFT 4
542#define IOSF_BAR_SHIFT 1
543#define IOSF_SB_BUSY (1<<0)
Jesse Barnesf3419152013-11-04 11:52:44 -0800544#define IOSF_PORT_BUNIT 0x3
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300545#define IOSF_PORT_PUNIT 0x4
546#define IOSF_PORT_NC 0x11
547#define IOSF_PORT_DPIO 0x12
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300548#define IOSF_PORT_DPIO_2 0x1a
Jani Nikulae9f882a2013-08-27 15:12:14 +0300549#define IOSF_PORT_GPIO_NC 0x13
550#define IOSF_PORT_CCK 0x14
551#define IOSF_PORT_CCU 0xA9
552#define IOSF_PORT_GPS_CORE 0x48
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530553#define IOSF_PORT_FLISDSI 0x1B
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300554#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
555#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
556
Jesse Barnes30a970c2013-11-04 13:48:12 -0800557/* See configdb bunit SB addr map */
558#define BUNIT_REG_BISOC 0x11
559
Jesse Barnes30a970c2013-11-04 13:48:12 -0800560#define PUNIT_REG_DSPFREQ 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +0300561#define DSPFREQSTAT_SHIFT_CHV 24
562#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
563#define DSPFREQGUAR_SHIFT_CHV 8
564#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800565#define DSPFREQSTAT_SHIFT 30
566#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
567#define DSPFREQGUAR_SHIFT 14
568#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjäläcfb41412015-03-05 21:19:51 +0200569#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
570#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
571#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
Ville Syrjälä26972b02014-06-28 02:04:11 +0300572#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
573#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
574#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
575#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
576#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
577#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
578#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
579#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
580#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
581#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
582#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
583#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +0200584
585/* See the PUNIT HAS v0.8 for the below bits */
586enum punit_power_well {
587 PUNIT_POWER_WELL_RENDER = 0,
588 PUNIT_POWER_WELL_MEDIA = 1,
589 PUNIT_POWER_WELL_DISP2D = 3,
590 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
591 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
592 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
593 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
594 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
595 PUNIT_POWER_WELL_DPIO_RX0 = 10,
596 PUNIT_POWER_WELL_DPIO_RX1 = 11,
Ville Syrjälä5d6f7ea2014-06-28 02:04:08 +0300597 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
Ville Syrjälä2ce147f2014-06-28 02:04:13 +0300598 /* FIXME: guesswork below */
599 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
600 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
601 PUNIT_POWER_WELL_DPIO_RX2 = 15,
Imre Deaka30180a2014-03-04 19:23:02 +0200602
603 PUNIT_POWER_WELL_NUM,
604};
605
Satheeshakrishna M94dd5132015-02-04 13:57:44 +0000606enum skl_disp_power_wells {
607 SKL_DISP_PW_MISC_IO,
608 SKL_DISP_PW_DDI_A_E,
609 SKL_DISP_PW_DDI_B,
610 SKL_DISP_PW_DDI_C,
611 SKL_DISP_PW_DDI_D,
612 SKL_DISP_PW_1 = 14,
613 SKL_DISP_PW_2,
614};
615
616#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
617#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
618
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800619#define PUNIT_REG_PWRGT_CTRL 0x60
620#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +0200621#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
622#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
623#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
624#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
625#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800626
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300627#define PUNIT_REG_GPU_LFM 0xd3
628#define PUNIT_REG_GPU_FREQ_REQ 0xd4
629#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläc8e96272014-11-07 21:33:44 +0200630#define GPLLENABLE (1<<4)
Ville Syrjäläe8474402013-06-26 17:43:24 +0300631#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300632#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -0400633#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300634
635#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
636#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
637
Deepak S095acd52015-01-17 11:05:59 +0530638#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
639#define FB_GFX_FREQ_FUSE_MASK 0xff
640#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
641#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
642#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
643
644#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
645#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
646
Ville Syrjäläfc1ac8d2015-03-05 21:19:52 +0200647#define PUNIT_REG_DDR_SETUP2 0x139
648#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
649#define FORCE_DDR_LOW_FREQ (1 << 1)
650#define FORCE_DDR_HIGH_FREQ (1 << 0)
651
Deepak S2b6b3a02014-05-27 15:59:30 +0530652#define PUNIT_GPU_STATUS_REG 0xdb
653#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
654#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
655#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
656#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
657
658#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
659#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
660#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
661
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300662#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
663#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
664#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
665#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
666#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
667#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
668#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
669#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
670#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
671#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
672
Deepak S31685c22014-07-03 17:33:01 -0400673#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
674#define VLV_RP_UP_EI_THRESHOLD 90
675#define VLV_RP_DOWN_EI_THRESHOLD 70
Deepak S31685c22014-07-03 17:33:01 -0400676
ymohanmabe4fc042013-08-27 23:40:56 +0300677/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800678#define CCK_FUSE_REG 0x8
679#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300680#define CCK_REG_DSI_PLL_FUSE 0x44
681#define CCK_REG_DSI_PLL_CONTROL 0x48
682#define DSI_PLL_VCO_EN (1 << 31)
683#define DSI_PLL_LDO_GATE (1 << 30)
684#define DSI_PLL_P1_POST_DIV_SHIFT 17
685#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
686#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
687#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
688#define DSI_PLL_MUX_MASK (3 << 9)
689#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
690#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
691#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
692#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
693#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
694#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
695#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
696#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
697#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
698#define DSI_PLL_LOCK (1 << 0)
699#define CCK_REG_DSI_PLL_DIVIDER 0x4c
700#define DSI_PLL_LFSR (1 << 31)
701#define DSI_PLL_FRACTION_EN (1 << 30)
702#define DSI_PLL_FRAC_COUNTER_SHIFT 27
703#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
704#define DSI_PLL_USYNC_CNT_SHIFT 18
705#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
706#define DSI_PLL_N1_DIV_SHIFT 16
707#define DSI_PLL_N1_DIV_MASK (3 << 16)
708#define DSI_PLL_M1_DIV_SHIFT 0
709#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800710#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä9cf33db2014-06-13 13:37:48 +0300711#define DISPLAY_TRUNK_FORCE_ON (1 << 17)
712#define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
713#define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
714#define DISPLAY_FREQUENCY_STATUS_SHIFT 8
715#define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +0300716
Ville Syrjälä0e767182014-04-25 20:14:31 +0300717/**
718 * DOC: DPIO
719 *
720 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
721 * ports. DPIO is the name given to such a display PHY. These PHYs
722 * don't follow the standard programming model using direct MMIO
723 * registers, and instead their registers must be accessed trough IOSF
724 * sideband. VLV has one such PHY for driving ports B and C, and CHV
725 * adds another PHY for driving port D. Each PHY responds to specific
726 * IOSF-SB port.
727 *
728 * Each display PHY is made up of one or two channels. Each channel
729 * houses a common lane part which contains the PLL and other common
730 * logic. CH0 common lane also contains the IOSF-SB logic for the
731 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
732 * must be running when any DPIO registers are accessed.
733 *
734 * In addition to having their own registers, the PHYs are also
735 * controlled through some dedicated signals from the display
736 * controller. These include PLL reference clock enable, PLL enable,
737 * and CRI clock selection, for example.
738 *
739 * Eeach channel also has two splines (also called data lanes), and
740 * each spline is made up of one Physical Access Coding Sub-Layer
741 * (PCS) block and two TX lanes. So each channel has two PCS blocks
742 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
743 * data/clock pairs depending on the output type.
744 *
745 * Additionally the PHY also contains an AUX lane with AUX blocks
746 * for each channel. This is used for DP AUX communication, but
747 * this fact isn't really relevant for the driver since AUX is
748 * controlled from the display controller side. No DPIO registers
749 * need to be accessed during AUX communication,
750 *
751 * Generally the common lane corresponds to the pipe and
Masanari Iida32197aa2014-10-20 23:53:13 +0900752 * the spline (PCS/TX) corresponds to the port.
Ville Syrjälä0e767182014-04-25 20:14:31 +0300753 *
754 * For dual channel PHY (VLV/CHV):
755 *
756 * pipe A == CMN/PLL/REF CH0
757 *
758 * pipe B == CMN/PLL/REF CH1
759 *
760 * port B == PCS/TX CH0
761 *
762 * port C == PCS/TX CH1
763 *
764 * This is especially important when we cross the streams
765 * ie. drive port B with pipe B, or port C with pipe A.
766 *
767 * For single channel PHY (CHV):
768 *
769 * pipe C == CMN/PLL/REF CH0
770 *
771 * port D == PCS/TX CH0
772 *
773 * Note: digital port B is DDI0, digital port C is DDI1,
774 * digital port D is DDI2
775 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300776/*
Ville Syrjälä0e767182014-04-25 20:14:31 +0300777 * Dual channel PHY (VLV/CHV)
778 * ---------------------------------
779 * | CH0 | CH1 |
780 * | CMN/PLL/REF | CMN/PLL/REF |
781 * |---------------|---------------| Display PHY
782 * | PCS01 | PCS23 | PCS01 | PCS23 |
783 * |-------|-------|-------|-------|
784 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
785 * ---------------------------------
786 * | DDI0 | DDI1 | DP/HDMI ports
787 * ---------------------------------
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200788 *
Ville Syrjälä0e767182014-04-25 20:14:31 +0300789 * Single channel PHY (CHV)
790 * -----------------
791 * | CH0 |
792 * | CMN/PLL/REF |
793 * |---------------| Display PHY
794 * | PCS01 | PCS23 |
795 * |-------|-------|
796 * |TX0|TX1|TX2|TX3|
797 * -----------------
798 * | DDI2 | DP/HDMI port
799 * -----------------
Jesse Barnes57f350b2012-03-28 13:39:25 -0700800 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300801#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300802
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200803#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700804#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
805#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
806#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700807#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700808
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800809#define DPIO_PHY(pipe) ((pipe) >> 1)
810#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
811
Daniel Vetter598fac62013-04-18 22:01:46 +0200812/*
813 * Per pipe/PLL DPIO regs
814 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800815#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -0700816#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200817#define DPIO_POST_DIV_DAC 0
818#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
819#define DPIO_POST_DIV_LVDS1 2
820#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700821#define DPIO_K_SHIFT (24) /* 4 bits */
822#define DPIO_P1_SHIFT (21) /* 3 bits */
823#define DPIO_P2_SHIFT (16) /* 5 bits */
824#define DPIO_N_SHIFT (12) /* 4 bits */
825#define DPIO_ENABLE_CALIBRATION (1<<11)
826#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
827#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800828#define _VLV_PLL_DW3_CH1 0x802c
829#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700830
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800831#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -0700832#define DPIO_REFSEL_OVERRIDE 27
833#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
834#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
835#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530836#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700837#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
838#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800839#define _VLV_PLL_DW5_CH1 0x8034
840#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700841
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800842#define _VLV_PLL_DW7_CH0 0x801c
843#define _VLV_PLL_DW7_CH1 0x803c
844#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700845
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800846#define _VLV_PLL_DW8_CH0 0x8040
847#define _VLV_PLL_DW8_CH1 0x8060
848#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200849
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800850#define VLV_PLL_DW9_BCAST 0xc044
851#define _VLV_PLL_DW9_CH0 0x8044
852#define _VLV_PLL_DW9_CH1 0x8064
853#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200854
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800855#define _VLV_PLL_DW10_CH0 0x8048
856#define _VLV_PLL_DW10_CH1 0x8068
857#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200858
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800859#define _VLV_PLL_DW11_CH0 0x804c
860#define _VLV_PLL_DW11_CH1 0x806c
861#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700862
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800863/* Spec for ref block start counts at DW10 */
864#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +0200865
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800866#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100867
Daniel Vetter598fac62013-04-18 22:01:46 +0200868/*
869 * Per DDI channel DPIO regs
870 */
871
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800872#define _VLV_PCS_DW0_CH0 0x8200
873#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +0200874#define DPIO_PCS_TX_LANE2_RESET (1<<16)
875#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300876#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
877#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800878#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200879
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300880#define _VLV_PCS01_DW0_CH0 0x200
881#define _VLV_PCS23_DW0_CH0 0x400
882#define _VLV_PCS01_DW0_CH1 0x2600
883#define _VLV_PCS23_DW0_CH1 0x2800
884#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
885#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
886
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800887#define _VLV_PCS_DW1_CH0 0x8204
888#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +0300889#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +0200890#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
891#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
892#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
893#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800894#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200895
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300896#define _VLV_PCS01_DW1_CH0 0x204
897#define _VLV_PCS23_DW1_CH0 0x404
898#define _VLV_PCS01_DW1_CH1 0x2604
899#define _VLV_PCS23_DW1_CH1 0x2804
900#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
901#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
902
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800903#define _VLV_PCS_DW8_CH0 0x8220
904#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +0300905#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
906#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800907#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200908
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800909#define _VLV_PCS01_DW8_CH0 0x0220
910#define _VLV_PCS23_DW8_CH0 0x0420
911#define _VLV_PCS01_DW8_CH1 0x2620
912#define _VLV_PCS23_DW8_CH1 0x2820
913#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
914#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200915
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800916#define _VLV_PCS_DW9_CH0 0x8224
917#define _VLV_PCS_DW9_CH1 0x8424
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300918#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
919#define DPIO_PCS_TX2MARGIN_000 (0<<13)
920#define DPIO_PCS_TX2MARGIN_101 (1<<13)
921#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
922#define DPIO_PCS_TX1MARGIN_000 (0<<10)
923#define DPIO_PCS_TX1MARGIN_101 (1<<10)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800924#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200925
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300926#define _VLV_PCS01_DW9_CH0 0x224
927#define _VLV_PCS23_DW9_CH0 0x424
928#define _VLV_PCS01_DW9_CH1 0x2624
929#define _VLV_PCS23_DW9_CH1 0x2824
930#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
931#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
932
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300933#define _CHV_PCS_DW10_CH0 0x8228
934#define _CHV_PCS_DW10_CH1 0x8428
935#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
936#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +0300937#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
938#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
939#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
940#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
941#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
942#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300943#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
944
Ville Syrjälä1966e592014-04-09 13:29:04 +0300945#define _VLV_PCS01_DW10_CH0 0x0228
946#define _VLV_PCS23_DW10_CH0 0x0428
947#define _VLV_PCS01_DW10_CH1 0x2628
948#define _VLV_PCS23_DW10_CH1 0x2828
949#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
950#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
951
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800952#define _VLV_PCS_DW11_CH0 0x822c
953#define _VLV_PCS_DW11_CH1 0x842c
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300954#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
955#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
956#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800957#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200958
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300959#define _VLV_PCS01_DW11_CH0 0x022c
960#define _VLV_PCS23_DW11_CH0 0x042c
961#define _VLV_PCS01_DW11_CH1 0x262c
962#define _VLV_PCS23_DW11_CH1 0x282c
Ville Syrjälä142d2ec2014-10-16 20:52:32 +0300963#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
964#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
Ville Syrjälä570e2a72014-08-18 14:42:46 +0300965
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800966#define _VLV_PCS_DW12_CH0 0x8230
967#define _VLV_PCS_DW12_CH1 0x8430
968#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200969
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800970#define _VLV_PCS_DW14_CH0 0x8238
971#define _VLV_PCS_DW14_CH1 0x8438
972#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200973
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800974#define _VLV_PCS_DW23_CH0 0x825c
975#define _VLV_PCS_DW23_CH1 0x845c
976#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200977
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800978#define _VLV_TX_DW2_CH0 0x8288
979#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300980#define DPIO_SWING_MARGIN000_SHIFT 16
981#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300982#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800983#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200984
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800985#define _VLV_TX_DW3_CH0 0x828c
986#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300987/* The following bit for CHV phy */
988#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300989#define DPIO_SWING_MARGIN101_SHIFT 16
990#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800991#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
992
993#define _VLV_TX_DW4_CH0 0x8290
994#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300995#define DPIO_SWING_DEEMPH9P5_SHIFT 24
996#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300997#define DPIO_SWING_DEEMPH6P0_SHIFT 16
998#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800999#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1000
1001#define _VLV_TX3_DW4_CH0 0x690
1002#define _VLV_TX3_DW4_CH1 0x2a90
1003#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1004
1005#define _VLV_TX_DW5_CH0 0x8294
1006#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +02001007#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001008#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001009
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001010#define _VLV_TX_DW11_CH0 0x82ac
1011#define _VLV_TX_DW11_CH1 0x84ac
1012#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +02001013
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001014#define _VLV_TX_DW14_CH0 0x82b8
1015#define _VLV_TX_DW14_CH1 0x84b8
1016#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +05301017
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001018/* CHV dpPhy registers */
1019#define _CHV_PLL_DW0_CH0 0x8000
1020#define _CHV_PLL_DW0_CH1 0x8180
1021#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1022
1023#define _CHV_PLL_DW1_CH0 0x8004
1024#define _CHV_PLL_DW1_CH1 0x8184
1025#define DPIO_CHV_N_DIV_SHIFT 8
1026#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1027#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1028
1029#define _CHV_PLL_DW2_CH0 0x8008
1030#define _CHV_PLL_DW2_CH1 0x8188
1031#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1032
1033#define _CHV_PLL_DW3_CH0 0x800c
1034#define _CHV_PLL_DW3_CH1 0x818c
1035#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1036#define DPIO_CHV_FIRST_MOD (0 << 8)
1037#define DPIO_CHV_SECOND_MOD (1 << 8)
1038#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05301039#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001040#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1041
1042#define _CHV_PLL_DW6_CH0 0x8018
1043#define _CHV_PLL_DW6_CH1 0x8198
1044#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1045#define DPIO_CHV_INT_COEFF_SHIFT 8
1046#define DPIO_CHV_PROP_COEFF_SHIFT 0
1047#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1048
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301049#define _CHV_PLL_DW8_CH0 0x8020
1050#define _CHV_PLL_DW8_CH1 0x81A0
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05301051#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1052#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301053#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1054
1055#define _CHV_PLL_DW9_CH0 0x8024
1056#define _CHV_PLL_DW9_CH1 0x81A4
1057#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05301058#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
Vijay Purushothamand3eee4b2015-02-16 15:07:58 +05301059#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1060#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1061
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001062#define _CHV_CMN_DW5_CH0 0x8114
1063#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1064#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1065#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1066#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1067#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1068#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1069#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1070#define CHV_BUFLEFTENA1_MASK (3 << 22)
1071
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001072#define _CHV_CMN_DW13_CH0 0x8134
1073#define _CHV_CMN_DW0_CH1 0x8080
1074#define DPIO_CHV_S1_DIV_SHIFT 21
1075#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1076#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1077#define DPIO_CHV_K_DIV_SHIFT 4
1078#define DPIO_PLL_FREQLOCK (1 << 1)
1079#define DPIO_PLL_LOCK (1 << 0)
1080#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1081
1082#define _CHV_CMN_DW14_CH0 0x8138
1083#define _CHV_CMN_DW1_CH1 0x8084
1084#define DPIO_AFC_RECAL (1 << 14)
1085#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03001086#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1087#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1088#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1089#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1090#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1091#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1092#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1093#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001094#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1095
Ville Syrjälä9197c882014-04-09 13:29:05 +03001096#define _CHV_CMN_DW19_CH0 0x814c
1097#define _CHV_CMN_DW6_CH1 0x8098
1098#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1099#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1100
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001101#define CHV_CMN_DW30 0x8178
1102#define DPIO_LRC_BYPASS (1 << 3)
1103
1104#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1105 (lane) * 0x200 + (offset))
1106
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03001107#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1108#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1109#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1110#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1111#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1112#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1113#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1114#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1115#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1116#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1117#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001118#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1119#define DPIO_FRC_LATENCY_SHFIT 8
1120#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1121#define DPIO_UPAR_SHIFT 30
Jesse Barnes585fb112008-07-29 11:54:06 -07001122/*
Jesse Barnesde151cf2008-11-12 10:03:55 -08001123 * Fence registers
1124 */
1125#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -07001126#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -08001127#define I830_FENCE_START_MASK 0x07f80000
1128#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -08001129#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001130#define I830_FENCE_PITCH_SHIFT 4
1131#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02001132#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07001133#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001134#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001135
1136#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08001137#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001138
1139#define FENCE_REG_965_0 0x03000
1140#define I965_FENCE_PITCH_SHIFT 2
1141#define I965_FENCE_TILING_Y_SHIFT 1
1142#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001143#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08001144
Eric Anholt4e901fd2009-10-26 16:44:17 -07001145#define FENCE_REG_SANDYBRIDGE_0 0x100000
1146#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03001147#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07001148
Deepak S2b6b3a02014-05-27 15:59:30 +05301149
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001150/* control register for cpu gtt access */
1151#define TILECTL 0x101000
1152#define TILECTL_SWZCTL (1 << 0)
1153#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1154#define TILECTL_BACKSNOOP_DIS (1 << 3)
1155
Jesse Barnesde151cf2008-11-12 10:03:55 -08001156/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001157 * Instruction and interrupt control regs
1158 */
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03001159#define PGTBL_CTL 0x02020
1160#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1161#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001162#define PGTBL_ER 0x02024
Ville Syrjälä81e7f202014-08-15 01:21:55 +03001163#define PRB0_BASE (0x2030-0x30)
1164#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1165#define PRB2_BASE (0x2050-0x30) /* gen3 */
1166#define SRB0_BASE (0x2100-0x30) /* gen2 */
1167#define SRB1_BASE (0x2110-0x30) /* gen2 */
1168#define SRB2_BASE (0x2120-0x30) /* 830 */
1169#define SRB3_BASE (0x2130-0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02001170#define RENDER_RING_BASE 0x02000
1171#define BSD_RING_BASE 0x04000
1172#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08001173#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -07001174#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +01001175#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +02001176#define RING_TAIL(base) ((base)+0x30)
1177#define RING_HEAD(base) ((base)+0x34)
1178#define RING_START(base) ((base)+0x38)
1179#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001180#define RING_SYNC_0(base) ((base)+0x40)
1181#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawsky1950de12013-05-28 19:22:20 -07001182#define RING_SYNC_2(base) ((base)+0x48)
1183#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1184#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1185#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1186#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1187#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1188#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1189#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1190#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1191#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1192#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1193#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1194#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ben Widawskyad776f82013-05-28 19:22:18 -07001195#define GEN6_NOSYNC 0
Chris Wilson2c550182014-12-16 10:02:27 +00001196#define RING_PSMI_CTL(base) ((base)+0x50)
Chris Wilson8fd26852010-12-08 18:40:43 +00001197#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001198#define RING_HWS_PGA(base) ((base)+0x80)
1199#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Imre Deak9e72b462014-05-05 15:13:55 +03001200
1201#define GEN7_WR_WATERMARK 0x4028
1202#define GEN7_GFX_PRIO_CTRL 0x402C
1203#define ARB_MODE 0x4030
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001204#define ARB_MODE_SWIZZLE_SNB (1<<4)
1205#define ARB_MODE_SWIZZLE_IVB (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03001206#define GEN7_GFX_PEND_TLB0 0x4034
1207#define GEN7_GFX_PEND_TLB1 0x4038
1208/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1209#define GEN7_LRA_LIMITS_BASE 0x403C
1210#define GEN7_LRA_LIMITS_REG_NUM 13
1211#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1212#define GEN7_GFX_MAX_REQ_COUNT 0x4074
1213
Ben Widawsky31a53362013-11-02 21:07:04 -07001214#define GAMTARBMODE 0x04a08
Ben Widawsky4afe8d32013-11-02 21:07:55 -07001215#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07001216#define ARB_MODE_SWIZZLE_BDW (1<<1)
Eric Anholt45930102011-05-06 17:12:35 -07001217#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001218#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -07001219#define RING_FAULT_GTTSEL_MASK (1<<11)
1220#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1221#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1222#define RING_FAULT_VALID (1<<0)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001223#define DONE_REG 0x40b0
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001224#define GEN8_PRIVATE_PAT 0x40e0
Eric Anholt45930102011-05-06 17:12:35 -07001225#define BSD_HWS_PGA_GEN7 (0x04180)
1226#define BLT_HWS_PGA_GEN7 (0x04280)
Ben Widawsky9a8a2212013-05-28 19:22:23 -07001227#define VEBOX_HWS_PGA_GEN7 (0x04380)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001228#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson50877442014-03-21 12:41:53 +00001229#define RING_ACTHD_UDW(base) ((base)+0x5c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001230#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +00001231#define RING_IMR(base) ((base)+0xa8)
Oscar Mateo73d477f2014-07-24 17:04:31 +01001232#define RING_HWSTAM(base) ((base)+0x98)
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001233#define RING_TIMESTAMP(base) ((base)+0x358)
Jesse Barnes585fb112008-07-29 11:54:06 -07001234#define TAIL_ADDR 0x001FFFF8
1235#define HEAD_WRAP_COUNT 0xFFE00000
1236#define HEAD_WRAP_ONE 0x00200000
1237#define HEAD_ADDR 0x001FFFFC
1238#define RING_NR_PAGES 0x001FF000
1239#define RING_REPORT_MASK 0x00000006
1240#define RING_REPORT_64K 0x00000002
1241#define RING_REPORT_128K 0x00000004
1242#define RING_NO_REPORT 0x00000000
1243#define RING_VALID_MASK 0x00000001
1244#define RING_VALID 0x00000001
1245#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01001246#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1247#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001248#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03001249
1250#define GEN7_TLB_RD_ADDR 0x4700
1251
Chris Wilson8168bd42010-11-11 17:54:52 +00001252#if 0
1253#define PRB0_TAIL 0x02030
1254#define PRB0_HEAD 0x02034
1255#define PRB0_START 0x02038
1256#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -07001257#define PRB1_TAIL 0x02040 /* 915+ only */
1258#define PRB1_HEAD 0x02044 /* 915+ only */
1259#define PRB1_START 0x02048 /* 915+ only */
1260#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00001261#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001262#define IPEIR_I965 0x02064
1263#define IPEHR_I965 0x02068
1264#define INSTDONE_I965 0x0206c
Ben Widawskyd53bd482012-08-22 11:32:14 -07001265#define GEN7_INSTDONE_1 0x0206c
1266#define GEN7_SC_INSTDONE 0x07100
1267#define GEN7_SAMPLER_INSTDONE 0x0e160
1268#define GEN7_ROW_INSTDONE 0x0e164
1269#define I915_NUM_INSTDONE_REG 4
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001270#define RING_IPEIR(base) ((base)+0x64)
1271#define RING_IPEHR(base) ((base)+0x68)
1272#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001273#define RING_INSTPS(base) ((base)+0x70)
1274#define RING_DMA_FADD(base) ((base)+0x78)
Ben Widawsky13ffadd2014-04-01 16:31:07 -07001275#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001276#define RING_INSTPM(base) ((base)+0xc0)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301277#define RING_MI_MODE(base) ((base)+0x9c)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001278#define INSTPS 0x02070 /* 965+ only */
1279#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001280#define ACTHD_I965 0x02074
1281#define HWS_PGA 0x02080
1282#define HWS_ADDRESS_MASK 0xfffff000
1283#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -07001284#define PWRCTXA 0x2088 /* 965GM+ only */
1285#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001286#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001287#define IPEHR 0x0208c
1288#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -07001289#define NOPID 0x02094
1290#define HWSTAM 0x02098
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001291#define DMA_FADD_I8XX 0x020d0
Chris Wilson94e39e22013-10-30 09:28:22 +00001292#define RING_BBSTATE(base) ((base)+0x110)
Ville Syrjälä3dda20a2013-12-10 21:44:43 +02001293#define RING_BBADDR(base) ((base)+0x140)
1294#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08001295
Chris Wilsonf4068392010-10-27 20:36:41 +01001296#define ERROR_GEN6 0x040a0
Ben Widawsky71e172e2012-08-20 16:15:13 -07001297#define GEN7_ERR_INT 0x44040
Paulo Zanonide032bf2013-04-12 17:57:58 -03001298#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03001299#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001300#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03001301#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001302#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03001303#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001304#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001305#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03001306#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Daniel Vetter7336df62013-07-09 22:59:16 +02001307#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01001308
Mika Kuoppala6c826f32015-03-24 14:54:19 +02001309#define GEN8_FAULT_TLB_DATA0 0x04b10
1310#define GEN8_FAULT_TLB_DATA1 0x04b14
1311
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03001312#define FPGA_DBG 0x42300
1313#define FPGA_DBG_RM_NOCLAIM (1<<31)
1314
Chris Wilson0f3b6842013-01-15 12:05:55 +00001315#define DERRMR 0x44050
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001316/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01001317#define DERRMR_PIPEA_SCANLINE (1<<0)
1318#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1319#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1320#define DERRMR_PIPEA_VBLANK (1<<3)
1321#define DERRMR_PIPEA_HBLANK (1<<5)
1322#define DERRMR_PIPEB_SCANLINE (1<<8)
1323#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1324#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1325#define DERRMR_PIPEB_VBLANK (1<<11)
1326#define DERRMR_PIPEB_HBLANK (1<<13)
1327/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1328#define DERRMR_PIPEC_SCANLINE (1<<14)
1329#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1330#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1331#define DERRMR_PIPEC_VBLANK (1<<21)
1332#define DERRMR_PIPEC_HBLANK (1<<22)
1333
Chris Wilson0f3b6842013-01-15 12:05:55 +00001334
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001335/* GM45+ chicken bits -- debug workaround bits that may be required
1336 * for various sorts of correct behavior. The top 16 bits of each are
1337 * the enables for writing to the corresponding low bit.
1338 */
1339#define _3D_CHICKEN 0x02084
Daniel Vetter42839082012-12-14 23:38:28 +01001340#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001341#define _3D_CHICKEN2 0x0208c
1342/* Disables pipelining of read flushes past the SF-WIZ interface.
1343 * Required on all Ironlake steppings according to the B-Spec, but the
1344 * particular danger of not doing so is not specified.
1345 */
1346# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1347#define _3D_CHICKEN3 0x02090
Jesse Barnes87f80202012-10-02 17:43:41 -05001348#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07001349#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02001350#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1351#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001352
Eric Anholt71cf39b2010-03-08 23:41:55 -08001353#define MI_MODE 0x0209c
1354# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08001355# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00001356# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301357# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01001358# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001359
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001360#define GEN6_GT_MODE 0x20d0
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02001361#define GEN7_GT_MODE 0x7008
Ville Syrjälä8d85d272014-02-04 21:59:15 +02001362#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1363#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1364#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1365#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
Damien Lespiau98533252014-12-08 17:33:51 +00001366#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001367#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Damien Lespiaub7668792015-02-14 18:30:29 +00001368#define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2))
1369#define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2))
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001370
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001371#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -07001372#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +01001373#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001374#define GFX_RUN_LIST_ENABLE (1<<15)
Chris Wilsonaa83e302014-03-21 17:18:54 +00001375#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001376#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1377#define GFX_REPLAY_MODE (1<<11)
1378#define GFX_PSMI_GRANULARITY (1<<10)
1379#define GFX_PPGTT_ENABLE (1<<9)
1380
Daniel Vettera7e806d2012-07-11 16:27:55 +02001381#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301382#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Daniel Vettera7e806d2012-07-11 16:27:55 +02001383
Imre Deak9e72b462014-05-05 15:13:55 +03001384#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1385#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
Jesse Barnes585fb112008-07-29 11:54:06 -07001386#define SCPD0 0x0209c /* 915+ only */
1387#define IER 0x020a0
1388#define IIR 0x020a4
1389#define IMR 0x020a8
1390#define ISR 0x020ac
Ville Syrjälä07ec7ec2013-01-24 15:29:51 +02001391#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001392#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07001393#define GCFG_DIS (1<<8)
Imre Deak9e72b462014-05-05 15:13:55 +03001394#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
Ville Syrjäläff763012013-01-24 15:29:52 +02001395#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1396#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1397#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1398#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1399#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001400#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05301401#define VLV_PCBR_ADDR_SHIFT 12
1402
Ville Syrjälä90a72f82013-02-19 23:16:44 +02001403#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001404#define EIR 0x020b0
1405#define EMR 0x020b4
1406#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001407#define GM45_ERROR_PAGE_TABLE (1<<5)
1408#define GM45_ERROR_MEM_PRIV (1<<4)
1409#define I915_ERROR_PAGE_TABLE (1<<4)
1410#define GM45_ERROR_CP_PRIV (1<<3)
1411#define I915_ERROR_MEMORY_REFRESH (1<<1)
1412#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001413#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +08001414#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02001415#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00001416 will not assert AGPBUSY# and will only
1417 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08001418#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01001419#define INSTPM_TLB_INVALIDATE (1<<9)
1420#define INSTPM_SYNC_FLUSH (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001421#define ACTHD 0x020c8
Ville Syrjälä10383922014-08-15 01:21:54 +03001422#define MEM_MODE 0x020cc
1423#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1424#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1425#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001426#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +00001427#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -07001428#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08001429#define FW_BLC_SELF_EN_MASK (1<<31)
1430#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1431#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001432#define MM_BURST_LENGTH 0x00700000
1433#define MM_FIFO_WATERMARK 0x0001F000
1434#define LM_BURST_LENGTH 0x00000700
1435#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -07001436#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07001437
1438/* Make render/texture TLB fetches lower priorty than associated data
1439 * fetches. This is not turned on by default
1440 */
1441#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1442
1443/* Isoch request wait on GTT enable (Display A/B/C streams).
1444 * Make isoch requests stall on the TLB update. May cause
1445 * display underruns (test mode only)
1446 */
1447#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1448
1449/* Block grant count for isoch requests when block count is
1450 * set to a finite value.
1451 */
1452#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1453#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1454#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1455#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1456#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1457
1458/* Enable render writes to complete in C2/C3/C4 power states.
1459 * If this isn't enabled, render writes are prevented in low
1460 * power states. That seems bad to me.
1461 */
1462#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1463
1464/* This acknowledges an async flip immediately instead
1465 * of waiting for 2TLB fetches.
1466 */
1467#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1468
1469/* Enables non-sequential data reads through arbiter
1470 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001471#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07001472
1473/* Disable FSB snooping of cacheable write cycles from binner/render
1474 * command stream
1475 */
1476#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1477
1478/* Arbiter time slice for non-isoch streams */
1479#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1480#define MI_ARB_TIME_SLICE_1 (0 << 5)
1481#define MI_ARB_TIME_SLICE_2 (1 << 5)
1482#define MI_ARB_TIME_SLICE_4 (2 << 5)
1483#define MI_ARB_TIME_SLICE_6 (3 << 5)
1484#define MI_ARB_TIME_SLICE_8 (4 << 5)
1485#define MI_ARB_TIME_SLICE_10 (5 << 5)
1486#define MI_ARB_TIME_SLICE_14 (6 << 5)
1487#define MI_ARB_TIME_SLICE_16 (7 << 5)
1488
1489/* Low priority grace period page size */
1490#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1491#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1492
1493/* Disable display A/B trickle feed */
1494#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1495
1496/* Set display plane priority */
1497#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1498#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1499
Ville Syrjälä54e472a2014-02-25 15:13:40 +02001500#define MI_STATE 0x020e4 /* gen2 only */
1501#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1502#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1503
Jesse Barnes585fb112008-07-29 11:54:06 -07001504#define CACHE_MODE_0 0x02120 /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02001505#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001506#define CM0_IZ_OPT_DISABLE (1<<6)
1507#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02001508#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001509#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1510#define CM0_COLOR_EVICT_DISABLE (1<<3)
1511#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1512#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1513#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001514#define GFX_FLSH_CNTL_GEN6 0x101008
1515#define GFX_FLSH_CNTL_EN (1<<0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07001516#define ECOSKPD 0x021d0
1517#define ECO_GATING_CX_ONLY (1<<3)
1518#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001519
Chia-I Wufe27c602014-01-28 13:29:33 +08001520#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05301521#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08001522#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Jesse Barnesfb046852012-03-28 13:39:26 -07001523#define CACHE_MODE_1 0x7004 /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00001524#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1525#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Damien Lespiau9370cd92015-02-09 19:33:17 +00001526#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
Jesse Barnesfb046852012-03-28 13:39:26 -07001527
Jesse Barnes4efe0702011-01-18 11:25:41 -08001528#define GEN6_BLITTER_ECOSKPD 0x221d0
1529#define GEN6_BLITTER_LOCK_SHIFT 16
1530#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1531
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001532#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
Chris Wilson2c550182014-12-16 10:02:27 +00001533#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001534#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001535#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001536
Deepak S693d11c2015-01-16 20:42:16 +05301537/* Fuse readout registers for GT */
1538#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
Jeff McGeec93043a2015-02-27 12:12:28 -08001539#define CHV_FGT_DISABLE_SS0 (1 << 10)
1540#define CHV_FGT_DISABLE_SS1 (1 << 11)
Deepak S693d11c2015-01-16 20:42:16 +05301541#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1542#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1543#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1544#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1545#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1546#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1547#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1548#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1549
Jeff McGee38732182015-02-13 10:27:54 -06001550#define GEN8_FUSE2 0x9120
1551#define GEN8_F2_S_ENA_SHIFT 25
1552#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
1553
1554#define GEN9_F2_SS_DIS_SHIFT 20
1555#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1556
1557#define GEN8_EU_DISABLE0 0x9134
1558#define GEN8_EU_DISABLE1 0x9138
1559#define GEN8_EU_DISABLE2 0x913c
1560
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001561#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
Chris Wilson12f55812012-07-05 17:14:01 +01001562#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1563#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1564#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1565#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001566
Ben Widawskycc609d52013-05-28 19:22:29 -07001567/* On modern GEN architectures interrupt control consists of two sets
1568 * of registers. The first set pertains to the ring generating the
1569 * interrupt. The second control is for the functional block generating the
1570 * interrupt. These are PM, GT, DE, etc.
1571 *
1572 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1573 * GT interrupt bits, so we don't need to duplicate the defines.
1574 *
1575 * These defines should cover us well from SNB->HSW with minor exceptions
1576 * it can also work on ILK.
1577 */
1578#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1579#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1580#define GT_BLT_USER_INTERRUPT (1 << 22)
1581#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1582#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001583#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Oscar Mateo73d477f2014-07-24 17:04:31 +01001584#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001585#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1586#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1587#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1588#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1589#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1590#define GT_RENDER_USER_INTERRUPT (1 << 0)
1591
Ben Widawsky12638c52013-05-28 19:22:31 -07001592#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1593#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1594
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001595#define GT_PARITY_ERROR(dev) \
1596 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +03001597 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001598
Ben Widawskycc609d52013-05-28 19:22:29 -07001599/* These are all the "old" interrupts */
1600#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001601
1602#define I915_PM_INTERRUPT (1<<31)
1603#define I915_ISP_INTERRUPT (1<<22)
1604#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1605#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02001606#define I915_MIPIC_INTERRUPT (1<<19)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001607#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07001608#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1609#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001610#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1611#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07001612#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001613#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07001614#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001615#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07001616#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001617#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07001618#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001619#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07001620#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001621#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07001622#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001623#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07001624#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001625#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001626#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1627#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1628#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1629#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1630#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001631#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1632#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07001633#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001634#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07001635#define I915_USER_INTERRUPT (1<<1)
1636#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001637#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001638
1639#define GEN6_BSD_RNCID 0x12198
1640
Ben Widawskya1e969e2012-04-14 18:41:32 -07001641#define GEN7_FF_THREAD_MODE 0x20a0
1642#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08001643#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001644#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1645#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1646#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1647#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08001648#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001649#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1650#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1651#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1652#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1653#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1654#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1655#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1656#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1657
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001658/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001659 * Framebuffer compression (915+ only)
1660 */
1661
1662#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1663#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1664#define FBC_CONTROL 0x03208
1665#define FBC_CTL_EN (1<<31)
1666#define FBC_CTL_PERIODIC (1<<30)
1667#define FBC_CTL_INTERVAL_SHIFT (16)
1668#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02001669#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07001670#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001671#define FBC_CTL_FENCENO_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001672#define FBC_COMMAND 0x0320c
1673#define FBC_CMD_COMPRESS (1<<0)
1674#define FBC_STATUS 0x03210
1675#define FBC_STAT_COMPRESSING (1<<31)
1676#define FBC_STAT_COMPRESSED (1<<30)
1677#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001678#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001679#define FBC_CONTROL2 0x03214
1680#define FBC_CTL_FENCE_DBL (0<<4)
1681#define FBC_CTL_IDLE_IMM (0<<2)
1682#define FBC_CTL_IDLE_FULL (1<<2)
1683#define FBC_CTL_IDLE_LINE (2<<2)
1684#define FBC_CTL_IDLE_DEBUG (3<<2)
1685#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001686#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf64f1722014-01-23 16:49:17 +02001687#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
Jesse Barnes80824002009-09-10 15:28:06 -07001688#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -07001689
1690#define FBC_LL_SIZE (1536)
1691
Jesse Barnes74dff282009-09-14 15:39:40 -07001692/* Framebuffer compression for GM45+ */
1693#define DPFC_CB_BASE 0x3200
1694#define DPFC_CONTROL 0x3208
1695#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001696#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1697#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07001698#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001699#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01001700#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07001701#define DPFC_SR_EN (1<<10)
1702#define DPFC_CTL_LIMIT_1X (0<<6)
1703#define DPFC_CTL_LIMIT_2X (1<<6)
1704#define DPFC_CTL_LIMIT_4X (2<<6)
1705#define DPFC_RECOMP_CTL 0x320c
1706#define DPFC_RECOMP_STALL_EN (1<<27)
1707#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1708#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1709#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1710#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1711#define DPFC_STATUS 0x3210
1712#define DPFC_INVAL_SEG_SHIFT (16)
1713#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1714#define DPFC_COMP_SEG_SHIFT (0)
1715#define DPFC_COMP_SEG_MASK (0x000003ff)
1716#define DPFC_STATUS2 0x3214
1717#define DPFC_FENCE_YOFF 0x3218
1718#define DPFC_CHICKEN 0x3224
1719#define DPFC_HT_MODIFY (1<<31)
1720
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001721/* Framebuffer compression for Ironlake */
1722#define ILK_DPFC_CB_BASE 0x43200
1723#define ILK_DPFC_CONTROL 0x43208
Rodrigo Vivida46f932014-08-01 02:04:45 -07001724#define FBC_CTL_FALSE_COLOR (1<<10)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001725/* The bit 28-8 is reserved */
1726#define DPFC_RESERVED (0x1FFFFF00)
1727#define ILK_DPFC_RECOMP_CTL 0x4320c
1728#define ILK_DPFC_STATUS 0x43210
1729#define ILK_DPFC_FENCE_YOFF 0x43218
1730#define ILK_DPFC_CHICKEN 0x43224
1731#define ILK_FBC_RT_BASE 0x2128
1732#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001733#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001734
1735#define ILK_DISPLAY_CHICKEN1 0x42000
1736#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04001737#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08001738
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001739
Jesse Barnes585fb112008-07-29 11:54:06 -07001740/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001741 * Framebuffer compression for Sandybridge
1742 *
1743 * The following two registers are of type GTTMMADR
1744 */
1745#define SNB_DPFC_CTL_SA 0x100100
1746#define SNB_CPU_FENCE_ENABLE (1<<29)
1747#define DPFC_CPU_FENCE_OFFSET 0x100104
1748
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001749/* Framebuffer compression for Ivybridge */
1750#define IVB_FBC_RT_BASE 0x7020
1751
Paulo Zanoni42db64e2013-05-31 16:33:22 -03001752#define IPS_CTL 0x43408
1753#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001754
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001755#define MSG_FBC_REND_STATE 0x50380
1756#define FBC_REND_NUKE (1<<2)
1757#define FBC_REND_CACHE_CLEAN (1<<1)
1758
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001759/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001760 * GPIO regs
1761 */
1762#define GPIOA 0x5010
1763#define GPIOB 0x5014
1764#define GPIOC 0x5018
1765#define GPIOD 0x501c
1766#define GPIOE 0x5020
1767#define GPIOF 0x5024
1768#define GPIOG 0x5028
1769#define GPIOH 0x502c
1770# define GPIO_CLOCK_DIR_MASK (1 << 0)
1771# define GPIO_CLOCK_DIR_IN (0 << 1)
1772# define GPIO_CLOCK_DIR_OUT (1 << 1)
1773# define GPIO_CLOCK_VAL_MASK (1 << 2)
1774# define GPIO_CLOCK_VAL_OUT (1 << 3)
1775# define GPIO_CLOCK_VAL_IN (1 << 4)
1776# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1777# define GPIO_DATA_DIR_MASK (1 << 8)
1778# define GPIO_DATA_DIR_IN (0 << 9)
1779# define GPIO_DATA_DIR_OUT (1 << 9)
1780# define GPIO_DATA_VAL_MASK (1 << 10)
1781# define GPIO_DATA_VAL_OUT (1 << 11)
1782# define GPIO_DATA_VAL_IN (1 << 12)
1783# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1784
Chris Wilsonf899fc62010-07-20 15:44:45 -07001785#define GMBUS0 0x5100 /* clock/port select */
1786#define GMBUS_RATE_100KHZ (0<<8)
1787#define GMBUS_RATE_50KHZ (1<<8)
1788#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1789#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1790#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1791#define GMBUS_PORT_DISABLED 0
1792#define GMBUS_PORT_SSC 1
1793#define GMBUS_PORT_VGADDC 2
1794#define GMBUS_PORT_PANEL 3
Ville Syrjäläc0c35322014-04-09 13:28:52 +03001795#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */
Chris Wilsonf899fc62010-07-20 15:44:45 -07001796#define GMBUS_PORT_DPC 4 /* HDMIC */
1797#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
Daniel Kurtze4fd17a2012-03-28 02:36:12 +08001798#define GMBUS_PORT_DPD 6 /* HDMID */
1799#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001800#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
Chris Wilsonf899fc62010-07-20 15:44:45 -07001801#define GMBUS1 0x5104 /* command/status */
1802#define GMBUS_SW_CLR_INT (1<<31)
1803#define GMBUS_SW_RDY (1<<30)
1804#define GMBUS_ENT (1<<29) /* enable timeout */
1805#define GMBUS_CYCLE_NONE (0<<25)
1806#define GMBUS_CYCLE_WAIT (1<<25)
1807#define GMBUS_CYCLE_INDEX (2<<25)
1808#define GMBUS_CYCLE_STOP (4<<25)
1809#define GMBUS_BYTE_COUNT_SHIFT 16
1810#define GMBUS_SLAVE_INDEX_SHIFT 8
1811#define GMBUS_SLAVE_ADDR_SHIFT 1
1812#define GMBUS_SLAVE_READ (1<<0)
1813#define GMBUS_SLAVE_WRITE (0<<0)
1814#define GMBUS2 0x5108 /* status */
1815#define GMBUS_INUSE (1<<15)
1816#define GMBUS_HW_WAIT_PHASE (1<<14)
1817#define GMBUS_STALL_TIMEOUT (1<<13)
1818#define GMBUS_INT (1<<12)
1819#define GMBUS_HW_RDY (1<<11)
1820#define GMBUS_SATOER (1<<10)
1821#define GMBUS_ACTIVE (1<<9)
1822#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1823#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1824#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1825#define GMBUS_NAK_EN (1<<3)
1826#define GMBUS_IDLE_EN (1<<2)
1827#define GMBUS_HW_WAIT_EN (1<<1)
1828#define GMBUS_HW_RDY_EN (1<<0)
1829#define GMBUS5 0x5120 /* byte index */
1830#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08001831
Jesse Barnes585fb112008-07-29 11:54:06 -07001832/*
1833 * Clock control & power management
1834 */
Ville Syrjälä2d401b12014-04-09 13:29:08 +03001835#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1836#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1837#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1838#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07001839
1840#define VGA0 0x6000
1841#define VGA1 0x6004
1842#define VGA_PD 0x6010
1843#define VGA0_PD_P2_DIV_4 (1 << 7)
1844#define VGA0_PD_P1_DIV_2 (1 << 5)
1845#define VGA0_PD_P1_SHIFT 0
1846#define VGA0_PD_P1_MASK (0x1f << 0)
1847#define VGA1_PD_P2_DIV_4 (1 << 15)
1848#define VGA1_PD_P1_DIV_2 (1 << 13)
1849#define VGA1_PD_P1_SHIFT 8
1850#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001851#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02001852#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1853#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001854#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07001855#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001856#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07001857#define DPLL_VGA_MODE_DIS (1 << 28)
1858#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1859#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1860#define DPLL_MODE_MASK (3 << 26)
1861#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1862#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1863#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1864#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1865#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1866#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001867#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001868#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02001869#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001870#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001871#define DPLL_SSC_REF_CLOCK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02001872#define DPLL_PORTC_READY_MASK (0xf << 4)
1873#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07001874
Jesse Barnes585fb112008-07-29 11:54:06 -07001875#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001876
1877/* Additional CHV pll/phy registers */
1878#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1879#define DPLL_PORTD_READY_MASK (0xf)
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001880#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03001881#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001882#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03001883#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001884
Jesse Barnes585fb112008-07-29 11:54:06 -07001885/*
1886 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1887 * this field (only one bit may be set).
1888 */
1889#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1890#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001891#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07001892/* i830, required in DVO non-gang */
1893#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1894#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1895#define PLL_REF_INPUT_DREFCLK (0 << 13)
1896#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1897#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1898#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1899#define PLL_REF_INPUT_MASK (3 << 13)
1900#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001901/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08001902# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1903# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1904# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1905# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1906# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1907
Jesse Barnes585fb112008-07-29 11:54:06 -07001908/*
1909 * Parallel to Serial Load Pulse phase selection.
1910 * Selects the phase for the 10X DPLL clock for the PCIe
1911 * digital display port. The range is 4 to 13; 10 or more
1912 * is just a flip delay. The default is 6
1913 */
1914#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1915#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1916/*
1917 * SDVO multiplier for 945G/GM. Not used on 965.
1918 */
1919#define SDVO_MULTIPLIER_MASK 0x000000ff
1920#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1921#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001922
Ville Syrjälä2d401b12014-04-09 13:29:08 +03001923#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1924#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1925#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1926#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001927
Jesse Barnes585fb112008-07-29 11:54:06 -07001928/*
1929 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1930 *
1931 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1932 */
1933#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1934#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1935/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1936#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1937#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1938/*
1939 * SDVO/UDI pixel multiplier.
1940 *
1941 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1942 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1943 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1944 * dummy bytes in the datastream at an increased clock rate, with both sides of
1945 * the link knowing how many bytes are fill.
1946 *
1947 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1948 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1949 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1950 * through an SDVO command.
1951 *
1952 * This register field has values of multiplication factor minus 1, with
1953 * a maximum multiplier of 5 for SDVO.
1954 */
1955#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1956#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1957/*
1958 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1959 * This best be set to the default value (3) or the CRT won't work. No,
1960 * I don't entirely understand what this does...
1961 */
1962#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1963#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001964
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001965#define _FPA0 0x06040
1966#define _FPA1 0x06044
1967#define _FPB0 0x06048
1968#define _FPB1 0x0604c
1969#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1970#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07001971#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001972#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07001973#define FP_N_DIV_SHIFT 16
1974#define FP_M1_DIV_MASK 0x00003f00
1975#define FP_M1_DIV_SHIFT 8
1976#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001977#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07001978#define FP_M2_DIV_SHIFT 0
1979#define DPLL_TEST 0x606c
1980#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1981#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1982#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1983#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1984#define DPLLB_TEST_N_BYPASS (1 << 19)
1985#define DPLLB_TEST_M_BYPASS (1 << 18)
1986#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1987#define DPLLA_TEST_N_BYPASS (1 << 3)
1988#define DPLLA_TEST_M_BYPASS (1 << 2)
1989#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1990#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001991#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07001992#define DSTATE_PLL_D3_OFF (1<<3)
1993#define DSTATE_GFX_CLOCK_GATING (1<<1)
1994#define DSTATE_DOT_CLOCK_GATING (1<<0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001995#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07001996# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1997# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1998# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1999# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2000# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2001# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2002# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2003# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2004# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2005# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2006# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2007# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2008# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2009# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2010# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2011# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2012# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2013# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2014# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2015# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2016# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2017# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2018# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2019# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2020# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2021# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2022# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2023# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002024/*
Jesse Barnes652c3932009-08-17 13:31:43 -07002025 * This bit must be set on the 830 to prevent hangs when turning off the
2026 * overlay scaler.
2027 */
2028# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2029# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2030# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2031# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2032# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2033
2034#define RENCLK_GATE_D1 0x6204
2035# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2036# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2037# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2038# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2039# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2040# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2041# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2042# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2043# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002044/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07002045# define MECI_CLOCK_GATE_DISABLE (1 << 4)
2046# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2047# define MEC_CLOCK_GATE_DISABLE (1 << 2)
2048# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002049/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07002050# define SV_CLOCK_GATE_DISABLE (1 << 0)
2051# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2052# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2053# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2054# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2055# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2056# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2057# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2058# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2059# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2060# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2061# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2062# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2063# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2064# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2065# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2066# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2067# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2068
2069# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002070/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07002071# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2072# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2073# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2074# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2075# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2076# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002077/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07002078# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2079# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2080# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2081# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2082# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2083# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2084# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2085# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2086# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2087# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2088# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2089# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2090# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2091# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2092# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2093# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2094# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2095# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2096# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2097
2098#define RENCLK_GATE_D2 0x6208
2099#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2100#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2101#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03002102
2103#define VDECCLK_GATE_D 0x620C /* g4x only */
2104#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2105
Jesse Barnes652c3932009-08-17 13:31:43 -07002106#define RAMCLK_GATE_D 0x6210 /* CRL only */
2107#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002108
Ville Syrjäläd88b2272013-01-24 15:29:48 +02002109#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07002110#define FW_CSPWRDWNEN (1<<15)
2111
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03002112#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2113
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002114#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2115#define CDCLK_FREQ_SHIFT 4
2116#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2117#define CZCLK_FREQ_MASK 0xf
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02002118
2119#define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)
2120#define PFI_CREDIT_63 (9 << 28) /* chv only */
2121#define PFI_CREDIT_31 (8 << 28) /* chv only */
2122#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2123#define PFI_CREDIT_RESEND (1 << 27)
2124#define VGA_FAST_MODE_DISABLE (1 << 14)
2125
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08002126#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2127
Jesse Barnes585fb112008-07-29 11:54:06 -07002128/*
2129 * Palette regs
2130 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002131#define PALETTE_A_OFFSET 0xa000
2132#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002133#define CHV_PALETTE_C_OFFSET 0xc000
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002134#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2135 dev_priv->info.display_mmio_offset)
Jesse Barnes585fb112008-07-29 11:54:06 -07002136
Eric Anholt673a3942008-07-30 12:06:12 -07002137/* MCH MMIO space */
2138
2139/*
2140 * MCHBAR mirror.
2141 *
2142 * This mirrors the MCHBAR MMIO space whose location is determined by
2143 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2144 * every way. It is not accessible from the CP register read instructions.
2145 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03002146 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2147 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07002148 */
2149#define MCHBAR_MIRROR_BASE 0x10000
2150
Yuanhan Liu13982612010-12-15 15:42:31 +08002151#define MCHBAR_MIRROR_BASE_SNB 0x140000
2152
Chris Wilson3ebecd02013-04-12 19:10:13 +01002153/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ben Widawsky153b4b952013-10-22 22:05:09 -07002154#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01002155
Ville Syrjälä646b4262014-04-25 20:14:30 +03002156/* 915-945 and GM965 MCH register controlling DRAM channel access */
Eric Anholt673a3942008-07-30 12:06:12 -07002157#define DCC 0x10200
2158#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2159#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2160#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2161#define DCC_ADDRESSING_MODE_MASK (3 << 0)
2162#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08002163#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Daniel Vetter656bfa32014-11-20 09:26:30 +01002164#define DCC2 0x10204
2165#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
Eric Anholt673a3942008-07-30 12:06:12 -07002166
Ville Syrjälä646b4262014-04-25 20:14:30 +03002167/* Pineview MCH register contains DDR3 setting */
Li Peng95534262010-05-18 18:58:44 +08002168#define CSHRDDR3CTL 0x101a8
2169#define CSHRDDR3CTL_DDR3 (1 << 2)
2170
Ville Syrjälä646b4262014-04-25 20:14:30 +03002171/* 965 MCH register controlling DRAM channel configuration */
Eric Anholt673a3942008-07-30 12:06:12 -07002172#define C0DRB3 0x10206
2173#define C1DRB3 0x10606
2174
Ville Syrjälä646b4262014-04-25 20:14:30 +03002175/* snb MCH registers for reading the DRAM channel configuration */
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002176#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2177#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2178#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2179#define MAD_DIMM_ECC_MASK (0x3 << 24)
2180#define MAD_DIMM_ECC_OFF (0x0 << 24)
2181#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2182#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2183#define MAD_DIMM_ECC_ON (0x3 << 24)
2184#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2185#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2186#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2187#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2188#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2189#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2190#define MAD_DIMM_A_SELECT (0x1 << 16)
2191/* DIMM sizes are in multiples of 256mb. */
2192#define MAD_DIMM_B_SIZE_SHIFT 8
2193#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2194#define MAD_DIMM_A_SIZE_SHIFT 0
2195#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2196
Ville Syrjälä646b4262014-04-25 20:14:30 +03002197/* snb MCH registers for priority tuning */
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01002198#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2199#define MCH_SSKPD_WM0_MASK 0x3f
2200#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002201
Jesse Barnesec013e72013-08-20 10:29:23 +01002202#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2203
Keith Packardb11248d2009-06-11 22:28:56 -07002204/* Clocking configuration register */
2205#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08002206#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07002207#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2208#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2209#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2210#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2211#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002212/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07002213#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002214#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07002215#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002216#define CLKCFG_MEM_533 (1 << 4)
2217#define CLKCFG_MEM_667 (2 << 4)
2218#define CLKCFG_MEM_800 (3 << 4)
2219#define CLKCFG_MEM_MASK (7 << 4)
2220
Jesse Barnesea056c12010-09-10 10:02:13 -07002221#define TSC1 0x11001
2222#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002223#define TR1 0x11006
2224#define TSFS 0x11020
2225#define TSFS_SLOPE_MASK 0x0000ff00
2226#define TSFS_SLOPE_SHIFT 8
2227#define TSFS_INTR_MASK 0x000000ff
2228
Jesse Barnesf97108d2010-01-29 11:27:07 -08002229#define CRSTANDVID 0x11100
2230#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2231#define PXVFREQ_PX_MASK 0x7f000000
2232#define PXVFREQ_PX_SHIFT 24
2233#define VIDFREQ_BASE 0x11110
2234#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2235#define VIDFREQ2 0x11114
2236#define VIDFREQ3 0x11118
2237#define VIDFREQ4 0x1111c
2238#define VIDFREQ_P0_MASK 0x1f000000
2239#define VIDFREQ_P0_SHIFT 24
2240#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2241#define VIDFREQ_P0_CSCLK_SHIFT 20
2242#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2243#define VIDFREQ_P0_CRCLK_SHIFT 16
2244#define VIDFREQ_P1_MASK 0x00001f00
2245#define VIDFREQ_P1_SHIFT 8
2246#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2247#define VIDFREQ_P1_CSCLK_SHIFT 4
2248#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2249#define INTTOEXT_BASE_ILK 0x11300
2250#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2251#define INTTOEXT_MAP3_SHIFT 24
2252#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2253#define INTTOEXT_MAP2_SHIFT 16
2254#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2255#define INTTOEXT_MAP1_SHIFT 8
2256#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2257#define INTTOEXT_MAP0_SHIFT 0
2258#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2259#define MEMSWCTL 0x11170 /* Ironlake only */
2260#define MEMCTL_CMD_MASK 0xe000
2261#define MEMCTL_CMD_SHIFT 13
2262#define MEMCTL_CMD_RCLK_OFF 0
2263#define MEMCTL_CMD_RCLK_ON 1
2264#define MEMCTL_CMD_CHFREQ 2
2265#define MEMCTL_CMD_CHVID 3
2266#define MEMCTL_CMD_VMMOFF 4
2267#define MEMCTL_CMD_VMMON 5
2268#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2269 when command complete */
2270#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2271#define MEMCTL_FREQ_SHIFT 8
2272#define MEMCTL_SFCAVM (1<<7)
2273#define MEMCTL_TGT_VID_MASK 0x007f
2274#define MEMIHYST 0x1117c
2275#define MEMINTREN 0x11180 /* 16 bits */
2276#define MEMINT_RSEXIT_EN (1<<8)
2277#define MEMINT_CX_SUPR_EN (1<<7)
2278#define MEMINT_CONT_BUSY_EN (1<<6)
2279#define MEMINT_AVG_BUSY_EN (1<<5)
2280#define MEMINT_EVAL_CHG_EN (1<<4)
2281#define MEMINT_MON_IDLE_EN (1<<3)
2282#define MEMINT_UP_EVAL_EN (1<<2)
2283#define MEMINT_DOWN_EVAL_EN (1<<1)
2284#define MEMINT_SW_CMD_EN (1<<0)
2285#define MEMINTRSTR 0x11182 /* 16 bits */
2286#define MEM_RSEXIT_MASK 0xc000
2287#define MEM_RSEXIT_SHIFT 14
2288#define MEM_CONT_BUSY_MASK 0x3000
2289#define MEM_CONT_BUSY_SHIFT 12
2290#define MEM_AVG_BUSY_MASK 0x0c00
2291#define MEM_AVG_BUSY_SHIFT 10
2292#define MEM_EVAL_CHG_MASK 0x0300
2293#define MEM_EVAL_BUSY_SHIFT 8
2294#define MEM_MON_IDLE_MASK 0x00c0
2295#define MEM_MON_IDLE_SHIFT 6
2296#define MEM_UP_EVAL_MASK 0x0030
2297#define MEM_UP_EVAL_SHIFT 4
2298#define MEM_DOWN_EVAL_MASK 0x000c
2299#define MEM_DOWN_EVAL_SHIFT 2
2300#define MEM_SW_CMD_MASK 0x0003
2301#define MEM_INT_STEER_GFX 0
2302#define MEM_INT_STEER_CMR 1
2303#define MEM_INT_STEER_SMI 2
2304#define MEM_INT_STEER_SCI 3
2305#define MEMINTRSTS 0x11184
2306#define MEMINT_RSEXIT (1<<7)
2307#define MEMINT_CONT_BUSY (1<<6)
2308#define MEMINT_AVG_BUSY (1<<5)
2309#define MEMINT_EVAL_CHG (1<<4)
2310#define MEMINT_MON_IDLE (1<<3)
2311#define MEMINT_UP_EVAL (1<<2)
2312#define MEMINT_DOWN_EVAL (1<<1)
2313#define MEMINT_SW_CMD (1<<0)
2314#define MEMMODECTL 0x11190
2315#define MEMMODE_BOOST_EN (1<<31)
2316#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2317#define MEMMODE_BOOST_FREQ_SHIFT 24
2318#define MEMMODE_IDLE_MODE_MASK 0x00030000
2319#define MEMMODE_IDLE_MODE_SHIFT 16
2320#define MEMMODE_IDLE_MODE_EVAL 0
2321#define MEMMODE_IDLE_MODE_CONT 1
2322#define MEMMODE_HWIDLE_EN (1<<15)
2323#define MEMMODE_SWMODE_EN (1<<14)
2324#define MEMMODE_RCLK_GATE (1<<13)
2325#define MEMMODE_HW_UPDATE (1<<12)
2326#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2327#define MEMMODE_FSTART_SHIFT 8
2328#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2329#define MEMMODE_FMAX_SHIFT 4
2330#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2331#define RCBMAXAVG 0x1119c
2332#define MEMSWCTL2 0x1119e /* Cantiga only */
2333#define SWMEMCMD_RENDER_OFF (0 << 13)
2334#define SWMEMCMD_RENDER_ON (1 << 13)
2335#define SWMEMCMD_SWFREQ (2 << 13)
2336#define SWMEMCMD_TARVID (3 << 13)
2337#define SWMEMCMD_VRM_OFF (4 << 13)
2338#define SWMEMCMD_VRM_ON (5 << 13)
2339#define CMDSTS (1<<12)
2340#define SFCAVM (1<<11)
2341#define SWFREQ_MASK 0x0380 /* P0-7 */
2342#define SWFREQ_SHIFT 7
2343#define TARVID_MASK 0x001f
2344#define MEMSTAT_CTG 0x111a0
2345#define RCBMINAVG 0x111a0
2346#define RCUPEI 0x111b0
2347#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08002348#define RSTDBYCTL 0x111b8
2349#define RS1EN (1<<31)
2350#define RS2EN (1<<30)
2351#define RS3EN (1<<29)
2352#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2353#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2354#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2355#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2356#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2357#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2358#define RSX_STATUS_MASK (7<<20)
2359#define RSX_STATUS_ON (0<<20)
2360#define RSX_STATUS_RC1 (1<<20)
2361#define RSX_STATUS_RC1E (2<<20)
2362#define RSX_STATUS_RS1 (3<<20)
2363#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2364#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2365#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2366#define RSX_STATUS_RSVD2 (7<<20)
2367#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2368#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2369#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2370#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2371#define RS1CONTSAV_MASK (3<<14)
2372#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2373#define RS1CONTSAV_RSVD (1<<14)
2374#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2375#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2376#define NORMSLEXLAT_MASK (3<<12)
2377#define SLOW_RS123 (0<<12)
2378#define SLOW_RS23 (1<<12)
2379#define SLOW_RS3 (2<<12)
2380#define NORMAL_RS123 (3<<12)
2381#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2382#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2383#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2384#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2385#define RS_CSTATE_MASK (3<<4)
2386#define RS_CSTATE_C367_RS1 (0<<4)
2387#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2388#define RS_CSTATE_RSVD (2<<4)
2389#define RS_CSTATE_C367_RS2 (3<<4)
2390#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2391#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002392#define VIDCTL 0x111c0
2393#define VIDSTS 0x111c8
2394#define VIDSTART 0x111cc /* 8 bits */
2395#define MEMSTAT_ILK 0x111f8
2396#define MEMSTAT_VID_MASK 0x7f00
2397#define MEMSTAT_VID_SHIFT 8
2398#define MEMSTAT_PSTATE_MASK 0x00f8
2399#define MEMSTAT_PSTATE_SHIFT 3
2400#define MEMSTAT_MON_ACTV (1<<2)
2401#define MEMSTAT_SRC_CTL_MASK 0x0003
2402#define MEMSTAT_SRC_CTL_CORE 0
2403#define MEMSTAT_SRC_CTL_TRB 1
2404#define MEMSTAT_SRC_CTL_THM 2
2405#define MEMSTAT_SRC_CTL_STDBY 3
2406#define RCPREVBSYTUPAVG 0x113b8
2407#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07002408#define PMMISC 0x11214
2409#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07002410#define SDEW 0x1124c
2411#define CSIEW0 0x11250
2412#define CSIEW1 0x11254
2413#define CSIEW2 0x11258
2414#define PEW 0x1125c
2415#define DEW 0x11270
2416#define MCHAFE 0x112c0
2417#define CSIEC 0x112e0
2418#define DMIEC 0x112e4
2419#define DDREC 0x112e8
2420#define PEG0EC 0x112ec
2421#define PEG1EC 0x112f0
2422#define GFXEC 0x112f4
2423#define RPPREVBSYTUPAVG 0x113b8
2424#define RPPREVBSYTDNAVG 0x113bc
2425#define ECR 0x11600
2426#define ECR_GPFE (1<<31)
2427#define ECR_IMONE (1<<30)
2428#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2429#define OGW0 0x11608
2430#define OGW1 0x1160c
2431#define EG0 0x11610
2432#define EG1 0x11614
2433#define EG2 0x11618
2434#define EG3 0x1161c
2435#define EG4 0x11620
2436#define EG5 0x11624
2437#define EG6 0x11628
2438#define EG7 0x1162c
2439#define PXW 0x11664
2440#define PXWL 0x11680
2441#define LCFUSE02 0x116c0
2442#define LCFUSE_HIV_MASK 0x000000ff
2443#define CSIPLL0 0x12c10
2444#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08002445#define PEG_BAND_GAP_DATA 0x14d68
2446
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002447#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2448#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002449
Ben Widawsky153b4b952013-10-22 22:05:09 -07002450#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2451#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2452#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002453
Akash Goelde43ae92015-03-06 11:07:14 +05302454#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
2455#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2456#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2457 INTERVAL_1_33_US(us) : \
2458 INTERVAL_1_28_US(us))
2459
Jesse Barnes585fb112008-07-29 11:54:06 -07002460/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002461 * Logical Context regs
2462 */
2463#define CCID 0x2180
2464#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002465/*
2466 * Notes on SNB/IVB/VLV context size:
2467 * - Power context is saved elsewhere (LLC or stolen)
2468 * - Ring/execlist context is saved on SNB, not on IVB
2469 * - Extended context size already includes render context size
2470 * - We always need to follow the extended context size.
2471 * SNB BSpec has comments indicating that we should use the
2472 * render context size instead if execlists are disabled, but
2473 * based on empirical testing that's just nonsense.
2474 * - Pipelined/VF state is saved on SNB/IVB respectively
2475 * - GT1 size just indicates how much of render context
2476 * doesn't need saving on GT1
2477 */
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002478#define CXT_SIZE 0x21a0
2479#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2480#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2481#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2482#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2483#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002484#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002485 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2486 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002487#define GEN7_CXT_SIZE 0x21a8
Ben Widawsky6a4ea122012-07-18 10:10:10 -07002488#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2489#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002490#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2491#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2492#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2493#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002494#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002495 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07002496/* Haswell does have the CXT_SIZE register however it does not appear to be
2497 * valid. Now, docs explain in dwords what is in the context object. The full
2498 * size is 70720 bytes, however, the power context and execlist context will
2499 * never be saved (power context is stored elsewhere, and execlists don't work
2500 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
2501 */
2502#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawsky88976442013-11-02 21:07:05 -07002503/* Same as Haswell, but 72064 bytes now. */
2504#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2505
Mika Kuoppala542a6b22014-07-09 14:55:56 +03002506#define CHV_CLK_CTL1 0x101100
Jesse Barnese454a052013-09-26 17:55:58 -07002507#define VLV_CLK_CTL2 0x101104
2508#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2509
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002510/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002511 * Overlay regs
2512 */
2513
2514#define OVADD 0x30000
2515#define DOVSTA 0x30008
2516#define OC_BUF (0x3<<20)
2517#define OGAMC5 0x30010
2518#define OGAMC4 0x30014
2519#define OGAMC3 0x30018
2520#define OGAMC2 0x3001c
2521#define OGAMC1 0x30020
2522#define OGAMC0 0x30024
2523
2524/*
2525 * Display engine regs
2526 */
2527
Shuang He8bf1e9f2013-10-15 18:55:27 +01002528/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002529#define _PIPE_CRC_CTL_A 0x60050
Shuang He8bf1e9f2013-10-15 18:55:27 +01002530#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002531/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01002532#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2533#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2534#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002535/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002536#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2537#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2538#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2539/* embedded DP port on the north display block, reserved on ivb */
2540#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2541#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02002542/* vlv source selection */
2543#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2544#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2545#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2546/* with DP port the pipe source is invalid */
2547#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2548#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2549#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2550/* gen3+ source selection */
2551#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2552#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2553#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2554/* with DP/TV port the pipe source is invalid */
2555#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2556#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2557#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2558#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2559#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2560/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02002561#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002562
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002563#define _PIPE_CRC_RES_1_A_IVB 0x60064
2564#define _PIPE_CRC_RES_2_A_IVB 0x60068
2565#define _PIPE_CRC_RES_3_A_IVB 0x6006c
2566#define _PIPE_CRC_RES_4_A_IVB 0x60070
2567#define _PIPE_CRC_RES_5_A_IVB 0x60074
2568
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002569#define _PIPE_CRC_RES_RED_A 0x60060
2570#define _PIPE_CRC_RES_GREEN_A 0x60064
2571#define _PIPE_CRC_RES_BLUE_A 0x60068
2572#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2573#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01002574
2575/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002576#define _PIPE_CRC_RES_1_B_IVB 0x61064
2577#define _PIPE_CRC_RES_2_B_IVB 0x61068
2578#define _PIPE_CRC_RES_3_B_IVB 0x6106c
2579#define _PIPE_CRC_RES_4_B_IVB 0x61070
2580#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01002581
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002582#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002583#define PIPE_CRC_RES_1_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002584 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002585#define PIPE_CRC_RES_2_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002586 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002587#define PIPE_CRC_RES_3_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002588 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002589#define PIPE_CRC_RES_4_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002590 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002591#define PIPE_CRC_RES_5_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002592 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002593
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002594#define PIPE_CRC_RES_RED(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002595 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002596#define PIPE_CRC_RES_GREEN(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002597 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002598#define PIPE_CRC_RES_BLUE(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002599 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002600#define PIPE_CRC_RES_RES1_I915(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002601 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002602#define PIPE_CRC_RES_RES2_G4X(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002603 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002604
Jesse Barnes585fb112008-07-29 11:54:06 -07002605/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002606#define _HTOTAL_A 0x60000
2607#define _HBLANK_A 0x60004
2608#define _HSYNC_A 0x60008
2609#define _VTOTAL_A 0x6000c
2610#define _VBLANK_A 0x60010
2611#define _VSYNC_A 0x60014
2612#define _PIPEASRC 0x6001c
2613#define _BCLRPAT_A 0x60020
2614#define _VSYNCSHIFT_A 0x60028
Clint Taylorebb69c92014-09-30 10:30:22 -07002615#define _PIPE_MULT_A 0x6002c
Jesse Barnes585fb112008-07-29 11:54:06 -07002616
2617/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002618#define _HTOTAL_B 0x61000
2619#define _HBLANK_B 0x61004
2620#define _HSYNC_B 0x61008
2621#define _VTOTAL_B 0x6100c
2622#define _VBLANK_B 0x61010
2623#define _VSYNC_B 0x61014
2624#define _PIPEBSRC 0x6101c
2625#define _BCLRPAT_B 0x61020
2626#define _VSYNCSHIFT_B 0x61028
Clint Taylorebb69c92014-09-30 10:30:22 -07002627#define _PIPE_MULT_B 0x6102c
Daniel Vetter0529a0d2012-01-28 14:49:24 +01002628
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002629#define TRANSCODER_A_OFFSET 0x60000
2630#define TRANSCODER_B_OFFSET 0x61000
2631#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002632#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002633#define TRANSCODER_EDP_OFFSET 0x6f000
2634
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002635#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2636 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2637 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002638
2639#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2640#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2641#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2642#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2643#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2644#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2645#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2646#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2647#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
Clint Taylorebb69c92014-09-30 10:30:22 -07002648#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
Chris Wilson5eddb702010-09-11 13:48:45 +01002649
Rodrigo Vivic8f7df52014-11-14 08:52:36 -08002650/* VLV eDP PSR registers */
2651#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
2652#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
2653#define VLV_EDP_PSR_ENABLE (1<<0)
2654#define VLV_EDP_PSR_RESET (1<<1)
2655#define VLV_EDP_PSR_MODE_MASK (7<<2)
2656#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
2657#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
2658#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
2659#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
2660#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
2661#define VLV_EDP_PSR_DBL_FRAME (1<<10)
2662#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
2663#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
2664#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
2665
2666#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
2667#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
2668#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
2669#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
2670#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
2671#define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)
2672
2673#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
2674#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
2675#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
2676#define VLV_EDP_PSR_CURR_STATE_MASK 7
2677#define VLV_EDP_PSR_DISABLED (0<<0)
2678#define VLV_EDP_PSR_INACTIVE (1<<0)
2679#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
2680#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
2681#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
2682#define VLV_EDP_PSR_EXIT (5<<0)
2683#define VLV_EDP_PSR_IN_TRANS (1<<7)
2684#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
2685
Ben Widawskyed8546a2013-11-04 22:45:05 -08002686/* HSW+ eDP PSR registers */
2687#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
Ben Widawsky18b59922013-09-20 09:35:30 -07002688#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002689#define EDP_PSR_ENABLE (1<<31)
Rodrigo Vivi82c56252014-06-12 10:16:42 -07002690#define BDW_PSR_SINGLE_FRAME (1<<30)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002691#define EDP_PSR_LINK_DISABLE (0<<27)
2692#define EDP_PSR_LINK_STANDBY (1<<27)
2693#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2694#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2695#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2696#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2697#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2698#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2699#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2700#define EDP_PSR_TP1_TP2_SEL (0<<11)
2701#define EDP_PSR_TP1_TP3_SEL (1<<11)
2702#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2703#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2704#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2705#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2706#define EDP_PSR_TP1_TIME_500us (0<<4)
2707#define EDP_PSR_TP1_TIME_100us (1<<4)
2708#define EDP_PSR_TP1_TIME_2500us (2<<4)
2709#define EDP_PSR_TP1_TIME_0us (3<<4)
2710#define EDP_PSR_IDLE_FRAME_SHIFT 0
2711
Ben Widawsky18b59922013-09-20 09:35:30 -07002712#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2713#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
Ben Widawsky18b59922013-09-20 09:35:30 -07002714#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
Ben Widawsky18b59922013-09-20 09:35:30 -07002715#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2716#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2717#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002718
Ben Widawsky18b59922013-09-20 09:35:30 -07002719#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002720#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002721#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2722#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2723#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2724#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2725#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2726#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2727#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2728#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2729#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2730#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2731#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2732#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2733#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2734#define EDP_PSR_STATUS_COUNT_SHIFT 16
2735#define EDP_PSR_STATUS_COUNT_MASK 0xf
2736#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2737#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2738#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2739#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2740#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2741#define EDP_PSR_STATUS_IDLE_MASK 0xf
2742
Ben Widawsky18b59922013-09-20 09:35:30 -07002743#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002744#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002745
Ben Widawsky18b59922013-09-20 09:35:30 -07002746#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002747#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2748#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2749#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2750
Jesse Barnes585fb112008-07-29 11:54:06 -07002751/* VGA port control */
2752#define ADPA 0x61100
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002753#define PCH_ADPA 0xe1100
Daniel Vetter540a8952012-07-11 16:27:57 +02002754#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002755
Jesse Barnes585fb112008-07-29 11:54:06 -07002756#define ADPA_DAC_ENABLE (1<<31)
2757#define ADPA_DAC_DISABLE 0
2758#define ADPA_PIPE_SELECT_MASK (1<<30)
2759#define ADPA_PIPE_A_SELECT 0
2760#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07002761#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002762/* CPT uses bits 29:30 for pch transcoder select */
2763#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2764#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2765#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2766#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2767#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2768#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2769#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2770#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2771#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2772#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2773#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2774#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2775#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2776#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2777#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2778#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2779#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2780#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2781#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07002782#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2783#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002784#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07002785#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002786#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07002787#define ADPA_HSYNC_CNTL_ENABLE 0
2788#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2789#define ADPA_VSYNC_ACTIVE_LOW 0
2790#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2791#define ADPA_HSYNC_ACTIVE_LOW 0
2792#define ADPA_DPMS_MASK (~(3<<10))
2793#define ADPA_DPMS_ON (0<<10)
2794#define ADPA_DPMS_SUSPEND (1<<10)
2795#define ADPA_DPMS_STANDBY (2<<10)
2796#define ADPA_DPMS_OFF (3<<10)
2797
Chris Wilson939fe4d2010-10-09 10:33:26 +01002798
Jesse Barnes585fb112008-07-29 11:54:06 -07002799/* Hotplug control (945+ only) */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002800#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01002801#define PORTB_HOTPLUG_INT_EN (1 << 29)
2802#define PORTC_HOTPLUG_INT_EN (1 << 28)
2803#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07002804#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2805#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2806#define TV_HOTPLUG_INT_EN (1 << 18)
2807#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05002808#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2809 PORTC_HOTPLUG_INT_EN | \
2810 PORTD_HOTPLUG_INT_EN | \
2811 SDVOC_HOTPLUG_INT_EN | \
2812 SDVOB_HOTPLUG_INT_EN | \
2813 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07002814#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08002815#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2816/* must use period 64 on GM45 according to docs */
2817#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2818#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2819#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2820#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2821#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2822#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2823#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2824#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2825#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2826#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2827#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2828#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002829
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002830#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02002831/*
2832 * HDMI/DP bits are gen4+
2833 *
2834 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2835 * Please check the detailed lore in the commit message for for experimental
2836 * evidence.
2837 */
Todd Previte232a6ee2014-01-23 00:13:41 -07002838#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2839#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2840#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2841/* VLV DP/HDMI bits again match Bspec */
2842#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2843#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2844#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01002845#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02002846#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2847#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01002848#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02002849#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2850#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01002851#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02002852#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2853#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01002854/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07002855#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2856#define TV_HOTPLUG_INT_STATUS (1 << 10)
2857#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2858#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2859#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2860#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01002861#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2862#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2863#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02002864#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2865
Chris Wilson084b6122012-05-11 18:01:33 +01002866/* SDVO is different across gen3/4 */
2867#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2868#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02002869/*
2870 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2871 * since reality corrobates that they're the same as on gen3. But keep these
2872 * bits here (and the comment!) to help any other lost wanderers back onto the
2873 * right tracks.
2874 */
Chris Wilson084b6122012-05-11 18:01:33 +01002875#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2876#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2877#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2878#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05002879#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2880 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2881 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2882 PORTB_HOTPLUG_INT_STATUS | \
2883 PORTC_HOTPLUG_INT_STATUS | \
2884 PORTD_HOTPLUG_INT_STATUS)
2885
Egbert Eiche5868a32013-02-28 04:17:12 -05002886#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2887 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2888 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2889 PORTB_HOTPLUG_INT_STATUS | \
2890 PORTC_HOTPLUG_INT_STATUS | \
2891 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07002892
Paulo Zanonic20cd312013-02-19 16:21:45 -03002893/* SDVO and HDMI port control.
2894 * The same register may be used for SDVO or HDMI */
2895#define GEN3_SDVOB 0x61140
2896#define GEN3_SDVOC 0x61160
2897#define GEN4_HDMIB GEN3_SDVOB
2898#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjälä9418c1f2014-04-09 13:28:56 +03002899#define CHV_HDMID 0x6116C
Paulo Zanonic20cd312013-02-19 16:21:45 -03002900#define PCH_SDVOB 0xe1140
2901#define PCH_HDMIB PCH_SDVOB
2902#define PCH_HDMIC 0xe1150
2903#define PCH_HDMID 0xe1160
2904
Daniel Vetter84093602013-11-01 10:50:21 +01002905#define PORT_DFT_I9XX 0x61150
2906#define DC_BALANCE_RESET (1 << 25)
Rodrigo Vivia8aab8b2014-06-05 14:28:17 -07002907#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01002908#define DC_BALANCE_RESET_VLV (1 << 31)
Ville Syrjäläeb736672014-12-09 21:28:28 +02002909#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2910#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
Daniel Vetter84093602013-11-01 10:50:21 +01002911#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2912#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2913
Paulo Zanonic20cd312013-02-19 16:21:45 -03002914/* Gen 3 SDVO bits: */
2915#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002916#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2917#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002918#define SDVO_PIPE_B_SELECT (1 << 30)
2919#define SDVO_STALL_SELECT (1 << 29)
2920#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002921/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002922 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07002923 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07002924 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2925 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002926#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07002927#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03002928#define SDVO_PHASE_SELECT_MASK (15 << 19)
2929#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2930#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2931#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2932#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2933#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2934#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002935/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002936#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2937 SDVO_INTERRUPT_ENABLE)
2938#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2939
2940/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002941#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03002942#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002943#define SDVO_ENCODING_SDVO (0 << 10)
2944#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002945#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2946#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002947#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002948#define SDVO_AUDIO_ENABLE (1 << 6)
2949/* VSYNC/HSYNC bits new with 965, default is to be set */
2950#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2951#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2952
2953/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002954#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002955#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2956
2957/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002958#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2959#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002960
Chon Ming Lee44f37d12014-04-09 13:28:21 +03002961/* CHV SDVO/HDMI bits: */
2962#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2963#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2964
Jesse Barnes585fb112008-07-29 11:54:06 -07002965
2966/* DVO port control */
2967#define DVOA 0x61120
2968#define DVOB 0x61140
2969#define DVOC 0x61160
2970#define DVO_ENABLE (1 << 31)
2971#define DVO_PIPE_B_SELECT (1 << 30)
2972#define DVO_PIPE_STALL_UNUSED (0 << 28)
2973#define DVO_PIPE_STALL (1 << 28)
2974#define DVO_PIPE_STALL_TV (2 << 28)
2975#define DVO_PIPE_STALL_MASK (3 << 28)
2976#define DVO_USE_VGA_SYNC (1 << 15)
2977#define DVO_DATA_ORDER_I740 (0 << 14)
2978#define DVO_DATA_ORDER_FP (1 << 14)
2979#define DVO_VSYNC_DISABLE (1 << 11)
2980#define DVO_HSYNC_DISABLE (1 << 10)
2981#define DVO_VSYNC_TRISTATE (1 << 9)
2982#define DVO_HSYNC_TRISTATE (1 << 8)
2983#define DVO_BORDER_ENABLE (1 << 7)
2984#define DVO_DATA_ORDER_GBRG (1 << 6)
2985#define DVO_DATA_ORDER_RGGB (0 << 6)
2986#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2987#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2988#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2989#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2990#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2991#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2992#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2993#define DVO_PRESERVE_MASK (0x7<<24)
2994#define DVOA_SRCDIM 0x61124
2995#define DVOB_SRCDIM 0x61144
2996#define DVOC_SRCDIM 0x61164
2997#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2998#define DVO_SRCDIM_VERTICAL_SHIFT 0
2999
3000/* LVDS port control */
3001#define LVDS 0x61180
3002/*
3003 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3004 * the DPLL semantics change when the LVDS is assigned to that pipe.
3005 */
3006#define LVDS_PORT_EN (1 << 31)
3007/* Selects pipe B for LVDS data. Must be set on pre-965. */
3008#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003009#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07003010#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08003011/* LVDS dithering flag on 965/g4x platform */
3012#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08003013/* LVDS sync polarity flags. Set to invert (i.e. negative) */
3014#define LVDS_VSYNC_POLARITY (1 << 21)
3015#define LVDS_HSYNC_POLARITY (1 << 20)
3016
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08003017/* Enable border for unscaled (or aspect-scaled) display */
3018#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07003019/*
3020 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3021 * pixel.
3022 */
3023#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3024#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3025#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3026/*
3027 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3028 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3029 * on.
3030 */
3031#define LVDS_A3_POWER_MASK (3 << 6)
3032#define LVDS_A3_POWER_DOWN (0 << 6)
3033#define LVDS_A3_POWER_UP (3 << 6)
3034/*
3035 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3036 * is set.
3037 */
3038#define LVDS_CLKB_POWER_MASK (3 << 4)
3039#define LVDS_CLKB_POWER_DOWN (0 << 4)
3040#define LVDS_CLKB_POWER_UP (3 << 4)
3041/*
3042 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3043 * setting for whether we are in dual-channel mode. The B3 pair will
3044 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3045 */
3046#define LVDS_B0B3_POWER_MASK (3 << 2)
3047#define LVDS_B0B3_POWER_DOWN (0 << 2)
3048#define LVDS_B0B3_POWER_UP (3 << 2)
3049
David Härdeman3c17fe42010-09-24 21:44:32 +02003050/* Video Data Island Packet control */
3051#define VIDEO_DIP_DATA 0x61178
Yannick Guerrinifd0753c2015-02-28 17:20:41 +01003052/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
Paulo Zanoniadf00b22012-09-25 13:23:34 -03003053 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3054 * of the infoframe structure specified by CEA-861. */
3055#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003056#define VIDEO_DIP_VSC_DATA_SIZE 36
David Härdeman3c17fe42010-09-24 21:44:32 +02003057#define VIDEO_DIP_CTL 0x61170
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003058/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02003059#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02003060#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03003061#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003062#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02003063#define VIDEO_DIP_ENABLE_AVI (1 << 21)
3064#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003065#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02003066#define VIDEO_DIP_ENABLE_SPD (8 << 21)
3067#define VIDEO_DIP_SELECT_AVI (0 << 19)
3068#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3069#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07003070#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02003071#define VIDEO_DIP_FREQ_ONCE (0 << 16)
3072#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3073#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03003074#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003075/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003076#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3077#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003078#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03003079#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3080#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03003081#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02003082
Jesse Barnes585fb112008-07-29 11:54:06 -07003083/* Panel power sequencing */
3084#define PP_STATUS 0x61200
3085#define PP_ON (1 << 31)
3086/*
3087 * Indicates that all dependencies of the panel are on:
3088 *
3089 * - PLL enabled
3090 * - pipe enabled
3091 * - LVDS/DVOB/DVOC on
3092 */
3093#define PP_READY (1 << 30)
3094#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07003095#define PP_SEQUENCE_POWER_UP (1 << 28)
3096#define PP_SEQUENCE_POWER_DOWN (2 << 28)
3097#define PP_SEQUENCE_MASK (3 << 28)
3098#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003099#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003100#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07003101#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3102#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3103#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3104#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3105#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3106#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3107#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3108#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3109#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003110#define PP_CONTROL 0x61204
3111#define POWER_TARGET_ON (1 << 0)
3112#define PP_ON_DELAYS 0x61208
3113#define PP_OFF_DELAYS 0x6120c
3114#define PP_DIVISOR 0x61210
3115
3116/* Panel fitting */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003117#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07003118#define PFIT_ENABLE (1 << 31)
3119#define PFIT_PIPE_MASK (3 << 29)
3120#define PFIT_PIPE_SHIFT 29
3121#define VERT_INTERP_DISABLE (0 << 10)
3122#define VERT_INTERP_BILINEAR (1 << 10)
3123#define VERT_INTERP_MASK (3 << 10)
3124#define VERT_AUTO_SCALE (1 << 9)
3125#define HORIZ_INTERP_DISABLE (0 << 6)
3126#define HORIZ_INTERP_BILINEAR (1 << 6)
3127#define HORIZ_INTERP_MASK (3 << 6)
3128#define HORIZ_AUTO_SCALE (1 << 5)
3129#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003130#define PFIT_FILTER_FUZZY (0 << 24)
3131#define PFIT_SCALING_AUTO (0 << 26)
3132#define PFIT_SCALING_PROGRAMMED (1 << 26)
3133#define PFIT_SCALING_PILLAR (2 << 26)
3134#define PFIT_SCALING_LETTER (3 << 26)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003135#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08003136/* Pre-965 */
3137#define PFIT_VERT_SCALE_SHIFT 20
3138#define PFIT_VERT_SCALE_MASK 0xfff00000
3139#define PFIT_HORIZ_SCALE_SHIFT 4
3140#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3141/* 965+ */
3142#define PFIT_VERT_SCALE_SHIFT_965 16
3143#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3144#define PFIT_HORIZ_SCALE_SHIFT_965 0
3145#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3146
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003147#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07003148
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003149#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3150#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003151#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3152 _VLV_BLC_PWM_CTL2_B)
3153
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003154#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3155#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003156#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3157 _VLV_BLC_PWM_CTL_B)
3158
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003159#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3160#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Jesse Barnes07bf1392013-10-31 18:55:50 +02003161#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3162 _VLV_BLC_HIST_CTL_B)
3163
Jesse Barnes585fb112008-07-29 11:54:06 -07003164/* Backlight control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003165#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003166#define BLM_PWM_ENABLE (1 << 31)
3167#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3168#define BLM_PIPE_SELECT (1 << 29)
3169#define BLM_PIPE_SELECT_IVB (3 << 29)
3170#define BLM_PIPE_A (0 << 29)
3171#define BLM_PIPE_B (1 << 29)
3172#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03003173#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3174#define BLM_TRANSCODER_B BLM_PIPE_B
3175#define BLM_TRANSCODER_C BLM_PIPE_C
3176#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003177#define BLM_PIPE(pipe) ((pipe) << 29)
3178#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3179#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3180#define BLM_PHASE_IN_ENABLE (1 << 25)
3181#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3182#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3183#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3184#define BLM_PHASE_IN_COUNT_SHIFT (8)
3185#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3186#define BLM_PHASE_IN_INCR_SHIFT (0)
3187#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003188#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01003189/*
3190 * This is the most significant 15 bits of the number of backlight cycles in a
3191 * complete cycle of the modulated backlight control.
3192 *
3193 * The actual value is this field multiplied by two.
3194 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02003195#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3196#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3197#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003198/*
3199 * This is the number of cycles out of the backlight modulation cycle for which
3200 * the backlight is on.
3201 *
3202 * This field must be no greater than the number of cycles in the complete
3203 * backlight modulation cycle.
3204 */
3205#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3206#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02003207#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3208#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003209
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003210#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07003211
Daniel Vetter7cf41602012-06-05 10:07:09 +02003212/* New registers for PCH-split platforms. Safe where new bits show up, the
3213 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3214#define BLC_PWM_CPU_CTL2 0x48250
3215#define BLC_PWM_CPU_CTL 0x48254
3216
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003217#define HSW_BLC_PWM2_CTL 0x48350
3218
Daniel Vetter7cf41602012-06-05 10:07:09 +02003219/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3220 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3221#define BLC_PWM_PCH_CTL1 0xc8250
Daniel Vetter4b4147c2012-07-11 00:31:06 +02003222#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003223#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3224#define BLM_PCH_POLARITY (1 << 29)
3225#define BLC_PWM_PCH_CTL2 0xc8254
3226
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003227#define UTIL_PIN_CTL 0x48400
3228#define UTIL_PIN_ENABLE (1 << 31)
3229
3230#define PCH_GTC_CTL 0xe7000
3231#define PCH_GTC_ENABLE (1 << 31)
3232
Jesse Barnes585fb112008-07-29 11:54:06 -07003233/* TV port control */
3234#define TV_CTL 0x68000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003235/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07003236# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003237/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003238# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003239/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003240# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003241/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003242# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003243/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003244# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003245/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003246# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3247# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003248/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003249# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003250/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003251# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003252/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07003253# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003254/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003255# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003256/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07003257# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003258/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07003259# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003260/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003261# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003262/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07003263# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003264/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003265# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003266/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003267 * Enables a fix for the 915GM only.
3268 *
3269 * Not sure what it does.
3270 */
3271# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003272/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08003273# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003274# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003275/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07003276# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003277/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003278# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003279/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003280# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003281/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07003282# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003283/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07003284# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003285/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003286# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003287/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003288# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003289/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07003290# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003291/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07003292# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003293/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003294 * This test mode forces the DACs to 50% of full output.
3295 *
3296 * This is used for load detection in combination with TVDAC_SENSE_MASK
3297 */
3298# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3299# define TV_TEST_MODE_MASK (7 << 0)
3300
3301#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01003302# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003303/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003304 * Reports that DAC state change logic has reported change (RO).
3305 *
3306 * This gets cleared when TV_DAC_STATE_EN is cleared
3307*/
3308# define TVDAC_STATE_CHG (1 << 31)
3309# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003310/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003311# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003312/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003313# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003314/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003315# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003316/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003317 * Enables DAC state detection logic, for load-based TV detection.
3318 *
3319 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3320 * to off, for load detection to work.
3321 */
3322# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003323/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003324# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003325/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003326# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003327/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003328# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003329/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07003330# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003331/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07003332# define ENC_TVDAC_SLEW_FAST (1 << 6)
3333# define DAC_A_1_3_V (0 << 4)
3334# define DAC_A_1_1_V (1 << 4)
3335# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08003336# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003337# define DAC_B_1_3_V (0 << 2)
3338# define DAC_B_1_1_V (1 << 2)
3339# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08003340# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003341# define DAC_C_1_3_V (0 << 0)
3342# define DAC_C_1_1_V (1 << 0)
3343# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08003344# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003345
Ville Syrjälä646b4262014-04-25 20:14:30 +03003346/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003347 * CSC coefficients are stored in a floating point format with 9 bits of
3348 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3349 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3350 * -1 (0x3) being the only legal negative value.
3351 */
3352#define TV_CSC_Y 0x68010
3353# define TV_RY_MASK 0x07ff0000
3354# define TV_RY_SHIFT 16
3355# define TV_GY_MASK 0x00000fff
3356# define TV_GY_SHIFT 0
3357
3358#define TV_CSC_Y2 0x68014
3359# define TV_BY_MASK 0x07ff0000
3360# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003361/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003362 * Y attenuation for component video.
3363 *
3364 * Stored in 1.9 fixed point.
3365 */
3366# define TV_AY_MASK 0x000003ff
3367# define TV_AY_SHIFT 0
3368
3369#define TV_CSC_U 0x68018
3370# define TV_RU_MASK 0x07ff0000
3371# define TV_RU_SHIFT 16
3372# define TV_GU_MASK 0x000007ff
3373# define TV_GU_SHIFT 0
3374
3375#define TV_CSC_U2 0x6801c
3376# define TV_BU_MASK 0x07ff0000
3377# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003378/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003379 * U attenuation for component video.
3380 *
3381 * Stored in 1.9 fixed point.
3382 */
3383# define TV_AU_MASK 0x000003ff
3384# define TV_AU_SHIFT 0
3385
3386#define TV_CSC_V 0x68020
3387# define TV_RV_MASK 0x0fff0000
3388# define TV_RV_SHIFT 16
3389# define TV_GV_MASK 0x000007ff
3390# define TV_GV_SHIFT 0
3391
3392#define TV_CSC_V2 0x68024
3393# define TV_BV_MASK 0x07ff0000
3394# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003395/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003396 * V attenuation for component video.
3397 *
3398 * Stored in 1.9 fixed point.
3399 */
3400# define TV_AV_MASK 0x000007ff
3401# define TV_AV_SHIFT 0
3402
3403#define TV_CLR_KNOBS 0x68028
Ville Syrjälä646b4262014-04-25 20:14:30 +03003404/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07003405# define TV_BRIGHTNESS_MASK 0xff000000
3406# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03003407/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003408# define TV_CONTRAST_MASK 0x00ff0000
3409# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003410/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003411# define TV_SATURATION_MASK 0x0000ff00
3412# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003413/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07003414# define TV_HUE_MASK 0x000000ff
3415# define TV_HUE_SHIFT 0
3416
3417#define TV_CLR_LEVEL 0x6802c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003418/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07003419# define TV_BLACK_LEVEL_MASK 0x01ff0000
3420# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003421/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07003422# define TV_BLANK_LEVEL_MASK 0x000001ff
3423# define TV_BLANK_LEVEL_SHIFT 0
3424
3425#define TV_H_CTL_1 0x68030
Ville Syrjälä646b4262014-04-25 20:14:30 +03003426/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003427# define TV_HSYNC_END_MASK 0x1fff0000
3428# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003429/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07003430# define TV_HTOTAL_MASK 0x00001fff
3431# define TV_HTOTAL_SHIFT 0
3432
3433#define TV_H_CTL_2 0x68034
Ville Syrjälä646b4262014-04-25 20:14:30 +03003434/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003435# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003436/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003437# define TV_HBURST_START_SHIFT 16
3438# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003439/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07003440# define TV_HBURST_LEN_SHIFT 0
3441# define TV_HBURST_LEN_MASK 0x0001fff
3442
3443#define TV_H_CTL_3 0x68038
Ville Syrjälä646b4262014-04-25 20:14:30 +03003444/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003445# define TV_HBLANK_END_SHIFT 16
3446# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003447/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003448# define TV_HBLANK_START_SHIFT 0
3449# define TV_HBLANK_START_MASK 0x0001fff
3450
3451#define TV_V_CTL_1 0x6803c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003452/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003453# define TV_NBR_END_SHIFT 16
3454# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003455/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003456# define TV_VI_END_F1_SHIFT 8
3457# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003458/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003459# define TV_VI_END_F2_SHIFT 0
3460# define TV_VI_END_F2_MASK 0x0000003f
3461
3462#define TV_V_CTL_2 0x68040
Ville Syrjälä646b4262014-04-25 20:14:30 +03003463/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003464# define TV_VSYNC_LEN_MASK 0x07ff0000
3465# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003466/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07003467 * number of half lines.
3468 */
3469# define TV_VSYNC_START_F1_MASK 0x00007f00
3470# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003471/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003472 * Offset of the start of vsync in field 2, measured in one less than the
3473 * number of half lines.
3474 */
3475# define TV_VSYNC_START_F2_MASK 0x0000007f
3476# define TV_VSYNC_START_F2_SHIFT 0
3477
3478#define TV_V_CTL_3 0x68044
Ville Syrjälä646b4262014-04-25 20:14:30 +03003479/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07003480# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003481/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003482# define TV_VEQ_LEN_MASK 0x007f0000
3483# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003484/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07003485 * the number of half lines.
3486 */
3487# define TV_VEQ_START_F1_MASK 0x0007f00
3488# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003489/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003490 * Offset of the start of equalization in field 2, measured in one less than
3491 * the number of half lines.
3492 */
3493# define TV_VEQ_START_F2_MASK 0x000007f
3494# define TV_VEQ_START_F2_SHIFT 0
3495
3496#define TV_V_CTL_4 0x68048
Ville Syrjälä646b4262014-04-25 20:14:30 +03003497/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003498 * Offset to start of vertical colorburst, measured in one less than the
3499 * number of lines from vertical start.
3500 */
3501# define TV_VBURST_START_F1_MASK 0x003f0000
3502# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003503/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003504 * Offset to the end of vertical colorburst, measured in one less than the
3505 * number of lines from the start of NBR.
3506 */
3507# define TV_VBURST_END_F1_MASK 0x000000ff
3508# define TV_VBURST_END_F1_SHIFT 0
3509
3510#define TV_V_CTL_5 0x6804c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003511/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003512 * Offset to start of vertical colorburst, measured in one less than the
3513 * number of lines from vertical start.
3514 */
3515# define TV_VBURST_START_F2_MASK 0x003f0000
3516# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003517/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003518 * Offset to the end of vertical colorburst, measured in one less than the
3519 * number of lines from the start of NBR.
3520 */
3521# define TV_VBURST_END_F2_MASK 0x000000ff
3522# define TV_VBURST_END_F2_SHIFT 0
3523
3524#define TV_V_CTL_6 0x68050
Ville Syrjälä646b4262014-04-25 20:14:30 +03003525/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003526 * Offset to start of vertical colorburst, measured in one less than the
3527 * number of lines from vertical start.
3528 */
3529# define TV_VBURST_START_F3_MASK 0x003f0000
3530# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003531/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003532 * Offset to the end of vertical colorburst, measured in one less than the
3533 * number of lines from the start of NBR.
3534 */
3535# define TV_VBURST_END_F3_MASK 0x000000ff
3536# define TV_VBURST_END_F3_SHIFT 0
3537
3538#define TV_V_CTL_7 0x68054
Ville Syrjälä646b4262014-04-25 20:14:30 +03003539/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003540 * Offset to start of vertical colorburst, measured in one less than the
3541 * number of lines from vertical start.
3542 */
3543# define TV_VBURST_START_F4_MASK 0x003f0000
3544# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003545/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003546 * Offset to the end of vertical colorburst, measured in one less than the
3547 * number of lines from the start of NBR.
3548 */
3549# define TV_VBURST_END_F4_MASK 0x000000ff
3550# define TV_VBURST_END_F4_SHIFT 0
3551
3552#define TV_SC_CTL_1 0x68060
Ville Syrjälä646b4262014-04-25 20:14:30 +03003553/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003554# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003555/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003556# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003557/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003558# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003559/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003560# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003561/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003562# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003563/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003564# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003565/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07003566# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003567/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003568# define TV_BURST_LEVEL_MASK 0x00ff0000
3569# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003570/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003571# define TV_SCDDA1_INC_MASK 0x00000fff
3572# define TV_SCDDA1_INC_SHIFT 0
3573
3574#define TV_SC_CTL_2 0x68064
Ville Syrjälä646b4262014-04-25 20:14:30 +03003575/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003576# define TV_SCDDA2_SIZE_MASK 0x7fff0000
3577# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003578/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003579# define TV_SCDDA2_INC_MASK 0x00007fff
3580# define TV_SCDDA2_INC_SHIFT 0
3581
3582#define TV_SC_CTL_3 0x68068
Ville Syrjälä646b4262014-04-25 20:14:30 +03003583/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003584# define TV_SCDDA3_SIZE_MASK 0x7fff0000
3585# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003586/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003587# define TV_SCDDA3_INC_MASK 0x00007fff
3588# define TV_SCDDA3_INC_SHIFT 0
3589
3590#define TV_WIN_POS 0x68070
Ville Syrjälä646b4262014-04-25 20:14:30 +03003591/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07003592# define TV_XPOS_MASK 0x1fff0000
3593# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003594/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003595# define TV_YPOS_MASK 0x00000fff
3596# define TV_YPOS_SHIFT 0
3597
3598#define TV_WIN_SIZE 0x68074
Ville Syrjälä646b4262014-04-25 20:14:30 +03003599/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003600# define TV_XSIZE_MASK 0x1fff0000
3601# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003602/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003603 * Vertical size of the display window, measured in pixels.
3604 *
3605 * Must be even for interlaced modes.
3606 */
3607# define TV_YSIZE_MASK 0x00000fff
3608# define TV_YSIZE_SHIFT 0
3609
3610#define TV_FILTER_CTL_1 0x68080
Ville Syrjälä646b4262014-04-25 20:14:30 +03003611/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003612 * Enables automatic scaling calculation.
3613 *
3614 * If set, the rest of the registers are ignored, and the calculated values can
3615 * be read back from the register.
3616 */
3617# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003618/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003619 * Disables the vertical filter.
3620 *
3621 * This is required on modes more than 1024 pixels wide */
3622# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003623/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07003624# define TV_VADAPT (1 << 28)
3625# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003626/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003627# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003628/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003629# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003630/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003631# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003632/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003633 * Sets the horizontal scaling factor.
3634 *
3635 * This should be the fractional part of the horizontal scaling factor divided
3636 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3637 *
3638 * (src width - 1) / ((oversample * dest width) - 1)
3639 */
3640# define TV_HSCALE_FRAC_MASK 0x00003fff
3641# define TV_HSCALE_FRAC_SHIFT 0
3642
3643#define TV_FILTER_CTL_2 0x68084
Ville Syrjälä646b4262014-04-25 20:14:30 +03003644/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003645 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3646 *
3647 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3648 */
3649# define TV_VSCALE_INT_MASK 0x00038000
3650# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003651/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003652 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3653 *
3654 * \sa TV_VSCALE_INT_MASK
3655 */
3656# define TV_VSCALE_FRAC_MASK 0x00007fff
3657# define TV_VSCALE_FRAC_SHIFT 0
3658
3659#define TV_FILTER_CTL_3 0x68088
Ville Syrjälä646b4262014-04-25 20:14:30 +03003660/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003661 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3662 *
3663 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3664 *
3665 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3666 */
3667# define TV_VSCALE_IP_INT_MASK 0x00038000
3668# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003669/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003670 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3671 *
3672 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3673 *
3674 * \sa TV_VSCALE_IP_INT_MASK
3675 */
3676# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3677# define TV_VSCALE_IP_FRAC_SHIFT 0
3678
3679#define TV_CC_CONTROL 0x68090
3680# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003681/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003682 * Specifies which field to send the CC data in.
3683 *
3684 * CC data is usually sent in field 0.
3685 */
3686# define TV_CC_FID_MASK (1 << 27)
3687# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03003688/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003689# define TV_CC_HOFF_MASK 0x03ff0000
3690# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003691/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07003692# define TV_CC_LINE_MASK 0x0000003f
3693# define TV_CC_LINE_SHIFT 0
3694
3695#define TV_CC_DATA 0x68094
3696# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003697/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003698# define TV_CC_DATA_2_MASK 0x007f0000
3699# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003700/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003701# define TV_CC_DATA_1_MASK 0x0000007f
3702# define TV_CC_DATA_1_SHIFT 0
3703
3704#define TV_H_LUMA_0 0x68100
3705#define TV_H_LUMA_59 0x681ec
3706#define TV_H_CHROMA_0 0x68200
3707#define TV_H_CHROMA_59 0x682ec
3708#define TV_V_LUMA_0 0x68300
3709#define TV_V_LUMA_42 0x683a8
3710#define TV_V_CHROMA_0 0x68400
3711#define TV_V_CHROMA_42 0x684a8
3712
Keith Packard040d87f2009-05-30 20:42:33 -07003713/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003714#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07003715#define DP_B 0x64100
3716#define DP_C 0x64200
3717#define DP_D 0x64300
3718
3719#define DP_PORT_EN (1 << 31)
3720#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003721#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03003722#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3723#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003724
Keith Packard040d87f2009-05-30 20:42:33 -07003725/* Link training mode - select a suitable mode for each stage */
3726#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3727#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3728#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3729#define DP_LINK_TRAIN_OFF (3 << 28)
3730#define DP_LINK_TRAIN_MASK (3 << 28)
3731#define DP_LINK_TRAIN_SHIFT 28
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003732#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
3733#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
Keith Packard040d87f2009-05-30 20:42:33 -07003734
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003735/* CPT Link training mode */
3736#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3737#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3738#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3739#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3740#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3741#define DP_LINK_TRAIN_SHIFT_CPT 8
3742
Keith Packard040d87f2009-05-30 20:42:33 -07003743/* Signal voltages. These are mostly controlled by the other end */
3744#define DP_VOLTAGE_0_4 (0 << 25)
3745#define DP_VOLTAGE_0_6 (1 << 25)
3746#define DP_VOLTAGE_0_8 (2 << 25)
3747#define DP_VOLTAGE_1_2 (3 << 25)
3748#define DP_VOLTAGE_MASK (7 << 25)
3749#define DP_VOLTAGE_SHIFT 25
3750
3751/* Signal pre-emphasis levels, like voltages, the other end tells us what
3752 * they want
3753 */
3754#define DP_PRE_EMPHASIS_0 (0 << 22)
3755#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3756#define DP_PRE_EMPHASIS_6 (2 << 22)
3757#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3758#define DP_PRE_EMPHASIS_MASK (7 << 22)
3759#define DP_PRE_EMPHASIS_SHIFT 22
3760
3761/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02003762#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07003763#define DP_PORT_WIDTH_MASK (7 << 19)
3764
3765/* Mystic DPCD version 1.1 special mode */
3766#define DP_ENHANCED_FRAMING (1 << 18)
3767
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003768/* eDP */
3769#define DP_PLL_FREQ_270MHZ (0 << 16)
3770#define DP_PLL_FREQ_160MHZ (1 << 16)
3771#define DP_PLL_FREQ_MASK (3 << 16)
3772
Ville Syrjälä646b4262014-04-25 20:14:30 +03003773/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07003774#define DP_PORT_REVERSAL (1 << 15)
3775
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003776/* eDP */
3777#define DP_PLL_ENABLE (1 << 14)
3778
Ville Syrjälä646b4262014-04-25 20:14:30 +03003779/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07003780#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3781
3782#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003783#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07003784
Ville Syrjälä646b4262014-04-25 20:14:30 +03003785/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07003786#define DP_COLOR_RANGE_16_235 (1 << 8)
3787
Ville Syrjälä646b4262014-04-25 20:14:30 +03003788/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07003789#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3790
Ville Syrjälä646b4262014-04-25 20:14:30 +03003791/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07003792#define DP_SYNC_VS_HIGH (1 << 4)
3793#define DP_SYNC_HS_HIGH (1 << 3)
3794
Ville Syrjälä646b4262014-04-25 20:14:30 +03003795/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07003796#define DP_DETECTED (1 << 2)
3797
Ville Syrjälä646b4262014-04-25 20:14:30 +03003798/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07003799 * signal sink for DDC etc. Max packet size supported
3800 * is 20 bytes in each direction, hence the 5 fixed
3801 * data registers
3802 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003803#define DPA_AUX_CH_CTL 0x64010
3804#define DPA_AUX_CH_DATA1 0x64014
3805#define DPA_AUX_CH_DATA2 0x64018
3806#define DPA_AUX_CH_DATA3 0x6401c
3807#define DPA_AUX_CH_DATA4 0x64020
3808#define DPA_AUX_CH_DATA5 0x64024
3809
Keith Packard040d87f2009-05-30 20:42:33 -07003810#define DPB_AUX_CH_CTL 0x64110
3811#define DPB_AUX_CH_DATA1 0x64114
3812#define DPB_AUX_CH_DATA2 0x64118
3813#define DPB_AUX_CH_DATA3 0x6411c
3814#define DPB_AUX_CH_DATA4 0x64120
3815#define DPB_AUX_CH_DATA5 0x64124
3816
3817#define DPC_AUX_CH_CTL 0x64210
3818#define DPC_AUX_CH_DATA1 0x64214
3819#define DPC_AUX_CH_DATA2 0x64218
3820#define DPC_AUX_CH_DATA3 0x6421c
3821#define DPC_AUX_CH_DATA4 0x64220
3822#define DPC_AUX_CH_DATA5 0x64224
3823
3824#define DPD_AUX_CH_CTL 0x64310
3825#define DPD_AUX_CH_DATA1 0x64314
3826#define DPD_AUX_CH_DATA2 0x64318
3827#define DPD_AUX_CH_DATA3 0x6431c
3828#define DPD_AUX_CH_DATA4 0x64320
3829#define DPD_AUX_CH_DATA5 0x64324
3830
3831#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3832#define DP_AUX_CH_CTL_DONE (1 << 30)
3833#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3834#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3835#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3836#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3837#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3838#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3839#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3840#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3841#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3842#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3843#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3844#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3845#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3846#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3847#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3848#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3849#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3850#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3851#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
Sonika Jindale3d99842015-01-22 14:30:54 +05303852#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
3853#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
3854#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
3855#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
3856#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00003857#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
Keith Packard040d87f2009-05-30 20:42:33 -07003858
3859/*
3860 * Computing GMCH M and N values for the Display Port link
3861 *
3862 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3863 *
3864 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3865 *
3866 * The GMCH value is used internally
3867 *
3868 * bytes_per_pixel is the number of bytes coming out of the plane,
3869 * which is after the LUTs, so we want the bytes for our color format.
3870 * For our current usage, this is always 3, one byte for R, G and B.
3871 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02003872#define _PIPEA_DATA_M_G4X 0x70050
3873#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07003874
3875/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003876#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02003877#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003878#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07003879
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003880#define DATA_LINK_M_N_MASK (0xffffff)
3881#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07003882
Daniel Vettere3b95f12013-05-03 11:49:49 +02003883#define _PIPEA_DATA_N_G4X 0x70054
3884#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07003885#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3886
3887/*
3888 * Computing Link M and N values for the Display Port link
3889 *
3890 * Link M / N = pixel_clock / ls_clk
3891 *
3892 * (the DP spec calls pixel_clock the 'strm_clk')
3893 *
3894 * The Link value is transmitted in the Main Stream
3895 * Attributes and VB-ID.
3896 */
3897
Daniel Vettere3b95f12013-05-03 11:49:49 +02003898#define _PIPEA_LINK_M_G4X 0x70060
3899#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07003900#define PIPEA_DP_LINK_M_MASK (0xffffff)
3901
Daniel Vettere3b95f12013-05-03 11:49:49 +02003902#define _PIPEA_LINK_N_G4X 0x70064
3903#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07003904#define PIPEA_DP_LINK_N_MASK (0xffffff)
3905
Daniel Vettere3b95f12013-05-03 11:49:49 +02003906#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3907#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3908#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3909#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003910
Jesse Barnes585fb112008-07-29 11:54:06 -07003911/* Display & cursor control */
3912
3913/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003914#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03003915#define DSL_LINEMASK_GEN2 0x00000fff
3916#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003917#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01003918#define PIPECONF_ENABLE (1<<31)
3919#define PIPECONF_DISABLE 0
3920#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003921#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03003922#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00003923#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01003924#define PIPECONF_SINGLE_WIDE 0
3925#define PIPECONF_PIPE_UNLOCKED 0
3926#define PIPECONF_PIPE_LOCKED (1<<25)
3927#define PIPECONF_PALETTE 0
3928#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07003929#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01003930#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03003931#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01003932/* Note that pre-gen3 does not support interlaced display directly. Panel
3933 * fitting must be disabled on pre-ilk for interlaced. */
3934#define PIPECONF_PROGRESSIVE (0 << 21)
3935#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3936#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3937#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3938#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3939/* Ironlake and later have a complete new set of values for interlaced. PFIT
3940 * means panel fitter required, PF means progressive fetch, DBL means power
3941 * saving pixel doubling. */
3942#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3943#define PIPECONF_INTERLACED_ILK (3 << 21)
3944#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3945#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02003946#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303947#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07003948#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05303949#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02003950#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003951#define PIPECONF_BPC_MASK (0x7 << 5)
3952#define PIPECONF_8BPC (0<<5)
3953#define PIPECONF_10BPC (1<<5)
3954#define PIPECONF_6BPC (2<<5)
3955#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07003956#define PIPECONF_DITHER_EN (1<<4)
3957#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3958#define PIPECONF_DITHER_TYPE_SP (0<<2)
3959#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3960#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3961#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003962#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07003963#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02003964#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003965#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3966#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003967#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003968#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003969#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003970#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3971#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3972#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3973#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02003974#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07003975#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3976#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3977#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02003978#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003979#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07003980#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3981#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003982#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07003983#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003984#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003985#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02003986#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3987#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07003988#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3989#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003990#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07003991#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02003992#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003993#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3994#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3995#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3996#define PIPE_DPST_EVENT_STATUS (1UL<<7)
Imre Deak10c59c52014-02-10 18:42:48 +02003997#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003998#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07003999#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4000#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02004001#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004002#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07004003#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4004#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004005#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07004006#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03004007#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07004008#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4009
Imre Deak755e9012014-02-10 18:42:47 +02004010#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4011#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4012
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03004013#define PIPE_A_OFFSET 0x70000
4014#define PIPE_B_OFFSET 0x71000
4015#define PIPE_C_OFFSET 0x72000
4016#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004017/*
4018 * There's actually no pipe EDP. Some pipe registers have
4019 * simply shifted from the pipe to the transcoder, while
4020 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4021 * to access such registers in transcoder EDP.
4022 */
4023#define PIPE_EDP_OFFSET 0x7f000
4024
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004025#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4026 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4027 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004028
4029#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
4030#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
4031#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
4032#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
4033#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01004034
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004035#define _PIPE_MISC_A 0x70030
4036#define _PIPE_MISC_B 0x71030
4037#define PIPEMISC_DITHER_BPC_MASK (7<<5)
4038#define PIPEMISC_DITHER_8_BPC (0<<5)
4039#define PIPEMISC_DITHER_10_BPC (1<<5)
4040#define PIPEMISC_DITHER_6_BPC (2<<5)
4041#define PIPEMISC_DITHER_12_BPC (3<<5)
4042#define PIPEMISC_DITHER_ENABLE (1<<4)
4043#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4044#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004045#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07004046
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02004047#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07004048#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004049#define PIPEB_HLINE_INT_EN (1<<28)
4050#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02004051#define SPRITED_FLIP_DONE_INT_EN (1<<26)
4052#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4053#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004054#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07004055#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004056#define PIPEA_HLINE_INT_EN (1<<20)
4057#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02004058#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4059#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004060#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03004061#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4062#define PIPEC_HLINE_INT_EN (1<<12)
4063#define PIPEC_VBLANK_INT_EN (1<<11)
4064#define SPRITEF_FLIPDONE_INT_EN (1<<10)
4065#define SPRITEE_FLIPDONE_INT_EN (1<<9)
4066#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004067
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004068#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4069#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4070#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4071#define PLANEC_INVALID_GTT_INT_EN (1<<25)
4072#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004073#define CURSORB_INVALID_GTT_INT_EN (1<<23)
4074#define CURSORA_INVALID_GTT_INT_EN (1<<22)
4075#define SPRITED_INVALID_GTT_INT_EN (1<<21)
4076#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4077#define PLANEB_INVALID_GTT_INT_EN (1<<19)
4078#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4079#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4080#define PLANEA_INVALID_GTT_INT_EN (1<<16)
4081#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004082#define DPINVGTT_EN_MASK_CHV 0xfff0000
4083#define SPRITEF_INVALID_GTT_STATUS (1<<11)
4084#define SPRITEE_INVALID_GTT_STATUS (1<<10)
4085#define PLANEC_INVALID_GTT_STATUS (1<<9)
4086#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004087#define CURSORB_INVALID_GTT_STATUS (1<<7)
4088#define CURSORA_INVALID_GTT_STATUS (1<<6)
4089#define SPRITED_INVALID_GTT_STATUS (1<<5)
4090#define SPRITEC_INVALID_GTT_STATUS (1<<4)
4091#define PLANEB_INVALID_GTT_STATUS (1<<3)
4092#define SPRITEB_INVALID_GTT_STATUS (1<<2)
4093#define SPRITEA_INVALID_GTT_STATUS (1<<1)
4094#define PLANEA_INVALID_GTT_STATUS (1<<0)
4095#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03004096#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07004097
Ville Syrjäläb5004722015-03-05 21:19:47 +02004098#define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
Jesse Barnes585fb112008-07-29 11:54:06 -07004099#define DSPARB_CSTART_MASK (0x7f << 7)
4100#define DSPARB_CSTART_SHIFT 7
4101#define DSPARB_BSTART_MASK (0x7f)
4102#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08004103#define DSPARB_BEND_SHIFT 9 /* on 855 */
4104#define DSPARB_AEND_SHIFT 0
4105
Ville Syrjäläb5004722015-03-05 21:19:47 +02004106#define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4107#define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */
4108
Ville Syrjälä0a560672014-06-11 16:51:18 +03004109/* pnv/gen4/g4x/vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004110#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004111#define DSPFW_SR_SHIFT 23
4112#define DSPFW_SR_MASK (0x1ff<<23)
4113#define DSPFW_CURSORB_SHIFT 16
4114#define DSPFW_CURSORB_MASK (0x3f<<16)
4115#define DSPFW_PLANEB_SHIFT 8
4116#define DSPFW_PLANEB_MASK (0x7f<<8)
4117#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4118#define DSPFW_PLANEA_SHIFT 0
4119#define DSPFW_PLANEA_MASK (0x7f<<0)
4120#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004121#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004122#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4123#define DSPFW_FBC_SR_SHIFT 28
4124#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4125#define DSPFW_FBC_HPLL_SR_SHIFT 24
4126#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4127#define DSPFW_SPRITEB_SHIFT (16)
4128#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4129#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4130#define DSPFW_CURSORA_SHIFT 8
4131#define DSPFW_CURSORA_MASK (0x3f<<8)
Ville Syrjäläf4998962015-03-10 17:02:21 +02004132#define DSPFW_PLANEC_OLD_SHIFT 0
4133#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004134#define DSPFW_SPRITEA_SHIFT 0
4135#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4136#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004137#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004138#define DSPFW_HPLL_SR_EN (1<<31)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004139#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004140#define DSPFW_CURSOR_SR_SHIFT 24
Zhao Yakuid4294342010-03-22 22:45:36 +08004141#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4142#define DSPFW_HPLL_CURSOR_SHIFT 16
4143#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004144#define DSPFW_HPLL_SR_SHIFT 0
4145#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4146
4147/* vlv/chv */
4148#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4149#define DSPFW_SPRITEB_WM1_SHIFT 16
4150#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4151#define DSPFW_CURSORA_WM1_SHIFT 8
4152#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4153#define DSPFW_SPRITEA_WM1_SHIFT 0
4154#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4155#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4156#define DSPFW_PLANEB_WM1_SHIFT 24
4157#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4158#define DSPFW_PLANEA_WM1_SHIFT 16
4159#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4160#define DSPFW_CURSORB_WM1_SHIFT 8
4161#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4162#define DSPFW_CURSOR_SR_WM1_SHIFT 0
4163#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4164#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4165#define DSPFW_SR_WM1_SHIFT 0
4166#define DSPFW_SR_WM1_MASK (0x1ff<<0)
4167#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4168#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4169#define DSPFW_SPRITED_WM1_SHIFT 24
4170#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4171#define DSPFW_SPRITED_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004172#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004173#define DSPFW_SPRITEC_WM1_SHIFT 8
4174#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4175#define DSPFW_SPRITEC_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004176#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004177#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4178#define DSPFW_SPRITEF_WM1_SHIFT 24
4179#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4180#define DSPFW_SPRITEF_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004181#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004182#define DSPFW_SPRITEE_WM1_SHIFT 8
4183#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4184#define DSPFW_SPRITEE_SHIFT 0
Ville Syrjälä15665972015-03-10 16:16:28 +02004185#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004186#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4187#define DSPFW_PLANEC_WM1_SHIFT 24
4188#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4189#define DSPFW_PLANEC_SHIFT 16
Ville Syrjälä15665972015-03-10 16:16:28 +02004190#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03004191#define DSPFW_CURSORC_WM1_SHIFT 8
4192#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4193#define DSPFW_CURSORC_SHIFT 0
4194#define DSPFW_CURSORC_MASK (0x3f<<0)
4195
4196/* vlv/chv high order bits */
4197#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4198#define DSPFW_SR_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004199#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004200#define DSPFW_SPRITEF_HI_SHIFT 23
4201#define DSPFW_SPRITEF_HI_MASK (1<<23)
4202#define DSPFW_SPRITEE_HI_SHIFT 22
4203#define DSPFW_SPRITEE_HI_MASK (1<<22)
4204#define DSPFW_PLANEC_HI_SHIFT 21
4205#define DSPFW_PLANEC_HI_MASK (1<<21)
4206#define DSPFW_SPRITED_HI_SHIFT 20
4207#define DSPFW_SPRITED_HI_MASK (1<<20)
4208#define DSPFW_SPRITEC_HI_SHIFT 16
4209#define DSPFW_SPRITEC_HI_MASK (1<<16)
4210#define DSPFW_PLANEB_HI_SHIFT 12
4211#define DSPFW_PLANEB_HI_MASK (1<<12)
4212#define DSPFW_SPRITEB_HI_SHIFT 8
4213#define DSPFW_SPRITEB_HI_MASK (1<<8)
4214#define DSPFW_SPRITEA_HI_SHIFT 4
4215#define DSPFW_SPRITEA_HI_MASK (1<<4)
4216#define DSPFW_PLANEA_HI_SHIFT 0
4217#define DSPFW_PLANEA_HI_MASK (1<<0)
4218#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4219#define DSPFW_SR_WM1_HI_SHIFT 24
Ville Syrjäläae801522015-03-05 21:19:49 +02004220#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
Ville Syrjälä0a560672014-06-11 16:51:18 +03004221#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4222#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4223#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4224#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4225#define DSPFW_PLANEC_WM1_HI_SHIFT 21
4226#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4227#define DSPFW_SPRITED_WM1_HI_SHIFT 20
4228#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4229#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4230#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4231#define DSPFW_PLANEB_WM1_HI_SHIFT 12
4232#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4233#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4234#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4235#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4236#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4237#define DSPFW_PLANEA_WM1_HI_SHIFT 0
4238#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004239
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004240/* drain latency register values*/
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004241#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004242#define DDL_CURSOR_SHIFT 24
Gajanan Bhat01e184c2014-08-07 17:03:30 +05304243#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004244#define DDL_PLANE_SHIFT 0
Ville Syrjälä341c5262015-03-05 21:19:44 +02004245#define DDL_PRECISION_HIGH (1<<7)
4246#define DDL_PRECISION_LOW (0<<7)
Gajanan Bhat0948c262014-08-07 01:58:24 +05304247#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004248
Ville Syrjäläc6beb132015-03-05 21:19:48 +02004249#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
4250#define CBR_PND_DEADLINE_DISABLE (1<<31)
4251
Shaohua Li7662c8b2009-06-26 11:23:55 +08004252/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09004253#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08004254#define I915_FIFO_LINE_SIZE 64
4255#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09004256
Jesse Barnesceb04242012-03-28 13:39:22 -07004257#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09004258#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08004259#define I965_FIFO_SIZE 512
4260#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08004261#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004262#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004263#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09004264
Jesse Barnesceb04242012-03-28 13:39:22 -07004265#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09004266#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08004267#define I915_MAX_WM 0x3f
4268
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004269#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4270#define PINEVIEW_FIFO_LINE_SIZE 64
4271#define PINEVIEW_MAX_WM 0x1ff
4272#define PINEVIEW_DFT_WM 0x3f
4273#define PINEVIEW_DFT_HPLLOFF_WM 0
4274#define PINEVIEW_GUARD_WM 10
4275#define PINEVIEW_CURSOR_FIFO 64
4276#define PINEVIEW_CURSOR_MAX_WM 0x3f
4277#define PINEVIEW_CURSOR_DFT_WM 0
4278#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08004279
Jesse Barnesceb04242012-03-28 13:39:22 -07004280#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004281#define I965_CURSOR_FIFO 64
4282#define I965_CURSOR_MAX_WM 32
4283#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004284
Pradeep Bhatfae12672014-11-04 17:06:39 +00004285/* Watermark register definitions for SKL */
4286#define CUR_WM_A_0 0x70140
4287#define CUR_WM_B_0 0x71140
4288#define PLANE_WM_1_A_0 0x70240
4289#define PLANE_WM_1_B_0 0x71240
4290#define PLANE_WM_2_A_0 0x70340
4291#define PLANE_WM_2_B_0 0x71340
4292#define PLANE_WM_TRANS_1_A_0 0x70268
4293#define PLANE_WM_TRANS_1_B_0 0x71268
4294#define PLANE_WM_TRANS_2_A_0 0x70368
4295#define PLANE_WM_TRANS_2_B_0 0x71368
4296#define CUR_WM_TRANS_A_0 0x70168
4297#define CUR_WM_TRANS_B_0 0x71168
4298#define PLANE_WM_EN (1 << 31)
4299#define PLANE_WM_LINES_SHIFT 14
4300#define PLANE_WM_LINES_MASK 0x1f
4301#define PLANE_WM_BLOCKS_MASK 0x3ff
4302
4303#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4304#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4305#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4306
4307#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4308#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4309#define _PLANE_WM_BASE(pipe, plane) \
4310 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4311#define PLANE_WM(pipe, plane, level) \
4312 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4313#define _PLANE_WM_TRANS_1(pipe) \
4314 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4315#define _PLANE_WM_TRANS_2(pipe) \
4316 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4317#define PLANE_WM_TRANS(pipe, plane) \
4318 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4319
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004320/* define the Watermark register on Ironlake */
4321#define WM0_PIPEA_ILK 0x45100
Ville Syrjälä1996d622013-10-09 19:18:07 +03004322#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004323#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03004324#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004325#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004326#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004327
4328#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07004329#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004330#define WM1_LP_ILK 0x45108
4331#define WM1_LP_SR_EN (1<<31)
4332#define WM1_LP_LATENCY_SHIFT 24
4333#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01004334#define WM1_LP_FBC_MASK (0xf<<20)
4335#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07004336#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03004337#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004338#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004339#define WM1_LP_CURSOR_MASK (0xff)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004340#define WM2_LP_ILK 0x4510c
4341#define WM2_LP_EN (1<<31)
4342#define WM3_LP_ILK 0x45110
4343#define WM3_LP_EN (1<<31)
4344#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004345#define WM2S_LP_IVB 0x45124
4346#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004347#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004348
Paulo Zanonicca32e92013-05-31 11:45:06 -03004349#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4350 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4351 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4352
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004353/* Memory latency timer register */
4354#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08004355#define MLTR_WM1_SHIFT 0
4356#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004357/* the unit of memory self-refresh latency time is 0.5us */
4358#define ILK_SRLT_MASK 0x3f
4359
Yuanhan Liu13982612010-12-15 15:42:31 +08004360
4361/* the address where we get all kinds of latency value */
4362#define SSKPD 0x5d10
4363#define SSKPD_WM_MASK 0x3f
4364#define SSKPD_WM0_SHIFT 0
4365#define SSKPD_WM1_SHIFT 8
4366#define SSKPD_WM2_SHIFT 16
4367#define SSKPD_WM3_SHIFT 24
4368
Jesse Barnes585fb112008-07-29 11:54:06 -07004369/*
4370 * The two pipe frame counter registers are not synchronized, so
4371 * reading a stable value is somewhat tricky. The following code
4372 * should work:
4373 *
4374 * do {
4375 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4376 * PIPE_FRAME_HIGH_SHIFT;
4377 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4378 * PIPE_FRAME_LOW_SHIFT);
4379 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4380 * PIPE_FRAME_HIGH_SHIFT);
4381 * } while (high1 != high2);
4382 * frame = (high1 << 8) | low1;
4383 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004384#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07004385#define PIPE_FRAME_HIGH_MASK 0x0000ffff
4386#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004387#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07004388#define PIPE_FRAME_LOW_MASK 0xff000000
4389#define PIPE_FRAME_LOW_SHIFT 24
4390#define PIPE_PIXEL_MASK 0x00ffffff
4391#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004392/* GM45+ just has to be different */
Rafael Barbalhoeb6008a2014-03-31 18:21:29 +03004393#define _PIPEA_FRMCOUNT_GM45 0x70040
4394#define _PIPEA_FLIPCOUNT_GM45 0x70044
4395#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03004396#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07004397
4398/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004399#define _CURACNTR 0x70080
Jesse Barnes14b60392009-05-20 16:47:08 -04004400/* Old style CUR*CNTR flags (desktop 8xx) */
4401#define CURSOR_ENABLE 0x80000000
4402#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03004403#define CURSOR_STRIDE_SHIFT 28
4404#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004405#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b60392009-05-20 16:47:08 -04004406#define CURSOR_FORMAT_SHIFT 24
4407#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4408#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4409#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4410#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4411#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4412#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4413/* New style CUR*CNTR flags */
4414#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07004415#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304416#define CURSOR_MODE_128_32B_AX 0x02
4417#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07004418#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304419#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4420#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07004421#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b60392009-05-20 16:47:08 -04004422#define MCURSOR_PIPE_SELECT (1 << 28)
4423#define MCURSOR_PIPE_A 0x00
4424#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07004425#define MCURSOR_GAMMA_ENABLE (1 << 26)
Ville Syrjälä4398ad42014-10-23 07:41:34 -07004426#define CURSOR_ROTATE_180 (1<<15)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03004427#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004428#define _CURABASE 0x70084
4429#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07004430#define CURSOR_POS_MASK 0x007FF
4431#define CURSOR_POS_SIGN 0x8000
4432#define CURSOR_X_SHIFT 0
4433#define CURSOR_Y_SHIFT 16
Jesse Barnes14b60392009-05-20 16:47:08 -04004434#define CURSIZE 0x700a0
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004435#define _CURBCNTR 0x700c0
4436#define _CURBBASE 0x700c4
4437#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07004438
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004439#define _CURBCNTR_IVB 0x71080
4440#define _CURBBASE_IVB 0x71084
4441#define _CURBPOS_IVB 0x71088
4442
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004443#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4444 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4445 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00004446
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004447#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4448#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4449#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4450
4451#define CURSOR_A_OFFSET 0x70080
4452#define CURSOR_B_OFFSET 0x700c0
4453#define CHV_CURSOR_C_OFFSET 0x700e0
4454#define IVB_CURSOR_B_OFFSET 0x71080
4455#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004456
Jesse Barnes585fb112008-07-29 11:54:06 -07004457/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004458#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07004459#define DISPLAY_PLANE_ENABLE (1<<31)
4460#define DISPLAY_PLANE_DISABLE 0
4461#define DISPPLANE_GAMMA_ENABLE (1<<30)
4462#define DISPPLANE_GAMMA_DISABLE 0
4463#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004464#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004465#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004466#define DISPPLANE_BGRA555 (0x3<<26)
4467#define DISPPLANE_BGRX555 (0x4<<26)
4468#define DISPPLANE_BGRX565 (0x5<<26)
4469#define DISPPLANE_BGRX888 (0x6<<26)
4470#define DISPPLANE_BGRA888 (0x7<<26)
4471#define DISPPLANE_RGBX101010 (0x8<<26)
4472#define DISPPLANE_RGBA101010 (0x9<<26)
4473#define DISPPLANE_BGRX101010 (0xa<<26)
4474#define DISPPLANE_RGBX161616 (0xc<<26)
4475#define DISPPLANE_RGBX888 (0xe<<26)
4476#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004477#define DISPPLANE_STEREO_ENABLE (1<<25)
4478#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004479#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08004480#define DISPPLANE_SEL_PIPE_SHIFT 24
4481#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004482#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08004483#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004484#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4485#define DISPPLANE_SRC_KEY_DISABLE 0
4486#define DISPPLANE_LINE_DOUBLE (1<<20)
4487#define DISPPLANE_NO_LINE_DOUBLE 0
4488#define DISPPLANE_STEREO_POLARITY_FIRST 0
4489#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004490#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4491#define DISPPLANE_ROTATE_180 (1<<15)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004492#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07004493#define DISPPLANE_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004494#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004495#define _DSPAADDR 0x70184
4496#define _DSPASTRIDE 0x70188
4497#define _DSPAPOS 0x7018C /* reserved */
4498#define _DSPASIZE 0x70190
4499#define _DSPASURF 0x7019C /* 965+ only */
4500#define _DSPATILEOFF 0x701A4 /* 965+ only */
4501#define _DSPAOFFSET 0x701A4 /* HSW */
4502#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07004503
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004504#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4505#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4506#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4507#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4508#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4509#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4510#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
Daniel Vettere506a0c2012-07-05 12:17:29 +02004511#define DSPLINOFF(plane) DSPADDR(plane)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004512#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4513#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01004514
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004515/* CHV pipe B blender and primary plane */
4516#define _CHV_BLEND_A 0x60a00
4517#define CHV_BLEND_LEGACY (0<<30)
4518#define CHV_BLEND_ANDROID (1<<30)
4519#define CHV_BLEND_MPO (2<<30)
4520#define CHV_BLEND_MASK (3<<30)
4521#define _CHV_CANVAS_A 0x60a04
4522#define _PRIMPOS_A 0x60a08
4523#define _PRIMSIZE_A 0x60a0c
4524#define _PRIMCNSTALPHA_A 0x60a10
4525#define PRIM_CONST_ALPHA_ENABLE (1<<31)
4526
4527#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4528#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4529#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4530#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4531#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4532
Armin Reese446f2542012-03-30 16:20:16 -07004533/* Display/Sprite base address macros */
4534#define DISP_BASEADDR_MASK (0xfffff000)
4535#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4536#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07004537
Jesse Barnes585fb112008-07-29 11:54:06 -07004538/* VBIOS flags */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004539#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4540#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4541#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4542#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4543#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4544#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4545#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4546#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4547#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4548#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4549#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4550#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4551#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
Jesse Barnes585fb112008-07-29 11:54:06 -07004552
4553/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004554#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4555#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4556#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004557#define _PIPEBFRAMEHIGH 0x71040
4558#define _PIPEBFRAMEPIXEL 0x71044
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004559#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4560#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004561
Jesse Barnes585fb112008-07-29 11:54:06 -07004562
4563/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004564#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07004565#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4566#define DISPPLANE_ALPHA_TRANS_DISABLE 0
4567#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4568#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004569#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4570#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4571#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4572#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4573#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4574#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4575#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4576#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07004577
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004578/* Sprite A control */
4579#define _DVSACNTR 0x72180
4580#define DVS_ENABLE (1<<31)
4581#define DVS_GAMMA_ENABLE (1<<30)
4582#define DVS_PIXFORMAT_MASK (3<<25)
4583#define DVS_FORMAT_YUV422 (0<<25)
4584#define DVS_FORMAT_RGBX101010 (1<<25)
4585#define DVS_FORMAT_RGBX888 (2<<25)
4586#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004587#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004588#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08004589#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004590#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4591#define DVS_YUV_ORDER_YUYV (0<<16)
4592#define DVS_YUV_ORDER_UYVY (1<<16)
4593#define DVS_YUV_ORDER_YVYU (2<<16)
4594#define DVS_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304595#define DVS_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004596#define DVS_DEST_KEY (1<<2)
4597#define DVS_TRICKLE_FEED_DISABLE (1<<14)
4598#define DVS_TILED (1<<10)
4599#define _DVSALINOFF 0x72184
4600#define _DVSASTRIDE 0x72188
4601#define _DVSAPOS 0x7218c
4602#define _DVSASIZE 0x72190
4603#define _DVSAKEYVAL 0x72194
4604#define _DVSAKEYMSK 0x72198
4605#define _DVSASURF 0x7219c
4606#define _DVSAKEYMAXVAL 0x721a0
4607#define _DVSATILEOFF 0x721a4
4608#define _DVSASURFLIVE 0x721ac
4609#define _DVSASCALE 0x72204
4610#define DVS_SCALE_ENABLE (1<<31)
4611#define DVS_FILTER_MASK (3<<29)
4612#define DVS_FILTER_MEDIUM (0<<29)
4613#define DVS_FILTER_ENHANCING (1<<29)
4614#define DVS_FILTER_SOFTENING (2<<29)
4615#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4616#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4617#define _DVSAGAMC 0x72300
4618
4619#define _DVSBCNTR 0x73180
4620#define _DVSBLINOFF 0x73184
4621#define _DVSBSTRIDE 0x73188
4622#define _DVSBPOS 0x7318c
4623#define _DVSBSIZE 0x73190
4624#define _DVSBKEYVAL 0x73194
4625#define _DVSBKEYMSK 0x73198
4626#define _DVSBSURF 0x7319c
4627#define _DVSBKEYMAXVAL 0x731a0
4628#define _DVSBTILEOFF 0x731a4
4629#define _DVSBSURFLIVE 0x731ac
4630#define _DVSBSCALE 0x73204
4631#define _DVSBGAMC 0x73300
4632
4633#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4634#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4635#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4636#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4637#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004638#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004639#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4640#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4641#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004642#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4643#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004644#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004645
4646#define _SPRA_CTL 0x70280
4647#define SPRITE_ENABLE (1<<31)
4648#define SPRITE_GAMMA_ENABLE (1<<30)
4649#define SPRITE_PIXFORMAT_MASK (7<<25)
4650#define SPRITE_FORMAT_YUV422 (0<<25)
4651#define SPRITE_FORMAT_RGBX101010 (1<<25)
4652#define SPRITE_FORMAT_RGBX888 (2<<25)
4653#define SPRITE_FORMAT_RGBX161616 (3<<25)
4654#define SPRITE_FORMAT_YUV444 (4<<25)
4655#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004656#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004657#define SPRITE_SOURCE_KEY (1<<22)
4658#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
4659#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
4660#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
4661#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
4662#define SPRITE_YUV_ORDER_YUYV (0<<16)
4663#define SPRITE_YUV_ORDER_UYVY (1<<16)
4664#define SPRITE_YUV_ORDER_YVYU (2<<16)
4665#define SPRITE_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304666#define SPRITE_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004667#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4668#define SPRITE_INT_GAMMA_ENABLE (1<<13)
4669#define SPRITE_TILED (1<<10)
4670#define SPRITE_DEST_KEY (1<<2)
4671#define _SPRA_LINOFF 0x70284
4672#define _SPRA_STRIDE 0x70288
4673#define _SPRA_POS 0x7028c
4674#define _SPRA_SIZE 0x70290
4675#define _SPRA_KEYVAL 0x70294
4676#define _SPRA_KEYMSK 0x70298
4677#define _SPRA_SURF 0x7029c
4678#define _SPRA_KEYMAX 0x702a0
4679#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004680#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004681#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004682#define _SPRA_SCALE 0x70304
4683#define SPRITE_SCALE_ENABLE (1<<31)
4684#define SPRITE_FILTER_MASK (3<<29)
4685#define SPRITE_FILTER_MEDIUM (0<<29)
4686#define SPRITE_FILTER_ENHANCING (1<<29)
4687#define SPRITE_FILTER_SOFTENING (2<<29)
4688#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4689#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
4690#define _SPRA_GAMC 0x70400
4691
4692#define _SPRB_CTL 0x71280
4693#define _SPRB_LINOFF 0x71284
4694#define _SPRB_STRIDE 0x71288
4695#define _SPRB_POS 0x7128c
4696#define _SPRB_SIZE 0x71290
4697#define _SPRB_KEYVAL 0x71294
4698#define _SPRB_KEYMSK 0x71298
4699#define _SPRB_SURF 0x7129c
4700#define _SPRB_KEYMAX 0x712a0
4701#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004702#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004703#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004704#define _SPRB_SCALE 0x71304
4705#define _SPRB_GAMC 0x71400
4706
4707#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4708#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4709#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4710#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4711#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4712#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4713#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4714#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4715#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4716#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
Damien Lespiauc54173a2012-10-26 18:20:11 +01004717#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004718#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4719#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004720#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004721
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004722#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004723#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08004724#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004725#define SP_PIXFORMAT_MASK (0xf<<26)
4726#define SP_FORMAT_YUV422 (0<<26)
4727#define SP_FORMAT_BGR565 (5<<26)
4728#define SP_FORMAT_BGRX8888 (6<<26)
4729#define SP_FORMAT_BGRA8888 (7<<26)
4730#define SP_FORMAT_RGBX1010102 (8<<26)
4731#define SP_FORMAT_RGBA1010102 (9<<26)
4732#define SP_FORMAT_RGBX8888 (0xe<<26)
4733#define SP_FORMAT_RGBA8888 (0xf<<26)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004734#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004735#define SP_SOURCE_KEY (1<<22)
4736#define SP_YUV_BYTE_ORDER_MASK (3<<16)
4737#define SP_YUV_ORDER_YUYV (0<<16)
4738#define SP_YUV_ORDER_UYVY (1<<16)
4739#define SP_YUV_ORDER_YVYU (2<<16)
4740#define SP_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304741#define SP_ROTATE_180 (1<<15)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004742#define SP_TILED (1<<10)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004743#define SP_MIRROR (1<<8) /* CHV pipe B */
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004744#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4745#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4746#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4747#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4748#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4749#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4750#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4751#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4752#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4753#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004754#define SP_CONST_ALPHA_ENABLE (1<<31)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004755#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004756
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004757#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4758#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4759#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4760#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4761#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4762#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4763#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4764#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4765#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4766#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4767#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4768#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004769
4770#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4771#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4772#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4773#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4774#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4775#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4776#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4777#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4778#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4779#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4780#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4781#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4782
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +03004783/*
4784 * CHV pipe B sprite CSC
4785 *
4786 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
4787 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
4788 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
4789 */
4790#define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
4791#define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
4792#define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
4793#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
4794#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
4795
4796#define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
4797#define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
4798#define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
4799#define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
4800#define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
4801#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
4802#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
4803
4804#define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
4805#define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
4806#define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
4807#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
4808#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
4809
4810#define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
4811#define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
4812#define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
4813#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
4814#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
4815
Damien Lespiau70d21f02013-07-03 21:06:04 +01004816/* Skylake plane registers */
4817
4818#define _PLANE_CTL_1_A 0x70180
4819#define _PLANE_CTL_2_A 0x70280
4820#define _PLANE_CTL_3_A 0x70380
4821#define PLANE_CTL_ENABLE (1 << 31)
4822#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
4823#define PLANE_CTL_FORMAT_MASK (0xf << 24)
4824#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
4825#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
4826#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
4827#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
4828#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
4829#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
4830#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
4831#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
4832#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00004833#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
4834#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
4835#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
Damien Lespiau70d21f02013-07-03 21:06:04 +01004836#define PLANE_CTL_ORDER_BGRX (0 << 20)
4837#define PLANE_CTL_ORDER_RGBX (1 << 20)
4838#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
4839#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
4840#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
4841#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
4842#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
4843#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
4844#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
4845#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
4846#define PLANE_CTL_TILED_MASK (0x7 << 10)
4847#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
4848#define PLANE_CTL_TILED_X ( 1 << 10)
4849#define PLANE_CTL_TILED_Y ( 4 << 10)
4850#define PLANE_CTL_TILED_YF ( 5 << 10)
4851#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
4852#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
4853#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
4854#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
Sonika Jindal1447dde2014-10-04 10:53:31 +01004855#define PLANE_CTL_ROTATE_MASK 0x3
4856#define PLANE_CTL_ROTATE_0 0x0
4857#define PLANE_CTL_ROTATE_180 0x2
Damien Lespiau70d21f02013-07-03 21:06:04 +01004858#define _PLANE_STRIDE_1_A 0x70188
4859#define _PLANE_STRIDE_2_A 0x70288
4860#define _PLANE_STRIDE_3_A 0x70388
4861#define _PLANE_POS_1_A 0x7018c
4862#define _PLANE_POS_2_A 0x7028c
4863#define _PLANE_POS_3_A 0x7038c
4864#define _PLANE_SIZE_1_A 0x70190
4865#define _PLANE_SIZE_2_A 0x70290
4866#define _PLANE_SIZE_3_A 0x70390
4867#define _PLANE_SURF_1_A 0x7019c
4868#define _PLANE_SURF_2_A 0x7029c
4869#define _PLANE_SURF_3_A 0x7039c
4870#define _PLANE_OFFSET_1_A 0x701a4
4871#define _PLANE_OFFSET_2_A 0x702a4
4872#define _PLANE_OFFSET_3_A 0x703a4
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00004873#define _PLANE_KEYVAL_1_A 0x70194
4874#define _PLANE_KEYVAL_2_A 0x70294
4875#define _PLANE_KEYMSK_1_A 0x70198
4876#define _PLANE_KEYMSK_2_A 0x70298
4877#define _PLANE_KEYMAX_1_A 0x701a0
4878#define _PLANE_KEYMAX_2_A 0x702a0
Damien Lespiau8211bd52014-11-04 17:06:44 +00004879#define _PLANE_BUF_CFG_1_A 0x7027c
4880#define _PLANE_BUF_CFG_2_A 0x7037c
Damien Lespiau70d21f02013-07-03 21:06:04 +01004881
4882#define _PLANE_CTL_1_B 0x71180
4883#define _PLANE_CTL_2_B 0x71280
4884#define _PLANE_CTL_3_B 0x71380
4885#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
4886#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
4887#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
4888#define PLANE_CTL(pipe, plane) \
4889 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
4890
4891#define _PLANE_STRIDE_1_B 0x71188
4892#define _PLANE_STRIDE_2_B 0x71288
4893#define _PLANE_STRIDE_3_B 0x71388
4894#define _PLANE_STRIDE_1(pipe) \
4895 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
4896#define _PLANE_STRIDE_2(pipe) \
4897 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
4898#define _PLANE_STRIDE_3(pipe) \
4899 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
4900#define PLANE_STRIDE(pipe, plane) \
4901 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
4902
4903#define _PLANE_POS_1_B 0x7118c
4904#define _PLANE_POS_2_B 0x7128c
4905#define _PLANE_POS_3_B 0x7138c
4906#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
4907#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
4908#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
4909#define PLANE_POS(pipe, plane) \
4910 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
4911
4912#define _PLANE_SIZE_1_B 0x71190
4913#define _PLANE_SIZE_2_B 0x71290
4914#define _PLANE_SIZE_3_B 0x71390
4915#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
4916#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
4917#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
4918#define PLANE_SIZE(pipe, plane) \
4919 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
4920
4921#define _PLANE_SURF_1_B 0x7119c
4922#define _PLANE_SURF_2_B 0x7129c
4923#define _PLANE_SURF_3_B 0x7139c
4924#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
4925#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
4926#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
4927#define PLANE_SURF(pipe, plane) \
4928 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
4929
4930#define _PLANE_OFFSET_1_B 0x711a4
4931#define _PLANE_OFFSET_2_B 0x712a4
4932#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
4933#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
4934#define PLANE_OFFSET(pipe, plane) \
4935 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
4936
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00004937#define _PLANE_KEYVAL_1_B 0x71194
4938#define _PLANE_KEYVAL_2_B 0x71294
4939#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
4940#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
4941#define PLANE_KEYVAL(pipe, plane) \
4942 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
4943
4944#define _PLANE_KEYMSK_1_B 0x71198
4945#define _PLANE_KEYMSK_2_B 0x71298
4946#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
4947#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
4948#define PLANE_KEYMSK(pipe, plane) \
4949 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
4950
4951#define _PLANE_KEYMAX_1_B 0x711a0
4952#define _PLANE_KEYMAX_2_B 0x712a0
4953#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
4954#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
4955#define PLANE_KEYMAX(pipe, plane) \
4956 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
4957
Damien Lespiau8211bd52014-11-04 17:06:44 +00004958#define _PLANE_BUF_CFG_1_B 0x7127c
4959#define _PLANE_BUF_CFG_2_B 0x7137c
4960#define _PLANE_BUF_CFG_1(pipe) \
4961 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
4962#define _PLANE_BUF_CFG_2(pipe) \
4963 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
4964#define PLANE_BUF_CFG(pipe, plane) \
4965 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
4966
4967/* SKL new cursor registers */
4968#define _CUR_BUF_CFG_A 0x7017c
4969#define _CUR_BUF_CFG_B 0x7117c
4970#define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
4971
Jesse Barnes585fb112008-07-29 11:54:06 -07004972/* VBIOS regs */
4973#define VGACNTRL 0x71400
4974# define VGA_DISP_DISABLE (1 << 31)
4975# define VGA_2X_MODE (1 << 30)
4976# define VGA_PIPE_B_SELECT (1 << 29)
4977
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004978#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4979
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004980/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004981
4982#define CPU_VGACNTRL 0x41000
4983
4984#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
4985#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
4986#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
4987#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
4988#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
4989#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
4990#define DIGITAL_PORTA_NO_DETECT (0 << 0)
4991#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
4992#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
4993
4994/* refresh rate hardware control */
4995#define RR_HW_CTL 0x45300
4996#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
4997#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
4998
4999#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01005000#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08005001#define FDI_PLL_BIOS_1 0x46004
5002#define FDI_PLL_BIOS_2 0x46008
5003#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
5004#define DISPLAY_PORT_PLL_BIOS_1 0x46010
5005#define DISPLAY_PORT_PLL_BIOS_2 0x46014
5006
Eric Anholt8956c8b2010-03-18 13:21:14 -07005007#define PCH_3DCGDIS0 0x46020
5008# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5009# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5010
Eric Anholt06f37752010-12-14 10:06:46 -08005011#define PCH_3DCGDIS1 0x46024
5012# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5013
Zhenyu Wangb9055052009-06-05 15:38:38 +08005014#define FDI_PLL_FREQ_CTL 0x46030
5015#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5016#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5017#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5018
5019
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005020#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01005021#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005022#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01005023#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005024
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005025#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01005026#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005027#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01005028#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005029
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005030#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01005031#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005032#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01005033#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005034
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005035#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01005036#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005037#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01005038#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005039
5040/* PIPEB timing regs are same start from 0x61000 */
5041
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005042#define _PIPEB_DATA_M1 0x61030
5043#define _PIPEB_DATA_N1 0x61034
5044#define _PIPEB_DATA_M2 0x61038
5045#define _PIPEB_DATA_N2 0x6103c
5046#define _PIPEB_LINK_M1 0x61040
5047#define _PIPEB_LINK_N1 0x61044
5048#define _PIPEB_LINK_M2 0x61048
5049#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005050
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005051#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
5052#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
5053#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
5054#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
5055#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
5056#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
5057#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
5058#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005059
5060/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005061/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5062#define _PFA_CTL_1 0x68080
5063#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08005064#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02005065#define PF_PIPE_SEL_MASK_IVB (3<<29)
5066#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08005067#define PF_FILTER_MASK (3<<23)
5068#define PF_FILTER_PROGRAMMED (0<<23)
5069#define PF_FILTER_MED_3x3 (1<<23)
5070#define PF_FILTER_EDGE_ENHANCE (2<<23)
5071#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005072#define _PFA_WIN_SZ 0x68074
5073#define _PFB_WIN_SZ 0x68874
5074#define _PFA_WIN_POS 0x68070
5075#define _PFB_WIN_POS 0x68870
5076#define _PFA_VSCALE 0x68084
5077#define _PFB_VSCALE 0x68884
5078#define _PFA_HSCALE 0x68090
5079#define _PFB_HSCALE 0x68890
5080
5081#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5082#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5083#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5084#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5085#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005086
Jesse Barnesbd2e2442014-11-13 17:51:47 +00005087#define _PSA_CTL 0x68180
5088#define _PSB_CTL 0x68980
5089#define PS_ENABLE (1<<31)
5090#define _PSA_WIN_SZ 0x68174
5091#define _PSB_WIN_SZ 0x68974
5092#define _PSA_WIN_POS 0x68170
5093#define _PSB_WIN_POS 0x68970
5094
5095#define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
5096#define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5097#define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5098
Zhenyu Wangb9055052009-06-05 15:38:38 +08005099/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005100#define _LGC_PALETTE_A 0x4a000
5101#define _LGC_PALETTE_B 0x4a800
5102#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005103
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005104#define _GAMMA_MODE_A 0x4a480
5105#define _GAMMA_MODE_B 0x4ac80
5106#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5107#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005108#define GAMMA_MODE_MODE_8BIT (0 << 0)
5109#define GAMMA_MODE_MODE_10BIT (1 << 0)
5110#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005111#define GAMMA_MODE_MODE_SPLIT (3 << 0)
5112
Zhenyu Wangb9055052009-06-05 15:38:38 +08005113/* interrupts */
5114#define DE_MASTER_IRQ_CONTROL (1 << 31)
5115#define DE_SPRITEB_FLIP_DONE (1 << 29)
5116#define DE_SPRITEA_FLIP_DONE (1 << 28)
5117#define DE_PLANEB_FLIP_DONE (1 << 27)
5118#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c2013-10-21 18:04:36 +02005119#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005120#define DE_PCU_EVENT (1 << 25)
5121#define DE_GTT_FAULT (1 << 24)
5122#define DE_POISON (1 << 23)
5123#define DE_PERFORM_COUNTER (1 << 22)
5124#define DE_PCH_EVENT (1 << 21)
5125#define DE_AUX_CHANNEL_A (1 << 20)
5126#define DE_DP_A_HOTPLUG (1 << 19)
5127#define DE_GSE (1 << 18)
5128#define DE_PIPEB_VBLANK (1 << 15)
5129#define DE_PIPEB_EVEN_FIELD (1 << 14)
5130#define DE_PIPEB_ODD_FIELD (1 << 13)
5131#define DE_PIPEB_LINE_COMPARE (1 << 12)
5132#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005133#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005134#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5135#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c2013-10-21 18:04:36 +02005136#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005137#define DE_PIPEA_EVEN_FIELD (1 << 6)
5138#define DE_PIPEA_ODD_FIELD (1 << 5)
5139#define DE_PIPEA_LINE_COMPARE (1 << 4)
5140#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02005141#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c2013-10-21 18:04:36 +02005142#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005143#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c2013-10-21 18:04:36 +02005144#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08005145
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005146/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03005147#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005148#define DE_GSE_IVB (1<<29)
5149#define DE_PCH_EVENT_IVB (1<<28)
5150#define DE_DP_A_HOTPLUG_IVB (1<<27)
5151#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01005152#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5153#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5154#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005155#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005156#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005157#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01005158#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5159#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c2013-10-21 18:04:36 +02005160#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07005161#define DE_PIPEA_VBLANK_IVB (1<<0)
Paulo Zanonib5184212013-07-12 20:00:08 -03005162#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
5163
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07005164#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5165#define MASTER_INTERRUPT_ENABLE (1<<31)
5166
Zhenyu Wangb9055052009-06-05 15:38:38 +08005167#define DEISR 0x44000
5168#define DEIMR 0x44004
5169#define DEIIR 0x44008
5170#define DEIER 0x4400c
5171
Zhenyu Wangb9055052009-06-05 15:38:38 +08005172#define GTISR 0x44010
5173#define GTIMR 0x44014
5174#define GTIIR 0x44018
5175#define GTIER 0x4401c
5176
Ben Widawskyabd58f02013-11-02 21:07:09 -07005177#define GEN8_MASTER_IRQ 0x44200
5178#define GEN8_MASTER_IRQ_CONTROL (1<<31)
5179#define GEN8_PCU_IRQ (1<<30)
5180#define GEN8_DE_PCH_IRQ (1<<23)
5181#define GEN8_DE_MISC_IRQ (1<<22)
5182#define GEN8_DE_PORT_IRQ (1<<20)
5183#define GEN8_DE_PIPE_C_IRQ (1<<18)
5184#define GEN8_DE_PIPE_B_IRQ (1<<17)
5185#define GEN8_DE_PIPE_A_IRQ (1<<16)
Daniel Vetterc42664c2013-11-07 11:05:40 +01005186#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
Ben Widawskyabd58f02013-11-02 21:07:09 -07005187#define GEN8_GT_VECS_IRQ (1<<6)
Ben Widawsky09610212014-05-15 20:58:08 +03005188#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005189#define GEN8_GT_VCS2_IRQ (1<<3)
5190#define GEN8_GT_VCS1_IRQ (1<<2)
5191#define GEN8_GT_BCS_IRQ (1<<1)
5192#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005193
5194#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5195#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5196#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5197#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5198
5199#define GEN8_BCS_IRQ_SHIFT 16
5200#define GEN8_RCS_IRQ_SHIFT 0
5201#define GEN8_VCS2_IRQ_SHIFT 16
5202#define GEN8_VCS1_IRQ_SHIFT 0
5203#define GEN8_VECS_IRQ_SHIFT 0
5204
5205#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5206#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5207#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5208#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01005209#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005210#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5211#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5212#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5213#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5214#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5215#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01005216#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005217#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5218#define GEN8_PIPE_VSYNC (1 << 1)
5219#define GEN8_PIPE_VBLANK (1 << 0)
Damien Lespiau770de832014-03-20 20:45:01 +00005220#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5221#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5222#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5223#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5224#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5225#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5226#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5227#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
Daniel Vetter30100f22013-11-07 14:49:24 +01005228#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5229 (GEN8_PIPE_CURSOR_FAULT | \
5230 GEN8_PIPE_SPRITE_FAULT | \
5231 GEN8_PIPE_PRIMARY_FAULT)
Damien Lespiau770de832014-03-20 20:45:01 +00005232#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5233 (GEN9_PIPE_CURSOR_FAULT | \
5234 GEN9_PIPE_PLANE3_FAULT | \
5235 GEN9_PIPE_PLANE2_FAULT | \
5236 GEN9_PIPE_PLANE1_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005237
5238#define GEN8_DE_PORT_ISR 0x44440
5239#define GEN8_DE_PORT_IMR 0x44444
5240#define GEN8_DE_PORT_IIR 0x44448
5241#define GEN8_DE_PORT_IER 0x4444c
Daniel Vetter6d766f02013-11-07 14:49:55 +01005242#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
Jesse Barnes88e04702014-11-13 17:51:48 +00005243#define GEN9_AUX_CHANNEL_D (1 << 27)
5244#define GEN9_AUX_CHANNEL_C (1 << 26)
5245#define GEN9_AUX_CHANNEL_B (1 << 25)
Daniel Vetter6d766f02013-11-07 14:49:55 +01005246#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07005247
5248#define GEN8_DE_MISC_ISR 0x44460
5249#define GEN8_DE_MISC_IMR 0x44464
5250#define GEN8_DE_MISC_IIR 0x44468
5251#define GEN8_DE_MISC_IER 0x4446c
5252#define GEN8_DE_MISC_GSE (1 << 27)
5253
5254#define GEN8_PCU_ISR 0x444e0
5255#define GEN8_PCU_IMR 0x444e4
5256#define GEN8_PCU_IIR 0x444e8
5257#define GEN8_PCU_IER 0x444ec
5258
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005259#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07005260/* Required on all Ironlake and Sandybridge according to the B-Spec. */
5261#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005262#define ILK_DPARB_GATE (1<<22)
5263#define ILK_VSDPFD_FULL (1<<21)
Damien Lespiaue3589902014-02-07 19:12:50 +00005264#define FUSE_STRAP 0x42014
5265#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5266#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5267#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5268#define ILK_HDCP_DISABLE (1 << 25)
5269#define ILK_eDP_A_DISABLE (1 << 24)
5270#define HSW_CDCLK_LIMIT (1 << 24)
5271#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08005272
Damien Lespiau231e54f2012-10-19 17:55:41 +01005273#define ILK_DSPCLK_GATE_D 0x42020
5274#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5275#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5276#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5277#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5278#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005279
Eric Anholt116ac8d2011-12-21 10:31:09 -08005280#define IVB_CHICKEN3 0x4200c
5281# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5282# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5283
Paulo Zanoni90a88642013-05-03 17:23:45 -03005284#define CHICKEN_PAR1_1 0x42080
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005285#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03005286#define FORCE_ARB_IDLE_PLANES (1 << 14)
5287
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005288#define _CHICKEN_PIPESL_1_A 0x420b0
5289#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02005290#define HSW_FBCQ_DIS (1 << 22)
5291#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07005292#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5293
Zhenyu Wang553bd142009-09-02 10:57:52 +08005294#define DISP_ARB_CTL 0x45000
5295#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005296#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02005297#define DISP_ARB_CTL2 0x45004
5298#define DISP_DATA_PARTITION_5_6 (1<<6)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07005299#define GEN7_MSG_CTL 0x45010
5300#define WAIT_FOR_PCH_RESET_ACK (1<<1)
5301#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01005302#define HSW_NDE_RSTWRN_OPT 0x46408
5303#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08005304
Damien Lespiau2caa3b22015-02-09 19:33:20 +00005305#define FF_SLICE_CS_CHICKEN2 0x02e4
5306#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
5307
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005308/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08005309#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5310# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Damien Lespiau183c6da2015-02-09 19:33:11 +00005311# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
Ben Widawskya75f3622013-11-02 21:07:59 -07005312#define COMMON_SLICE_CHICKEN2 0x7014
5313# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08005314
Damien Lespiaud0bbbc42015-02-09 19:33:16 +00005315#define HIZ_CHICKEN 0x7018
5316# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
5317# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
Kenneth Graunked60de812015-01-10 18:02:22 -08005318
Damien Lespiau183c6da2015-02-09 19:33:11 +00005319#define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308
5320#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
5321
Ville Syrjälä031994e2014-01-22 21:32:46 +02005322#define GEN7_L3SQCREG1 0xB010
5323#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5324
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005325#define GEN7_L3CNTLREG1 0xB01C
Chris Wilson1af84522014-02-14 22:34:43 +00005326#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07005327#define GEN7_L3AGDIS (1<<19)
Brad Volkinc9224fa2014-06-17 14:10:34 -07005328#define GEN7_L3CNTLREG2 0xB020
5329#define GEN7_L3CNTLREG3 0xB024
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08005330
5331#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5332#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5333
Jesse Barnes61939d92012-10-02 17:43:38 -05005334#define GEN7_L3SQCREG4 0xb034
5335#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5336
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00005337#define GEN8_L3SQCREG4 0xb118
5338#define GEN8_LQSC_RO_PERF_DIS (1<<27)
5339
Ben Widawsky63801f22013-12-12 17:26:03 -08005340/* GEN8 chicken */
5341#define HDC_CHICKEN0 0x7300
Rodrigo Vivida096542014-09-19 20:16:27 -04005342#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
Damien Lespiau35cb6f32015-02-10 10:31:00 +00005343#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5344#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
5345#define HDC_FORCE_NON_COHERENT (1<<4)
Damien Lespiau65ca7512015-02-09 19:33:22 +00005346#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
Ben Widawsky63801f22013-12-12 17:26:03 -08005347
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08005348/* WaCatErrorRejectionIssue */
5349#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5350#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5351
Francisco Jerezf3fc4882013-10-02 15:53:16 -07005352#define HSW_SCRATCH1 0xb038
5353#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5354
Damien Lespiau77719d22015-02-09 19:33:13 +00005355#define BDW_SCRATCH1 0xb11c
5356#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
5357
Zhenyu Wangb9055052009-06-05 15:38:38 +08005358/* PCH */
5359
Adam Jackson23e81d62012-06-06 15:45:44 -04005360/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08005361#define SDE_AUDIO_POWER_D (1 << 27)
5362#define SDE_AUDIO_POWER_C (1 << 26)
5363#define SDE_AUDIO_POWER_B (1 << 25)
5364#define SDE_AUDIO_POWER_SHIFT (25)
5365#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5366#define SDE_GMBUS (1 << 24)
5367#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5368#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5369#define SDE_AUDIO_HDCP_MASK (3 << 22)
5370#define SDE_AUDIO_TRANSB (1 << 21)
5371#define SDE_AUDIO_TRANSA (1 << 20)
5372#define SDE_AUDIO_TRANS_MASK (3 << 20)
5373#define SDE_POISON (1 << 19)
5374/* 18 reserved */
5375#define SDE_FDI_RXB (1 << 17)
5376#define SDE_FDI_RXA (1 << 16)
5377#define SDE_FDI_MASK (3 << 16)
5378#define SDE_AUXD (1 << 15)
5379#define SDE_AUXC (1 << 14)
5380#define SDE_AUXB (1 << 13)
5381#define SDE_AUX_MASK (7 << 13)
5382/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005383#define SDE_CRT_HOTPLUG (1 << 11)
5384#define SDE_PORTD_HOTPLUG (1 << 10)
5385#define SDE_PORTC_HOTPLUG (1 << 9)
5386#define SDE_PORTB_HOTPLUG (1 << 8)
5387#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05005388#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5389 SDE_SDVOB_HOTPLUG | \
5390 SDE_PORTB_HOTPLUG | \
5391 SDE_PORTC_HOTPLUG | \
5392 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08005393#define SDE_TRANSB_CRC_DONE (1 << 5)
5394#define SDE_TRANSB_CRC_ERR (1 << 4)
5395#define SDE_TRANSB_FIFO_UNDER (1 << 3)
5396#define SDE_TRANSA_CRC_DONE (1 << 2)
5397#define SDE_TRANSA_CRC_ERR (1 << 1)
5398#define SDE_TRANSA_FIFO_UNDER (1 << 0)
5399#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04005400
5401/* south display engine interrupt: CPT/PPT */
5402#define SDE_AUDIO_POWER_D_CPT (1 << 31)
5403#define SDE_AUDIO_POWER_C_CPT (1 << 30)
5404#define SDE_AUDIO_POWER_B_CPT (1 << 29)
5405#define SDE_AUDIO_POWER_SHIFT_CPT 29
5406#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5407#define SDE_AUXD_CPT (1 << 27)
5408#define SDE_AUXC_CPT (1 << 26)
5409#define SDE_AUXB_CPT (1 << 25)
5410#define SDE_AUX_MASK_CPT (7 << 25)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005411#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5412#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5413#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04005414#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01005415#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01005416#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01005417 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01005418 SDE_PORTD_HOTPLUG_CPT | \
5419 SDE_PORTC_HOTPLUG_CPT | \
5420 SDE_PORTB_HOTPLUG_CPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04005421#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03005422#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04005423#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5424#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5425#define SDE_FDI_RXC_CPT (1 << 8)
5426#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5427#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5428#define SDE_FDI_RXB_CPT (1 << 4)
5429#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5430#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5431#define SDE_FDI_RXA_CPT (1 << 0)
5432#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5433 SDE_AUDIO_CP_REQ_B_CPT | \
5434 SDE_AUDIO_CP_REQ_A_CPT)
5435#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5436 SDE_AUDIO_CP_CHG_B_CPT | \
5437 SDE_AUDIO_CP_CHG_A_CPT)
5438#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5439 SDE_FDI_RXB_CPT | \
5440 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005441
5442#define SDEISR 0xc4000
5443#define SDEIMR 0xc4004
5444#define SDEIIR 0xc4008
5445#define SDEIER 0xc400c
5446
Paulo Zanoni86642812013-04-12 17:57:57 -03005447#define SERR_INT 0xc4040
Paulo Zanonide032bf2013-04-12 17:57:58 -03005448#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03005449#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
5450#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
5451#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Daniel Vetter1dd246f2013-07-10 08:30:23 +02005452#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03005453
Zhenyu Wangb9055052009-06-05 15:38:38 +08005454/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07005455#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005456#define PORTD_HOTPLUG_ENABLE (1 << 20)
5457#define PORTD_PULSE_DURATION_2ms (0)
5458#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
5459#define PORTD_PULSE_DURATION_6ms (2 << 18)
5460#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07005461#define PORTD_PULSE_DURATION_MASK (3 << 18)
Damien Lespiaub6965192012-12-13 16:08:59 +00005462#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
5463#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5464#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5465#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005466#define PORTC_HOTPLUG_ENABLE (1 << 12)
5467#define PORTC_PULSE_DURATION_2ms (0)
5468#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
5469#define PORTC_PULSE_DURATION_6ms (2 << 10)
5470#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07005471#define PORTC_PULSE_DURATION_MASK (3 << 10)
Damien Lespiaub6965192012-12-13 16:08:59 +00005472#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
5473#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
5474#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
5475#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005476#define PORTB_HOTPLUG_ENABLE (1 << 4)
5477#define PORTB_PULSE_DURATION_2ms (0)
5478#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
5479#define PORTB_PULSE_DURATION_6ms (2 << 2)
5480#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07005481#define PORTB_PULSE_DURATION_MASK (3 << 2)
Damien Lespiaub6965192012-12-13 16:08:59 +00005482#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
5483#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
5484#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
5485#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005486
5487#define PCH_GPIOA 0xc5010
5488#define PCH_GPIOB 0xc5014
5489#define PCH_GPIOC 0xc5018
5490#define PCH_GPIOD 0xc501c
5491#define PCH_GPIOE 0xc5020
5492#define PCH_GPIOF 0xc5024
5493
Eric Anholtf0217c42009-12-01 11:56:30 -08005494#define PCH_GMBUS0 0xc5100
5495#define PCH_GMBUS1 0xc5104
5496#define PCH_GMBUS2 0xc5108
5497#define PCH_GMBUS3 0xc510c
5498#define PCH_GMBUS4 0xc5110
5499#define PCH_GMBUS5 0xc5120
5500
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005501#define _PCH_DPLL_A 0xc6014
5502#define _PCH_DPLL_B 0xc6018
Daniel Vettere9a632a2013-06-05 13:34:13 +02005503#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005504
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005505#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00005506#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005507#define _PCH_FPA1 0xc6044
5508#define _PCH_FPB0 0xc6048
5509#define _PCH_FPB1 0xc604c
Daniel Vettere9a632a2013-06-05 13:34:13 +02005510#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
5511#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005512
5513#define PCH_DPLL_TEST 0xc606c
5514
5515#define PCH_DREF_CONTROL 0xC6200
5516#define DREF_CONTROL_MASK 0x7fc3
5517#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
5518#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
5519#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
5520#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
5521#define DREF_SSC_SOURCE_DISABLE (0<<11)
5522#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08005523#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005524#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
5525#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
5526#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08005527#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005528#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
5529#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08005530#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005531#define DREF_SSC4_DOWNSPREAD (0<<6)
5532#define DREF_SSC4_CENTERSPREAD (1<<6)
5533#define DREF_SSC1_DISABLE (0<<1)
5534#define DREF_SSC1_ENABLE (1<<1)
5535#define DREF_SSC4_DISABLE (0)
5536#define DREF_SSC4_ENABLE (1)
5537
5538#define PCH_RAWCLK_FREQ 0xc6204
5539#define FDL_TP1_TIMER_SHIFT 12
5540#define FDL_TP1_TIMER_MASK (3<<12)
5541#define FDL_TP2_TIMER_SHIFT 10
5542#define FDL_TP2_TIMER_MASK (3<<10)
5543#define RAWCLK_FREQ_MASK 0x3ff
5544
5545#define PCH_DPLL_TMR_CFG 0xc6208
5546
5547#define PCH_SSC4_PARMS 0xc6210
5548#define PCH_SSC4_AUX_PARMS 0xc6214
5549
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005550#define PCH_DPLL_SEL 0xc7000
Daniel Vetter11887392013-06-05 13:34:09 +02005551#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
5552#define TRANS_DPLLA_SEL(pipe) 0
5553#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005554
Zhenyu Wangb9055052009-06-05 15:38:38 +08005555/* transcoder */
5556
Daniel Vetter275f01b22013-05-03 11:49:47 +02005557#define _PCH_TRANS_HTOTAL_A 0xe0000
5558#define TRANS_HTOTAL_SHIFT 16
5559#define TRANS_HACTIVE_SHIFT 0
5560#define _PCH_TRANS_HBLANK_A 0xe0004
5561#define TRANS_HBLANK_END_SHIFT 16
5562#define TRANS_HBLANK_START_SHIFT 0
5563#define _PCH_TRANS_HSYNC_A 0xe0008
5564#define TRANS_HSYNC_END_SHIFT 16
5565#define TRANS_HSYNC_START_SHIFT 0
5566#define _PCH_TRANS_VTOTAL_A 0xe000c
5567#define TRANS_VTOTAL_SHIFT 16
5568#define TRANS_VACTIVE_SHIFT 0
5569#define _PCH_TRANS_VBLANK_A 0xe0010
5570#define TRANS_VBLANK_END_SHIFT 16
5571#define TRANS_VBLANK_START_SHIFT 0
5572#define _PCH_TRANS_VSYNC_A 0xe0014
5573#define TRANS_VSYNC_END_SHIFT 16
5574#define TRANS_VSYNC_START_SHIFT 0
5575#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08005576
Daniel Vettere3b95f12013-05-03 11:49:49 +02005577#define _PCH_TRANSA_DATA_M1 0xe0030
5578#define _PCH_TRANSA_DATA_N1 0xe0034
5579#define _PCH_TRANSA_DATA_M2 0xe0038
5580#define _PCH_TRANSA_DATA_N2 0xe003c
5581#define _PCH_TRANSA_LINK_M1 0xe0040
5582#define _PCH_TRANSA_LINK_N1 0xe0044
5583#define _PCH_TRANSA_LINK_M2 0xe0048
5584#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005585
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005586/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07005587#define _VIDEO_DIP_CTL_A 0xe0200
5588#define _VIDEO_DIP_DATA_A 0xe0208
5589#define _VIDEO_DIP_GCP_A 0xe0210
5590
5591#define _VIDEO_DIP_CTL_B 0xe1200
5592#define _VIDEO_DIP_DATA_B 0xe1208
5593#define _VIDEO_DIP_GCP_B 0xe1210
5594
5595#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5596#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5597#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5598
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005599/* Per-transcoder DIP controls (VLV) */
Ville Syrjäläb9064872013-01-24 15:29:31 +02005600#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5601#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5602#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005603
Ville Syrjäläb9064872013-01-24 15:29:31 +02005604#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5605#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5606#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005607
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005608#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5609#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5610#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5611
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005612#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005613 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
5614 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005615#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005616 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
5617 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005618#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005619 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5620 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005621
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03005622/* Haswell DIP controls */
5623#define HSW_VIDEO_DIP_CTL_A 0x60200
5624#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5625#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
5626#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5627#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5628#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5629#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5630#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
5631#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5632#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5633#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5634#define HSW_VIDEO_DIP_GCP_A 0x60210
5635
5636#define HSW_VIDEO_DIP_CTL_B 0x61200
5637#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5638#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
5639#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5640#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5641#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5642#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5643#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
5644#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5645#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5646#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5647#define HSW_VIDEO_DIP_GCP_B 0x61210
5648
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005649#define HSW_TVIDEO_DIP_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005650 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005651#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005652 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +01005653#define HSW_TVIDEO_DIP_VS_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005654 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005655#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005656 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005657#define HSW_TVIDEO_DIP_GCP(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005658 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005659#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005660 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03005661
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03005662#define HSW_STEREO_3D_CTL_A 0x70020
5663#define S3D_ENABLE (1<<31)
5664#define HSW_STEREO_3D_CTL_B 0x71020
5665
5666#define HSW_STEREO_3D_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005667 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03005668
Daniel Vetter275f01b22013-05-03 11:49:47 +02005669#define _PCH_TRANS_HTOTAL_B 0xe1000
5670#define _PCH_TRANS_HBLANK_B 0xe1004
5671#define _PCH_TRANS_HSYNC_B 0xe1008
5672#define _PCH_TRANS_VTOTAL_B 0xe100c
5673#define _PCH_TRANS_VBLANK_B 0xe1010
5674#define _PCH_TRANS_VSYNC_B 0xe1014
5675#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08005676
Daniel Vetter275f01b22013-05-03 11:49:47 +02005677#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5678#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5679#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5680#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5681#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5682#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5683#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5684 _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01005685
Daniel Vettere3b95f12013-05-03 11:49:49 +02005686#define _PCH_TRANSB_DATA_M1 0xe1030
5687#define _PCH_TRANSB_DATA_N1 0xe1034
5688#define _PCH_TRANSB_DATA_M2 0xe1038
5689#define _PCH_TRANSB_DATA_N2 0xe103c
5690#define _PCH_TRANSB_LINK_M1 0xe1040
5691#define _PCH_TRANSB_LINK_N1 0xe1044
5692#define _PCH_TRANSB_LINK_M2 0xe1048
5693#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005694
Daniel Vettere3b95f12013-05-03 11:49:49 +02005695#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5696#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5697#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5698#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5699#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5700#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5701#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5702#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005703
Daniel Vetterab9412b2013-05-03 11:49:46 +02005704#define _PCH_TRANSACONF 0xf0008
5705#define _PCH_TRANSBCONF 0xf1008
5706#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5707#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005708#define TRANS_DISABLE (0<<31)
5709#define TRANS_ENABLE (1<<31)
5710#define TRANS_STATE_MASK (1<<30)
5711#define TRANS_STATE_DISABLE (0<<30)
5712#define TRANS_STATE_ENABLE (1<<30)
5713#define TRANS_FSYNC_DELAY_HB1 (0<<27)
5714#define TRANS_FSYNC_DELAY_HB2 (1<<27)
5715#define TRANS_FSYNC_DELAY_HB3 (2<<27)
5716#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005717#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005718#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005719#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02005720#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005721#define TRANS_8BPC (0<<5)
5722#define TRANS_10BPC (1<<5)
5723#define TRANS_6BPC (2<<5)
5724#define TRANS_12BPC (3<<5)
5725
Daniel Vetterce401412012-10-31 22:52:30 +01005726#define _TRANSA_CHICKEN1 0xf0060
5727#define _TRANSB_CHICKEN1 0xf1060
5728#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5729#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005730#define _TRANSA_CHICKEN2 0xf0064
5731#define _TRANSB_CHICKEN2 0xf1064
5732#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03005733#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
5734#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
5735#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
5736#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
5737#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005738
Jesse Barnes291427f2011-07-29 12:42:37 -07005739#define SOUTH_CHICKEN1 0xc2000
5740#define FDIA_PHASE_SYNC_SHIFT_OVR 19
5741#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02005742#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5743#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5744#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005745#define SOUTH_CHICKEN2 0xc2004
Paulo Zanonidde86e22012-12-01 12:04:25 -02005746#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
5747#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
5748#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005749
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005750#define _FDI_RXA_CHICKEN 0xc200c
5751#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08005752#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
5753#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005754#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005755
Jesse Barnes382b0932010-10-07 16:01:25 -07005756#define SOUTH_DSPCLK_GATE_D 0xc2020
Jesse Barnescd664072013-10-02 10:34:19 -07005757#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07005758#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07005759#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02005760#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07005761
Zhenyu Wangb9055052009-06-05 15:38:38 +08005762/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005763#define _FDI_TXA_CTL 0x60100
5764#define _FDI_TXB_CTL 0x61100
5765#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005766#define FDI_TX_DISABLE (0<<31)
5767#define FDI_TX_ENABLE (1<<31)
5768#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
5769#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
5770#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
5771#define FDI_LINK_TRAIN_NONE (3<<28)
5772#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
5773#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
5774#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
5775#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
5776#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
5777#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
5778#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
5779#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005780/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
5781 SNB has different settings. */
5782/* SNB A-stepping */
5783#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5784#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5785#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5786#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5787/* SNB B-stepping */
5788#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
5789#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
5790#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
5791#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
5792#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005793#define FDI_DP_PORT_WIDTH_SHIFT 19
5794#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
5795#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005796#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005797/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005798#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07005799
5800/* Ivybridge has different bits for lolz */
5801#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
5802#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
5803#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
5804#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
5805
Zhenyu Wangb9055052009-06-05 15:38:38 +08005806/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07005807#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07005808#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005809#define FDI_SCRAMBLING_ENABLE (0<<7)
5810#define FDI_SCRAMBLING_DISABLE (1<<7)
5811
5812/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005813#define _FDI_RXA_CTL 0xf000c
5814#define _FDI_RXB_CTL 0xf100c
5815#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005816#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005817/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07005818#define FDI_FS_ERRC_ENABLE (1<<27)
5819#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02005820#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005821#define FDI_8BPC (0<<16)
5822#define FDI_10BPC (1<<16)
5823#define FDI_6BPC (2<<16)
5824#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00005825#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005826#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
5827#define FDI_RX_PLL_ENABLE (1<<13)
5828#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
5829#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
5830#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
5831#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
5832#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01005833#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005834/* CPT */
5835#define FDI_AUTO_TRAINING (1<<10)
5836#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
5837#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
5838#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
5839#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
5840#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005841
Paulo Zanoni04945642012-11-01 21:00:59 -02005842#define _FDI_RXA_MISC 0xf0010
5843#define _FDI_RXB_MISC 0xf1010
5844#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
5845#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
5846#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
5847#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
5848#define FDI_RX_TP1_TO_TP2_48 (2<<20)
5849#define FDI_RX_TP1_TO_TP2_64 (3<<20)
5850#define FDI_RX_FDI_DELAY_90 (0x90<<0)
5851#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5852
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005853#define _FDI_RXA_TUSIZE1 0xf0030
5854#define _FDI_RXA_TUSIZE2 0xf0038
5855#define _FDI_RXB_TUSIZE1 0xf1030
5856#define _FDI_RXB_TUSIZE2 0xf1038
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005857#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5858#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005859
5860/* FDI_RX interrupt register format */
5861#define FDI_RX_INTER_LANE_ALIGN (1<<10)
5862#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
5863#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
5864#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
5865#define FDI_RX_FS_CODE_ERR (1<<6)
5866#define FDI_RX_FE_CODE_ERR (1<<5)
5867#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
5868#define FDI_RX_HDCP_LINK_FAIL (1<<3)
5869#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
5870#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
5871#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
5872
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005873#define _FDI_RXA_IIR 0xf0014
5874#define _FDI_RXA_IMR 0xf0018
5875#define _FDI_RXB_IIR 0xf1014
5876#define _FDI_RXB_IMR 0xf1018
5877#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5878#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005879
5880#define FDI_PLL_CTL_1 0xfe000
5881#define FDI_PLL_CTL_2 0xfe004
5882
Zhenyu Wangb9055052009-06-05 15:38:38 +08005883#define PCH_LVDS 0xe1180
5884#define LVDS_DETECTED (1 << 1)
5885
Shobhit Kumar98364372012-06-15 11:55:14 -07005886/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005887#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5888#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5889#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Ville Syrjäläad933b52014-08-18 22:15:56 +03005890#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005891#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5892#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07005893
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005894#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
5895#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
5896#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
5897#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
5898#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07005899
Jesse Barnes453c5422013-03-28 09:55:41 -07005900#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5901#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5902#define VLV_PIPE_PP_ON_DELAYS(pipe) \
5903 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5904#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5905 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5906#define VLV_PIPE_PP_DIVISOR(pipe) \
5907 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5908
Zhenyu Wangb9055052009-06-05 15:38:38 +08005909#define PCH_PP_STATUS 0xc7200
5910#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07005911#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07005912#define PANEL_UNLOCK_MASK (0xffff << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005913#define EDP_FORCE_VDD (1 << 3)
5914#define EDP_BLC_ENABLE (1 << 2)
5915#define PANEL_POWER_RESET (1 << 1)
5916#define PANEL_POWER_OFF (0 << 0)
5917#define PANEL_POWER_ON (1 << 0)
5918#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07005919#define PANEL_PORT_SELECT_MASK (3 << 30)
5920#define PANEL_PORT_SELECT_LVDS (0 << 30)
5921#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07005922#define PANEL_PORT_SELECT_DPC (2 << 30)
5923#define PANEL_PORT_SELECT_DPD (3 << 30)
5924#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
5925#define PANEL_POWER_UP_DELAY_SHIFT 16
5926#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
5927#define PANEL_LIGHT_ON_DELAY_SHIFT 0
5928
Zhenyu Wangb9055052009-06-05 15:38:38 +08005929#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07005930#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
5931#define PANEL_POWER_DOWN_DELAY_SHIFT 16
5932#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
5933#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
5934
Zhenyu Wangb9055052009-06-05 15:38:38 +08005935#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07005936#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
5937#define PP_REFERENCE_DIVIDER_SHIFT 8
5938#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
5939#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005940
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005941#define PCH_DP_B 0xe4100
5942#define PCH_DPB_AUX_CH_CTL 0xe4110
5943#define PCH_DPB_AUX_CH_DATA1 0xe4114
5944#define PCH_DPB_AUX_CH_DATA2 0xe4118
5945#define PCH_DPB_AUX_CH_DATA3 0xe411c
5946#define PCH_DPB_AUX_CH_DATA4 0xe4120
5947#define PCH_DPB_AUX_CH_DATA5 0xe4124
5948
5949#define PCH_DP_C 0xe4200
5950#define PCH_DPC_AUX_CH_CTL 0xe4210
5951#define PCH_DPC_AUX_CH_DATA1 0xe4214
5952#define PCH_DPC_AUX_CH_DATA2 0xe4218
5953#define PCH_DPC_AUX_CH_DATA3 0xe421c
5954#define PCH_DPC_AUX_CH_DATA4 0xe4220
5955#define PCH_DPC_AUX_CH_DATA5 0xe4224
5956
5957#define PCH_DP_D 0xe4300
5958#define PCH_DPD_AUX_CH_CTL 0xe4310
5959#define PCH_DPD_AUX_CH_DATA1 0xe4314
5960#define PCH_DPD_AUX_CH_DATA2 0xe4318
5961#define PCH_DPD_AUX_CH_DATA3 0xe431c
5962#define PCH_DPD_AUX_CH_DATA4 0xe4320
5963#define PCH_DPD_AUX_CH_DATA5 0xe4324
5964
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005965/* CPT */
5966#define PORT_TRANS_A_SEL_CPT 0
5967#define PORT_TRANS_B_SEL_CPT (1<<29)
5968#define PORT_TRANS_C_SEL_CPT (2<<29)
5969#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07005970#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02005971#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
5972#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03005973#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
5974#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005975
5976#define TRANS_DP_CTL_A 0xe0300
5977#define TRANS_DP_CTL_B 0xe1300
5978#define TRANS_DP_CTL_C 0xe2300
Daniel Vetter23670b322012-11-01 09:15:30 +01005979#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005980#define TRANS_DP_OUTPUT_ENABLE (1<<31)
5981#define TRANS_DP_PORT_SEL_B (0<<29)
5982#define TRANS_DP_PORT_SEL_C (1<<29)
5983#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08005984#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005985#define TRANS_DP_PORT_SEL_MASK (3<<29)
5986#define TRANS_DP_AUDIO_ONLY (1<<26)
5987#define TRANS_DP_ENH_FRAMING (1<<18)
5988#define TRANS_DP_8BPC (0<<9)
5989#define TRANS_DP_10BPC (1<<9)
5990#define TRANS_DP_6BPC (2<<9)
5991#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08005992#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005993#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
5994#define TRANS_DP_VSYNC_ACTIVE_LOW 0
5995#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
5996#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01005997#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005998
5999/* SNB eDP training params */
6000/* SNB A-stepping */
6001#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6002#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6003#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6004#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6005/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08006006#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6007#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6008#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6009#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6010#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08006011#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6012
Keith Packard1a2eb462011-11-16 16:26:07 -08006013/* IVB */
6014#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6015#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6016#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6017#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6018#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6019#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03006020#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08006021
6022/* legacy values */
6023#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6024#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6025#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6026#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6027#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6028
6029#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6030
Imre Deak9e72b462014-05-05 15:13:55 +03006031#define VLV_PMWGICZ 0x1300a4
6032
Zou Nan haicae58522010-11-09 17:17:32 +08006033#define FORCEWAKE 0xA18C
Jesse Barnes575155a2012-03-28 13:39:37 -07006034#define FORCEWAKE_VLV 0x1300b0
6035#define FORCEWAKE_ACK_VLV 0x1300b4
Jesse Barnesed5de392013-03-08 10:45:57 -08006036#define FORCEWAKE_MEDIA_VLV 0x1300b8
6037#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
Eugeni Dodonove7911c42012-07-02 11:51:04 -03006038#define FORCEWAKE_ACK_HSW 0x130044
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00006039#define FORCEWAKE_ACK 0x130090
Jesse Barnesd62b4892013-03-08 10:45:53 -08006040#define VLV_GTLC_WAKE_CTRL 0x130090
Imre Deak981a5ae2014-04-14 20:24:22 +03006041#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6042#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6043#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6044
Jesse Barnesd62b4892013-03-08 10:45:53 -08006045#define VLV_GTLC_PW_STATUS 0x130094
Imre Deak981a5ae2014-04-14 20:24:22 +03006046#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6047#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6048#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6049#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Keith Packard8d715f02011-11-18 20:39:01 -08006050#define FORCEWAKE_MT 0xa188 /* multi-threaded */
Zhe Wang38cff0b2014-11-04 17:07:04 +00006051#define FORCEWAKE_MEDIA_GEN9 0xa270
6052#define FORCEWAKE_RENDER_GEN9 0xa278
6053#define FORCEWAKE_BLITTER_GEN9 0xa188
6054#define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
6055#define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
6056#define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
Chris Wilsonc5836c22012-10-17 12:09:55 +01006057#define FORCEWAKE_KERNEL 0x1
6058#define FORCEWAKE_USER 0x2
Keith Packard8d715f02011-11-18 20:39:01 -08006059#define FORCEWAKE_MT_ACK 0x130040
6060#define ECOBUS 0xa180
6061#define FORCEWAKE_MT_ENABLE (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03006062#define VLV_SPAREG2H 0xA194
Chris Wilson8fd26852010-12-08 18:40:43 +00006063
Ben Widawskydd202c62012-02-09 10:15:18 +01006064#define GTFIFODBG 0x120000
Ville Syrjälä90f256b2013-11-14 01:59:59 +02006065#define GT_FIFO_SBDROPERR (1<<6)
6066#define GT_FIFO_BLOBDROPERR (1<<5)
6067#define GT_FIFO_SB_READ_ABORTERR (1<<4)
6068#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01006069#define GT_FIFO_OVFERR (1<<2)
6070#define GT_FIFO_IAWRERR (1<<1)
6071#define GT_FIFO_IARDERR (1<<0)
6072
Ville Syrjälä46520e22013-11-14 02:00:00 +02006073#define GTFIFOCTL 0x120008
6074#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01006075#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Chris Wilson91355832011-03-04 19:22:40 +00006076
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006077#define HSW_IDICR 0x9008
6078#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6079#define HSW_EDRAM_PRESENT 0x120010
Damien Lespiau2db59d52015-02-03 14:25:14 +00006080#define EDRAM_ENABLED 0x1
Ben Widawsky05e21cc2013-07-04 11:02:04 -07006081
Daniel Vetter80e829f2012-03-31 11:21:57 +02006082#define GEN6_UCGCTL1 0x9400
Ville Syrjäläe4443e42014-04-09 13:28:41 +03006083# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006084# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02006085# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02006086
Eric Anholt406478d2011-11-07 16:07:04 -08006087#define GEN6_UCGCTL2 0x9404
Jesse Barnes0f846f82012-06-14 11:04:47 -07006088# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07006089# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08006090# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08006091# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08006092# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08006093
Imre Deak9e72b462014-05-05 15:13:55 +03006094#define GEN6_UCGCTL3 0x9408
6095
Jesse Barnese3f33d42012-06-14 11:04:50 -07006096#define GEN7_UCGCTL4 0x940c
6097#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6098
Imre Deak9e72b462014-05-05 15:13:55 +03006099#define GEN6_RCGCTL1 0x9410
6100#define GEN6_RCGCTL2 0x9414
6101#define GEN6_RSTCTL 0x9420
6102
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006103#define GEN8_UCGCTL6 0x9430
Damien Lespiau9253c2e2015-02-09 19:33:10 +00006104#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02006105#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6106
Imre Deak9e72b462014-05-05 15:13:55 +03006107#define GEN6_GFXPAUSE 0xA000
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006108#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00006109#define GEN6_TURBO_DISABLE (1<<31)
6110#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03006111#define HSW_FREQUENCY(x) ((x)<<24)
Akash Goelde43ae92015-03-06 11:07:14 +05306112#define GEN9_FREQUENCY(x) ((x)<<23)
Chris Wilson8fd26852010-12-08 18:40:43 +00006113#define GEN6_OFFSET(x) ((x)<<19)
6114#define GEN6_AGGRESSIVE_TURBO (0<<15)
6115#define GEN6_RC_VIDEO_FREQ 0xA00C
6116#define GEN6_RC_CONTROL 0xA090
6117#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6118#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6119#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
6120#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
6121#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08006122#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07006123#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00006124#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6125#define GEN6_RC_CTL_HW_ENABLE (1<<31)
6126#define GEN6_RP_DOWN_TIMEOUT 0xA010
6127#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006128#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08006129#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08006130#define HSW_CAGF_SHIFT 7
Akash Goelde43ae92015-03-06 11:07:14 +05306131#define GEN9_CAGF_SHIFT 23
Jesse Barnesccab5c82011-01-18 15:49:25 -08006132#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08006133#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Akash Goelde43ae92015-03-06 11:07:14 +05306134#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00006135#define GEN6_RP_CONTROL 0xA024
6136#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08006137#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6138#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6139#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6140#define GEN6_RP_MEDIA_HW_MODE (1<<9)
6141#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00006142#define GEN6_RP_MEDIA_IS_GFX (1<<8)
6143#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08006144#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6145#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6146#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01006147#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08006148#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00006149#define GEN6_RP_UP_THRESHOLD 0xA02C
6150#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08006151#define GEN6_RP_CUR_UP_EI 0xA050
6152#define GEN6_CURICONT_MASK 0xffffff
6153#define GEN6_RP_CUR_UP 0xA054
6154#define GEN6_CURBSYTAVG_MASK 0xffffff
6155#define GEN6_RP_PREV_UP 0xA058
6156#define GEN6_RP_CUR_DOWN_EI 0xA05C
6157#define GEN6_CURIAVG_MASK 0xffffff
6158#define GEN6_RP_CUR_DOWN 0xA060
6159#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00006160#define GEN6_RP_UP_EI 0xA068
6161#define GEN6_RP_DOWN_EI 0xA06C
6162#define GEN6_RP_IDLE_HYSTERSIS 0xA070
Imre Deak9e72b462014-05-05 15:13:55 +03006163#define GEN6_RPDEUHWTC 0xA080
6164#define GEN6_RPDEUC 0xA084
6165#define GEN6_RPDEUCSW 0xA088
Chris Wilson8fd26852010-12-08 18:40:43 +00006166#define GEN6_RC_STATE 0xA094
6167#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
6168#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
6169#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
6170#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
6171#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
6172#define GEN6_RC_SLEEP 0xA0B0
Imre Deak9e72b462014-05-05 15:13:55 +03006173#define GEN6_RCUBMABDTMR 0xA0B0
Chris Wilson8fd26852010-12-08 18:40:43 +00006174#define GEN6_RC1e_THRESHOLD 0xA0B4
6175#define GEN6_RC6_THRESHOLD 0xA0B8
6176#define GEN6_RC6p_THRESHOLD 0xA0BC
Imre Deak9e72b462014-05-05 15:13:55 +03006177#define VLV_RCEDATA 0xA0BC
Chris Wilson8fd26852010-12-08 18:40:43 +00006178#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006179#define GEN6_PMINTRMSK 0xA168
Deepak Sbaccd452014-05-15 20:58:09 +03006180#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
Imre Deak9e72b462014-05-05 15:13:55 +03006181#define VLV_PWRDWNUPCTL 0xA294
Zhe Wang38c23522015-01-20 12:23:04 +00006182#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
6183#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
6184#define GEN9_PG_ENABLE 0xA210
Chris Wilson8fd26852010-12-08 18:40:43 +00006185
Gaurav K Singha9da9bc2014-12-05 14:13:41 +05306186#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6187#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6188#define PIXEL_OVERLAP_CNT_SHIFT 30
6189
Chris Wilson8fd26852010-12-08 18:40:43 +00006190#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07006191#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00006192#define GEN6_PMIIR 0x44028
6193#define GEN6_PMIER 0x4402C
6194#define GEN6_PM_MBOX_EVENT (1<<25)
6195#define GEN6_PM_THERMAL_EVENT (1<<24)
6196#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6197#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6198#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6199#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6200#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07006201#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07006202 GEN6_PM_RP_DOWN_THRESHOLD | \
6203 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00006204
Imre Deak9e72b462014-05-05 15:13:55 +03006205#define GEN7_GT_SCRATCH_BASE 0x4F100
6206#define GEN7_GT_SCRATCH_REG_NUM 8
6207
Deepak S76c3552f2014-01-30 23:08:16 +05306208#define VLV_GTLC_SURVIVABILITY_REG 0x130098
6209#define VLV_GFX_CLK_STATUS_BIT (1<<3)
6210#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6211
Ben Widawskycce66a22012-03-27 18:59:38 -07006212#define GEN6_GT_GFX_RC6_LOCKED 0x138104
Jesse Barnes49798eb2013-09-26 17:55:57 -07006213#define VLV_COUNTER_CONTROL 0x138104
6214#define VLV_COUNT_RANGE_HIGH (1<<15)
Deepak S31685c22014-07-03 17:33:01 -04006215#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6216#define VLV_RENDER_RC0_COUNT_EN (1<<4)
Jesse Barnes49798eb2013-09-26 17:55:57 -07006217#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6218#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ben Widawskycce66a22012-03-27 18:59:38 -07006219#define GEN6_GT_GFX_RC6 0x138108
Imre Deak9cc19be2014-04-14 20:24:24 +03006220#define VLV_GT_RENDER_RC6 0x138108
6221#define VLV_GT_MEDIA_RC6 0x13810C
6222
Ben Widawskycce66a22012-03-27 18:59:38 -07006223#define GEN6_GT_GFX_RC6p 0x13810C
6224#define GEN6_GT_GFX_RC6pp 0x138110
Chris Wilson43cf3bf2015-03-18 09:48:22 +00006225#define VLV_RENDER_C0_COUNT 0x138118
6226#define VLV_MEDIA_C0_COUNT 0x13811C
Ben Widawskycce66a22012-03-27 18:59:38 -07006227
Chris Wilson8fd26852010-12-08 18:40:43 +00006228#define GEN6_PCODE_MAILBOX 0x138124
6229#define GEN6_PCODE_READY (1<<31)
Jesse Barnesa6044e22010-12-20 11:34:20 -08006230#define GEN6_READ_OC_PARAMS 0xc
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07006231#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6232#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
Ben Widawsky31643d52012-09-26 10:34:01 -07006233#define GEN6_PCODE_WRITE_RC6VIDS 0x4
6234#define GEN6_PCODE_READ_RC6VIDS 0x5
Paulo Zanoni515b2392013-09-10 19:36:37 -03006235#define GEN6_PCODE_READ_D_COMP 0x10
6236#define GEN6_PCODE_WRITE_D_COMP 0x11
Ben Widawsky7083e052013-02-01 16:41:14 -08006237#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6238#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ben Widawsky2a114cc2013-11-02 21:07:47 -07006239#define DISPLAY_IPS_CONTROL 0x19
Tom O'Rourke93ee2922014-11-19 14:21:52 -08006240#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
Chris Wilson8fd26852010-12-08 18:40:43 +00006241#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07006242#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01006243#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Damien Lespiaudddab342014-11-13 17:51:50 +00006244#define GEN6_PCODE_DATA1 0x13812C
Chris Wilson8fd26852010-12-08 18:40:43 +00006245
Pradeep Bhat2af30a52014-11-04 17:06:38 +00006246#define GEN9_PCODE_READ_MEM_LATENCY 0x6
6247#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6248#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6249#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6250#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
6251
Ben Widawsky4d855292011-12-12 19:34:16 -08006252#define GEN6_GT_CORE_STATUS 0x138060
6253#define GEN6_CORE_CPD_STATE_MASK (7<<4)
6254#define GEN6_RCn_MASK 7
6255#define GEN6_RC0 0
6256#define GEN6_RC3 2
6257#define GEN6_RC6 3
6258#define GEN6_RC7 4
6259
Jeff McGee5575f032015-02-27 10:22:32 -08006260#define CHV_POWER_SS0_SIG1 0xa720
6261#define CHV_POWER_SS1_SIG1 0xa728
6262#define CHV_SS_PG_ENABLE (1<<1)
6263#define CHV_EU08_PG_ENABLE (1<<9)
6264#define CHV_EU19_PG_ENABLE (1<<17)
6265#define CHV_EU210_PG_ENABLE (1<<25)
6266
6267#define CHV_POWER_SS0_SIG2 0xa724
6268#define CHV_POWER_SS1_SIG2 0xa72c
6269#define CHV_EU311_PG_ENABLE (1<<1)
6270
Jeff McGee7f992ab2015-02-13 10:27:55 -06006271#define GEN9_SLICE0_PGCTL_ACK 0x804c
6272#define GEN9_SLICE1_PGCTL_ACK 0x8050
6273#define GEN9_SLICE2_PGCTL_ACK 0x8054
6274#define GEN9_PGCTL_SLICE_ACK (1 << 0)
6275
6276#define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c
6277#define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060
6278#define GEN9_SLICE1_SS01_EU_PGCTL_ACK 0x8064
6279#define GEN9_SLICE1_SS23_EU_PGCTL_ACK 0x8068
6280#define GEN9_SLICE2_SS01_EU_PGCTL_ACK 0x806c
6281#define GEN9_SLICE2_SS23_EU_PGCTL_ACK 0x8070
6282#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
6283#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
6284#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
6285#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
6286#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
6287#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
6288#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
6289#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
6290
Ben Widawskye3689192012-05-25 16:56:22 -07006291#define GEN7_MISCCPCTL (0x9424)
6292#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6293
6294/* IVYBRIDGE DPF */
6295#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07006296#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07006297#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6298#define GEN7_PARITY_ERROR_VALID (1<<13)
6299#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6300#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6301#define GEN7_PARITY_ERROR_ROW(reg) \
6302 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6303#define GEN7_PARITY_ERROR_BANK(reg) \
6304 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6305#define GEN7_PARITY_ERROR_SUBBANK(reg) \
6306 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6307#define GEN7_L3CDERRST1_ENABLE (1<<7)
6308
Ben Widawskyb9524a12012-05-25 16:56:24 -07006309#define GEN7_L3LOG_BASE 0xB070
Ben Widawsky35a85ac2013-09-19 11:13:41 -07006310#define HSW_L3LOG_BASE_SLICE1 0xB270
Ben Widawskyb9524a12012-05-25 16:56:24 -07006311#define GEN7_L3LOG_SIZE 0x80
6312
Jesse Barnes12f33822012-10-25 12:15:45 -07006313#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6314#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6315#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07006316#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Jesse Barnes12f33822012-10-25 12:15:45 -07006317#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6318
Damien Lespiau3ca5da42014-03-26 18:18:01 +00006319#define GEN9_HALF_SLICE_CHICKEN5 0xe188
6320#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
Damien Lespiaue2db7072015-02-09 19:33:21 +00006321#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
Damien Lespiau3ca5da42014-03-26 18:18:01 +00006322
Kenneth Graunkec8966e12014-02-26 23:59:30 -08006323#define GEN8_ROW_CHICKEN 0xe4f0
6324#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08006325#define STALL_DOP_GATING_DISABLE (1<<5)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08006326
Jesse Barnes8ab43972012-10-25 12:15:42 -07006327#define GEN7_ROW_CHICKEN2 0xe4f4
6328#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
6329#define DOP_CLOCK_GATING_DISABLE (1<<0)
6330
Francisco Jerezf3fc4882013-10-02 15:53:16 -07006331#define HSW_ROW_CHICKEN3 0xe49c
6332#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
6333
Ben Widawskyfd392b62013-11-04 22:52:39 -08006334#define HALF_SLICE_CHICKEN3 0xe184
Kenneth Graunke94411592014-12-31 16:23:00 -08006335#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
Ben Widawskyfd392b62013-11-04 22:52:39 -08006336#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Nick Hoath84241712015-02-05 10:47:20 +00006337#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
Ben Widawskybf663472013-11-02 21:07:57 -07006338#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08006339
Nick Hoathcac23df2015-02-05 10:47:22 +00006340#define GEN9_HALF_SLICE_CHICKEN7 0xe194
6341#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
6342
Jani Nikulac46f1112014-10-27 16:26:52 +02006343/* Audio */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006344#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
Jani Nikulac46f1112014-10-27 16:26:52 +02006345#define INTEL_AUDIO_DEVCL 0x808629FB
6346#define INTEL_AUDIO_DEVBLC 0x80862801
6347#define INTEL_AUDIO_DEVCTG 0x80862802
Wu Fengguange0dac652011-09-05 14:25:34 +08006348
6349#define G4X_AUD_CNTL_ST 0x620B4
Jani Nikulac46f1112014-10-27 16:26:52 +02006350#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
6351#define G4X_ELDV_DEVCTG (1 << 14)
6352#define G4X_ELD_ADDR_MASK (0xf << 5)
6353#define G4X_ELD_ACK (1 << 4)
Wu Fengguange0dac652011-09-05 14:25:34 +08006354#define G4X_HDMIW_HDMIEDID 0x6210C
6355
Jani Nikulac46f1112014-10-27 16:26:52 +02006356#define _IBX_HDMIW_HDMIEDID_A 0xE2050
6357#define _IBX_HDMIW_HDMIEDID_B 0xE2150
Wang Xingchao9b138a82012-08-09 16:52:18 +08006358#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006359 _IBX_HDMIW_HDMIEDID_A, \
6360 _IBX_HDMIW_HDMIEDID_B)
6361#define _IBX_AUD_CNTL_ST_A 0xE20B4
6362#define _IBX_AUD_CNTL_ST_B 0xE21B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08006363#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006364 _IBX_AUD_CNTL_ST_A, \
6365 _IBX_AUD_CNTL_ST_B)
6366#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
6367#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
6368#define IBX_ELD_ACK (1 << 4)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006369#define IBX_AUD_CNTL_ST2 0xE20C0
Jani Nikula82910ac2014-10-27 16:26:59 +02006370#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
6371#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
Wu Fengguange0dac652011-09-05 14:25:34 +08006372
Jani Nikulac46f1112014-10-27 16:26:52 +02006373#define _CPT_HDMIW_HDMIEDID_A 0xE5050
6374#define _CPT_HDMIW_HDMIEDID_B 0xE5150
Wang Xingchao9b138a82012-08-09 16:52:18 +08006375#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006376 _CPT_HDMIW_HDMIEDID_A, \
6377 _CPT_HDMIW_HDMIEDID_B)
6378#define _CPT_AUD_CNTL_ST_A 0xE50B4
6379#define _CPT_AUD_CNTL_ST_B 0xE51B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08006380#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006381 _CPT_AUD_CNTL_ST_A, \
6382 _CPT_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006383#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08006384
Jani Nikulac46f1112014-10-27 16:26:52 +02006385#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
6386#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006387#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006388 _VLV_HDMIW_HDMIEDID_A, \
6389 _VLV_HDMIW_HDMIEDID_B)
6390#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
6391#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006392#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006393 _VLV_AUD_CNTL_ST_A, \
6394 _VLV_AUD_CNTL_ST_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006395#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
6396
Eric Anholtae662d32012-01-03 09:23:29 -08006397/* These are the 4 32-bit write offset registers for each stream
6398 * output buffer. It determines the offset from the
6399 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6400 */
6401#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
6402
Jani Nikulac46f1112014-10-27 16:26:52 +02006403#define _IBX_AUD_CONFIG_A 0xe2000
6404#define _IBX_AUD_CONFIG_B 0xe2100
Wang Xingchao9b138a82012-08-09 16:52:18 +08006405#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006406 _IBX_AUD_CONFIG_A, \
6407 _IBX_AUD_CONFIG_B)
6408#define _CPT_AUD_CONFIG_A 0xe5000
6409#define _CPT_AUD_CONFIG_B 0xe5100
Wang Xingchao9b138a82012-08-09 16:52:18 +08006410#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006411 _CPT_AUD_CONFIG_A, \
6412 _CPT_AUD_CONFIG_B)
6413#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
6414#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006415#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
Jani Nikulac46f1112014-10-27 16:26:52 +02006416 _VLV_AUD_CONFIG_A, \
6417 _VLV_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04006418
Wu Fengguangb6daa022012-01-06 14:41:31 -06006419#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
6420#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
6421#define AUD_CONFIG_UPPER_N_SHIFT 20
Jani Nikulac46f1112014-10-27 16:26:52 +02006422#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006423#define AUD_CONFIG_LOWER_N_SHIFT 4
Jani Nikulac46f1112014-10-27 16:26:52 +02006424#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006425#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03006426#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
6427#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
6428#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
6429#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
6430#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
6431#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
6432#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
6433#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
6434#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
6435#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
6436#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06006437#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
6438
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006439/* HSW Audio */
Jani Nikulac46f1112014-10-27 16:26:52 +02006440#define _HSW_AUD_CONFIG_A 0x65000
6441#define _HSW_AUD_CONFIG_B 0x65100
6442#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
6443 _HSW_AUD_CONFIG_A, \
6444 _HSW_AUD_CONFIG_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006445
Jani Nikulac46f1112014-10-27 16:26:52 +02006446#define _HSW_AUD_MISC_CTRL_A 0x65010
6447#define _HSW_AUD_MISC_CTRL_B 0x65110
6448#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
6449 _HSW_AUD_MISC_CTRL_A, \
6450 _HSW_AUD_MISC_CTRL_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006451
Jani Nikulac46f1112014-10-27 16:26:52 +02006452#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
6453#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
6454#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
6455 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
6456 _HSW_AUD_DIP_ELD_CTRL_ST_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006457
6458/* Audio Digital Converter */
Jani Nikulac46f1112014-10-27 16:26:52 +02006459#define _HSW_AUD_DIG_CNVT_1 0x65080
6460#define _HSW_AUD_DIG_CNVT_2 0x65180
6461#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
6462 _HSW_AUD_DIG_CNVT_1, \
6463 _HSW_AUD_DIG_CNVT_2)
6464#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006465
Jani Nikulac46f1112014-10-27 16:26:52 +02006466#define _HSW_AUD_EDID_DATA_A 0x65050
6467#define _HSW_AUD_EDID_DATA_B 0x65150
6468#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
6469 _HSW_AUD_EDID_DATA_A, \
6470 _HSW_AUD_EDID_DATA_B)
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006471
Jani Nikulac46f1112014-10-27 16:26:52 +02006472#define HSW_AUD_PIPE_CONV_CFG 0x6507c
6473#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
Jani Nikula82910ac2014-10-27 16:26:59 +02006474#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
6475#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
6476#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
6477#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08006478
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03006479/* HSW Power Wells */
Paulo Zanonifa42e232013-01-25 16:59:11 -02006480#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
6481#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
6482#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
6483#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03006484#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
6485#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006486#define HSW_PWR_WELL_CTL5 0x45410
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03006487#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
6488#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006489#define HSW_PWR_WELL_FORCE_ON (1<<19)
6490#define HSW_PWR_WELL_CTL6 0x45414
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03006491
Satheeshakrishna M94dd5132015-02-04 13:57:44 +00006492/* SKL Fuse Status */
6493#define SKL_FUSE_STATUS 0x42000
6494#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
6495#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
6496#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
6497#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
6498
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03006499/* Per-pipe DDI Function Control */
Paulo Zanoniad80a812012-10-24 16:06:19 -02006500#define TRANS_DDI_FUNC_CTL_A 0x60400
6501#define TRANS_DDI_FUNC_CTL_B 0x61400
6502#define TRANS_DDI_FUNC_CTL_C 0x62400
6503#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006504#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
6505
Paulo Zanoniad80a812012-10-24 16:06:19 -02006506#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03006507/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02006508#define TRANS_DDI_PORT_MASK (7<<28)
Daniel Vetter26804af2014-06-25 22:01:55 +03006509#define TRANS_DDI_PORT_SHIFT 28
Paulo Zanoniad80a812012-10-24 16:06:19 -02006510#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
6511#define TRANS_DDI_PORT_NONE (0<<28)
6512#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
6513#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
6514#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
6515#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
6516#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
6517#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
6518#define TRANS_DDI_BPC_MASK (7<<20)
6519#define TRANS_DDI_BPC_8 (0<<20)
6520#define TRANS_DDI_BPC_10 (1<<20)
6521#define TRANS_DDI_BPC_6 (2<<20)
6522#define TRANS_DDI_BPC_12 (3<<20)
6523#define TRANS_DDI_PVSYNC (1<<17)
6524#define TRANS_DDI_PHSYNC (1<<16)
6525#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
6526#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
6527#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
6528#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
6529#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
Dave Airlie01b887c2014-05-02 11:17:41 +10006530#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
Paulo Zanoniad80a812012-10-24 16:06:19 -02006531#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03006532
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03006533/* DisplayPort Transport Control */
6534#define DP_TP_CTL_A 0x64040
6535#define DP_TP_CTL_B 0x64140
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006536#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
6537#define DP_TP_CTL_ENABLE (1<<31)
6538#define DP_TP_CTL_MODE_SST (0<<27)
6539#define DP_TP_CTL_MODE_MST (1<<27)
Dave Airlie01b887c2014-05-02 11:17:41 +10006540#define DP_TP_CTL_FORCE_ACT (1<<25)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03006541#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006542#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03006543#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
6544#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
6545#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03006546#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
6547#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006548#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03006549#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03006550
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03006551/* DisplayPort Transport Status */
6552#define DP_TP_STATUS_A 0x64044
6553#define DP_TP_STATUS_B 0x64144
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006554#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
Dave Airlie01b887c2014-05-02 11:17:41 +10006555#define DP_TP_STATUS_IDLE_DONE (1<<25)
6556#define DP_TP_STATUS_ACT_SENT (1<<24)
6557#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
6558#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
6559#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
6560#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
6561#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03006562
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03006563/* DDI Buffer Control */
6564#define DDI_BUF_CTL_A 0x64000
6565#define DDI_BUF_CTL_B 0x64100
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006566#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
6567#define DDI_BUF_CTL_ENABLE (1<<31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05306568#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006569#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00006570#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006571#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02006572#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02006573#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03006574#define DDI_INIT_DISPLAY_DETECTED (1<<0)
6575
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03006576/* DDI Buffer Translations */
6577#define DDI_BUF_TRANS_A 0x64E00
6578#define DDI_BUF_TRANS_B 0x64E60
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006579#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03006580
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006581/* Sideband Interface (SBI) is programmed indirectly, via
6582 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6583 * which contains the payload */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006584#define SBI_ADDR 0xC6000
6585#define SBI_DATA 0xC6004
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006586#define SBI_CTL_STAT 0xC6008
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02006587#define SBI_CTL_DEST_ICLK (0x0<<16)
6588#define SBI_CTL_DEST_MPHY (0x1<<16)
6589#define SBI_CTL_OP_IORD (0x2<<8)
6590#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006591#define SBI_CTL_OP_CRRD (0x6<<8)
6592#define SBI_CTL_OP_CRWR (0x7<<8)
6593#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006594#define SBI_RESPONSE_SUCCESS (0x0<<1)
6595#define SBI_BUSY (0x1<<0)
6596#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006597
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006598/* SBI offsets */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006599#define SBI_SSCDIVINTPHASE6 0x0600
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006600#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
6601#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
6602#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
6603#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006604#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006605#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006606#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006607#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02006608#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006609#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006610#define SBI_SSCAUXDIV6 0x0610
6611#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006612#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006613#define SBI_GEN0 0x1f00
6614#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006615
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006616/* LPT PIXCLK_GATE */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006617#define PIXCLK_GATE 0xC6020
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03006618#define PIXCLK_GATE_UNGATE (1<<0)
6619#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006620
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006621/* SPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006622#define SPLL_CTL 0x46020
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006623#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01006624#define SPLL_PLL_SSC (1<<28)
6625#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08006626#define SPLL_PLL_LCPLL (3<<28)
6627#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006628#define SPLL_PLL_FREQ_810MHz (0<<26)
6629#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08006630#define SPLL_PLL_FREQ_2700MHz (2<<26)
6631#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006632
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03006633/* WRPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006634#define WRPLL_CTL1 0x46040
6635#define WRPLL_CTL2 0x46060
Daniel Vetterd452c5b2014-07-04 11:27:39 -03006636#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006637#define WRPLL_PLL_ENABLE (1<<31)
Daniel Vetter114fe482014-06-25 22:01:48 +03006638#define WRPLL_PLL_SSC (1<<28)
6639#define WRPLL_PLL_NON_SSC (2<<28)
6640#define WRPLL_PLL_LCPLL (3<<28)
6641#define WRPLL_PLL_REF_MASK (3<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03006642/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006643#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08006644#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006645#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08006646#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
6647#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006648#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08006649#define WRPLL_DIVIDER_FB_SHIFT 16
6650#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03006651
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006652/* Port clock selection */
6653#define PORT_CLK_SEL_A 0x46100
6654#define PORT_CLK_SEL_B 0x46104
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006655#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006656#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
6657#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
6658#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006659#define PORT_CLK_SEL_SPLL (3<<29)
Daniel Vetter716c2e52014-06-25 22:02:02 +03006660#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006661#define PORT_CLK_SEL_WRPLL1 (4<<29)
6662#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03006663#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08006664#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006665
Paulo Zanonibb523fc2012-10-23 18:29:56 -02006666/* Transcoder clock selection */
6667#define TRANS_CLK_SEL_A 0x46140
6668#define TRANS_CLK_SEL_B 0x46144
6669#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
6670/* For each transcoder, we need to select the corresponding port clock */
6671#define TRANS_CLK_SEL_DISABLED (0x0<<29)
6672#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006673
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006674#define TRANSA_MSA_MISC 0x60410
6675#define TRANSB_MSA_MISC 0x61410
6676#define TRANSC_MSA_MISC 0x62410
6677#define TRANS_EDP_MSA_MISC 0x6f410
6678#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
6679
Paulo Zanonic9809792012-10-23 18:30:00 -02006680#define TRANS_MSA_SYNC_CLK (1<<0)
6681#define TRANS_MSA_6_BPC (0<<5)
6682#define TRANS_MSA_8_BPC (1<<5)
6683#define TRANS_MSA_10_BPC (2<<5)
6684#define TRANS_MSA_12_BPC (3<<5)
6685#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03006686
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006687/* LCPLL Control */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006688#define LCPLL_CTL 0x130040
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006689#define LCPLL_PLL_DISABLE (1<<31)
6690#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03006691#define LCPLL_CLK_FREQ_MASK (3<<26)
6692#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07006693#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
6694#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
6695#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006696#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006697#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006698#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03006699#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006700#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
6701
Satheeshakrishna M326ac392014-11-13 14:55:13 +00006702/*
6703 * SKL Clocks
6704 */
6705
6706/* CDCLK_CTL */
6707#define CDCLK_CTL 0x46000
6708#define CDCLK_FREQ_SEL_MASK (3<<26)
6709#define CDCLK_FREQ_450_432 (0<<26)
6710#define CDCLK_FREQ_540 (1<<26)
6711#define CDCLK_FREQ_337_308 (2<<26)
6712#define CDCLK_FREQ_675_617 (3<<26)
6713#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
6714
6715/* LCPLL_CTL */
6716#define LCPLL1_CTL 0x46010
6717#define LCPLL2_CTL 0x46014
6718#define LCPLL_PLL_ENABLE (1<<31)
6719
6720/* DPLL control1 */
6721#define DPLL_CTRL1 0x6C058
6722#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
6723#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
6724#define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
Satheeshakrishna M540e7322014-11-13 14:55:16 +00006725#define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1)
Satheeshakrishna M326ac392014-11-13 14:55:13 +00006726#define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
6727#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
6728#define DPLL_CRTL1_LINK_RATE_2700 0
6729#define DPLL_CRTL1_LINK_RATE_1350 1
6730#define DPLL_CRTL1_LINK_RATE_810 2
6731#define DPLL_CRTL1_LINK_RATE_1620 3
6732#define DPLL_CRTL1_LINK_RATE_1080 4
6733#define DPLL_CRTL1_LINK_RATE_2160 5
6734
6735/* DPLL control2 */
6736#define DPLL_CTRL2 0x6C05C
6737#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
6738#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
Satheeshakrishna M540e7322014-11-13 14:55:16 +00006739#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
Satheeshakrishna M326ac392014-11-13 14:55:13 +00006740#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
6741#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
6742
6743/* DPLL Status */
6744#define DPLL_STATUS 0x6C060
6745#define DPLL_LOCK(id) (1<<((id)*8))
6746
6747/* DPLL cfg */
6748#define DPLL1_CFGCR1 0x6C040
6749#define DPLL2_CFGCR1 0x6C048
6750#define DPLL3_CFGCR1 0x6C050
6751#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
6752#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
6753#define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
6754#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
6755
6756#define DPLL1_CFGCR2 0x6C044
6757#define DPLL2_CFGCR2 0x6C04C
6758#define DPLL3_CFGCR2 0x6C054
6759#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
6760#define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
6761#define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
6762#define DPLL_CFGCR2_KDIV_MASK (3<<5)
6763#define DPLL_CFGCR2_KDIV(x) (x<<5)
6764#define DPLL_CFGCR2_KDIV_5 (0<<5)
6765#define DPLL_CFGCR2_KDIV_2 (1<<5)
6766#define DPLL_CFGCR2_KDIV_3 (2<<5)
6767#define DPLL_CFGCR2_KDIV_1 (3<<5)
6768#define DPLL_CFGCR2_PDIV_MASK (7<<2)
6769#define DPLL_CFGCR2_PDIV(x) (x<<2)
6770#define DPLL_CFGCR2_PDIV_1 (0<<2)
6771#define DPLL_CFGCR2_PDIV_2 (1<<2)
6772#define DPLL_CFGCR2_PDIV_3 (2<<2)
6773#define DPLL_CFGCR2_PDIV_7 (4<<2)
6774#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
6775
Satheeshakrishna M540e7322014-11-13 14:55:16 +00006776#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
6777#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
6778
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03006779/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6780 * since on HSW we can't write to it using I915_WRITE. */
6781#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6782#define D_COMP_BDW 0x138144
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006783#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
6784#define D_COMP_COMP_FORCE (1<<8)
6785#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006786
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03006787/* Pipe WM_LINETIME - watermark line time */
6788#define PIPE_WM_LINETIME_A 0x45270
6789#define PIPE_WM_LINETIME_B 0x45274
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006790#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
6791 PIPE_WM_LINETIME_B)
6792#define PIPE_WM_LINETIME_MASK (0x1ff)
6793#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03006794#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006795#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03006796
6797/* SFUSE_STRAP */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006798#define SFUSE_STRAP 0xc2014
Damien Lespiau658ac4c2014-02-10 17:19:45 +00006799#define SFUSE_STRAP_FUSE_LOCK (1<<13)
6800#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03006801#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
6802#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
6803#define SFUSE_STRAP_DDID_DETECTED (1<<0)
6804
Paulo Zanoni801bcff2013-05-31 10:08:35 -03006805#define WM_MISC 0x45260
6806#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6807
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03006808#define WM_DBG 0x45280
6809#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
6810#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
6811#define WM_DBG_DISALLOW_SPRITE (1<<2)
6812
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006813/* pipe CSC */
6814#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6815#define _PIPE_A_CSC_COEFF_BY 0x49014
6816#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6817#define _PIPE_A_CSC_COEFF_BU 0x4901c
6818#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6819#define _PIPE_A_CSC_COEFF_BV 0x49024
6820#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03006821#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
6822#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
6823#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006824#define _PIPE_A_CSC_PREOFF_HI 0x49030
6825#define _PIPE_A_CSC_PREOFF_ME 0x49034
6826#define _PIPE_A_CSC_PREOFF_LO 0x49038
6827#define _PIPE_A_CSC_POSTOFF_HI 0x49040
6828#define _PIPE_A_CSC_POSTOFF_ME 0x49044
6829#define _PIPE_A_CSC_POSTOFF_LO 0x49048
6830
6831#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6832#define _PIPE_B_CSC_COEFF_BY 0x49114
6833#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6834#define _PIPE_B_CSC_COEFF_BU 0x4911c
6835#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6836#define _PIPE_B_CSC_COEFF_BV 0x49124
6837#define _PIPE_B_CSC_MODE 0x49128
6838#define _PIPE_B_CSC_PREOFF_HI 0x49130
6839#define _PIPE_B_CSC_PREOFF_ME 0x49134
6840#define _PIPE_B_CSC_PREOFF_LO 0x49138
6841#define _PIPE_B_CSC_POSTOFF_HI 0x49140
6842#define _PIPE_B_CSC_POSTOFF_ME 0x49144
6843#define _PIPE_B_CSC_POSTOFF_LO 0x49148
6844
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006845#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6846#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6847#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6848#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6849#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6850#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6851#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6852#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6853#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6854#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6855#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6856#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6857#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6858
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006859/* MIPI DSI registers */
6860
6861#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
Jani Nikula3230bf12013-08-27 15:12:16 +03006862
6863#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006864#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
6865#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
6866#define DPI_ENABLE (1 << 31) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03006867#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
6868#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
Gaurav K Singh369602d2014-12-05 14:09:28 +05306869#define DUAL_LINK_MODE_SHIFT 26
Jani Nikula3230bf12013-08-27 15:12:16 +03006870#define DUAL_LINK_MODE_MASK (1 << 26)
6871#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
6872#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006873#define DITHERING_ENABLE (1 << 25) /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03006874#define FLOPPED_HSTX (1 << 23)
6875#define DE_INVERT (1 << 19) /* XXX */
6876#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
6877#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
6878#define AFE_LATCHOUT (1 << 17)
6879#define LP_OUTPUT_HOLD (1 << 16)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006880#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
6881#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
6882#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
6883#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
Jani Nikula3230bf12013-08-27 15:12:16 +03006884#define CSB_SHIFT 9
6885#define CSB_MASK (3 << 9)
6886#define CSB_20MHZ (0 << 9)
6887#define CSB_10MHZ (1 << 9)
6888#define CSB_40MHZ (2 << 9)
6889#define BANDGAP_MASK (1 << 8)
6890#define BANDGAP_PNW_CIRCUIT (0 << 8)
6891#define BANDGAP_LNC_CIRCUIT (1 << 8)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006892#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
6893#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
6894#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
6895#define TEARING_EFFECT_SHIFT 2 /* A + C */
Jani Nikula3230bf12013-08-27 15:12:16 +03006896#define TEARING_EFFECT_MASK (3 << 2)
6897#define TEARING_EFFECT_OFF (0 << 2)
6898#define TEARING_EFFECT_DSI (1 << 2)
6899#define TEARING_EFFECT_GPIO (2 << 2)
6900#define LANE_CONFIGURATION_SHIFT 0
6901#define LANE_CONFIGURATION_MASK (3 << 0)
6902#define LANE_CONFIGURATION_4LANE (0 << 0)
6903#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
6904#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
6905
6906#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006907#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
6908#define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \
6909 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006910#define TEARING_EFFECT_DELAY_SHIFT 0
6911#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
6912
6913/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306914#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +03006915
6916/* MIPI DSI Controller and D-PHY registers */
6917
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306918#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006919#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
6920#define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \
6921 _MIPIC_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +03006922#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
6923#define ULPS_STATE_MASK (3 << 1)
6924#define ULPS_STATE_ENTER (2 << 1)
6925#define ULPS_STATE_EXIT (1 << 1)
6926#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
6927#define DEVICE_READY (1 << 0)
6928
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306929#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006930#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
6931#define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \
6932 _MIPIC_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306933#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006934#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
6935#define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \
6936 _MIPIC_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +03006937#define TEARING_EFFECT (1 << 31)
6938#define SPL_PKT_SENT_INTERRUPT (1 << 30)
6939#define GEN_READ_DATA_AVAIL (1 << 29)
6940#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
6941#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
6942#define RX_PROT_VIOLATION (1 << 26)
6943#define RX_INVALID_TX_LENGTH (1 << 25)
6944#define ACK_WITH_NO_ERROR (1 << 24)
6945#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
6946#define LP_RX_TIMEOUT (1 << 22)
6947#define HS_TX_TIMEOUT (1 << 21)
6948#define DPI_FIFO_UNDERRUN (1 << 20)
6949#define LOW_CONTENTION (1 << 19)
6950#define HIGH_CONTENTION (1 << 18)
6951#define TXDSI_VC_ID_INVALID (1 << 17)
6952#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
6953#define TXCHECKSUM_ERROR (1 << 15)
6954#define TXECC_MULTIBIT_ERROR (1 << 14)
6955#define TXECC_SINGLE_BIT_ERROR (1 << 13)
6956#define TXFALSE_CONTROL_ERROR (1 << 12)
6957#define RXDSI_VC_ID_INVALID (1 << 11)
6958#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
6959#define RXCHECKSUM_ERROR (1 << 9)
6960#define RXECC_MULTIBIT_ERROR (1 << 8)
6961#define RXECC_SINGLE_BIT_ERROR (1 << 7)
6962#define RXFALSE_CONTROL_ERROR (1 << 6)
6963#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
6964#define RX_LP_TX_SYNC_ERROR (1 << 4)
6965#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
6966#define RXEOT_SYNC_ERROR (1 << 2)
6967#define RXSOT_SYNC_ERROR (1 << 1)
6968#define RXSOT_ERROR (1 << 0)
6969
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306970#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006971#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
6972#define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
6973 _MIPIC_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +03006974#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
6975#define CMD_MODE_NOT_SUPPORTED (0 << 13)
6976#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
6977#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
6978#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
6979#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
6980#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
6981#define VID_MODE_FORMAT_MASK (0xf << 7)
6982#define VID_MODE_NOT_SUPPORTED (0 << 7)
6983#define VID_MODE_FORMAT_RGB565 (1 << 7)
6984#define VID_MODE_FORMAT_RGB666 (2 << 7)
6985#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
6986#define VID_MODE_FORMAT_RGB888 (4 << 7)
6987#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
6988#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
6989#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
6990#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
6991#define DATA_LANES_PRG_REG_SHIFT 0
6992#define DATA_LANES_PRG_REG_MASK (7 << 0)
6993
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306994#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02006995#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
6996#define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
6997 _MIPIC_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006998#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
6999
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307000#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007001#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7002#define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
7003 _MIPIC_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007004#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
7005
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307006#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007007#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7008#define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \
7009 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007010#define TURN_AROUND_TIMEOUT_MASK 0x3f
7011
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307012#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007013#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7014#define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \
7015 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +03007016#define DEVICE_RESET_TIMER_MASK 0xffff
7017
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307018#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007019#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7020#define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
7021 _MIPIC_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +03007022#define VERTICAL_ADDRESS_SHIFT 16
7023#define VERTICAL_ADDRESS_MASK (0xffff << 16)
7024#define HORIZONTAL_ADDRESS_SHIFT 0
7025#define HORIZONTAL_ADDRESS_MASK 0xffff
7026
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307027#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007028#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7029#define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \
7030 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007031#define DBI_FIFO_EMPTY_HALF (0 << 0)
7032#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
7033#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
7034
7035/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307036#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007037#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7038#define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7039 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007040
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307041#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007042#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7043#define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \
7044 _MIPIC_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007045
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307046#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007047#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7048#define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \
7049 _MIPIC_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007050
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307051#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007052#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7053#define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \
7054 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007055
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307056#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007057#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7058#define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7059 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007060
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307061#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007062#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7063#define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \
7064 _MIPIC_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007065
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307066#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007067#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7068#define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \
7069 _MIPIC_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007070
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307071#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007072#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7073#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \
7074 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307075
Jani Nikula3230bf12013-08-27 15:12:16 +03007076/* regs above are bits 15:0 */
7077
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307078#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007079#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7080#define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
7081 _MIPIC_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007082#define DPI_LP_MODE (1 << 6)
7083#define BACKLIGHT_OFF (1 << 5)
7084#define BACKLIGHT_ON (1 << 4)
7085#define COLOR_MODE_OFF (1 << 3)
7086#define COLOR_MODE_ON (1 << 2)
7087#define TURN_ON (1 << 1)
7088#define SHUTDOWN (1 << 0)
7089
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307090#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007091#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7092#define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \
7093 _MIPIC_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007094#define COMMAND_BYTE_SHIFT 0
7095#define COMMAND_BYTE_MASK (0x3f << 0)
7096
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307097#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007098#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7099#define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \
7100 _MIPIC_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007101#define MASTER_INIT_TIMER_SHIFT 0
7102#define MASTER_INIT_TIMER_MASK (0xffff << 0)
7103
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307104#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007105#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7106#define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \
7107 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007108#define MAX_RETURN_PKT_SIZE_SHIFT 0
7109#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
7110
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307111#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007112#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7113#define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \
7114 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007115#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
7116#define DISABLE_VIDEO_BTA (1 << 3)
7117#define IP_TG_CONFIG (1 << 2)
7118#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
7119#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
7120#define VIDEO_MODE_BURST (3 << 0)
7121
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307122#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007123#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7124#define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
7125 _MIPIC_EOT_DISABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007126#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
7127#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
7128#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
7129#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
7130#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7131#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
7132#define CLOCKSTOP (1 << 1)
7133#define EOT_DISABLE (1 << 0)
7134
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307135#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007136#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7137#define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
7138 _MIPIC_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +03007139#define LP_BYTECLK_SHIFT 0
7140#define LP_BYTECLK_MASK (0xffff << 0)
7141
7142/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307143#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007144#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7145#define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
7146 _MIPIC_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007147
7148/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307149#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007150#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7151#define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
7152 _MIPIC_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03007153
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307154#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007155#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7156#define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
7157 _MIPIC_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307158#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007159#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7160#define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
7161 _MIPIC_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007162#define LONG_PACKET_WORD_COUNT_SHIFT 8
7163#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
7164#define SHORT_PACKET_PARAM_SHIFT 8
7165#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
7166#define VIRTUAL_CHANNEL_SHIFT 6
7167#define VIRTUAL_CHANNEL_MASK (3 << 6)
7168#define DATA_TYPE_SHIFT 0
7169#define DATA_TYPE_MASK (3f << 0)
7170/* data type values, see include/video/mipi_display.h */
7171
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307172#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007173#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
7174#define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
7175 _MIPIC_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007176#define DPI_FIFO_EMPTY (1 << 28)
7177#define DBI_FIFO_EMPTY (1 << 27)
7178#define LP_CTRL_FIFO_EMPTY (1 << 26)
7179#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
7180#define LP_CTRL_FIFO_FULL (1 << 24)
7181#define HS_CTRL_FIFO_EMPTY (1 << 18)
7182#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
7183#define HS_CTRL_FIFO_FULL (1 << 16)
7184#define LP_DATA_FIFO_EMPTY (1 << 10)
7185#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
7186#define LP_DATA_FIFO_FULL (1 << 8)
7187#define HS_DATA_FIFO_EMPTY (1 << 2)
7188#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
7189#define HS_DATA_FIFO_FULL (1 << 0)
7190
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307191#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007192#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
7193#define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \
7194 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03007195#define DBI_HS_LP_MODE_MASK (1 << 0)
7196#define DBI_LP_MODE (1 << 0)
7197#define DBI_HS_MODE (0 << 0)
7198
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307199#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007200#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
7201#define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
7202 _MIPIC_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +03007203#define EXIT_ZERO_COUNT_SHIFT 24
7204#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
7205#define TRAIL_COUNT_SHIFT 16
7206#define TRAIL_COUNT_MASK (0x1f << 16)
7207#define CLK_ZERO_COUNT_SHIFT 8
7208#define CLK_ZERO_COUNT_MASK (0xff << 8)
7209#define PREPARE_COUNT_SHIFT 0
7210#define PREPARE_COUNT_MASK (0x3f << 0)
7211
7212/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307213#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007214#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
7215#define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
7216 _MIPIC_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007217
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307218#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7219 + 0xb088)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007220#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307221 + 0xb888)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007222#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \
7223 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03007224#define LP_HS_SSW_CNT_SHIFT 16
7225#define LP_HS_SSW_CNT_MASK (0xffff << 16)
7226#define HS_LP_PWR_SW_CNT_SHIFT 0
7227#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
7228
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307229#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007230#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
7231#define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \
7232 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007233#define STOP_STATE_STALL_COUNTER_SHIFT 0
7234#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
7235
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307236#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007237#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
7238#define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \
7239 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307240#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007241#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7242#define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
7243 _MIPIC_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +03007244#define RX_CONTENTION_DETECTED (1 << 0)
7245
7246/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307247#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +03007248#define DBI_TYPEC_ENABLE (1 << 31)
7249#define DBI_TYPEC_WIP (1 << 30)
7250#define DBI_TYPEC_OPTION_SHIFT 28
7251#define DBI_TYPEC_OPTION_MASK (3 << 28)
7252#define DBI_TYPEC_FREQ_SHIFT 24
7253#define DBI_TYPEC_FREQ_MASK (0xf << 24)
7254#define DBI_TYPEC_OVERRIDE (1 << 8)
7255#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
7256#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
7257
7258
7259/* MIPI adapter registers */
7260
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307261#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007262#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7263#define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \
7264 _MIPIC_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03007265#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
7266#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
7267#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
7268#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
7269#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
7270#define READ_REQUEST_PRIORITY_SHIFT 3
7271#define READ_REQUEST_PRIORITY_MASK (3 << 3)
7272#define READ_REQUEST_PRIORITY_LOW (0 << 3)
7273#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
7274#define RGB_FLIP_TO_BGR (1 << 2)
7275
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307276#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007277#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7278#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
7279 _MIPIC_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03007280#define DATA_MEM_ADDRESS_SHIFT 5
7281#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
7282#define DATA_VALID (1 << 0)
7283
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307284#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007285#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7286#define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
7287 _MIPIC_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03007288#define DATA_LENGTH_SHIFT 0
7289#define DATA_LENGTH_MASK (0xfffff << 0)
7290
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307291#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007292#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7293#define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \
7294 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03007295#define COMMAND_MEM_ADDRESS_SHIFT 5
7296#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
7297#define AUTO_PWG_ENABLE (1 << 2)
7298#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
7299#define COMMAND_VALID (1 << 0)
7300
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307301#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007302#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7303#define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
7304 _MIPIC_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03007305#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
7306#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
7307
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307308#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007309#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7310#define MIPI_READ_DATA_RETURN(port, n) \
7311 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
Shashank Sharmaa2560a62014-06-02 18:07:48 +05307312 + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +03007313
Shashank Sharma4ad83e92014-06-02 18:07:47 +05307314#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
Jani Nikulae7d7cad2014-11-14 16:54:21 +02007315#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7316#define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \
7317 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +03007318#define READ_DATA_VALID(n) (1 << (n))
7319
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007320/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00007321#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7322#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02007323
Jesse Barnes585fb112008-07-29 11:54:06 -07007324#endif /* _I915_REG_H_ */