blob: b5dba4795f6f5441a3ac68aff606de49481f8279 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Jesse Barnes63eeaf32009-06-18 16:56:52 -070029#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010035#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define MAX_NOPID ((u32)~0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Keith Packard7c463582008-11-04 02:03:27 -080040/**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050047#define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Keith Packard7c463582008-11-04 02:03:27 -080054
55/** Interrupts that we mask and unmask at runtime. */
Zou Nan haid1b851f2010-05-21 09:08:57 +080056#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
Keith Packard7c463582008-11-04 02:03:27 -080057
Jesse Barnes79e53942008-11-07 14:24:08 -080058#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +010067void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050068ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080069{
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75}
76
Eric Anholt62fdfea2010-05-21 13:26:39 -070077void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050078ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080079{
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85}
86
87/* For display hotplug interrupt */
88void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050089ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080090{
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96}
97
98static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050099ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800100{
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106}
107
108void
Eric Anholted4cb412008-07-29 12:10:39 -0700109i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110{
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116}
117
Eric Anholt62fdfea2010-05-21 13:26:39 -0700118void
Eric Anholted4cb412008-07-29 12:10:39 -0700119i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120{
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126}
127
Keith Packard7c463582008-11-04 02:03:27 -0800128static inline u32
129i915_pipestat(int pipe)
130{
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
Andrew Morton9c84ba42008-12-01 13:14:08 -0800135 BUG();
Keith Packard7c463582008-11-04 02:03:27 -0800136}
137
138void
139i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140{
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149}
150
151void
152i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153{
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161}
162
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000163/**
Zhao Yakui01c66882009-10-28 05:10:00 +0000164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166void intel_enable_asle (struct drm_device *dev)
167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
Eric Anholtc619eed2010-01-28 16:45:52 -0800170 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500171 ironlake_enable_display_irq(dev_priv, DE_GSE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800172 else {
Zhao Yakui01c66882009-10-28 05:10:00 +0000173 i915_enable_pipestat(dev_priv, 1,
174 I915_LEGACY_BLC_EVENT_ENABLE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800175 if (IS_I965G(dev))
176 i915_enable_pipestat(dev_priv, 0,
177 I915_LEGACY_BLC_EVENT_ENABLE);
178 }
Zhao Yakui01c66882009-10-28 05:10:00 +0000179}
180
181/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190static int
191i915_pipe_enabled(struct drm_device *dev, int pipe)
192{
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
195
196 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
197 return 1;
198
199 return 0;
200}
201
Keith Packard42f52ef2008-10-18 19:39:29 -0700202/* Called from drm generic code, passed a 'crtc', which
203 * we use as a pipe index
204 */
205u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700206{
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208 unsigned long high_frame;
209 unsigned long low_frame;
210 u32 high1, high2, low, count;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700211
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700212 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
213 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
214
215 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800216 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
217 "pipe %d\n", pipe);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700218 return 0;
219 }
220
221 /*
222 * High & low register fields aren't synchronized, so make sure
223 * we get a low value that's stable across two reads of the high
224 * register.
225 */
226 do {
227 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228 PIPE_FRAME_HIGH_SHIFT);
229 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
230 PIPE_FRAME_LOW_SHIFT);
231 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
232 PIPE_FRAME_HIGH_SHIFT);
233 } while (high1 != high2);
234
235 count = (high1 << 8) | low;
236
237 return count;
238}
239
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800240u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
241{
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
244
245 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800246 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
247 "pipe %d\n", pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800248 return 0;
249 }
250
251 return I915_READ(reg);
252}
253
Jesse Barnes5ca58282009-03-31 14:11:15 -0700254/*
255 * Handle hotplug events outside the interrupt handler proper.
256 */
257static void i915_hotplug_work_func(struct work_struct *work)
258{
259 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
260 hotplug_work);
261 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700262 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wang5bf4c9c2010-03-30 14:39:26 +0800263 struct drm_encoder *encoder;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700264
Zhenyu Wang5bf4c9c2010-03-30 14:39:26 +0800265 if (mode_config->num_encoder) {
266 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
267 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700268
Eric Anholt21d40d32010-03-25 11:11:14 -0700269 if (intel_encoder->hot_plug)
270 (*intel_encoder->hot_plug) (intel_encoder);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700271 }
272 }
Jesse Barnes5ca58282009-03-31 14:11:15 -0700273 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000274 drm_helper_hpd_irq_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700275}
276
Jesse Barnesf97108d2010-01-29 11:27:07 -0800277static void i915_handle_rps_change(struct drm_device *dev)
278{
279 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000280 u32 busy_up, busy_down, max_avg, min_avg;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800281 u8 new_delay = dev_priv->cur_delay;
282
Jesse Barnes7648fa92010-05-20 14:28:11 -0700283 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000284 busy_up = I915_READ(RCPREVBSYTUPAVG);
285 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800286 max_avg = I915_READ(RCBMAXAVG);
287 min_avg = I915_READ(RCBMINAVG);
288
289 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000290 if (busy_up > max_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800291 if (dev_priv->cur_delay != dev_priv->max_delay)
292 new_delay = dev_priv->cur_delay - 1;
293 if (new_delay < dev_priv->max_delay)
294 new_delay = dev_priv->max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000295 } else if (busy_down < min_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800296 if (dev_priv->cur_delay != dev_priv->min_delay)
297 new_delay = dev_priv->cur_delay + 1;
298 if (new_delay > dev_priv->min_delay)
299 new_delay = dev_priv->min_delay;
300 }
301
Jesse Barnes7648fa92010-05-20 14:28:11 -0700302 if (ironlake_set_drps(dev, new_delay))
303 dev_priv->cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800304
305 return;
306}
307
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500308irqreturn_t ironlake_irq_handler(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800309{
310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
311 int ret = IRQ_NONE;
Dave Airlie3ff99162009-12-08 14:03:47 +1000312 u32 de_iir, gt_iir, de_ier, pch_iir;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800313 struct drm_i915_master_private *master_priv;
Zou Nan hai852835f2010-05-21 09:08:56 +0800314 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800315
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000316 /* disable master interrupt before clearing iir */
317 de_ier = I915_READ(DEIER);
318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
319 (void)I915_READ(DEIER);
320
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800321 de_iir = I915_READ(DEIIR);
322 gt_iir = I915_READ(GTIIR);
Zhenyu Wangc6501562009-11-03 18:57:21 +0000323 pch_iir = I915_READ(SDEIIR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800324
Zou Nan haic7c85102010-01-15 10:29:06 +0800325 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
326 goto done;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800327
Zou Nan haic7c85102010-01-15 10:29:06 +0800328 ret = IRQ_HANDLED;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800329
Zou Nan haic7c85102010-01-15 10:29:06 +0800330 if (dev->primary->master) {
331 master_priv = dev->primary->master->driver_priv;
332 if (master_priv->sarea_priv)
333 master_priv->sarea_priv->last_dispatch =
334 READ_BREADCRUMB(dev_priv);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800335 }
336
Jesse Barnese552eb72010-04-21 11:39:23 -0700337 if (gt_iir & GT_PIPE_NOTIFY) {
Zou Nan hai852835f2010-05-21 09:08:56 +0800338 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
339 render_ring->irq_gem_seqno = seqno;
Zou Nan haic7c85102010-01-15 10:29:06 +0800340 trace_i915_gem_request_complete(dev, seqno);
Zou Nan hai852835f2010-05-21 09:08:56 +0800341 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
Zou Nan haic7c85102010-01-15 10:29:06 +0800342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
344 }
Zou Nan haid1b851f2010-05-21 09:08:57 +0800345 if (gt_iir & GT_BSD_USER_INTERRUPT)
346 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
347
Zou Nan haic7c85102010-01-15 10:29:06 +0800348
349 if (de_iir & DE_GSE)
350 ironlake_opregion_gse_intr(dev);
351
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800352 if (de_iir & DE_PLANEA_FLIP_DONE) {
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800353 intel_prepare_page_flip(dev, 0);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800354 intel_finish_page_flip(dev, 0);
355 }
356
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800357 if (de_iir & DE_PLANEB_FLIP_DONE) {
358 intel_prepare_page_flip(dev, 1);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800359 intel_finish_page_flip(dev, 1);
360 }
Li Pengc062df62010-01-23 00:12:58 +0800361
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800362 if (de_iir & DE_PIPEA_VBLANK)
363 drm_handle_vblank(dev, 0);
364
365 if (de_iir & DE_PIPEB_VBLANK)
366 drm_handle_vblank(dev, 1);
367
Zou Nan haic7c85102010-01-15 10:29:06 +0800368 /* check event from PCH */
369 if ((de_iir & DE_PCH_EVENT) &&
370 (pch_iir & SDE_HOTPLUG_MASK)) {
371 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
372 }
373
Jesse Barnesf97108d2010-01-29 11:27:07 -0800374 if (de_iir & DE_PCU_EVENT) {
Jesse Barnes7648fa92010-05-20 14:28:11 -0700375 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
Jesse Barnesf97108d2010-01-29 11:27:07 -0800376 i915_handle_rps_change(dev);
377 }
378
Zou Nan haic7c85102010-01-15 10:29:06 +0800379 /* should clear PCH hotplug event before clear CPU irq */
380 I915_WRITE(SDEIIR, pch_iir);
381 I915_WRITE(GTIIR, gt_iir);
382 I915_WRITE(DEIIR, de_iir);
383
384done:
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000385 I915_WRITE(DEIER, de_ier);
386 (void)I915_READ(DEIER);
387
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800388 return ret;
389}
390
Jesse Barnes8a905232009-07-11 16:48:03 -0400391/**
392 * i915_error_work_func - do process context error handling work
393 * @work: work struct
394 *
395 * Fire an error uevent so userspace can see that a hang or error
396 * was detected.
397 */
398static void i915_error_work_func(struct work_struct *work)
399{
400 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
401 error_work);
402 struct drm_device *dev = dev_priv->dev;
Ben Gamarif316a422009-09-14 17:48:46 -0400403 char *error_event[] = { "ERROR=1", NULL };
404 char *reset_event[] = { "RESET=1", NULL };
405 char *reset_done_event[] = { "ERROR=0", NULL };
Jesse Barnes8a905232009-07-11 16:48:03 -0400406
Zhao Yakui44d98a62009-10-09 11:39:40 +0800407 DRM_DEBUG_DRIVER("generating error event\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400408 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -0400409
Ben Gamariba1234d2009-09-14 17:48:47 -0400410 if (atomic_read(&dev_priv->mm.wedged)) {
Ben Gamarif316a422009-09-14 17:48:46 -0400411 if (IS_I965G(dev)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800412 DRM_DEBUG_DRIVER("resetting chip\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400413 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
414 if (!i965_reset(dev, GDRST_RENDER)) {
Ben Gamariba1234d2009-09-14 17:48:47 -0400415 atomic_set(&dev_priv->mm.wedged, 0);
Ben Gamarif316a422009-09-14 17:48:46 -0400416 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
417 }
418 } else {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800419 DRM_DEBUG_DRIVER("reboot required\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400420 }
421 }
Jesse Barnes8a905232009-07-11 16:48:03 -0400422}
423
Chris Wilson9df30792010-02-18 10:24:56 +0000424static struct drm_i915_error_object *
425i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src)
427{
428 struct drm_i915_error_object *dst;
429 struct drm_i915_gem_object *src_priv;
430 int page, page_count;
431
432 if (src == NULL)
433 return NULL;
434
Daniel Vetter23010e42010-03-08 13:35:02 +0100435 src_priv = to_intel_bo(src);
Chris Wilson9df30792010-02-18 10:24:56 +0000436 if (src_priv->pages == NULL)
437 return NULL;
438
439 page_count = src->size / PAGE_SIZE;
440
441 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
442 if (dst == NULL)
443 return NULL;
444
445 for (page = 0; page < page_count; page++) {
446 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
Andrew Morton788885a2010-05-11 14:07:05 -0700447 unsigned long flags;
448
Chris Wilson9df30792010-02-18 10:24:56 +0000449 if (d == NULL)
450 goto unwind;
Andrew Morton788885a2010-05-11 14:07:05 -0700451 local_irq_save(flags);
452 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
Chris Wilson9df30792010-02-18 10:24:56 +0000453 memcpy(d, s, PAGE_SIZE);
Andrew Morton788885a2010-05-11 14:07:05 -0700454 kunmap_atomic(s, KM_IRQ0);
455 local_irq_restore(flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000456 dst->pages[page] = d;
457 }
458 dst->page_count = page_count;
459 dst->gtt_offset = src_priv->gtt_offset;
460
461 return dst;
462
463unwind:
464 while (page--)
465 kfree(dst->pages[page]);
466 kfree(dst);
467 return NULL;
468}
469
470static void
471i915_error_object_free(struct drm_i915_error_object *obj)
472{
473 int page;
474
475 if (obj == NULL)
476 return;
477
478 for (page = 0; page < obj->page_count; page++)
479 kfree(obj->pages[page]);
480
481 kfree(obj);
482}
483
484static void
485i915_error_state_free(struct drm_device *dev,
486 struct drm_i915_error_state *error)
487{
488 i915_error_object_free(error->batchbuffer[0]);
489 i915_error_object_free(error->batchbuffer[1]);
490 i915_error_object_free(error->ringbuffer);
491 kfree(error->active_bo);
492 kfree(error);
493}
494
495static u32
496i915_get_bbaddr(struct drm_device *dev, u32 *ring)
497{
498 u32 cmd;
499
500 if (IS_I830(dev) || IS_845G(dev))
501 cmd = MI_BATCH_BUFFER;
502 else if (IS_I965G(dev))
503 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
504 MI_BATCH_NON_SECURE_I965);
505 else
506 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
507
508 return ring[0] == cmd ? ring[1] : 0;
509}
510
511static u32
512i915_ringbuffer_last_batch(struct drm_device *dev)
513{
514 struct drm_i915_private *dev_priv = dev->dev_private;
515 u32 head, bbaddr;
516 u32 *ring;
517
518 /* Locate the current position in the ringbuffer and walk back
519 * to find the most recently dispatched batch buffer.
520 */
521 bbaddr = 0;
522 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
Eric Anholtd3301d82010-05-21 13:55:54 -0700523 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
Chris Wilson9df30792010-02-18 10:24:56 +0000524
Eric Anholtd3301d82010-05-21 13:55:54 -0700525 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
Chris Wilson9df30792010-02-18 10:24:56 +0000526 bbaddr = i915_get_bbaddr(dev, ring);
527 if (bbaddr)
528 break;
529 }
530
531 if (bbaddr == 0) {
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800532 ring = (u32 *)(dev_priv->render_ring.virtual_start
533 + dev_priv->render_ring.size);
Eric Anholtd3301d82010-05-21 13:55:54 -0700534 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
Chris Wilson9df30792010-02-18 10:24:56 +0000535 bbaddr = i915_get_bbaddr(dev, ring);
536 if (bbaddr)
537 break;
538 }
539 }
540
541 return bbaddr;
542}
543
Jesse Barnes8a905232009-07-11 16:48:03 -0400544/**
545 * i915_capture_error_state - capture an error record for later analysis
546 * @dev: drm device
547 *
548 * Should be called when an error is detected (either a hang or an error
549 * interrupt) to capture error state from the time of the error. Fills
550 * out a structure which becomes available in debugfs for user level tools
551 * to pick up.
552 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700553static void i915_capture_error_state(struct drm_device *dev)
554{
555 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9df30792010-02-18 10:24:56 +0000556 struct drm_i915_gem_object *obj_priv;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700557 struct drm_i915_error_state *error;
Chris Wilson9df30792010-02-18 10:24:56 +0000558 struct drm_gem_object *batchbuffer[2];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700559 unsigned long flags;
Chris Wilson9df30792010-02-18 10:24:56 +0000560 u32 bbaddr;
561 int count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700562
563 spin_lock_irqsave(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000564 error = dev_priv->first_error;
565 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
566 if (error)
567 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700568
569 error = kmalloc(sizeof(*error), GFP_ATOMIC);
570 if (!error) {
Chris Wilson9df30792010-02-18 10:24:56 +0000571 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
572 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700573 }
574
Zou Nan hai852835f2010-05-21 09:08:56 +0800575 error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700576 error->eir = I915_READ(EIR);
577 error->pgtbl_er = I915_READ(PGTBL_ER);
578 error->pipeastat = I915_READ(PIPEASTAT);
579 error->pipebstat = I915_READ(PIPEBSTAT);
580 error->instpm = I915_READ(INSTPM);
581 if (!IS_I965G(dev)) {
582 error->ipeir = I915_READ(IPEIR);
583 error->ipehr = I915_READ(IPEHR);
584 error->instdone = I915_READ(INSTDONE);
585 error->acthd = I915_READ(ACTHD);
Chris Wilson9df30792010-02-18 10:24:56 +0000586 error->bbaddr = 0;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700587 } else {
588 error->ipeir = I915_READ(IPEIR_I965);
589 error->ipehr = I915_READ(IPEHR_I965);
590 error->instdone = I915_READ(INSTDONE_I965);
591 error->instps = I915_READ(INSTPS);
592 error->instdone1 = I915_READ(INSTDONE1);
593 error->acthd = I915_READ(ACTHD_I965);
Chris Wilson9df30792010-02-18 10:24:56 +0000594 error->bbaddr = I915_READ64(BB_ADDR);
595 }
596
597 bbaddr = i915_ringbuffer_last_batch(dev);
598
599 /* Grab the current batchbuffer, most likely to have crashed. */
600 batchbuffer[0] = NULL;
601 batchbuffer[1] = NULL;
602 count = 0;
Zou Nan hai852835f2010-05-21 09:08:56 +0800603 list_for_each_entry(obj_priv,
604 &dev_priv->render_ring.active_list, list) {
605
Daniel Vettera8089e82010-04-09 19:05:09 +0000606 struct drm_gem_object *obj = &obj_priv->base;
Chris Wilson9df30792010-02-18 10:24:56 +0000607
608 if (batchbuffer[0] == NULL &&
609 bbaddr >= obj_priv->gtt_offset &&
610 bbaddr < obj_priv->gtt_offset + obj->size)
611 batchbuffer[0] = obj;
612
613 if (batchbuffer[1] == NULL &&
614 error->acthd >= obj_priv->gtt_offset &&
615 error->acthd < obj_priv->gtt_offset + obj->size &&
616 batchbuffer[0] != obj)
617 batchbuffer[1] = obj;
618
619 count++;
620 }
621
622 /* We need to copy these to an anonymous buffer as the simplest
623 * method to avoid being overwritten by userpace.
624 */
625 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
626 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
627
628 /* Record the ringbuffer */
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800629 error->ringbuffer = i915_error_object_create(dev,
630 dev_priv->render_ring.gem_object);
Chris Wilson9df30792010-02-18 10:24:56 +0000631
632 /* Record buffers on the active list. */
633 error->active_bo = NULL;
634 error->active_bo_count = 0;
635
636 if (count)
637 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
638 GFP_ATOMIC);
639
640 if (error->active_bo) {
641 int i = 0;
Zou Nan hai852835f2010-05-21 09:08:56 +0800642 list_for_each_entry(obj_priv,
643 &dev_priv->render_ring.active_list, list) {
Daniel Vettera8089e82010-04-09 19:05:09 +0000644 struct drm_gem_object *obj = &obj_priv->base;
Chris Wilson9df30792010-02-18 10:24:56 +0000645
646 error->active_bo[i].size = obj->size;
647 error->active_bo[i].name = obj->name;
648 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
649 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
650 error->active_bo[i].read_domains = obj->read_domains;
651 error->active_bo[i].write_domain = obj->write_domain;
652 error->active_bo[i].fence_reg = obj_priv->fence_reg;
653 error->active_bo[i].pinned = 0;
654 if (obj_priv->pin_count > 0)
655 error->active_bo[i].pinned = 1;
656 if (obj_priv->user_pin_count > 0)
657 error->active_bo[i].pinned = -1;
658 error->active_bo[i].tiling = obj_priv->tiling_mode;
659 error->active_bo[i].dirty = obj_priv->dirty;
660 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
661
662 if (++i == count)
663 break;
664 }
665 error->active_bo_count = i;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700666 }
667
Jesse Barnes8a905232009-07-11 16:48:03 -0400668 do_gettimeofday(&error->time);
669
Chris Wilson9df30792010-02-18 10:24:56 +0000670 spin_lock_irqsave(&dev_priv->error_lock, flags);
671 if (dev_priv->first_error == NULL) {
672 dev_priv->first_error = error;
673 error = NULL;
674 }
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700675 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000676
677 if (error)
678 i915_error_state_free(dev, error);
679}
680
681void i915_destroy_error_state(struct drm_device *dev)
682{
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct drm_i915_error_state *error;
685
686 spin_lock(&dev_priv->error_lock);
687 error = dev_priv->first_error;
688 dev_priv->first_error = NULL;
689 spin_unlock(&dev_priv->error_lock);
690
691 if (error)
692 i915_error_state_free(dev, error);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700693}
694
Jesse Barnes8a905232009-07-11 16:48:03 -0400695/**
696 * i915_handle_error - handle an error interrupt
697 * @dev: drm device
698 *
699 * Do some basic checking of regsiter state at error interrupt time and
700 * dump it to the syslog. Also call i915_capture_error_state() to make
701 * sure we get a record and make it available in debugfs. Fire a uevent
702 * so userspace knows something bad happened (should trigger collection
703 * of a ring dump etc.).
704 */
Ben Gamariba1234d2009-09-14 17:48:47 -0400705static void i915_handle_error(struct drm_device *dev, bool wedged)
Jesse Barnes8a905232009-07-11 16:48:03 -0400706{
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 u32 eir = I915_READ(EIR);
709 u32 pipea_stats = I915_READ(PIPEASTAT);
710 u32 pipeb_stats = I915_READ(PIPEBSTAT);
711
712 i915_capture_error_state(dev);
713
714 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
715 eir);
716
717 if (IS_G4X(dev)) {
718 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
719 u32 ipeir = I915_READ(IPEIR_I965);
720
721 printk(KERN_ERR " IPEIR: 0x%08x\n",
722 I915_READ(IPEIR_I965));
723 printk(KERN_ERR " IPEHR: 0x%08x\n",
724 I915_READ(IPEHR_I965));
725 printk(KERN_ERR " INSTDONE: 0x%08x\n",
726 I915_READ(INSTDONE_I965));
727 printk(KERN_ERR " INSTPS: 0x%08x\n",
728 I915_READ(INSTPS));
729 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
730 I915_READ(INSTDONE1));
731 printk(KERN_ERR " ACTHD: 0x%08x\n",
732 I915_READ(ACTHD_I965));
733 I915_WRITE(IPEIR_I965, ipeir);
734 (void)I915_READ(IPEIR_I965);
735 }
736 if (eir & GM45_ERROR_PAGE_TABLE) {
737 u32 pgtbl_err = I915_READ(PGTBL_ER);
738 printk(KERN_ERR "page table error\n");
739 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
740 pgtbl_err);
741 I915_WRITE(PGTBL_ER, pgtbl_err);
742 (void)I915_READ(PGTBL_ER);
743 }
744 }
745
746 if (IS_I9XX(dev)) {
747 if (eir & I915_ERROR_PAGE_TABLE) {
748 u32 pgtbl_err = I915_READ(PGTBL_ER);
749 printk(KERN_ERR "page table error\n");
750 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
751 pgtbl_err);
752 I915_WRITE(PGTBL_ER, pgtbl_err);
753 (void)I915_READ(PGTBL_ER);
754 }
755 }
756
757 if (eir & I915_ERROR_MEMORY_REFRESH) {
758 printk(KERN_ERR "memory refresh error\n");
759 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
760 pipea_stats);
761 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
762 pipeb_stats);
763 /* pipestat has already been acked */
764 }
765 if (eir & I915_ERROR_INSTRUCTION) {
766 printk(KERN_ERR "instruction error\n");
767 printk(KERN_ERR " INSTPM: 0x%08x\n",
768 I915_READ(INSTPM));
769 if (!IS_I965G(dev)) {
770 u32 ipeir = I915_READ(IPEIR);
771
772 printk(KERN_ERR " IPEIR: 0x%08x\n",
773 I915_READ(IPEIR));
774 printk(KERN_ERR " IPEHR: 0x%08x\n",
775 I915_READ(IPEHR));
776 printk(KERN_ERR " INSTDONE: 0x%08x\n",
777 I915_READ(INSTDONE));
778 printk(KERN_ERR " ACTHD: 0x%08x\n",
779 I915_READ(ACTHD));
780 I915_WRITE(IPEIR, ipeir);
781 (void)I915_READ(IPEIR);
782 } else {
783 u32 ipeir = I915_READ(IPEIR_I965);
784
785 printk(KERN_ERR " IPEIR: 0x%08x\n",
786 I915_READ(IPEIR_I965));
787 printk(KERN_ERR " IPEHR: 0x%08x\n",
788 I915_READ(IPEHR_I965));
789 printk(KERN_ERR " INSTDONE: 0x%08x\n",
790 I915_READ(INSTDONE_I965));
791 printk(KERN_ERR " INSTPS: 0x%08x\n",
792 I915_READ(INSTPS));
793 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
794 I915_READ(INSTDONE1));
795 printk(KERN_ERR " ACTHD: 0x%08x\n",
796 I915_READ(ACTHD_I965));
797 I915_WRITE(IPEIR_I965, ipeir);
798 (void)I915_READ(IPEIR_I965);
799 }
800 }
801
802 I915_WRITE(EIR, eir);
803 (void)I915_READ(EIR);
804 eir = I915_READ(EIR);
805 if (eir) {
806 /*
807 * some errors might have become stuck,
808 * mask them.
809 */
810 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
811 I915_WRITE(EMR, I915_READ(EMR) | eir);
812 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
813 }
814
Ben Gamariba1234d2009-09-14 17:48:47 -0400815 if (wedged) {
816 atomic_set(&dev_priv->mm.wedged, 1);
817
Ben Gamari11ed50e2009-09-14 17:48:45 -0400818 /*
819 * Wakeup waiting processes so they don't hang
820 */
Zou Nan hai852835f2010-05-21 09:08:56 +0800821 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400822 }
823
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700824 queue_work(dev_priv->wq, &dev_priv->error_work);
Jesse Barnes8a905232009-07-11 16:48:03 -0400825}
826
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
828{
Dave Airlie84b1fd12007-07-11 15:53:27 +1000829 struct drm_device *dev = (struct drm_device *) arg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000831 struct drm_i915_master_private *master_priv;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800832 u32 iir, new_iir;
833 u32 pipea_stats, pipeb_stats;
Keith Packard05eff842008-11-19 14:03:05 -0800834 u32 vblank_status;
835 u32 vblank_enable;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700836 int vblank = 0;
Keith Packard7c463582008-11-04 02:03:27 -0800837 unsigned long irqflags;
Keith Packard05eff842008-11-19 14:03:05 -0800838 int irq_received;
839 int ret = IRQ_NONE;
Zou Nan hai852835f2010-05-21 09:08:56 +0800840 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000841
Eric Anholt630681d2008-10-06 15:14:12 -0700842 atomic_inc(&dev_priv->irq_received);
843
Eric Anholtbad720f2009-10-22 16:11:14 -0700844 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500845 return ironlake_irq_handler(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800846
Eric Anholted4cb412008-07-29 12:10:39 -0700847 iir = I915_READ(IIR);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000848
Keith Packard05eff842008-11-19 14:03:05 -0800849 if (IS_I965G(dev)) {
850 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
851 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
852 } else {
853 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
854 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
855 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856
Keith Packard05eff842008-11-19 14:03:05 -0800857 for (;;) {
858 irq_received = iir != 0;
859
860 /* Can't rely on pipestat interrupt bit in iir as it might
861 * have been cleared after the pipestat interrupt was received.
862 * It doesn't set the bit in iir again, but it still produces
863 * interrupts (for non-MSI).
864 */
865 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
866 pipea_stats = I915_READ(PIPEASTAT);
867 pipeb_stats = I915_READ(PIPEBSTAT);
Jesse Barnes79e53942008-11-07 14:24:08 -0800868
Jesse Barnes8a905232009-07-11 16:48:03 -0400869 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Ben Gamariba1234d2009-09-14 17:48:47 -0400870 i915_handle_error(dev, false);
Jesse Barnes8a905232009-07-11 16:48:03 -0400871
Eric Anholtcdfbc412008-11-04 15:50:30 -0800872 /*
873 * Clear the PIPE(A|B)STAT regs before the IIR
874 */
Keith Packard05eff842008-11-19 14:03:05 -0800875 if (pipea_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800876 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800877 DRM_DEBUG_DRIVER("pipe a underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800878 I915_WRITE(PIPEASTAT, pipea_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800879 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800880 }
Keith Packard7c463582008-11-04 02:03:27 -0800881
Keith Packard05eff842008-11-19 14:03:05 -0800882 if (pipeb_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800883 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800884 DRM_DEBUG_DRIVER("pipe b underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800885 I915_WRITE(PIPEBSTAT, pipeb_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800886 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800887 }
Keith Packard05eff842008-11-19 14:03:05 -0800888 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
889
890 if (!irq_received)
891 break;
892
893 ret = IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894
Jesse Barnes5ca58282009-03-31 14:11:15 -0700895 /* Consume port. Then clear IIR or we'll miss events */
896 if ((I915_HAS_HOTPLUG(dev)) &&
897 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
898 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
899
Zhao Yakui44d98a62009-10-09 11:39:40 +0800900 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
Jesse Barnes5ca58282009-03-31 14:11:15 -0700901 hotplug_status);
902 if (hotplug_status & dev_priv->hotplug_supported_mask)
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700903 queue_work(dev_priv->wq,
904 &dev_priv->hotplug_work);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700905
906 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
907 I915_READ(PORT_HOTPLUG_STAT);
908 }
909
Eric Anholtcdfbc412008-11-04 15:50:30 -0800910 I915_WRITE(IIR, iir);
911 new_iir = I915_READ(IIR); /* Flush posted writes */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100912
Dave Airlie7c1c2872008-11-28 14:22:24 +1000913 if (dev->primary->master) {
914 master_priv = dev->primary->master->driver_priv;
915 if (master_priv->sarea_priv)
916 master_priv->sarea_priv->last_dispatch =
917 READ_BREADCRUMB(dev_priv);
918 }
Keith Packard7c463582008-11-04 02:03:27 -0800919
Eric Anholtcdfbc412008-11-04 15:50:30 -0800920 if (iir & I915_USER_INTERRUPT) {
Zou Nan hai852835f2010-05-21 09:08:56 +0800921 u32 seqno =
922 render_ring->get_gem_seqno(dev, render_ring);
923 render_ring->irq_gem_seqno = seqno;
Chris Wilson1c5d22f2009-08-25 11:15:50 +0100924 trace_i915_gem_request_complete(dev, seqno);
Zou Nan hai852835f2010-05-21 09:08:56 +0800925 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
Ben Gamarif65d9422009-09-14 17:48:44 -0400926 dev_priv->hangcheck_count = 0;
927 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800928 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700929
Zou Nan haid1b851f2010-05-21 09:08:57 +0800930 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
931 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
932
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500933 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
934 intel_prepare_page_flip(dev, 0);
935
936 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
937 intel_prepare_page_flip(dev, 1);
938
Keith Packard05eff842008-11-19 14:03:05 -0800939 if (pipea_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800940 vblank++;
941 drm_handle_vblank(dev, 0);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500942 intel_finish_page_flip(dev, 0);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800943 }
Eric Anholt673a3942008-07-30 12:06:12 -0700944
Keith Packard05eff842008-11-19 14:03:05 -0800945 if (pipeb_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800946 vblank++;
947 drm_handle_vblank(dev, 1);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500948 intel_finish_page_flip(dev, 1);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800949 }
Keith Packard7c463582008-11-04 02:03:27 -0800950
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800951 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
952 (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
Eric Anholtcdfbc412008-11-04 15:50:30 -0800953 (iir & I915_ASLE_INTERRUPT))
954 opregion_asle_intr(dev);
Keith Packard7c463582008-11-04 02:03:27 -0800955
Eric Anholtcdfbc412008-11-04 15:50:30 -0800956 /* With MSI, interrupts are only generated when iir
957 * transitions from zero to nonzero. If another bit got
958 * set while we were handling the existing iir bits, then
959 * we would never get another interrupt.
960 *
961 * This is fine on non-MSI as well, as if we hit this path
962 * we avoid exiting the interrupt handler only to generate
963 * another one.
964 *
965 * Note that for MSI this could cause a stray interrupt report
966 * if an interrupt landed in the time between writing IIR and
967 * the posting read. This should be rare enough to never
968 * trigger the 99% of 100,000 interrupts test for disabling
969 * stray interrupts.
970 */
971 iir = new_iir;
Keith Packard05eff842008-11-19 14:03:05 -0800972 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700973
Keith Packard05eff842008-11-19 14:03:05 -0800974 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975}
976
Dave Airlieaf6061a2008-05-07 12:15:39 +1000977static int i915_emit_irq(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978{
979 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000980 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981
982 i915_kernel_lost_context(dev);
983
Zhao Yakui44d98a62009-10-09 11:39:40 +0800984 DRM_DEBUG_DRIVER("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400986 dev_priv->counter++;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000987 if (dev_priv->counter > 0x7FFFFFFFUL)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400988 dev_priv->counter = 1;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000989 if (master_priv->sarea_priv)
990 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000991
Keith Packard0baf8232008-11-08 11:44:14 +1000992 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -0700993 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +1000994 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Alan Hourihanec29b6692006-08-12 16:29:24 +1000995 OUT_RING(dev_priv->counter);
Jesse Barnes585fb112008-07-29 11:54:06 -0700996 OUT_RING(MI_USER_INTERRUPT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 ADVANCE_LP_RING();
Dave Airliebc5f4522007-11-05 12:50:58 +1000998
Alan Hourihanec29b6692006-08-12 16:29:24 +1000999 return dev_priv->counter;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000}
1001
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001002void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1003{
1004 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001005 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001006
1007 if (dev_priv->trace_irq_seqno == 0)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001008 render_ring->user_irq_get(dev, render_ring);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001009
1010 dev_priv->trace_irq_seqno = seqno;
1011}
1012
Dave Airlie84b1fd12007-07-11 15:53:27 +10001013static int i915_wait_irq(struct drm_device * dev, int irq_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014{
1015 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001016 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 int ret = 0;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001018 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019
Zhao Yakui44d98a62009-10-09 11:39:40 +08001020 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 READ_BREADCRUMB(dev_priv));
1022
Eric Anholted4cb412008-07-29 12:10:39 -07001023 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10001024 if (master_priv->sarea_priv)
1025 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026 return 0;
Eric Anholted4cb412008-07-29 12:10:39 -07001027 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028
Dave Airlie7c1c2872008-11-28 14:22:24 +10001029 if (master_priv->sarea_priv)
1030 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001032 render_ring->user_irq_get(dev, render_ring);
Zou Nan hai852835f2010-05-21 09:08:56 +08001033 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 READ_BREADCRUMB(dev_priv) >= irq_nr);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001035 render_ring->user_irq_put(dev, render_ring);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036
Eric Anholt20caafa2007-08-25 19:22:43 +10001037 if (ret == -EBUSY) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001038 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1040 }
1041
Dave Airlieaf6061a2008-05-07 12:15:39 +10001042 return ret;
1043}
1044
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045/* Needs the lock as it touches the ring.
1046 */
Eric Anholtc153f452007-09-03 12:06:45 +10001047int i915_irq_emit(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001051 drm_i915_irq_emit_t *emit = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 int result;
1053
Eric Anholtd3301d82010-05-21 13:55:54 -07001054 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001055 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001056 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 }
Eric Anholt299eb932009-02-24 22:14:12 -08001058
1059 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1060
Eric Anholt546b0972008-09-01 16:45:29 -07001061 mutex_lock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062 result = i915_emit_irq(dev);
Eric Anholt546b0972008-09-01 16:45:29 -07001063 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064
Eric Anholtc153f452007-09-03 12:06:45 +10001065 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001067 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 }
1069
1070 return 0;
1071}
1072
1073/* Doesn't need the hardware lock.
1074 */
Eric Anholtc153f452007-09-03 12:06:45 +10001075int i915_irq_wait(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001079 drm_i915_irq_wait_t *irqwait = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080
1081 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001082 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001083 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 }
1085
Eric Anholtc153f452007-09-03 12:06:45 +10001086 return i915_wait_irq(dev, irqwait->irq_seq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087}
1088
Keith Packard42f52ef2008-10-18 19:39:29 -07001089/* Called from drm generic code, passed 'crtc' which
1090 * we use as a pipe index
1091 */
1092int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001093{
1094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001095 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001096 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1097 u32 pipeconf;
1098
1099 pipeconf = I915_READ(pipeconf_reg);
1100 if (!(pipeconf & PIPEACONF_ENABLE))
1101 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001102
Keith Packarde9d21d72008-10-16 11:31:38 -07001103 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001104 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001105 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1106 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1107 else if (IS_I965G(dev))
Keith Packard7c463582008-11-04 02:03:27 -08001108 i915_enable_pipestat(dev_priv, pipe,
1109 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001110 else
Keith Packard7c463582008-11-04 02:03:27 -08001111 i915_enable_pipestat(dev_priv, pipe,
1112 PIPE_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001113 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001114 return 0;
1115}
1116
Keith Packard42f52ef2008-10-18 19:39:29 -07001117/* Called from drm generic code, passed 'crtc' which
1118 * we use as a pipe index
1119 */
1120void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001121{
1122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001123 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001124
Keith Packarde9d21d72008-10-16 11:31:38 -07001125 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001126 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001127 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1128 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1129 else
1130 i915_disable_pipestat(dev_priv, pipe,
1131 PIPE_VBLANK_INTERRUPT_ENABLE |
1132 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001133 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001134}
1135
Jesse Barnes79e53942008-11-07 14:24:08 -08001136void i915_enable_interrupt (struct drm_device *dev)
1137{
1138 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wange170b032009-06-05 15:38:40 +08001139
Eric Anholtbad720f2009-10-22 16:11:14 -07001140 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wange170b032009-06-05 15:38:40 +08001141 opregion_enable_asle(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001142 dev_priv->irq_enabled = 1;
1143}
1144
1145
Dave Airlie702880f2006-06-24 17:07:34 +10001146/* Set the vblank monitor pipe
1147 */
Eric Anholtc153f452007-09-03 12:06:45 +10001148int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1149 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001150{
Dave Airlie702880f2006-06-24 17:07:34 +10001151 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie702880f2006-06-24 17:07:34 +10001152
1153 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001154 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001155 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001156 }
1157
=?utf-8?q?Michel_D=C3=A4nzer?=5b516942006-10-25 00:08:23 +10001158 return 0;
Dave Airlie702880f2006-06-24 17:07:34 +10001159}
1160
Eric Anholtc153f452007-09-03 12:06:45 +10001161int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1162 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001163{
Dave Airlie702880f2006-06-24 17:07:34 +10001164 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001165 drm_i915_vblank_pipe_t *pipe = data;
Dave Airlie702880f2006-06-24 17:07:34 +10001166
1167 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001168 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001169 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001170 }
1171
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001172 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Eric Anholtc153f452007-09-03 12:06:45 +10001173
Dave Airlie702880f2006-06-24 17:07:34 +10001174 return 0;
1175}
1176
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001177/**
1178 * Schedule buffer swap at given vertical blank.
1179 */
Eric Anholtc153f452007-09-03 12:06:45 +10001180int i915_vblank_swap(struct drm_device *dev, void *data,
1181 struct drm_file *file_priv)
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001182{
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001183 /* The delayed swap mechanism was fundamentally racy, and has been
1184 * removed. The model was that the client requested a delayed flip/swap
1185 * from the kernel, then waited for vblank before continuing to perform
1186 * rendering. The problem was that the kernel might wake the client
1187 * up before it dispatched the vblank swap (since the lock has to be
1188 * held while touching the ringbuffer), in which case the client would
1189 * clear and start the next frame before the swap occurred, and
1190 * flicker would occur in addition to likely missing the vblank.
1191 *
1192 * In the absence of this ioctl, userland falls back to a correct path
1193 * of waiting for a vblank, then dispatching the swap on its own.
1194 * Context switching to userland and back is plenty fast enough for
1195 * meeting the requirements of vblank swapping.
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001196 */
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001197 return -EINVAL;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001198}
1199
Zou Nan hai852835f2010-05-21 09:08:56 +08001200struct drm_i915_gem_request *
1201i915_get_tail_request(struct drm_device *dev)
1202{
Ben Gamarif65d9422009-09-14 17:48:44 -04001203 drm_i915_private_t *dev_priv = dev->dev_private;
Zou Nan hai852835f2010-05-21 09:08:56 +08001204 return list_entry(dev_priv->render_ring.request_list.prev,
1205 struct drm_i915_gem_request, list);
Ben Gamarif65d9422009-09-14 17:48:44 -04001206}
1207
1208/**
1209 * This is called when the chip hasn't reported back with completed
1210 * batchbuffers in a long time. The first time this is called we simply record
1211 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1212 * again, we assume the chip is wedged and try to fix it.
1213 */
1214void i915_hangcheck_elapsed(unsigned long data)
1215{
1216 struct drm_device *dev = (struct drm_device *)data;
1217 drm_i915_private_t *dev_priv = dev->dev_private;
1218 uint32_t acthd;
Eric Anholtb9201c12010-01-08 14:25:16 -08001219
1220 /* No reset support on this chip yet. */
1221 if (IS_GEN6(dev))
1222 return;
1223
Ben Gamarif65d9422009-09-14 17:48:44 -04001224 if (!IS_I965G(dev))
1225 acthd = I915_READ(ACTHD);
1226 else
1227 acthd = I915_READ(ACTHD_I965);
1228
1229 /* If all work is done then ACTHD clearly hasn't advanced. */
Zou Nan hai852835f2010-05-21 09:08:56 +08001230 if (list_empty(&dev_priv->render_ring.request_list) ||
1231 i915_seqno_passed(i915_get_gem_seqno(dev,
1232 &dev_priv->render_ring),
1233 i915_get_tail_request(dev)->seqno)) {
Ben Gamarif65d9422009-09-14 17:48:44 -04001234 dev_priv->hangcheck_count = 0;
1235 return;
1236 }
1237
1238 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1239 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04001240 i915_handle_error(dev, true);
Ben Gamarif65d9422009-09-14 17:48:44 -04001241 return;
1242 }
1243
1244 /* Reset timer case chip hangs without another request being added */
1245 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1246
1247 if (acthd != dev_priv->last_acthd)
1248 dev_priv->hangcheck_count = 0;
1249 else
1250 dev_priv->hangcheck_count++;
1251
1252 dev_priv->last_acthd = acthd;
1253}
1254
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255/* drm_dma.h hooks
1256*/
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001257static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001258{
1259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1260
1261 I915_WRITE(HWSTAM, 0xeffe);
1262
1263 /* XXX hotplug from PCH */
1264
1265 I915_WRITE(DEIMR, 0xffffffff);
1266 I915_WRITE(DEIER, 0x0);
1267 (void) I915_READ(DEIER);
1268
1269 /* and GT */
1270 I915_WRITE(GTIMR, 0xffffffff);
1271 I915_WRITE(GTIER, 0x0);
1272 (void) I915_READ(GTIER);
Zhenyu Wangc6501562009-11-03 18:57:21 +00001273
1274 /* south display irq */
1275 I915_WRITE(SDEIMR, 0xffffffff);
1276 I915_WRITE(SDEIER, 0x0);
1277 (void) I915_READ(SDEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001278}
1279
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001280static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001281{
1282 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1283 /* enable kind of interrupts always enabled */
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001284 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1285 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
Zou Nan haid1b851f2010-05-21 09:08:57 +08001286 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
Zhenyu Wangc6501562009-11-03 18:57:21 +00001287 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1288 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001289
1290 dev_priv->irq_mask_reg = ~display_mask;
Li Peng643ced92010-01-28 01:05:09 +08001291 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001292
1293 /* should always can generate irq */
1294 I915_WRITE(DEIIR, I915_READ(DEIIR));
1295 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1296 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1297 (void) I915_READ(DEIER);
1298
1299 /* user interrupt should be enabled, but masked initial */
Zou Nan hai852835f2010-05-21 09:08:56 +08001300 dev_priv->gt_irq_mask_reg = ~render_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001301 dev_priv->gt_irq_enable_reg = render_mask;
1302
1303 I915_WRITE(GTIIR, I915_READ(GTIIR));
1304 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1305 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1306 (void) I915_READ(GTIER);
1307
Zhenyu Wangc6501562009-11-03 18:57:21 +00001308 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1309 dev_priv->pch_irq_enable_reg = hotplug_mask;
1310
1311 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1312 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1313 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1314 (void) I915_READ(SDEIER);
1315
Jesse Barnesf97108d2010-01-29 11:27:07 -08001316 if (IS_IRONLAKE_M(dev)) {
1317 /* Clear & enable PCU event interrupts */
1318 I915_WRITE(DEIIR, DE_PCU_EVENT);
1319 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1320 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1321 }
1322
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001323 return 0;
1324}
1325
Dave Airlie84b1fd12007-07-11 15:53:27 +10001326void i915_driver_irq_preinstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327{
1328 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1329
Jesse Barnes79e53942008-11-07 14:24:08 -08001330 atomic_set(&dev_priv->irq_received, 0);
1331
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001332 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Jesse Barnes8a905232009-07-11 16:48:03 -04001333 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001334
Eric Anholtbad720f2009-10-22 16:11:14 -07001335 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001336 ironlake_irq_preinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001337 return;
1338 }
1339
Jesse Barnes5ca58282009-03-31 14:11:15 -07001340 if (I915_HAS_HOTPLUG(dev)) {
1341 I915_WRITE(PORT_HOTPLUG_EN, 0);
1342 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1343 }
1344
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001345 I915_WRITE(HWSTAM, 0xeffe);
Keith Packard7c463582008-11-04 02:03:27 -08001346 I915_WRITE(PIPEASTAT, 0);
1347 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001348 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001349 I915_WRITE(IER, 0x0);
Keith Packard7c463582008-11-04 02:03:27 -08001350 (void) I915_READ(IER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351}
1352
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001353/*
1354 * Must be called after intel_modeset_init or hotplug interrupts won't be
1355 * enabled correctly.
1356 */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001357int i915_driver_irq_postinstall(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358{
1359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes5ca58282009-03-31 14:11:15 -07001360 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001361 u32 error_mask;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001362
Zou Nan hai852835f2010-05-21 09:08:56 +08001363 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001364
Zou Nan haid1b851f2010-05-21 09:08:57 +08001365 if (HAS_BSD(dev))
1366 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1367
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001368 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001369
Eric Anholtbad720f2009-10-22 16:11:14 -07001370 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001371 return ironlake_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001372
Keith Packard7c463582008-11-04 02:03:27 -08001373 /* Unmask the interrupts that we always want on. */
1374 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001375
Keith Packard7c463582008-11-04 02:03:27 -08001376 dev_priv->pipestat[0] = 0;
1377 dev_priv->pipestat[1] = 0;
1378
Jesse Barnes5ca58282009-03-31 14:11:15 -07001379 if (I915_HAS_HOTPLUG(dev)) {
1380 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1381
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001382 /* Note HDMI and DP share bits */
1383 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1384 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1385 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1386 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1387 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1388 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1389 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1390 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1391 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1392 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1393 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1394 hotplug_en |= CRT_HOTPLUG_INT_EN;
1395 /* Ignore TV since it's buggy */
1396
Jesse Barnes5ca58282009-03-31 14:11:15 -07001397 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1398
Jesse Barnes5ca58282009-03-31 14:11:15 -07001399 /* Enable in IER... */
1400 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1401 /* and unmask in IMR */
1402 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1403 }
1404
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001405 /*
1406 * Enable some error detection, note the instruction error mask
1407 * bit is reserved, so we leave it masked.
1408 */
1409 if (IS_G4X(dev)) {
1410 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1411 GM45_ERROR_MEM_PRIV |
1412 GM45_ERROR_CP_PRIV |
1413 I915_ERROR_MEMORY_REFRESH);
1414 } else {
1415 error_mask = ~(I915_ERROR_PAGE_TABLE |
1416 I915_ERROR_MEMORY_REFRESH);
1417 }
1418 I915_WRITE(EMR, error_mask);
1419
Keith Packard7c463582008-11-04 02:03:27 -08001420 /* Disable pipe interrupt enables, clear pending pipe status */
1421 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1422 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1423 /* Clear pending interrupt status */
1424 I915_WRITE(IIR, I915_READ(IIR));
1425
Jesse Barnes5ca58282009-03-31 14:11:15 -07001426 I915_WRITE(IER, enable_mask);
Keith Packard7c463582008-11-04 02:03:27 -08001427 I915_WRITE(IMR, dev_priv->irq_mask_reg);
Eric Anholted4cb412008-07-29 12:10:39 -07001428 (void) I915_READ(IER);
1429
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001430 opregion_enable_asle(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001431
1432 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433}
1434
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001435static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001436{
1437 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1438 I915_WRITE(HWSTAM, 0xffffffff);
1439
1440 I915_WRITE(DEIMR, 0xffffffff);
1441 I915_WRITE(DEIER, 0x0);
1442 I915_WRITE(DEIIR, I915_READ(DEIIR));
1443
1444 I915_WRITE(GTIMR, 0xffffffff);
1445 I915_WRITE(GTIER, 0x0);
1446 I915_WRITE(GTIIR, I915_READ(GTIIR));
1447}
1448
Dave Airlie84b1fd12007-07-11 15:53:27 +10001449void i915_driver_irq_uninstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450{
1451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie91e37382006-02-18 15:17:04 +11001452
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453 if (!dev_priv)
1454 return;
1455
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001456 dev_priv->vblank_pipe = 0;
1457
Eric Anholtbad720f2009-10-22 16:11:14 -07001458 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001459 ironlake_irq_uninstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001460 return;
1461 }
1462
Jesse Barnes5ca58282009-03-31 14:11:15 -07001463 if (I915_HAS_HOTPLUG(dev)) {
1464 I915_WRITE(PORT_HOTPLUG_EN, 0);
1465 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1466 }
1467
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001468 I915_WRITE(HWSTAM, 0xffffffff);
Keith Packard7c463582008-11-04 02:03:27 -08001469 I915_WRITE(PIPEASTAT, 0);
1470 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001471 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001472 I915_WRITE(IER, 0x0);
Dave Airlie91e37382006-02-18 15:17:04 +11001473
Keith Packard7c463582008-11-04 02:03:27 -08001474 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1475 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1476 I915_WRITE(IIR, I915_READ(IIR));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477}