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Brett Russ20f733e2005-09-01 18:26:17 -04001/*
2 * sata_mv.c - Marvell SATA support
3 *
Mark Lord40f21b12009-03-10 18:51:04 -04004 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
Jeff Garzik8b260242005-11-12 12:32:50 -05005 * Copyright 2005: EMC Corporation, all rights reserved.
Jeff Garzike2b1be52005-11-18 14:04:23 -05006 * Copyright 2005 Red Hat, Inc. All rights reserved.
Brett Russ20f733e2005-09-01 18:26:17 -04007 *
Mark Lord40f21b12009-03-10 18:51:04 -04008 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
Brett Russ20f733e2005-09-01 18:26:17 -040011 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
Jeff Garzik4a05e202007-05-24 23:40:15 -040028/*
Mark Lord85afb932008-04-19 14:54:41 -040029 * sata_mv TODO list:
30 *
Mark Lord85afb932008-04-19 14:54:41 -040031 * --> Develop a low-power-consumption strategy, and implement it.
32 *
Mark Lord2b748a02009-03-10 22:01:17 -040033 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
Mark Lord85afb932008-04-19 14:54:41 -040034 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
Jeff Garzik4a05e202007-05-24 23:40:15 -040042
Mark Lord65ad7fef2009-04-06 15:24:14 -040043/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
Brett Russ20f733e2005-09-01 18:26:17 -040052#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
Andrew Morton8d8b6002008-02-04 23:43:44 -080059#include <linux/dmapool.h>
Brett Russ20f733e2005-09-01 18:26:17 -040060#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050061#include <linux/device.h>
Saeed Bisharaf351b2d2008-02-01 18:08:03 -050062#include <linux/platform_device.h>
63#include <linux/ata_platform.h>
Lennert Buytenhek15a32632008-03-27 14:51:39 -040064#include <linux/mbus.h>
Mark Lordc46938c2008-05-02 14:02:28 -040065#include <linux/bitops.h>
Brett Russ20f733e2005-09-01 18:26:17 -040066#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050067#include <scsi/scsi_cmnd.h>
Jeff Garzik6c087722007-10-12 00:16:23 -040068#include <scsi/scsi_device.h>
Brett Russ20f733e2005-09-01 18:26:17 -040069#include <linux/libata.h>
Brett Russ20f733e2005-09-01 18:26:17 -040070
71#define DRV_NAME "sata_mv"
Mark Lordcae5a292009-04-06 16:43:45 -040072#define DRV_VERSION "1.28"
Brett Russ20f733e2005-09-01 18:26:17 -040073
Mark Lord40f21b12009-03-10 18:51:04 -040074/*
75 * module options
76 */
77
78static int msi;
79#ifdef CONFIG_PCI
80module_param(msi, int, S_IRUGO);
81MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
82#endif
83
Mark Lord2b748a02009-03-10 22:01:17 -040084static int irq_coalescing_io_count;
85module_param(irq_coalescing_io_count, int, S_IRUGO);
86MODULE_PARM_DESC(irq_coalescing_io_count,
87 "IRQ coalescing I/O count threshold (0..255)");
88
89static int irq_coalescing_usecs;
90module_param(irq_coalescing_usecs, int, S_IRUGO);
91MODULE_PARM_DESC(irq_coalescing_usecs,
92 "IRQ coalescing time threshold in usecs");
93
Brett Russ20f733e2005-09-01 18:26:17 -040094enum {
95 /* BAR's are enumerated in terms of pci_resource_start() terms */
96 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
97 MV_IO_BAR = 2, /* offset 0x18: IO space */
98 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
99
100 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
101 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
102
Mark Lord2b748a02009-03-10 22:01:17 -0400103 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
104 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
105 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
106 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
107
Brett Russ20f733e2005-09-01 18:26:17 -0400108 MV_PCI_REG_BASE = 0,
Mark Lord615ab952006-05-19 16:24:56 -0400109
Mark Lord2b748a02009-03-10 22:01:17 -0400110 /*
111 * Per-chip ("all ports") interrupt coalescing feature.
112 * This is only for GEN_II / GEN_IIE hardware.
113 *
114 * Coalescing defers the interrupt until either the IO_THRESHOLD
115 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
116 */
Mark Lordcae5a292009-04-06 16:43:45 -0400117 COAL_REG_BASE = 0x18000,
118 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
Mark Lord2b748a02009-03-10 22:01:17 -0400119 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
120
Mark Lordcae5a292009-04-06 16:43:45 -0400121 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
122 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
Mark Lord2b748a02009-03-10 22:01:17 -0400123
124 /*
125 * Registers for the (unused here) transaction coalescing feature:
126 */
Mark Lordcae5a292009-04-06 16:43:45 -0400127 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
128 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
Mark Lord2b748a02009-03-10 22:01:17 -0400129
Mark Lordcae5a292009-04-06 16:43:45 -0400130 SATAHC0_REG_BASE = 0x20000,
131 FLASH_CTL = 0x1046c,
132 GPIO_PORT_CTL = 0x104f0,
133 RESET_CFG = 0x180d8,
Brett Russ20f733e2005-09-01 18:26:17 -0400134
135 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
136 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
137 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
138 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
139
Brett Russ31961942005-09-30 01:36:00 -0400140 MV_MAX_Q_DEPTH = 32,
141 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
142
143 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
144 * CRPB needs alignment on a 256B boundary. Size == 256B
Brett Russ31961942005-09-30 01:36:00 -0400145 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
146 */
147 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
148 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
Mark Lordda2fa9b2008-01-26 18:32:45 -0500149 MV_MAX_SG_CT = 256,
Brett Russ31961942005-09-30 01:36:00 -0400150 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
Brett Russ31961942005-09-30 01:36:00 -0400151
Mark Lord352fab72008-04-19 14:43:42 -0400152 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
Brett Russ20f733e2005-09-01 18:26:17 -0400153 MV_PORT_HC_SHIFT = 2,
Mark Lord352fab72008-04-19 14:43:42 -0400154 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
155 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
156 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
Brett Russ20f733e2005-09-01 18:26:17 -0400157
158 /* Host Flags */
159 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100160
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400161 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Mark Lord91b1a842009-01-30 18:46:39 -0500162 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
Mark Lordad3aef52008-05-14 09:21:43 -0400163
Mark Lord91b1a842009-01-30 18:46:39 -0500164 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
Brett Russ20f733e2005-09-01 18:26:17 -0400165
Mark Lord40f21b12009-03-10 18:51:04 -0400166 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
167 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
Mark Lord91b1a842009-01-30 18:46:39 -0500168
169 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
Mark Lordad3aef52008-05-14 09:21:43 -0400170
Brett Russ31961942005-09-30 01:36:00 -0400171 CRQB_FLAG_READ = (1 << 0),
172 CRQB_TAG_SHIFT = 1,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400173 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
Mark Lorde12bef52008-03-31 19:33:56 -0400174 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400175 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
Brett Russ31961942005-09-30 01:36:00 -0400176 CRQB_CMD_ADDR_SHIFT = 8,
177 CRQB_CMD_CS = (0x2 << 11),
178 CRQB_CMD_LAST = (1 << 15),
179
180 CRPB_FLAG_STATUS_SHIFT = 8,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400181 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
182 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
Brett Russ31961942005-09-30 01:36:00 -0400183
184 EPRD_FLAG_END_OF_TBL = (1 << 31),
185
Brett Russ20f733e2005-09-01 18:26:17 -0400186 /* PCI interface registers */
187
Mark Lordcae5a292009-04-06 16:43:45 -0400188 MV_PCI_COMMAND = 0xc00,
189 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
190 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
Brett Russ31961942005-09-30 01:36:00 -0400191
Mark Lordcae5a292009-04-06 16:43:45 -0400192 PCI_MAIN_CMD_STS = 0xd30,
Brett Russ20f733e2005-09-01 18:26:17 -0400193 STOP_PCI_MASTER = (1 << 2),
194 PCI_MASTER_EMPTY = (1 << 3),
195 GLOB_SFT_RST = (1 << 4),
196
Mark Lordcae5a292009-04-06 16:43:45 -0400197 MV_PCI_MODE = 0xd00,
Mark Lord8e7decd2008-05-02 02:07:51 -0400198 MV_PCI_MODE_MASK = 0x30,
199
Jeff Garzik522479f2005-11-12 22:14:02 -0500200 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
201 MV_PCI_DISC_TIMER = 0xd04,
202 MV_PCI_MSI_TRIGGER = 0xc38,
203 MV_PCI_SERR_MASK = 0xc28,
Mark Lordcae5a292009-04-06 16:43:45 -0400204 MV_PCI_XBAR_TMOUT = 0x1d04,
Jeff Garzik522479f2005-11-12 22:14:02 -0500205 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
206 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
207 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
208 MV_PCI_ERR_COMMAND = 0x1d50,
209
Mark Lordcae5a292009-04-06 16:43:45 -0400210 PCI_IRQ_CAUSE = 0x1d58,
211 PCI_IRQ_MASK = 0x1d5c,
Brett Russ20f733e2005-09-01 18:26:17 -0400212 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
213
Mark Lordcae5a292009-04-06 16:43:45 -0400214 PCIE_IRQ_CAUSE = 0x1900,
215 PCIE_IRQ_MASK = 0x1910,
Mark Lord646a4da2008-01-26 18:30:37 -0500216 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
Mark Lord02a121d2007-12-01 13:07:22 -0500217
Mark Lord7368f912008-04-25 11:24:24 -0400218 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
Mark Lordcae5a292009-04-06 16:43:45 -0400219 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
220 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
221 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
222 SOC_HC_MAIN_IRQ_MASK = 0x20024,
Mark Lord40f21b12009-03-10 18:51:04 -0400223 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
224 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
Brett Russ20f733e2005-09-01 18:26:17 -0400225 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
226 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
Mark Lord2b748a02009-03-10 22:01:17 -0400227 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
228 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
Brett Russ20f733e2005-09-01 18:26:17 -0400229 PCI_ERR = (1 << 18),
Mark Lord40f21b12009-03-10 18:51:04 -0400230 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
231 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
232 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
233 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
234 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400235 GPIO_INT = (1 << 22),
236 SELF_INT = (1 << 23),
237 TWSI_INT = (1 << 24),
238 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
Jeff Garzikfb621e22007-02-25 04:19:45 -0500239 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
Mark Lorde12bef52008-03-31 19:33:56 -0400240 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
Brett Russ20f733e2005-09-01 18:26:17 -0400241
242 /* SATAHC registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400243 HC_CFG = 0x00,
Brett Russ20f733e2005-09-01 18:26:17 -0400244
Mark Lordcae5a292009-04-06 16:43:45 -0400245 HC_IRQ_CAUSE = 0x14,
Mark Lord352fab72008-04-19 14:43:42 -0400246 DMA_IRQ = (1 << 0), /* shift by port # */
247 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400248 DEV_IRQ = (1 << 8), /* shift by port # */
249
Mark Lord2b748a02009-03-10 22:01:17 -0400250 /*
251 * Per-HC (Host-Controller) interrupt coalescing feature.
252 * This is present on all chip generations.
253 *
254 * Coalescing defers the interrupt until either the IO_THRESHOLD
255 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
256 */
Mark Lordcae5a292009-04-06 16:43:45 -0400257 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
258 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
Mark Lord2b748a02009-03-10 22:01:17 -0400259
Mark Lordcae5a292009-04-06 16:43:45 -0400260 SOC_LED_CTRL = 0x2c,
Mark Lord000b3442009-03-15 11:33:19 -0400261 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
262 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
263 /* with dev activity LED */
264
Brett Russ20f733e2005-09-01 18:26:17 -0400265 /* Shadow block registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400266 SHD_BLK = 0x100,
267 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
Brett Russ20f733e2005-09-01 18:26:17 -0400268
269 /* SATA registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400270 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
271 SATA_ACTIVE = 0x350,
272 FIS_IRQ_CAUSE = 0x364,
273 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
Mark Lord17c5aab2008-04-16 14:56:51 -0400274
Mark Lordcae5a292009-04-06 16:43:45 -0400275 LTMODE = 0x30c, /* requires read-after-write */
Mark Lord17c5aab2008-04-16 14:56:51 -0400276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
277
Mark Lordcae5a292009-04-06 16:43:45 -0400278 PHY_MODE2 = 0x330,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500279 PHY_MODE3 = 0x310,
Mark Lordcae5a292009-04-06 16:43:45 -0400280
281 PHY_MODE4 = 0x314, /* requires read-after-write */
Mark Lordba069e32008-05-31 16:46:34 -0400282 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
283 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
284 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
285 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
286
Mark Lordcae5a292009-04-06 16:43:45 -0400287 SATA_IFCTL = 0x344,
288 SATA_TESTCTL = 0x348,
289 SATA_IFSTAT = 0x34c,
290 VENDOR_UNIQUE_FIS = 0x35c,
Mark Lord17c5aab2008-04-16 14:56:51 -0400291
Mark Lordcae5a292009-04-06 16:43:45 -0400292 FISCFG = 0x360,
Mark Lord8e7decd2008-05-02 02:07:51 -0400293 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
294 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
Mark Lord17c5aab2008-04-16 14:56:51 -0400295
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200296 PHY_MODE9_GEN2 = 0x398,
297 PHY_MODE9_GEN1 = 0x39c,
298 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
299
Jeff Garzikc9d39132005-11-13 17:47:51 -0500300 MV5_PHY_MODE = 0x74,
Mark Lordcae5a292009-04-06 16:43:45 -0400301 MV5_LTMODE = 0x30,
302 MV5_PHY_CTL = 0x0C,
303 SATA_IFCFG = 0x050,
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500304
305 MV_M2_PREAMP_MASK = 0x7e0,
Brett Russ20f733e2005-09-01 18:26:17 -0400306
307 /* Port registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400308 EDMA_CFG = 0,
Mark Lord0c589122008-01-26 18:31:16 -0500309 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
310 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
311 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
312 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
313 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
Mark Lorde12bef52008-03-31 19:33:56 -0400314 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
315 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
Brett Russ20f733e2005-09-01 18:26:17 -0400316
Mark Lordcae5a292009-04-06 16:43:45 -0400317 EDMA_ERR_IRQ_CAUSE = 0x8,
318 EDMA_ERR_IRQ_MASK = 0xc,
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400319 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
320 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
321 EDMA_ERR_DEV = (1 << 2), /* device error */
322 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
323 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
324 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400325 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
326 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400327 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400328 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400329 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
330 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
331 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
332 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
Mark Lord646a4da2008-01-26 18:30:37 -0500333
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400334 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500335 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
336 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
337 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
338 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
339
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400340 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500341
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400342 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500343 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
344 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
345 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
346 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
347 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
348
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400349 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500350
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400351 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400352 EDMA_ERR_OVERRUN_5 = (1 << 5),
353 EDMA_ERR_UNDERRUN_5 = (1 << 6),
Mark Lord646a4da2008-01-26 18:30:37 -0500354
355 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
356 EDMA_ERR_LNK_CTRL_RX_1 |
357 EDMA_ERR_LNK_CTRL_RX_3 |
Mark Lord85afb932008-04-19 14:54:41 -0400358 EDMA_ERR_LNK_CTRL_TX,
Mark Lord646a4da2008-01-26 18:30:37 -0500359
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400360 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
361 EDMA_ERR_PRD_PAR |
362 EDMA_ERR_DEV_DCON |
363 EDMA_ERR_DEV_CON |
364 EDMA_ERR_SERR |
365 EDMA_ERR_SELF_DIS |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400366 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400367 EDMA_ERR_CRPB_PAR |
368 EDMA_ERR_INTRL_PAR |
369 EDMA_ERR_IORDY |
370 EDMA_ERR_LNK_CTRL_RX_2 |
371 EDMA_ERR_LNK_DATA_RX |
372 EDMA_ERR_LNK_DATA_TX |
373 EDMA_ERR_TRANS_PROTO,
Mark Lorde12bef52008-03-31 19:33:56 -0400374
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400375 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
376 EDMA_ERR_PRD_PAR |
377 EDMA_ERR_DEV_DCON |
378 EDMA_ERR_DEV_CON |
379 EDMA_ERR_OVERRUN_5 |
380 EDMA_ERR_UNDERRUN_5 |
381 EDMA_ERR_SELF_DIS_5 |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400382 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400383 EDMA_ERR_CRPB_PAR |
384 EDMA_ERR_INTRL_PAR |
385 EDMA_ERR_IORDY,
Brett Russ20f733e2005-09-01 18:26:17 -0400386
Mark Lordcae5a292009-04-06 16:43:45 -0400387 EDMA_REQ_Q_BASE_HI = 0x10,
388 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400389
Mark Lordcae5a292009-04-06 16:43:45 -0400390 EDMA_REQ_Q_OUT_PTR = 0x18,
Brett Russ31961942005-09-30 01:36:00 -0400391 EDMA_REQ_Q_PTR_SHIFT = 5,
392
Mark Lordcae5a292009-04-06 16:43:45 -0400393 EDMA_RSP_Q_BASE_HI = 0x1c,
394 EDMA_RSP_Q_IN_PTR = 0x20,
395 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400396 EDMA_RSP_Q_PTR_SHIFT = 3,
397
Mark Lordcae5a292009-04-06 16:43:45 -0400398 EDMA_CMD = 0x28, /* EDMA command register */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400399 EDMA_EN = (1 << 0), /* enable EDMA */
400 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
Mark Lord8e7decd2008-05-02 02:07:51 -0400401 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
Brett Russ20f733e2005-09-01 18:26:17 -0400402
Mark Lordcae5a292009-04-06 16:43:45 -0400403 EDMA_STATUS = 0x30, /* EDMA engine status */
Mark Lord8e7decd2008-05-02 02:07:51 -0400404 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
405 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
406
Mark Lordcae5a292009-04-06 16:43:45 -0400407 EDMA_IORDY_TMOUT = 0x34,
408 EDMA_ARB_CFG = 0x38,
Mark Lord8e7decd2008-05-02 02:07:51 -0400409
Mark Lordcae5a292009-04-06 16:43:45 -0400410 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
411 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
Mark Lordda142652009-01-30 18:51:54 -0500412
Mark Lordcae5a292009-04-06 16:43:45 -0400413 BMDMA_CMD = 0x224, /* bmdma command register */
414 BMDMA_STATUS = 0x228, /* bmdma status register */
415 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
416 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
Mark Lordda142652009-01-30 18:51:54 -0500417
Brett Russ31961942005-09-30 01:36:00 -0400418 /* Host private flags (hp_flags) */
419 MV_HP_FLAG_MSI = (1 << 0),
Jeff Garzik47c2b672005-11-12 21:13:17 -0500420 MV_HP_ERRATA_50XXB0 = (1 << 1),
421 MV_HP_ERRATA_50XXB2 = (1 << 2),
422 MV_HP_ERRATA_60X1B2 = (1 << 3),
423 MV_HP_ERRATA_60X1C0 = (1 << 4),
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400424 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
425 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
426 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
Mark Lord02a121d2007-12-01 13:07:22 -0500427 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
Mark Lord616d4a92008-05-02 02:08:32 -0400428 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
Mark Lord1f398472008-05-27 17:54:48 -0400429 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
Mark Lord000b3442009-03-15 11:33:19 -0400430 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
Brett Russ20f733e2005-09-01 18:26:17 -0400431
Brett Russ31961942005-09-30 01:36:00 -0400432 /* Port private flags (pp_flags) */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400433 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
Mark Lord72109162008-01-26 18:31:33 -0500434 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
Mark Lord00f42ea2008-05-02 02:11:45 -0400435 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
Mark Lord29d187b2008-05-02 02:15:37 -0400436 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
Mark Lordd16ab3f2009-02-25 15:17:43 -0500437 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
Brett Russ31961942005-09-30 01:36:00 -0400438};
439
Jeff Garzikee9ccdf2007-07-12 15:51:22 -0400440#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
441#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
Jeff Garzike4e7b892006-01-31 12:18:41 -0500442#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
Mark Lord8e7decd2008-05-02 02:07:51 -0400443#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
Mark Lord1f398472008-05-27 17:54:48 -0400444#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500445
Lennert Buytenhek15a32632008-03-27 14:51:39 -0400446#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
447#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
448
Jeff Garzik095fec82005-11-12 09:50:49 -0500449enum {
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400450 /* DMA boundary 0xffff is required by the s/g splitting
451 * we need on /length/ in mv_fill-sg().
452 */
453 MV_DMA_BOUNDARY = 0xffffU,
Jeff Garzik095fec82005-11-12 09:50:49 -0500454
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400455 /* mask of register bits containing lower 32 bits
456 * of EDMA request queue DMA address
457 */
Jeff Garzik095fec82005-11-12 09:50:49 -0500458 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
459
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400460 /* ditto, for response queue */
Jeff Garzik095fec82005-11-12 09:50:49 -0500461 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
462};
463
Jeff Garzik522479f2005-11-12 22:14:02 -0500464enum chip_type {
465 chip_504x,
466 chip_508x,
467 chip_5080,
468 chip_604x,
469 chip_608x,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500470 chip_6042,
471 chip_7042,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500472 chip_soc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500473};
474
Brett Russ31961942005-09-30 01:36:00 -0400475/* Command ReQuest Block: 32B */
476struct mv_crqb {
Mark Lorde1469872006-05-22 19:02:03 -0400477 __le32 sg_addr;
478 __le32 sg_addr_hi;
479 __le16 ctrl_flags;
480 __le16 ata_cmd[11];
Brett Russ31961942005-09-30 01:36:00 -0400481};
482
Jeff Garzike4e7b892006-01-31 12:18:41 -0500483struct mv_crqb_iie {
Mark Lorde1469872006-05-22 19:02:03 -0400484 __le32 addr;
485 __le32 addr_hi;
486 __le32 flags;
487 __le32 len;
488 __le32 ata_cmd[4];
Jeff Garzike4e7b892006-01-31 12:18:41 -0500489};
490
Brett Russ31961942005-09-30 01:36:00 -0400491/* Command ResPonse Block: 8B */
492struct mv_crpb {
Mark Lorde1469872006-05-22 19:02:03 -0400493 __le16 id;
494 __le16 flags;
495 __le32 tmstmp;
Brett Russ31961942005-09-30 01:36:00 -0400496};
497
498/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
499struct mv_sg {
Mark Lorde1469872006-05-22 19:02:03 -0400500 __le32 addr;
501 __le32 flags_size;
502 __le32 addr_hi;
503 __le32 reserved;
Brett Russ20f733e2005-09-01 18:26:17 -0400504};
505
Mark Lord08da1752009-02-25 15:13:03 -0500506/*
507 * We keep a local cache of a few frequently accessed port
508 * registers here, to avoid having to read them (very slow)
509 * when switching between EDMA and non-EDMA modes.
510 */
511struct mv_cached_regs {
512 u32 fiscfg;
513 u32 ltmode;
514 u32 haltcond;
Mark Lordc01e8a22009-02-25 15:14:48 -0500515 u32 unknown_rsvd;
Mark Lord08da1752009-02-25 15:13:03 -0500516};
517
Brett Russ20f733e2005-09-01 18:26:17 -0400518struct mv_port_priv {
Brett Russ31961942005-09-30 01:36:00 -0400519 struct mv_crqb *crqb;
520 dma_addr_t crqb_dma;
521 struct mv_crpb *crpb;
522 dma_addr_t crpb_dma;
Mark Lordeb73d552008-01-29 13:24:00 -0500523 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
524 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400525
526 unsigned int req_idx;
527 unsigned int resp_idx;
528
Brett Russ31961942005-09-30 01:36:00 -0400529 u32 pp_flags;
Mark Lord08da1752009-02-25 15:13:03 -0500530 struct mv_cached_regs cached;
Mark Lord29d187b2008-05-02 02:15:37 -0400531 unsigned int delayed_eh_pmp_map;
Brett Russ20f733e2005-09-01 18:26:17 -0400532};
533
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500534struct mv_port_signal {
535 u32 amps;
536 u32 pre;
537};
538
Mark Lord02a121d2007-12-01 13:07:22 -0500539struct mv_host_priv {
540 u32 hp_flags;
Mark Lord96e2c4872008-05-17 13:38:00 -0400541 u32 main_irq_mask;
Mark Lord02a121d2007-12-01 13:07:22 -0500542 struct mv_port_signal signal[8];
543 const struct mv_hw_ops *ops;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500544 int n_ports;
545 void __iomem *base;
Mark Lord7368f912008-04-25 11:24:24 -0400546 void __iomem *main_irq_cause_addr;
547 void __iomem *main_irq_mask_addr;
Mark Lordcae5a292009-04-06 16:43:45 -0400548 u32 irq_cause_offset;
549 u32 irq_mask_offset;
Mark Lord02a121d2007-12-01 13:07:22 -0500550 u32 unmask_all_irqs;
Mark Lordda2fa9b2008-01-26 18:32:45 -0500551 /*
552 * These consistent DMA memory pools give us guaranteed
553 * alignment for hardware-accessed data structures,
554 * and less memory waste in accomplishing the alignment.
555 */
556 struct dma_pool *crqb_pool;
557 struct dma_pool *crpb_pool;
558 struct dma_pool *sg_tbl_pool;
Mark Lord02a121d2007-12-01 13:07:22 -0500559};
560
Jeff Garzik47c2b672005-11-12 21:13:17 -0500561struct mv_hw_ops {
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500562 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
563 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500564 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
565 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
566 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500567 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
568 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500569 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100570 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500571};
572
Tejun Heo82ef04f2008-07-31 17:02:40 +0900573static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
574static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
575static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
576static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
Brett Russ31961942005-09-30 01:36:00 -0400577static int mv_port_start(struct ata_port *ap);
578static void mv_port_stop(struct ata_port *ap);
Mark Lord3e4a1392008-05-02 02:10:02 -0400579static int mv_qc_defer(struct ata_queued_cmd *qc);
Brett Russ31961942005-09-30 01:36:00 -0400580static void mv_qc_prep(struct ata_queued_cmd *qc);
Jeff Garzike4e7b892006-01-31 12:18:41 -0500581static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900582static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900583static int mv_hardreset(struct ata_link *link, unsigned int *class,
584 unsigned long deadline);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400585static void mv_eh_freeze(struct ata_port *ap);
586static void mv_eh_thaw(struct ata_port *ap);
Mark Lordf2738272008-01-26 18:32:29 -0500587static void mv6_dev_config(struct ata_device *dev);
Brett Russ20f733e2005-09-01 18:26:17 -0400588
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500589static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
590 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500591static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
592static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
593 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500594static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
595 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500596static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100597static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500598
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500599static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
600 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500601static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
602static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
603 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500604static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
605 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500606static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500607static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
608 void __iomem *mmio);
609static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
612 void __iomem *mmio, unsigned int n_hc);
613static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
614 void __iomem *mmio);
615static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200616static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
617 void __iomem *mmio, unsigned int port);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100618static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
Mark Lorde12bef52008-03-31 19:33:56 -0400619static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500620 unsigned int port_no);
Mark Lorde12bef52008-03-31 19:33:56 -0400621static int mv_stop_edma(struct ata_port *ap);
Mark Lordb5624682008-03-31 19:34:40 -0400622static int mv_stop_edma_engine(void __iomem *port_mmio);
Mark Lord00b81232009-01-30 18:47:51 -0500623static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500624
Mark Lorde49856d2008-04-16 14:59:07 -0400625static void mv_pmp_select(struct ata_port *ap, int pmp);
626static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
627 unsigned long deadline);
628static int mv_softreset(struct ata_link *link, unsigned int *class,
629 unsigned long deadline);
Mark Lord29d187b2008-05-02 02:15:37 -0400630static void mv_pmp_error_handler(struct ata_port *ap);
Mark Lord4c299ca2008-05-02 02:16:20 -0400631static void mv_process_crpb_entries(struct ata_port *ap,
632 struct mv_port_priv *pp);
Brett Russ20f733e2005-09-01 18:26:17 -0400633
Mark Lordda142652009-01-30 18:51:54 -0500634static void mv_sff_irq_clear(struct ata_port *ap);
635static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
636static void mv_bmdma_setup(struct ata_queued_cmd *qc);
637static void mv_bmdma_start(struct ata_queued_cmd *qc);
638static void mv_bmdma_stop(struct ata_queued_cmd *qc);
639static u8 mv_bmdma_status(struct ata_port *ap);
Mark Lordd16ab3f2009-02-25 15:17:43 -0500640static u8 mv_sff_check_status(struct ata_port *ap);
Mark Lordda142652009-01-30 18:51:54 -0500641
Mark Lordeb73d552008-01-29 13:24:00 -0500642/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
643 * because we have to allow room for worst case splitting of
644 * PRDs for 64K boundaries in mv_fill_sg().
645 */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400646static struct scsi_host_template mv5_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900647 ATA_BASE_SHT(DRV_NAME),
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400648 .sg_tablesize = MV_MAX_SG_CT / 2,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400649 .dma_boundary = MV_DMA_BOUNDARY,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400650};
651
652static struct scsi_host_template mv6_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900653 ATA_NCQ_SHT(DRV_NAME),
Mark Lord138bfdd2008-01-26 18:33:18 -0500654 .can_queue = MV_MAX_Q_DEPTH - 1,
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400655 .sg_tablesize = MV_MAX_SG_CT / 2,
Brett Russ20f733e2005-09-01 18:26:17 -0400656 .dma_boundary = MV_DMA_BOUNDARY,
Brett Russ20f733e2005-09-01 18:26:17 -0400657};
658
Tejun Heo029cfd62008-03-25 12:22:49 +0900659static struct ata_port_operations mv5_ops = {
660 .inherits = &ata_sff_port_ops,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500661
Alan Coxc96f1732009-03-24 10:23:46 +0000662 .lost_interrupt = ATA_OP_NULL,
663
Mark Lord3e4a1392008-05-02 02:10:02 -0400664 .qc_defer = mv_qc_defer,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500665 .qc_prep = mv_qc_prep,
666 .qc_issue = mv_qc_issue,
667
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400668 .freeze = mv_eh_freeze,
669 .thaw = mv_eh_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900670 .hardreset = mv_hardreset,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900671 .error_handler = ata_std_error_handler, /* avoid SFF EH */
Tejun Heo029cfd62008-03-25 12:22:49 +0900672 .post_internal_cmd = ATA_OP_NULL,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400673
Jeff Garzikc9d39132005-11-13 17:47:51 -0500674 .scr_read = mv5_scr_read,
675 .scr_write = mv5_scr_write,
676
677 .port_start = mv_port_start,
678 .port_stop = mv_port_stop,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500679};
680
Tejun Heo029cfd62008-03-25 12:22:49 +0900681static struct ata_port_operations mv6_ops = {
682 .inherits = &mv5_ops,
Mark Lordf2738272008-01-26 18:32:29 -0500683 .dev_config = mv6_dev_config,
Brett Russ20f733e2005-09-01 18:26:17 -0400684 .scr_read = mv_scr_read,
685 .scr_write = mv_scr_write,
686
Mark Lorde49856d2008-04-16 14:59:07 -0400687 .pmp_hardreset = mv_pmp_hardreset,
688 .pmp_softreset = mv_softreset,
689 .softreset = mv_softreset,
Mark Lord29d187b2008-05-02 02:15:37 -0400690 .error_handler = mv_pmp_error_handler,
Mark Lordda142652009-01-30 18:51:54 -0500691
Mark Lord40f21b12009-03-10 18:51:04 -0400692 .sff_check_status = mv_sff_check_status,
Mark Lordda142652009-01-30 18:51:54 -0500693 .sff_irq_clear = mv_sff_irq_clear,
694 .check_atapi_dma = mv_check_atapi_dma,
695 .bmdma_setup = mv_bmdma_setup,
696 .bmdma_start = mv_bmdma_start,
697 .bmdma_stop = mv_bmdma_stop,
698 .bmdma_status = mv_bmdma_status,
Brett Russ20f733e2005-09-01 18:26:17 -0400699};
700
Tejun Heo029cfd62008-03-25 12:22:49 +0900701static struct ata_port_operations mv_iie_ops = {
702 .inherits = &mv6_ops,
703 .dev_config = ATA_OP_NULL,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500704 .qc_prep = mv_qc_prep_iie,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500705};
706
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100707static const struct ata_port_info mv_port_info[] = {
Brett Russ20f733e2005-09-01 18:26:17 -0400708 { /* chip_504x */
Mark Lord91b1a842009-01-30 18:46:39 -0500709 .flags = MV_GEN_I_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400710 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400711 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500712 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400713 },
714 { /* chip_508x */
Mark Lord91b1a842009-01-30 18:46:39 -0500715 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400716 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400717 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500718 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400719 },
Jeff Garzik47c2b672005-11-12 21:13:17 -0500720 { /* chip_5080 */
Mark Lord91b1a842009-01-30 18:46:39 -0500721 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400722 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400723 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500724 .port_ops = &mv5_ops,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500725 },
Brett Russ20f733e2005-09-01 18:26:17 -0400726 { /* chip_604x */
Mark Lord91b1a842009-01-30 18:46:39 -0500727 .flags = MV_GEN_II_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400728 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400729 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500730 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400731 },
732 { /* chip_608x */
Mark Lord91b1a842009-01-30 18:46:39 -0500733 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400734 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400735 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500736 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400737 },
Jeff Garzike4e7b892006-01-31 12:18:41 -0500738 { /* chip_6042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500739 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400740 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400741 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500742 .port_ops = &mv_iie_ops,
743 },
744 { /* chip_7042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500745 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400746 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400747 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500748 .port_ops = &mv_iie_ops,
749 },
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500750 { /* chip_soc */
Mark Lord91b1a842009-01-30 18:46:39 -0500751 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400752 .pio_mask = ATA_PIO4,
Mark Lord17c5aab2008-04-16 14:56:51 -0400753 .udma_mask = ATA_UDMA6,
754 .port_ops = &mv_iie_ops,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500755 },
Brett Russ20f733e2005-09-01 18:26:17 -0400756};
757
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500758static const struct pci_device_id mv_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400759 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
760 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
761 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
762 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
Mark Lord46c57842008-09-04 18:21:07 -0400763 /* RocketRAID 1720/174x have different identifiers */
764 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
Mark Lord44622542009-01-27 16:33:13 -0500765 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
766 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
Brett Russ20f733e2005-09-01 18:26:17 -0400767
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400768 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
769 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
770 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
771 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
772 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
Jeff Garzik29179532005-11-11 08:08:03 -0500773
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400774 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
775
Florian Attenbergerd9f9c6b2007-07-02 17:09:29 +0200776 /* Adaptec 1430SA */
777 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
778
Mark Lord02a121d2007-12-01 13:07:22 -0500779 /* Marvell 7042 support */
Morrison, Tom6a3d5862007-03-06 02:38:10 -0800780 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
781
Mark Lord02a121d2007-12-01 13:07:22 -0500782 /* Highpoint RocketRAID PCIe series */
783 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
784 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
785
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400786 { } /* terminate list */
Brett Russ20f733e2005-09-01 18:26:17 -0400787};
788
Jeff Garzik47c2b672005-11-12 21:13:17 -0500789static const struct mv_hw_ops mv5xxx_ops = {
790 .phy_errata = mv5_phy_errata,
791 .enable_leds = mv5_enable_leds,
792 .read_preamp = mv5_read_preamp,
793 .reset_hc = mv5_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500794 .reset_flash = mv5_reset_flash,
795 .reset_bus = mv5_reset_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500796};
797
798static const struct mv_hw_ops mv6xxx_ops = {
799 .phy_errata = mv6_phy_errata,
800 .enable_leds = mv6_enable_leds,
801 .read_preamp = mv6_read_preamp,
802 .reset_hc = mv6_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500803 .reset_flash = mv6_reset_flash,
804 .reset_bus = mv_reset_pci_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500805};
806
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500807static const struct mv_hw_ops mv_soc_ops = {
808 .phy_errata = mv6_phy_errata,
809 .enable_leds = mv_soc_enable_leds,
810 .read_preamp = mv_soc_read_preamp,
811 .reset_hc = mv_soc_reset_hc,
812 .reset_flash = mv_soc_reset_flash,
813 .reset_bus = mv_soc_reset_bus,
814};
815
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200816static const struct mv_hw_ops mv_soc_65n_ops = {
817 .phy_errata = mv_soc_65n_phy_errata,
818 .enable_leds = mv_soc_enable_leds,
819 .reset_hc = mv_soc_reset_hc,
820 .reset_flash = mv_soc_reset_flash,
821 .reset_bus = mv_soc_reset_bus,
822};
823
Brett Russ20f733e2005-09-01 18:26:17 -0400824/*
825 * Functions
826 */
827
828static inline void writelfl(unsigned long data, void __iomem *addr)
829{
830 writel(data, addr);
831 (void) readl(addr); /* flush to avoid PCI posted write */
832}
833
Jeff Garzikc9d39132005-11-13 17:47:51 -0500834static inline unsigned int mv_hc_from_port(unsigned int port)
835{
836 return port >> MV_PORT_HC_SHIFT;
837}
838
839static inline unsigned int mv_hardport_from_port(unsigned int port)
840{
841 return port & MV_PORT_MASK;
842}
843
Mark Lord1cfd19a2008-04-19 15:05:50 -0400844/*
845 * Consolidate some rather tricky bit shift calculations.
846 * This is hot-path stuff, so not a function.
847 * Simple code, with two return values, so macro rather than inline.
848 *
849 * port is the sole input, in range 0..7.
Mark Lord7368f912008-04-25 11:24:24 -0400850 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
851 * hardport is the other output, in range 0..3.
Mark Lord1cfd19a2008-04-19 15:05:50 -0400852 *
853 * Note that port and hardport may be the same variable in some cases.
854 */
855#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
856{ \
857 shift = mv_hc_from_port(port) * HC_SHIFT; \
858 hardport = mv_hardport_from_port(port); \
859 shift += hardport * 2; \
860}
861
Mark Lord352fab72008-04-19 14:43:42 -0400862static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
863{
Mark Lordcae5a292009-04-06 16:43:45 -0400864 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
Mark Lord352fab72008-04-19 14:43:42 -0400865}
866
Jeff Garzikc9d39132005-11-13 17:47:51 -0500867static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
868 unsigned int port)
869{
870 return mv_hc_base(base, mv_hc_from_port(port));
871}
872
Brett Russ20f733e2005-09-01 18:26:17 -0400873static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
874{
Jeff Garzikc9d39132005-11-13 17:47:51 -0500875 return mv_hc_base_from_port(base, port) +
Jeff Garzik8b260242005-11-12 12:32:50 -0500876 MV_SATAHC_ARBTR_REG_SZ +
Jeff Garzikc9d39132005-11-13 17:47:51 -0500877 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
Brett Russ20f733e2005-09-01 18:26:17 -0400878}
879
Mark Lorde12bef52008-03-31 19:33:56 -0400880static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
881{
882 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
883 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
884
885 return hc_mmio + ofs;
886}
887
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500888static inline void __iomem *mv_host_base(struct ata_host *host)
889{
890 struct mv_host_priv *hpriv = host->private_data;
891 return hpriv->base;
892}
893
Brett Russ20f733e2005-09-01 18:26:17 -0400894static inline void __iomem *mv_ap_base(struct ata_port *ap)
895{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500896 return mv_port_base(mv_host_base(ap->host), ap->port_no);
Brett Russ20f733e2005-09-01 18:26:17 -0400897}
898
Jeff Garzikcca39742006-08-24 03:19:22 -0400899static inline int mv_get_hc_count(unsigned long port_flags)
Brett Russ20f733e2005-09-01 18:26:17 -0400900{
Jeff Garzikcca39742006-08-24 03:19:22 -0400901 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
Brett Russ20f733e2005-09-01 18:26:17 -0400902}
903
Mark Lord08da1752009-02-25 15:13:03 -0500904/**
905 * mv_save_cached_regs - (re-)initialize cached port registers
906 * @ap: the port whose registers we are caching
907 *
908 * Initialize the local cache of port registers,
909 * so that reading them over and over again can
910 * be avoided on the hotter paths of this driver.
911 * This saves a few microseconds each time we switch
912 * to/from EDMA mode to perform (eg.) a drive cache flush.
913 */
914static void mv_save_cached_regs(struct ata_port *ap)
915{
916 void __iomem *port_mmio = mv_ap_base(ap);
917 struct mv_port_priv *pp = ap->private_data;
918
Mark Lordcae5a292009-04-06 16:43:45 -0400919 pp->cached.fiscfg = readl(port_mmio + FISCFG);
920 pp->cached.ltmode = readl(port_mmio + LTMODE);
921 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
922 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
Mark Lord08da1752009-02-25 15:13:03 -0500923}
924
925/**
926 * mv_write_cached_reg - write to a cached port register
927 * @addr: hardware address of the register
928 * @old: pointer to cached value of the register
929 * @new: new value for the register
930 *
931 * Write a new value to a cached register,
932 * but only if the value is different from before.
933 */
934static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
935{
936 if (new != *old) {
Mark Lord12f3b6d2009-04-06 15:26:24 -0400937 unsigned long laddr;
Mark Lord08da1752009-02-25 15:13:03 -0500938 *old = new;
Mark Lord12f3b6d2009-04-06 15:26:24 -0400939 /*
940 * Workaround for 88SX60x1-B2 FEr SATA#13:
941 * Read-after-write is needed to prevent generating 64-bit
942 * write cycles on the PCI bus for SATA interface registers
943 * at offsets ending in 0x4 or 0xc.
944 *
945 * Looks like a lot of fuss, but it avoids an unnecessary
946 * +1 usec read-after-write delay for unaffected registers.
947 */
948 laddr = (long)addr & 0xffff;
949 if (laddr >= 0x300 && laddr <= 0x33c) {
950 laddr &= 0x000f;
951 if (laddr == 0x4 || laddr == 0xc) {
952 writelfl(new, addr); /* read after write */
953 return;
954 }
955 }
956 writel(new, addr); /* unaffected by the errata */
Mark Lord08da1752009-02-25 15:13:03 -0500957 }
958}
959
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400960static void mv_set_edma_ptrs(void __iomem *port_mmio,
961 struct mv_host_priv *hpriv,
962 struct mv_port_priv *pp)
963{
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400964 u32 index;
965
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400966 /*
967 * initialize request queue
968 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400969 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
970 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400971
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400972 WARN_ON(pp->crqb_dma & 0x3ff);
Mark Lordcae5a292009-04-06 16:43:45 -0400973 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400974 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -0400975 port_mmio + EDMA_REQ_Q_IN_PTR);
976 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400977
978 /*
979 * initialize response queue
980 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400981 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
982 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400983
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400984 WARN_ON(pp->crpb_dma & 0xff);
Mark Lordcae5a292009-04-06 16:43:45 -0400985 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
986 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400987 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -0400988 port_mmio + EDMA_RSP_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400989}
990
Mark Lord2b748a02009-03-10 22:01:17 -0400991static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
992{
993 /*
994 * When writing to the main_irq_mask in hardware,
995 * we must ensure exclusivity between the interrupt coalescing bits
996 * and the corresponding individual port DONE_IRQ bits.
997 *
998 * Note that this register is really an "IRQ enable" register,
999 * not an "IRQ mask" register as Marvell's naming might suggest.
1000 */
1001 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1002 mask &= ~DONE_IRQ_0_3;
1003 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1004 mask &= ~DONE_IRQ_4_7;
1005 writelfl(mask, hpriv->main_irq_mask_addr);
1006}
1007
Mark Lordc4de5732008-05-17 13:35:21 -04001008static void mv_set_main_irq_mask(struct ata_host *host,
1009 u32 disable_bits, u32 enable_bits)
1010{
1011 struct mv_host_priv *hpriv = host->private_data;
1012 u32 old_mask, new_mask;
1013
Mark Lord96e2c4872008-05-17 13:38:00 -04001014 old_mask = hpriv->main_irq_mask;
Mark Lordc4de5732008-05-17 13:35:21 -04001015 new_mask = (old_mask & ~disable_bits) | enable_bits;
Mark Lord96e2c4872008-05-17 13:38:00 -04001016 if (new_mask != old_mask) {
1017 hpriv->main_irq_mask = new_mask;
Mark Lord2b748a02009-03-10 22:01:17 -04001018 mv_write_main_irq_mask(new_mask, hpriv);
Mark Lord96e2c4872008-05-17 13:38:00 -04001019 }
Mark Lordc4de5732008-05-17 13:35:21 -04001020}
1021
1022static void mv_enable_port_irqs(struct ata_port *ap,
1023 unsigned int port_bits)
1024{
1025 unsigned int shift, hardport, port = ap->port_no;
1026 u32 disable_bits, enable_bits;
1027
1028 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1029
1030 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1031 enable_bits = port_bits << shift;
1032 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1033}
1034
Mark Lord00b81232009-01-30 18:47:51 -05001035static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1036 void __iomem *port_mmio,
1037 unsigned int port_irqs)
1038{
1039 struct mv_host_priv *hpriv = ap->host->private_data;
1040 int hardport = mv_hardport_from_port(ap->port_no);
1041 void __iomem *hc_mmio = mv_hc_base_from_port(
1042 mv_host_base(ap->host), ap->port_no);
1043 u32 hc_irq_cause;
1044
1045 /* clear EDMA event indicators, if any */
Mark Lordcae5a292009-04-06 16:43:45 -04001046 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001047
1048 /* clear pending irq events */
1049 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04001050 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001051
1052 /* clear FIS IRQ Cause */
1053 if (IS_GEN_IIE(hpriv))
Mark Lordcae5a292009-04-06 16:43:45 -04001054 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001055
1056 mv_enable_port_irqs(ap, port_irqs);
1057}
1058
Mark Lord2b748a02009-03-10 22:01:17 -04001059static void mv_set_irq_coalescing(struct ata_host *host,
1060 unsigned int count, unsigned int usecs)
1061{
1062 struct mv_host_priv *hpriv = host->private_data;
1063 void __iomem *mmio = hpriv->base, *hc_mmio;
1064 u32 coal_enable = 0;
1065 unsigned long flags;
Mark Lord6abf4672009-03-11 00:56:00 -04001066 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
Mark Lord2b748a02009-03-10 22:01:17 -04001067 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1068 ALL_PORTS_COAL_DONE;
1069
1070 /* Disable IRQ coalescing if either threshold is zero */
1071 if (!usecs || !count) {
1072 clks = count = 0;
1073 } else {
1074 /* Respect maximum limits of the hardware */
1075 clks = usecs * COAL_CLOCKS_PER_USEC;
1076 if (clks > MAX_COAL_TIME_THRESHOLD)
1077 clks = MAX_COAL_TIME_THRESHOLD;
1078 if (count > MAX_COAL_IO_COUNT)
1079 count = MAX_COAL_IO_COUNT;
1080 }
1081
1082 spin_lock_irqsave(&host->lock, flags);
Mark Lord6abf4672009-03-11 00:56:00 -04001083 mv_set_main_irq_mask(host, coal_disable, 0);
Mark Lord2b748a02009-03-10 22:01:17 -04001084
Mark Lord6abf4672009-03-11 00:56:00 -04001085 if (is_dual_hc && !IS_GEN_I(hpriv)) {
Mark Lord2b748a02009-03-10 22:01:17 -04001086 /*
Mark Lord6abf4672009-03-11 00:56:00 -04001087 * GEN_II/GEN_IIE with dual host controllers:
1088 * one set of global thresholds for the entire chip.
Mark Lord2b748a02009-03-10 22:01:17 -04001089 */
Mark Lordcae5a292009-04-06 16:43:45 -04001090 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1091 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
Mark Lord2b748a02009-03-10 22:01:17 -04001092 /* clear leftover coal IRQ bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001093 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001094 if (count)
1095 coal_enable = ALL_PORTS_COAL_DONE;
1096 clks = count = 0; /* force clearing of regular regs below */
Mark Lord2b748a02009-03-10 22:01:17 -04001097 }
Mark Lord6abf4672009-03-11 00:56:00 -04001098
Mark Lord2b748a02009-03-10 22:01:17 -04001099 /*
1100 * All chips: independent thresholds for each HC on the chip.
1101 */
1102 hc_mmio = mv_hc_base_from_port(mmio, 0);
Mark Lordcae5a292009-04-06 16:43:45 -04001103 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1104 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1105 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001106 if (count)
1107 coal_enable |= PORTS_0_3_COAL_DONE;
1108 if (is_dual_hc) {
Mark Lord2b748a02009-03-10 22:01:17 -04001109 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
Mark Lordcae5a292009-04-06 16:43:45 -04001110 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1111 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1112 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001113 if (count)
1114 coal_enable |= PORTS_4_7_COAL_DONE;
Mark Lord2b748a02009-03-10 22:01:17 -04001115 }
Mark Lord2b748a02009-03-10 22:01:17 -04001116
Mark Lord6abf4672009-03-11 00:56:00 -04001117 mv_set_main_irq_mask(host, 0, coal_enable);
Mark Lord2b748a02009-03-10 22:01:17 -04001118 spin_unlock_irqrestore(&host->lock, flags);
1119}
1120
Brett Russ05b308e2005-10-05 17:08:53 -04001121/**
Mark Lord00b81232009-01-30 18:47:51 -05001122 * mv_start_edma - Enable eDMA engine
Brett Russ05b308e2005-10-05 17:08:53 -04001123 * @base: port base address
1124 * @pp: port private data
1125 *
Tejun Heobeec7db2006-02-11 19:11:13 +09001126 * Verify the local cache of the eDMA state is accurate with a
1127 * WARN_ON.
Brett Russ05b308e2005-10-05 17:08:53 -04001128 *
1129 * LOCKING:
1130 * Inherited from caller.
1131 */
Mark Lord00b81232009-01-30 18:47:51 -05001132static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
Mark Lord72109162008-01-26 18:31:33 -05001133 struct mv_port_priv *pp, u8 protocol)
Brett Russ31961942005-09-30 01:36:00 -04001134{
Mark Lord72109162008-01-26 18:31:33 -05001135 int want_ncq = (protocol == ATA_PROT_NCQ);
1136
1137 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1138 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1139 if (want_ncq != using_ncq)
Mark Lordb5624682008-03-31 19:34:40 -04001140 mv_stop_edma(ap);
Mark Lord72109162008-01-26 18:31:33 -05001141 }
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001142 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
Mark Lord0c589122008-01-26 18:31:16 -05001143 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lord0c589122008-01-26 18:31:16 -05001144
Mark Lord00b81232009-01-30 18:47:51 -05001145 mv_edma_cfg(ap, want_ncq, 1);
Mark Lord0c589122008-01-26 18:31:16 -05001146
Mark Lordf630d562008-01-26 18:31:00 -05001147 mv_set_edma_ptrs(port_mmio, hpriv, pp);
Mark Lord00b81232009-01-30 18:47:51 -05001148 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001149
Mark Lordcae5a292009-04-06 16:43:45 -04001150 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
Brett Russafb0edd2005-10-05 17:08:42 -04001151 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1152 }
Brett Russ31961942005-09-30 01:36:00 -04001153}
1154
Mark Lord9b2c4e02008-05-02 02:09:14 -04001155static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1156{
1157 void __iomem *port_mmio = mv_ap_base(ap);
1158 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1159 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1160 int i;
1161
1162 /*
1163 * Wait for the EDMA engine to finish transactions in progress.
Mark Lordc46938c2008-05-02 14:02:28 -04001164 * No idea what a good "timeout" value might be, but measurements
1165 * indicate that it often requires hundreds of microseconds
1166 * with two drives in-use. So we use the 15msec value above
1167 * as a rough guess at what even more drives might require.
Mark Lord9b2c4e02008-05-02 02:09:14 -04001168 */
1169 for (i = 0; i < timeout; ++i) {
Mark Lordcae5a292009-04-06 16:43:45 -04001170 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
Mark Lord9b2c4e02008-05-02 02:09:14 -04001171 if ((edma_stat & empty_idle) == empty_idle)
1172 break;
1173 udelay(per_loop);
1174 }
1175 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1176}
1177
Brett Russ05b308e2005-10-05 17:08:53 -04001178/**
Mark Lorde12bef52008-03-31 19:33:56 -04001179 * mv_stop_edma_engine - Disable eDMA engine
Mark Lordb5624682008-03-31 19:34:40 -04001180 * @port_mmio: io base address
Brett Russ05b308e2005-10-05 17:08:53 -04001181 *
1182 * LOCKING:
1183 * Inherited from caller.
1184 */
Mark Lordb5624682008-03-31 19:34:40 -04001185static int mv_stop_edma_engine(void __iomem *port_mmio)
Brett Russ31961942005-09-30 01:36:00 -04001186{
Mark Lordb5624682008-03-31 19:34:40 -04001187 int i;
Brett Russ31961942005-09-30 01:36:00 -04001188
Mark Lordb5624682008-03-31 19:34:40 -04001189 /* Disable eDMA. The disable bit auto clears. */
Mark Lordcae5a292009-04-06 16:43:45 -04001190 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
Jeff Garzik8b260242005-11-12 12:32:50 -05001191
Mark Lordb5624682008-03-31 19:34:40 -04001192 /* Wait for the chip to confirm eDMA is off. */
1193 for (i = 10000; i > 0; i--) {
Mark Lordcae5a292009-04-06 16:43:45 -04001194 u32 reg = readl(port_mmio + EDMA_CMD);
Jeff Garzik4537deb2007-07-12 14:30:19 -04001195 if (!(reg & EDMA_EN))
Mark Lordb5624682008-03-31 19:34:40 -04001196 return 0;
1197 udelay(10);
Brett Russ31961942005-09-30 01:36:00 -04001198 }
Mark Lordb5624682008-03-31 19:34:40 -04001199 return -EIO;
Brett Russ31961942005-09-30 01:36:00 -04001200}
1201
Mark Lorde12bef52008-03-31 19:33:56 -04001202static int mv_stop_edma(struct ata_port *ap)
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001203{
Mark Lordb5624682008-03-31 19:34:40 -04001204 void __iomem *port_mmio = mv_ap_base(ap);
1205 struct mv_port_priv *pp = ap->private_data;
Mark Lord66e57a22009-01-30 18:52:58 -05001206 int err = 0;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001207
Mark Lordb5624682008-03-31 19:34:40 -04001208 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1209 return 0;
1210 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lord9b2c4e02008-05-02 02:09:14 -04001211 mv_wait_for_edma_empty_idle(ap);
Mark Lordb5624682008-03-31 19:34:40 -04001212 if (mv_stop_edma_engine(port_mmio)) {
1213 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
Mark Lord66e57a22009-01-30 18:52:58 -05001214 err = -EIO;
Mark Lordb5624682008-03-31 19:34:40 -04001215 }
Mark Lord66e57a22009-01-30 18:52:58 -05001216 mv_edma_cfg(ap, 0, 0);
1217 return err;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001218}
1219
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001220#ifdef ATA_DEBUG
Brett Russ31961942005-09-30 01:36:00 -04001221static void mv_dump_mem(void __iomem *start, unsigned bytes)
1222{
Brett Russ31961942005-09-30 01:36:00 -04001223 int b, w;
1224 for (b = 0; b < bytes; ) {
1225 DPRINTK("%p: ", start + b);
1226 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001227 printk("%08x ", readl(start + b));
Brett Russ31961942005-09-30 01:36:00 -04001228 b += sizeof(u32);
1229 }
1230 printk("\n");
1231 }
Brett Russ31961942005-09-30 01:36:00 -04001232}
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001233#endif
1234
Brett Russ31961942005-09-30 01:36:00 -04001235static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1236{
1237#ifdef ATA_DEBUG
1238 int b, w;
1239 u32 dw;
1240 for (b = 0; b < bytes; ) {
1241 DPRINTK("%02x: ", b);
1242 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001243 (void) pci_read_config_dword(pdev, b, &dw);
1244 printk("%08x ", dw);
Brett Russ31961942005-09-30 01:36:00 -04001245 b += sizeof(u32);
1246 }
1247 printk("\n");
1248 }
1249#endif
1250}
1251static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1252 struct pci_dev *pdev)
1253{
1254#ifdef ATA_DEBUG
Jeff Garzik8b260242005-11-12 12:32:50 -05001255 void __iomem *hc_base = mv_hc_base(mmio_base,
Brett Russ31961942005-09-30 01:36:00 -04001256 port >> MV_PORT_HC_SHIFT);
1257 void __iomem *port_base;
1258 int start_port, num_ports, p, start_hc, num_hcs, hc;
1259
1260 if (0 > port) {
1261 start_hc = start_port = 0;
1262 num_ports = 8; /* shld be benign for 4 port devs */
1263 num_hcs = 2;
1264 } else {
1265 start_hc = port >> MV_PORT_HC_SHIFT;
1266 start_port = port;
1267 num_ports = num_hcs = 1;
1268 }
Jeff Garzik8b260242005-11-12 12:32:50 -05001269 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
Brett Russ31961942005-09-30 01:36:00 -04001270 num_ports > 1 ? num_ports - 1 : start_port);
1271
1272 if (NULL != pdev) {
1273 DPRINTK("PCI config space regs:\n");
1274 mv_dump_pci_cfg(pdev, 0x68);
1275 }
1276 DPRINTK("PCI regs:\n");
1277 mv_dump_mem(mmio_base+0xc00, 0x3c);
1278 mv_dump_mem(mmio_base+0xd00, 0x34);
1279 mv_dump_mem(mmio_base+0xf00, 0x4);
1280 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1281 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
Dan Alonid220c372006-04-10 23:20:22 -07001282 hc_base = mv_hc_base(mmio_base, hc);
Brett Russ31961942005-09-30 01:36:00 -04001283 DPRINTK("HC regs (HC %i):\n", hc);
1284 mv_dump_mem(hc_base, 0x1c);
1285 }
1286 for (p = start_port; p < start_port + num_ports; p++) {
1287 port_base = mv_port_base(mmio_base, p);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001288 DPRINTK("EDMA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001289 mv_dump_mem(port_base, 0x54);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001290 DPRINTK("SATA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001291 mv_dump_mem(port_base+0x300, 0x60);
1292 }
1293#endif
1294}
1295
Brett Russ20f733e2005-09-01 18:26:17 -04001296static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1297{
1298 unsigned int ofs;
1299
1300 switch (sc_reg_in) {
1301 case SCR_STATUS:
1302 case SCR_CONTROL:
1303 case SCR_ERROR:
Mark Lordcae5a292009-04-06 16:43:45 -04001304 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
Brett Russ20f733e2005-09-01 18:26:17 -04001305 break;
1306 case SCR_ACTIVE:
Mark Lordcae5a292009-04-06 16:43:45 -04001307 ofs = SATA_ACTIVE; /* active is not with the others */
Brett Russ20f733e2005-09-01 18:26:17 -04001308 break;
1309 default:
1310 ofs = 0xffffffffU;
1311 break;
1312 }
1313 return ofs;
1314}
1315
Tejun Heo82ef04f2008-07-31 17:02:40 +09001316static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Brett Russ20f733e2005-09-01 18:26:17 -04001317{
1318 unsigned int ofs = mv_scr_offset(sc_reg_in);
1319
Tejun Heoda3dbb12007-07-16 14:29:40 +09001320 if (ofs != 0xffffffffU) {
Tejun Heo82ef04f2008-07-31 17:02:40 +09001321 *val = readl(mv_ap_base(link->ap) + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001322 return 0;
1323 } else
1324 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001325}
1326
Tejun Heo82ef04f2008-07-31 17:02:40 +09001327static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Brett Russ20f733e2005-09-01 18:26:17 -04001328{
1329 unsigned int ofs = mv_scr_offset(sc_reg_in);
1330
Tejun Heoda3dbb12007-07-16 14:29:40 +09001331 if (ofs != 0xffffffffU) {
Mark Lord20091772009-04-06 15:24:57 -04001332 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1333 if (sc_reg_in == SCR_CONTROL) {
1334 /*
1335 * Workaround for 88SX60x1 FEr SATA#26:
1336 *
1337 * COMRESETs have to take care not to accidently
1338 * put the drive to sleep when writing SCR_CONTROL.
1339 * Setting bits 12..15 prevents this problem.
1340 *
1341 * So if we see an outbound COMMRESET, set those bits.
1342 * Ditto for the followup write that clears the reset.
1343 *
1344 * The proprietary driver does this for
1345 * all chip versions, and so do we.
1346 */
1347 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1348 val |= 0xf000;
1349 }
1350 writelfl(val, addr);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001351 return 0;
1352 } else
1353 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001354}
1355
Mark Lordf2738272008-01-26 18:32:29 -05001356static void mv6_dev_config(struct ata_device *adev)
1357{
1358 /*
Mark Lorde49856d2008-04-16 14:59:07 -04001359 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1360 *
1361 * Gen-II does not support NCQ over a port multiplier
1362 * (no FIS-based switching).
Mark Lordf2738272008-01-26 18:32:29 -05001363 */
Mark Lorde49856d2008-04-16 14:59:07 -04001364 if (adev->flags & ATA_DFLAG_NCQ) {
Mark Lord352fab72008-04-19 14:43:42 -04001365 if (sata_pmp_attached(adev->link->ap)) {
Mark Lorde49856d2008-04-16 14:59:07 -04001366 adev->flags &= ~ATA_DFLAG_NCQ;
Mark Lord352fab72008-04-19 14:43:42 -04001367 ata_dev_printk(adev, KERN_INFO,
1368 "NCQ disabled for command-based switching\n");
Mark Lord352fab72008-04-19 14:43:42 -04001369 }
Mark Lorde49856d2008-04-16 14:59:07 -04001370 }
Mark Lordf2738272008-01-26 18:32:29 -05001371}
1372
Mark Lord3e4a1392008-05-02 02:10:02 -04001373static int mv_qc_defer(struct ata_queued_cmd *qc)
1374{
1375 struct ata_link *link = qc->dev->link;
1376 struct ata_port *ap = link->ap;
1377 struct mv_port_priv *pp = ap->private_data;
1378
1379 /*
Mark Lord29d187b2008-05-02 02:15:37 -04001380 * Don't allow new commands if we're in a delayed EH state
1381 * for NCQ and/or FIS-based switching.
1382 */
1383 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1384 return ATA_DEFER_PORT;
1385 /*
Mark Lord3e4a1392008-05-02 02:10:02 -04001386 * If the port is completely idle, then allow the new qc.
1387 */
1388 if (ap->nr_active_links == 0)
1389 return 0;
1390
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001391 /*
1392 * The port is operating in host queuing mode (EDMA) with NCQ
1393 * enabled, allow multiple NCQ commands. EDMA also allows
1394 * queueing multiple DMA commands but libata core currently
1395 * doesn't allow it.
1396 */
1397 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1398 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1399 return 0;
1400
Mark Lord3e4a1392008-05-02 02:10:02 -04001401 return ATA_DEFER_PORT;
1402}
1403
Mark Lord08da1752009-02-25 15:13:03 -05001404static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
Mark Lorde49856d2008-04-16 14:59:07 -04001405{
Mark Lord08da1752009-02-25 15:13:03 -05001406 struct mv_port_priv *pp = ap->private_data;
1407 void __iomem *port_mmio;
Mark Lord00f42ea2008-05-02 02:11:45 -04001408
Mark Lord08da1752009-02-25 15:13:03 -05001409 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1410 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1411 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
Mark Lord00f42ea2008-05-02 02:11:45 -04001412
Mark Lord08da1752009-02-25 15:13:03 -05001413 ltmode = *old_ltmode & ~LTMODE_BIT8;
1414 haltcond = *old_haltcond | EDMA_ERR_DEV;
Mark Lord00f42ea2008-05-02 02:11:45 -04001415
1416 if (want_fbs) {
Mark Lord08da1752009-02-25 15:13:03 -05001417 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1418 ltmode = *old_ltmode | LTMODE_BIT8;
Mark Lord4c299ca2008-05-02 02:16:20 -04001419 if (want_ncq)
Mark Lord08da1752009-02-25 15:13:03 -05001420 haltcond &= ~EDMA_ERR_DEV;
Mark Lord4c299ca2008-05-02 02:16:20 -04001421 else
Mark Lord08da1752009-02-25 15:13:03 -05001422 fiscfg |= FISCFG_WAIT_DEV_ERR;
1423 } else {
1424 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
Mark Lorde49856d2008-04-16 14:59:07 -04001425 }
Mark Lord00f42ea2008-05-02 02:11:45 -04001426
Mark Lord08da1752009-02-25 15:13:03 -05001427 port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04001428 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1429 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1430 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
Mark Lord0c589122008-01-26 18:31:16 -05001431}
Jeff Garzike4e7b892006-01-31 12:18:41 -05001432
Mark Lorddd2890f2008-05-02 02:10:56 -04001433static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1434{
1435 struct mv_host_priv *hpriv = ap->host->private_data;
1436 u32 old, new;
1437
1438 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
Mark Lordcae5a292009-04-06 16:43:45 -04001439 old = readl(hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001440 if (want_ncq)
1441 new = old | (1 << 22);
1442 else
1443 new = old & ~(1 << 22);
1444 if (new != old)
Mark Lordcae5a292009-04-06 16:43:45 -04001445 writel(new, hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001446}
1447
Mark Lordc01e8a22009-02-25 15:14:48 -05001448/**
Mark Lord40f21b12009-03-10 18:51:04 -04001449 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1450 * @ap: Port being initialized
Mark Lordc01e8a22009-02-25 15:14:48 -05001451 *
1452 * There are two DMA modes on these chips: basic DMA, and EDMA.
1453 *
1454 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1455 * of basic DMA on the GEN_IIE versions of the chips.
1456 *
1457 * This bit survives EDMA resets, and must be set for basic DMA
1458 * to function, and should be cleared when EDMA is active.
1459 */
1460static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1461{
1462 struct mv_port_priv *pp = ap->private_data;
1463 u32 new, *old = &pp->cached.unknown_rsvd;
1464
1465 if (enable_bmdma)
1466 new = *old | 1;
1467 else
1468 new = *old & ~1;
Mark Lordcae5a292009-04-06 16:43:45 -04001469 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
Mark Lordc01e8a22009-02-25 15:14:48 -05001470}
1471
Mark Lord000b3442009-03-15 11:33:19 -04001472/*
1473 * SOC chips have an issue whereby the HDD LEDs don't always blink
1474 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1475 * of the SOC takes care of it, generating a steady blink rate when
1476 * any drive on the chip is active.
1477 *
1478 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1479 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1480 *
1481 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1482 * LED operation works then, and provides better (more accurate) feedback.
1483 *
1484 * Note that this code assumes that an SOC never has more than one HC onboard.
1485 */
1486static void mv_soc_led_blink_enable(struct ata_port *ap)
1487{
1488 struct ata_host *host = ap->host;
1489 struct mv_host_priv *hpriv = host->private_data;
1490 void __iomem *hc_mmio;
1491 u32 led_ctrl;
1492
1493 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1494 return;
1495 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1496 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001497 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1498 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001499}
1500
1501static void mv_soc_led_blink_disable(struct ata_port *ap)
1502{
1503 struct ata_host *host = ap->host;
1504 struct mv_host_priv *hpriv = host->private_data;
1505 void __iomem *hc_mmio;
1506 u32 led_ctrl;
1507 unsigned int port;
1508
1509 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1510 return;
1511
1512 /* disable led-blink only if no ports are using NCQ */
1513 for (port = 0; port < hpriv->n_ports; port++) {
1514 struct ata_port *this_ap = host->ports[port];
1515 struct mv_port_priv *pp = this_ap->private_data;
1516
1517 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1518 return;
1519 }
1520
1521 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1522 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001523 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1524 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001525}
1526
Mark Lord00b81232009-01-30 18:47:51 -05001527static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
Jeff Garzike4e7b892006-01-31 12:18:41 -05001528{
1529 u32 cfg;
Mark Lorde12bef52008-03-31 19:33:56 -04001530 struct mv_port_priv *pp = ap->private_data;
1531 struct mv_host_priv *hpriv = ap->host->private_data;
1532 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001533
1534 /* set up non-NCQ EDMA configuration */
1535 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
Mark Lordd16ab3f2009-02-25 15:17:43 -05001536 pp->pp_flags &=
1537 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001538
1539 if (IS_GEN_I(hpriv))
1540 cfg |= (1 << 8); /* enab config burst size mask */
1541
Mark Lorddd2890f2008-05-02 02:10:56 -04001542 else if (IS_GEN_II(hpriv)) {
Jeff Garzike4e7b892006-01-31 12:18:41 -05001543 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
Mark Lorddd2890f2008-05-02 02:10:56 -04001544 mv_60x1_errata_sata25(ap, want_ncq);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001545
Mark Lorddd2890f2008-05-02 02:10:56 -04001546 } else if (IS_GEN_IIE(hpriv)) {
Mark Lord00f42ea2008-05-02 02:11:45 -04001547 int want_fbs = sata_pmp_attached(ap);
1548 /*
1549 * Possible future enhancement:
1550 *
1551 * The chip can use FBS with non-NCQ, if we allow it,
1552 * But first we need to have the error handling in place
1553 * for this mode (datasheet section 7.3.15.4.2.3).
1554 * So disallow non-NCQ FBS for now.
1555 */
1556 want_fbs &= want_ncq;
1557
Mark Lord08da1752009-02-25 15:13:03 -05001558 mv_config_fbs(ap, want_ncq, want_fbs);
Mark Lord00f42ea2008-05-02 02:11:45 -04001559
1560 if (want_fbs) {
1561 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1562 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1563 }
1564
Jeff Garzike728eab2007-02-25 02:53:41 -05001565 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
Mark Lord00b81232009-01-30 18:47:51 -05001566 if (want_edma) {
1567 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1568 if (!IS_SOC(hpriv))
1569 cfg |= (1 << 18); /* enab early completion */
1570 }
Mark Lord616d4a92008-05-02 02:08:32 -04001571 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1572 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
Mark Lordc01e8a22009-02-25 15:14:48 -05001573 mv_bmdma_enable_iie(ap, !want_edma);
Mark Lord000b3442009-03-15 11:33:19 -04001574
1575 if (IS_SOC(hpriv)) {
1576 if (want_ncq)
1577 mv_soc_led_blink_enable(ap);
1578 else
1579 mv_soc_led_blink_disable(ap);
1580 }
Jeff Garzike4e7b892006-01-31 12:18:41 -05001581 }
1582
Mark Lord72109162008-01-26 18:31:33 -05001583 if (want_ncq) {
1584 cfg |= EDMA_CFG_NCQ;
1585 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
Mark Lord00b81232009-01-30 18:47:51 -05001586 }
Mark Lord72109162008-01-26 18:31:33 -05001587
Mark Lordcae5a292009-04-06 16:43:45 -04001588 writelfl(cfg, port_mmio + EDMA_CFG);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001589}
1590
Mark Lordda2fa9b2008-01-26 18:32:45 -05001591static void mv_port_free_dma_mem(struct ata_port *ap)
1592{
1593 struct mv_host_priv *hpriv = ap->host->private_data;
1594 struct mv_port_priv *pp = ap->private_data;
Mark Lordeb73d552008-01-29 13:24:00 -05001595 int tag;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001596
1597 if (pp->crqb) {
1598 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1599 pp->crqb = NULL;
1600 }
1601 if (pp->crpb) {
1602 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1603 pp->crpb = NULL;
1604 }
Mark Lordeb73d552008-01-29 13:24:00 -05001605 /*
1606 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1607 * For later hardware, we have one unique sg_tbl per NCQ tag.
1608 */
1609 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1610 if (pp->sg_tbl[tag]) {
1611 if (tag == 0 || !IS_GEN_I(hpriv))
1612 dma_pool_free(hpriv->sg_tbl_pool,
1613 pp->sg_tbl[tag],
1614 pp->sg_tbl_dma[tag]);
1615 pp->sg_tbl[tag] = NULL;
1616 }
Mark Lordda2fa9b2008-01-26 18:32:45 -05001617 }
1618}
1619
Brett Russ05b308e2005-10-05 17:08:53 -04001620/**
1621 * mv_port_start - Port specific init/start routine.
1622 * @ap: ATA channel to manipulate
1623 *
1624 * Allocate and point to DMA memory, init port private memory,
1625 * zero indices.
1626 *
1627 * LOCKING:
1628 * Inherited from caller.
1629 */
Brett Russ31961942005-09-30 01:36:00 -04001630static int mv_port_start(struct ata_port *ap)
1631{
Jeff Garzikcca39742006-08-24 03:19:22 -04001632 struct device *dev = ap->host->dev;
1633 struct mv_host_priv *hpriv = ap->host->private_data;
Brett Russ31961942005-09-30 01:36:00 -04001634 struct mv_port_priv *pp;
Mark Lord933cb8e2009-04-06 12:30:43 -04001635 unsigned long flags;
James Bottomleydde20202008-02-19 11:36:56 +01001636 int tag;
Brett Russ31961942005-09-30 01:36:00 -04001637
Tejun Heo24dc5f32007-01-20 16:00:28 +09001638 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -05001639 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001640 return -ENOMEM;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001641 ap->private_data = pp;
Brett Russ31961942005-09-30 01:36:00 -04001642
Mark Lordda2fa9b2008-01-26 18:32:45 -05001643 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1644 if (!pp->crqb)
1645 return -ENOMEM;
1646 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001647
Mark Lordda2fa9b2008-01-26 18:32:45 -05001648 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1649 if (!pp->crpb)
1650 goto out_port_free_dma_mem;
1651 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001652
Mark Lord3bd0a702008-06-18 12:11:16 -04001653 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1654 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1655 ap->flags |= ATA_FLAG_AN;
Mark Lordeb73d552008-01-29 13:24:00 -05001656 /*
1657 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1658 * For later hardware, we need one unique sg_tbl per NCQ tag.
1659 */
1660 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1661 if (tag == 0 || !IS_GEN_I(hpriv)) {
1662 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1663 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1664 if (!pp->sg_tbl[tag])
1665 goto out_port_free_dma_mem;
1666 } else {
1667 pp->sg_tbl[tag] = pp->sg_tbl[0];
1668 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1669 }
1670 }
Mark Lord933cb8e2009-04-06 12:30:43 -04001671
1672 spin_lock_irqsave(ap->lock, flags);
Mark Lord08da1752009-02-25 15:13:03 -05001673 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05001674 mv_edma_cfg(ap, 0, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001675 spin_unlock_irqrestore(ap->lock, flags);
1676
Brett Russ31961942005-09-30 01:36:00 -04001677 return 0;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001678
1679out_port_free_dma_mem:
1680 mv_port_free_dma_mem(ap);
1681 return -ENOMEM;
Brett Russ31961942005-09-30 01:36:00 -04001682}
1683
Brett Russ05b308e2005-10-05 17:08:53 -04001684/**
1685 * mv_port_stop - Port specific cleanup/stop routine.
1686 * @ap: ATA channel to manipulate
1687 *
1688 * Stop DMA, cleanup port memory.
1689 *
1690 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04001691 * This routine uses the host lock to protect the DMA stop.
Brett Russ05b308e2005-10-05 17:08:53 -04001692 */
Brett Russ31961942005-09-30 01:36:00 -04001693static void mv_port_stop(struct ata_port *ap)
1694{
Mark Lord933cb8e2009-04-06 12:30:43 -04001695 unsigned long flags;
1696
1697 spin_lock_irqsave(ap->lock, flags);
Mark Lorde12bef52008-03-31 19:33:56 -04001698 mv_stop_edma(ap);
Mark Lord88e675e2008-05-17 13:36:30 -04001699 mv_enable_port_irqs(ap, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001700 spin_unlock_irqrestore(ap->lock, flags);
Mark Lordda2fa9b2008-01-26 18:32:45 -05001701 mv_port_free_dma_mem(ap);
Brett Russ31961942005-09-30 01:36:00 -04001702}
1703
Brett Russ05b308e2005-10-05 17:08:53 -04001704/**
1705 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1706 * @qc: queued command whose SG list to source from
1707 *
1708 * Populate the SG list and mark the last entry.
1709 *
1710 * LOCKING:
1711 * Inherited from caller.
1712 */
Jeff Garzik6c087722007-10-12 00:16:23 -04001713static void mv_fill_sg(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04001714{
1715 struct mv_port_priv *pp = qc->ap->private_data;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001716 struct scatterlist *sg;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001717 struct mv_sg *mv_sg, *last_sg = NULL;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001718 unsigned int si;
Brett Russ31961942005-09-30 01:36:00 -04001719
Mark Lordeb73d552008-01-29 13:24:00 -05001720 mv_sg = pp->sg_tbl[qc->tag];
Tejun Heoff2aeb12007-12-05 16:43:11 +09001721 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikd88184f2007-02-26 01:26:06 -05001722 dma_addr_t addr = sg_dma_address(sg);
1723 u32 sg_len = sg_dma_len(sg);
Brett Russ31961942005-09-30 01:36:00 -04001724
Olof Johansson4007b492007-10-02 20:45:27 -05001725 while (sg_len) {
1726 u32 offset = addr & 0xffff;
1727 u32 len = sg_len;
Brett Russ31961942005-09-30 01:36:00 -04001728
Mark Lord32cd11a2009-02-01 16:50:32 -05001729 if (offset + len > 0x10000)
Olof Johansson4007b492007-10-02 20:45:27 -05001730 len = 0x10000 - offset;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001731
Olof Johansson4007b492007-10-02 20:45:27 -05001732 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1733 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
Jeff Garzik6c087722007-10-12 00:16:23 -04001734 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
Mark Lord32cd11a2009-02-01 16:50:32 -05001735 mv_sg->reserved = 0;
Olof Johansson4007b492007-10-02 20:45:27 -05001736
1737 sg_len -= len;
1738 addr += len;
1739
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001740 last_sg = mv_sg;
Olof Johansson4007b492007-10-02 20:45:27 -05001741 mv_sg++;
Olof Johansson4007b492007-10-02 20:45:27 -05001742 }
Brett Russ31961942005-09-30 01:36:00 -04001743 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001744
1745 if (likely(last_sg))
1746 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
Mark Lord32cd11a2009-02-01 16:50:32 -05001747 mb(); /* ensure data structure is visible to the chipset */
Brett Russ31961942005-09-30 01:36:00 -04001748}
1749
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001750static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
Brett Russ31961942005-09-30 01:36:00 -04001751{
Mark Lord559eeda2006-05-19 16:40:15 -04001752 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
Brett Russ31961942005-09-30 01:36:00 -04001753 (last ? CRQB_CMD_LAST : 0);
Mark Lord559eeda2006-05-19 16:40:15 -04001754 *cmdw = cpu_to_le16(tmp);
Brett Russ31961942005-09-30 01:36:00 -04001755}
1756
Brett Russ05b308e2005-10-05 17:08:53 -04001757/**
Mark Lordda142652009-01-30 18:51:54 -05001758 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1759 * @ap: Port associated with this ATA transaction.
1760 *
1761 * We need this only for ATAPI bmdma transactions,
1762 * as otherwise we experience spurious interrupts
1763 * after libata-sff handles the bmdma interrupts.
1764 */
1765static void mv_sff_irq_clear(struct ata_port *ap)
1766{
1767 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1768}
1769
1770/**
1771 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1772 * @qc: queued command to check for chipset/DMA compatibility.
1773 *
1774 * The bmdma engines cannot handle speculative data sizes
1775 * (bytecount under/over flow). So only allow DMA for
1776 * data transfer commands with known data sizes.
1777 *
1778 * LOCKING:
1779 * Inherited from caller.
1780 */
1781static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1782{
1783 struct scsi_cmnd *scmd = qc->scsicmd;
1784
1785 if (scmd) {
1786 switch (scmd->cmnd[0]) {
1787 case READ_6:
1788 case READ_10:
1789 case READ_12:
1790 case WRITE_6:
1791 case WRITE_10:
1792 case WRITE_12:
1793 case GPCMD_READ_CD:
1794 case GPCMD_SEND_DVD_STRUCTURE:
1795 case GPCMD_SEND_CUE_SHEET:
1796 return 0; /* DMA is safe */
1797 }
1798 }
1799 return -EOPNOTSUPP; /* use PIO instead */
1800}
1801
1802/**
1803 * mv_bmdma_setup - Set up BMDMA transaction
1804 * @qc: queued command to prepare DMA for.
1805 *
1806 * LOCKING:
1807 * Inherited from caller.
1808 */
1809static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1810{
1811 struct ata_port *ap = qc->ap;
1812 void __iomem *port_mmio = mv_ap_base(ap);
1813 struct mv_port_priv *pp = ap->private_data;
1814
1815 mv_fill_sg(qc);
1816
1817 /* clear all DMA cmd bits */
Mark Lordcae5a292009-04-06 16:43:45 -04001818 writel(0, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001819
1820 /* load PRD table addr. */
1821 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
Mark Lordcae5a292009-04-06 16:43:45 -04001822 port_mmio + BMDMA_PRD_HIGH);
Mark Lordda142652009-01-30 18:51:54 -05001823 writelfl(pp->sg_tbl_dma[qc->tag],
Mark Lordcae5a292009-04-06 16:43:45 -04001824 port_mmio + BMDMA_PRD_LOW);
Mark Lordda142652009-01-30 18:51:54 -05001825
1826 /* issue r/w command */
1827 ap->ops->sff_exec_command(ap, &qc->tf);
1828}
1829
1830/**
1831 * mv_bmdma_start - Start a BMDMA transaction
1832 * @qc: queued command to start DMA on.
1833 *
1834 * LOCKING:
1835 * Inherited from caller.
1836 */
1837static void mv_bmdma_start(struct ata_queued_cmd *qc)
1838{
1839 struct ata_port *ap = qc->ap;
1840 void __iomem *port_mmio = mv_ap_base(ap);
1841 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1842 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1843
1844 /* start host DMA transaction */
Mark Lordcae5a292009-04-06 16:43:45 -04001845 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001846}
1847
1848/**
1849 * mv_bmdma_stop - Stop BMDMA transfer
1850 * @qc: queued command to stop DMA on.
1851 *
1852 * Clears the ATA_DMA_START flag in the bmdma control register
1853 *
1854 * LOCKING:
1855 * Inherited from caller.
1856 */
1857static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1858{
1859 struct ata_port *ap = qc->ap;
1860 void __iomem *port_mmio = mv_ap_base(ap);
1861 u32 cmd;
1862
1863 /* clear start/stop bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001864 cmd = readl(port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001865 cmd &= ~ATA_DMA_START;
Mark Lordcae5a292009-04-06 16:43:45 -04001866 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001867
1868 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1869 ata_sff_dma_pause(ap);
1870}
1871
1872/**
1873 * mv_bmdma_status - Read BMDMA status
1874 * @ap: port for which to retrieve DMA status.
1875 *
1876 * Read and return equivalent of the sff BMDMA status register.
1877 *
1878 * LOCKING:
1879 * Inherited from caller.
1880 */
1881static u8 mv_bmdma_status(struct ata_port *ap)
1882{
1883 void __iomem *port_mmio = mv_ap_base(ap);
1884 u32 reg, status;
1885
1886 /*
1887 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1888 * and the ATA_DMA_INTR bit doesn't exist.
1889 */
Mark Lordcae5a292009-04-06 16:43:45 -04001890 reg = readl(port_mmio + BMDMA_STATUS);
Mark Lordda142652009-01-30 18:51:54 -05001891 if (reg & ATA_DMA_ACTIVE)
1892 status = ATA_DMA_ACTIVE;
1893 else
1894 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1895 return status;
1896}
1897
Mark Lord299b3f82009-04-13 11:29:34 -04001898static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1899{
1900 struct ata_taskfile *tf = &qc->tf;
1901 /*
1902 * Workaround for 88SX60x1 FEr SATA#24.
1903 *
1904 * Chip may corrupt WRITEs if multi_count >= 4kB.
1905 * Note that READs are unaffected.
1906 *
1907 * It's not clear if this errata really means "4K bytes",
1908 * or if it always happens for multi_count > 7
1909 * regardless of device sector_size.
1910 *
1911 * So, for safety, any write with multi_count > 7
1912 * gets converted here into a regular PIO write instead:
1913 */
1914 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1915 if (qc->dev->multi_count > 7) {
1916 switch (tf->command) {
1917 case ATA_CMD_WRITE_MULTI:
1918 tf->command = ATA_CMD_PIO_WRITE;
1919 break;
1920 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1921 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1922 /* fall through */
1923 case ATA_CMD_WRITE_MULTI_EXT:
1924 tf->command = ATA_CMD_PIO_WRITE_EXT;
1925 break;
1926 }
1927 }
1928 }
1929}
1930
Mark Lordda142652009-01-30 18:51:54 -05001931/**
Brett Russ05b308e2005-10-05 17:08:53 -04001932 * mv_qc_prep - Host specific command preparation.
1933 * @qc: queued command to prepare
1934 *
1935 * This routine simply redirects to the general purpose routine
1936 * if command is not DMA. Else, it handles prep of the CRQB
1937 * (command request block), does some sanity checking, and calls
1938 * the SG load routine.
1939 *
1940 * LOCKING:
1941 * Inherited from caller.
1942 */
Brett Russ31961942005-09-30 01:36:00 -04001943static void mv_qc_prep(struct ata_queued_cmd *qc)
1944{
1945 struct ata_port *ap = qc->ap;
1946 struct mv_port_priv *pp = ap->private_data;
Mark Lorde1469872006-05-22 19:02:03 -04001947 __le16 *cw;
Mark Lord8d2b4502009-04-13 11:27:18 -04001948 struct ata_taskfile *tf = &qc->tf;
Brett Russ31961942005-09-30 01:36:00 -04001949 u16 flags = 0;
Mark Lorda6432432006-05-19 16:36:36 -04001950 unsigned in_index;
Brett Russ31961942005-09-30 01:36:00 -04001951
Mark Lord299b3f82009-04-13 11:29:34 -04001952 switch (tf->protocol) {
1953 case ATA_PROT_DMA:
1954 case ATA_PROT_NCQ:
1955 break; /* continue below */
1956 case ATA_PROT_PIO:
1957 mv_rw_multi_errata_sata24(qc);
Brett Russ31961942005-09-30 01:36:00 -04001958 return;
Mark Lord299b3f82009-04-13 11:29:34 -04001959 default:
1960 return;
1961 }
Brett Russ20f733e2005-09-01 18:26:17 -04001962
Brett Russ31961942005-09-30 01:36:00 -04001963 /* Fill in command request block
1964 */
Mark Lord8d2b4502009-04-13 11:27:18 -04001965 if (!(tf->flags & ATA_TFLAG_WRITE))
Brett Russ31961942005-09-30 01:36:00 -04001966 flags |= CRQB_FLAG_READ;
Tejun Heobeec7db2006-02-11 19:11:13 +09001967 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Brett Russ31961942005-09-30 01:36:00 -04001968 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04001969 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Brett Russ31961942005-09-30 01:36:00 -04001970
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001971 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04001972 in_index = pp->req_idx;
Brett Russ31961942005-09-30 01:36:00 -04001973
Mark Lorda6432432006-05-19 16:36:36 -04001974 pp->crqb[in_index].sg_addr =
Mark Lordeb73d552008-01-29 13:24:00 -05001975 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
Mark Lorda6432432006-05-19 16:36:36 -04001976 pp->crqb[in_index].sg_addr_hi =
Mark Lordeb73d552008-01-29 13:24:00 -05001977 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Mark Lorda6432432006-05-19 16:36:36 -04001978 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1979
1980 cw = &pp->crqb[in_index].ata_cmd[0];
Brett Russ31961942005-09-30 01:36:00 -04001981
1982 /* Sadly, the CRQB cannot accomodate all registers--there are
1983 * only 11 bytes...so we must pick and choose required
1984 * registers based on the command. So, we drop feature and
1985 * hob_feature for [RW] DMA commands, but they are needed for
Mark Lordcd12e1f2009-01-19 18:06:28 -05001986 * NCQ. NCQ will drop hob_nsect, which is not needed there
1987 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
Brett Russ31961942005-09-30 01:36:00 -04001988 */
1989 switch (tf->command) {
1990 case ATA_CMD_READ:
1991 case ATA_CMD_READ_EXT:
1992 case ATA_CMD_WRITE:
1993 case ATA_CMD_WRITE_EXT:
Jens Axboec15d85c2006-02-15 15:59:25 +01001994 case ATA_CMD_WRITE_FUA_EXT:
Brett Russ31961942005-09-30 01:36:00 -04001995 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1996 break;
Brett Russ31961942005-09-30 01:36:00 -04001997 case ATA_CMD_FPDMA_READ:
1998 case ATA_CMD_FPDMA_WRITE:
Jeff Garzik8b260242005-11-12 12:32:50 -05001999 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
Brett Russ31961942005-09-30 01:36:00 -04002000 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2001 break;
Brett Russ31961942005-09-30 01:36:00 -04002002 default:
2003 /* The only other commands EDMA supports in non-queued and
2004 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2005 * of which are defined/used by Linux. If we get here, this
2006 * driver needs work.
2007 *
2008 * FIXME: modify libata to give qc_prep a return value and
2009 * return error here.
2010 */
2011 BUG_ON(tf->command);
2012 break;
2013 }
2014 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2015 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2016 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2017 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2018 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2019 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2020 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2021 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2022 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2023
Jeff Garzike4e7b892006-01-31 12:18:41 -05002024 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
Brett Russ31961942005-09-30 01:36:00 -04002025 return;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002026 mv_fill_sg(qc);
2027}
2028
2029/**
2030 * mv_qc_prep_iie - Host specific command preparation.
2031 * @qc: queued command to prepare
2032 *
2033 * This routine simply redirects to the general purpose routine
2034 * if command is not DMA. Else, it handles prep of the CRQB
2035 * (command request block), does some sanity checking, and calls
2036 * the SG load routine.
2037 *
2038 * LOCKING:
2039 * Inherited from caller.
2040 */
2041static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2042{
2043 struct ata_port *ap = qc->ap;
2044 struct mv_port_priv *pp = ap->private_data;
2045 struct mv_crqb_iie *crqb;
Mark Lord8d2b4502009-04-13 11:27:18 -04002046 struct ata_taskfile *tf = &qc->tf;
Mark Lorda6432432006-05-19 16:36:36 -04002047 unsigned in_index;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002048 u32 flags = 0;
2049
Mark Lord8d2b4502009-04-13 11:27:18 -04002050 if ((tf->protocol != ATA_PROT_DMA) &&
2051 (tf->protocol != ATA_PROT_NCQ))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002052 return;
2053
Mark Lorde12bef52008-03-31 19:33:56 -04002054 /* Fill in Gen IIE command request block */
Mark Lord8d2b4502009-04-13 11:27:18 -04002055 if (!(tf->flags & ATA_TFLAG_WRITE))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002056 flags |= CRQB_FLAG_READ;
2057
Tejun Heobeec7db2006-02-11 19:11:13 +09002058 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002059 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lord8c0aeb42008-01-26 18:31:48 -05002060 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04002061 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002062
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002063 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002064 in_index = pp->req_idx;
Mark Lorda6432432006-05-19 16:36:36 -04002065
2066 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
Mark Lordeb73d552008-01-29 13:24:00 -05002067 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2068 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002069 crqb->flags = cpu_to_le32(flags);
2070
Jeff Garzike4e7b892006-01-31 12:18:41 -05002071 crqb->ata_cmd[0] = cpu_to_le32(
2072 (tf->command << 16) |
2073 (tf->feature << 24)
2074 );
2075 crqb->ata_cmd[1] = cpu_to_le32(
2076 (tf->lbal << 0) |
2077 (tf->lbam << 8) |
2078 (tf->lbah << 16) |
2079 (tf->device << 24)
2080 );
2081 crqb->ata_cmd[2] = cpu_to_le32(
2082 (tf->hob_lbal << 0) |
2083 (tf->hob_lbam << 8) |
2084 (tf->hob_lbah << 16) |
2085 (tf->hob_feature << 24)
2086 );
2087 crqb->ata_cmd[3] = cpu_to_le32(
2088 (tf->nsect << 0) |
2089 (tf->hob_nsect << 8)
2090 );
2091
2092 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2093 return;
Brett Russ31961942005-09-30 01:36:00 -04002094 mv_fill_sg(qc);
2095}
2096
Brett Russ05b308e2005-10-05 17:08:53 -04002097/**
Mark Lordd16ab3f2009-02-25 15:17:43 -05002098 * mv_sff_check_status - fetch device status, if valid
2099 * @ap: ATA port to fetch status from
2100 *
2101 * When using command issue via mv_qc_issue_fis(),
2102 * the initial ATA_BUSY state does not show up in the
2103 * ATA status (shadow) register. This can confuse libata!
2104 *
2105 * So we have a hook here to fake ATA_BUSY for that situation,
2106 * until the first time a BUSY, DRQ, or ERR bit is seen.
2107 *
2108 * The rest of the time, it simply returns the ATA status register.
2109 */
2110static u8 mv_sff_check_status(struct ata_port *ap)
2111{
2112 u8 stat = ioread8(ap->ioaddr.status_addr);
2113 struct mv_port_priv *pp = ap->private_data;
2114
2115 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2116 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2117 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2118 else
2119 stat = ATA_BUSY;
2120 }
2121 return stat;
2122}
2123
2124/**
Mark Lord70f8b792009-02-25 15:19:20 -05002125 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2126 * @fis: fis to be sent
2127 * @nwords: number of 32-bit words in the fis
2128 */
2129static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2130{
2131 void __iomem *port_mmio = mv_ap_base(ap);
2132 u32 ifctl, old_ifctl, ifstat;
2133 int i, timeout = 200, final_word = nwords - 1;
2134
2135 /* Initiate FIS transmission mode */
Mark Lordcae5a292009-04-06 16:43:45 -04002136 old_ifctl = readl(port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002137 ifctl = 0x100 | (old_ifctl & 0xf);
Mark Lordcae5a292009-04-06 16:43:45 -04002138 writelfl(ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002139
2140 /* Send all words of the FIS except for the final word */
2141 for (i = 0; i < final_word; ++i)
Mark Lordcae5a292009-04-06 16:43:45 -04002142 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002143
2144 /* Flag end-of-transmission, and then send the final word */
Mark Lordcae5a292009-04-06 16:43:45 -04002145 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2146 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002147
2148 /*
2149 * Wait for FIS transmission to complete.
2150 * This typically takes just a single iteration.
2151 */
2152 do {
Mark Lordcae5a292009-04-06 16:43:45 -04002153 ifstat = readl(port_mmio + SATA_IFSTAT);
Mark Lord70f8b792009-02-25 15:19:20 -05002154 } while (!(ifstat & 0x1000) && --timeout);
2155
2156 /* Restore original port configuration */
Mark Lordcae5a292009-04-06 16:43:45 -04002157 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002158
2159 /* See if it worked */
2160 if ((ifstat & 0x3000) != 0x1000) {
2161 ata_port_printk(ap, KERN_WARNING,
2162 "%s transmission error, ifstat=%08x\n",
2163 __func__, ifstat);
2164 return AC_ERR_OTHER;
2165 }
2166 return 0;
2167}
2168
2169/**
2170 * mv_qc_issue_fis - Issue a command directly as a FIS
2171 * @qc: queued command to start
2172 *
2173 * Note that the ATA shadow registers are not updated
2174 * after command issue, so the device will appear "READY"
2175 * if polled, even while it is BUSY processing the command.
2176 *
2177 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2178 *
2179 * Note: we don't get updated shadow regs on *completion*
2180 * of non-data commands. So avoid sending them via this function,
2181 * as they will appear to have completed immediately.
2182 *
2183 * GEN_IIE has special registers that we could get the result tf from,
2184 * but earlier chipsets do not. For now, we ignore those registers.
2185 */
2186static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2187{
2188 struct ata_port *ap = qc->ap;
2189 struct mv_port_priv *pp = ap->private_data;
2190 struct ata_link *link = qc->dev->link;
2191 u32 fis[5];
2192 int err = 0;
2193
2194 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2195 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2196 if (err)
2197 return err;
2198
2199 switch (qc->tf.protocol) {
2200 case ATAPI_PROT_PIO:
2201 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2202 /* fall through */
2203 case ATAPI_PROT_NODATA:
2204 ap->hsm_task_state = HSM_ST_FIRST;
2205 break;
2206 case ATA_PROT_PIO:
2207 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2208 if (qc->tf.flags & ATA_TFLAG_WRITE)
2209 ap->hsm_task_state = HSM_ST_FIRST;
2210 else
2211 ap->hsm_task_state = HSM_ST;
2212 break;
2213 default:
2214 ap->hsm_task_state = HSM_ST_LAST;
2215 break;
2216 }
2217
2218 if (qc->tf.flags & ATA_TFLAG_POLLING)
2219 ata_pio_queue_task(ap, qc, 0);
2220 return 0;
2221}
2222
2223/**
Brett Russ05b308e2005-10-05 17:08:53 -04002224 * mv_qc_issue - Initiate a command to the host
2225 * @qc: queued command to start
2226 *
2227 * This routine simply redirects to the general purpose routine
2228 * if command is not DMA. Else, it sanity checks our local
2229 * caches of the request producer/consumer indices then enables
2230 * DMA and bumps the request producer index.
2231 *
2232 * LOCKING:
2233 * Inherited from caller.
2234 */
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002235static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04002236{
Mark Lordf48765c2009-01-30 18:48:41 -05002237 static int limit_warnings = 10;
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002238 struct ata_port *ap = qc->ap;
2239 void __iomem *port_mmio = mv_ap_base(ap);
2240 struct mv_port_priv *pp = ap->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002241 u32 in_index;
Mark Lord42ed8932009-02-25 15:15:39 -05002242 unsigned int port_irqs;
Brett Russ31961942005-09-30 01:36:00 -04002243
Mark Lordd16ab3f2009-02-25 15:17:43 -05002244 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2245
Mark Lordf48765c2009-01-30 18:48:41 -05002246 switch (qc->tf.protocol) {
2247 case ATA_PROT_DMA:
2248 case ATA_PROT_NCQ:
2249 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2250 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2251 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2252
2253 /* Write the request in pointer to kick the EDMA to life */
2254 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
Mark Lordcae5a292009-04-06 16:43:45 -04002255 port_mmio + EDMA_REQ_Q_IN_PTR);
Mark Lordf48765c2009-01-30 18:48:41 -05002256 return 0;
2257
2258 case ATA_PROT_PIO:
Mark Lordc6112bd2008-06-18 12:13:02 -04002259 /*
2260 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2261 *
2262 * Someday, we might implement special polling workarounds
2263 * for these, but it all seems rather unnecessary since we
2264 * normally use only DMA for commands which transfer more
2265 * than a single block of data.
2266 *
2267 * Much of the time, this could just work regardless.
2268 * So for now, just log the incident, and allow the attempt.
2269 */
Mark Lordc7843e82008-06-18 21:57:42 -04002270 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
Mark Lordc6112bd2008-06-18 12:13:02 -04002271 --limit_warnings;
2272 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2273 ": attempting PIO w/multiple DRQ: "
2274 "this may fail due to h/w errata\n");
2275 }
Mark Lordf48765c2009-01-30 18:48:41 -05002276 /* drop through */
Mark Lord42ed8932009-02-25 15:15:39 -05002277 case ATA_PROT_NODATA:
Mark Lordf48765c2009-01-30 18:48:41 -05002278 case ATAPI_PROT_PIO:
Mark Lord42ed8932009-02-25 15:15:39 -05002279 case ATAPI_PROT_NODATA:
2280 if (ap->flags & ATA_FLAG_PIO_POLLING)
2281 qc->tf.flags |= ATA_TFLAG_POLLING;
2282 break;
Brett Russ31961942005-09-30 01:36:00 -04002283 }
Mark Lord42ed8932009-02-25 15:15:39 -05002284
2285 if (qc->tf.flags & ATA_TFLAG_POLLING)
2286 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2287 else
2288 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2289
2290 /*
2291 * We're about to send a non-EDMA capable command to the
2292 * port. Turn off EDMA so there won't be problems accessing
2293 * shadow block, etc registers.
2294 */
2295 mv_stop_edma(ap);
2296 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2297 mv_pmp_select(ap, qc->dev->link->pmp);
Mark Lord70f8b792009-02-25 15:19:20 -05002298
2299 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2300 struct mv_host_priv *hpriv = ap->host->private_data;
2301 /*
2302 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
Mark Lord40f21b12009-03-10 18:51:04 -04002303 *
Mark Lord70f8b792009-02-25 15:19:20 -05002304 * After any NCQ error, the READ_LOG_EXT command
2305 * from libata-eh *must* use mv_qc_issue_fis().
2306 * Otherwise it might fail, due to chip errata.
2307 *
2308 * Rather than special-case it, we'll just *always*
2309 * use this method here for READ_LOG_EXT, making for
2310 * easier testing.
2311 */
2312 if (IS_GEN_II(hpriv))
2313 return mv_qc_issue_fis(qc);
2314 }
Mark Lord42ed8932009-02-25 15:15:39 -05002315 return ata_sff_qc_issue(qc);
Brett Russ31961942005-09-30 01:36:00 -04002316}
2317
Mark Lord8f767f82008-04-19 14:53:07 -04002318static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2319{
2320 struct mv_port_priv *pp = ap->private_data;
2321 struct ata_queued_cmd *qc;
2322
2323 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2324 return NULL;
2325 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Mark Lord95db5052009-01-30 18:49:29 -05002326 if (qc) {
2327 if (qc->tf.flags & ATA_TFLAG_POLLING)
2328 qc = NULL;
2329 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2330 qc = NULL;
2331 }
Mark Lord8f767f82008-04-19 14:53:07 -04002332 return qc;
2333}
2334
Mark Lord29d187b2008-05-02 02:15:37 -04002335static void mv_pmp_error_handler(struct ata_port *ap)
2336{
2337 unsigned int pmp, pmp_map;
2338 struct mv_port_priv *pp = ap->private_data;
2339
2340 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2341 /*
2342 * Perform NCQ error analysis on failed PMPs
2343 * before we freeze the port entirely.
2344 *
2345 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2346 */
2347 pmp_map = pp->delayed_eh_pmp_map;
2348 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2349 for (pmp = 0; pmp_map != 0; pmp++) {
2350 unsigned int this_pmp = (1 << pmp);
2351 if (pmp_map & this_pmp) {
2352 struct ata_link *link = &ap->pmp_link[pmp];
2353 pmp_map &= ~this_pmp;
2354 ata_eh_analyze_ncq_error(link);
2355 }
2356 }
2357 ata_port_freeze(ap);
2358 }
2359 sata_pmp_error_handler(ap);
2360}
2361
Mark Lord4c299ca2008-05-02 02:16:20 -04002362static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2363{
2364 void __iomem *port_mmio = mv_ap_base(ap);
2365
Mark Lordcae5a292009-04-06 16:43:45 -04002366 return readl(port_mmio + SATA_TESTCTL) >> 16;
Mark Lord4c299ca2008-05-02 02:16:20 -04002367}
2368
Mark Lord4c299ca2008-05-02 02:16:20 -04002369static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2370{
2371 struct ata_eh_info *ehi;
2372 unsigned int pmp;
2373
2374 /*
2375 * Initialize EH info for PMPs which saw device errors
2376 */
2377 ehi = &ap->link.eh_info;
2378 for (pmp = 0; pmp_map != 0; pmp++) {
2379 unsigned int this_pmp = (1 << pmp);
2380 if (pmp_map & this_pmp) {
2381 struct ata_link *link = &ap->pmp_link[pmp];
2382
2383 pmp_map &= ~this_pmp;
2384 ehi = &link->eh_info;
2385 ata_ehi_clear_desc(ehi);
2386 ata_ehi_push_desc(ehi, "dev err");
2387 ehi->err_mask |= AC_ERR_DEV;
2388 ehi->action |= ATA_EH_RESET;
2389 ata_link_abort(link);
2390 }
2391 }
2392}
2393
Mark Lord06aaca32008-05-19 09:01:24 -04002394static int mv_req_q_empty(struct ata_port *ap)
2395{
2396 void __iomem *port_mmio = mv_ap_base(ap);
2397 u32 in_ptr, out_ptr;
2398
Mark Lordcae5a292009-04-06 16:43:45 -04002399 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002400 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
Mark Lordcae5a292009-04-06 16:43:45 -04002401 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002402 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2403 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2404}
2405
Mark Lord4c299ca2008-05-02 02:16:20 -04002406static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2407{
2408 struct mv_port_priv *pp = ap->private_data;
2409 int failed_links;
2410 unsigned int old_map, new_map;
2411
2412 /*
2413 * Device error during FBS+NCQ operation:
2414 *
2415 * Set a port flag to prevent further I/O being enqueued.
2416 * Leave the EDMA running to drain outstanding commands from this port.
2417 * Perform the post-mortem/EH only when all responses are complete.
2418 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2419 */
2420 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2421 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2422 pp->delayed_eh_pmp_map = 0;
2423 }
2424 old_map = pp->delayed_eh_pmp_map;
2425 new_map = old_map | mv_get_err_pmp_map(ap);
2426
2427 if (old_map != new_map) {
2428 pp->delayed_eh_pmp_map = new_map;
2429 mv_pmp_eh_prep(ap, new_map & ~old_map);
2430 }
Mark Lordc46938c2008-05-02 14:02:28 -04002431 failed_links = hweight16(new_map);
Mark Lord4c299ca2008-05-02 02:16:20 -04002432
2433 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2434 "failed_links=%d nr_active_links=%d\n",
2435 __func__, pp->delayed_eh_pmp_map,
2436 ap->qc_active, failed_links,
2437 ap->nr_active_links);
2438
Mark Lord06aaca32008-05-19 09:01:24 -04002439 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
Mark Lord4c299ca2008-05-02 02:16:20 -04002440 mv_process_crpb_entries(ap, pp);
2441 mv_stop_edma(ap);
2442 mv_eh_freeze(ap);
2443 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2444 return 1; /* handled */
2445 }
2446 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2447 return 1; /* handled */
2448}
2449
2450static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2451{
2452 /*
2453 * Possible future enhancement:
2454 *
2455 * FBS+non-NCQ operation is not yet implemented.
2456 * See related notes in mv_edma_cfg().
2457 *
2458 * Device error during FBS+non-NCQ operation:
2459 *
2460 * We need to snapshot the shadow registers for each failed command.
2461 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2462 */
2463 return 0; /* not handled */
2464}
2465
2466static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2467{
2468 struct mv_port_priv *pp = ap->private_data;
2469
2470 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2471 return 0; /* EDMA was not active: not handled */
2472 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2473 return 0; /* FBS was not active: not handled */
2474
2475 if (!(edma_err_cause & EDMA_ERR_DEV))
2476 return 0; /* non DEV error: not handled */
2477 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2478 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2479 return 0; /* other problems: not handled */
2480
2481 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2482 /*
2483 * EDMA should NOT have self-disabled for this case.
2484 * If it did, then something is wrong elsewhere,
2485 * and we cannot handle it here.
2486 */
2487 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2488 ata_port_printk(ap, KERN_WARNING,
2489 "%s: err_cause=0x%x pp_flags=0x%x\n",
2490 __func__, edma_err_cause, pp->pp_flags);
2491 return 0; /* not handled */
2492 }
2493 return mv_handle_fbs_ncq_dev_err(ap);
2494 } else {
2495 /*
2496 * EDMA should have self-disabled for this case.
2497 * If it did not, then something is wrong elsewhere,
2498 * and we cannot handle it here.
2499 */
2500 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2501 ata_port_printk(ap, KERN_WARNING,
2502 "%s: err_cause=0x%x pp_flags=0x%x\n",
2503 __func__, edma_err_cause, pp->pp_flags);
2504 return 0; /* not handled */
2505 }
2506 return mv_handle_fbs_non_ncq_dev_err(ap);
2507 }
2508 return 0; /* not handled */
2509}
2510
Mark Lorda9010322008-05-02 02:14:02 -04002511static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
Mark Lord8f767f82008-04-19 14:53:07 -04002512{
Mark Lord8f767f82008-04-19 14:53:07 -04002513 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lorda9010322008-05-02 02:14:02 -04002514 char *when = "idle";
Mark Lord8f767f82008-04-19 14:53:07 -04002515
Mark Lord8f767f82008-04-19 14:53:07 -04002516 ata_ehi_clear_desc(ehi);
Mark Lorda9010322008-05-02 02:14:02 -04002517 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2518 when = "disabled";
2519 } else if (edma_was_enabled) {
2520 when = "EDMA enabled";
Mark Lord8f767f82008-04-19 14:53:07 -04002521 } else {
2522 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2523 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
Mark Lorda9010322008-05-02 02:14:02 -04002524 when = "polling";
Mark Lord8f767f82008-04-19 14:53:07 -04002525 }
Mark Lorda9010322008-05-02 02:14:02 -04002526 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
Mark Lord8f767f82008-04-19 14:53:07 -04002527 ehi->err_mask |= AC_ERR_OTHER;
2528 ehi->action |= ATA_EH_RESET;
2529 ata_port_freeze(ap);
2530}
2531
Brett Russ05b308e2005-10-05 17:08:53 -04002532/**
Brett Russ05b308e2005-10-05 17:08:53 -04002533 * mv_err_intr - Handle error interrupts on the port
2534 * @ap: ATA channel to manipulate
2535 *
Mark Lord8d073792008-04-19 15:07:49 -04002536 * Most cases require a full reset of the chip's state machine,
2537 * which also performs a COMRESET.
2538 * Also, if the port disabled DMA, update our cached copy to match.
Brett Russ05b308e2005-10-05 17:08:53 -04002539 *
2540 * LOCKING:
2541 * Inherited from caller.
2542 */
Mark Lord37b90462008-05-02 02:12:34 -04002543static void mv_err_intr(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04002544{
Brett Russ31961942005-09-30 01:36:00 -04002545 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002546 u32 edma_err_cause, eh_freeze_mask, serr = 0;
Mark Lorde4006072008-05-14 09:19:30 -04002547 u32 fis_cause = 0;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002548 struct mv_port_priv *pp = ap->private_data;
2549 struct mv_host_priv *hpriv = ap->host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002550 unsigned int action = 0, err_mask = 0;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002551 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lord37b90462008-05-02 02:12:34 -04002552 struct ata_queued_cmd *qc;
2553 int abort = 0;
Brett Russ20f733e2005-09-01 18:26:17 -04002554
Mark Lord8d073792008-04-19 15:07:49 -04002555 /*
Mark Lord37b90462008-05-02 02:12:34 -04002556 * Read and clear the SError and err_cause bits.
Mark Lorde4006072008-05-14 09:19:30 -04002557 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2558 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
Mark Lord8d073792008-04-19 15:07:49 -04002559 */
Mark Lord37b90462008-05-02 02:12:34 -04002560 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2561 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2562
Mark Lordcae5a292009-04-06 16:43:45 -04002563 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002564 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lordcae5a292009-04-06 16:43:45 -04002565 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2566 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002567 }
Mark Lordcae5a292009-04-06 16:43:45 -04002568 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002569
Mark Lord4c299ca2008-05-02 02:16:20 -04002570 if (edma_err_cause & EDMA_ERR_DEV) {
2571 /*
2572 * Device errors during FIS-based switching operation
2573 * require special handling.
2574 */
2575 if (mv_handle_dev_err(ap, edma_err_cause))
2576 return;
2577 }
2578
Mark Lord37b90462008-05-02 02:12:34 -04002579 qc = mv_get_active_qc(ap);
2580 ata_ehi_clear_desc(ehi);
2581 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2582 edma_err_cause, pp->pp_flags);
Mark Lorde4006072008-05-14 09:19:30 -04002583
Mark Lordc443c502008-05-14 09:24:39 -04002584 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lorde4006072008-05-14 09:19:30 -04002585 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
Mark Lordcae5a292009-04-06 16:43:45 -04002586 if (fis_cause & FIS_IRQ_CAUSE_AN) {
Mark Lordc443c502008-05-14 09:24:39 -04002587 u32 ec = edma_err_cause &
2588 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2589 sata_async_notification(ap);
2590 if (!ec)
2591 return; /* Just an AN; no need for the nukes */
2592 ata_ehi_push_desc(ehi, "SDB notify");
2593 }
2594 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002595 /*
Mark Lord352fab72008-04-19 14:43:42 -04002596 * All generations share these EDMA error cause bits:
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002597 */
Mark Lord37b90462008-05-02 02:12:34 -04002598 if (edma_err_cause & EDMA_ERR_DEV) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002599 err_mask |= AC_ERR_DEV;
Mark Lord37b90462008-05-02 02:12:34 -04002600 action |= ATA_EH_RESET;
2601 ata_ehi_push_desc(ehi, "dev error");
2602 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002603 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002604 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002605 EDMA_ERR_INTRL_PAR)) {
2606 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002607 action |= ATA_EH_RESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09002608 ata_ehi_push_desc(ehi, "parity error");
Brett Russafb0edd2005-10-05 17:08:42 -04002609 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002610 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2611 ata_ehi_hotplugged(ehi);
2612 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
Tejun Heob64bbc32007-07-16 14:29:39 +09002613 "dev disconnect" : "dev connect");
Tejun Heocf480622008-01-24 00:05:14 +09002614 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002615 }
2616
Mark Lord352fab72008-04-19 14:43:42 -04002617 /*
2618 * Gen-I has a different SELF_DIS bit,
2619 * different FREEZE bits, and no SERR bit:
2620 */
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002621 if (IS_GEN_I(hpriv)) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002622 eh_freeze_mask = EDMA_EH_FREEZE_5;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002623 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002624 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002625 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002626 }
2627 } else {
2628 eh_freeze_mask = EDMA_EH_FREEZE;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002629 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002630 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002631 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002632 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002633 if (edma_err_cause & EDMA_ERR_SERR) {
Mark Lord8d073792008-04-19 15:07:49 -04002634 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2635 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002636 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002637 }
2638 }
Brett Russ20f733e2005-09-01 18:26:17 -04002639
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002640 if (!err_mask) {
2641 err_mask = AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09002642 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002643 }
2644
2645 ehi->serror |= serr;
2646 ehi->action |= action;
2647
2648 if (qc)
2649 qc->err_mask |= err_mask;
2650 else
2651 ehi->err_mask |= err_mask;
2652
Mark Lord37b90462008-05-02 02:12:34 -04002653 if (err_mask == AC_ERR_DEV) {
2654 /*
2655 * Cannot do ata_port_freeze() here,
2656 * because it would kill PIO access,
2657 * which is needed for further diagnosis.
2658 */
2659 mv_eh_freeze(ap);
2660 abort = 1;
2661 } else if (edma_err_cause & eh_freeze_mask) {
2662 /*
2663 * Note to self: ata_port_freeze() calls ata_port_abort()
2664 */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002665 ata_port_freeze(ap);
Mark Lord37b90462008-05-02 02:12:34 -04002666 } else {
2667 abort = 1;
2668 }
2669
2670 if (abort) {
2671 if (qc)
2672 ata_link_abort(qc->dev->link);
2673 else
2674 ata_port_abort(ap);
2675 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002676}
2677
Mark Lordfcfb1f72008-04-19 15:06:40 -04002678static void mv_process_crpb_response(struct ata_port *ap,
2679 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2680{
2681 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2682
2683 if (qc) {
2684 u8 ata_status;
2685 u16 edma_status = le16_to_cpu(response->flags);
2686 /*
2687 * edma_status from a response queue entry:
Mark Lordcae5a292009-04-06 16:43:45 -04002688 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
Mark Lordfcfb1f72008-04-19 15:06:40 -04002689 * MSB is saved ATA status from command completion.
2690 */
2691 if (!ncq_enabled) {
2692 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2693 if (err_cause) {
2694 /*
2695 * Error will be seen/handled by mv_err_intr().
2696 * So do nothing at all here.
2697 */
2698 return;
2699 }
2700 }
2701 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
Mark Lord37b90462008-05-02 02:12:34 -04002702 if (!ac_err_mask(ata_status))
2703 ata_qc_complete(qc);
2704 /* else: leave it for mv_err_intr() */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002705 } else {
2706 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2707 __func__, tag);
2708 }
2709}
2710
2711static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002712{
2713 void __iomem *port_mmio = mv_ap_base(ap);
2714 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002715 u32 in_index;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002716 bool work_done = false;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002717 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002718
Mark Lordfcfb1f72008-04-19 15:06:40 -04002719 /* Get the hardware queue position index */
Mark Lordcae5a292009-04-06 16:43:45 -04002720 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002721 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2722
Mark Lordfcfb1f72008-04-19 15:06:40 -04002723 /* Process new responses from since the last time we looked */
2724 while (in_index != pp->resp_idx) {
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002725 unsigned int tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002726 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002727
Mark Lordfcfb1f72008-04-19 15:06:40 -04002728 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002729
Mark Lordfcfb1f72008-04-19 15:06:40 -04002730 if (IS_GEN_I(hpriv)) {
2731 /* 50xx: no NCQ, only one command active at a time */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002732 tag = ap->link.active_tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002733 } else {
2734 /* Gen II/IIE: get command tag from CRPB entry */
2735 tag = le16_to_cpu(response->id) & 0x1f;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002736 }
Mark Lordfcfb1f72008-04-19 15:06:40 -04002737 mv_process_crpb_response(ap, response, tag, ncq_enabled);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002738 work_done = true;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002739 }
2740
Mark Lord352fab72008-04-19 14:43:42 -04002741 /* Update the software queue position index in hardware */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002742 if (work_done)
2743 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
Mark Lordfcfb1f72008-04-19 15:06:40 -04002744 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
Mark Lordcae5a292009-04-06 16:43:45 -04002745 port_mmio + EDMA_RSP_Q_OUT_PTR);
Brett Russ20f733e2005-09-01 18:26:17 -04002746}
2747
Mark Lorda9010322008-05-02 02:14:02 -04002748static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2749{
2750 struct mv_port_priv *pp;
2751 int edma_was_enabled;
2752
2753 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2754 mv_unexpected_intr(ap, 0);
2755 return;
2756 }
2757 /*
2758 * Grab a snapshot of the EDMA_EN flag setting,
2759 * so that we have a consistent view for this port,
2760 * even if something we call of our routines changes it.
2761 */
2762 pp = ap->private_data;
2763 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2764 /*
2765 * Process completed CRPB response(s) before other events.
2766 */
2767 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2768 mv_process_crpb_entries(ap, pp);
Mark Lord4c299ca2008-05-02 02:16:20 -04002769 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2770 mv_handle_fbs_ncq_dev_err(ap);
Mark Lorda9010322008-05-02 02:14:02 -04002771 }
2772 /*
2773 * Handle chip-reported errors, or continue on to handle PIO.
2774 */
2775 if (unlikely(port_cause & ERR_IRQ)) {
2776 mv_err_intr(ap);
2777 } else if (!edma_was_enabled) {
2778 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2779 if (qc)
2780 ata_sff_host_intr(ap, qc);
2781 else
2782 mv_unexpected_intr(ap, edma_was_enabled);
2783 }
2784}
2785
Brett Russ05b308e2005-10-05 17:08:53 -04002786/**
2787 * mv_host_intr - Handle all interrupts on the given host controller
Jeff Garzikcca39742006-08-24 03:19:22 -04002788 * @host: host specific structure
Mark Lord7368f912008-04-25 11:24:24 -04002789 * @main_irq_cause: Main interrupt cause register for the chip.
Brett Russ05b308e2005-10-05 17:08:53 -04002790 *
2791 * LOCKING:
2792 * Inherited from caller.
2793 */
Mark Lord7368f912008-04-25 11:24:24 -04002794static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
Brett Russ20f733e2005-09-01 18:26:17 -04002795{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002796 struct mv_host_priv *hpriv = host->private_data;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002797 void __iomem *mmio = hpriv->base, *hc_mmio;
Mark Lorda3718c12008-04-19 15:07:18 -04002798 unsigned int handled = 0, port;
Brett Russ20f733e2005-09-01 18:26:17 -04002799
Mark Lord2b748a02009-03-10 22:01:17 -04002800 /* If asserted, clear the "all ports" IRQ coalescing bit */
2801 if (main_irq_cause & ALL_PORTS_COAL_DONE)
Mark Lordcae5a292009-04-06 16:43:45 -04002802 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord2b748a02009-03-10 22:01:17 -04002803
Mark Lorda3718c12008-04-19 15:07:18 -04002804 for (port = 0; port < hpriv->n_ports; port++) {
Jeff Garzikcca39742006-08-24 03:19:22 -04002805 struct ata_port *ap = host->ports[port];
Mark Lordeabd5eb2008-05-02 02:13:27 -04002806 unsigned int p, shift, hardport, port_cause;
2807
Mark Lorda3718c12008-04-19 15:07:18 -04002808 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
Mark Lorda3718c12008-04-19 15:07:18 -04002809 /*
Mark Lordeabd5eb2008-05-02 02:13:27 -04002810 * Each hc within the host has its own hc_irq_cause register,
2811 * where the interrupting ports bits get ack'd.
Mark Lorda3718c12008-04-19 15:07:18 -04002812 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002813 if (hardport == 0) { /* first port on this hc ? */
2814 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2815 u32 port_mask, ack_irqs;
2816 /*
2817 * Skip this entire hc if nothing pending for any ports
2818 */
2819 if (!hc_cause) {
2820 port += MV_PORTS_PER_HC - 1;
2821 continue;
2822 }
2823 /*
2824 * We don't need/want to read the hc_irq_cause register,
2825 * because doing so hurts performance, and
2826 * main_irq_cause already gives us everything we need.
2827 *
2828 * But we do have to *write* to the hc_irq_cause to ack
2829 * the ports that we are handling this time through.
2830 *
2831 * This requires that we create a bitmap for those
2832 * ports which interrupted us, and use that bitmap
2833 * to ack (only) those ports via hc_irq_cause.
2834 */
2835 ack_irqs = 0;
Mark Lord2b748a02009-03-10 22:01:17 -04002836 if (hc_cause & PORTS_0_3_COAL_DONE)
2837 ack_irqs = HC_COAL_IRQ;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002838 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2839 if ((port + p) >= hpriv->n_ports)
2840 break;
2841 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2842 if (hc_cause & port_mask)
2843 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2844 }
Mark Lorda3718c12008-04-19 15:07:18 -04002845 hc_mmio = mv_hc_base_from_port(mmio, port);
Mark Lordcae5a292009-04-06 16:43:45 -04002846 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
Mark Lorda3718c12008-04-19 15:07:18 -04002847 handled = 1;
2848 }
Mark Lorda9010322008-05-02 02:14:02 -04002849 /*
2850 * Handle interrupts signalled for this port:
2851 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002852 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
Mark Lorda9010322008-05-02 02:14:02 -04002853 if (port_cause)
2854 mv_port_intr(ap, port_cause);
Brett Russ20f733e2005-09-01 18:26:17 -04002855 }
Mark Lorda3718c12008-04-19 15:07:18 -04002856 return handled;
Brett Russ20f733e2005-09-01 18:26:17 -04002857}
2858
Mark Lorda3718c12008-04-19 15:07:18 -04002859static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002860{
Mark Lord02a121d2007-12-01 13:07:22 -05002861 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002862 struct ata_port *ap;
2863 struct ata_queued_cmd *qc;
2864 struct ata_eh_info *ehi;
2865 unsigned int i, err_mask, printed = 0;
2866 u32 err_cause;
2867
Mark Lordcae5a292009-04-06 16:43:45 -04002868 err_cause = readl(mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002869
2870 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2871 err_cause);
2872
2873 DPRINTK("All regs @ PCI error\n");
2874 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2875
Mark Lordcae5a292009-04-06 16:43:45 -04002876 writelfl(0, mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002877
2878 for (i = 0; i < host->n_ports; i++) {
2879 ap = host->ports[i];
Tejun Heo936fd732007-08-06 18:36:23 +09002880 if (!ata_link_offline(&ap->link)) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002881 ehi = &ap->link.eh_info;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002882 ata_ehi_clear_desc(ehi);
2883 if (!printed++)
2884 ata_ehi_push_desc(ehi,
2885 "PCI err cause 0x%08x", err_cause);
2886 err_mask = AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002887 ehi->action = ATA_EH_RESET;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002888 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002889 if (qc)
2890 qc->err_mask |= err_mask;
2891 else
2892 ehi->err_mask |= err_mask;
2893
2894 ata_port_freeze(ap);
2895 }
2896 }
Mark Lorda3718c12008-04-19 15:07:18 -04002897 return 1; /* handled */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002898}
2899
Brett Russ05b308e2005-10-05 17:08:53 -04002900/**
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002901 * mv_interrupt - Main interrupt event handler
Brett Russ05b308e2005-10-05 17:08:53 -04002902 * @irq: unused
2903 * @dev_instance: private data; in this case the host structure
Brett Russ05b308e2005-10-05 17:08:53 -04002904 *
2905 * Read the read only register to determine if any host
2906 * controllers have pending interrupts. If so, call lower level
2907 * routine to handle. Also check for PCI errors which are only
2908 * reported here.
2909 *
Jeff Garzik8b260242005-11-12 12:32:50 -05002910 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04002911 * This routine holds the host lock while processing pending
Brett Russ05b308e2005-10-05 17:08:53 -04002912 * interrupts.
2913 */
David Howells7d12e782006-10-05 14:55:46 +01002914static irqreturn_t mv_interrupt(int irq, void *dev_instance)
Brett Russ20f733e2005-09-01 18:26:17 -04002915{
Jeff Garzikcca39742006-08-24 03:19:22 -04002916 struct ata_host *host = dev_instance;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002917 struct mv_host_priv *hpriv = host->private_data;
Mark Lorda3718c12008-04-19 15:07:18 -04002918 unsigned int handled = 0;
Mark Lord6d3c30e2009-01-21 10:31:29 -05002919 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
Mark Lord96e2c4872008-05-17 13:38:00 -04002920 u32 main_irq_cause, pending_irqs;
Brett Russ20f733e2005-09-01 18:26:17 -04002921
Mark Lord646a4da2008-01-26 18:30:37 -05002922 spin_lock(&host->lock);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002923
2924 /* for MSI: block new interrupts while in here */
2925 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04002926 mv_write_main_irq_mask(0, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002927
Mark Lord7368f912008-04-25 11:24:24 -04002928 main_irq_cause = readl(hpriv->main_irq_cause_addr);
Mark Lord96e2c4872008-05-17 13:38:00 -04002929 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
Mark Lord352fab72008-04-19 14:43:42 -04002930 /*
2931 * Deal with cases where we either have nothing pending, or have read
2932 * a bogus register value which can indicate HW removal or PCI fault.
Brett Russ20f733e2005-09-01 18:26:17 -04002933 */
Mark Lorda44253d2008-05-17 13:37:07 -04002934 if (pending_irqs && main_irq_cause != 0xffffffffU) {
Mark Lord1f398472008-05-27 17:54:48 -04002935 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
Mark Lorda3718c12008-04-19 15:07:18 -04002936 handled = mv_pci_error(host, hpriv->base);
2937 else
Mark Lorda44253d2008-05-17 13:37:07 -04002938 handled = mv_host_intr(host, pending_irqs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002939 }
Mark Lord6d3c30e2009-01-21 10:31:29 -05002940
2941 /* for MSI: unmask; interrupt cause bits will retrigger now */
2942 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04002943 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002944
Mark Lord9d51af72009-03-10 16:28:51 -04002945 spin_unlock(&host->lock);
2946
Brett Russ20f733e2005-09-01 18:26:17 -04002947 return IRQ_RETVAL(handled);
2948}
2949
Jeff Garzikc9d39132005-11-13 17:47:51 -05002950static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2951{
2952 unsigned int ofs;
2953
2954 switch (sc_reg_in) {
2955 case SCR_STATUS:
2956 case SCR_ERROR:
2957 case SCR_CONTROL:
2958 ofs = sc_reg_in * sizeof(u32);
2959 break;
2960 default:
2961 ofs = 0xffffffffU;
2962 break;
2963 }
2964 return ofs;
2965}
2966
Tejun Heo82ef04f2008-07-31 17:02:40 +09002967static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05002968{
Tejun Heo82ef04f2008-07-31 17:02:40 +09002969 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002970 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002971 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002972 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2973
Tejun Heoda3dbb12007-07-16 14:29:40 +09002974 if (ofs != 0xffffffffU) {
2975 *val = readl(addr + ofs);
2976 return 0;
2977 } else
2978 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05002979}
2980
Tejun Heo82ef04f2008-07-31 17:02:40 +09002981static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05002982{
Tejun Heo82ef04f2008-07-31 17:02:40 +09002983 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002984 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002985 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05002986 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2987
Tejun Heoda3dbb12007-07-16 14:29:40 +09002988 if (ofs != 0xffffffffU) {
Tejun Heo0d5ff562007-02-01 15:06:36 +09002989 writelfl(val, addr + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09002990 return 0;
2991 } else
2992 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05002993}
2994
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002995static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik522479f2005-11-12 22:14:02 -05002996{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11002997 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzik522479f2005-11-12 22:14:02 -05002998 int early_5080;
2999
Auke Kok44c10132007-06-08 15:46:36 -07003000 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
Jeff Garzik522479f2005-11-12 22:14:02 -05003001
3002 if (!early_5080) {
3003 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3004 tmp |= (1 << 0);
3005 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3006 }
3007
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003008 mv_reset_pci_bus(host, mmio);
Jeff Garzik522479f2005-11-12 22:14:02 -05003009}
3010
3011static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3012{
Mark Lordcae5a292009-04-06 16:43:45 -04003013 writel(0x0fcfffff, mmio + FLASH_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003014}
3015
Jeff Garzik47c2b672005-11-12 21:13:17 -05003016static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003017 void __iomem *mmio)
3018{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003019 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3020 u32 tmp;
3021
3022 tmp = readl(phy_mmio + MV5_PHY_MODE);
3023
3024 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3025 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003026}
3027
Jeff Garzik47c2b672005-11-12 21:13:17 -05003028static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003029{
Jeff Garzik522479f2005-11-12 22:14:02 -05003030 u32 tmp;
3031
Mark Lordcae5a292009-04-06 16:43:45 -04003032 writel(0, mmio + GPIO_PORT_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003033
3034 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3035
3036 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3037 tmp |= ~(1 << 0);
3038 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003039}
3040
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003041static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3042 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003043{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003044 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3045 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3046 u32 tmp;
3047 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3048
3049 if (fix_apm_sq) {
Mark Lordcae5a292009-04-06 16:43:45 -04003050 tmp = readl(phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003051 tmp |= (1 << 19);
Mark Lordcae5a292009-04-06 16:43:45 -04003052 writel(tmp, phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003053
Mark Lordcae5a292009-04-06 16:43:45 -04003054 tmp = readl(phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003055 tmp &= ~0x3;
3056 tmp |= 0x1;
Mark Lordcae5a292009-04-06 16:43:45 -04003057 writel(tmp, phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003058 }
3059
3060 tmp = readl(phy_mmio + MV5_PHY_MODE);
3061 tmp &= ~mask;
3062 tmp |= hpriv->signal[port].pre;
3063 tmp |= hpriv->signal[port].amps;
3064 writel(tmp, phy_mmio + MV5_PHY_MODE);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003065}
3066
Jeff Garzikc9d39132005-11-13 17:47:51 -05003067
3068#undef ZERO
3069#define ZERO(reg) writel(0, port_mmio + (reg))
3070static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3071 unsigned int port)
Jeff Garzik47c2b672005-11-12 21:13:17 -05003072{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003073 void __iomem *port_mmio = mv_port_base(mmio, port);
3074
Mark Lorde12bef52008-03-31 19:33:56 -04003075 mv_reset_channel(hpriv, mmio, port);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003076
3077 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003078 writel(0x11f, port_mmio + EDMA_CFG);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003079 ZERO(0x004); /* timer */
3080 ZERO(0x008); /* irq err cause */
3081 ZERO(0x00c); /* irq err mask */
3082 ZERO(0x010); /* rq bah */
3083 ZERO(0x014); /* rq inp */
3084 ZERO(0x018); /* rq outp */
3085 ZERO(0x01c); /* respq bah */
3086 ZERO(0x024); /* respq outp */
3087 ZERO(0x020); /* respq inp */
3088 ZERO(0x02c); /* test control */
Mark Lordcae5a292009-04-06 16:43:45 -04003089 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003090}
3091#undef ZERO
3092
3093#define ZERO(reg) writel(0, hc_mmio + (reg))
3094static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3095 unsigned int hc)
3096{
3097 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3098 u32 tmp;
3099
3100 ZERO(0x00c);
3101 ZERO(0x010);
3102 ZERO(0x014);
3103 ZERO(0x018);
3104
3105 tmp = readl(hc_mmio + 0x20);
3106 tmp &= 0x1c1c1c1c;
3107 tmp |= 0x03030303;
3108 writel(tmp, hc_mmio + 0x20);
3109}
3110#undef ZERO
3111
3112static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3113 unsigned int n_hc)
3114{
3115 unsigned int hc, port;
3116
3117 for (hc = 0; hc < n_hc; hc++) {
3118 for (port = 0; port < MV_PORTS_PER_HC; port++)
3119 mv5_reset_hc_port(hpriv, mmio,
3120 (hc * MV_PORTS_PER_HC) + port);
3121
3122 mv5_reset_one_hc(hpriv, mmio, hc);
3123 }
3124
3125 return 0;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003126}
3127
Jeff Garzik101ffae2005-11-12 22:17:49 -05003128#undef ZERO
3129#define ZERO(reg) writel(0, mmio + (reg))
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003130static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003131{
Mark Lord02a121d2007-12-01 13:07:22 -05003132 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003133 u32 tmp;
3134
Mark Lordcae5a292009-04-06 16:43:45 -04003135 tmp = readl(mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003136 tmp &= 0xff00ffff;
Mark Lordcae5a292009-04-06 16:43:45 -04003137 writel(tmp, mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003138
3139 ZERO(MV_PCI_DISC_TIMER);
3140 ZERO(MV_PCI_MSI_TRIGGER);
Mark Lordcae5a292009-04-06 16:43:45 -04003141 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003142 ZERO(MV_PCI_SERR_MASK);
Mark Lordcae5a292009-04-06 16:43:45 -04003143 ZERO(hpriv->irq_cause_offset);
3144 ZERO(hpriv->irq_mask_offset);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003145 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3146 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3147 ZERO(MV_PCI_ERR_ATTRIBUTE);
3148 ZERO(MV_PCI_ERR_COMMAND);
3149}
3150#undef ZERO
3151
3152static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3153{
3154 u32 tmp;
3155
3156 mv5_reset_flash(hpriv, mmio);
3157
Mark Lordcae5a292009-04-06 16:43:45 -04003158 tmp = readl(mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003159 tmp &= 0x3;
3160 tmp |= (1 << 5) | (1 << 6);
Mark Lordcae5a292009-04-06 16:43:45 -04003161 writel(tmp, mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003162}
3163
3164/**
3165 * mv6_reset_hc - Perform the 6xxx global soft reset
3166 * @mmio: base address of the HBA
3167 *
3168 * This routine only applies to 6xxx parts.
3169 *
3170 * LOCKING:
3171 * Inherited from caller.
3172 */
Jeff Garzikc9d39132005-11-13 17:47:51 -05003173static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3174 unsigned int n_hc)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003175{
Mark Lordcae5a292009-04-06 16:43:45 -04003176 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003177 int i, rc = 0;
3178 u32 t;
3179
3180 /* Following procedure defined in PCI "main command and status
3181 * register" table.
3182 */
3183 t = readl(reg);
3184 writel(t | STOP_PCI_MASTER, reg);
3185
3186 for (i = 0; i < 1000; i++) {
3187 udelay(1);
3188 t = readl(reg);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04003189 if (PCI_MASTER_EMPTY & t)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003190 break;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003191 }
3192 if (!(PCI_MASTER_EMPTY & t)) {
3193 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3194 rc = 1;
3195 goto done;
3196 }
3197
3198 /* set reset */
3199 i = 5;
3200 do {
3201 writel(t | GLOB_SFT_RST, reg);
3202 t = readl(reg);
3203 udelay(1);
3204 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3205
3206 if (!(GLOB_SFT_RST & t)) {
3207 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3208 rc = 1;
3209 goto done;
3210 }
3211
3212 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3213 i = 5;
3214 do {
3215 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3216 t = readl(reg);
3217 udelay(1);
3218 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3219
3220 if (GLOB_SFT_RST & t) {
3221 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3222 rc = 1;
3223 }
3224done:
3225 return rc;
3226}
3227
Jeff Garzik47c2b672005-11-12 21:13:17 -05003228static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003229 void __iomem *mmio)
3230{
3231 void __iomem *port_mmio;
3232 u32 tmp;
3233
Mark Lordcae5a292009-04-06 16:43:45 -04003234 tmp = readl(mmio + RESET_CFG);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003235 if ((tmp & (1 << 0)) == 0) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003236 hpriv->signal[idx].amps = 0x7 << 8;
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003237 hpriv->signal[idx].pre = 0x1 << 5;
3238 return;
3239 }
3240
3241 port_mmio = mv_port_base(mmio, idx);
3242 tmp = readl(port_mmio + PHY_MODE2);
3243
3244 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3245 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3246}
3247
Jeff Garzik47c2b672005-11-12 21:13:17 -05003248static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003249{
Mark Lordcae5a292009-04-06 16:43:45 -04003250 writel(0x00000060, mmio + GPIO_PORT_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003251}
3252
Jeff Garzikc9d39132005-11-13 17:47:51 -05003253static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003254 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003255{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003256 void __iomem *port_mmio = mv_port_base(mmio, port);
3257
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003258 u32 hp_flags = hpriv->hp_flags;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003259 int fix_phy_mode2 =
3260 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003261 int fix_phy_mode4 =
Jeff Garzik47c2b672005-11-12 21:13:17 -05003262 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Mark Lord8c30a8b2008-05-27 17:56:31 -04003263 u32 m2, m3;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003264
3265 if (fix_phy_mode2) {
3266 m2 = readl(port_mmio + PHY_MODE2);
3267 m2 &= ~(1 << 16);
3268 m2 |= (1 << 31);
3269 writel(m2, port_mmio + PHY_MODE2);
3270
3271 udelay(200);
3272
3273 m2 = readl(port_mmio + PHY_MODE2);
3274 m2 &= ~((1 << 16) | (1 << 31));
3275 writel(m2, port_mmio + PHY_MODE2);
3276
3277 udelay(200);
3278 }
3279
Mark Lord8c30a8b2008-05-27 17:56:31 -04003280 /*
3281 * Gen-II/IIe PHY_MODE3 errata RM#2:
3282 * Achieves better receiver noise performance than the h/w default:
3283 */
3284 m3 = readl(port_mmio + PHY_MODE3);
3285 m3 = (m3 & 0x1f) | (0x5555601 << 5);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003286
Mark Lord0388a8c2008-05-28 13:41:52 -04003287 /* Guideline 88F5182 (GL# SATA-S11) */
3288 if (IS_SOC(hpriv))
3289 m3 &= ~0x1c;
3290
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003291 if (fix_phy_mode4) {
Mark Lordba069e32008-05-31 16:46:34 -04003292 u32 m4 = readl(port_mmio + PHY_MODE4);
3293 /*
3294 * Enforce reserved-bit restrictions on GenIIe devices only.
3295 * For earlier chipsets, force only the internal config field
3296 * (workaround for errata FEr SATA#10 part 1).
3297 */
Mark Lord8c30a8b2008-05-27 17:56:31 -04003298 if (IS_GEN_IIE(hpriv))
Mark Lordba069e32008-05-31 16:46:34 -04003299 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3300 else
3301 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
Mark Lord8c30a8b2008-05-27 17:56:31 -04003302 writel(m4, port_mmio + PHY_MODE4);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003303 }
Mark Lordb406c7a2008-05-28 12:01:12 -04003304 /*
3305 * Workaround for 60x1-B2 errata SATA#13:
3306 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3307 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
Mark Lordba684602009-04-06 15:25:39 -04003308 * Or ensure we use writelfl() when writing PHY_MODE4.
Mark Lordb406c7a2008-05-28 12:01:12 -04003309 */
3310 writel(m3, port_mmio + PHY_MODE3);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003311
3312 /* Revert values of pre-emphasis and signal amps to the saved ones */
3313 m2 = readl(port_mmio + PHY_MODE2);
3314
3315 m2 &= ~MV_M2_PREAMP_MASK;
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003316 m2 |= hpriv->signal[port].amps;
3317 m2 |= hpriv->signal[port].pre;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003318 m2 &= ~(1 << 16);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003319
Jeff Garzike4e7b892006-01-31 12:18:41 -05003320 /* according to mvSata 3.6.1, some IIE values are fixed */
3321 if (IS_GEN_IIE(hpriv)) {
3322 m2 &= ~0xC30FF01F;
3323 m2 |= 0x0000900F;
3324 }
3325
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003326 writel(m2, port_mmio + PHY_MODE2);
3327}
3328
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003329/* TODO: use the generic LED interface to configure the SATA Presence */
3330/* & Acitivy LEDs on the board */
3331static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3332 void __iomem *mmio)
3333{
3334 return;
3335}
3336
3337static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3338 void __iomem *mmio)
3339{
3340 void __iomem *port_mmio;
3341 u32 tmp;
3342
3343 port_mmio = mv_port_base(mmio, idx);
3344 tmp = readl(port_mmio + PHY_MODE2);
3345
3346 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3347 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3348}
3349
3350#undef ZERO
3351#define ZERO(reg) writel(0, port_mmio + (reg))
3352static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3353 void __iomem *mmio, unsigned int port)
3354{
3355 void __iomem *port_mmio = mv_port_base(mmio, port);
3356
Mark Lorde12bef52008-03-31 19:33:56 -04003357 mv_reset_channel(hpriv, mmio, port);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003358
3359 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003360 writel(0x101f, port_mmio + EDMA_CFG);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003361 ZERO(0x004); /* timer */
3362 ZERO(0x008); /* irq err cause */
3363 ZERO(0x00c); /* irq err mask */
3364 ZERO(0x010); /* rq bah */
3365 ZERO(0x014); /* rq inp */
3366 ZERO(0x018); /* rq outp */
3367 ZERO(0x01c); /* respq bah */
3368 ZERO(0x024); /* respq outp */
3369 ZERO(0x020); /* respq inp */
3370 ZERO(0x02c); /* test control */
Mark Lordcae5a292009-04-06 16:43:45 -04003371 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003372}
3373
3374#undef ZERO
3375
3376#define ZERO(reg) writel(0, hc_mmio + (reg))
3377static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3378 void __iomem *mmio)
3379{
3380 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3381
3382 ZERO(0x00c);
3383 ZERO(0x010);
3384 ZERO(0x014);
3385
3386}
3387
3388#undef ZERO
3389
3390static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3391 void __iomem *mmio, unsigned int n_hc)
3392{
3393 unsigned int port;
3394
3395 for (port = 0; port < hpriv->n_ports; port++)
3396 mv_soc_reset_hc_port(hpriv, mmio, port);
3397
3398 mv_soc_reset_one_hc(hpriv, mmio);
3399
3400 return 0;
3401}
3402
3403static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3404 void __iomem *mmio)
3405{
3406 return;
3407}
3408
3409static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3410{
3411 return;
3412}
3413
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003414static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3415 void __iomem *mmio, unsigned int port)
3416{
3417 void __iomem *port_mmio = mv_port_base(mmio, port);
3418 u32 reg;
3419
3420 reg = readl(port_mmio + PHY_MODE3);
3421 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3422 reg |= (0x1 << 27);
3423 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3424 reg |= (0x1 << 29);
3425 writel(reg, port_mmio + PHY_MODE3);
3426
3427 reg = readl(port_mmio + PHY_MODE4);
3428 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3429 reg |= (0x1 << 16);
3430 writel(reg, port_mmio + PHY_MODE4);
3431
3432 reg = readl(port_mmio + PHY_MODE9_GEN2);
3433 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3434 reg |= 0x8;
3435 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3436 writel(reg, port_mmio + PHY_MODE9_GEN2);
3437
3438 reg = readl(port_mmio + PHY_MODE9_GEN1);
3439 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3440 reg |= 0x8;
3441 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3442 writel(reg, port_mmio + PHY_MODE9_GEN1);
3443}
3444
3445/**
3446 * soc_is_65 - check if the soc is 65 nano device
3447 *
3448 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3449 * register, this register should contain non-zero value and it exists only
3450 * in the 65 nano devices, when reading it from older devices we get 0.
3451 */
3452static bool soc_is_65n(struct mv_host_priv *hpriv)
3453{
3454 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3455
3456 if (readl(port0_mmio + PHYCFG_OFS))
3457 return true;
3458 return false;
3459}
3460
Mark Lord8e7decd2008-05-02 02:07:51 -04003461static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
Mark Lordb67a1062008-03-31 19:35:13 -04003462{
Mark Lordcae5a292009-04-06 16:43:45 -04003463 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003464
Mark Lord8e7decd2008-05-02 02:07:51 -04003465 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
Mark Lordb67a1062008-03-31 19:35:13 -04003466 if (want_gen2i)
Mark Lord8e7decd2008-05-02 02:07:51 -04003467 ifcfg |= (1 << 7); /* enable gen2i speed */
Mark Lordcae5a292009-04-06 16:43:45 -04003468 writelfl(ifcfg, port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003469}
3470
Mark Lorde12bef52008-03-31 19:33:56 -04003471static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -05003472 unsigned int port_no)
Brett Russ20f733e2005-09-01 18:26:17 -04003473{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003474 void __iomem *port_mmio = mv_port_base(mmio, port_no);
Brett Russ20f733e2005-09-01 18:26:17 -04003475
Mark Lord8e7decd2008-05-02 02:07:51 -04003476 /*
3477 * The datasheet warns against setting EDMA_RESET when EDMA is active
3478 * (but doesn't say what the problem might be). So we first try
3479 * to disable the EDMA engine before doing the EDMA_RESET operation.
3480 */
Mark Lord0d8be5c2008-04-16 14:56:12 -04003481 mv_stop_edma_engine(port_mmio);
Mark Lordcae5a292009-04-06 16:43:45 -04003482 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003483
Mark Lordb67a1062008-03-31 19:35:13 -04003484 if (!IS_GEN_I(hpriv)) {
Mark Lord8e7decd2008-05-02 02:07:51 -04003485 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3486 mv_setup_ifcfg(port_mmio, 1);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003487 }
Mark Lordb67a1062008-03-31 19:35:13 -04003488 /*
Mark Lord8e7decd2008-05-02 02:07:51 -04003489 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
Mark Lordb67a1062008-03-31 19:35:13 -04003490 * link, and physical layers. It resets all SATA interface registers
Mark Lordcae5a292009-04-06 16:43:45 -04003491 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
Brett Russ20f733e2005-09-01 18:26:17 -04003492 */
Mark Lordcae5a292009-04-06 16:43:45 -04003493 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Mark Lordb67a1062008-03-31 19:35:13 -04003494 udelay(25); /* allow reset propagation */
Mark Lordcae5a292009-04-06 16:43:45 -04003495 writelfl(0, port_mmio + EDMA_CMD);
Brett Russ20f733e2005-09-01 18:26:17 -04003496
Jeff Garzikc9d39132005-11-13 17:47:51 -05003497 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3498
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003499 if (IS_GEN_I(hpriv))
Jeff Garzikc9d39132005-11-13 17:47:51 -05003500 mdelay(1);
3501}
3502
Mark Lorde49856d2008-04-16 14:59:07 -04003503static void mv_pmp_select(struct ata_port *ap, int pmp)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003504{
Mark Lorde49856d2008-04-16 14:59:07 -04003505 if (sata_pmp_supported(ap)) {
3506 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04003507 u32 reg = readl(port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003508 int old = reg & 0xf;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003509
Mark Lorde49856d2008-04-16 14:59:07 -04003510 if (old != pmp) {
3511 reg = (reg & ~0xf) | pmp;
Mark Lordcae5a292009-04-06 16:43:45 -04003512 writelfl(reg, port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003513 }
Tejun Heoda3dbb12007-07-16 14:29:40 +09003514 }
Brett Russ20f733e2005-09-01 18:26:17 -04003515}
3516
Mark Lorde49856d2008-04-16 14:59:07 -04003517static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3518 unsigned long deadline)
Jeff Garzik22374672005-11-17 10:59:48 -05003519{
Mark Lorde49856d2008-04-16 14:59:07 -04003520 mv_pmp_select(link->ap, sata_srst_pmp(link));
3521 return sata_std_hardreset(link, class, deadline);
3522}
Jeff Garzik0ea9e172007-07-13 17:06:45 -04003523
Mark Lorde49856d2008-04-16 14:59:07 -04003524static int mv_softreset(struct ata_link *link, unsigned int *class,
3525 unsigned long deadline)
3526{
3527 mv_pmp_select(link->ap, sata_srst_pmp(link));
3528 return ata_sff_softreset(link, class, deadline);
Jeff Garzik22374672005-11-17 10:59:48 -05003529}
3530
Tejun Heocc0680a2007-08-06 18:36:23 +09003531static int mv_hardreset(struct ata_link *link, unsigned int *class,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003532 unsigned long deadline)
3533{
Tejun Heocc0680a2007-08-06 18:36:23 +09003534 struct ata_port *ap = link->ap;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003535 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordb5624682008-03-31 19:34:40 -04003536 struct mv_port_priv *pp = ap->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003537 void __iomem *mmio = hpriv->base;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003538 int rc, attempts = 0, extra = 0;
3539 u32 sstatus;
3540 bool online;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003541
Mark Lorde12bef52008-03-31 19:33:56 -04003542 mv_reset_channel(hpriv, mmio, ap->port_no);
Mark Lordb5624682008-03-31 19:34:40 -04003543 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lordd16ab3f2009-02-25 15:17:43 -05003544 pp->pp_flags &=
3545 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003546
Mark Lord0d8be5c2008-04-16 14:56:12 -04003547 /* Workaround for errata FEr SATA#10 (part 2) */
3548 do {
Mark Lord17c5aab2008-04-16 14:56:51 -04003549 const unsigned long *timing =
3550 sata_ehc_deb_timing(&link->eh_context);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003551
Mark Lord17c5aab2008-04-16 14:56:51 -04003552 rc = sata_link_hardreset(link, timing, deadline + extra,
3553 &online, NULL);
Mark Lord9dcffd92008-05-14 09:18:12 -04003554 rc = online ? -EAGAIN : rc;
Mark Lord17c5aab2008-04-16 14:56:51 -04003555 if (rc)
Mark Lord0d8be5c2008-04-16 14:56:12 -04003556 return rc;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003557 sata_scr_read(link, SCR_STATUS, &sstatus);
3558 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3559 /* Force 1.5gb/s link speed and try again */
Mark Lord8e7decd2008-05-02 02:07:51 -04003560 mv_setup_ifcfg(mv_ap_base(ap), 0);
Mark Lord0d8be5c2008-04-16 14:56:12 -04003561 if (time_after(jiffies + HZ, deadline))
3562 extra = HZ; /* only extend it once, max */
3563 }
3564 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
Mark Lord08da1752009-02-25 15:13:03 -05003565 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05003566 mv_edma_cfg(ap, 0, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003567
Mark Lord17c5aab2008-04-16 14:56:51 -04003568 return rc;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003569}
3570
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003571static void mv_eh_freeze(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04003572{
Mark Lord1cfd19a2008-04-19 15:05:50 -04003573 mv_stop_edma(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003574 mv_enable_port_irqs(ap, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003575}
3576
3577static void mv_eh_thaw(struct ata_port *ap)
3578{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003579 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordc4de5732008-05-17 13:35:21 -04003580 unsigned int port = ap->port_no;
3581 unsigned int hardport = mv_hardport_from_port(port);
Mark Lord1cfd19a2008-04-19 15:05:50 -04003582 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003583 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003584 u32 hc_irq_cause;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003585
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003586 /* clear EDMA errors on this port */
Mark Lordcae5a292009-04-06 16:43:45 -04003587 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003588
3589 /* clear pending irq events */
Mark Lordcae6edc2009-01-19 18:05:42 -05003590 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04003591 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003592
Mark Lord88e675e2008-05-17 13:36:30 -04003593 mv_enable_port_irqs(ap, ERR_IRQ);
Brett Russ31961942005-09-30 01:36:00 -04003594}
3595
Brett Russ05b308e2005-10-05 17:08:53 -04003596/**
3597 * mv_port_init - Perform some early initialization on a single port.
3598 * @port: libata data structure storing shadow register addresses
3599 * @port_mmio: base address of the port
3600 *
3601 * Initialize shadow register mmio addresses, clear outstanding
3602 * interrupts on the port, and unmask interrupts for the future
3603 * start of the port.
3604 *
3605 * LOCKING:
3606 * Inherited from caller.
3607 */
Brett Russ31961942005-09-30 01:36:00 -04003608static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3609{
Mark Lordcae5a292009-04-06 16:43:45 -04003610 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
Brett Russ31961942005-09-30 01:36:00 -04003611
Jeff Garzik8b260242005-11-12 12:32:50 -05003612 /* PIO related setup
Brett Russ31961942005-09-30 01:36:00 -04003613 */
3614 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
Jeff Garzik8b260242005-11-12 12:32:50 -05003615 port->error_addr =
Brett Russ31961942005-09-30 01:36:00 -04003616 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3617 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3618 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3619 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3620 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3621 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
Jeff Garzik8b260242005-11-12 12:32:50 -05003622 port->status_addr =
Brett Russ31961942005-09-30 01:36:00 -04003623 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3624 /* special case: control/altstatus doesn't have ATA_REG_ address */
Mark Lordcae5a292009-04-06 16:43:45 -04003625 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
Brett Russ31961942005-09-30 01:36:00 -04003626
3627 /* unused: */
Randy Dunlap8d9db2d2007-02-16 01:40:06 -08003628 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
Brett Russ20f733e2005-09-01 18:26:17 -04003629
Brett Russ31961942005-09-30 01:36:00 -04003630 /* Clear any currently outstanding port interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003631 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3632 writelfl(readl(serr), serr);
3633 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Brett Russ31961942005-09-30 01:36:00 -04003634
Mark Lord646a4da2008-01-26 18:30:37 -05003635 /* unmask all non-transient EDMA error interrupts */
Mark Lordcae5a292009-04-06 16:43:45 -04003636 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
Brett Russ20f733e2005-09-01 18:26:17 -04003637
Jeff Garzik8b260242005-11-12 12:32:50 -05003638 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
Mark Lordcae5a292009-04-06 16:43:45 -04003639 readl(port_mmio + EDMA_CFG),
3640 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3641 readl(port_mmio + EDMA_ERR_IRQ_MASK));
Brett Russ20f733e2005-09-01 18:26:17 -04003642}
3643
Mark Lord616d4a92008-05-02 02:08:32 -04003644static unsigned int mv_in_pcix_mode(struct ata_host *host)
3645{
3646 struct mv_host_priv *hpriv = host->private_data;
3647 void __iomem *mmio = hpriv->base;
3648 u32 reg;
3649
Mark Lord1f398472008-05-27 17:54:48 -04003650 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
Mark Lord616d4a92008-05-02 02:08:32 -04003651 return 0; /* not PCI-X capable */
Mark Lordcae5a292009-04-06 16:43:45 -04003652 reg = readl(mmio + MV_PCI_MODE);
Mark Lord616d4a92008-05-02 02:08:32 -04003653 if ((reg & MV_PCI_MODE_MASK) == 0)
3654 return 0; /* conventional PCI mode */
3655 return 1; /* chip is in PCI-X mode */
3656}
3657
3658static int mv_pci_cut_through_okay(struct ata_host *host)
3659{
3660 struct mv_host_priv *hpriv = host->private_data;
3661 void __iomem *mmio = hpriv->base;
3662 u32 reg;
3663
3664 if (!mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003665 reg = readl(mmio + MV_PCI_COMMAND);
3666 if (reg & MV_PCI_COMMAND_MRDTRIG)
Mark Lord616d4a92008-05-02 02:08:32 -04003667 return 0; /* not okay */
3668 }
3669 return 1; /* okay */
3670}
3671
Mark Lord65ad7fef2009-04-06 15:24:14 -04003672static void mv_60x1b2_errata_pci7(struct ata_host *host)
3673{
3674 struct mv_host_priv *hpriv = host->private_data;
3675 void __iomem *mmio = hpriv->base;
3676
3677 /* workaround for 60x1-B2 errata PCI#7 */
3678 if (mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003679 u32 reg = readl(mmio + MV_PCI_COMMAND);
3680 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
Mark Lord65ad7fef2009-04-06 15:24:14 -04003681 }
3682}
3683
Tejun Heo4447d352007-04-17 23:44:08 +09003684static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003685{
Tejun Heo4447d352007-04-17 23:44:08 +09003686 struct pci_dev *pdev = to_pci_dev(host->dev);
3687 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003688 u32 hp_flags = hpriv->hp_flags;
3689
Jeff Garzik5796d1c2007-10-26 00:03:37 -04003690 switch (board_idx) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003691 case chip_5080:
3692 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003693 hp_flags |= MV_HP_GEN_I;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003694
Auke Kok44c10132007-06-08 15:46:36 -07003695 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003696 case 0x1:
3697 hp_flags |= MV_HP_ERRATA_50XXB0;
3698 break;
3699 case 0x3:
3700 hp_flags |= MV_HP_ERRATA_50XXB2;
3701 break;
3702 default:
3703 dev_printk(KERN_WARNING, &pdev->dev,
3704 "Applying 50XXB2 workarounds to unknown rev\n");
3705 hp_flags |= MV_HP_ERRATA_50XXB2;
3706 break;
3707 }
3708 break;
3709
3710 case chip_504x:
3711 case chip_508x:
3712 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003713 hp_flags |= MV_HP_GEN_I;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003714
Auke Kok44c10132007-06-08 15:46:36 -07003715 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003716 case 0x0:
3717 hp_flags |= MV_HP_ERRATA_50XXB0;
3718 break;
3719 case 0x3:
3720 hp_flags |= MV_HP_ERRATA_50XXB2;
3721 break;
3722 default:
3723 dev_printk(KERN_WARNING, &pdev->dev,
3724 "Applying B2 workarounds to unknown rev\n");
3725 hp_flags |= MV_HP_ERRATA_50XXB2;
3726 break;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003727 }
3728 break;
3729
3730 case chip_604x:
3731 case chip_608x:
Jeff Garzik47c2b672005-11-12 21:13:17 -05003732 hpriv->ops = &mv6xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003733 hp_flags |= MV_HP_GEN_II;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003734
Auke Kok44c10132007-06-08 15:46:36 -07003735 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003736 case 0x7:
Mark Lord65ad7fef2009-04-06 15:24:14 -04003737 mv_60x1b2_errata_pci7(host);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003738 hp_flags |= MV_HP_ERRATA_60X1B2;
3739 break;
3740 case 0x9:
3741 hp_flags |= MV_HP_ERRATA_60X1C0;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003742 break;
3743 default:
3744 dev_printk(KERN_WARNING, &pdev->dev,
Jeff Garzik47c2b672005-11-12 21:13:17 -05003745 "Applying B2 workarounds to unknown rev\n");
3746 hp_flags |= MV_HP_ERRATA_60X1B2;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003747 break;
3748 }
3749 break;
3750
Jeff Garzike4e7b892006-01-31 12:18:41 -05003751 case chip_7042:
Mark Lord616d4a92008-05-02 02:08:32 -04003752 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
Mark Lord306b30f2007-12-04 14:07:52 -05003753 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3754 (pdev->device == 0x2300 || pdev->device == 0x2310))
3755 {
Mark Lord4e520032007-12-11 12:58:05 -05003756 /*
3757 * Highpoint RocketRAID PCIe 23xx series cards:
3758 *
3759 * Unconfigured drives are treated as "Legacy"
3760 * by the BIOS, and it overwrites sector 8 with
3761 * a "Lgcy" metadata block prior to Linux boot.
3762 *
3763 * Configured drives (RAID or JBOD) leave sector 8
3764 * alone, but instead overwrite a high numbered
3765 * sector for the RAID metadata. This sector can
3766 * be determined exactly, by truncating the physical
3767 * drive capacity to a nice even GB value.
3768 *
3769 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3770 *
3771 * Warn the user, lest they think we're just buggy.
3772 */
3773 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3774 " BIOS CORRUPTS DATA on all attached drives,"
3775 " regardless of if/how they are configured."
3776 " BEWARE!\n");
3777 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3778 " use sectors 8-9 on \"Legacy\" drives,"
3779 " and avoid the final two gigabytes on"
3780 " all RocketRAID BIOS initialized drives.\n");
Mark Lord306b30f2007-12-04 14:07:52 -05003781 }
Mark Lord8e7decd2008-05-02 02:07:51 -04003782 /* drop through */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003783 case chip_6042:
3784 hpriv->ops = &mv6xxx_ops;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003785 hp_flags |= MV_HP_GEN_IIE;
Mark Lord616d4a92008-05-02 02:08:32 -04003786 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3787 hp_flags |= MV_HP_CUT_THROUGH;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003788
Auke Kok44c10132007-06-08 15:46:36 -07003789 switch (pdev->revision) {
Mark Lord5cf73bf2008-05-27 17:58:56 -04003790 case 0x2: /* Rev.B0: the first/only public release */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003791 hp_flags |= MV_HP_ERRATA_60X1C0;
3792 break;
3793 default:
3794 dev_printk(KERN_WARNING, &pdev->dev,
3795 "Applying 60X1C0 workarounds to unknown rev\n");
3796 hp_flags |= MV_HP_ERRATA_60X1C0;
3797 break;
3798 }
3799 break;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003800 case chip_soc:
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003801 if (soc_is_65n(hpriv))
3802 hpriv->ops = &mv_soc_65n_ops;
3803 else
3804 hpriv->ops = &mv_soc_ops;
Saeed Bisharaeb3a55a2008-08-04 00:52:55 -11003805 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3806 MV_HP_ERRATA_60X1C0;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003807 break;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003808
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003809 default:
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003810 dev_printk(KERN_ERR, host->dev,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04003811 "BUG: invalid board index %u\n", board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003812 return 1;
3813 }
3814
3815 hpriv->hp_flags = hp_flags;
Mark Lord02a121d2007-12-01 13:07:22 -05003816 if (hp_flags & MV_HP_PCIE) {
Mark Lordcae5a292009-04-06 16:43:45 -04003817 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3818 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003819 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3820 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003821 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3822 hpriv->irq_mask_offset = PCI_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003823 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3824 }
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003825
3826 return 0;
3827}
3828
Brett Russ05b308e2005-10-05 17:08:53 -04003829/**
Jeff Garzik47c2b672005-11-12 21:13:17 -05003830 * mv_init_host - Perform some early initialization of the host.
Tejun Heo4447d352007-04-17 23:44:08 +09003831 * @host: ATA host to initialize
3832 * @board_idx: controller index
Brett Russ05b308e2005-10-05 17:08:53 -04003833 *
3834 * If possible, do an early global reset of the host. Then do
3835 * our port init and clear/unmask all/relevant host interrupts.
3836 *
3837 * LOCKING:
3838 * Inherited from caller.
3839 */
Tejun Heo4447d352007-04-17 23:44:08 +09003840static int mv_init_host(struct ata_host *host, unsigned int board_idx)
Brett Russ20f733e2005-09-01 18:26:17 -04003841{
3842 int rc = 0, n_hc, port, hc;
Tejun Heo4447d352007-04-17 23:44:08 +09003843 struct mv_host_priv *hpriv = host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003844 void __iomem *mmio = hpriv->base;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003845
Tejun Heo4447d352007-04-17 23:44:08 +09003846 rc = mv_chip_id(host, board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003847 if (rc)
Mark Lord352fab72008-04-19 14:43:42 -04003848 goto done;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003849
Mark Lord1f398472008-05-27 17:54:48 -04003850 if (IS_SOC(hpriv)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003851 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3852 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
Mark Lord1f398472008-05-27 17:54:48 -04003853 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003854 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3855 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003856 }
Mark Lord352fab72008-04-19 14:43:42 -04003857
Thomas Reitmayr5d0fb2e2009-01-24 20:24:58 +01003858 /* initialize shadow irq mask with register's value */
3859 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3860
Mark Lord352fab72008-04-19 14:43:42 -04003861 /* global interrupt mask: 0 == mask everything */
Mark Lordc4de5732008-05-17 13:35:21 -04003862 mv_set_main_irq_mask(host, ~0, 0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003863
Tejun Heo4447d352007-04-17 23:44:08 +09003864 n_hc = mv_get_hc_count(host->ports[0]->flags);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003865
Tejun Heo4447d352007-04-17 23:44:08 +09003866 for (port = 0; port < host->n_ports; port++)
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003867 if (hpriv->ops->read_preamp)
3868 hpriv->ops->read_preamp(hpriv, port, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003869
Jeff Garzikc9d39132005-11-13 17:47:51 -05003870 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003871 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04003872 goto done;
Brett Russ20f733e2005-09-01 18:26:17 -04003873
Jeff Garzik522479f2005-11-12 22:14:02 -05003874 hpriv->ops->reset_flash(hpriv, mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003875 hpriv->ops->reset_bus(host, mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003876 hpriv->ops->enable_leds(hpriv, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003877
Tejun Heo4447d352007-04-17 23:44:08 +09003878 for (port = 0; port < host->n_ports; port++) {
Tejun Heocbcdd872007-08-18 13:14:55 +09003879 struct ata_port *ap = host->ports[port];
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003880 void __iomem *port_mmio = mv_port_base(mmio, port);
Tejun Heocbcdd872007-08-18 13:14:55 +09003881
3882 mv_port_init(&ap->ioaddr, port_mmio);
3883
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003884#ifdef CONFIG_PCI
Mark Lord1f398472008-05-27 17:54:48 -04003885 if (!IS_SOC(hpriv)) {
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003886 unsigned int offset = port_mmio - mmio;
3887 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3888 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3889 }
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003890#endif
Brett Russ20f733e2005-09-01 18:26:17 -04003891 }
3892
3893 for (hc = 0; hc < n_hc; hc++) {
Brett Russ31961942005-09-30 01:36:00 -04003894 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3895
3896 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3897 "(before clear)=0x%08x\n", hc,
Mark Lordcae5a292009-04-06 16:43:45 -04003898 readl(hc_mmio + HC_CFG),
3899 readl(hc_mmio + HC_IRQ_CAUSE));
Brett Russ31961942005-09-30 01:36:00 -04003900
3901 /* Clear any currently outstanding hc interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003902 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
Brett Russ20f733e2005-09-01 18:26:17 -04003903 }
3904
Mark Lord44c65d12009-04-06 12:29:49 -04003905 if (!IS_SOC(hpriv)) {
3906 /* Clear any currently outstanding host interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003907 writelfl(0, mmio + hpriv->irq_cause_offset);
Brett Russ31961942005-09-30 01:36:00 -04003908
Mark Lord44c65d12009-04-06 12:29:49 -04003909 /* and unmask interrupt generation for host regs */
Mark Lordcae5a292009-04-06 16:43:45 -04003910 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
Mark Lord44c65d12009-04-06 12:29:49 -04003911 }
Jeff Garzikfb621e22007-02-25 04:19:45 -05003912
Mark Lord6be96ac2009-02-19 10:38:04 -05003913 /*
3914 * enable only global host interrupts for now.
3915 * The per-port interrupts get done later as ports are set up.
3916 */
3917 mv_set_main_irq_mask(host, 0, PCI_ERR);
Mark Lord2b748a02009-03-10 22:01:17 -04003918 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3919 irq_coalescing_usecs);
Brett Russ31961942005-09-30 01:36:00 -04003920done:
Brett Russ20f733e2005-09-01 18:26:17 -04003921 return rc;
3922}
3923
Byron Bradleyfbf14e22008-02-10 21:17:30 +00003924static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3925{
3926 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3927 MV_CRQB_Q_SZ, 0);
3928 if (!hpriv->crqb_pool)
3929 return -ENOMEM;
3930
3931 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3932 MV_CRPB_Q_SZ, 0);
3933 if (!hpriv->crpb_pool)
3934 return -ENOMEM;
3935
3936 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3937 MV_SG_TBL_SZ, 0);
3938 if (!hpriv->sg_tbl_pool)
3939 return -ENOMEM;
3940
3941 return 0;
3942}
3943
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003944static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3945 struct mbus_dram_target_info *dram)
3946{
3947 int i;
3948
3949 for (i = 0; i < 4; i++) {
3950 writel(0, hpriv->base + WINDOW_CTRL(i));
3951 writel(0, hpriv->base + WINDOW_BASE(i));
3952 }
3953
3954 for (i = 0; i < dram->num_cs; i++) {
3955 struct mbus_dram_window *cs = dram->cs + i;
3956
3957 writel(((cs->size - 1) & 0xffff0000) |
3958 (cs->mbus_attr << 8) |
3959 (dram->mbus_dram_target_id << 4) | 1,
3960 hpriv->base + WINDOW_CTRL(i));
3961 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3962 }
3963}
3964
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003965/**
3966 * mv_platform_probe - handle a positive probe of an soc Marvell
3967 * host
3968 * @pdev: platform device found
3969 *
3970 * LOCKING:
3971 * Inherited from caller.
3972 */
3973static int mv_platform_probe(struct platform_device *pdev)
3974{
3975 static int printed_version;
3976 const struct mv_sata_platform_data *mv_platform_data;
3977 const struct ata_port_info *ppi[] =
3978 { &mv_port_info[chip_soc], NULL };
3979 struct ata_host *host;
3980 struct mv_host_priv *hpriv;
3981 struct resource *res;
3982 int n_ports, rc;
3983
3984 if (!printed_version++)
3985 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3986
3987 /*
3988 * Simple resource validation ..
3989 */
3990 if (unlikely(pdev->num_resources != 2)) {
3991 dev_err(&pdev->dev, "invalid number of resources\n");
3992 return -EINVAL;
3993 }
3994
3995 /*
3996 * Get the register base first
3997 */
3998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3999 if (res == NULL)
4000 return -EINVAL;
4001
4002 /* allocate host */
4003 mv_platform_data = pdev->dev.platform_data;
4004 n_ports = mv_platform_data->n_ports;
4005
4006 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4007 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4008
4009 if (!host || !hpriv)
4010 return -ENOMEM;
4011 host->private_data = hpriv;
4012 hpriv->n_ports = n_ports;
4013
4014 host->iomap = NULL;
Saeed Bisharaf1cb0ea2008-02-18 07:42:28 -11004015 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4016 res->end - res->start + 1);
Mark Lordcae5a292009-04-06 16:43:45 -04004017 hpriv->base -= SATAHC0_REG_BASE;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004018
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004019 /*
4020 * (Re-)program MBUS remapping windows if we are asked to.
4021 */
4022 if (mv_platform_data->dram != NULL)
4023 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4024
Byron Bradleyfbf14e22008-02-10 21:17:30 +00004025 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4026 if (rc)
4027 return rc;
4028
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004029 /* initialize adapter */
4030 rc = mv_init_host(host, chip_soc);
4031 if (rc)
4032 return rc;
4033
4034 dev_printk(KERN_INFO, &pdev->dev,
4035 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4036 host->n_ports);
4037
4038 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4039 IRQF_SHARED, &mv6_sht);
4040}
4041
4042/*
4043 *
4044 * mv_platform_remove - unplug a platform interface
4045 * @pdev: platform device
4046 *
4047 * A platform bus SATA device has been unplugged. Perform the needed
4048 * cleanup. Also called on module unload for any active devices.
4049 */
4050static int __devexit mv_platform_remove(struct platform_device *pdev)
4051{
4052 struct device *dev = &pdev->dev;
4053 struct ata_host *host = dev_get_drvdata(dev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004054
4055 ata_host_detach(host);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004056 return 0;
4057}
4058
4059static struct platform_driver mv_platform_driver = {
4060 .probe = mv_platform_probe,
4061 .remove = __devexit_p(mv_platform_remove),
4062 .driver = {
4063 .name = DRV_NAME,
4064 .owner = THIS_MODULE,
4065 },
4066};
4067
4068
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004069#ifdef CONFIG_PCI
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004070static int mv_pci_init_one(struct pci_dev *pdev,
4071 const struct pci_device_id *ent);
4072
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004073
4074static struct pci_driver mv_pci_driver = {
4075 .name = DRV_NAME,
4076 .id_table = mv_pci_tbl,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004077 .probe = mv_pci_init_one,
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004078 .remove = ata_pci_remove_one,
4079};
4080
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004081/* move to PCI layer or libata core? */
4082static int pci_go_64(struct pci_dev *pdev)
4083{
4084 int rc;
4085
Yang Hongyang6a355282009-04-06 19:01:13 -07004086 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4087 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004088 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07004089 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004090 if (rc) {
4091 dev_printk(KERN_ERR, &pdev->dev,
4092 "64-bit DMA enable failed\n");
4093 return rc;
4094 }
4095 }
4096 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07004097 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004098 if (rc) {
4099 dev_printk(KERN_ERR, &pdev->dev,
4100 "32-bit DMA enable failed\n");
4101 return rc;
4102 }
Yang Hongyang284901a2009-04-06 19:01:15 -07004103 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004104 if (rc) {
4105 dev_printk(KERN_ERR, &pdev->dev,
4106 "32-bit consistent DMA enable failed\n");
4107 return rc;
4108 }
4109 }
4110
4111 return rc;
4112}
4113
Brett Russ05b308e2005-10-05 17:08:53 -04004114/**
4115 * mv_print_info - Dump key info to kernel log for perusal.
Tejun Heo4447d352007-04-17 23:44:08 +09004116 * @host: ATA host to print info about
Brett Russ05b308e2005-10-05 17:08:53 -04004117 *
4118 * FIXME: complete this.
4119 *
4120 * LOCKING:
4121 * Inherited from caller.
4122 */
Tejun Heo4447d352007-04-17 23:44:08 +09004123static void mv_print_info(struct ata_host *host)
Brett Russ31961942005-09-30 01:36:00 -04004124{
Tejun Heo4447d352007-04-17 23:44:08 +09004125 struct pci_dev *pdev = to_pci_dev(host->dev);
4126 struct mv_host_priv *hpriv = host->private_data;
Auke Kok44c10132007-06-08 15:46:36 -07004127 u8 scc;
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004128 const char *scc_s, *gen;
Brett Russ31961942005-09-30 01:36:00 -04004129
4130 /* Use this to determine the HW stepping of the chip so we know
4131 * what errata to workaround
4132 */
Brett Russ31961942005-09-30 01:36:00 -04004133 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4134 if (scc == 0)
4135 scc_s = "SCSI";
4136 else if (scc == 0x01)
4137 scc_s = "RAID";
4138 else
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004139 scc_s = "?";
4140
4141 if (IS_GEN_I(hpriv))
4142 gen = "I";
4143 else if (IS_GEN_II(hpriv))
4144 gen = "II";
4145 else if (IS_GEN_IIE(hpriv))
4146 gen = "IIE";
4147 else
4148 gen = "?";
Brett Russ31961942005-09-30 01:36:00 -04004149
Jeff Garzika9524a72005-10-30 14:39:11 -05004150 dev_printk(KERN_INFO, &pdev->dev,
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004151 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4152 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
Brett Russ31961942005-09-30 01:36:00 -04004153 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4154}
4155
Brett Russ05b308e2005-10-05 17:08:53 -04004156/**
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004157 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
Brett Russ05b308e2005-10-05 17:08:53 -04004158 * @pdev: PCI device found
4159 * @ent: PCI device ID entry for the matched host
4160 *
4161 * LOCKING:
4162 * Inherited from caller.
4163 */
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004164static int mv_pci_init_one(struct pci_dev *pdev,
4165 const struct pci_device_id *ent)
Brett Russ20f733e2005-09-01 18:26:17 -04004166{
Jeff Garzik2dcb4072007-10-19 06:42:56 -04004167 static int printed_version;
Brett Russ20f733e2005-09-01 18:26:17 -04004168 unsigned int board_idx = (unsigned int)ent->driver_data;
Tejun Heo4447d352007-04-17 23:44:08 +09004169 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4170 struct ata_host *host;
4171 struct mv_host_priv *hpriv;
4172 int n_ports, rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004173
Jeff Garzika9524a72005-10-30 14:39:11 -05004174 if (!printed_version++)
4175 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
Brett Russ20f733e2005-09-01 18:26:17 -04004176
Tejun Heo4447d352007-04-17 23:44:08 +09004177 /* allocate host */
4178 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4179
4180 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4181 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4182 if (!host || !hpriv)
4183 return -ENOMEM;
4184 host->private_data = hpriv;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004185 hpriv->n_ports = n_ports;
Tejun Heo4447d352007-04-17 23:44:08 +09004186
4187 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09004188 rc = pcim_enable_device(pdev);
4189 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04004190 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004191
Tejun Heo0d5ff562007-02-01 15:06:36 +09004192 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4193 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004194 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09004195 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004196 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09004197 host->iomap = pcim_iomap_table(pdev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004198 hpriv->base = host->iomap[MV_PRIMARY_BAR];
Brett Russ20f733e2005-09-01 18:26:17 -04004199
Jeff Garzikd88184f2007-02-26 01:26:06 -05004200 rc = pci_go_64(pdev);
4201 if (rc)
4202 return rc;
4203
Mark Lordda2fa9b2008-01-26 18:32:45 -05004204 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4205 if (rc)
4206 return rc;
4207
Brett Russ20f733e2005-09-01 18:26:17 -04004208 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09004209 rc = mv_init_host(host, board_idx);
Tejun Heo24dc5f32007-01-20 16:00:28 +09004210 if (rc)
4211 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004212
Mark Lord6d3c30e2009-01-21 10:31:29 -05004213 /* Enable message-switched interrupts, if requested */
4214 if (msi && pci_enable_msi(pdev) == 0)
4215 hpriv->hp_flags |= MV_HP_FLAG_MSI;
Brett Russ20f733e2005-09-01 18:26:17 -04004216
Brett Russ31961942005-09-30 01:36:00 -04004217 mv_dump_pci_cfg(pdev, 0x68);
Tejun Heo4447d352007-04-17 23:44:08 +09004218 mv_print_info(host);
Brett Russ20f733e2005-09-01 18:26:17 -04004219
Tejun Heo4447d352007-04-17 23:44:08 +09004220 pci_set_master(pdev);
Jeff Garzikea8b4db2007-07-17 02:21:50 -04004221 pci_try_set_mwi(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09004222 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
Jeff Garzikc5d3e452007-07-11 18:30:50 -04004223 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
Brett Russ20f733e2005-09-01 18:26:17 -04004224}
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004225#endif
Brett Russ20f733e2005-09-01 18:26:17 -04004226
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004227static int mv_platform_probe(struct platform_device *pdev);
4228static int __devexit mv_platform_remove(struct platform_device *pdev);
4229
Brett Russ20f733e2005-09-01 18:26:17 -04004230static int __init mv_init(void)
4231{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004232 int rc = -ENODEV;
4233#ifdef CONFIG_PCI
4234 rc = pci_register_driver(&mv_pci_driver);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004235 if (rc < 0)
4236 return rc;
4237#endif
4238 rc = platform_driver_register(&mv_platform_driver);
4239
4240#ifdef CONFIG_PCI
4241 if (rc < 0)
4242 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004243#endif
4244 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004245}
4246
4247static void __exit mv_exit(void)
4248{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004249#ifdef CONFIG_PCI
Brett Russ20f733e2005-09-01 18:26:17 -04004250 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004251#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004252 platform_driver_unregister(&mv_platform_driver);
Brett Russ20f733e2005-09-01 18:26:17 -04004253}
4254
4255MODULE_AUTHOR("Brett Russ");
4256MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4257MODULE_LICENSE("GPL");
4258MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4259MODULE_VERSION(DRV_VERSION);
Mark Lord17c5aab2008-04-16 14:56:51 -04004260MODULE_ALIAS("platform:" DRV_NAME);
Brett Russ20f733e2005-09-01 18:26:17 -04004261
Brett Russ20f733e2005-09-01 18:26:17 -04004262module_init(mv_init);
4263module_exit(mv_exit);