Blame - drivers/gpu/drm/radeon/cikd.h - kernel/msm-4.9

2013-04-09 12:41:24 -0400

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Alex Deucher

*/

#ifndef CIK_H

#define CIK_H

#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001

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#define CIK_RB_BITMAP_WIDTH_PER_SH 2

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/* DIDT IND registers */

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#define DIDT_SQ_CTRL0 0x0

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# define DIDT_CTRL_EN (1 << 0)

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#define DIDT_DB_CTRL0 0x20

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#define DIDT_TD_CTRL0 0x40

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#define DIDT_TCP_CTRL0 0x60

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/* SMC IND registers */

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#define DPM_TABLE_475 0x3F768

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# define SamuBootLevel(x) ((x) << 0)

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# define SamuBootLevel_MASK 0x000000ff

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# define SamuBootLevel_SHIFT 0

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# define AcpBootLevel(x) ((x) << 8)

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# define AcpBootLevel_MASK 0x0000ff00

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# define AcpBootLevel_SHIFT 8

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# define VceBootLevel(x) ((x) << 16)

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# define VceBootLevel_MASK 0x00ff0000

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# define VceBootLevel_SHIFT 16

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# define UvdBootLevel(x) ((x) << 24)

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# define UvdBootLevel_MASK 0xff000000

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# define UvdBootLevel_SHIFT 24

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#define FIRMWARE_FLAGS 0x3F800

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# define INTERRUPTS_ENABLED (1 << 0)

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#define NB_DPM_CONFIG_1 0x3F9E8

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# define Dpm0PgNbPsLo(x) ((x) << 0)

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# define Dpm0PgNbPsLo_MASK 0x000000ff

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# define Dpm0PgNbPsLo_SHIFT 0

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# define Dpm0PgNbPsHi(x) ((x) << 8)

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# define Dpm0PgNbPsHi_MASK 0x0000ff00

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# define Dpm0PgNbPsHi_SHIFT 8

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# define DpmXNbPsLo(x) ((x) << 16)

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# define DpmXNbPsLo_MASK 0x00ff0000

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# define DpmXNbPsLo_SHIFT 16

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# define DpmXNbPsHi(x) ((x) << 24)

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# define DpmXNbPsHi_MASK 0xff000000

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# define DpmXNbPsHi_SHIFT 24

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#define SMC_SYSCON_RESET_CNTL 0x80000000

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# define RST_REG (1 << 0)

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#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004

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# define CK_DISABLE (1 << 0)

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# define CKEN (1 << 24)

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#define SMC_SYSCON_MISC_CNTL 0x80000010

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#define SMC_SYSCON_MSG_ARG_0 0x80000068

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#define SMC_PC_C 0x80000370

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#define SMC_SCRATCH9 0x80000424

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#define RCU_UC_EVENTS 0xC0000004

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# define BOOT_SEQ_DONE (1 << 7)

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#define GENERAL_PWRMGT 0xC0200000

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# define GLOBAL_PWRMGT_EN (1 << 0)

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# define STATIC_PM_EN (1 << 1)

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# define THERMAL_PROTECTION_DIS (1 << 2)

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# define THERMAL_PROTECTION_TYPE (1 << 3)

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# define SW_SMIO_INDEX(x) ((x) << 6)

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# define SW_SMIO_INDEX_MASK (1 << 6)

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# define SW_SMIO_INDEX_SHIFT 6

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# define VOLT_PWRMGT_EN (1 << 10)

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# define GPU_COUNTER_CLK (1 << 15)

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# define DYN_SPREAD_SPECTRUM_EN (1 << 23)

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#define CNB_PWRMGT_CNTL 0xC0200004

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# define GNB_SLOW_MODE(x) ((x) << 0)

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# define GNB_SLOW_MODE_MASK (3 << 0)

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# define GNB_SLOW_MODE_SHIFT 0

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# define GNB_SLOW (1 << 2)

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# define FORCE_NB_PS1 (1 << 3)

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# define DPM_ENABLED (1 << 4)

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#define SCLK_PWRMGT_CNTL 0xC0200008

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# define SCLK_PWRMGT_OFF (1 << 0)

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# define RESET_BUSY_CNT (1 << 4)

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# define RESET_SCLK_CNT (1 << 5)

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# define DYNAMIC_PM_EN (1 << 21)

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#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014

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# define CURRENT_STATE_MASK (0xf << 4)

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# define CURRENT_STATE_SHIFT 4

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# define CURR_MCLK_INDEX_MASK (0xf << 8)

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# define CURR_MCLK_INDEX_SHIFT 8

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# define CURR_SCLK_INDEX_MASK (0x1f << 16)

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# define CURR_SCLK_INDEX_SHIFT 16

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#define CG_SSP 0xC0200044

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# define SST(x) ((x) << 0)

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# define SST_MASK (0xffff << 0)

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# define SSTU(x) ((x) << 16)

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# define SSTU_MASK (0xf << 16)

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#define CG_DISPLAY_GAP_CNTL 0xC0200060

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# define DISP_GAP(x) ((x) << 0)

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# define DISP_GAP_MASK (3 << 0)

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# define VBI_TIMER_COUNT(x) ((x) << 4)

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# define VBI_TIMER_COUNT_MASK (0x3fff << 4)

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# define VBI_TIMER_UNIT(x) ((x) << 20)

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# define VBI_TIMER_UNIT_MASK (7 << 20)

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# define DISP_GAP_MCHG(x) ((x) << 24)

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# define DISP_GAP_MCHG_MASK (3 << 24)

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#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0

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# define CURR_PCIE_INDEX_MASK (0xf << 24)

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# define CURR_PCIE_INDEX_SHIFT 24

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#define CG_ULV_PARAMETER 0xC0200158

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#define CG_FTV_0 0xC02001A8

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#define CG_FTV_1 0xC02001AC

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#define CG_FTV_2 0xC02001B0

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#define CG_FTV_3 0xC02001B4

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#define CG_FTV_4 0xC02001B8

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#define CG_FTV_5 0xC02001BC

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#define CG_FTV_6 0xC02001C0

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#define CG_FTV_7 0xC02001C4

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#define CG_DISPLAY_GAP_CNTL2 0xC0200230

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#define LCAC_SX0_OVR_SEL 0xC0400D04

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#define LCAC_SX0_OVR_VAL 0xC0400D08

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#define LCAC_MC0_CNTL 0xC0400D30

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#define LCAC_MC0_OVR_SEL 0xC0400D34

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#define LCAC_MC0_OVR_VAL 0xC0400D38

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#define LCAC_MC1_CNTL 0xC0400D3C

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#define LCAC_MC1_OVR_SEL 0xC0400D40

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#define LCAC_MC1_OVR_VAL 0xC0400D44

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#define LCAC_MC2_OVR_SEL 0xC0400D4C

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#define LCAC_MC2_OVR_VAL 0xC0400D50

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#define LCAC_MC3_OVR_SEL 0xC0400D58

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#define LCAC_MC3_OVR_VAL 0xC0400D5C

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#define LCAC_CPL_CNTL 0xC0400D80

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#define LCAC_CPL_OVR_SEL 0xC0400D84

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#define LCAC_CPL_OVR_VAL 0xC0400D88

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/* dGPU */

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#define CG_THERMAL_CTRL 0xC0300004

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#define DPM_EVENT_SRC(x) ((x) << 0)

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#define DPM_EVENT_SRC_MASK (7 << 0)

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#define DIG_THERM_DPM(x) ((x) << 14)

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#define DIG_THERM_DPM_MASK 0x003FC000

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#define DIG_THERM_DPM_SHIFT 14

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#define CG_THERMAL_INT 0xC030000C

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#define CI_DIG_THERM_INTH(x) ((x) << 8)

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#define CI_DIG_THERM_INTH_MASK 0x0000FF00

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#define CI_DIG_THERM_INTH_SHIFT 8

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#define CI_DIG_THERM_INTL(x) ((x) << 16)

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#define CI_DIG_THERM_INTL_MASK 0x00FF0000

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#define CI_DIG_THERM_INTL_SHIFT 16

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#define THERM_INT_MASK_HIGH (1 << 24)

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#define THERM_INT_MASK_LOW (1 << 25)

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#define CG_MULT_THERMAL_STATUS 0xC0300014

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#define ASIC_MAX_TEMP(x) ((x) << 0)

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#define ASIC_MAX_TEMP_MASK 0x000001ff

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#define ASIC_MAX_TEMP_SHIFT 0

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#define CTF_TEMP(x) ((x) << 9)

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#define CTF_TEMP_MASK 0x0003fe00

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#define CTF_TEMP_SHIFT 9

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#define CG_SPLL_FUNC_CNTL 0xC0500140

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#define SPLL_RESET (1 << 0)

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#define SPLL_PWRON (1 << 1)

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#define SPLL_BYPASS_EN (1 << 3)

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#define SPLL_REF_DIV(x) ((x) << 5)

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#define SPLL_REF_DIV_MASK (0x3f << 5)

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#define SPLL_PDIV_A(x) ((x) << 20)

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#define SPLL_PDIV_A_MASK (0x7f << 20)

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#define SPLL_PDIV_A_SHIFT 20

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#define CG_SPLL_FUNC_CNTL_2 0xC0500144

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#define SCLK_MUX_SEL(x) ((x) << 0)

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#define SCLK_MUX_SEL_MASK (0x1ff << 0)

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#define CG_SPLL_FUNC_CNTL_3 0xC0500148

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#define SPLL_FB_DIV(x) ((x) << 0)

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#define SPLL_FB_DIV_MASK (0x3ffffff << 0)

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#define SPLL_FB_DIV_SHIFT 0

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#define SPLL_DITHEN (1 << 28)

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#define CG_SPLL_FUNC_CNTL_4 0xC050014C

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#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164

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#define SSEN (1 << 0)

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#define CLK_S(x) ((x) << 4)

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#define CLK_S_MASK (0xfff << 4)

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#define CLK_S_SHIFT 4

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#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168

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#define CLK_V(x) ((x) << 0)

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#define CLK_V_MASK (0x3ffffff << 0)

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#define CLK_V_SHIFT 0

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#define MPLL_BYPASSCLK_SEL 0xC050019C

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# define MPLL_CLKOUT_SEL(x) ((x) << 8)

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# define MPLL_CLKOUT_SEL_MASK 0xFF00

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#define CG_CLKPIN_CNTL 0xC05001A0

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# define XTALIN_DIVIDE (1 << 1)

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# define BCLK_AS_XCLK (1 << 2)

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#define CG_CLKPIN_CNTL_2 0xC05001A4

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# define FORCE_BIF_REFCLK_EN (1 << 3)

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# define MUX_TCLK_TO_XCLK (1 << 8)

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#define THM_CLK_CNTL 0xC05001A8

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# define CMON_CLK_SEL(x) ((x) << 0)

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# define CMON_CLK_SEL_MASK 0xFF

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# define TMON_CLK_SEL(x) ((x) << 8)

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# define TMON_CLK_SEL_MASK 0xFF00

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#define MISC_CLK_CTRL 0xC05001AC

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# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)

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# define DEEP_SLEEP_CLK_SEL_MASK 0xFF

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# define ZCLK_SEL(x) ((x) << 8)

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# define ZCLK_SEL_MASK 0xFF00

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/* KV/KB */

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#define CG_THERMAL_INT_CTRL 0xC2100028

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#define DIG_THERM_INTH(x) ((x) << 0)

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#define DIG_THERM_INTH_MASK 0x000000FF

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#define DIG_THERM_INTH_SHIFT 0

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#define DIG_THERM_INTL(x) ((x) << 8)

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#define DIG_THERM_INTL_MASK 0x0000FF00

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#define DIG_THERM_INTL_SHIFT 8

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#define THERM_INTH_MASK (1 << 24)

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#define THERM_INTL_MASK (1 << 25)

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/* PCIE registers idx/data 0x38/0x3c */

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#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */

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# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)

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# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)

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# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7

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# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)

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# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)

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# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10

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# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)

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# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)

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# define PLL_RAMP_UP_TIME_0_SHIFT 24

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#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */

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# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)

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# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)

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# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7

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# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)

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# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)

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# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10

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# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)

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# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)

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# define PLL_RAMP_UP_TIME_1_SHIFT 24

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#define PCIE_CNTL2 0x1001001c /* PCIE */

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# define SLV_MEM_LS_EN (1 << 16)

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# define MST_MEM_LS_EN (1 << 18)

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# define REPLAY_MEM_LS_EN (1 << 19)

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#define PCIE_LC_STATUS1 0x1400028 /* PCIE */

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# define LC_REVERSE_RCVR (1 << 0)

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# define LC_REVERSE_XMIT (1 << 1)

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# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)

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# define LC_OPERATING_LINK_WIDTH_SHIFT 2

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# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)

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# define LC_DETECTED_LINK_WIDTH_SHIFT 5

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#define PCIE_P_CNTL 0x1400040 /* PCIE */

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# define P_IGNORE_EDB_ERR (1 << 6)

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#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */

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#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */

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#define PCIE_LC_CNTL 0x100100A0 /* PCIE */

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# define LC_L0S_INACTIVITY(x) ((x) << 8)

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# define LC_L0S_INACTIVITY_MASK (0xf << 8)

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# define LC_L0S_INACTIVITY_SHIFT 8

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# define LC_L1_INACTIVITY(x) ((x) << 12)

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# define LC_L1_INACTIVITY_MASK (0xf << 12)

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# define LC_L1_INACTIVITY_SHIFT 12

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# define LC_PMI_TO_L1_DIS (1 << 16)

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# define LC_ASPM_TO_L1_DIS (1 << 24)

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#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */

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# define LC_LINK_WIDTH_SHIFT 0

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# define LC_LINK_WIDTH_MASK 0x7

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# define LC_LINK_WIDTH_X0 0

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# define LC_LINK_WIDTH_X1 1

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# define LC_LINK_WIDTH_X2 2

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# define LC_LINK_WIDTH_X4 3

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# define LC_LINK_WIDTH_X8 4

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# define LC_LINK_WIDTH_X16 6

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# define LC_LINK_WIDTH_RD_SHIFT 4

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# define LC_LINK_WIDTH_RD_MASK 0x70

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# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

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# define LC_RECONFIG_NOW (1 << 8)

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# define LC_RENEGOTIATION_SUPPORT (1 << 9)

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# define LC_RENEGOTIATE_EN (1 << 10)

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# define LC_SHORT_RECONFIG_EN (1 << 11)

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# define LC_UPCONFIGURE_SUPPORT (1 << 12)

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# define LC_UPCONFIGURE_DIS (1 << 13)

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# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)

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# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)

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# define LC_DYN_LANES_PWR_STATE_SHIFT 21

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#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */

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# define LC_XMIT_N_FTS(x) ((x) << 0)

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# define LC_XMIT_N_FTS_MASK (0xff << 0)

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# define LC_XMIT_N_FTS_SHIFT 0

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# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)

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# define LC_N_FTS_MASK (0xff << 24)

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#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */

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# define LC_GEN2_EN_STRAP (1 << 0)

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# define LC_GEN3_EN_STRAP (1 << 1)

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# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)

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# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)

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# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3

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# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)

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# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)

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# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)

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# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)

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# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)

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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)

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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10

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# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */

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# define LC_CURRENT_DATA_RATE_SHIFT 13

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# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)

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# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)

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# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)

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# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)

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# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)

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#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */

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# define LC_ALLOW_PDWN_IN_L1 (1 << 17)

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# define LC_ALLOW_PDWN_IN_L23 (1 << 18)

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#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */

364

# define LC_GO_TO_RECOVERY (1 << 30)

Alex Deucher

2013-08-06 11:29:39 -0400

[diff] [blame]

365

#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */

366

# define LC_REDO_EQ (1 << 5)

367

# define LC_SET_QUIESCE (1 << 13)

368

369

/* direct registers */

Alex Deucher

6e2c3c0

2013-04-03 19:28:32 -0400

[diff] [blame]

370

#define PCIE_INDEX 0x38

371

#define PCIE_DATA 0x3C

372

Alex Deucher

2013-08-14 01:01:40 -0400

[diff] [blame]

373

#define SMC_IND_INDEX_0 0x200

374

#define SMC_IND_DATA_0 0x204

375

376

#define SMC_IND_ACCESS_CNTL 0x240

377

#define AUTO_INCREMENT_IND_0 (1 << 0)

378

379

#define SMC_MESSAGE_0 0x250

380

#define SMC_MSG_MASK 0xffff

381

#define SMC_RESP_0 0x254

382

#define SMC_RESP_MASK 0xffff

383

384

#define SMC_MSG_ARG_0 0x290

385

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

386

#define VGA_HDP_CONTROL 0x328

387

#define VGA_MEMORY_DISABLE (1 << 4)

388

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

389

#define DMIF_ADDR_CALC 0xC00

390

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

391

#define SRBM_GFX_CNTL 0xE44

392

#define PIPEID(x) ((x) << 0)

393

#define MEID(x) ((x) << 2)

394

#define VMID(x) ((x) << 4)

395

#define QUEUEID(x) ((x) << 8)

396

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

397

#define SRBM_STATUS2 0xE4C

Alex Deucher

cc06671

2013-04-09 12:59:51 -0400

[diff] [blame]

398

#define SDMA_BUSY (1 << 5)

399

#define SDMA1_BUSY (1 << 6)

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

400

#define SRBM_STATUS 0xE50

Alex Deucher

cc06671

2013-04-09 12:59:51 -0400

[diff] [blame]

401

#define UVD_RQ_PENDING (1 << 1)

402

#define GRBM_RQ_PENDING (1 << 5)

403

#define VMC_BUSY (1 << 8)

404

#define MCB_BUSY (1 << 9)

405

#define MCB_NON_DISPLAY_BUSY (1 << 10)

406

#define MCC_BUSY (1 << 11)

407

#define MCD_BUSY (1 << 12)

408

#define SEM_BUSY (1 << 14)

409

#define IH_BUSY (1 << 17)

410

#define UVD_BUSY (1 << 19)

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

411

Alex Deucher

21a93e1

2013-04-09 12:47:11 -0400

[diff] [blame]

412

#define SRBM_SOFT_RESET 0xE60

413

#define SOFT_RESET_BIF (1 << 1)

414

#define SOFT_RESET_R0PLL (1 << 4)

415

#define SOFT_RESET_DC (1 << 5)

416

#define SOFT_RESET_SDMA1 (1 << 6)

417

#define SOFT_RESET_GRBM (1 << 8)

418

#define SOFT_RESET_HDP (1 << 9)

419

#define SOFT_RESET_IH (1 << 10)

420

#define SOFT_RESET_MC (1 << 11)

421

#define SOFT_RESET_ROM (1 << 14)

422

#define SOFT_RESET_SEM (1 << 15)

423

#define SOFT_RESET_VMC (1 << 17)

424

#define SOFT_RESET_SDMA (1 << 20)

425

#define SOFT_RESET_TST (1 << 21)

426

#define SOFT_RESET_REGBB (1 << 22)

427

#define SOFT_RESET_ORB (1 << 23)

428

#define SOFT_RESET_VCE (1 << 24)

429

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

430

#define VM_L2_CNTL 0x1400

431

#define ENABLE_L2_CACHE (1 << 0)

432

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

433

#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)

434

#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)

435

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

436

#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)

437

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)

438

#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)

439

#define VM_L2_CNTL2 0x1404

440

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

441

#define INVALIDATE_L2_CACHE (1 << 1)

442

#define INVALIDATE_CACHE_MODE(x) ((x) << 26)

443

#define INVALIDATE_PTE_AND_PDE_CACHES 0

444

#define INVALIDATE_ONLY_PTE_CACHES 1

445

#define INVALIDATE_ONLY_PDE_CACHES 2

446

#define VM_L2_CNTL3 0x1408

447

#define BANK_SELECT(x) ((x) << 0)

448

#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)

449

#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)

450

#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)

451

#define VM_L2_STATUS 0x140C

452

#define L2_BUSY (1 << 0)

453

#define VM_CONTEXT0_CNTL 0x1410

454

#define ENABLE_CONTEXT (1 << 0)

455

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

Alex Deucher

a00024b

2012-09-18 16:06:01 -0400

[diff] [blame]

456

#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

457

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

Alex Deucher

a00024b

2012-09-18 16:06:01 -0400

[diff] [blame]

458

#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)

459

#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)

460

#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)

461

#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)

462

#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)

463

#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)

464

#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)

465

#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)

466

#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)

467

#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

468

#define VM_CONTEXT1_CNTL 0x1414

469

#define VM_CONTEXT0_CNTL2 0x1430

470

#define VM_CONTEXT1_CNTL2 0x1434

471

#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438

472

#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c

473

#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440

474

#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444

475

#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448

476

#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c

477

#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450

478

#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454

479

480

#define VM_INVALIDATE_REQUEST 0x1478

481

#define VM_INVALIDATE_RESPONSE 0x147c

482

Alex Deucher

9d97c99

2012-09-06 14:24:48 -0400

[diff] [blame]

483

#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC

Alex Deucher

3ec7d11

2013-06-14 10:42:22 -0400

[diff] [blame]

484

#define PROTECTIONS_MASK (0xf << 0)

485

#define PROTECTIONS_SHIFT 0

/* bit 0: range

* bit 1: pde0

* bit 2: valid

* bit 3: read

* bit 4: write

*/

#define MEMORY_CLIENT_ID_MASK (0xff << 12)

493

#define MEMORY_CLIENT_ID_SHIFT 12

494

#define MEMORY_CLIENT_RW_MASK (1 << 24)

495

#define MEMORY_CLIENT_RW_SHIFT 24

496

#define FAULT_VMID_MASK (0xf << 25)

497

#define FAULT_VMID_SHIFT 25

498

499

#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4

Alex Deucher

9d97c99

2012-09-06 14:24:48 -0400

[diff] [blame]

500

501

#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC

502

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

503

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518

504

#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c

505

506

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c

507

#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540

508

#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544

509

#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548

510

#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c

511

#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550

512

#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554

513

#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558

514

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c

515

#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560

516

517

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C

518

#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580

519

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

520

#define VM_L2_CG 0x15c0

521

#define MC_CG_ENABLE (1 << 18)

522

#define MC_LS_ENABLE (1 << 19)

523

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

524

#define MC_SHARED_CHMAP 0x2004

525

#define NOOFCHAN_SHIFT 12

526

#define NOOFCHAN_MASK 0x0000f000

527

#define MC_SHARED_CHREMAP 0x2008

528

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

529

#define CHUB_CONTROL 0x1864

530

#define BYPASS_VM (1 << 0)

531

532

#define MC_VM_FB_LOCATION 0x2024

533

#define MC_VM_AGP_TOP 0x2028

534

#define MC_VM_AGP_BOT 0x202C

535

#define MC_VM_AGP_BASE 0x2030

536

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

537

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

538

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C

539

540

#define MC_VM_MX_L1_TLB_CNTL 0x2064

541

#define ENABLE_L1_TLB (1 << 0)

542

#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

543

#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)

544

#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)

545

#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

546

#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)

547

#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

548

#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)

549

#define MC_VM_FB_OFFSET 0x2068

550

Alex Deucher

2012-06-29 19:44:04 -0400

[diff] [blame]

551

#define MC_SHARED_BLACKOUT_CNTL 0x20ac

552

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

553

#define MC_HUB_MISC_HUB_CG 0x20b8

554

#define MC_HUB_MISC_VM_CG 0x20bc

555

556

#define MC_HUB_MISC_SIP_CG 0x20c0

557

558

#define MC_XPB_CLK_GAT 0x2478

559

560

#define MC_CITF_MISC_RD_CG 0x2648

561

#define MC_CITF_MISC_WR_CG 0x264c

562

#define MC_CITF_MISC_VM_CG 0x2650

563

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

564

#define MC_ARB_RAMCFG 0x2760

565

#define NOOFBANK_SHIFT 0

566

#define NOOFBANK_MASK 0x00000003

567

#define NOOFRANK_SHIFT 2

568

#define NOOFRANK_MASK 0x00000004

569

#define NOOFROWS_SHIFT 3

570

#define NOOFROWS_MASK 0x00000038

571

#define NOOFCOLS_SHIFT 6

572

#define NOOFCOLS_MASK 0x000000C0

573

#define CHANSIZE_SHIFT 8

574

#define CHANSIZE_MASK 0x00000100

575

#define NOOFGROUPS_SHIFT 12

576

#define NOOFGROUPS_MASK 0x00001000

577

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

578

#define MC_ARB_DRAM_TIMING 0x2774

579

#define MC_ARB_DRAM_TIMING2 0x2778

580

581

#define MC_ARB_BURST_TIME 0x2808

582

#define STATE0(x) ((x) << 0)

583

#define STATE0_MASK (0x1f << 0)

584

#define STATE0_SHIFT 0

585

#define STATE1(x) ((x) << 5)

586

#define STATE1_MASK (0x1f << 5)

587

#define STATE1_SHIFT 5

588

#define STATE2(x) ((x) << 10)

589

#define STATE2_MASK (0x1f << 10)

590

#define STATE2_SHIFT 10

591

#define STATE3(x) ((x) << 15)

592

#define STATE3_MASK (0x1f << 15)

593

#define STATE3_SHIFT 15

594

595

#define MC_SEQ_RAS_TIMING 0x28a0

596

#define MC_SEQ_CAS_TIMING 0x28a4

597

#define MC_SEQ_MISC_TIMING 0x28a8

598

#define MC_SEQ_MISC_TIMING2 0x28ac

599

#define MC_SEQ_PMG_TIMING 0x28b0

600

#define MC_SEQ_RD_CTL_D0 0x28b4

601

#define MC_SEQ_RD_CTL_D1 0x28b8

602

#define MC_SEQ_WR_CTL_D0 0x28bc

603

#define MC_SEQ_WR_CTL_D1 0x28c0

604

Alex Deucher

2012-06-29 19:44:04 -0400

[diff] [blame]

605

#define MC_SEQ_SUP_CNTL 0x28c8

606

#define RUN_MASK (1 << 0)

607

#define MC_SEQ_SUP_PGM 0x28cc

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

608

#define MC_PMG_AUTO_CMD 0x28d0

Alex Deucher

2012-06-29 19:44:04 -0400

[diff] [blame]

609

610

#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8

611

#define TRAIN_DONE_D0 (1 << 30)

612

#define TRAIN_DONE_D1 (1 << 31)

613

614

#define MC_IO_PAD_CNTL_D0 0x29d0

615

#define MEM_FALL_OUT_CMD (1 << 8)

616

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

617

#define MC_SEQ_MISC0 0x2a00

618

#define MC_SEQ_MISC0_VEN_ID_SHIFT 8

619

#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00

620

#define MC_SEQ_MISC0_VEN_ID_VALUE 3

621

#define MC_SEQ_MISC0_REV_ID_SHIFT 12

622

#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000

623

#define MC_SEQ_MISC0_REV_ID_VALUE 1

624

#define MC_SEQ_MISC0_GDDR5_SHIFT 28

625

#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000

626

#define MC_SEQ_MISC0_GDDR5_VALUE 5

627

#define MC_SEQ_MISC1 0x2a04

628

#define MC_SEQ_RESERVE_M 0x2a08

629

#define MC_PMG_CMD_EMRS 0x2a0c

630

Alex Deucher

2012-06-29 19:44:04 -0400

[diff] [blame]

631

#define MC_SEQ_IO_DEBUG_INDEX 0x2a44

632

#define MC_SEQ_IO_DEBUG_DATA 0x2a48

633

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

634

#define MC_SEQ_MISC5 0x2a54

635

#define MC_SEQ_MISC6 0x2a58

636

637

#define MC_SEQ_MISC7 0x2a64

638

639

#define MC_SEQ_RAS_TIMING_LP 0x2a6c

640

#define MC_SEQ_CAS_TIMING_LP 0x2a70

641

#define MC_SEQ_MISC_TIMING_LP 0x2a74

642

#define MC_SEQ_MISC_TIMING2_LP 0x2a78

643

#define MC_SEQ_WR_CTL_D0_LP 0x2a7c

644

#define MC_SEQ_WR_CTL_D1_LP 0x2a80

645

#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84

646

#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88

647

648

#define MC_PMG_CMD_MRS 0x2aac

649

650

#define MC_SEQ_RD_CTL_D0_LP 0x2b1c

651

#define MC_SEQ_RD_CTL_D1_LP 0x2b20

652

653

#define MC_PMG_CMD_MRS1 0x2b44

654

#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48

655

#define MC_SEQ_PMG_TIMING_LP 0x2b4c

656

657

#define MC_SEQ_WR_CTL_2 0x2b54

658

#define MC_SEQ_WR_CTL_2_LP 0x2b58

659

#define MC_PMG_CMD_MRS2 0x2b5c

660

#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60

661

662

#define MCLK_PWRMGT_CNTL 0x2ba0

663

# define DLL_SPEED(x) ((x) << 0)

664

# define DLL_SPEED_MASK (0x1f << 0)

665

# define DLL_READY (1 << 6)

666

# define MC_INT_CNTL (1 << 7)

667

# define MRDCK0_PDNB (1 << 8)

668

# define MRDCK1_PDNB (1 << 9)

669

# define MRDCK0_RESET (1 << 16)

670

# define MRDCK1_RESET (1 << 17)

671

# define DLL_READY_READ (1 << 24)

672

#define DLL_CNTL 0x2ba4

673

# define MRDCK0_BYPASS (1 << 24)

674

# define MRDCK1_BYPASS (1 << 25)

675

676

#define MPLL_FUNC_CNTL 0x2bb4

677

#define BWCTRL(x) ((x) << 20)

678

#define BWCTRL_MASK (0xff << 20)

679

#define MPLL_FUNC_CNTL_1 0x2bb8

680

#define VCO_MODE(x) ((x) << 0)

681

#define VCO_MODE_MASK (3 << 0)

682

#define CLKFRAC(x) ((x) << 4)

683

#define CLKFRAC_MASK (0xfff << 4)

684

#define CLKF(x) ((x) << 16)

685

#define CLKF_MASK (0xfff << 16)

686

#define MPLL_FUNC_CNTL_2 0x2bbc

687

#define MPLL_AD_FUNC_CNTL 0x2bc0

688

#define YCLK_POST_DIV(x) ((x) << 0)

689

#define YCLK_POST_DIV_MASK (7 << 0)

690

#define MPLL_DQ_FUNC_CNTL 0x2bc4

691

#define YCLK_SEL(x) ((x) << 4)

692

#define YCLK_SEL_MASK (1 << 4)

693

694

#define MPLL_SS1 0x2bcc

695

#define CLKV(x) ((x) << 0)

696

#define CLKV_MASK (0x3ffffff << 0)

697

#define MPLL_SS2 0x2bd0

698

#define CLKS(x) ((x) << 0)

699

#define CLKS_MASK (0xfff << 0)

700

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

701

#define HDP_HOST_PATH_CNTL 0x2C00

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

702

#define CLOCK_GATING_DIS (1 << 23)

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

703

#define HDP_NONSURFACE_BASE 0x2C04

704

#define HDP_NONSURFACE_INFO 0x2C08

705

#define HDP_NONSURFACE_SIZE 0x2C0C

706

707

#define HDP_ADDR_CONFIG 0x2F48

708

#define HDP_MISC_CNTL 0x2F4C

709

#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

710

#define HDP_MEM_POWER_LS 0x2F50

711

#define HDP_LS_ENABLE (1 << 0)

712

713

#define ATC_MISC_CG 0x3350

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

714

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

715

#define MC_SEQ_CNTL_3 0x3600

716

# define CAC_EN (1 << 31)

717

#define MC_SEQ_G5PDX_CTRL 0x3604

718

#define MC_SEQ_G5PDX_CTRL_LP 0x3608

719

#define MC_SEQ_G5PDX_CMD0 0x360c

720

#define MC_SEQ_G5PDX_CMD0_LP 0x3610

721

#define MC_SEQ_G5PDX_CMD1 0x3614

722

#define MC_SEQ_G5PDX_CMD1_LP 0x3618

723

724

#define MC_SEQ_PMG_DVS_CTL 0x3628

725

#define MC_SEQ_PMG_DVS_CTL_LP 0x362c

726

#define MC_SEQ_PMG_DVS_CMD 0x3630

727

#define MC_SEQ_PMG_DVS_CMD_LP 0x3634

728

#define MC_SEQ_DLL_STBY 0x3638

729

#define MC_SEQ_DLL_STBY_LP 0x363c

730

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

731

#define IH_RB_CNTL 0x3e00

732

# define IH_RB_ENABLE (1 << 0)

733

# define IH_RB_SIZE(x) ((x) << 1) /* log2 */

734

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

735

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

736

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

737

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

738

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

739

#define IH_RB_BASE 0x3e04

740

#define IH_RB_RPTR 0x3e08

741

#define IH_RB_WPTR 0x3e0c

742

# define RB_OVERFLOW (1 << 0)

743

# define WPTR_OFFSET_MASK 0x3fffc

744

#define IH_RB_WPTR_ADDR_HI 0x3e10

745

#define IH_RB_WPTR_ADDR_LO 0x3e14

746

#define IH_CNTL 0x3e18

747

# define ENABLE_INTR (1 << 0)

748

# define IH_MC_SWAP(x) ((x) << 1)

749

# define IH_MC_SWAP_NONE 0

750

# define IH_MC_SWAP_16BIT 1

751

# define IH_MC_SWAP_32BIT 2

752

# define IH_MC_SWAP_64BIT 3

753

# define RPTR_REARM (1 << 4)

754

# define MC_WRREQ_CREDIT(x) ((x) << 15)

755

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

756

# define MC_VMID(x) ((x) << 25)

757

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

758

#define BIF_LNCNT_RESET 0x5220

759

# define RESET_LNCNT_EN (1 << 0)

760

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

761

#define CONFIG_MEMSIZE 0x5428

762

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

763

#define INTERRUPT_CNTL 0x5468

764

# define IH_DUMMY_RD_OVERRIDE (1 << 0)

765

# define IH_DUMMY_RD_EN (1 << 1)

766

# define IH_REQ_NONSNOOP_EN (1 << 3)

767

# define GEN_IH_INT_EN (1 << 8)

768

#define INTERRUPT_CNTL2 0x546c

769

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

770

#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

771

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

772

#define BIF_FB_EN 0x5490

773

#define FB_READ_EN (1 << 0)

774

#define FB_WRITE_EN (1 << 1)

775

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

776

#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

777

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

778

#define GPU_HDP_FLUSH_REQ 0x54DC

779

#define GPU_HDP_FLUSH_DONE 0x54E0

#define CP0 (1 << 0)

#define CP1 (1 << 1)

#define CP2 (1 << 2)

#define CP3 (1 << 3)

#define CP4 (1 << 4)

#define CP5 (1 << 5)

#define CP6 (1 << 6)

#define CP7 (1 << 7)

#define CP8 (1 << 8)

#define CP9 (1 << 9)

#define SDMA0 (1 << 10)

791

#define SDMA1 (1 << 11)

792

Alex Deucher

cd84a27

2012-07-20 17:13:13 -0400

[diff] [blame]

793

/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */

794

#define LB_MEMORY_CTRL 0x6b04

795

#define LB_MEMORY_SIZE(x) ((x) << 0)

796

#define LB_MEMORY_CONFIG(x) ((x) << 20)

797

798

#define DPG_WATERMARK_MASK_CONTROL 0x6cc8

799

# define LATENCY_WATERMARK_MASK(x) ((x) << 8)

800

#define DPG_PIPE_LATENCY_CONTROL 0x6ccc

801

# define LATENCY_LOW_WATERMARK(x) ((x) << 0)

802

# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)

803

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

804

/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */

805

#define LB_VLINE_STATUS 0x6b24

806

# define VLINE_OCCURRED (1 << 0)

807

# define VLINE_ACK (1 << 4)

808

# define VLINE_STAT (1 << 12)

809

# define VLINE_INTERRUPT (1 << 16)

810

# define VLINE_INTERRUPT_TYPE (1 << 17)

811

/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */

812

#define LB_VBLANK_STATUS 0x6b2c

813

# define VBLANK_OCCURRED (1 << 0)

814

# define VBLANK_ACK (1 << 4)

815

# define VBLANK_STAT (1 << 12)

816

# define VBLANK_INTERRUPT (1 << 16)

817

# define VBLANK_INTERRUPT_TYPE (1 << 17)

818

819

/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */

820

#define LB_INTERRUPT_MASK 0x6b20

821

# define VBLANK_INTERRUPT_MASK (1 << 0)

822

# define VLINE_INTERRUPT_MASK (1 << 4)

823

# define VLINE2_INTERRUPT_MASK (1 << 8)

824

825

#define DISP_INTERRUPT_STATUS 0x60f4

826

# define LB_D1_VLINE_INTERRUPT (1 << 2)

827

# define LB_D1_VBLANK_INTERRUPT (1 << 3)

828

# define DC_HPD1_INTERRUPT (1 << 17)

829

# define DC_HPD1_RX_INTERRUPT (1 << 18)

830

# define DACA_AUTODETECT_INTERRUPT (1 << 22)

831

# define DACB_AUTODETECT_INTERRUPT (1 << 23)

832

# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)

833

# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)

834

#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8

835

# define LB_D2_VLINE_INTERRUPT (1 << 2)

836

# define LB_D2_VBLANK_INTERRUPT (1 << 3)

837

# define DC_HPD2_INTERRUPT (1 << 17)

838

# define DC_HPD2_RX_INTERRUPT (1 << 18)

839

# define DISP_TIMER_INTERRUPT (1 << 24)

840

#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc

841

# define LB_D3_VLINE_INTERRUPT (1 << 2)

842

# define LB_D3_VBLANK_INTERRUPT (1 << 3)

843

# define DC_HPD3_INTERRUPT (1 << 17)

844

# define DC_HPD3_RX_INTERRUPT (1 << 18)

845

#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100

846

# define LB_D4_VLINE_INTERRUPT (1 << 2)

847

# define LB_D4_VBLANK_INTERRUPT (1 << 3)

848

# define DC_HPD4_INTERRUPT (1 << 17)

849

# define DC_HPD4_RX_INTERRUPT (1 << 18)

850

#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c

851

# define LB_D5_VLINE_INTERRUPT (1 << 2)

852

# define LB_D5_VBLANK_INTERRUPT (1 << 3)

853

# define DC_HPD5_INTERRUPT (1 << 17)

854

# define DC_HPD5_RX_INTERRUPT (1 << 18)

855

#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150

856

# define LB_D6_VLINE_INTERRUPT (1 << 2)

857

# define LB_D6_VBLANK_INTERRUPT (1 << 3)

858

# define DC_HPD6_INTERRUPT (1 << 17)

859

# define DC_HPD6_RX_INTERRUPT (1 << 18)

860

#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780

861

862

#define DAC_AUTODETECT_INT_CONTROL 0x67c8

863

864

#define DC_HPD1_INT_STATUS 0x601c

865

#define DC_HPD2_INT_STATUS 0x6028

866

#define DC_HPD3_INT_STATUS 0x6034

867

#define DC_HPD4_INT_STATUS 0x6040

868

#define DC_HPD5_INT_STATUS 0x604c

869

#define DC_HPD6_INT_STATUS 0x6058

870

# define DC_HPDx_INT_STATUS (1 << 0)

871

# define DC_HPDx_SENSE (1 << 1)

872

# define DC_HPDx_SENSE_DELAYED (1 << 4)

873

# define DC_HPDx_RX_INT_STATUS (1 << 8)

874

875

#define DC_HPD1_INT_CONTROL 0x6020

876

#define DC_HPD2_INT_CONTROL 0x602c

877

#define DC_HPD3_INT_CONTROL 0x6038

878

#define DC_HPD4_INT_CONTROL 0x6044

879

#define DC_HPD5_INT_CONTROL 0x6050

880

#define DC_HPD6_INT_CONTROL 0x605c

881

# define DC_HPDx_INT_ACK (1 << 0)

882

# define DC_HPDx_INT_POLARITY (1 << 8)

883

# define DC_HPDx_INT_EN (1 << 16)

884

# define DC_HPDx_RX_INT_ACK (1 << 20)

885

# define DC_HPDx_RX_INT_EN (1 << 24)

886

887

#define DC_HPD1_CONTROL 0x6024

888

#define DC_HPD2_CONTROL 0x6030

889

#define DC_HPD3_CONTROL 0x603c

890

#define DC_HPD4_CONTROL 0x6048

891

#define DC_HPD5_CONTROL 0x6054

892

#define DC_HPD6_CONTROL 0x6060

893

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

894

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

895

# define DC_HPDx_EN (1 << 28)

896

Alex Deucher

2013-08-14 01:03:41 -0400

[diff] [blame]

897

#define DPG_PIPE_STUTTER_CONTROL 0x6cd4

898

# define STUTTER_ENABLE (1 << 0)

899

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

900

#define GRBM_CNTL 0x8000

901

#define GRBM_READ_TIMEOUT(x) ((x) << 0)

902

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

903

#define GRBM_STATUS2 0x8008

904

#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F

905

#define ME0PIPE1_CF_RQ_PENDING (1 << 4)

906

#define ME0PIPE1_PF_RQ_PENDING (1 << 5)

907

#define ME1PIPE0_RQ_PENDING (1 << 6)

908

#define ME1PIPE1_RQ_PENDING (1 << 7)

909

#define ME1PIPE2_RQ_PENDING (1 << 8)

910

#define ME1PIPE3_RQ_PENDING (1 << 9)

911

#define ME2PIPE0_RQ_PENDING (1 << 10)

912

#define ME2PIPE1_RQ_PENDING (1 << 11)

913

#define ME2PIPE2_RQ_PENDING (1 << 12)

914

#define ME2PIPE3_RQ_PENDING (1 << 13)

915

#define RLC_RQ_PENDING (1 << 14)

916

#define RLC_BUSY (1 << 24)

917

#define TC_BUSY (1 << 25)

918

#define CPF_BUSY (1 << 28)

919

#define CPC_BUSY (1 << 29)

920

#define CPG_BUSY (1 << 30)

921

922

#define GRBM_STATUS 0x8010

923

#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F

924

#define SRBM_RQ_PENDING (1 << 5)

925

#define ME0PIPE0_CF_RQ_PENDING (1 << 7)

926

#define ME0PIPE0_PF_RQ_PENDING (1 << 8)

927

#define GDS_DMA_RQ_PENDING (1 << 9)

928

#define DB_CLEAN (1 << 12)

929

#define CB_CLEAN (1 << 13)

930

#define TA_BUSY (1 << 14)

931

#define GDS_BUSY (1 << 15)

932

#define WD_BUSY_NO_DMA (1 << 16)

933

#define VGT_BUSY (1 << 17)

934

#define IA_BUSY_NO_DMA (1 << 18)

935

#define IA_BUSY (1 << 19)

936

#define SX_BUSY (1 << 20)

937

#define WD_BUSY (1 << 21)

938

#define SPI_BUSY (1 << 22)

939

#define BCI_BUSY (1 << 23)

940

#define SC_BUSY (1 << 24)

941

#define PA_BUSY (1 << 25)

942

#define DB_BUSY (1 << 26)

943

#define CP_COHERENCY_BUSY (1 << 28)

944

#define CP_BUSY (1 << 29)

945

#define CB_BUSY (1 << 30)

946

#define GUI_ACTIVE (1 << 31)

947

#define GRBM_STATUS_SE0 0x8014

948

#define GRBM_STATUS_SE1 0x8018

949

#define GRBM_STATUS_SE2 0x8038

950

#define GRBM_STATUS_SE3 0x803C

951

#define SE_DB_CLEAN (1 << 1)

952

#define SE_CB_CLEAN (1 << 2)

953

#define SE_BCI_BUSY (1 << 22)

954

#define SE_VGT_BUSY (1 << 23)

955

#define SE_PA_BUSY (1 << 24)

956

#define SE_TA_BUSY (1 << 25)

957

#define SE_SX_BUSY (1 << 26)

958

#define SE_SPI_BUSY (1 << 27)

959

#define SE_SC_BUSY (1 << 29)

960

#define SE_DB_BUSY (1 << 30)

961

#define SE_CB_BUSY (1 << 31)

962

963

#define GRBM_SOFT_RESET 0x8020

964

#define SOFT_RESET_CP (1 << 0) /* All CP blocks */

965

#define SOFT_RESET_RLC (1 << 2) /* RLC */

966

#define SOFT_RESET_GFX (1 << 16) /* GFX */

967

#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */

968

#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */

969

#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */

970

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

971

#define GRBM_INT_CNTL 0x8060

972

# define RDERR_INT_ENABLE (1 << 0)

973

# define GUI_IDLE_INT_ENABLE (1 << 19)

974

Alex Deucher

2013-06-26 17:37:11 -0400

[diff] [blame]

975

#define CP_CPC_STATUS 0x8210

976

#define CP_CPC_BUSY_STAT 0x8214

977

#define CP_CPC_STALLED_STAT1 0x8218

978

#define CP_CPF_STATUS 0x821c

979

#define CP_CPF_BUSY_STAT 0x8220

980

#define CP_CPF_STALLED_STAT1 0x8224

981

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

982

#define CP_MEC_CNTL 0x8234

983

#define MEC_ME2_HALT (1 << 28)

984

#define MEC_ME1_HALT (1 << 30)

985

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

986

#define CP_MEC_CNTL 0x8234

987

#define MEC_ME2_HALT (1 << 28)

988

#define MEC_ME1_HALT (1 << 30)

989

Alex Deucher

2013-06-26 17:37:11 -0400

[diff] [blame]

990

#define CP_STALLED_STAT3 0x8670

991

#define CP_STALLED_STAT1 0x8674

992

#define CP_STALLED_STAT2 0x8678

993

994

#define CP_STAT 0x8680

995

Alex Deucher

2013-04-09 12:43:41 -0400

[diff] [blame]

996

#define CP_ME_CNTL 0x86D8

997

#define CP_CE_HALT (1 << 24)

998

#define CP_PFP_HALT (1 << 26)

999

#define CP_ME_HALT (1 << 28)

1000

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1001

#define CP_RB0_RPTR 0x8700

1002

#define CP_RB_WPTR_DELAY 0x8704

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1003

#define CP_RB_WPTR_POLL_CNTL 0x8708

1004

#define IDLE_POLL_COUNT(x) ((x) << 16)

1005

#define IDLE_POLL_COUNT_MASK (0xffff << 16)

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1006

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

1007

#define CP_MEQ_THRESHOLDS 0x8764

1008

#define MEQ1_START(x) ((x) << 0)

1009

#define MEQ2_START(x) ((x) << 8)

1010

1011

#define VGT_VTX_VECT_EJECT_REG 0x88B0

1012

1013

#define VGT_CACHE_INVALIDATION 0x88C4

1014

#define CACHE_INVALIDATION(x) ((x) << 0)

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define AUTO_INVLD_EN(x) ((x) << 6)

#define NO_AUTO 0

#define ES_AUTO 1

#define GS_AUTO 2

#define ES_AND_GS_AUTO 3

1023

1024

#define VGT_GS_VERTEX_REUSE 0x88D4

1025

1026

#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc

1027

#define INACTIVE_CUS_MASK 0xFFFF0000

1028

#define INACTIVE_CUS_SHIFT 16

1029

#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0

1030

1031

#define PA_CL_ENHANCE 0x8A14

1032

#define CLIP_VTX_REORDER_ENA (1 << 0)

1033

#define NUM_CLIP_SEQ(x) ((x) << 1)

1034

1035

#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24

1036

#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

1037

#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)

1038

1039

#define PA_SC_FIFO_SIZE 0x8BCC

1040

#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)

1041

#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)

1042

#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)

1043

#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)

1044

1045

#define PA_SC_ENHANCE 0x8BF0

1046

#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)

1047

#define DISABLE_PA_SC_GUIDANCE (1 << 13)

1048

1049

#define SQ_CONFIG 0x8C00

1050

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

1051

#define SH_MEM_BASES 0x8C28

1052

/* if PTR32, these are the bases for scratch and lds */

1053

#define PRIVATE_BASE(x) ((x) << 0) /* scratch */

1054

#define SHARED_BASE(x) ((x) << 16) /* LDS */

1055

#define SH_MEM_APE1_BASE 0x8C2C

1056

/* if PTR32, this is the base location of GPUVM */

1057

#define SH_MEM_APE1_LIMIT 0x8C30

1058

/* if PTR32, this is the upper limit of GPUVM */

1059

#define SH_MEM_CONFIG 0x8C34

1060

#define PTR32 (1 << 0)

1061

#define ALIGNMENT_MODE(x) ((x) << 2)

1062

#define SH_MEM_ALIGNMENT_MODE_DWORD 0

1063

#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1

1064

#define SH_MEM_ALIGNMENT_MODE_STRICT 2

1065

#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3

1066

#define DEFAULT_MTYPE(x) ((x) << 4)

1067

#define APE1_MTYPE(x) ((x) << 7)

1068

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

1069

#define SX_DEBUG_1 0x9060

1070

1071

#define SPI_CONFIG_CNTL 0x9100

1072

1073

#define SPI_CONFIG_CNTL_1 0x913C

1074

#define VTX_DONE_DELAY(x) ((x) << 0)

1075

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

1076

1077

#define TA_CNTL_AUX 0x9508

1078

1079

#define DB_DEBUG 0x9830

1080

#define DB_DEBUG2 0x9834

1081

#define DB_DEBUG3 0x9838

1082

1083

#define CC_RB_BACKEND_DISABLE 0x98F4

1084

#define BACKEND_DISABLE(x) ((x) << 16)

1085

#define GB_ADDR_CONFIG 0x98F8

1086

#define NUM_PIPES(x) ((x) << 0)

1087

#define NUM_PIPES_MASK 0x00000007

1088

#define NUM_PIPES_SHIFT 0

1089

#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)

1090

#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070

1091

#define PIPE_INTERLEAVE_SIZE_SHIFT 4

1092

#define NUM_SHADER_ENGINES(x) ((x) << 12)

1093

#define NUM_SHADER_ENGINES_MASK 0x00003000

1094

#define NUM_SHADER_ENGINES_SHIFT 12

1095

#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)

1096

#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000

1097

#define SHADER_ENGINE_TILE_SIZE_SHIFT 16

1098

#define ROW_SIZE(x) ((x) << 28)

1099

#define ROW_SIZE_MASK 0x30000000

1100

#define ROW_SIZE_SHIFT 28

1101

1102

#define GB_TILE_MODE0 0x9910

1103

# define ARRAY_MODE(x) ((x) << 2)

1104

# define ARRAY_LINEAR_GENERAL 0

1105

# define ARRAY_LINEAR_ALIGNED 1

1106

# define ARRAY_1D_TILED_THIN1 2

1107

# define ARRAY_2D_TILED_THIN1 4

1108

# define ARRAY_PRT_TILED_THIN1 5

1109

# define ARRAY_PRT_2D_TILED_THIN1 6

1110

# define PIPE_CONFIG(x) ((x) << 6)

1111

# define ADDR_SURF_P2 0

1112

# define ADDR_SURF_P4_8x16 4

1113

# define ADDR_SURF_P4_16x16 5

1114

# define ADDR_SURF_P4_16x32 6

1115

# define ADDR_SURF_P4_32x32 7

1116

# define ADDR_SURF_P8_16x16_8x16 8

1117

# define ADDR_SURF_P8_16x32_8x16 9

1118

# define ADDR_SURF_P8_32x32_8x16 10

1119

# define ADDR_SURF_P8_16x32_16x16 11

1120

# define ADDR_SURF_P8_32x32_16x16 12

1121

# define ADDR_SURF_P8_32x32_16x32 13

1122

# define ADDR_SURF_P8_32x64_32x32 14

1123

# define TILE_SPLIT(x) ((x) << 11)

1124

# define ADDR_SURF_TILE_SPLIT_64B 0

1125

# define ADDR_SURF_TILE_SPLIT_128B 1

1126

# define ADDR_SURF_TILE_SPLIT_256B 2

1127

# define ADDR_SURF_TILE_SPLIT_512B 3

1128

# define ADDR_SURF_TILE_SPLIT_1KB 4

1129

# define ADDR_SURF_TILE_SPLIT_2KB 5

1130

# define ADDR_SURF_TILE_SPLIT_4KB 6

1131

# define MICRO_TILE_MODE_NEW(x) ((x) << 22)

1132

# define ADDR_SURF_DISPLAY_MICRO_TILING 0

1133

# define ADDR_SURF_THIN_MICRO_TILING 1

1134

# define ADDR_SURF_DEPTH_MICRO_TILING 2

1135

# define ADDR_SURF_ROTATED_MICRO_TILING 3

1136

# define SAMPLE_SPLIT(x) ((x) << 25)

1137

# define ADDR_SURF_SAMPLE_SPLIT_1 0

1138

# define ADDR_SURF_SAMPLE_SPLIT_2 1

1139

# define ADDR_SURF_SAMPLE_SPLIT_4 2

1140

# define ADDR_SURF_SAMPLE_SPLIT_8 3

1141

1142

#define GB_MACROTILE_MODE0 0x9990

1143

# define BANK_WIDTH(x) ((x) << 0)

1144

# define ADDR_SURF_BANK_WIDTH_1 0

1145

# define ADDR_SURF_BANK_WIDTH_2 1

1146

# define ADDR_SURF_BANK_WIDTH_4 2

1147

# define ADDR_SURF_BANK_WIDTH_8 3

1148

# define BANK_HEIGHT(x) ((x) << 2)

1149

# define ADDR_SURF_BANK_HEIGHT_1 0

1150

# define ADDR_SURF_BANK_HEIGHT_2 1

1151

# define ADDR_SURF_BANK_HEIGHT_4 2

1152

# define ADDR_SURF_BANK_HEIGHT_8 3

1153

# define MACRO_TILE_ASPECT(x) ((x) << 4)

1154

# define ADDR_SURF_MACRO_ASPECT_1 0

1155

# define ADDR_SURF_MACRO_ASPECT_2 1

1156

# define ADDR_SURF_MACRO_ASPECT_4 2

1157

# define ADDR_SURF_MACRO_ASPECT_8 3

1158

# define NUM_BANKS(x) ((x) << 6)

1159

# define ADDR_SURF_2_BANK 0

1160

# define ADDR_SURF_4_BANK 1

1161

# define ADDR_SURF_8_BANK 2

1162

# define ADDR_SURF_16_BANK 3

1163

1164

#define CB_HW_CONTROL 0x9A10

1165

1166

#define GC_USER_RB_BACKEND_DISABLE 0x9B7C

1167

#define BACKEND_DISABLE_MASK 0x00FF0000

1168

#define BACKEND_DISABLE_SHIFT 16

1169

1170

#define TCP_CHAN_STEER_LO 0xac0c

1171

#define TCP_CHAN_STEER_HI 0xac10

1172

Alex Deucher

2013-04-09 12:45:26 -0400

[diff] [blame]

1173

#define TC_CFG_L1_LOAD_POLICY0 0xAC68

1174

#define TC_CFG_L1_LOAD_POLICY1 0xAC6C

1175

#define TC_CFG_L1_STORE_POLICY 0xAC70

1176

#define TC_CFG_L2_LOAD_POLICY0 0xAC74

1177

#define TC_CFG_L2_LOAD_POLICY1 0xAC78

1178

#define TC_CFG_L2_STORE_POLICY0 0xAC7C

1179

#define TC_CFG_L2_STORE_POLICY1 0xAC80

1180

#define TC_CFG_L2_ATOMIC_POLICY 0xAC84

1181

#define TC_CFG_L1_VOLATILE 0xAC88

1182

#define TC_CFG_L2_VOLATILE 0xAC8C

1183

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1184

#define CP_RB0_BASE 0xC100

1185

#define CP_RB0_CNTL 0xC104

1186

#define RB_BUFSZ(x) ((x) << 0)

1187

#define RB_BLKSZ(x) ((x) << 8)

1188

#define BUF_SWAP_32BIT (2 << 16)

1189

#define RB_NO_UPDATE (1 << 27)

1190

#define RB_RPTR_WR_ENA (1 << 31)

1191

1192

#define CP_RB0_RPTR_ADDR 0xC10C

1193

#define RB_RPTR_SWAP_32BIT (2 << 0)

1194

#define CP_RB0_RPTR_ADDR_HI 0xC110

1195

#define CP_RB0_WPTR 0xC114

1196

1197

#define CP_DEVICE_ID 0xC12C

1198

#define CP_ENDIAN_SWAP 0xC140

1199

#define CP_RB_VMID 0xC144

1200

1201

#define CP_PFP_UCODE_ADDR 0xC150

1202

#define CP_PFP_UCODE_DATA 0xC154

1203

#define CP_ME_RAM_RADDR 0xC158

1204

#define CP_ME_RAM_WADDR 0xC15C

1205

#define CP_ME_RAM_DATA 0xC160

1206

1207

#define CP_CE_UCODE_ADDR 0xC168

1208

#define CP_CE_UCODE_DATA 0xC16C

1209

#define CP_MEC_ME1_UCODE_ADDR 0xC170

1210

#define CP_MEC_ME1_UCODE_DATA 0xC174

1211

#define CP_MEC_ME2_UCODE_ADDR 0xC178

1212

#define CP_MEC_ME2_UCODE_DATA 0xC17C

1213

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1214

#define CP_INT_CNTL_RING0 0xC1A8

1215

# define CNTX_BUSY_INT_ENABLE (1 << 19)

1216

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

1217

# define PRIV_INSTR_INT_ENABLE (1 << 22)

1218

# define PRIV_REG_INT_ENABLE (1 << 23)

1219

# define TIME_STAMP_INT_ENABLE (1 << 26)

1220

# define CP_RINGID2_INT_ENABLE (1 << 29)

1221

# define CP_RINGID1_INT_ENABLE (1 << 30)

1222

# define CP_RINGID0_INT_ENABLE (1 << 31)

1223

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

1224

#define CP_INT_STATUS_RING0 0xC1B4

1225

# define PRIV_INSTR_INT_STAT (1 << 22)

1226

# define PRIV_REG_INT_STAT (1 << 23)

1227

# define TIME_STAMP_INT_STAT (1 << 26)

1228

# define CP_RINGID2_INT_STAT (1 << 29)

1229

# define CP_RINGID1_INT_STAT (1 << 30)

1230

# define CP_RINGID0_INT_STAT (1 << 31)

1231

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1232

#define CP_MEM_SLP_CNTL 0xC1E4

1233

# define CP_MEM_LS_EN (1 << 0)

1234

Alex Deucher

2013-06-26 17:37:11 -0400

[diff] [blame]

1235

#define CP_CPF_DEBUG 0xC200

1236

1237

#define CP_PQ_WPTR_POLL_CNTL 0xC20C

1238

#define WPTR_POLL_EN (1 << 31)

1239

Alex Deucher

2012-11-09 10:45:57 -0500

[diff] [blame]

1240

#define CP_ME1_PIPE0_INT_CNTL 0xC214

1241

#define CP_ME1_PIPE1_INT_CNTL 0xC218

1242

#define CP_ME1_PIPE2_INT_CNTL 0xC21C

1243

#define CP_ME1_PIPE3_INT_CNTL 0xC220

1244

#define CP_ME2_PIPE0_INT_CNTL 0xC224

1245

#define CP_ME2_PIPE1_INT_CNTL 0xC228

1246

#define CP_ME2_PIPE2_INT_CNTL 0xC22C

1247

#define CP_ME2_PIPE3_INT_CNTL 0xC230

1248

# define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)

1249

# define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)

1250

# define PRIV_REG_INT_ENABLE (1 << 23)

1251

# define TIME_STAMP_INT_ENABLE (1 << 26)

1252

# define GENERIC2_INT_ENABLE (1 << 29)

1253

# define GENERIC1_INT_ENABLE (1 << 30)

1254

# define GENERIC0_INT_ENABLE (1 << 31)

1255

#define CP_ME1_PIPE0_INT_STATUS 0xC214

1256

#define CP_ME1_PIPE1_INT_STATUS 0xC218

1257

#define CP_ME1_PIPE2_INT_STATUS 0xC21C

1258

#define CP_ME1_PIPE3_INT_STATUS 0xC220

1259

#define CP_ME2_PIPE0_INT_STATUS 0xC224

1260

#define CP_ME2_PIPE1_INT_STATUS 0xC228

1261

#define CP_ME2_PIPE2_INT_STATUS 0xC22C

1262

#define CP_ME2_PIPE3_INT_STATUS 0xC230

1263

# define DEQUEUE_REQUEST_INT_STATUS (1 << 13)

1264

# define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)

1265

# define PRIV_REG_INT_STATUS (1 << 23)

1266

# define TIME_STAMP_INT_STATUS (1 << 26)

1267

# define GENERIC2_INT_STATUS (1 << 29)

1268

# define GENERIC1_INT_STATUS (1 << 30)

1269

# define GENERIC0_INT_STATUS (1 << 31)

1270

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1271

#define CP_MAX_CONTEXT 0xC2B8

1272

1273

#define CP_RB0_BASE_HI 0xC2C4

1274

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1275

#define RLC_CNTL 0xC300

1276

# define RLC_ENABLE (1 << 0)

1277

1278

#define RLC_MC_CNTL 0xC30C

1279

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1280

#define RLC_MEM_SLP_CNTL 0xC318

1281

# define RLC_MEM_LS_EN (1 << 0)

1282

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1283

#define RLC_LB_CNTR_MAX 0xC348

1284

1285

#define RLC_LB_CNTL 0xC364

Alex Deucher

866d83d

2013-04-15 17:13:29 -0400

[diff] [blame]

1286

# define LOAD_BALANCE_ENABLE (1 << 0)

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1287

1288

#define RLC_LB_CNTR_INIT 0xC36C

1289

1290

#define RLC_SAVE_AND_RESTORE_BASE 0xC374

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1291

#define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */

1292

#define RLC_CP_TABLE_RESTORE 0xC378 /* APU */

1293

#define RLC_PG_DELAY_2 0xC37C

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1294

1295

#define RLC_GPM_UCODE_ADDR 0xC388

1296

#define RLC_GPM_UCODE_DATA 0xC38C

Alex Deucher

44fa346

2012-12-18 22:17:00 -0500

[diff] [blame]

1297

#define RLC_GPU_CLOCK_COUNT_LSB 0xC390

1298

#define RLC_GPU_CLOCK_COUNT_MSB 0xC394

1299

#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1300

#define RLC_UCODE_CNTL 0xC39C

1301

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1302

#define RLC_GPM_STAT 0xC400

1303

# define RLC_GPM_BUSY (1 << 0)

Alex Deucher

a412fce

2013-04-22 20:23:31 -0400

[diff] [blame]

1304

# define GFX_POWER_STATUS (1 << 1)

1305

# define GFX_CLOCK_STATUS (1 << 2)

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1306

1307

#define RLC_PG_CNTL 0xC40C

1308

# define GFX_PG_ENABLE (1 << 0)

1309

# define GFX_PG_SRC (1 << 1)

1310

# define DYN_PER_CU_PG_ENABLE (1 << 2)

1311

# define STATIC_PER_CU_PG_ENABLE (1 << 3)

1312

# define DISABLE_GDS_PG (1 << 13)

1313

# define DISABLE_CP_PG (1 << 15)

1314

# define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)

1315

# define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)

1316

1317

#define RLC_CGTT_MGCG_OVERRIDE 0xC420

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1318

#define RLC_CGCG_CGLS_CTRL 0xC424

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1319

# define CGCG_EN (1 << 0)

1320

# define CGLS_EN (1 << 1)

1321

1322

#define RLC_PG_DELAY 0xC434

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1323

1324

#define RLC_LB_INIT_CU_MASK 0xC43C

1325

1326

#define RLC_LB_PARAMS 0xC444

1327

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1328

#define RLC_PG_AO_CU_MASK 0xC44C

1329

1330

#define RLC_MAX_PG_CU 0xC450

1331

# define MAX_PU_CU(x) ((x) << 0)

1332

# define MAX_PU_CU_MASK (0xff << 0)

1333

#define RLC_AUTO_PG_CTRL 0xC454

1334

# define AUTO_PG_EN (1 << 0)

1335

# define GRBM_REG_SGIT(x) ((x) << 3)

1336

# define GRBM_REG_SGIT_MASK (0xffff << 3)

1337

1338

#define RLC_SERDES_WR_CU_MASTER_MASK 0xC474

1339

#define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478

1340

#define RLC_SERDES_WR_CTRL 0xC47C

1341

#define BPM_ADDR(x) ((x) << 0)

1342

#define BPM_ADDR_MASK (0xff << 0)

1343

#define CGLS_ENABLE (1 << 16)

1344

#define CGCG_OVERRIDE_0 (1 << 20)

1345

#define MGCG_OVERRIDE_0 (1 << 22)

1346

#define MGCG_OVERRIDE_1 (1 << 23)

1347

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1348

#define RLC_SERDES_CU_MASTER_BUSY 0xC484

1349

#define RLC_SERDES_NONCU_MASTER_BUSY 0xC488

1350

# define SE_MASTER_BUSY_MASK 0x0000ffff

1351

# define GC_MASTER_BUSY (1 << 16)

1352

# define TC0_MASTER_BUSY (1 << 17)

1353

# define TC1_MASTER_BUSY (1 << 18)

1354

1355

#define RLC_GPM_SCRATCH_ADDR 0xC4B0

1356

#define RLC_GPM_SCRATCH_DATA 0xC4B4

1357

Alex Deucher

a412fce

2013-04-22 20:23:31 -0400

[diff] [blame]

1358

#define RLC_GPR_REG2 0xC4E8

1359

#define REQ 0x00000001

1360

#define MESSAGE(x) ((x) << 1)

1361

#define MESSAGE_MASK 0x0000001e

1362

#define MSG_ENTER_RLC_SAFE_MODE 1

1363

#define MSG_EXIT_RLC_SAFE_MODE 0

1364

Alex Deucher

2013-06-26 17:37:11 -0400

[diff] [blame]

1365

#define CP_HPD_EOP_BASE_ADDR 0xC904

1366

#define CP_HPD_EOP_BASE_ADDR_HI 0xC908

1367

#define CP_HPD_EOP_VMID 0xC90C

1368

#define CP_HPD_EOP_CONTROL 0xC910

1369

#define EOP_SIZE(x) ((x) << 0)

1370

#define EOP_SIZE_MASK (0x3f << 0)

1371

#define CP_MQD_BASE_ADDR 0xC914

1372

#define CP_MQD_BASE_ADDR_HI 0xC918

1373

#define CP_HQD_ACTIVE 0xC91C

1374

#define CP_HQD_VMID 0xC920

1375

1376

#define CP_HQD_PQ_BASE 0xC934

1377

#define CP_HQD_PQ_BASE_HI 0xC938

1378

#define CP_HQD_PQ_RPTR 0xC93C

1379

#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940

1380

#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944

1381

#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948

1382

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C

1383

#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950

1384

#define DOORBELL_OFFSET(x) ((x) << 2)

1385

#define DOORBELL_OFFSET_MASK (0x1fffff << 2)

1386

#define DOORBELL_SOURCE (1 << 28)

1387

#define DOORBELL_SCHD_HIT (1 << 29)

1388

#define DOORBELL_EN (1 << 30)

1389

#define DOORBELL_HIT (1 << 31)

1390

#define CP_HQD_PQ_WPTR 0xC954

1391

#define CP_HQD_PQ_CONTROL 0xC958

1392

#define QUEUE_SIZE(x) ((x) << 0)

1393

#define QUEUE_SIZE_MASK (0x3f << 0)

1394

#define RPTR_BLOCK_SIZE(x) ((x) << 8)

1395

#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)

1396

#define PQ_VOLATILE (1 << 26)

1397

#define NO_UPDATE_RPTR (1 << 27)

1398

#define UNORD_DISPATCH (1 << 28)

1399

#define ROQ_PQ_IB_FLIP (1 << 29)

1400

#define PRIV_STATE (1 << 30)

1401

#define KMD_QUEUE (1 << 31)

1402

1403

#define CP_HQD_DEQUEUE_REQUEST 0xC974

1404

1405

#define CP_MQD_CONTROL 0xC99C

1406

#define MQD_VMID(x) ((x) << 0)

1407

#define MQD_VMID_MASK (0xf << 0)

1408

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1409

#define DB_RENDER_CONTROL 0x28000

1410

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

1411

#define PA_SC_RASTER_CONFIG 0x28350

1412

# define RASTER_CONFIG_RB_MAP_0 0

1413

# define RASTER_CONFIG_RB_MAP_1 1

1414

# define RASTER_CONFIG_RB_MAP_2 2

1415

# define RASTER_CONFIG_RB_MAP_3 3

1416

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1417

#define VGT_EVENT_INITIATOR 0x28a90

1418

# define SAMPLE_STREAMOUTSTATS1 (1 << 0)

1419

# define SAMPLE_STREAMOUTSTATS2 (2 << 0)

1420

# define SAMPLE_STREAMOUTSTATS3 (3 << 0)

1421

# define CACHE_FLUSH_TS (4 << 0)

1422

# define CACHE_FLUSH (6 << 0)

1423

# define CS_PARTIAL_FLUSH (7 << 0)

1424

# define VGT_STREAMOUT_RESET (10 << 0)

1425

# define END_OF_PIPE_INCR_DE (11 << 0)

1426

# define END_OF_PIPE_IB_END (12 << 0)

1427

# define RST_PIX_CNT (13 << 0)

1428

# define VS_PARTIAL_FLUSH (15 << 0)

1429

# define PS_PARTIAL_FLUSH (16 << 0)

1430

# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)

1431

# define ZPASS_DONE (21 << 0)

1432

# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)

1433

# define PERFCOUNTER_START (23 << 0)

1434

# define PERFCOUNTER_STOP (24 << 0)

1435

# define PIPELINESTAT_START (25 << 0)

1436

# define PIPELINESTAT_STOP (26 << 0)

1437

# define PERFCOUNTER_SAMPLE (27 << 0)

1438

# define SAMPLE_PIPELINESTAT (30 << 0)

1439

# define SO_VGT_STREAMOUT_FLUSH (31 << 0)

1440

# define SAMPLE_STREAMOUTSTATS (32 << 0)

1441

# define RESET_VTX_CNT (33 << 0)

1442

# define VGT_FLUSH (36 << 0)

1443

# define BOTTOM_OF_PIPE_TS (40 << 0)

1444

# define DB_CACHE_FLUSH_AND_INV (42 << 0)

1445

# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)

1446

# define FLUSH_AND_INV_DB_META (44 << 0)

1447

# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)

1448

# define FLUSH_AND_INV_CB_META (46 << 0)

1449

# define CS_DONE (47 << 0)

1450

# define PS_DONE (48 << 0)

1451

# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)

1452

# define THREAD_TRACE_START (51 << 0)

1453

# define THREAD_TRACE_STOP (52 << 0)

1454

# define THREAD_TRACE_FLUSH (54 << 0)

1455

# define THREAD_TRACE_FINISH (55 << 0)

1456

# define PIXEL_PIPE_STAT_CONTROL (56 << 0)

1457

# define PIXEL_PIPE_STAT_DUMP (57 << 0)

1458

# define PIXEL_PIPE_STAT_RESET (58 << 0)

1459

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1460

#define SCRATCH_REG0 0x30100

1461

#define SCRATCH_REG1 0x30104

1462

#define SCRATCH_REG2 0x30108

1463

#define SCRATCH_REG3 0x3010C

1464

#define SCRATCH_REG4 0x30110

1465

#define SCRATCH_REG5 0x30114

1466

#define SCRATCH_REG6 0x30118

1467

#define SCRATCH_REG7 0x3011C

1468

1469

#define SCRATCH_UMSK 0x30140

1470

#define SCRATCH_ADDR 0x30144

1471

1472

#define CP_SEM_WAIT_TIMER 0x301BC

1473

1474

#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8

1475

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1476

#define CP_WAIT_REG_MEM_TIMEOUT 0x301D0

1477

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

1478

#define GRBM_GFX_INDEX 0x30800

1479

#define INSTANCE_INDEX(x) ((x) << 0)

1480

#define SH_INDEX(x) ((x) << 8)

1481

#define SE_INDEX(x) ((x) << 16)

1482

#define SH_BROADCAST_WRITES (1 << 29)

1483

#define INSTANCE_BROADCAST_WRITES (1 << 30)

1484

#define SE_BROADCAST_WRITES (1 << 31)

1485

1486

#define VGT_ESGS_RING_SIZE 0x30900

1487

#define VGT_GSVS_RING_SIZE 0x30904

1488

#define VGT_PRIMITIVE_TYPE 0x30908

1489

#define VGT_INDEX_TYPE 0x3090C

1490

1491

#define VGT_NUM_INDICES 0x30930

1492

#define VGT_NUM_INSTANCES 0x30934

1493

#define VGT_TF_RING_SIZE 0x30938

1494

#define VGT_HS_OFFCHIP_PARAM 0x3093C

1495

#define VGT_TF_MEMORY_BASE 0x30940

1496

1497

#define PA_SU_LINE_STIPPLE_VALUE 0x30a00

1498

#define PA_SC_LINE_STIPPLE_STATE 0x30a04

1499

1500

#define SQC_CACHES 0x30d20

1501

1502

#define CP_PERFMON_CNTL 0x36020

1503

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1504

#define CGTS_SM_CTRL_REG 0x3c000

1505

#define SM_MODE(x) ((x) << 17)

1506

#define SM_MODE_MASK (0x7 << 17)

1507

#define SM_MODE_ENABLE (1 << 20)

1508

#define CGTS_OVERRIDE (1 << 21)

1509

#define CGTS_LS_OVERRIDE (1 << 22)

1510

#define ON_MONITOR_ADD_EN (1 << 23)

1511

#define ON_MONITOR_ADD(x) ((x) << 24)

1512

#define ON_MONITOR_ADD_MASK (0xff << 24)

1513

Alex Deucher

2013-04-09 12:41:24 -0400

[diff] [blame]

1514

#define CGTS_TCC_DISABLE 0x3c00c

1515

#define CGTS_USER_TCC_DISABLE 0x3c010

1516

#define TCC_DISABLE_MASK 0xFFFF0000

1517

#define TCC_DISABLE_SHIFT 16

1518

Alex Deucher

2012-11-09 10:44:08 -0500

[diff] [blame]

1519

#define CB_CGTT_SCLK_CTRL 0x3c2a0

1520

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

/*

* PM4

*/

#define PACKET_TYPE0 0

1525

#define PACKET_TYPE1 1

1526

#define PACKET_TYPE2 2

1527

#define PACKET_TYPE3 3

1528

1529

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)

1530

#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)

1531

#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)

1532

#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)

1533

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

1534

(((reg) >> 2) & 0xFFFF) | \

1535

((n) & 0x3FFF) << 16)

1536

#define CP_PACKET2 0x80000000

1537

#define PACKET2_PAD_SHIFT 0

1538

#define PACKET2_PAD_MASK (0x3fffffff << 0)

1539

1540

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

1541

1542

#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \

1543

(((op) & 0xFF) << 8) | \

1544

((n) & 0x3FFF) << 16)

1545

1546

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

1547

1548

/* Packet 3 types */

1549

#define PACKET3_NOP 0x10

1550

#define PACKET3_SET_BASE 0x11

1551

#define PACKET3_BASE_INDEX(x) ((x) << 0)

1552

#define CE_PARTITION_BASE 3

1553

#define PACKET3_CLEAR_STATE 0x12

1554

#define PACKET3_INDEX_BUFFER_SIZE 0x13

1555

#define PACKET3_DISPATCH_DIRECT 0x15

1556

#define PACKET3_DISPATCH_INDIRECT 0x16

1557

#define PACKET3_ATOMIC_GDS 0x1D

1558

#define PACKET3_ATOMIC_MEM 0x1E

1559

#define PACKET3_OCCLUSION_QUERY 0x1F

1560

#define PACKET3_SET_PREDICATION 0x20

1561

#define PACKET3_REG_RMW 0x21

1562

#define PACKET3_COND_EXEC 0x22

1563

#define PACKET3_PRED_EXEC 0x23

1564

#define PACKET3_DRAW_INDIRECT 0x24

1565

#define PACKET3_DRAW_INDEX_INDIRECT 0x25

1566

#define PACKET3_INDEX_BASE 0x26

1567

#define PACKET3_DRAW_INDEX_2 0x27

1568

#define PACKET3_CONTEXT_CONTROL 0x28

1569

#define PACKET3_INDEX_TYPE 0x2A

1570

#define PACKET3_DRAW_INDIRECT_MULTI 0x2C

1571

#define PACKET3_DRAW_INDEX_AUTO 0x2D

1572

#define PACKET3_NUM_INSTANCES 0x2F

1573

#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30

1574

#define PACKET3_INDIRECT_BUFFER_CONST 0x33

1575

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

1576

#define PACKET3_DRAW_INDEX_OFFSET_2 0x35

1577

#define PACKET3_DRAW_PREAMBLE 0x36

1578

#define PACKET3_WRITE_DATA 0x37

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1579

#define WRITE_DATA_DST_SEL(x) ((x) << 8)

1580

/* 0 - register

1581

* 1 - memory (sync - via GRBM)

* 2 - gl2

* 3 - gds

* 4 - reserved

* 5 - memory (async - direct)

1586

*/

1587

#define WR_ONE_ADDR (1 << 16)

1588

#define WR_CONFIRM (1 << 20)

1589

#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)

/* 0 - LRU

* 1 - Stream

*/

#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)

/* 0 - me

* 1 - pfp

* 2 - ce

*/

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1598

#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38

1599

#define PACKET3_MEM_SEMAPHORE 0x39

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1600

# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)

1601

# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */

1602

# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */

1603

# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)

1604

# define PACKET3_SEM_SEL_WAIT (0x7 << 29)

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1605

#define PACKET3_COPY_DW 0x3B

1606

#define PACKET3_WAIT_REG_MEM 0x3C

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1607

#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)

/* 0 - always

* 1 - <

* 2 - <=

* 3 - ==

* 4 - !=

* 5 - >=

* 6 - >

*/

#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)

/* 0 - reg

* 1 - mem

*/

#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)

/* 0 - wait_reg_mem

* 1 - wr_wait_wr_reg

*/

#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)

1625

/* 0 - me

1626

* 1 - pfp

1627

*/

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1628

#define PACKET3_INDIRECT_BUFFER 0x3F

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1629

#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)

1630

#define INDIRECT_BUFFER_VALID (1 << 23)

1631

#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)

/* 0 - LRU

* 1 - Stream

* 2 - Bypass

*/

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1636

#define PACKET3_COPY_DATA 0x40

1637

#define PACKET3_PFP_SYNC_ME 0x42

1638

#define PACKET3_SURFACE_SYNC 0x43

1639

# define PACKET3_DEST_BASE_0_ENA (1 << 0)

1640

# define PACKET3_DEST_BASE_1_ENA (1 << 1)

1641

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

1642

# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)

1643

# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)

1644

# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)

1645

# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)

1646

# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)

1647

# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)

1648

# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)

1649

# define PACKET3_DB_DEST_BASE_ENA (1 << 14)

1650

# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)

1651

# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */

1652

# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */

1653

# define PACKET3_DEST_BASE_2_ENA (1 << 19)

1654

# define PACKET3_DEST_BASE_3_ENA (1 << 21)

1655

# define PACKET3_TCL1_ACTION_ENA (1 << 22)

1656

# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */

1657

# define PACKET3_CB_ACTION_ENA (1 << 25)

1658

# define PACKET3_DB_ACTION_ENA (1 << 26)

1659

# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)

1660

# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)

1661

# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)

1662

#define PACKET3_COND_WRITE 0x45

1663

#define PACKET3_EVENT_WRITE 0x46

1664

#define EVENT_TYPE(x) ((x) << 0)

1665

#define EVENT_INDEX(x) ((x) << 8)

1666

/* 0 - any non-TS event

1667

* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*

1668

* 2 - SAMPLE_PIPELINESTAT

1669

* 3 - SAMPLE_STREAMOUTSTAT*

1670

* 4 - *S_PARTIAL_FLUSH

* 5 - EOP events

* 6 - EOS events

*/

#define PACKET3_EVENT_WRITE_EOP 0x47

1675

#define EOP_TCL1_VOL_ACTION_EN (1 << 12)

1676

#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */

1677

#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */

1678

#define EOP_TCL1_ACTION_EN (1 << 16)

1679

#define EOP_TC_ACTION_EN (1 << 17) /* L2 */

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1680

#define EOP_CACHE_POLICY(x) ((x) << 25)

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

/* 0 - LRU

* 1 - Stream

* 2 - Bypass

*/

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1685

#define EOP_TCL2_VOLATILE (1 << 27)

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1686

#define DATA_SEL(x) ((x) << 29)

1687

/* 0 - discard

1688

* 1 - send low 32bit data

1689

* 2 - send 64bit data

1690

* 3 - send 64bit GPU counter value

1691

* 4 - send 64bit sys counter value

1692

*/

1693

#define INT_SEL(x) ((x) << 24)

1694

/* 0 - none

1695

* 1 - interrupt only (DATA_SEL = 0)

1696

* 2 - interrupt when data write is confirmed

1697

*/

1698

#define DST_SEL(x) ((x) << 16)

/* 0 - MC

* 1 - TC/L2

*/

#define PACKET3_EVENT_WRITE_EOS 0x48

1703

#define PACKET3_RELEASE_MEM 0x49

1704

#define PACKET3_PREAMBLE_CNTL 0x4A

1705

# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)

1706

# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)

1707

#define PACKET3_DMA_DATA 0x50

1708

#define PACKET3_AQUIRE_MEM 0x58

1709

#define PACKET3_REWIND 0x59

1710

#define PACKET3_LOAD_UCONFIG_REG 0x5E

1711

#define PACKET3_LOAD_SH_REG 0x5F

1712

#define PACKET3_LOAD_CONFIG_REG 0x60

1713

#define PACKET3_LOAD_CONTEXT_REG 0x61

1714

#define PACKET3_SET_CONFIG_REG 0x68

1715

#define PACKET3_SET_CONFIG_REG_START 0x00008000

1716

#define PACKET3_SET_CONFIG_REG_END 0x0000b000

1717

#define PACKET3_SET_CONTEXT_REG 0x69

1718

#define PACKET3_SET_CONTEXT_REG_START 0x00028000

1719

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

1720

#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73

1721

#define PACKET3_SET_SH_REG 0x76

1722

#define PACKET3_SET_SH_REG_START 0x0000b000

1723

#define PACKET3_SET_SH_REG_END 0x0000c000

1724

#define PACKET3_SET_SH_REG_OFFSET 0x77

1725

#define PACKET3_SET_QUEUE_REG 0x78

1726

#define PACKET3_SET_UCONFIG_REG 0x79

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1727

#define PACKET3_SET_UCONFIG_REG_START 0x00030000

1728

#define PACKET3_SET_UCONFIG_REG_END 0x00031000

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1729

#define PACKET3_SCRATCH_RAM_WRITE 0x7D

1730

#define PACKET3_SCRATCH_RAM_READ 0x7E

1731

#define PACKET3_LOAD_CONST_RAM 0x80

1732

#define PACKET3_WRITE_CONST_RAM 0x81

1733

#define PACKET3_DUMP_CONST_RAM 0x83

1734

#define PACKET3_INCREMENT_CE_COUNTER 0x84

1735

#define PACKET3_INCREMENT_DE_COUNTER 0x85

1736

#define PACKET3_WAIT_ON_CE_COUNTER 0x86

1737

#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88

Alex Deucher

2012-07-05 11:45:40 -0400

[diff] [blame]

1738

#define PACKET3_SWITCH_BUFFER 0x8B

Alex Deucher

2012-12-18 21:47:44 -0500

[diff] [blame]

1739

Alex Deucher

21a93e1

2013-04-09 12:47:11 -0400

[diff] [blame]

1740

/* SDMA - first instance at 0xd000, second at 0xd800 */

1741

#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */

1742

#define SDMA1_REGISTER_OFFSET 0x800 /* not a register */

1743

1744

#define SDMA0_UCODE_ADDR 0xD000

1745

#define SDMA0_UCODE_DATA 0xD004

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1746

#define SDMA0_POWER_CNTL 0xD008

1747

#define SDMA0_CLK_CTRL 0xD00C

Alex Deucher

21a93e1

2013-04-09 12:47:11 -0400

[diff] [blame]

1748

1749

#define SDMA0_CNTL 0xD010

1750

# define TRAP_ENABLE (1 << 0)

1751

# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)

1752

# define SEM_WAIT_INT_ENABLE (1 << 2)

1753

# define DATA_SWAP_ENABLE (1 << 3)

1754

# define FENCE_SWAP_ENABLE (1 << 4)

1755

# define AUTO_CTXSW_ENABLE (1 << 18)

1756

# define CTXEMPTY_INT_ENABLE (1 << 28)

1757

1758

#define SDMA0_TILING_CONFIG 0xD018

1759

1760

#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020

1761

#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024

1762

1763

#define SDMA0_STATUS_REG 0xd034

1764

# define SDMA_IDLE (1 << 0)

1765

1766

#define SDMA0_ME_CNTL 0xD048

1767

# define SDMA_HALT (1 << 0)

1768

1769

#define SDMA0_GFX_RB_CNTL 0xD200

1770

# define SDMA_RB_ENABLE (1 << 0)

1771

# define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */

1772

# define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */

1773

# define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)

1774

# define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */

1775

# define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */

1776

#define SDMA0_GFX_RB_BASE 0xD204

1777

#define SDMA0_GFX_RB_BASE_HI 0xD208

1778

#define SDMA0_GFX_RB_RPTR 0xD20C

1779

#define SDMA0_GFX_RB_WPTR 0xD210

1780

1781

#define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220

1782

#define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224

1783

#define SDMA0_GFX_IB_CNTL 0xD228

1784

# define SDMA_IB_ENABLE (1 << 0)

1785

# define SDMA_IB_SWAP_ENABLE (1 << 4)

1786

# define SDMA_SWITCH_INSIDE_IB (1 << 8)

1787

# define SDMA_CMD_VMID(x) ((x) << 16)

1788

1789

#define SDMA0_GFX_VIRTUAL_ADDR 0xD29C

1790

#define SDMA0_GFX_APE1_CNTL 0xD2A0

1791

1792

#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \

1793

(((sub_op) & 0xFF) << 8) | \

1794

(((op) & 0xFF) << 0))

1795

/* sDMA opcodes */

1796

#define SDMA_OPCODE_NOP 0

1797

#define SDMA_OPCODE_COPY 1

1798

# define SDMA_COPY_SUB_OPCODE_LINEAR 0

1799

# define SDMA_COPY_SUB_OPCODE_TILED 1

1800

# define SDMA_COPY_SUB_OPCODE_SOA 3

1801

# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4

1802

# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5

1803

# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6

1804

#define SDMA_OPCODE_WRITE 2

1805

# define SDMA_WRITE_SUB_OPCODE_LINEAR 0

1806

# define SDMA_WRTIE_SUB_OPCODE_TILED 1

1807

#define SDMA_OPCODE_INDIRECT_BUFFER 4

1808

#define SDMA_OPCODE_FENCE 5

1809

#define SDMA_OPCODE_TRAP 6

1810

#define SDMA_OPCODE_SEMAPHORE 7

1811

# define SDMA_SEMAPHORE_EXTRA_O (1 << 13)

/* 0 - increment

* 1 - write 1

*/

# define SDMA_SEMAPHORE_EXTRA_S (1 << 14)

/* 0 - wait

* 1 - signal

*/

# define SDMA_SEMAPHORE_EXTRA_M (1 << 15)

1820

/* mailbox */

1821

#define SDMA_OPCODE_POLL_REG_MEM 8

1822

# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)

/* 0 - wait_reg_mem

* 1 - wr_wait_wr_reg

*/

# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)

/* 0 - always

* 1 - <

* 2 - <=

* 3 - ==

* 4 - !=

* 5 - >=

* 6 - >

*/

# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)

/* 0 = register

* 1 = memory

*/

#define SDMA_OPCODE_COND_EXEC 9

1840

#define SDMA_OPCODE_CONSTANT_FILL 11

1841

# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)

/* 0 = byte fill

* 2 = DW fill

*/

#define SDMA_OPCODE_GENERATE_PTE_PDE 12

1846

#define SDMA_OPCODE_TIMESTAMP 13

1847

# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0

1848

# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1

1849

# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2

1850

#define SDMA_OPCODE_SRBM_WRITE 14

1851

# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)

1852

/* byte mask */

1853

Christian König

87167bb

2013-04-09 13:39:21 -0400

[diff] [blame]

1854

/* UVD */

1855

1856

#define UVD_UDEC_ADDR_CONFIG 0xef4c

1857

#define UVD_UDEC_DB_ADDR_CONFIG 0xef50

1858

#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54

1859

1860

#define UVD_LMI_EXT40_ADDR 0xf498

1861

#define UVD_LMI_ADDR_EXT 0xf594

1862

#define UVD_VCPU_CACHE_OFFSET0 0xf608

1863

#define UVD_VCPU_CACHE_SIZE0 0xf60c

1864

#define UVD_VCPU_CACHE_OFFSET1 0xf610

1865

#define UVD_VCPU_CACHE_SIZE1 0xf614

1866

#define UVD_VCPU_CACHE_OFFSET2 0xf618

1867

#define UVD_VCPU_CACHE_SIZE2 0xf61c

1868

1869

#define UVD_RBC_RB_RPTR 0xf690

1870

#define UVD_RBC_RB_WPTR 0xf694

1871

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1872

#define UVD_CGC_CTRL 0xF4B0

1873

# define DCM (1 << 0)

1874

# define CG_DT(x) ((x) << 2)

1875

# define CG_DT_MASK (0xf << 2)

1876

# define CLK_OD(x) ((x) << 6)

1877

# define CLK_OD_MASK (0x1f << 6)

1878

Christian König

87167bb

2013-04-09 13:39:21 -0400

[diff] [blame]

1879

/* UVD clocks */

1880

1881

#define CG_DCLK_CNTL 0xC050009C

1882

# define DCLK_DIVIDER_MASK 0x7f

1883

# define DCLK_DIR_CNTL_EN (1 << 8)

1884

#define CG_DCLK_STATUS 0xC05000A0

1885

# define DCLK_STATUS (1 << 0)

1886

#define CG_VCLK_CNTL 0xC05000A4

1887

#define CG_VCLK_STATUS 0xC05000A8

1888

Alex Deucher

2013-07-23 09:41:05 -0400

[diff] [blame]

1889

/* UVD CTX indirect */

1890

#define UVD_CGC_MEM_CTRL 0xC0

1891

Alex Deucher