blob: 1b05896648bce47cff20ed04acbf5d1ee6175a8b [file] [log] [blame]
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001/*
2 * Driver for OHCI 1394 controllers
Kristian Høgsberged568912006-12-19 19:58:35 -05003 *
Kristian Høgsberged568912006-12-19 19:58:35 -05004 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
Stefan Richter65b27422010-06-12 20:26:51 +020021#include <linux/bug.h>
Stefan Richtere524f6162007-08-20 21:58:30 +020022#include <linux/compiler.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050023#include <linux/delay.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020024#include <linux/device.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080025#include <linux/dma-mapping.h>
Stefan Richter77c9a5d2009-06-05 16:26:18 +020026#include <linux/firewire.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020027#include <linux/firewire-constants.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020028#include <linux/init.h>
29#include <linux/interrupt.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020030#include <linux/io.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020031#include <linux/kernel.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020032#include <linux/list.h>
Al Virofaa2fb42007-05-15 20:36:10 +010033#include <linux/mm.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020034#include <linux/module.h>
Stefan Richterad3c0fe2008-03-20 22:04:36 +010035#include <linux/moduleparam.h>
Stefan Richter02d37be2010-07-08 16:09:06 +020036#include <linux/mutex.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020037#include <linux/pci.h>
Stefan Richterfc383792009-08-28 13:25:15 +020038#include <linux/pci_ids.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090039#include <linux/slab.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020040#include <linux/spinlock.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020041#include <linux/string.h>
Stefan Richtere78483c2010-08-02 09:33:25 +020042#include <linux/time.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080043
Stefan Richtere8ca9702009-06-04 21:09:38 +020044#include <asm/byteorder.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020045#include <asm/page.h>
Stefan Richteree71c2f2007-08-25 14:08:19 +020046#include <asm/system.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050047
Stefan Richterea8d0062008-03-01 02:42:56 +010048#ifdef CONFIG_PPC_PMAC
49#include <asm/pmac_feature.h>
50#endif
51
Stefan Richter77c9a5d2009-06-05 16:26:18 +020052#include "core.h"
53#include "ohci.h"
Kristian Høgsberged568912006-12-19 19:58:35 -050054
Kristian Høgsberga77754a2007-05-07 20:33:35 -040055#define DESCRIPTOR_OUTPUT_MORE 0
56#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
57#define DESCRIPTOR_INPUT_MORE (2 << 12)
58#define DESCRIPTOR_INPUT_LAST (3 << 12)
59#define DESCRIPTOR_STATUS (1 << 11)
60#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
61#define DESCRIPTOR_PING (1 << 7)
62#define DESCRIPTOR_YY (1 << 6)
63#define DESCRIPTOR_NO_IRQ (0 << 4)
64#define DESCRIPTOR_IRQ_ERROR (1 << 4)
65#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
66#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
67#define DESCRIPTOR_WAIT (3 << 0)
Kristian Høgsberged568912006-12-19 19:58:35 -050068
69struct descriptor {
70 __le16 req_count;
71 __le16 control;
72 __le32 data_address;
73 __le32 branch_address;
74 __le16 res_count;
75 __le16 transfer_status;
76} __attribute__((aligned(16)));
77
Kristian Høgsberga77754a2007-05-07 20:33:35 -040078#define CONTROL_SET(regs) (regs)
79#define CONTROL_CLEAR(regs) ((regs) + 4)
80#define COMMAND_PTR(regs) ((regs) + 12)
81#define CONTEXT_MATCH(regs) ((regs) + 16)
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050082
Kristian Høgsberg32b46092007-02-06 14:49:30 -050083struct ar_buffer {
84 struct descriptor descriptor;
85 struct ar_buffer *next;
86 __le32 data[0];
87};
88
Kristian Høgsberged568912006-12-19 19:58:35 -050089struct ar_context {
90 struct fw_ohci *ohci;
Kristian Høgsberg32b46092007-02-06 14:49:30 -050091 struct ar_buffer *current_buffer;
92 struct ar_buffer *last_buffer;
93 void *pointer;
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050094 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -050095 struct tasklet_struct tasklet;
96};
97
Kristian Høgsberg30200732007-02-16 17:34:39 -050098struct context;
99
100typedef int (*descriptor_callback_t)(struct context *ctx,
101 struct descriptor *d,
102 struct descriptor *last);
David Moorefe5ca632008-01-06 17:21:41 -0500103
104/*
105 * A buffer that contains a block of DMA-able coherent memory used for
106 * storing a portion of a DMA descriptor program.
107 */
108struct descriptor_buffer {
109 struct list_head list;
110 dma_addr_t buffer_bus;
111 size_t buffer_size;
112 size_t used;
113 struct descriptor buffer[0];
114};
115
Kristian Høgsberg30200732007-02-16 17:34:39 -0500116struct context {
Stefan Richter373b2ed2007-03-04 14:45:18 +0100117 struct fw_ohci *ohci;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500118 u32 regs;
David Moorefe5ca632008-01-06 17:21:41 -0500119 int total_allocation;
Stefan Richter373b2ed2007-03-04 14:45:18 +0100120
David Moorefe5ca632008-01-06 17:21:41 -0500121 /*
122 * List of page-sized buffers for storing DMA descriptors.
123 * Head of list contains buffers in use and tail of list contains
124 * free buffers.
125 */
126 struct list_head buffer_list;
127
128 /*
129 * Pointer to a buffer inside buffer_list that contains the tail
130 * end of the current DMA program.
131 */
132 struct descriptor_buffer *buffer_tail;
133
134 /*
135 * The descriptor containing the branch address of the first
136 * descriptor that has not yet been filled by the device.
137 */
138 struct descriptor *last;
139
140 /*
141 * The last descriptor in the DMA program. It contains the branch
142 * address that must be updated upon appending a new descriptor.
143 */
144 struct descriptor *prev;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500145
146 descriptor_callback_t callback;
147
Stefan Richter373b2ed2007-03-04 14:45:18 +0100148 struct tasklet_struct tasklet;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500149};
Kristian Høgsberg30200732007-02-16 17:34:39 -0500150
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400151#define IT_HEADER_SY(v) ((v) << 0)
152#define IT_HEADER_TCODE(v) ((v) << 4)
153#define IT_HEADER_CHANNEL(v) ((v) << 8)
154#define IT_HEADER_TAG(v) ((v) << 14)
155#define IT_HEADER_SPEED(v) ((v) << 16)
156#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
Kristian Høgsberged568912006-12-19 19:58:35 -0500157
158struct iso_context {
159 struct fw_iso_context base;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500160 struct context context;
David Moore0642b652007-12-19 03:09:18 -0500161 int excess_bytes;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500162 void *header;
163 size_t header_length;
Kristian Høgsberged568912006-12-19 19:58:35 -0500164};
165
166#define CONFIG_ROM_SIZE 1024
167
168struct fw_ohci {
169 struct fw_card card;
170
171 __iomem char *registers;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500172 int node_id;
Kristian Høgsberged568912006-12-19 19:58:35 -0500173 int generation;
Stefan Richtere09770d2008-03-11 02:23:29 +0100174 int request_generation; /* for timestamping incoming requests */
Stefan Richter4a635592010-02-21 17:58:01 +0100175 unsigned quirks;
Clemens Ladischa1a11322010-06-10 08:35:06 +0200176 unsigned int pri_req_max;
Clemens Ladischa48777e2010-06-10 08:33:07 +0200177 u32 bus_time;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +0200178 bool is_root;
Stefan Richterc8a94de2010-06-12 20:34:50 +0200179 bool csr_state_setclear_abdicate;
Kristian Høgsberged568912006-12-19 19:58:35 -0500180
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400181 /*
182 * Spinlock for accessing fw_ohci data. Never call out of
183 * this driver with this lock held.
184 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500185 spinlock_t lock;
Kristian Høgsberged568912006-12-19 19:58:35 -0500186
Stefan Richter02d37be2010-07-08 16:09:06 +0200187 struct mutex phy_reg_mutex;
188
Kristian Høgsberged568912006-12-19 19:58:35 -0500189 struct ar_context ar_request_ctx;
190 struct ar_context ar_response_ctx;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500191 struct context at_request_ctx;
192 struct context at_response_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -0500193
Stefan Richter872e3302010-07-29 18:19:22 +0200194 u32 it_context_mask; /* unoccupied IT contexts */
Kristian Høgsberged568912006-12-19 19:58:35 -0500195 struct iso_context *it_context_list;
Stefan Richter872e3302010-07-29 18:19:22 +0200196 u64 ir_context_channels; /* unoccupied channels */
197 u32 ir_context_mask; /* unoccupied IR contexts */
Kristian Høgsberged568912006-12-19 19:58:35 -0500198 struct iso_context *ir_context_list;
Stefan Richter872e3302010-07-29 18:19:22 +0200199 u64 mc_channels; /* channels in use by the multichannel IR context */
200 bool mc_allocated;
Stefan Richterecb1cf92010-02-21 17:57:32 +0100201
202 __be32 *config_rom;
203 dma_addr_t config_rom_bus;
204 __be32 *next_config_rom;
205 dma_addr_t next_config_rom_bus;
206 __be32 next_header;
207
208 __le32 *self_id_cpu;
209 dma_addr_t self_id_bus;
210 struct tasklet_struct bus_reset_tasklet;
211
212 u32 self_id_buffer[512];
Kristian Høgsberged568912006-12-19 19:58:35 -0500213};
214
Adrian Bunk95688e92007-01-22 19:17:37 +0100215static inline struct fw_ohci *fw_ohci(struct fw_card *card)
Kristian Høgsberged568912006-12-19 19:58:35 -0500216{
217 return container_of(card, struct fw_ohci, card);
218}
219
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500220#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
221#define IR_CONTEXT_BUFFER_FILL 0x80000000
222#define IR_CONTEXT_ISOCH_HEADER 0x40000000
223#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
224#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
225#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
Kristian Høgsberged568912006-12-19 19:58:35 -0500226
227#define CONTEXT_RUN 0x8000
228#define CONTEXT_WAKE 0x1000
229#define CONTEXT_DEAD 0x0800
230#define CONTEXT_ACTIVE 0x0400
231
Stefan Richter8b7b6af2009-01-20 19:10:58 +0100232#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
Kristian Høgsberged568912006-12-19 19:58:35 -0500233#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
234#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
235
Kristian Høgsberged568912006-12-19 19:58:35 -0500236#define OHCI1394_REGISTER_SIZE 0x800
237#define OHCI_LOOP_COUNT 500
238#define OHCI1394_PCI_HCI_Control 0x40
239#define SELF_ID_BUF_SIZE 0x800
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500240#define OHCI_TCODE_PHY_PACKET 0x0e
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500241#define OHCI_VERSION_1_1 0x010010
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500242
Kristian Høgsberged568912006-12-19 19:58:35 -0500243static char ohci_driver_name[] = KBUILD_MODNAME;
244
Clemens Ladisch262444e2010-06-05 12:31:25 +0200245#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
Clemens Ladisch8301b912010-03-17 11:07:55 +0100246#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
247
Stefan Richter4a635592010-02-21 17:58:01 +0100248#define QUIRK_CYCLE_TIMER 1
249#define QUIRK_RESET_PACKET 2
250#define QUIRK_BE_HEADERS 4
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200251#define QUIRK_NO_1394A 8
Clemens Ladisch262444e2010-06-05 12:31:25 +0200252#define QUIRK_NO_MSI 16
Stefan Richter4a635592010-02-21 17:58:01 +0100253
254/* In case of multiple matches in ohci_quirks[], only the first one is used. */
255static const struct {
256 unsigned short vendor, device, flags;
257} ohci_quirks[] = {
Clemens Ladisch8301b912010-03-17 11:07:55 +0100258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200259 QUIRK_RESET_PACKET |
260 QUIRK_NO_1394A},
Stefan Richter4a635592010-02-21 17:58:01 +0100261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
Clemens Ladisch262444e2010-06-05 12:31:25 +0200263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
Stefan Richter4a635592010-02-21 17:58:01 +0100264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
Heikki Lindholm970f4be2010-09-06 22:30:45 +0300266 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
Stefan Richter4a635592010-02-21 17:58:01 +0100267 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
268};
269
Stefan Richter3e9cc2f2010-02-21 17:58:29 +0100270/* This overrides anything that was found in ohci_quirks[]. */
271static int param_quirks;
272module_param_named(quirks, param_quirks, int, 0644);
273MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
274 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
275 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
276 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200277 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
Clemens Ladisch262444e2010-06-05 12:31:25 +0200278 ", disable MSI = " __stringify(QUIRK_NO_MSI)
Stefan Richter3e9cc2f2010-02-21 17:58:29 +0100279 ")");
280
Stefan Richtera007bb82008-04-07 22:33:35 +0200281#define OHCI_PARAM_DEBUG_AT_AR 1
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100282#define OHCI_PARAM_DEBUG_SELFIDS 2
Stefan Richtera007bb82008-04-07 22:33:35 +0200283#define OHCI_PARAM_DEBUG_IRQS 4
284#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100285
Stefan Richter5da3dac2010-04-02 14:05:02 +0200286#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
287
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100288static int param_debug;
289module_param_named(debug, param_debug, int, 0644);
290MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100291 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
Stefan Richtera007bb82008-04-07 22:33:35 +0200292 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
293 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
294 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100295 ", or a combination, or all = -1)");
296
297static void log_irqs(u32 evt)
298{
Stefan Richtera007bb82008-04-07 22:33:35 +0200299 if (likely(!(param_debug &
300 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100301 return;
302
Stefan Richtera007bb82008-04-07 22:33:35 +0200303 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
304 !(evt & OHCI1394_busReset))
305 return;
306
Clemens Ladischa48777e2010-06-10 08:33:07 +0200307 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
Stefan Richter161b96e2008-06-14 14:23:43 +0200308 evt & OHCI1394_selfIDComplete ? " selfID" : "",
309 evt & OHCI1394_RQPkt ? " AR_req" : "",
310 evt & OHCI1394_RSPkt ? " AR_resp" : "",
311 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
312 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
313 evt & OHCI1394_isochRx ? " IR" : "",
314 evt & OHCI1394_isochTx ? " IT" : "",
315 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
316 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
Clemens Ladischa48777e2010-06-10 08:33:07 +0200317 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
Jay Fenlason5ed1f322009-11-17 12:29:17 -0500318 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
Stefan Richter161b96e2008-06-14 14:23:43 +0200319 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
320 evt & OHCI1394_busReset ? " busReset" : "",
321 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
322 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
323 OHCI1394_respTxComplete | OHCI1394_isochRx |
324 OHCI1394_isochTx | OHCI1394_postedWriteErr |
Clemens Ladischa48777e2010-06-10 08:33:07 +0200325 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
326 OHCI1394_cycleInconsistent |
Stefan Richter161b96e2008-06-14 14:23:43 +0200327 OHCI1394_regAccessFail | OHCI1394_busReset)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100328 ? " ?" : "");
329}
330
331static const char *speed[] = {
332 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
333};
334static const char *power[] = {
335 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
336 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
337};
338static const char port[] = { '.', '-', 'p', 'c', };
339
340static char _p(u32 *s, int shift)
341{
342 return port[*s >> shift & 3];
343}
344
Stefan Richter08ddb2f2008-04-11 00:51:15 +0200345static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100346{
347 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
348 return;
349
Stefan Richter161b96e2008-06-14 14:23:43 +0200350 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
351 self_id_count, generation, node_id);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100352
353 for (; self_id_count--; ++s)
354 if ((*s & 1 << 23) == 0)
Stefan Richter161b96e2008-06-14 14:23:43 +0200355 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
356 "%s gc=%d %s %s%s%s\n",
357 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
358 speed[*s >> 14 & 3], *s >> 16 & 63,
359 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
360 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100361 else
Stefan Richter161b96e2008-06-14 14:23:43 +0200362 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
363 *s, *s >> 24 & 63,
364 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
365 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100366}
367
368static const char *evts[] = {
369 [0x00] = "evt_no_status", [0x01] = "-reserved-",
370 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
371 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
372 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
373 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
374 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
375 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
376 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
377 [0x10] = "-reserved-", [0x11] = "ack_complete",
378 [0x12] = "ack_pending ", [0x13] = "-reserved-",
379 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
380 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
381 [0x18] = "-reserved-", [0x19] = "-reserved-",
382 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
383 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
384 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
385 [0x20] = "pending/cancelled",
386};
387static const char *tcodes[] = {
388 [0x0] = "QW req", [0x1] = "BW req",
389 [0x2] = "W resp", [0x3] = "-reserved-",
390 [0x4] = "QR req", [0x5] = "BR req",
391 [0x6] = "QR resp", [0x7] = "BR resp",
392 [0x8] = "cycle start", [0x9] = "Lk req",
393 [0xa] = "async stream packet", [0xb] = "Lk resp",
394 [0xc] = "-reserved-", [0xd] = "-reserved-",
395 [0xe] = "link internal", [0xf] = "-reserved-",
396};
397static const char *phys[] = {
398 [0x0] = "phy config packet", [0x1] = "link-on packet",
399 [0x2] = "self-id packet", [0x3] = "-reserved-",
400};
401
402static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
403{
404 int tcode = header[0] >> 4 & 0xf;
405 char specific[12];
406
407 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
408 return;
409
410 if (unlikely(evt >= ARRAY_SIZE(evts)))
411 evt = 0x1f;
412
Stefan Richter08ddb2f2008-04-11 00:51:15 +0200413 if (evt == OHCI1394_evt_bus_reset) {
Stefan Richter161b96e2008-06-14 14:23:43 +0200414 fw_notify("A%c evt_bus_reset, generation %d\n",
415 dir, (header[2] >> 16) & 0xff);
Stefan Richter08ddb2f2008-04-11 00:51:15 +0200416 return;
417 }
418
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100419 if (header[0] == ~header[1]) {
Stefan Richter161b96e2008-06-14 14:23:43 +0200420 fw_notify("A%c %s, %s, %08x\n",
421 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100422 return;
423 }
424
425 switch (tcode) {
426 case 0x0: case 0x6: case 0x8:
427 snprintf(specific, sizeof(specific), " = %08x",
428 be32_to_cpu((__force __be32)header[3]));
429 break;
430 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
431 snprintf(specific, sizeof(specific), " %x,%x",
432 header[3] >> 16, header[3] & 0xffff);
433 break;
434 default:
435 specific[0] = '\0';
436 }
437
438 switch (tcode) {
439 case 0xe: case 0xa:
Stefan Richter161b96e2008-06-14 14:23:43 +0200440 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100441 break;
442 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
Stefan Richter161b96e2008-06-14 14:23:43 +0200443 fw_notify("A%c spd %x tl %02x, "
444 "%04x -> %04x, %s, "
445 "%s, %04x%08x%s\n",
446 dir, speed, header[0] >> 10 & 0x3f,
447 header[1] >> 16, header[0] >> 16, evts[evt],
448 tcodes[tcode], header[1] & 0xffff, header[2], specific);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100449 break;
450 default:
Stefan Richter161b96e2008-06-14 14:23:43 +0200451 fw_notify("A%c spd %x tl %02x, "
452 "%04x -> %04x, %s, "
453 "%s%s\n",
454 dir, speed, header[0] >> 10 & 0x3f,
455 header[1] >> 16, header[0] >> 16, evts[evt],
456 tcodes[tcode], specific);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100457 }
458}
459
460#else
461
Stefan Richter5da3dac2010-04-02 14:05:02 +0200462#define param_debug 0
463static inline void log_irqs(u32 evt) {}
464static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
465static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100466
467#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
468
Adrian Bunk95688e92007-01-22 19:17:37 +0100469static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
Kristian Høgsberged568912006-12-19 19:58:35 -0500470{
471 writel(data, ohci->registers + offset);
472}
473
Adrian Bunk95688e92007-01-22 19:17:37 +0100474static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
Kristian Høgsberged568912006-12-19 19:58:35 -0500475{
476 return readl(ohci->registers + offset);
477}
478
Adrian Bunk95688e92007-01-22 19:17:37 +0100479static inline void flush_writes(const struct fw_ohci *ohci)
Kristian Høgsberged568912006-12-19 19:58:35 -0500480{
481 /* Do a dummy read to flush writes. */
482 reg_read(ohci, OHCI1394_Version);
483}
484
Stefan Richter35d999b2010-04-10 16:04:56 +0200485static int read_phy_reg(struct fw_ohci *ohci, int addr)
Kristian Høgsberged568912006-12-19 19:58:35 -0500486{
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200487 u32 val;
Stefan Richter35d999b2010-04-10 16:04:56 +0200488 int i;
Kristian Høgsberged568912006-12-19 19:58:35 -0500489
490 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
Clemens Ladisch153e3972010-06-10 08:22:07 +0200491 for (i = 0; i < 3 + 100; i++) {
Stefan Richter35d999b2010-04-10 16:04:56 +0200492 val = reg_read(ohci, OHCI1394_PhyControl);
493 if (val & OHCI1394_PhyControl_ReadDone)
494 return OHCI1394_PhyControl_ReadData(val);
495
Clemens Ladisch153e3972010-06-10 08:22:07 +0200496 /*
497 * Try a few times without waiting. Sleeping is necessary
498 * only when the link/PHY interface is busy.
499 */
500 if (i >= 3)
501 msleep(1);
Kristian Høgsberged568912006-12-19 19:58:35 -0500502 }
Stefan Richter35d999b2010-04-10 16:04:56 +0200503 fw_error("failed to read phy reg\n");
Kristian Høgsberged568912006-12-19 19:58:35 -0500504
Stefan Richter35d999b2010-04-10 16:04:56 +0200505 return -EBUSY;
506}
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200507
Stefan Richter35d999b2010-04-10 16:04:56 +0200508static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
509{
510 int i;
511
512 reg_write(ohci, OHCI1394_PhyControl,
513 OHCI1394_PhyControl_Write(addr, val));
Clemens Ladisch153e3972010-06-10 08:22:07 +0200514 for (i = 0; i < 3 + 100; i++) {
Stefan Richter35d999b2010-04-10 16:04:56 +0200515 val = reg_read(ohci, OHCI1394_PhyControl);
516 if (!(val & OHCI1394_PhyControl_WritePending))
517 return 0;
518
Clemens Ladisch153e3972010-06-10 08:22:07 +0200519 if (i >= 3)
520 msleep(1);
Stefan Richter35d999b2010-04-10 16:04:56 +0200521 }
522 fw_error("failed to write phy reg\n");
523
524 return -EBUSY;
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200525}
526
Stefan Richter02d37be2010-07-08 16:09:06 +0200527static int update_phy_reg(struct fw_ohci *ohci, int addr,
528 int clear_bits, int set_bits)
Kristian Høgsberged568912006-12-19 19:58:35 -0500529{
Stefan Richter02d37be2010-07-08 16:09:06 +0200530 int ret = read_phy_reg(ohci, addr);
Stefan Richter35d999b2010-04-10 16:04:56 +0200531 if (ret < 0)
532 return ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500533
Clemens Ladische7014da2010-04-01 16:40:18 +0200534 /*
535 * The interrupt status bits are cleared by writing a one bit.
536 * Avoid clearing them unless explicitly requested in set_bits.
537 */
538 if (addr == 5)
539 clear_bits |= PHY_INT_STATUS_BITS;
Kristian Høgsberged568912006-12-19 19:58:35 -0500540
Stefan Richter35d999b2010-04-10 16:04:56 +0200541 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
Kristian Høgsberged568912006-12-19 19:58:35 -0500542}
543
Stefan Richter35d999b2010-04-10 16:04:56 +0200544static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200545{
Stefan Richter35d999b2010-04-10 16:04:56 +0200546 int ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200547
Stefan Richter02d37be2010-07-08 16:09:06 +0200548 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
Stefan Richter35d999b2010-04-10 16:04:56 +0200549 if (ret < 0)
550 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200551
Stefan Richter35d999b2010-04-10 16:04:56 +0200552 return read_phy_reg(ohci, addr);
Kristian Høgsberged568912006-12-19 19:58:35 -0500553}
554
Stefan Richter02d37be2010-07-08 16:09:06 +0200555static int ohci_read_phy_reg(struct fw_card *card, int addr)
556{
557 struct fw_ohci *ohci = fw_ohci(card);
558 int ret;
559
560 mutex_lock(&ohci->phy_reg_mutex);
561 ret = read_phy_reg(ohci, addr);
562 mutex_unlock(&ohci->phy_reg_mutex);
563
564 return ret;
565}
566
Kristian Høgsberged568912006-12-19 19:58:35 -0500567static int ohci_update_phy_reg(struct fw_card *card, int addr,
568 int clear_bits, int set_bits)
569{
570 struct fw_ohci *ohci = fw_ohci(card);
Stefan Richter02d37be2010-07-08 16:09:06 +0200571 int ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500572
Stefan Richter02d37be2010-07-08 16:09:06 +0200573 mutex_lock(&ohci->phy_reg_mutex);
574 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
575 mutex_unlock(&ohci->phy_reg_mutex);
Kristian Høgsberged568912006-12-19 19:58:35 -0500576
Stefan Richter02d37be2010-07-08 16:09:06 +0200577 return ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500578}
579
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500580static int ar_context_add_page(struct ar_context *ctx)
Kristian Høgsberged568912006-12-19 19:58:35 -0500581{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500582 struct device *dev = ctx->ohci->card.device;
583 struct ar_buffer *ab;
Stefan Richterf5101d582008-03-14 00:27:49 +0100584 dma_addr_t uninitialized_var(ab_bus);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500585 size_t offset;
586
Jarod Wilsonbde17092008-03-12 17:43:26 -0400587 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500588 if (ab == NULL)
589 return -ENOMEM;
590
Jay Fenlasona55709b2008-10-22 15:59:42 -0400591 ab->next = NULL;
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400592 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400593 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
594 DESCRIPTOR_STATUS |
595 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500596 offset = offsetof(struct ar_buffer, data);
597 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
598 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
599 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
600 ab->descriptor.branch_address = 0;
601
Stefan Richter071595e2010-07-27 13:20:33 +0200602 wmb(); /* finish init of new descriptors before branch_address update */
Kristian Høgsbergec839e42007-05-22 18:55:48 -0400603 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500604 ctx->last_buffer->next = ab;
605 ctx->last_buffer = ab;
606
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400607 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberged568912006-12-19 19:58:35 -0500608 flush_writes(ctx->ohci);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500609
610 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -0500611}
612
Jay Fenlasona55709b2008-10-22 15:59:42 -0400613static void ar_context_release(struct ar_context *ctx)
614{
615 struct ar_buffer *ab, *ab_next;
616 size_t offset;
617 dma_addr_t ab_bus;
618
619 for (ab = ctx->current_buffer; ab; ab = ab_next) {
620 ab_next = ab->next;
621 offset = offsetof(struct ar_buffer, data);
622 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
623 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
624 ab, ab_bus);
625 }
626}
627
Stefan Richter11bf20a2008-03-01 02:47:15 +0100628#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
629#define cond_le32_to_cpu(v) \
Stefan Richter4a635592010-02-21 17:58:01 +0100630 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
Stefan Richter11bf20a2008-03-01 02:47:15 +0100631#else
632#define cond_le32_to_cpu(v) le32_to_cpu(v)
633#endif
634
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500635static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
Kristian Høgsberged568912006-12-19 19:58:35 -0500636{
Kristian Høgsberged568912006-12-19 19:58:35 -0500637 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500638 struct fw_packet p;
639 u32 status, length, tcode;
Stefan Richter43286562008-03-11 21:22:26 +0100640 int evt;
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500641
Stefan Richter11bf20a2008-03-01 02:47:15 +0100642 p.header[0] = cond_le32_to_cpu(buffer[0]);
643 p.header[1] = cond_le32_to_cpu(buffer[1]);
644 p.header[2] = cond_le32_to_cpu(buffer[2]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500645
646 tcode = (p.header[0] >> 4) & 0x0f;
647 switch (tcode) {
648 case TCODE_WRITE_QUADLET_REQUEST:
649 case TCODE_READ_QUADLET_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500650 p.header[3] = (__force __u32) buffer[3];
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500651 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500652 p.payload_length = 0;
653 break;
654
655 case TCODE_READ_BLOCK_REQUEST :
Stefan Richter11bf20a2008-03-01 02:47:15 +0100656 p.header[3] = cond_le32_to_cpu(buffer[3]);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500657 p.header_length = 16;
658 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500659 break;
660
661 case TCODE_WRITE_BLOCK_REQUEST:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500662 case TCODE_READ_BLOCK_RESPONSE:
663 case TCODE_LOCK_REQUEST:
664 case TCODE_LOCK_RESPONSE:
Stefan Richter11bf20a2008-03-01 02:47:15 +0100665 p.header[3] = cond_le32_to_cpu(buffer[3]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500666 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500667 p.payload_length = p.header[3] >> 16;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500668 break;
669
670 case TCODE_WRITE_RESPONSE:
671 case TCODE_READ_QUADLET_REQUEST:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500672 case OHCI_TCODE_PHY_PACKET:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500673 p.header_length = 12;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500674 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500675 break;
Stefan Richterccff9622008-05-31 19:36:06 +0200676
677 default:
678 /* FIXME: Stop context, discard everything, and restart? */
679 p.header_length = 0;
680 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500681 }
682
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500683 p.payload = (void *) buffer + p.header_length;
684
685 /* FIXME: What to do about evt_* errors? */
686 length = (p.header_length + p.payload_length + 3) / 4;
Stefan Richter11bf20a2008-03-01 02:47:15 +0100687 status = cond_le32_to_cpu(buffer[length]);
Stefan Richter43286562008-03-11 21:22:26 +0100688 evt = (status >> 16) & 0x1f;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500689
Stefan Richter43286562008-03-11 21:22:26 +0100690 p.ack = evt - 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500691 p.speed = (status >> 21) & 0x7;
692 p.timestamp = status & 0xffff;
693 p.generation = ohci->request_generation;
Kristian Høgsberged568912006-12-19 19:58:35 -0500694
Stefan Richter43286562008-03-11 21:22:26 +0100695 log_ar_at_event('R', p.speed, p.header, evt);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100696
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400697 /*
Stefan Richtera4dc0902010-08-28 14:21:26 +0200698 * Several controllers, notably from NEC and VIA, forget to
699 * write ack_complete status at PHY packet reception.
700 */
701 if (evt == OHCI1394_evt_no_status &&
702 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
703 p.ack = ACK_COMPLETE;
704
705 /*
706 * The OHCI bus reset handler synthesizes a PHY packet with
Kristian Høgsberged568912006-12-19 19:58:35 -0500707 * the new generation number when a bus reset happens (see
708 * section 8.4.2.3). This helps us determine when a request
709 * was received and make sure we send the response in the same
710 * generation. We only need this for requests; for responses
711 * we use the unique tlabel for finding the matching
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400712 * request.
Stefan Richterd34316a2008-04-12 22:31:25 +0200713 *
714 * Alas some chips sometimes emit bus reset packets with a
715 * wrong generation. We set the correct generation for these
716 * at a slightly incorrect time (in bus_reset_tasklet).
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400717 */
Stefan Richterd34316a2008-04-12 22:31:25 +0200718 if (evt == OHCI1394_evt_bus_reset) {
Stefan Richter4a635592010-02-21 17:58:01 +0100719 if (!(ohci->quirks & QUIRK_RESET_PACKET))
Stefan Richterd34316a2008-04-12 22:31:25 +0200720 ohci->request_generation = (p.header[2] >> 16) & 0xff;
721 } else if (ctx == &ohci->ar_request_ctx) {
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500722 fw_core_handle_request(&ohci->card, &p);
Stefan Richterd34316a2008-04-12 22:31:25 +0200723 } else {
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500724 fw_core_handle_response(&ohci->card, &p);
Stefan Richterd34316a2008-04-12 22:31:25 +0200725 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500726
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500727 return buffer + length + 1;
728}
Kristian Høgsberged568912006-12-19 19:58:35 -0500729
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500730static void ar_context_tasklet(unsigned long data)
731{
732 struct ar_context *ctx = (struct ar_context *)data;
733 struct fw_ohci *ohci = ctx->ohci;
734 struct ar_buffer *ab;
735 struct descriptor *d;
736 void *buffer, *end;
Kristian Høgsberged568912006-12-19 19:58:35 -0500737
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500738 ab = ctx->current_buffer;
739 d = &ab->descriptor;
Kristian Høgsberged568912006-12-19 19:58:35 -0500740
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500741 if (d->res_count == 0) {
742 size_t size, rest, offset;
Jarod Wilson6b842362008-03-25 16:47:16 -0400743 dma_addr_t start_bus;
744 void *start;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500745
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400746 /*
747 * This descriptor is finished and we may have a
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500748 * packet split across this and the next buffer. We
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400749 * reuse the page for reassembling the split packet.
750 */
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500751
752 offset = offsetof(struct ar_buffer, data);
Jarod Wilson6b842362008-03-25 16:47:16 -0400753 start = buffer = ab;
754 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500755
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500756 ab = ab->next;
757 d = &ab->descriptor;
758 size = buffer + PAGE_SIZE - ctx->pointer;
759 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
760 memmove(buffer, ctx->pointer, size);
761 memcpy(buffer + size, ab->data, rest);
762 ctx->current_buffer = ab;
763 ctx->pointer = (void *) ab->data + rest;
764 end = buffer + size + rest;
765
766 while (buffer < end)
767 buffer = handle_ar_packet(ctx, buffer);
768
Jarod Wilsonbde17092008-03-12 17:43:26 -0400769 dma_free_coherent(ohci->card.device, PAGE_SIZE,
Jarod Wilson6b842362008-03-25 16:47:16 -0400770 start, start_bus);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500771 ar_context_add_page(ctx);
772 } else {
773 buffer = ctx->pointer;
774 ctx->pointer = end =
775 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
776
777 while (buffer < end)
778 buffer = handle_ar_packet(ctx, buffer);
779 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500780}
781
Stefan Richter53dca512008-12-14 21:47:04 +0100782static int ar_context_init(struct ar_context *ctx,
783 struct fw_ohci *ohci, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500784{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500785 struct ar_buffer ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500786
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500787 ctx->regs = regs;
788 ctx->ohci = ohci;
789 ctx->last_buffer = &ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500790 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
791
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500792 ar_context_add_page(ctx);
793 ar_context_add_page(ctx);
794 ctx->current_buffer = ab.next;
795 ctx->pointer = ctx->current_buffer->data;
796
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400797 return 0;
798}
799
800static void ar_context_run(struct ar_context *ctx)
801{
802 struct ar_buffer *ab = ctx->current_buffer;
803 dma_addr_t ab_bus;
804 size_t offset;
805
806 offset = offsetof(struct ar_buffer, data);
Stefan Richter0a9972b2007-06-23 20:28:17 +0200807 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400808
809 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400810 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500811 flush_writes(ctx->ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500812}
Stefan Richter373b2ed2007-03-04 14:45:18 +0100813
Stefan Richter53dca512008-12-14 21:47:04 +0100814static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500815{
816 int b, key;
817
818 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
819 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
820
821 /* figure out which descriptor the branch address goes in */
822 if (z == 2 && (b == 3 || key == 2))
823 return d;
824 else
825 return d + z - 1;
826}
827
Kristian Høgsberg30200732007-02-16 17:34:39 -0500828static void context_tasklet(unsigned long data)
829{
830 struct context *ctx = (struct context *) data;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500831 struct descriptor *d, *last;
832 u32 address;
833 int z;
David Moorefe5ca632008-01-06 17:21:41 -0500834 struct descriptor_buffer *desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500835
David Moorefe5ca632008-01-06 17:21:41 -0500836 desc = list_entry(ctx->buffer_list.next,
837 struct descriptor_buffer, list);
838 last = ctx->last;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500839 while (last->branch_address != 0) {
David Moorefe5ca632008-01-06 17:21:41 -0500840 struct descriptor_buffer *old_desc = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500841 address = le32_to_cpu(last->branch_address);
842 z = address & 0xf;
David Moorefe5ca632008-01-06 17:21:41 -0500843 address &= ~0xf;
844
845 /* If the branch address points to a buffer outside of the
846 * current buffer, advance to the next buffer. */
847 if (address < desc->buffer_bus ||
848 address >= desc->buffer_bus + desc->used)
849 desc = list_entry(desc->list.next,
850 struct descriptor_buffer, list);
851 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500852 last = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500853
854 if (!ctx->callback(ctx, d, last))
855 break;
856
David Moorefe5ca632008-01-06 17:21:41 -0500857 if (old_desc != desc) {
858 /* If we've advanced to the next buffer, move the
859 * previous buffer to the free list. */
860 unsigned long flags;
861 old_desc->used = 0;
862 spin_lock_irqsave(&ctx->ohci->lock, flags);
863 list_move_tail(&old_desc->list, &ctx->buffer_list);
864 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
865 }
866 ctx->last = last;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500867 }
868}
869
David Moorefe5ca632008-01-06 17:21:41 -0500870/*
871 * Allocate a new buffer and add it to the list of free buffers for this
872 * context. Must be called with ohci->lock held.
873 */
Stefan Richter53dca512008-12-14 21:47:04 +0100874static int context_add_buffer(struct context *ctx)
David Moorefe5ca632008-01-06 17:21:41 -0500875{
876 struct descriptor_buffer *desc;
Stefan Richterf5101d582008-03-14 00:27:49 +0100877 dma_addr_t uninitialized_var(bus_addr);
David Moorefe5ca632008-01-06 17:21:41 -0500878 int offset;
879
880 /*
881 * 16MB of descriptors should be far more than enough for any DMA
882 * program. This will catch run-away userspace or DoS attacks.
883 */
884 if (ctx->total_allocation >= 16*1024*1024)
885 return -ENOMEM;
886
887 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
888 &bus_addr, GFP_ATOMIC);
889 if (!desc)
890 return -ENOMEM;
891
892 offset = (void *)&desc->buffer - (void *)desc;
893 desc->buffer_size = PAGE_SIZE - offset;
894 desc->buffer_bus = bus_addr + offset;
895 desc->used = 0;
896
897 list_add_tail(&desc->list, &ctx->buffer_list);
898 ctx->total_allocation += PAGE_SIZE;
899
900 return 0;
901}
902
Stefan Richter53dca512008-12-14 21:47:04 +0100903static int context_init(struct context *ctx, struct fw_ohci *ohci,
904 u32 regs, descriptor_callback_t callback)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500905{
906 ctx->ohci = ohci;
907 ctx->regs = regs;
David Moorefe5ca632008-01-06 17:21:41 -0500908 ctx->total_allocation = 0;
909
910 INIT_LIST_HEAD(&ctx->buffer_list);
911 if (context_add_buffer(ctx) < 0)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500912 return -ENOMEM;
913
David Moorefe5ca632008-01-06 17:21:41 -0500914 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
915 struct descriptor_buffer, list);
916
Kristian Høgsberg30200732007-02-16 17:34:39 -0500917 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
918 ctx->callback = callback;
919
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400920 /*
921 * We put a dummy descriptor in the buffer that has a NULL
Kristian Høgsberg30200732007-02-16 17:34:39 -0500922 * branch address and looks like it's been sent. That way we
David Moorefe5ca632008-01-06 17:21:41 -0500923 * have a descriptor to append DMA programs to.
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400924 */
David Moorefe5ca632008-01-06 17:21:41 -0500925 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
926 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
927 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
928 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
929 ctx->last = ctx->buffer_tail->buffer;
930 ctx->prev = ctx->buffer_tail->buffer;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500931
932 return 0;
933}
934
Stefan Richter53dca512008-12-14 21:47:04 +0100935static void context_release(struct context *ctx)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500936{
937 struct fw_card *card = &ctx->ohci->card;
David Moorefe5ca632008-01-06 17:21:41 -0500938 struct descriptor_buffer *desc, *tmp;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500939
David Moorefe5ca632008-01-06 17:21:41 -0500940 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
941 dma_free_coherent(card->device, PAGE_SIZE, desc,
942 desc->buffer_bus -
943 ((void *)&desc->buffer - (void *)desc));
Kristian Høgsberg30200732007-02-16 17:34:39 -0500944}
945
David Moorefe5ca632008-01-06 17:21:41 -0500946/* Must be called with ohci->lock held */
Stefan Richter53dca512008-12-14 21:47:04 +0100947static struct descriptor *context_get_descriptors(struct context *ctx,
948 int z, dma_addr_t *d_bus)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500949{
David Moorefe5ca632008-01-06 17:21:41 -0500950 struct descriptor *d = NULL;
951 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500952
David Moorefe5ca632008-01-06 17:21:41 -0500953 if (z * sizeof(*d) > desc->buffer_size)
954 return NULL;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500955
David Moorefe5ca632008-01-06 17:21:41 -0500956 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
957 /* No room for the descriptor in this buffer, so advance to the
958 * next one. */
959
960 if (desc->list.next == &ctx->buffer_list) {
961 /* If there is no free buffer next in the list,
962 * allocate one. */
963 if (context_add_buffer(ctx) < 0)
964 return NULL;
965 }
966 desc = list_entry(desc->list.next,
967 struct descriptor_buffer, list);
968 ctx->buffer_tail = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500969 }
970
David Moorefe5ca632008-01-06 17:21:41 -0500971 d = desc->buffer + desc->used / sizeof(*d);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400972 memset(d, 0, z * sizeof(*d));
David Moorefe5ca632008-01-06 17:21:41 -0500973 *d_bus = desc->buffer_bus + desc->used;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500974
975 return d;
976}
977
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500978static void context_run(struct context *ctx, u32 extra)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500979{
980 struct fw_ohci *ohci = ctx->ohci;
981
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400982 reg_write(ohci, COMMAND_PTR(ctx->regs),
David Moorefe5ca632008-01-06 17:21:41 -0500983 le32_to_cpu(ctx->last->branch_address));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400984 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
985 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500986 flush_writes(ohci);
987}
988
989static void context_append(struct context *ctx,
990 struct descriptor *d, int z, int extra)
991{
992 dma_addr_t d_bus;
David Moorefe5ca632008-01-06 17:21:41 -0500993 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500994
David Moorefe5ca632008-01-06 17:21:41 -0500995 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500996
David Moorefe5ca632008-01-06 17:21:41 -0500997 desc->used += (z + extra) * sizeof(*d);
Stefan Richter071595e2010-07-27 13:20:33 +0200998
999 wmb(); /* finish init of new descriptors before branch_address update */
David Moorefe5ca632008-01-06 17:21:41 -05001000 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1001 ctx->prev = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001002
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001003 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001004 flush_writes(ctx->ohci);
1005}
1006
1007static void context_stop(struct context *ctx)
1008{
1009 u32 reg;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001010 int i;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001011
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001012 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001013 flush_writes(ctx->ohci);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001014
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001015 for (i = 0; i < 10; i++) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001016 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001017 if ((reg & CONTEXT_ACTIVE) == 0)
Stefan Richterb0068542009-01-05 20:43:23 +01001018 return;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001019
Stefan Richterb980f5a2007-07-12 22:25:14 +02001020 mdelay(1);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001021 }
Stefan Richterb0068542009-01-05 20:43:23 +01001022 fw_error("Error: DMA context still active (0x%08x)\n", reg);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001023}
Kristian Høgsberged568912006-12-19 19:58:35 -05001024
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001025struct driver_data {
Kristian Høgsberged568912006-12-19 19:58:35 -05001026 struct fw_packet *packet;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001027};
1028
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001029/*
1030 * This function apppends a packet to the DMA queue for transmission.
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001031 * Must always be called with the ochi->lock held to ensure proper
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001032 * generation handling and locking around packet queue manipulation.
1033 */
Stefan Richter53dca512008-12-14 21:47:04 +01001034static int at_context_queue_packet(struct context *ctx,
1035 struct fw_packet *packet)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001036{
Kristian Høgsberged568912006-12-19 19:58:35 -05001037 struct fw_ohci *ohci = ctx->ohci;
Stefan Richter4b6d51e2007-10-21 11:20:07 +02001038 dma_addr_t d_bus, uninitialized_var(payload_bus);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001039 struct driver_data *driver_data;
1040 struct descriptor *d, *last;
1041 __le32 *header;
Kristian Høgsberged568912006-12-19 19:58:35 -05001042 int z, tcode;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001043 u32 reg;
Kristian Høgsberged568912006-12-19 19:58:35 -05001044
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001045 d = context_get_descriptors(ctx, 4, &d_bus);
1046 if (d == NULL) {
1047 packet->ack = RCODE_SEND_ERROR;
1048 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001049 }
1050
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001051 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001052 d[0].res_count = cpu_to_le16(packet->timestamp);
1053
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001054 /*
1055 * The DMA format for asyncronous link packets is different
Kristian Høgsberged568912006-12-19 19:58:35 -05001056 * from the IEEE1394 layout, so shift the fields around
1057 * accordingly. If header_length is 8, it's a PHY packet, to
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001058 * which we need to prepend an extra quadlet.
1059 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001060
1061 header = (__le32 *) &d[1];
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001062 switch (packet->header_length) {
1063 case 16:
1064 case 12:
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001065 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1066 (packet->speed << 16));
1067 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1068 (packet->header[0] & 0xffff0000));
1069 header[2] = cpu_to_le32(packet->header[2]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001070
1071 tcode = (packet->header[0] >> 4) & 0x0f;
1072 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001073 header[3] = cpu_to_le32(packet->header[3]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001074 else
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001075 header[3] = (__force __le32) packet->header[3];
1076
1077 d[0].req_count = cpu_to_le16(packet->header_length);
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001078 break;
1079
1080 case 8:
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001081 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1082 (packet->speed << 16));
1083 header[1] = cpu_to_le32(packet->header[0]);
1084 header[2] = cpu_to_le32(packet->header[1]);
1085 d[0].req_count = cpu_to_le16(12);
Stefan Richtercc550212010-07-18 13:00:50 +02001086
1087 if (is_ping_packet(packet->header))
1088 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001089 break;
1090
1091 case 4:
1092 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1093 (packet->speed << 16));
1094 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1095 d[0].req_count = cpu_to_le16(8);
1096 break;
1097
1098 default:
1099 /* BUG(); */
1100 packet->ack = RCODE_SEND_ERROR;
1101 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001102 }
1103
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001104 driver_data = (struct driver_data *) &d[3];
1105 driver_data->packet = packet;
Kristian Høgsberg20d11672007-03-26 19:18:19 -04001106 packet->driver_data = driver_data;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001107
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001108 if (packet->payload_length > 0) {
1109 payload_bus =
1110 dma_map_single(ohci->card.device, packet->payload,
1111 packet->payload_length, DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -07001112 if (dma_mapping_error(ohci->card.device, payload_bus)) {
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001113 packet->ack = RCODE_SEND_ERROR;
1114 return -1;
1115 }
Stefan Richter19593ff2009-10-14 20:40:10 +02001116 packet->payload_bus = payload_bus;
1117 packet->payload_mapped = true;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001118
1119 d[2].req_count = cpu_to_le16(packet->payload_length);
1120 d[2].data_address = cpu_to_le32(payload_bus);
1121 last = &d[2];
1122 z = 3;
1123 } else {
1124 last = &d[0];
1125 z = 2;
1126 }
1127
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001128 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1129 DESCRIPTOR_IRQ_ALWAYS |
1130 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001131
Jarod Wilson76f73ca2008-04-07 22:32:33 +02001132 /*
1133 * If the controller and packet generations don't match, we need to
1134 * bail out and try again. If IntEvent.busReset is set, the AT context
1135 * is halted, so appending to the context and trying to run it is
1136 * futile. Most controllers do the right thing and just flush the AT
1137 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1138 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1139 * up stalling out. So we just bail out in software and try again
1140 * later, and everyone is happy.
1141 * FIXME: Document how the locking works.
1142 */
1143 if (ohci->generation != packet->generation ||
1144 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
Stefan Richter19593ff2009-10-14 20:40:10 +02001145 if (packet->payload_mapped)
Stefan Richterab88ca42007-08-29 19:40:28 +02001146 dma_unmap_single(ohci->card.device, payload_bus,
1147 packet->payload_length, DMA_TO_DEVICE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001148 packet->ack = RCODE_GENERATION;
1149 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001150 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001151
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001152 context_append(ctx, d, z, 4 - z);
Kristian Høgsberged568912006-12-19 19:58:35 -05001153
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001154 /* If the context isn't already running, start it up. */
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001155 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsberg053b3082007-04-10 18:11:17 -04001156 if ((reg & CONTEXT_RUN) == 0)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001157 context_run(ctx, 0);
Kristian Høgsberged568912006-12-19 19:58:35 -05001158
1159 return 0;
1160}
1161
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001162static int handle_at_packet(struct context *context,
1163 struct descriptor *d,
1164 struct descriptor *last)
1165{
1166 struct driver_data *driver_data;
1167 struct fw_packet *packet;
1168 struct fw_ohci *ohci = context->ohci;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001169 int evt;
1170
1171 if (last->transfer_status == 0)
1172 /* This descriptor isn't done yet, stop iteration. */
1173 return 0;
1174
1175 driver_data = (struct driver_data *) &d[3];
1176 packet = driver_data->packet;
1177 if (packet == NULL)
1178 /* This packet was cancelled, just continue. */
1179 return 1;
1180
Stefan Richter19593ff2009-10-14 20:40:10 +02001181 if (packet->payload_mapped)
Stefan Richter1d1dc5e2008-12-10 00:20:38 +01001182 dma_unmap_single(ohci->card.device, packet->payload_bus,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001183 packet->payload_length, DMA_TO_DEVICE);
1184
1185 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1186 packet->timestamp = le16_to_cpu(last->res_count);
1187
Stefan Richterad3c0fe2008-03-20 22:04:36 +01001188 log_ar_at_event('T', packet->speed, packet->header, evt);
1189
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001190 switch (evt) {
1191 case OHCI1394_evt_timeout:
1192 /* Async response transmit timed out. */
1193 packet->ack = RCODE_CANCELLED;
1194 break;
1195
1196 case OHCI1394_evt_flushed:
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001197 /*
1198 * The packet was flushed should give same error as
1199 * when we try to use a stale generation count.
1200 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001201 packet->ack = RCODE_GENERATION;
1202 break;
1203
1204 case OHCI1394_evt_missing_ack:
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001205 /*
1206 * Using a valid (current) generation count, but the
1207 * node is not on the bus or not sending acks.
1208 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001209 packet->ack = RCODE_NO_ACK;
1210 break;
1211
1212 case ACK_COMPLETE + 0x10:
1213 case ACK_PENDING + 0x10:
1214 case ACK_BUSY_X + 0x10:
1215 case ACK_BUSY_A + 0x10:
1216 case ACK_BUSY_B + 0x10:
1217 case ACK_DATA_ERROR + 0x10:
1218 case ACK_TYPE_ERROR + 0x10:
1219 packet->ack = evt - 0x10;
1220 break;
1221
1222 default:
1223 packet->ack = RCODE_SEND_ERROR;
1224 break;
1225 }
1226
1227 packet->callback(packet, &ohci->card, packet->ack);
1228
1229 return 1;
1230}
1231
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001232#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1233#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1234#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1235#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1236#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001237
Stefan Richter53dca512008-12-14 21:47:04 +01001238static void handle_local_rom(struct fw_ohci *ohci,
1239 struct fw_packet *packet, u32 csr)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001240{
1241 struct fw_packet response;
1242 int tcode, length, i;
1243
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001244 tcode = HEADER_GET_TCODE(packet->header[0]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001245 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001246 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001247 else
1248 length = 4;
1249
1250 i = csr - CSR_CONFIG_ROM;
1251 if (i + length > CONFIG_ROM_SIZE) {
1252 fw_fill_response(&response, packet->header,
1253 RCODE_ADDRESS_ERROR, NULL, 0);
1254 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1255 fw_fill_response(&response, packet->header,
1256 RCODE_TYPE_ERROR, NULL, 0);
1257 } else {
1258 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1259 (void *) ohci->config_rom + i, length);
1260 }
1261
1262 fw_core_handle_response(&ohci->card, &response);
1263}
1264
Stefan Richter53dca512008-12-14 21:47:04 +01001265static void handle_local_lock(struct fw_ohci *ohci,
1266 struct fw_packet *packet, u32 csr)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001267{
1268 struct fw_packet response;
Clemens Ladische1393662010-04-12 10:35:44 +02001269 int tcode, length, ext_tcode, sel, try;
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001270 __be32 *payload, lock_old;
1271 u32 lock_arg, lock_data;
1272
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001273 tcode = HEADER_GET_TCODE(packet->header[0]);
1274 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001275 payload = packet->payload;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001276 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001277
1278 if (tcode == TCODE_LOCK_REQUEST &&
1279 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1280 lock_arg = be32_to_cpu(payload[0]);
1281 lock_data = be32_to_cpu(payload[1]);
1282 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1283 lock_arg = 0;
1284 lock_data = 0;
1285 } else {
1286 fw_fill_response(&response, packet->header,
1287 RCODE_TYPE_ERROR, NULL, 0);
1288 goto out;
1289 }
1290
1291 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1292 reg_write(ohci, OHCI1394_CSRData, lock_data);
1293 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1294 reg_write(ohci, OHCI1394_CSRControl, sel);
1295
Clemens Ladische1393662010-04-12 10:35:44 +02001296 for (try = 0; try < 20; try++)
1297 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1298 lock_old = cpu_to_be32(reg_read(ohci,
1299 OHCI1394_CSRData));
1300 fw_fill_response(&response, packet->header,
1301 RCODE_COMPLETE,
1302 &lock_old, sizeof(lock_old));
1303 goto out;
1304 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001305
Clemens Ladische1393662010-04-12 10:35:44 +02001306 fw_error("swap not done (CSR lock timeout)\n");
1307 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1308
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001309 out:
1310 fw_core_handle_response(&ohci->card, &response);
1311}
1312
Stefan Richter53dca512008-12-14 21:47:04 +01001313static void handle_local_request(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001314{
Clemens Ladisch26082032010-04-12 10:35:30 +02001315 u64 offset, csr;
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001316
Kristian Høgsberg473d28c2007-03-07 12:12:55 -05001317 if (ctx == &ctx->ohci->at_request_ctx) {
1318 packet->ack = ACK_PENDING;
1319 packet->callback(packet, &ctx->ohci->card, packet->ack);
1320 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001321
1322 offset =
1323 ((unsigned long long)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001324 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001325 packet->header[2];
1326 csr = offset - CSR_REGISTER_BASE;
1327
1328 /* Handle config rom reads. */
1329 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1330 handle_local_rom(ctx->ohci, packet, csr);
1331 else switch (csr) {
1332 case CSR_BUS_MANAGER_ID:
1333 case CSR_BANDWIDTH_AVAILABLE:
1334 case CSR_CHANNELS_AVAILABLE_HI:
1335 case CSR_CHANNELS_AVAILABLE_LO:
1336 handle_local_lock(ctx->ohci, packet, csr);
1337 break;
1338 default:
1339 if (ctx == &ctx->ohci->at_request_ctx)
1340 fw_core_handle_request(&ctx->ohci->card, packet);
1341 else
1342 fw_core_handle_response(&ctx->ohci->card, packet);
1343 break;
1344 }
Kristian Høgsberg473d28c2007-03-07 12:12:55 -05001345
1346 if (ctx == &ctx->ohci->at_response_ctx) {
1347 packet->ack = ACK_COMPLETE;
1348 packet->callback(packet, &ctx->ohci->card, packet->ack);
1349 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001350}
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001351
Stefan Richter53dca512008-12-14 21:47:04 +01001352static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberged568912006-12-19 19:58:35 -05001353{
Kristian Høgsberged568912006-12-19 19:58:35 -05001354 unsigned long flags;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001355 int ret;
Kristian Høgsberged568912006-12-19 19:58:35 -05001356
1357 spin_lock_irqsave(&ctx->ohci->lock, flags);
1358
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001359 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001360 ctx->ohci->generation == packet->generation) {
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001361 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1362 handle_local_request(ctx, packet);
1363 return;
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001364 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001365
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001366 ret = at_context_queue_packet(ctx, packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001367 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1368
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001369 if (ret < 0)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001370 packet->callback(packet, &ctx->ohci->card, packet->ack);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001371
Kristian Høgsberged568912006-12-19 19:58:35 -05001372}
1373
Clemens Ladischa48777e2010-06-10 08:33:07 +02001374static u32 cycle_timer_ticks(u32 cycle_timer)
1375{
1376 u32 ticks;
1377
1378 ticks = cycle_timer & 0xfff;
1379 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1380 ticks += (3072 * 8000) * (cycle_timer >> 25);
1381
1382 return ticks;
1383}
1384
1385/*
1386 * Some controllers exhibit one or more of the following bugs when updating the
1387 * iso cycle timer register:
1388 * - When the lowest six bits are wrapping around to zero, a read that happens
1389 * at the same time will return garbage in the lowest ten bits.
1390 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1391 * not incremented for about 60 ns.
1392 * - Occasionally, the entire register reads zero.
1393 *
1394 * To catch these, we read the register three times and ensure that the
1395 * difference between each two consecutive reads is approximately the same, i.e.
1396 * less than twice the other. Furthermore, any negative difference indicates an
1397 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1398 * execute, so we have enough precision to compute the ratio of the differences.)
1399 */
1400static u32 get_cycle_time(struct fw_ohci *ohci)
1401{
1402 u32 c0, c1, c2;
1403 u32 t0, t1, t2;
1404 s32 diff01, diff12;
1405 int i;
1406
1407 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1408
1409 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1410 i = 0;
1411 c1 = c2;
1412 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1413 do {
1414 c0 = c1;
1415 c1 = c2;
1416 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1417 t0 = cycle_timer_ticks(c0);
1418 t1 = cycle_timer_ticks(c1);
1419 t2 = cycle_timer_ticks(c2);
1420 diff01 = t1 - t0;
1421 diff12 = t2 - t1;
1422 } while ((diff01 <= 0 || diff12 <= 0 ||
1423 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1424 && i++ < 20);
1425 }
1426
1427 return c2;
1428}
1429
1430/*
1431 * This function has to be called at least every 64 seconds. The bus_time
1432 * field stores not only the upper 25 bits of the BUS_TIME register but also
1433 * the most significant bit of the cycle timer in bit 6 so that we can detect
1434 * changes in this bit.
1435 */
1436static u32 update_bus_time(struct fw_ohci *ohci)
1437{
1438 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1439
1440 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1441 ohci->bus_time += 0x40;
1442
1443 return ohci->bus_time | cycle_time_seconds;
1444}
1445
Kristian Høgsberged568912006-12-19 19:58:35 -05001446static void bus_reset_tasklet(unsigned long data)
1447{
1448 struct fw_ohci *ohci = (struct fw_ohci *)data;
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001449 int self_id_count, i, j, reg;
Kristian Høgsberged568912006-12-19 19:58:35 -05001450 int generation, new_generation;
1451 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001452 void *free_rom = NULL;
1453 dma_addr_t free_rom_bus = 0;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02001454 bool is_new_root;
Kristian Høgsberged568912006-12-19 19:58:35 -05001455
1456 reg = reg_read(ohci, OHCI1394_NodeID);
1457 if (!(reg & OHCI1394_NodeID_idValid)) {
Stefan Richter02ff8f82007-08-30 00:11:40 +02001458 fw_notify("node ID not valid, new bus reset in progress\n");
Kristian Høgsberged568912006-12-19 19:58:35 -05001459 return;
1460 }
Stefan Richter02ff8f82007-08-30 00:11:40 +02001461 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1462 fw_notify("malconfigured bus\n");
1463 return;
1464 }
1465 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1466 OHCI1394_NodeID_nodeNumber);
Kristian Høgsberged568912006-12-19 19:58:35 -05001467
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02001468 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1469 if (!(ohci->is_root && is_new_root))
1470 reg_write(ohci, OHCI1394_LinkControlSet,
1471 OHCI1394_LinkControl_cycleMaster);
1472 ohci->is_root = is_new_root;
1473
Stefan Richterc8a9a492008-03-19 21:40:32 +01001474 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1475 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1476 fw_notify("inconsistent self IDs\n");
1477 return;
1478 }
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001479 /*
1480 * The count in the SelfIDCount register is the number of
Kristian Høgsberged568912006-12-19 19:58:35 -05001481 * bytes in the self ID receive buffer. Since we also receive
1482 * the inverted quadlets and a header quadlet, we shift one
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001483 * bit extra to get the actual number of self IDs.
1484 */
Stefan Richter928ec5f2009-09-06 18:49:17 +02001485 self_id_count = (reg >> 3) & 0xff;
1486 if (self_id_count == 0 || self_id_count > 252) {
Stefan Richter016bf3d2008-03-19 22:05:02 +01001487 fw_notify("inconsistent self IDs\n");
1488 return;
1489 }
Stefan Richter11bf20a2008-03-01 02:47:15 +01001490 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
Stefan Richteree71c2f2007-08-25 14:08:19 +02001491 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001492
1493 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
Stefan Richterc8a9a492008-03-19 21:40:32 +01001494 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1495 fw_notify("inconsistent self IDs\n");
1496 return;
1497 }
Stefan Richter11bf20a2008-03-01 02:47:15 +01001498 ohci->self_id_buffer[j] =
1499 cond_le32_to_cpu(ohci->self_id_cpu[i]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001500 }
Stefan Richteree71c2f2007-08-25 14:08:19 +02001501 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001502
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001503 /*
1504 * Check the consistency of the self IDs we just read. The
Kristian Høgsberged568912006-12-19 19:58:35 -05001505 * problem we face is that a new bus reset can start while we
1506 * read out the self IDs from the DMA buffer. If this happens,
1507 * the DMA buffer will be overwritten with new self IDs and we
1508 * will read out inconsistent data. The OHCI specification
1509 * (section 11.2) recommends a technique similar to
1510 * linux/seqlock.h, where we remember the generation of the
1511 * self IDs in the buffer before reading them out and compare
1512 * it to the current generation after reading them out. If
1513 * the two generations match we know we have a consistent set
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001514 * of self IDs.
1515 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001516
1517 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1518 if (new_generation != generation) {
1519 fw_notify("recursive bus reset detected, "
1520 "discarding self ids\n");
1521 return;
1522 }
1523
1524 /* FIXME: Document how the locking works. */
1525 spin_lock_irqsave(&ohci->lock, flags);
1526
1527 ohci->generation = generation;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001528 context_stop(&ohci->at_request_ctx);
1529 context_stop(&ohci->at_response_ctx);
Kristian Høgsberged568912006-12-19 19:58:35 -05001530 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1531
Stefan Richter4a635592010-02-21 17:58:01 +01001532 if (ohci->quirks & QUIRK_RESET_PACKET)
Stefan Richterd34316a2008-04-12 22:31:25 +02001533 ohci->request_generation = generation;
1534
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001535 /*
1536 * This next bit is unrelated to the AT context stuff but we
Kristian Høgsberged568912006-12-19 19:58:35 -05001537 * have to do it under the spinlock also. If a new config rom
1538 * was set up before this reset, the old one is now no longer
1539 * in use and we can free it. Update the config rom pointers
1540 * to point to the current config rom and clear the
Thomas Weber88393162010-03-16 11:47:56 +01001541 * next_config_rom pointer so a new update can take place.
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001542 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001543
1544 if (ohci->next_config_rom != NULL) {
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001545 if (ohci->next_config_rom != ohci->config_rom) {
1546 free_rom = ohci->config_rom;
1547 free_rom_bus = ohci->config_rom_bus;
1548 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001549 ohci->config_rom = ohci->next_config_rom;
1550 ohci->config_rom_bus = ohci->next_config_rom_bus;
1551 ohci->next_config_rom = NULL;
1552
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001553 /*
1554 * Restore config_rom image and manually update
Kristian Høgsberged568912006-12-19 19:58:35 -05001555 * config_rom registers. Writing the header quadlet
1556 * will indicate that the config rom is ready, so we
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001557 * do that last.
1558 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001559 reg_write(ohci, OHCI1394_BusOptions,
1560 be32_to_cpu(ohci->config_rom[2]));
Stefan Richter8e859732009-10-08 00:41:59 +02001561 ohci->config_rom[0] = ohci->next_header;
1562 reg_write(ohci, OHCI1394_ConfigROMhdr,
1563 be32_to_cpu(ohci->next_header));
Kristian Høgsberged568912006-12-19 19:58:35 -05001564 }
1565
Stefan Richter080de8c2008-02-28 20:54:43 +01001566#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1567 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1568 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1569#endif
1570
Kristian Høgsberged568912006-12-19 19:58:35 -05001571 spin_unlock_irqrestore(&ohci->lock, flags);
1572
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001573 if (free_rom)
1574 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1575 free_rom, free_rom_bus);
1576
Stefan Richter08ddb2f2008-04-11 00:51:15 +02001577 log_selfids(ohci->node_id, generation,
1578 self_id_count, ohci->self_id_buffer);
Stefan Richterad3c0fe2008-03-20 22:04:36 +01001579
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001580 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
Stefan Richterc8a94de2010-06-12 20:34:50 +02001581 self_id_count, ohci->self_id_buffer,
1582 ohci->csr_state_setclear_abdicate);
1583 ohci->csr_state_setclear_abdicate = false;
Kristian Høgsberged568912006-12-19 19:58:35 -05001584}
1585
1586static irqreturn_t irq_handler(int irq, void *data)
1587{
1588 struct fw_ohci *ohci = data;
Stefan Richter168cf9a2010-02-14 18:49:18 +01001589 u32 event, iso_event;
Kristian Høgsberged568912006-12-19 19:58:35 -05001590 int i;
1591
1592 event = reg_read(ohci, OHCI1394_IntEventClear);
1593
Stefan Richtera5159582007-06-09 19:31:14 +02001594 if (!event || !~event)
Kristian Høgsberged568912006-12-19 19:58:35 -05001595 return IRQ_NONE;
1596
Stefan Richtera007bb82008-04-07 22:33:35 +02001597 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1598 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
Stefan Richterad3c0fe2008-03-20 22:04:36 +01001599 log_irqs(event);
Kristian Høgsberged568912006-12-19 19:58:35 -05001600
1601 if (event & OHCI1394_selfIDComplete)
1602 tasklet_schedule(&ohci->bus_reset_tasklet);
1603
1604 if (event & OHCI1394_RQPkt)
1605 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1606
1607 if (event & OHCI1394_RSPkt)
1608 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1609
1610 if (event & OHCI1394_reqTxComplete)
1611 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1612
1613 if (event & OHCI1394_respTxComplete)
1614 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1615
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001616 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001617 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1618
1619 while (iso_event) {
1620 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001621 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001622 iso_event &= ~(1 << i);
1623 }
1624
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001625 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001626 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1627
1628 while (iso_event) {
1629 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001630 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001631 iso_event &= ~(1 << i);
1632 }
1633
Jarod Wilson75f78322008-04-03 17:18:23 -04001634 if (unlikely(event & OHCI1394_regAccessFail))
1635 fw_error("Register access failure - "
1636 "please notify linux1394-devel@lists.sf.net\n");
1637
Stefan Richtere524f6162007-08-20 21:58:30 +02001638 if (unlikely(event & OHCI1394_postedWriteErr))
1639 fw_error("PCI posted write error\n");
1640
Stefan Richterbb9f2202007-12-22 22:14:52 +01001641 if (unlikely(event & OHCI1394_cycleTooLong)) {
1642 if (printk_ratelimit())
1643 fw_notify("isochronous cycle too long\n");
1644 reg_write(ohci, OHCI1394_LinkControlSet,
1645 OHCI1394_LinkControl_cycleMaster);
1646 }
1647
Jay Fenlason5ed1f322009-11-17 12:29:17 -05001648 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1649 /*
1650 * We need to clear this event bit in order to make
1651 * cycleMatch isochronous I/O work. In theory we should
1652 * stop active cycleMatch iso contexts now and restart
1653 * them at least two cycles later. (FIXME?)
1654 */
1655 if (printk_ratelimit())
1656 fw_notify("isochronous cycle inconsistent\n");
1657 }
1658
Clemens Ladischa48777e2010-06-10 08:33:07 +02001659 if (event & OHCI1394_cycle64Seconds) {
1660 spin_lock(&ohci->lock);
1661 update_bus_time(ohci);
1662 spin_unlock(&ohci->lock);
1663 }
1664
Kristian Høgsberged568912006-12-19 19:58:35 -05001665 return IRQ_HANDLED;
1666}
1667
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001668static int software_reset(struct fw_ohci *ohci)
1669{
1670 int i;
1671
1672 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1673
1674 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1675 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1676 OHCI1394_HCControl_softReset) == 0)
1677 return 0;
1678 msleep(1);
1679 }
1680
1681 return -EBUSY;
1682}
1683
Stefan Richter8e859732009-10-08 00:41:59 +02001684static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1685{
1686 size_t size = length * 4;
1687
1688 memcpy(dest, src, size);
1689 if (size < CONFIG_ROM_SIZE)
1690 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1691}
1692
Clemens Ladisch925e7a62010-04-04 15:19:54 +02001693static int configure_1394a_enhancements(struct fw_ohci *ohci)
1694{
1695 bool enable_1394a;
Stefan Richter35d999b2010-04-10 16:04:56 +02001696 int ret, clear, set, offset;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02001697
1698 /* Check if the driver should configure link and PHY. */
1699 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1700 OHCI1394_HCControl_programPhyEnable))
1701 return 0;
1702
1703 /* Paranoia: check whether the PHY supports 1394a, too. */
1704 enable_1394a = false;
Stefan Richter35d999b2010-04-10 16:04:56 +02001705 ret = read_phy_reg(ohci, 2);
1706 if (ret < 0)
1707 return ret;
1708 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1709 ret = read_paged_phy_reg(ohci, 1, 8);
1710 if (ret < 0)
1711 return ret;
1712 if (ret >= 1)
Clemens Ladisch925e7a62010-04-04 15:19:54 +02001713 enable_1394a = true;
1714 }
1715
1716 if (ohci->quirks & QUIRK_NO_1394A)
1717 enable_1394a = false;
1718
1719 /* Configure PHY and link consistently. */
1720 if (enable_1394a) {
1721 clear = 0;
1722 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1723 } else {
1724 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1725 set = 0;
1726 }
Stefan Richter02d37be2010-07-08 16:09:06 +02001727 ret = update_phy_reg(ohci, 5, clear, set);
Stefan Richter35d999b2010-04-10 16:04:56 +02001728 if (ret < 0)
1729 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02001730
1731 if (enable_1394a)
1732 offset = OHCI1394_HCControlSet;
1733 else
1734 offset = OHCI1394_HCControlClear;
1735 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1736
1737 /* Clean up: configuration has been taken care of. */
1738 reg_write(ohci, OHCI1394_HCControlClear,
1739 OHCI1394_HCControl_programPhyEnable);
1740
1741 return 0;
1742}
1743
Stefan Richter8e859732009-10-08 00:41:59 +02001744static int ohci_enable(struct fw_card *card,
1745 const __be32 *config_rom, size_t length)
Kristian Høgsberged568912006-12-19 19:58:35 -05001746{
1747 struct fw_ohci *ohci = fw_ohci(card);
1748 struct pci_dev *dev = to_pci_dev(card->device);
Clemens Ladische91b2782010-06-10 08:40:49 +02001749 u32 lps, seconds, version, irqs;
Stefan Richter35d999b2010-04-10 16:04:56 +02001750 int i, ret;
Kristian Høgsberged568912006-12-19 19:58:35 -05001751
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001752 if (software_reset(ohci)) {
1753 fw_error("Failed to reset ohci card.\n");
1754 return -EBUSY;
1755 }
1756
1757 /*
1758 * Now enable LPS, which we need in order to start accessing
1759 * most of the registers. In fact, on some cards (ALI M5251),
1760 * accessing registers in the SClk domain without LPS enabled
1761 * will lock up the machine. Wait 50msec to make sure we have
Jarod Wilson02214722008-03-28 10:02:50 -04001762 * full link enabled. However, with some cards (well, at least
1763 * a JMicron PCIe card), we have to try again sometimes.
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001764 */
1765 reg_write(ohci, OHCI1394_HCControlSet,
1766 OHCI1394_HCControl_LPS |
1767 OHCI1394_HCControl_postedWriteEnable);
1768 flush_writes(ohci);
Jarod Wilson02214722008-03-28 10:02:50 -04001769
1770 for (lps = 0, i = 0; !lps && i < 3; i++) {
1771 msleep(50);
1772 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1773 OHCI1394_HCControl_LPS;
1774 }
1775
1776 if (!lps) {
1777 fw_error("Failed to set Link Power Status\n");
1778 return -EIO;
1779 }
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001780
1781 reg_write(ohci, OHCI1394_HCControlClear,
1782 OHCI1394_HCControl_noByteSwapData);
1783
Stefan Richteraffc9c22008-06-05 20:50:53 +02001784 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001785 reg_write(ohci, OHCI1394_LinkControlSet,
1786 OHCI1394_LinkControl_rcvSelfID |
Stefan Richterbf54e142010-07-16 22:25:51 +02001787 OHCI1394_LinkControl_rcvPhyPkt |
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001788 OHCI1394_LinkControl_cycleTimerEnable |
1789 OHCI1394_LinkControl_cycleMaster);
1790
1791 reg_write(ohci, OHCI1394_ATRetries,
1792 OHCI1394_MAX_AT_REQ_RETRIES |
1793 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
Clemens Ladisch27a23292010-06-10 08:34:13 +02001794 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1795 (200 << 16));
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001796
Clemens Ladischa48777e2010-06-10 08:33:07 +02001797 seconds = lower_32_bits(get_seconds());
1798 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1799 ohci->bus_time = seconds & ~0x3f;
1800
Clemens Ladische91b2782010-06-10 08:40:49 +02001801 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1802 if (version >= OHCI_VERSION_1_1) {
1803 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1804 0xfffffffe);
Stefan Richterdb3c9cc2010-06-12 20:30:21 +02001805 card->broadcast_channel_auto_allocated = true;
Clemens Ladische91b2782010-06-10 08:40:49 +02001806 }
1807
Clemens Ladischa1a11322010-06-10 08:35:06 +02001808 /* Get implemented bits of the priority arbitration request counter. */
1809 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1810 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1811 reg_write(ohci, OHCI1394_FairnessControl, 0);
Stefan Richterdb3c9cc2010-06-12 20:30:21 +02001812 card->priority_budget_implemented = ohci->pri_req_max != 0;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001813
1814 ar_context_run(&ohci->ar_request_ctx);
1815 ar_context_run(&ohci->ar_response_ctx);
1816
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001817 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1818 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1819 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001820
Stefan Richter35d999b2010-04-10 16:04:56 +02001821 ret = configure_1394a_enhancements(ohci);
1822 if (ret < 0)
1823 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02001824
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001825 /* Activate link_on bit and contender bit in our self ID packets.*/
Stefan Richter35d999b2010-04-10 16:04:56 +02001826 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1827 if (ret < 0)
1828 return ret;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001829
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001830 /*
1831 * When the link is not yet enabled, the atomic config rom
Kristian Høgsberged568912006-12-19 19:58:35 -05001832 * update mechanism described below in ohci_set_config_rom()
1833 * is not active. We have to update ConfigRomHeader and
1834 * BusOptions manually, and the write to ConfigROMmap takes
1835 * effect immediately. We tie this to the enabling of the
1836 * link, so we have a valid config rom before enabling - the
1837 * OHCI requires that ConfigROMhdr and BusOptions have valid
1838 * values before enabling.
1839 *
1840 * However, when the ConfigROMmap is written, some controllers
1841 * always read back quadlets 0 and 2 from the config rom to
1842 * the ConfigRomHeader and BusOptions registers on bus reset.
1843 * They shouldn't do that in this initial case where the link
1844 * isn't enabled. This means we have to use the same
1845 * workaround here, setting the bus header to 0 and then write
1846 * the right values in the bus reset tasklet.
1847 */
1848
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001849 if (config_rom) {
1850 ohci->next_config_rom =
1851 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1852 &ohci->next_config_rom_bus,
1853 GFP_KERNEL);
1854 if (ohci->next_config_rom == NULL)
1855 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001856
Stefan Richter8e859732009-10-08 00:41:59 +02001857 copy_config_rom(ohci->next_config_rom, config_rom, length);
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001858 } else {
1859 /*
1860 * In the suspend case, config_rom is NULL, which
1861 * means that we just reuse the old config rom.
1862 */
1863 ohci->next_config_rom = ohci->config_rom;
1864 ohci->next_config_rom_bus = ohci->config_rom_bus;
1865 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001866
Stefan Richter8e859732009-10-08 00:41:59 +02001867 ohci->next_header = ohci->next_config_rom[0];
Kristian Høgsberged568912006-12-19 19:58:35 -05001868 ohci->next_config_rom[0] = 0;
1869 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001870 reg_write(ohci, OHCI1394_BusOptions,
1871 be32_to_cpu(ohci->next_config_rom[2]));
Kristian Høgsberged568912006-12-19 19:58:35 -05001872 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1873
1874 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1875
Clemens Ladisch262444e2010-06-05 12:31:25 +02001876 if (!(ohci->quirks & QUIRK_NO_MSI))
1877 pci_enable_msi(dev);
Kristian Høgsberged568912006-12-19 19:58:35 -05001878 if (request_irq(dev->irq, irq_handler,
Clemens Ladisch262444e2010-06-05 12:31:25 +02001879 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1880 ohci_driver_name, ohci)) {
1881 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1882 pci_disable_msi(dev);
Kristian Høgsberged568912006-12-19 19:58:35 -05001883 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1884 ohci->config_rom, ohci->config_rom_bus);
1885 return -EIO;
1886 }
1887
Stefan Richter148c7862010-06-05 11:46:49 +02001888 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1889 OHCI1394_RQPkt | OHCI1394_RSPkt |
1890 OHCI1394_isochTx | OHCI1394_isochRx |
1891 OHCI1394_postedWriteErr |
1892 OHCI1394_selfIDComplete |
1893 OHCI1394_regAccessFail |
Clemens Ladischa48777e2010-06-10 08:33:07 +02001894 OHCI1394_cycle64Seconds |
Stefan Richter148c7862010-06-05 11:46:49 +02001895 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1896 OHCI1394_masterIntEnable;
1897 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1898 irqs |= OHCI1394_busReset;
1899 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1900
Kristian Høgsberged568912006-12-19 19:58:35 -05001901 reg_write(ohci, OHCI1394_HCControlSet,
1902 OHCI1394_HCControl_linkEnable |
1903 OHCI1394_HCControl_BIBimageValid);
1904 flush_writes(ohci);
1905
Stefan Richter02d37be2010-07-08 16:09:06 +02001906 /* We are ready to go, reset bus to finish initialization. */
1907 fw_schedule_bus_reset(&ohci->card, false, true);
Kristian Høgsberged568912006-12-19 19:58:35 -05001908
1909 return 0;
1910}
1911
Stefan Richter53dca512008-12-14 21:47:04 +01001912static int ohci_set_config_rom(struct fw_card *card,
Stefan Richter8e859732009-10-08 00:41:59 +02001913 const __be32 *config_rom, size_t length)
Kristian Høgsberged568912006-12-19 19:58:35 -05001914{
1915 struct fw_ohci *ohci;
1916 unsigned long flags;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001917 int ret = -EBUSY;
Kristian Høgsberged568912006-12-19 19:58:35 -05001918 __be32 *next_config_rom;
Stefan Richterf5101d582008-03-14 00:27:49 +01001919 dma_addr_t uninitialized_var(next_config_rom_bus);
Kristian Høgsberged568912006-12-19 19:58:35 -05001920
1921 ohci = fw_ohci(card);
1922
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001923 /*
1924 * When the OHCI controller is enabled, the config rom update
Kristian Høgsberged568912006-12-19 19:58:35 -05001925 * mechanism is a bit tricky, but easy enough to use. See
1926 * section 5.5.6 in the OHCI specification.
1927 *
1928 * The OHCI controller caches the new config rom address in a
1929 * shadow register (ConfigROMmapNext) and needs a bus reset
1930 * for the changes to take place. When the bus reset is
1931 * detected, the controller loads the new values for the
1932 * ConfigRomHeader and BusOptions registers from the specified
1933 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1934 * shadow register. All automatically and atomically.
1935 *
1936 * Now, there's a twist to this story. The automatic load of
1937 * ConfigRomHeader and BusOptions doesn't honor the
1938 * noByteSwapData bit, so with a be32 config rom, the
1939 * controller will load be32 values in to these registers
1940 * during the atomic update, even on litte endian
1941 * architectures. The workaround we use is to put a 0 in the
1942 * header quadlet; 0 is endian agnostic and means that the
1943 * config rom isn't ready yet. In the bus reset tasklet we
1944 * then set up the real values for the two registers.
1945 *
1946 * We use ohci->lock to avoid racing with the code that sets
1947 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1948 */
1949
1950 next_config_rom =
1951 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1952 &next_config_rom_bus, GFP_KERNEL);
1953 if (next_config_rom == NULL)
1954 return -ENOMEM;
1955
1956 spin_lock_irqsave(&ohci->lock, flags);
1957
1958 if (ohci->next_config_rom == NULL) {
1959 ohci->next_config_rom = next_config_rom;
1960 ohci->next_config_rom_bus = next_config_rom_bus;
1961
Stefan Richter8e859732009-10-08 00:41:59 +02001962 copy_config_rom(ohci->next_config_rom, config_rom, length);
Kristian Høgsberged568912006-12-19 19:58:35 -05001963
1964 ohci->next_header = config_rom[0];
1965 ohci->next_config_rom[0] = 0;
1966
1967 reg_write(ohci, OHCI1394_ConfigROMmap,
1968 ohci->next_config_rom_bus);
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001969 ret = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001970 }
1971
1972 spin_unlock_irqrestore(&ohci->lock, flags);
1973
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001974 /*
1975 * Now initiate a bus reset to have the changes take
Kristian Høgsberged568912006-12-19 19:58:35 -05001976 * effect. We clean up the old config rom memory and DMA
1977 * mappings in the bus reset tasklet, since the OHCI
1978 * controller could need to access it before the bus reset
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001979 * takes effect.
1980 */
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001981 if (ret == 0)
Stefan Richter02d37be2010-07-08 16:09:06 +02001982 fw_schedule_bus_reset(&ohci->card, true, true);
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001983 else
1984 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1985 next_config_rom, next_config_rom_bus);
Kristian Høgsberged568912006-12-19 19:58:35 -05001986
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001987 return ret;
Kristian Høgsberged568912006-12-19 19:58:35 -05001988}
1989
1990static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1991{
1992 struct fw_ohci *ohci = fw_ohci(card);
1993
1994 at_context_transmit(&ohci->at_request_ctx, packet);
1995}
1996
1997static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1998{
1999 struct fw_ohci *ohci = fw_ohci(card);
2000
2001 at_context_transmit(&ohci->at_response_ctx, packet);
2002}
2003
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002004static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2005{
2006 struct fw_ohci *ohci = fw_ohci(card);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002007 struct context *ctx = &ohci->at_request_ctx;
2008 struct driver_data *driver_data = packet->driver_data;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002009 int ret = -ENOENT;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002010
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002011 tasklet_disable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002012
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002013 if (packet->ack != 0)
2014 goto out;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002015
Stefan Richter19593ff2009-10-14 20:40:10 +02002016 if (packet->payload_mapped)
Stefan Richter1d1dc5e2008-12-10 00:20:38 +01002017 dma_unmap_single(ohci->card.device, packet->payload_bus,
2018 packet->payload_length, DMA_TO_DEVICE);
2019
Stefan Richterad3c0fe2008-03-20 22:04:36 +01002020 log_ar_at_event('T', packet->speed, packet->header, 0x20);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002021 driver_data->packet = NULL;
2022 packet->ack = RCODE_CANCELLED;
2023 packet->callback(packet, &ohci->card, packet->ack);
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002024 ret = 0;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002025 out:
2026 tasklet_enable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002027
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002028 return ret;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002029}
2030
Stefan Richter53dca512008-12-14 21:47:04 +01002031static int ohci_enable_phys_dma(struct fw_card *card,
2032 int node_id, int generation)
Kristian Høgsberged568912006-12-19 19:58:35 -05002033{
Stefan Richter080de8c2008-02-28 20:54:43 +01002034#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2035 return 0;
2036#else
Kristian Høgsberged568912006-12-19 19:58:35 -05002037 struct fw_ohci *ohci = fw_ohci(card);
2038 unsigned long flags;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002039 int n, ret = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05002040
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002041 /*
2042 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2043 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2044 */
Kristian Høgsberged568912006-12-19 19:58:35 -05002045
2046 spin_lock_irqsave(&ohci->lock, flags);
2047
2048 if (ohci->generation != generation) {
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002049 ret = -ESTALE;
Kristian Høgsberged568912006-12-19 19:58:35 -05002050 goto out;
2051 }
2052
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002053 /*
2054 * Note, if the node ID contains a non-local bus ID, physical DMA is
2055 * enabled for _all_ nodes on remote buses.
2056 */
Stefan Richter907293d2007-01-23 21:11:43 +01002057
2058 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2059 if (n < 32)
2060 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2061 else
2062 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2063
Kristian Høgsberged568912006-12-19 19:58:35 -05002064 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05002065 out:
Stefan Richter6cad95f2007-01-21 20:46:45 +01002066 spin_unlock_irqrestore(&ohci->lock, flags);
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002067
2068 return ret;
Stefan Richter080de8c2008-02-28 20:54:43 +01002069#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
Kristian Høgsberged568912006-12-19 19:58:35 -05002070}
Stefan Richter373b2ed2007-03-04 14:45:18 +01002071
Stefan Richter0fcff4e2010-06-12 20:35:52 +02002072static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002073{
2074 struct fw_ohci *ohci = fw_ohci(card);
Clemens Ladischa48777e2010-06-10 08:33:07 +02002075 unsigned long flags;
2076 u32 value;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002077
Clemens Ladisch60d32972010-06-10 08:24:35 +02002078 switch (csr_offset) {
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002079 case CSR_STATE_CLEAR:
2080 case CSR_STATE_SET:
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002081 if (ohci->is_root &&
2082 (reg_read(ohci, OHCI1394_LinkControlSet) &
2083 OHCI1394_LinkControl_cycleMaster))
Stefan Richterc8a94de2010-06-12 20:34:50 +02002084 value = CSR_STATE_BIT_CMSTR;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002085 else
Stefan Richterc8a94de2010-06-12 20:34:50 +02002086 value = 0;
2087 if (ohci->csr_state_setclear_abdicate)
2088 value |= CSR_STATE_BIT_ABDICATE;
Stefan Richter4a9bde92010-02-20 22:24:43 +01002089
Stefan Richterc8a94de2010-06-12 20:34:50 +02002090 return value;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002091
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002092 case CSR_NODE_IDS:
2093 return reg_read(ohci, OHCI1394_NodeID) << 16;
2094
Clemens Ladisch60d32972010-06-10 08:24:35 +02002095 case CSR_CYCLE_TIME:
2096 return get_cycle_time(ohci);
2097
Clemens Ladischa48777e2010-06-10 08:33:07 +02002098 case CSR_BUS_TIME:
2099 /*
2100 * We might be called just after the cycle timer has wrapped
2101 * around but just before the cycle64Seconds handler, so we
2102 * better check here, too, if the bus time needs to be updated.
2103 */
2104 spin_lock_irqsave(&ohci->lock, flags);
2105 value = update_bus_time(ohci);
2106 spin_unlock_irqrestore(&ohci->lock, flags);
2107 return value;
2108
Clemens Ladisch27a23292010-06-10 08:34:13 +02002109 case CSR_BUSY_TIMEOUT:
2110 value = reg_read(ohci, OHCI1394_ATRetries);
2111 return (value >> 4) & 0x0ffff00f;
2112
Clemens Ladischa1a11322010-06-10 08:35:06 +02002113 case CSR_PRIORITY_BUDGET:
2114 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2115 (ohci->pri_req_max << 8);
2116
Clemens Ladisch60d32972010-06-10 08:24:35 +02002117 default:
2118 WARN_ON(1);
2119 return 0;
Clemens Ladischb6775322010-01-20 09:58:02 +01002120 }
Clemens Ladisch60d32972010-06-10 08:24:35 +02002121}
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002122
Stefan Richter0fcff4e2010-06-12 20:35:52 +02002123static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002124{
2125 struct fw_ohci *ohci = fw_ohci(card);
Clemens Ladischa48777e2010-06-10 08:33:07 +02002126 unsigned long flags;
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002127
2128 switch (csr_offset) {
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002129 case CSR_STATE_CLEAR:
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002130 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2131 reg_write(ohci, OHCI1394_LinkControlClear,
2132 OHCI1394_LinkControl_cycleMaster);
2133 flush_writes(ohci);
2134 }
Stefan Richterc8a94de2010-06-12 20:34:50 +02002135 if (value & CSR_STATE_BIT_ABDICATE)
2136 ohci->csr_state_setclear_abdicate = false;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002137 break;
2138
2139 case CSR_STATE_SET:
2140 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2141 reg_write(ohci, OHCI1394_LinkControlSet,
2142 OHCI1394_LinkControl_cycleMaster);
2143 flush_writes(ohci);
2144 }
Stefan Richterc8a94de2010-06-12 20:34:50 +02002145 if (value & CSR_STATE_BIT_ABDICATE)
2146 ohci->csr_state_setclear_abdicate = true;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002147 break;
2148
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002149 case CSR_NODE_IDS:
2150 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2151 flush_writes(ohci);
2152 break;
2153
Clemens Ladisch9ab50712010-06-10 08:26:48 +02002154 case CSR_CYCLE_TIME:
2155 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2156 reg_write(ohci, OHCI1394_IntEventSet,
2157 OHCI1394_cycleInconsistent);
2158 flush_writes(ohci);
2159 break;
2160
Clemens Ladischa48777e2010-06-10 08:33:07 +02002161 case CSR_BUS_TIME:
2162 spin_lock_irqsave(&ohci->lock, flags);
2163 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2164 spin_unlock_irqrestore(&ohci->lock, flags);
2165 break;
2166
Clemens Ladisch27a23292010-06-10 08:34:13 +02002167 case CSR_BUSY_TIMEOUT:
2168 value = (value & 0xf) | ((value & 0xf) << 4) |
2169 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2170 reg_write(ohci, OHCI1394_ATRetries, value);
2171 flush_writes(ohci);
2172 break;
2173
Clemens Ladischa1a11322010-06-10 08:35:06 +02002174 case CSR_PRIORITY_BUDGET:
2175 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2176 flush_writes(ohci);
2177 break;
2178
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002179 default:
2180 WARN_ON(1);
2181 break;
2182 }
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002183}
2184
David Moore1aa292b2008-07-22 23:23:40 -07002185static void copy_iso_headers(struct iso_context *ctx, void *p)
2186{
2187 int i = ctx->header_length;
2188
2189 if (i + ctx->base.header_size > PAGE_SIZE)
2190 return;
2191
2192 /*
2193 * The iso header is byteswapped to little endian by
2194 * the controller, but the remaining header quadlets
2195 * are big endian. We want to present all the headers
2196 * as big endian, so we have to swap the first quadlet.
2197 */
2198 if (ctx->base.header_size > 0)
2199 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2200 if (ctx->base.header_size > 4)
2201 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2202 if (ctx->base.header_size > 8)
2203 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2204 ctx->header_length += ctx->base.header_size;
2205}
2206
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002207static int handle_ir_packet_per_buffer(struct context *context,
2208 struct descriptor *d,
2209 struct descriptor *last)
2210{
2211 struct iso_context *ctx =
2212 container_of(context, struct iso_context, context);
David Moorebcee8932007-12-19 15:26:38 -05002213 struct descriptor *pd;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002214 __le32 *ir_header;
David Moorebcee8932007-12-19 15:26:38 -05002215 void *p;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002216
Stefan Richter872e3302010-07-29 18:19:22 +02002217 for (pd = d; pd <= last; pd++)
David Moorebcee8932007-12-19 15:26:38 -05002218 if (pd->transfer_status)
2219 break;
David Moorebcee8932007-12-19 15:26:38 -05002220 if (pd > last)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002221 /* Descriptor(s) not done yet, stop iteration */
2222 return 0;
2223
David Moore1aa292b2008-07-22 23:23:40 -07002224 p = last + 1;
2225 copy_iso_headers(ctx, p);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002226
David Moorebcee8932007-12-19 15:26:38 -05002227 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2228 ir_header = (__le32 *) p;
Stefan Richter872e3302010-07-29 18:19:22 +02002229 ctx->base.callback.sc(&ctx->base,
2230 le32_to_cpu(ir_header[0]) & 0xffff,
2231 ctx->header_length, ctx->header,
2232 ctx->base.callback_data);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002233 ctx->header_length = 0;
2234 }
2235
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002236 return 1;
2237}
2238
Stefan Richter872e3302010-07-29 18:19:22 +02002239/* d == last because each descriptor block is only a single descriptor. */
2240static int handle_ir_buffer_fill(struct context *context,
2241 struct descriptor *d,
2242 struct descriptor *last)
2243{
2244 struct iso_context *ctx =
2245 container_of(context, struct iso_context, context);
2246
2247 if (!last->transfer_status)
2248 /* Descriptor(s) not done yet, stop iteration */
2249 return 0;
2250
2251 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2252 ctx->base.callback.mc(&ctx->base,
2253 le32_to_cpu(last->data_address) +
2254 le16_to_cpu(last->req_count) -
2255 le16_to_cpu(last->res_count),
2256 ctx->base.callback_data);
2257
2258 return 1;
2259}
2260
Kristian Høgsberg30200732007-02-16 17:34:39 -05002261static int handle_it_packet(struct context *context,
2262 struct descriptor *d,
2263 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05002264{
Kristian Høgsberg30200732007-02-16 17:34:39 -05002265 struct iso_context *ctx =
2266 container_of(context, struct iso_context, context);
Jay Fenlason31769ce2009-11-21 00:05:56 +01002267 int i;
2268 struct descriptor *pd;
Stefan Richter373b2ed2007-03-04 14:45:18 +01002269
Jay Fenlason31769ce2009-11-21 00:05:56 +01002270 for (pd = d; pd <= last; pd++)
2271 if (pd->transfer_status)
2272 break;
2273 if (pd > last)
2274 /* Descriptor(s) not done yet, stop iteration */
Kristian Høgsberg30200732007-02-16 17:34:39 -05002275 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05002276
Jay Fenlason31769ce2009-11-21 00:05:56 +01002277 i = ctx->header_length;
2278 if (i + 4 < PAGE_SIZE) {
2279 /* Present this value as big-endian to match the receive code */
2280 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2281 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2282 le16_to_cpu(pd->res_count));
2283 ctx->header_length += 4;
2284 }
2285 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
Stefan Richter872e3302010-07-29 18:19:22 +02002286 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2287 ctx->header_length, ctx->header,
2288 ctx->base.callback_data);
Jay Fenlason31769ce2009-11-21 00:05:56 +01002289 ctx->header_length = 0;
2290 }
Kristian Høgsberg30200732007-02-16 17:34:39 -05002291 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05002292}
2293
Stefan Richter872e3302010-07-29 18:19:22 +02002294static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2295{
2296 u32 hi = channels >> 32, lo = channels;
2297
2298 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2299 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2300 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2301 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2302 mmiowb();
2303 ohci->mc_channels = channels;
2304}
2305
Stefan Richter53dca512008-12-14 21:47:04 +01002306static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
Stefan Richter4817ed22008-12-21 16:39:46 +01002307 int type, int channel, size_t header_size)
Kristian Høgsberged568912006-12-19 19:58:35 -05002308{
2309 struct fw_ohci *ohci = fw_ohci(card);
Stefan Richter872e3302010-07-29 18:19:22 +02002310 struct iso_context *uninitialized_var(ctx);
2311 descriptor_callback_t uninitialized_var(callback);
2312 u64 *uninitialized_var(channels);
2313 u32 *uninitialized_var(mask), uninitialized_var(regs);
Kristian Høgsberged568912006-12-19 19:58:35 -05002314 unsigned long flags;
Stefan Richter872e3302010-07-29 18:19:22 +02002315 int index, ret = -EBUSY;
Kristian Høgsberged568912006-12-19 19:58:35 -05002316
2317 spin_lock_irqsave(&ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02002318
2319 switch (type) {
2320 case FW_ISO_CONTEXT_TRANSMIT:
2321 mask = &ohci->it_context_mask;
2322 callback = handle_it_packet;
2323 index = ffs(*mask) - 1;
2324 if (index >= 0) {
2325 *mask &= ~(1 << index);
2326 regs = OHCI1394_IsoXmitContextBase(index);
2327 ctx = &ohci->it_context_list[index];
2328 }
2329 break;
2330
2331 case FW_ISO_CONTEXT_RECEIVE:
2332 channels = &ohci->ir_context_channels;
2333 mask = &ohci->ir_context_mask;
2334 callback = handle_ir_packet_per_buffer;
2335 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2336 if (index >= 0) {
2337 *channels &= ~(1ULL << channel);
2338 *mask &= ~(1 << index);
2339 regs = OHCI1394_IsoRcvContextBase(index);
2340 ctx = &ohci->ir_context_list[index];
2341 }
2342 break;
2343
2344 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2345 mask = &ohci->ir_context_mask;
2346 callback = handle_ir_buffer_fill;
2347 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2348 if (index >= 0) {
2349 ohci->mc_allocated = true;
2350 *mask &= ~(1 << index);
2351 regs = OHCI1394_IsoRcvContextBase(index);
2352 ctx = &ohci->ir_context_list[index];
2353 }
2354 break;
2355
2356 default:
2357 index = -1;
2358 ret = -ENOSYS;
Stefan Richter4817ed22008-12-21 16:39:46 +01002359 }
Stefan Richter872e3302010-07-29 18:19:22 +02002360
Kristian Høgsberged568912006-12-19 19:58:35 -05002361 spin_unlock_irqrestore(&ohci->lock, flags);
2362
2363 if (index < 0)
Stefan Richter872e3302010-07-29 18:19:22 +02002364 return ERR_PTR(ret);
Kristian Høgsberged568912006-12-19 19:58:35 -05002365
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002366 memset(ctx, 0, sizeof(*ctx));
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002367 ctx->header_length = 0;
2368 ctx->header = (void *) __get_free_page(GFP_KERNEL);
Stefan Richter872e3302010-07-29 18:19:22 +02002369 if (ctx->header == NULL) {
2370 ret = -ENOMEM;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002371 goto out;
Stefan Richter872e3302010-07-29 18:19:22 +02002372 }
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002373 ret = context_init(&ctx->context, ohci, regs, callback);
2374 if (ret < 0)
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002375 goto out_with_header;
Kristian Høgsberged568912006-12-19 19:58:35 -05002376
Stefan Richter872e3302010-07-29 18:19:22 +02002377 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2378 set_multichannel_mask(ohci, 0);
2379
Kristian Høgsberged568912006-12-19 19:58:35 -05002380 return &ctx->base;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002381
2382 out_with_header:
2383 free_page((unsigned long)ctx->header);
2384 out:
2385 spin_lock_irqsave(&ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02002386
2387 switch (type) {
2388 case FW_ISO_CONTEXT_RECEIVE:
2389 *channels |= 1ULL << channel;
2390 break;
2391
2392 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2393 ohci->mc_allocated = false;
2394 break;
2395 }
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002396 *mask |= 1 << index;
Stefan Richter872e3302010-07-29 18:19:22 +02002397
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002398 spin_unlock_irqrestore(&ohci->lock, flags);
2399
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002400 return ERR_PTR(ret);
Kristian Høgsberged568912006-12-19 19:58:35 -05002401}
2402
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04002403static int ohci_start_iso(struct fw_iso_context *base,
2404 s32 cycle, u32 sync, u32 tags)
Kristian Høgsberged568912006-12-19 19:58:35 -05002405{
Stefan Richter373b2ed2007-03-04 14:45:18 +01002406 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05002407 struct fw_ohci *ohci = ctx->context.ohci;
Stefan Richter872e3302010-07-29 18:19:22 +02002408 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
Kristian Høgsberged568912006-12-19 19:58:35 -05002409 int index;
2410
Stefan Richter872e3302010-07-29 18:19:22 +02002411 switch (ctx->base.type) {
2412 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002413 index = ctx - ohci->it_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04002414 match = 0;
2415 if (cycle >= 0)
2416 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002417 (cycle & 0x7fff) << 16;
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05002418
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002419 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2420 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04002421 context_run(&ctx->context, match);
Stefan Richter872e3302010-07-29 18:19:22 +02002422 break;
2423
2424 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2425 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2426 /* fall through */
2427 case FW_ISO_CONTEXT_RECEIVE:
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002428 index = ctx - ohci->ir_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04002429 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2430 if (cycle >= 0) {
2431 match |= (cycle & 0x07fff) << 12;
2432 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2433 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002434
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002435 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2436 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002437 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04002438 context_run(&ctx->context, control);
Stefan Richter872e3302010-07-29 18:19:22 +02002439 break;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002440 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002441
2442 return 0;
2443}
2444
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002445static int ohci_stop_iso(struct fw_iso_context *base)
2446{
2447 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01002448 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002449 int index;
2450
Stefan Richter872e3302010-07-29 18:19:22 +02002451 switch (ctx->base.type) {
2452 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002453 index = ctx - ohci->it_context_list;
2454 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
Stefan Richter872e3302010-07-29 18:19:22 +02002455 break;
2456
2457 case FW_ISO_CONTEXT_RECEIVE:
2458 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002459 index = ctx - ohci->ir_context_list;
2460 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
Stefan Richter872e3302010-07-29 18:19:22 +02002461 break;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002462 }
2463 flush_writes(ohci);
2464 context_stop(&ctx->context);
2465
2466 return 0;
2467}
2468
Kristian Høgsberged568912006-12-19 19:58:35 -05002469static void ohci_free_iso_context(struct fw_iso_context *base)
2470{
2471 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01002472 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberged568912006-12-19 19:58:35 -05002473 unsigned long flags;
2474 int index;
2475
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002476 ohci_stop_iso(base);
2477 context_release(&ctx->context);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002478 free_page((unsigned long)ctx->header);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002479
Kristian Høgsberged568912006-12-19 19:58:35 -05002480 spin_lock_irqsave(&ohci->lock, flags);
2481
Stefan Richter872e3302010-07-29 18:19:22 +02002482 switch (base->type) {
2483 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsberged568912006-12-19 19:58:35 -05002484 index = ctx - ohci->it_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05002485 ohci->it_context_mask |= 1 << index;
Stefan Richter872e3302010-07-29 18:19:22 +02002486 break;
2487
2488 case FW_ISO_CONTEXT_RECEIVE:
Kristian Høgsberged568912006-12-19 19:58:35 -05002489 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05002490 ohci->ir_context_mask |= 1 << index;
Stefan Richter4817ed22008-12-21 16:39:46 +01002491 ohci->ir_context_channels |= 1ULL << base->channel;
Stefan Richter872e3302010-07-29 18:19:22 +02002492 break;
2493
2494 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2495 index = ctx - ohci->ir_context_list;
2496 ohci->ir_context_mask |= 1 << index;
2497 ohci->ir_context_channels |= ohci->mc_channels;
2498 ohci->mc_channels = 0;
2499 ohci->mc_allocated = false;
2500 break;
Kristian Høgsberged568912006-12-19 19:58:35 -05002501 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002502
2503 spin_unlock_irqrestore(&ohci->lock, flags);
2504}
2505
Stefan Richter872e3302010-07-29 18:19:22 +02002506static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
Kristian Høgsberged568912006-12-19 19:58:35 -05002507{
Stefan Richter872e3302010-07-29 18:19:22 +02002508 struct fw_ohci *ohci = fw_ohci(base->card);
2509 unsigned long flags;
2510 int ret;
2511
2512 switch (base->type) {
2513 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2514
2515 spin_lock_irqsave(&ohci->lock, flags);
2516
2517 /* Don't allow multichannel to grab other contexts' channels. */
2518 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2519 *channels = ohci->ir_context_channels;
2520 ret = -EBUSY;
2521 } else {
2522 set_multichannel_mask(ohci, *channels);
2523 ret = 0;
2524 }
2525
2526 spin_unlock_irqrestore(&ohci->lock, flags);
2527
2528 break;
2529 default:
2530 ret = -EINVAL;
2531 }
2532
2533 return ret;
2534}
2535
2536static int queue_iso_transmit(struct iso_context *ctx,
2537 struct fw_iso_packet *packet,
2538 struct fw_iso_buffer *buffer,
2539 unsigned long payload)
2540{
Kristian Høgsberg30200732007-02-16 17:34:39 -05002541 struct descriptor *d, *last, *pd;
Kristian Høgsberged568912006-12-19 19:58:35 -05002542 struct fw_iso_packet *p;
2543 __le32 *header;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05002544 dma_addr_t d_bus, page_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -05002545 u32 z, header_z, payload_z, irq;
2546 u32 payload_index, payload_end_index, next_page_index;
Kristian Høgsberg30200732007-02-16 17:34:39 -05002547 int page, end_page, i, length, offset;
Kristian Høgsberged568912006-12-19 19:58:35 -05002548
Kristian Høgsberged568912006-12-19 19:58:35 -05002549 p = packet;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05002550 payload_index = payload;
Kristian Høgsberged568912006-12-19 19:58:35 -05002551
2552 if (p->skip)
2553 z = 1;
2554 else
2555 z = 2;
2556 if (p->header_length > 0)
2557 z++;
2558
2559 /* Determine the first page the payload isn't contained in. */
2560 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2561 if (p->payload_length > 0)
2562 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2563 else
2564 payload_z = 0;
2565
2566 z += payload_z;
2567
2568 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002569 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05002570
Kristian Høgsberg30200732007-02-16 17:34:39 -05002571 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2572 if (d == NULL)
2573 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05002574
2575 if (!p->skip) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002576 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsberged568912006-12-19 19:58:35 -05002577 d[0].req_count = cpu_to_le16(8);
Clemens Ladisch7f51a102010-02-08 08:30:03 +01002578 /*
2579 * Link the skip address to this descriptor itself. This causes
2580 * a context to skip a cycle whenever lost cycles or FIFO
2581 * overruns occur, without dropping the data. The application
2582 * should then decide whether this is an error condition or not.
2583 * FIXME: Make the context's cycle-lost behaviour configurable?
2584 */
2585 d[0].branch_address = cpu_to_le32(d_bus | z);
Kristian Høgsberged568912006-12-19 19:58:35 -05002586
2587 header = (__le32 *) &d[1];
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002588 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2589 IT_HEADER_TAG(p->tag) |
2590 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2591 IT_HEADER_CHANNEL(ctx->base.channel) |
2592 IT_HEADER_SPEED(ctx->base.speed));
Kristian Høgsberged568912006-12-19 19:58:35 -05002593 header[1] =
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002594 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
Kristian Høgsberged568912006-12-19 19:58:35 -05002595 p->payload_length));
2596 }
2597
2598 if (p->header_length > 0) {
2599 d[2].req_count = cpu_to_le16(p->header_length);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002600 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05002601 memcpy(&d[z], p->header, p->header_length);
2602 }
2603
2604 pd = d + z - payload_z;
2605 payload_end_index = payload_index + p->payload_length;
2606 for (i = 0; i < payload_z; i++) {
2607 page = payload_index >> PAGE_SHIFT;
2608 offset = payload_index & ~PAGE_MASK;
2609 next_page_index = (page + 1) << PAGE_SHIFT;
2610 length =
2611 min(next_page_index, payload_end_index) - payload_index;
2612 pd[i].req_count = cpu_to_le16(length);
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05002613
2614 page_bus = page_private(buffer->pages[page]);
2615 pd[i].data_address = cpu_to_le32(page_bus + offset);
Kristian Høgsberged568912006-12-19 19:58:35 -05002616
2617 payload_index += length;
2618 }
2619
Kristian Høgsberged568912006-12-19 19:58:35 -05002620 if (p->interrupt)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002621 irq = DESCRIPTOR_IRQ_ALWAYS;
Kristian Høgsberged568912006-12-19 19:58:35 -05002622 else
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002623 irq = DESCRIPTOR_NO_IRQ;
Kristian Høgsberged568912006-12-19 19:58:35 -05002624
Kristian Høgsberg30200732007-02-16 17:34:39 -05002625 last = z == 2 ? d : d + z - 1;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04002626 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2627 DESCRIPTOR_STATUS |
2628 DESCRIPTOR_BRANCH_ALWAYS |
Kristian Høgsbergcbb59da2007-02-16 17:34:35 -05002629 irq);
Kristian Høgsberged568912006-12-19 19:58:35 -05002630
Kristian Høgsberg30200732007-02-16 17:34:39 -05002631 context_append(&ctx->context, d, z, header_z);
Kristian Høgsberged568912006-12-19 19:58:35 -05002632
2633 return 0;
2634}
Stefan Richter373b2ed2007-03-04 14:45:18 +01002635
Stefan Richter872e3302010-07-29 18:19:22 +02002636static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2637 struct fw_iso_packet *packet,
2638 struct fw_iso_buffer *buffer,
2639 unsigned long payload)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002640{
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05002641 struct descriptor *d, *pd;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002642 dma_addr_t d_bus, page_bus;
2643 u32 z, header_z, rest;
David Moorebcee8932007-12-19 15:26:38 -05002644 int i, j, length;
2645 int page, offset, packet_count, header_size, payload_per_buffer;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002646
2647 /*
David Moore1aa292b2008-07-22 23:23:40 -07002648 * The OHCI controller puts the isochronous header and trailer in the
2649 * buffer, so we need at least 8 bytes.
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002650 */
Stefan Richter872e3302010-07-29 18:19:22 +02002651 packet_count = packet->header_length / ctx->base.header_size;
David Moore1aa292b2008-07-22 23:23:40 -07002652 header_size = max(ctx->base.header_size, (size_t)8);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002653
2654 /* Get header size in number of descriptors. */
2655 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2656 page = payload >> PAGE_SHIFT;
2657 offset = payload & ~PAGE_MASK;
Stefan Richter872e3302010-07-29 18:19:22 +02002658 payload_per_buffer = packet->payload_length / packet_count;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002659
2660 for (i = 0; i < packet_count; i++) {
2661 /* d points to the header descriptor */
David Moorebcee8932007-12-19 15:26:38 -05002662 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002663 d = context_get_descriptors(&ctx->context,
David Moorebcee8932007-12-19 15:26:38 -05002664 z + header_z, &d_bus);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002665 if (d == NULL)
2666 return -ENOMEM;
2667
David Moorebcee8932007-12-19 15:26:38 -05002668 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2669 DESCRIPTOR_INPUT_MORE);
Stefan Richter872e3302010-07-29 18:19:22 +02002670 if (packet->skip && i == 0)
David Moorebcee8932007-12-19 15:26:38 -05002671 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002672 d->req_count = cpu_to_le16(header_size);
2673 d->res_count = d->req_count;
David Moorebcee8932007-12-19 15:26:38 -05002674 d->transfer_status = 0;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002675 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2676
David Moorebcee8932007-12-19 15:26:38 -05002677 rest = payload_per_buffer;
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05002678 pd = d;
David Moorebcee8932007-12-19 15:26:38 -05002679 for (j = 1; j < z; j++) {
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05002680 pd++;
David Moorebcee8932007-12-19 15:26:38 -05002681 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2682 DESCRIPTOR_INPUT_MORE);
2683
2684 if (offset + rest < PAGE_SIZE)
2685 length = rest;
2686 else
2687 length = PAGE_SIZE - offset;
2688 pd->req_count = cpu_to_le16(length);
2689 pd->res_count = pd->req_count;
2690 pd->transfer_status = 0;
2691
2692 page_bus = page_private(buffer->pages[page]);
2693 pd->data_address = cpu_to_le32(page_bus + offset);
2694
2695 offset = (offset + length) & ~PAGE_MASK;
2696 rest -= length;
2697 if (offset == 0)
2698 page++;
2699 }
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002700 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2701 DESCRIPTOR_INPUT_LAST |
2702 DESCRIPTOR_BRANCH_ALWAYS);
Stefan Richter872e3302010-07-29 18:19:22 +02002703 if (packet->interrupt && i == packet_count - 1)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002704 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2705
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002706 context_append(&ctx->context, d, z, header_z);
2707 }
2708
2709 return 0;
2710}
2711
Stefan Richter872e3302010-07-29 18:19:22 +02002712static int queue_iso_buffer_fill(struct iso_context *ctx,
2713 struct fw_iso_packet *packet,
2714 struct fw_iso_buffer *buffer,
2715 unsigned long payload)
2716{
2717 struct descriptor *d;
2718 dma_addr_t d_bus, page_bus;
2719 int page, offset, rest, z, i, length;
2720
2721 page = payload >> PAGE_SHIFT;
2722 offset = payload & ~PAGE_MASK;
2723 rest = packet->payload_length;
2724
2725 /* We need one descriptor for each page in the buffer. */
2726 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2727
2728 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2729 return -EFAULT;
2730
2731 for (i = 0; i < z; i++) {
2732 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2733 if (d == NULL)
2734 return -ENOMEM;
2735
2736 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2737 DESCRIPTOR_BRANCH_ALWAYS);
2738 if (packet->skip && i == 0)
2739 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2740 if (packet->interrupt && i == z - 1)
2741 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2742
2743 if (offset + rest < PAGE_SIZE)
2744 length = rest;
2745 else
2746 length = PAGE_SIZE - offset;
2747 d->req_count = cpu_to_le16(length);
2748 d->res_count = d->req_count;
2749 d->transfer_status = 0;
2750
2751 page_bus = page_private(buffer->pages[page]);
2752 d->data_address = cpu_to_le32(page_bus + offset);
2753
2754 rest -= length;
2755 offset = 0;
2756 page++;
2757
2758 context_append(&ctx->context, d, 1, 0);
2759 }
2760
2761 return 0;
2762}
2763
Stefan Richter53dca512008-12-14 21:47:04 +01002764static int ohci_queue_iso(struct fw_iso_context *base,
2765 struct fw_iso_packet *packet,
2766 struct fw_iso_buffer *buffer,
2767 unsigned long payload)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002768{
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002769 struct iso_context *ctx = container_of(base, struct iso_context, base);
David Moorefe5ca632008-01-06 17:21:41 -05002770 unsigned long flags;
Stefan Richter872e3302010-07-29 18:19:22 +02002771 int ret = -ENOSYS;
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002772
David Moorefe5ca632008-01-06 17:21:41 -05002773 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02002774 switch (base->type) {
2775 case FW_ISO_CONTEXT_TRANSMIT:
2776 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2777 break;
2778 case FW_ISO_CONTEXT_RECEIVE:
2779 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2780 break;
2781 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2782 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2783 break;
2784 }
David Moorefe5ca632008-01-06 17:21:41 -05002785 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2786
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002787 return ret;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002788}
2789
Stefan Richter21ebcd12007-01-14 15:29:07 +01002790static const struct fw_card_driver ohci_driver = {
Kristian Høgsberged568912006-12-19 19:58:35 -05002791 .enable = ohci_enable,
Stefan Richter02d37be2010-07-08 16:09:06 +02002792 .read_phy_reg = ohci_read_phy_reg,
Kristian Høgsberged568912006-12-19 19:58:35 -05002793 .update_phy_reg = ohci_update_phy_reg,
2794 .set_config_rom = ohci_set_config_rom,
2795 .send_request = ohci_send_request,
2796 .send_response = ohci_send_response,
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002797 .cancel_packet = ohci_cancel_packet,
Kristian Høgsberged568912006-12-19 19:58:35 -05002798 .enable_phys_dma = ohci_enable_phys_dma,
Stefan Richter0fcff4e2010-06-12 20:35:52 +02002799 .read_csr = ohci_read_csr,
2800 .write_csr = ohci_write_csr,
Kristian Høgsberged568912006-12-19 19:58:35 -05002801
2802 .allocate_iso_context = ohci_allocate_iso_context,
2803 .free_iso_context = ohci_free_iso_context,
Stefan Richter872e3302010-07-29 18:19:22 +02002804 .set_iso_channels = ohci_set_iso_channels,
Kristian Høgsberged568912006-12-19 19:58:35 -05002805 .queue_iso = ohci_queue_iso,
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05002806 .start_iso = ohci_start_iso,
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002807 .stop_iso = ohci_stop_iso,
Kristian Høgsberged568912006-12-19 19:58:35 -05002808};
2809
Stefan Richter2ed0f182008-03-01 12:35:29 +01002810#ifdef CONFIG_PPC_PMAC
Stefan Richter5da3dac2010-04-02 14:05:02 +02002811static void pmac_ohci_on(struct pci_dev *dev)
Stefan Richter2ed0f182008-03-01 12:35:29 +01002812{
2813 if (machine_is(powermac)) {
2814 struct device_node *ofn = pci_device_to_OF_node(dev);
2815
2816 if (ofn) {
2817 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2818 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2819 }
2820 }
2821}
2822
Stefan Richter5da3dac2010-04-02 14:05:02 +02002823static void pmac_ohci_off(struct pci_dev *dev)
Stefan Richter2ed0f182008-03-01 12:35:29 +01002824{
2825 if (machine_is(powermac)) {
2826 struct device_node *ofn = pci_device_to_OF_node(dev);
2827
2828 if (ofn) {
2829 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2830 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2831 }
2832 }
2833}
2834#else
Stefan Richter5da3dac2010-04-02 14:05:02 +02002835static inline void pmac_ohci_on(struct pci_dev *dev) {}
2836static inline void pmac_ohci_off(struct pci_dev *dev) {}
Stefan Richter2ed0f182008-03-01 12:35:29 +01002837#endif /* CONFIG_PPC_PMAC */
2838
Stefan Richter53dca512008-12-14 21:47:04 +01002839static int __devinit pci_probe(struct pci_dev *dev,
2840 const struct pci_device_id *ent)
Kristian Høgsberged568912006-12-19 19:58:35 -05002841{
2842 struct fw_ohci *ohci;
Clemens Ladisch54672382010-04-01 16:43:59 +02002843 u32 bus_options, max_receive, link_speed, version, link_enh;
Kristian Høgsberged568912006-12-19 19:58:35 -05002844 u64 guid;
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01002845 int i, err, n_ir, n_it;
Kristian Høgsberged568912006-12-19 19:58:35 -05002846 size_t size;
2847
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002848 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
Kristian Høgsberged568912006-12-19 19:58:35 -05002849 if (ohci == NULL) {
Stefan Richter7007a072008-10-26 09:50:31 +01002850 err = -ENOMEM;
2851 goto fail;
Kristian Høgsberged568912006-12-19 19:58:35 -05002852 }
2853
2854 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2855
Stefan Richter5da3dac2010-04-02 14:05:02 +02002856 pmac_ohci_on(dev);
Stefan Richter130d5492008-03-24 20:55:28 +01002857
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002858 err = pci_enable_device(dev);
2859 if (err) {
Stefan Richter7007a072008-10-26 09:50:31 +01002860 fw_error("Failed to enable OHCI hardware\n");
Stefan Richterbd7dee62008-02-24 18:59:55 +01002861 goto fail_free;
Kristian Høgsberged568912006-12-19 19:58:35 -05002862 }
2863
2864 pci_set_master(dev);
2865 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2866 pci_set_drvdata(dev, ohci);
2867
2868 spin_lock_init(&ohci->lock);
Stefan Richter02d37be2010-07-08 16:09:06 +02002869 mutex_init(&ohci->phy_reg_mutex);
Kristian Høgsberged568912006-12-19 19:58:35 -05002870
2871 tasklet_init(&ohci->bus_reset_tasklet,
2872 bus_reset_tasklet, (unsigned long)ohci);
2873
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002874 err = pci_request_region(dev, 0, ohci_driver_name);
2875 if (err) {
Kristian Høgsberged568912006-12-19 19:58:35 -05002876 fw_error("MMIO resource unavailable\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002877 goto fail_disable;
Kristian Høgsberged568912006-12-19 19:58:35 -05002878 }
2879
2880 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2881 if (ohci->registers == NULL) {
2882 fw_error("Failed to remap registers\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002883 err = -ENXIO;
2884 goto fail_iomem;
Kristian Høgsberged568912006-12-19 19:58:35 -05002885 }
2886
Stefan Richter4a635592010-02-21 17:58:01 +01002887 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2888 if (ohci_quirks[i].vendor == dev->vendor &&
2889 (ohci_quirks[i].device == dev->device ||
2890 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2891 ohci->quirks = ohci_quirks[i].flags;
2892 break;
2893 }
Stefan Richter3e9cc2f2010-02-21 17:58:29 +01002894 if (param_quirks)
2895 ohci->quirks = param_quirks;
Clemens Ladischb6775322010-01-20 09:58:02 +01002896
Clemens Ladisch54672382010-04-01 16:43:59 +02002897 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2898 if (dev->vendor == PCI_VENDOR_ID_TI) {
2899 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2900
2901 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2902 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2903 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2904
2905 /* use priority arbitration for asynchronous responses */
2906 link_enh |= TI_LinkEnh_enab_unfair;
2907
2908 /* required for aPhyEnhanceEnable to work */
2909 link_enh |= TI_LinkEnh_enab_accel;
2910
2911 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2912 }
2913
Kristian Høgsberged568912006-12-19 19:58:35 -05002914 ar_context_init(&ohci->ar_request_ctx, ohci,
2915 OHCI1394_AsReqRcvContextControlSet);
2916
2917 ar_context_init(&ohci->ar_response_ctx, ohci,
2918 OHCI1394_AsRspRcvContextControlSet);
2919
David Moorefe5ca632008-01-06 17:21:41 -05002920 context_init(&ohci->at_request_ctx, ohci,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002921 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05002922
David Moorefe5ca632008-01-06 17:21:41 -05002923 context_init(&ohci->at_response_ctx, ohci,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002924 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05002925
Kristian Høgsberged568912006-12-19 19:58:35 -05002926 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
Stefan Richter4817ed22008-12-21 16:39:46 +01002927 ohci->ir_context_channels = ~0ULL;
Stefan Richter4802f162010-02-21 17:58:52 +01002928 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2929 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01002930 n_ir = hweight32(ohci->ir_context_mask);
2931 size = sizeof(struct iso_context) * n_ir;
Kristian Høgsberged568912006-12-19 19:58:35 -05002932 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2933
Stefan Richter4802f162010-02-21 17:58:52 +01002934 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2935 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2936 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01002937 n_it = hweight32(ohci->it_context_mask);
2938 size = sizeof(struct iso_context) * n_it;
Stefan Richter4802f162010-02-21 17:58:52 +01002939 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2940
Kristian Høgsberged568912006-12-19 19:58:35 -05002941 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002942 err = -ENOMEM;
Stefan Richter7007a072008-10-26 09:50:31 +01002943 goto fail_contexts;
Kristian Høgsberged568912006-12-19 19:58:35 -05002944 }
2945
2946 /* self-id dma buffer allocation */
2947 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2948 SELF_ID_BUF_SIZE,
2949 &ohci->self_id_bus,
2950 GFP_KERNEL);
2951 if (ohci->self_id_cpu == NULL) {
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002952 err = -ENOMEM;
Stefan Richter7007a072008-10-26 09:50:31 +01002953 goto fail_contexts;
Kristian Høgsberged568912006-12-19 19:58:35 -05002954 }
2955
Kristian Høgsberged568912006-12-19 19:58:35 -05002956 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2957 max_receive = (bus_options >> 12) & 0xf;
2958 link_speed = bus_options & 0x7;
2959 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2960 reg_read(ohci, OHCI1394_GUIDLo);
2961
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002962 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
Stefan Richtere1eff7a2009-02-03 17:55:19 +01002963 if (err)
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002964 goto fail_self_id;
Kristian Høgsberged568912006-12-19 19:58:35 -05002965
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01002966 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2967 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2968 "%d IR + %d IT contexts, quirks 0x%x\n",
2969 dev_name(&dev->dev), version >> 16, version & 0xff,
2970 n_ir, n_it, ohci->quirks);
Stefan Richtere1eff7a2009-02-03 17:55:19 +01002971
Kristian Høgsberged568912006-12-19 19:58:35 -05002972 return 0;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002973
2974 fail_self_id:
2975 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2976 ohci->self_id_cpu, ohci->self_id_bus);
Stefan Richter7007a072008-10-26 09:50:31 +01002977 fail_contexts:
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002978 kfree(ohci->ir_context_list);
Stefan Richter7007a072008-10-26 09:50:31 +01002979 kfree(ohci->it_context_list);
2980 context_release(&ohci->at_response_ctx);
2981 context_release(&ohci->at_request_ctx);
2982 ar_context_release(&ohci->ar_response_ctx);
2983 ar_context_release(&ohci->ar_request_ctx);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002984 pci_iounmap(dev, ohci->registers);
2985 fail_iomem:
2986 pci_release_region(dev, 0);
2987 fail_disable:
2988 pci_disable_device(dev);
Stefan Richterbd7dee62008-02-24 18:59:55 +01002989 fail_free:
2990 kfree(&ohci->card);
Stefan Richter5da3dac2010-04-02 14:05:02 +02002991 pmac_ohci_off(dev);
Stefan Richter7007a072008-10-26 09:50:31 +01002992 fail:
2993 if (err == -ENOMEM)
2994 fw_error("Out of memory\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002995
2996 return err;
Kristian Høgsberged568912006-12-19 19:58:35 -05002997}
2998
2999static void pci_remove(struct pci_dev *dev)
3000{
3001 struct fw_ohci *ohci;
3002
3003 ohci = pci_get_drvdata(dev);
Kristian Høgsberge254a4b2007-03-07 12:12:38 -05003004 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3005 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05003006 fw_core_remove_card(&ohci->card);
3007
Kristian Høgsbergc781c062007-05-07 20:33:32 -04003008 /*
3009 * FIXME: Fail all pending packets here, now that the upper
3010 * layers can't queue any more.
3011 */
Kristian Høgsberged568912006-12-19 19:58:35 -05003012
3013 software_reset(ohci);
3014 free_irq(dev->irq, ohci);
Jay Fenlasona55709b2008-10-22 15:59:42 -04003015
3016 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3017 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3018 ohci->next_config_rom, ohci->next_config_rom_bus);
3019 if (ohci->config_rom)
3020 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3021 ohci->config_rom, ohci->config_rom_bus);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003022 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3023 ohci->self_id_cpu, ohci->self_id_bus);
Jay Fenlasona55709b2008-10-22 15:59:42 -04003024 ar_context_release(&ohci->ar_request_ctx);
3025 ar_context_release(&ohci->ar_response_ctx);
3026 context_release(&ohci->at_request_ctx);
3027 context_release(&ohci->at_response_ctx);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003028 kfree(ohci->it_context_list);
3029 kfree(ohci->ir_context_list);
Clemens Ladisch262444e2010-06-05 12:31:25 +02003030 pci_disable_msi(dev);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003031 pci_iounmap(dev, ohci->registers);
3032 pci_release_region(dev, 0);
3033 pci_disable_device(dev);
Stefan Richterbd7dee62008-02-24 18:59:55 +01003034 kfree(&ohci->card);
Stefan Richter5da3dac2010-04-02 14:05:02 +02003035 pmac_ohci_off(dev);
Stefan Richterea8d0062008-03-01 02:42:56 +01003036
Kristian Høgsberged568912006-12-19 19:58:35 -05003037 fw_notify("Removed fw-ohci device.\n");
3038}
3039
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003040#ifdef CONFIG_PM
Stefan Richter2ed0f182008-03-01 12:35:29 +01003041static int pci_suspend(struct pci_dev *dev, pm_message_t state)
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003042{
Stefan Richter2ed0f182008-03-01 12:35:29 +01003043 struct fw_ohci *ohci = pci_get_drvdata(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003044 int err;
3045
3046 software_reset(ohci);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003047 free_irq(dev->irq, ohci);
Clemens Ladisch262444e2010-06-05 12:31:25 +02003048 pci_disable_msi(dev);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003049 err = pci_save_state(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003050 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02003051 fw_error("pci_save_state failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003052 return err;
3053 }
Stefan Richter2ed0f182008-03-01 12:35:29 +01003054 err = pci_set_power_state(dev, pci_choose_state(dev, state));
Stefan Richter55111422007-09-06 09:50:30 +02003055 if (err)
3056 fw_error("pci_set_power_state failed with %d\n", err);
Stefan Richter5da3dac2010-04-02 14:05:02 +02003057 pmac_ohci_off(dev);
Stefan Richterea8d0062008-03-01 02:42:56 +01003058
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003059 return 0;
3060}
3061
Stefan Richter2ed0f182008-03-01 12:35:29 +01003062static int pci_resume(struct pci_dev *dev)
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003063{
Stefan Richter2ed0f182008-03-01 12:35:29 +01003064 struct fw_ohci *ohci = pci_get_drvdata(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003065 int err;
3066
Stefan Richter5da3dac2010-04-02 14:05:02 +02003067 pmac_ohci_on(dev);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003068 pci_set_power_state(dev, PCI_D0);
3069 pci_restore_state(dev);
3070 err = pci_enable_device(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003071 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02003072 fw_error("pci_enable_device failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003073 return err;
3074 }
3075
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04003076 return ohci_enable(&ohci->card, NULL, 0);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003077}
3078#endif
3079
Németh Mártona67483d2010-01-10 13:14:26 +01003080static const struct pci_device_id pci_table[] = {
Kristian Høgsberged568912006-12-19 19:58:35 -05003081 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3082 { }
3083};
3084
3085MODULE_DEVICE_TABLE(pci, pci_table);
3086
3087static struct pci_driver fw_ohci_pci_driver = {
3088 .name = ohci_driver_name,
3089 .id_table = pci_table,
3090 .probe = pci_probe,
3091 .remove = pci_remove,
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003092#ifdef CONFIG_PM
3093 .resume = pci_resume,
3094 .suspend = pci_suspend,
3095#endif
Kristian Høgsberged568912006-12-19 19:58:35 -05003096};
3097
3098MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3099MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3100MODULE_LICENSE("GPL");
3101
Olaf Hering1e4c7b02007-05-05 23:17:13 +02003102/* Provide a module alias so root-on-sbp2 initrds don't break. */
3103#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3104MODULE_ALIAS("ohci1394");
3105#endif
3106
Kristian Høgsberged568912006-12-19 19:58:35 -05003107static int __init fw_ohci_init(void)
3108{
3109 return pci_register_driver(&fw_ohci_pci_driver);
3110}
3111
3112static void __exit fw_ohci_cleanup(void)
3113{
3114 pci_unregister_driver(&fw_ohci_pci_driver);
3115}
3116
3117module_init(fw_ohci_init);
3118module_exit(fw_ohci_cleanup);