Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 ARM Ltd. |
| 3 | * Copyright (c) 2010 ST-Ericsson SA |
| 4 | * |
| 5 | * Author: Peter Pearse <peter.pearse@arm.com> |
| 6 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the Free |
| 10 | * Software Foundation; either version 2 of the License, or (at your option) |
| 11 | * any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 21 | * |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 22 | * The full GNU General Public License is in this distribution in the file |
| 23 | * called COPYING. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 24 | * |
| 25 | * Documentation: ARM DDI 0196G == PL080 |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 26 | * Documentation: ARM DDI 0218E == PL081 |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 27 | * Documentation: S3C6410 User's Manual == PL080S |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 28 | * |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 29 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
| 30 | * channel. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 31 | * |
| 32 | * The PL080 has 8 channels available for simultaneous use, and the PL081 |
| 33 | * has only two channels. So on these DMA controllers the number of channels |
| 34 | * and the number of incoming DMA signals are two totally different things. |
| 35 | * It is usually not possible to theoretically handle all physical signals, |
| 36 | * so a multiplexing scheme with possible denial of use is necessary. |
| 37 | * |
| 38 | * The PL080 has a dual bus master, PL081 has a single master. |
| 39 | * |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 40 | * PL080S is a version modified by Samsung and used in S3C64xx SoCs. |
| 41 | * It differs in following aspects: |
| 42 | * - CH_CONFIG register at different offset, |
| 43 | * - separate CH_CONTROL2 register for transfer size, |
| 44 | * - bigger maximum transfer size, |
| 45 | * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word, |
| 46 | * - no support for peripheral flow control. |
| 47 | * |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 48 | * Memory to peripheral transfer may be visualized as |
| 49 | * Get data from memory to DMAC |
| 50 | * Until no data left |
| 51 | * On burst request from peripheral |
| 52 | * Destination burst from DMAC to peripheral |
| 53 | * Clear burst request |
| 54 | * Raise terminal count interrupt |
| 55 | * |
| 56 | * For peripherals with a FIFO: |
| 57 | * Source burst size == half the depth of the peripheral FIFO |
| 58 | * Destination burst size == the depth of the peripheral FIFO |
| 59 | * |
| 60 | * (Bursts are irrelevant for mem to mem transfers - there are no burst |
| 61 | * signals, the DMA controller will simply facilitate its AHB master.) |
| 62 | * |
| 63 | * ASSUMES default (little) endianness for DMA transfers |
| 64 | * |
Russell King - ARM Linux | 9dc2c20 | 2011-01-03 22:33:06 +0000 | [diff] [blame] | 65 | * The PL08x has two flow control settings: |
| 66 | * - DMAC flow control: the transfer size defines the number of transfers |
| 67 | * which occur for the current LLI entry, and the DMAC raises TC at the |
| 68 | * end of every LLI entry. Observed behaviour shows the DMAC listening |
| 69 | * to both the BREQ and SREQ signals (contrary to documented), |
| 70 | * transferring data if either is active. The LBREQ and LSREQ signals |
| 71 | * are ignored. |
| 72 | * |
| 73 | * - Peripheral flow control: the transfer size is ignored (and should be |
| 74 | * zero). The data is transferred from the current LLI entry, until |
| 75 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 76 | * will then move to the next LLI entry. Unsupported by PL080S. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 77 | */ |
Russell King - ARM Linux | 730404a | 2011-01-03 22:34:07 +0000 | [diff] [blame] | 78 | #include <linux/amba/bus.h> |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 79 | #include <linux/amba/pl08x.h> |
| 80 | #include <linux/debugfs.h> |
Viresh Kumar | 0c38d70 | 2011-08-05 15:32:28 +0530 | [diff] [blame] | 81 | #include <linux/delay.h> |
| 82 | #include <linux/device.h> |
| 83 | #include <linux/dmaengine.h> |
| 84 | #include <linux/dmapool.h> |
Vinod Koul | 8516f52 | 2011-09-02 16:43:44 +0530 | [diff] [blame] | 85 | #include <linux/dma-mapping.h> |
Viresh Kumar | 0c38d70 | 2011-08-05 15:32:28 +0530 | [diff] [blame] | 86 | #include <linux/init.h> |
| 87 | #include <linux/interrupt.h> |
| 88 | #include <linux/module.h> |
Viresh Kumar | b7b6018 | 2011-08-05 15:32:33 +0530 | [diff] [blame] | 89 | #include <linux/pm_runtime.h> |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 90 | #include <linux/seq_file.h> |
Viresh Kumar | 0c38d70 | 2011-08-05 15:32:28 +0530 | [diff] [blame] | 91 | #include <linux/slab.h> |
Alessandro Rubini | 3a95b9f | 2012-11-24 00:22:56 +0000 | [diff] [blame] | 92 | #include <linux/amba/pl080.h> |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 93 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 94 | #include "dmaengine.h" |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 95 | #include "virt-dma.h" |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 96 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 97 | #define DRIVER_NAME "pl08xdmac" |
| 98 | |
Russell King - ARM Linux | 7703eac | 2011-08-31 09:34:35 +0100 | [diff] [blame] | 99 | static struct amba_driver pl08x_amba_driver; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 100 | struct pl08x_driver_data; |
Russell King - ARM Linux | 7703eac | 2011-08-31 09:34:35 +0100 | [diff] [blame] | 101 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 102 | /** |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 103 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 104 | * @channels: the number of channels available in this variant |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 105 | * @dualmaster: whether this version supports dual AHB masters or not. |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 106 | * @nomadik: whether the channels have Nomadik security extension bits |
| 107 | * that need to be checked for permission before use and some registers are |
| 108 | * missing |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 109 | * @pl080s: whether this version is a PL080S, which has separate register and |
| 110 | * LLI word for transfer size. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 111 | */ |
| 112 | struct vendor_data { |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 113 | u8 config_offset; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 114 | u8 channels; |
| 115 | bool dualmaster; |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 116 | bool nomadik; |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 117 | bool pl080s; |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 118 | u32 max_transfer_size; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 119 | }; |
| 120 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 121 | /** |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 122 | * struct pl08x_bus_data - information of source or destination |
| 123 | * busses for a transfer |
| 124 | * @addr: current address |
| 125 | * @maxwidth: the maximum width of a transfer on this bus |
| 126 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 |
| 127 | */ |
| 128 | struct pl08x_bus_data { |
| 129 | dma_addr_t addr; |
| 130 | u8 maxwidth; |
| 131 | u8 buswidth; |
| 132 | }; |
| 133 | |
| 134 | /** |
| 135 | * struct pl08x_phy_chan - holder for the physical channels |
| 136 | * @id: physical index to this channel |
| 137 | * @lock: a lock to use when altering an instance of this struct |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 138 | * @serving: the virtual channel currently being served by this physical |
| 139 | * channel |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 140 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
| 141 | * world |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 142 | */ |
| 143 | struct pl08x_phy_chan { |
| 144 | unsigned int id; |
| 145 | void __iomem *base; |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 146 | void __iomem *reg_config; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 147 | spinlock_t lock; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 148 | struct pl08x_dma_chan *serving; |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 149 | bool locked; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | /** |
| 153 | * struct pl08x_sg - structure containing data per sg |
| 154 | * @src_addr: src address of sg |
| 155 | * @dst_addr: dst address of sg |
| 156 | * @len: transfer len in bytes |
| 157 | * @node: node for txd's dsg_list |
| 158 | */ |
| 159 | struct pl08x_sg { |
| 160 | dma_addr_t src_addr; |
| 161 | dma_addr_t dst_addr; |
| 162 | size_t len; |
| 163 | struct list_head node; |
| 164 | }; |
| 165 | |
| 166 | /** |
| 167 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 168 | * @vd: virtual DMA descriptor |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 169 | * @dsg_list: list of children sg's |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 170 | * @llis_bus: DMA memory address (physical) start for the LLIs |
| 171 | * @llis_va: virtual memory address start for the LLIs |
| 172 | * @cctl: control reg values for current txd |
| 173 | * @ccfg: config reg values for current txd |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 174 | * @done: this marks completed descriptors, which should not have their |
| 175 | * mux released. |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 176 | */ |
| 177 | struct pl08x_txd { |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 178 | struct virt_dma_desc vd; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 179 | struct list_head dsg_list; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 180 | dma_addr_t llis_bus; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 181 | u32 *llis_va; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 182 | /* Default cctl value for LLIs */ |
| 183 | u32 cctl; |
| 184 | /* |
| 185 | * Settings to be put into the physical channel when we |
| 186 | * trigger this txd. Other registers are in llis_va[0]. |
| 187 | */ |
| 188 | u32 ccfg; |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 189 | bool done; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | /** |
| 193 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel |
| 194 | * states |
| 195 | * @PL08X_CHAN_IDLE: the channel is idle |
| 196 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport |
| 197 | * channel and is running a transfer on it |
| 198 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport |
| 199 | * channel, but the transfer is currently paused |
| 200 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport |
| 201 | * channel to become available (only pertains to memcpy channels) |
| 202 | */ |
| 203 | enum pl08x_dma_chan_state { |
| 204 | PL08X_CHAN_IDLE, |
| 205 | PL08X_CHAN_RUNNING, |
| 206 | PL08X_CHAN_PAUSED, |
| 207 | PL08X_CHAN_WAITING, |
| 208 | }; |
| 209 | |
| 210 | /** |
| 211 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 212 | * @vc: wrappped virtual channel |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 213 | * @phychan: the physical channel utilized by this channel, if there is one |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 214 | * @name: name of channel |
| 215 | * @cd: channel platform data |
| 216 | * @runtime_addr: address for RX/TX according to the runtime config |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 217 | * @at: active transaction on this channel |
| 218 | * @lock: a lock for this channel data |
| 219 | * @host: a pointer to the host (internal use) |
| 220 | * @state: whether the channel is idle, paused, running etc |
| 221 | * @slave: whether this channel is a device (slave) or for memcpy |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 222 | * @signal: the physical DMA request signal which this channel is using |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 223 | * @mux_use: count of descriptors using this DMA request signal setting |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 224 | */ |
| 225 | struct pl08x_dma_chan { |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 226 | struct virt_dma_chan vc; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 227 | struct pl08x_phy_chan *phychan; |
Russell King | 550ec36 | 2012-05-28 10:18:55 +0100 | [diff] [blame] | 228 | const char *name; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 229 | const struct pl08x_channel_data *cd; |
Russell King | ed91c13 | 2012-05-16 11:02:40 +0100 | [diff] [blame] | 230 | struct dma_slave_config cfg; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 231 | struct pl08x_txd *at; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 232 | struct pl08x_driver_data *host; |
| 233 | enum pl08x_dma_chan_state state; |
| 234 | bool slave; |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 235 | int signal; |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 236 | unsigned mux_use; |
Russell King | b23f204 | 2012-05-16 10:48:44 +0100 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | /** |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 240 | * struct pl08x_driver_data - the local state holder for the PL08x |
| 241 | * @slave: slave engine for this instance |
| 242 | * @memcpy: memcpy engine for this instance |
| 243 | * @base: virtual memory base (remapped) for the PL08x |
| 244 | * @adev: the corresponding AMBA (PrimeCell) bus entry |
| 245 | * @vd: vendor data for this PL08x variant |
| 246 | * @pd: platform data passed in from the platform/machine |
| 247 | * @phy_chans: array of data for the physical channels |
| 248 | * @pool: a pool for the LLI descriptors |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 249 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
| 250 | * fetches |
Russell King - ARM Linux | 30749cb | 2011-01-03 22:41:13 +0000 | [diff] [blame] | 251 | * @mem_buses: set to indicate memory transfers on AHB2. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 252 | * @lock: a spinlock for this struct |
| 253 | */ |
| 254 | struct pl08x_driver_data { |
| 255 | struct dma_device slave; |
| 256 | struct dma_device memcpy; |
| 257 | void __iomem *base; |
| 258 | struct amba_device *adev; |
Russell King - ARM Linux | f96ca9ec | 2011-01-03 22:35:08 +0000 | [diff] [blame] | 259 | const struct vendor_data *vd; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 260 | struct pl08x_platform_data *pd; |
| 261 | struct pl08x_phy_chan *phy_chans; |
| 262 | struct dma_pool *pool; |
Russell King - ARM Linux | 30749cb | 2011-01-03 22:41:13 +0000 | [diff] [blame] | 263 | u8 lli_buses; |
| 264 | u8 mem_buses; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 265 | u8 lli_words; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | /* |
| 269 | * PL08X specific defines |
| 270 | */ |
| 271 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 272 | /* The order of words in an LLI. */ |
| 273 | #define PL080_LLI_SRC 0 |
| 274 | #define PL080_LLI_DST 1 |
| 275 | #define PL080_LLI_LLI 2 |
| 276 | #define PL080_LLI_CCTL 3 |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 277 | #define PL080S_LLI_CCTL2 4 |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 278 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 279 | /* Total words in an LLI. */ |
| 280 | #define PL080_LLI_WORDS 4 |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 281 | #define PL080S_LLI_WORDS 8 |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 282 | |
| 283 | /* |
| 284 | * Number of LLIs in each LLI buffer allocated for one transfer |
| 285 | * (maximum times we call dma_pool_alloc on this pool without freeing) |
| 286 | */ |
| 287 | #define MAX_NUM_TSFR_LLIS 512 |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 288 | #define PL08X_ALIGN 8 |
| 289 | |
| 290 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) |
| 291 | { |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 292 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 293 | } |
| 294 | |
Russell King - ARM Linux | 501e67e | 2011-01-03 22:44:57 +0000 | [diff] [blame] | 295 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
| 296 | { |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 297 | return container_of(tx, struct pl08x_txd, vd.tx); |
Russell King - ARM Linux | 501e67e | 2011-01-03 22:44:57 +0000 | [diff] [blame] | 298 | } |
| 299 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 300 | /* |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 301 | * Mux handling. |
| 302 | * |
| 303 | * This gives us the DMA request input to the PL08x primecell which the |
| 304 | * peripheral described by the channel data will be routed to, possibly |
| 305 | * via a board/SoC specific external MUX. One important point to note |
| 306 | * here is that this does not depend on the physical channel. |
| 307 | */ |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 308 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 309 | { |
| 310 | const struct pl08x_platform_data *pd = plchan->host->pd; |
| 311 | int ret; |
| 312 | |
Mark Brown | d7cabee | 2013-06-19 20:38:28 +0100 | [diff] [blame] | 313 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
| 314 | ret = pd->get_xfer_signal(plchan->cd); |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 315 | if (ret < 0) { |
| 316 | plchan->mux_use = 0; |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 317 | return ret; |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 318 | } |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 319 | |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 320 | plchan->signal = ret; |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 321 | } |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) |
| 326 | { |
| 327 | const struct pl08x_platform_data *pd = plchan->host->pd; |
| 328 | |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 329 | if (plchan->signal >= 0) { |
| 330 | WARN_ON(plchan->mux_use == 0); |
| 331 | |
Mark Brown | d7cabee | 2013-06-19 20:38:28 +0100 | [diff] [blame] | 332 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
| 333 | pd->put_xfer_signal(plchan->cd, plchan->signal); |
Russell King | 5e2479b | 2012-05-25 11:32:45 +0100 | [diff] [blame] | 334 | plchan->signal = -1; |
| 335 | } |
Russell King | 6b16c8b | 2012-05-25 11:10:58 +0100 | [diff] [blame] | 336 | } |
| 337 | } |
| 338 | |
| 339 | /* |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 340 | * Physical channel handling |
| 341 | */ |
| 342 | |
| 343 | /* Whether a certain channel is busy or not */ |
| 344 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) |
| 345 | { |
| 346 | unsigned int val; |
| 347 | |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 348 | val = readl(ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 349 | return val & PL080_CONFIG_ACTIVE; |
| 350 | } |
| 351 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 352 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
| 353 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) |
| 354 | { |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 355 | if (pl08x->vd->pl080s) |
| 356 | dev_vdbg(&pl08x->adev->dev, |
| 357 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " |
| 358 | "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n", |
| 359 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], |
| 360 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], |
| 361 | lli[PL080S_LLI_CCTL2], ccfg); |
| 362 | else |
| 363 | dev_vdbg(&pl08x->adev->dev, |
| 364 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " |
| 365 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
| 366 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], |
| 367 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 368 | |
| 369 | writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR); |
| 370 | writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR); |
| 371 | writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI); |
| 372 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL); |
| 373 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 374 | if (pl08x->vd->pl080s) |
| 375 | writel_relaxed(lli[PL080S_LLI_CCTL2], |
| 376 | phychan->base + PL080S_CH_CONTROL2); |
| 377 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 378 | writel(ccfg, phychan->reg_config); |
| 379 | } |
| 380 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 381 | /* |
| 382 | * Set the initial DMA register values i.e. those for the first LLI |
Russell King - ARM Linux | e8b5e11 | 2011-01-03 22:30:24 +0000 | [diff] [blame] | 383 | * The next LLI pointer and the configuration interrupt bit have |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 384 | * been set when the LLIs were constructed. Poke them into the hardware |
| 385 | * and start the transfer. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 386 | */ |
Russell King | eab8253 | 2012-05-25 12:32:00 +0100 | [diff] [blame] | 387 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 388 | { |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 389 | struct pl08x_driver_data *pl08x = plchan->host; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 390 | struct pl08x_phy_chan *phychan = plchan->phychan; |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 391 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
| 392 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); |
Russell King - ARM Linux | 09b3c32 | 2011-01-03 22:39:53 +0000 | [diff] [blame] | 393 | u32 val; |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 394 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 395 | list_del(&txd->vd.node); |
Russell King | eab8253 | 2012-05-25 12:32:00 +0100 | [diff] [blame] | 396 | |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 397 | plchan->at = txd; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 398 | |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 399 | /* Wait for channel inactive */ |
| 400 | while (pl08x_phy_channel_busy(phychan)) |
Russell King - ARM Linux | 19386b32 | 2011-01-03 22:36:29 +0000 | [diff] [blame] | 401 | cpu_relax(); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 402 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 403 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 404 | |
| 405 | /* Enable the DMA channel */ |
| 406 | /* Do not access config register until channel shows as disabled */ |
| 407 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) |
| 408 | cpu_relax(); |
| 409 | |
| 410 | /* Do not access config register until channel shows as inactive */ |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 411 | val = readl(phychan->reg_config); |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 412 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 413 | val = readl(phychan->reg_config); |
Russell King - ARM Linux | c885bee | 2011-01-03 22:38:52 +0000 | [diff] [blame] | 414 | |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 415 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | /* |
Russell King - ARM Linux | 8179661 | 2011-01-27 12:37:44 +0000 | [diff] [blame] | 419 | * Pause the channel by setting the HALT bit. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 420 | * |
Russell King - ARM Linux | 8179661 | 2011-01-27 12:37:44 +0000 | [diff] [blame] | 421 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
| 422 | * the FIFO can only drain if the peripheral is still requesting data. |
| 423 | * (note: this can still timeout if the DMAC FIFO never drains of data.) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 424 | * |
Russell King - ARM Linux | 8179661 | 2011-01-27 12:37:44 +0000 | [diff] [blame] | 425 | * For P->M transfers, disable the peripheral first to stop it filling |
| 426 | * the DMAC FIFO, and then pause the DMAC. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 427 | */ |
| 428 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) |
| 429 | { |
| 430 | u32 val; |
Russell King - ARM Linux | 8179661 | 2011-01-27 12:37:44 +0000 | [diff] [blame] | 431 | int timeout; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 432 | |
| 433 | /* Set the HALT bit and wait for the FIFO to drain */ |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 434 | val = readl(ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 435 | val |= PL080_CONFIG_HALT; |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 436 | writel(val, ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 437 | |
| 438 | /* Wait for channel inactive */ |
Russell King - ARM Linux | 8179661 | 2011-01-27 12:37:44 +0000 | [diff] [blame] | 439 | for (timeout = 1000; timeout; timeout--) { |
| 440 | if (!pl08x_phy_channel_busy(ch)) |
| 441 | break; |
| 442 | udelay(1); |
| 443 | } |
| 444 | if (pl08x_phy_channel_busy(ch)) |
| 445 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) |
| 449 | { |
| 450 | u32 val; |
| 451 | |
| 452 | /* Clear the HALT bit */ |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 453 | val = readl(ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 454 | val &= ~PL080_CONFIG_HALT; |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 455 | writel(val, ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 456 | } |
| 457 | |
Russell King - ARM Linux | fb52621 | 2011-01-27 12:32:53 +0000 | [diff] [blame] | 458 | /* |
| 459 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and |
| 460 | * clears any pending interrupt status. This should not be used for |
| 461 | * an on-going transfer, but as a method of shutting down a channel |
| 462 | * (eg, when it's no longer used) or terminating a transfer. |
| 463 | */ |
| 464 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, |
| 465 | struct pl08x_phy_chan *ch) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 466 | { |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 467 | u32 val = readl(ch->reg_config); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 468 | |
Russell King - ARM Linux | fb52621 | 2011-01-27 12:32:53 +0000 | [diff] [blame] | 469 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
| 470 | PL080_CONFIG_TC_IRQ_MASK); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 471 | |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 472 | writel(val, ch->reg_config); |
Russell King - ARM Linux | fb52621 | 2011-01-27 12:32:53 +0000 | [diff] [blame] | 473 | |
| 474 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); |
| 475 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | static inline u32 get_bytes_in_cctl(u32 cctl) |
| 479 | { |
| 480 | /* The source width defines the number of bytes */ |
| 481 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; |
| 482 | |
Alban Bedel | f3287a5 | 2013-08-11 19:59:19 +0200 | [diff] [blame^] | 483 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
| 484 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 485 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
| 486 | case PL080_WIDTH_8BIT: |
| 487 | break; |
| 488 | case PL080_WIDTH_16BIT: |
| 489 | bytes *= 2; |
| 490 | break; |
| 491 | case PL080_WIDTH_32BIT: |
| 492 | bytes *= 4; |
| 493 | break; |
| 494 | } |
| 495 | return bytes; |
| 496 | } |
| 497 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 498 | static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) |
| 499 | { |
| 500 | /* The source width defines the number of bytes */ |
| 501 | u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK; |
| 502 | |
Alban Bedel | f3287a5 | 2013-08-11 19:59:19 +0200 | [diff] [blame^] | 503 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
| 504 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 505 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
| 506 | case PL080_WIDTH_8BIT: |
| 507 | break; |
| 508 | case PL080_WIDTH_16BIT: |
| 509 | bytes *= 2; |
| 510 | break; |
| 511 | case PL080_WIDTH_32BIT: |
| 512 | bytes *= 4; |
| 513 | break; |
| 514 | } |
| 515 | return bytes; |
| 516 | } |
| 517 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 518 | /* The channel should be paused when calling this */ |
| 519 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) |
| 520 | { |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 521 | struct pl08x_driver_data *pl08x = plchan->host; |
| 522 | const u32 *llis_va, *llis_va_limit; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 523 | struct pl08x_phy_chan *ch; |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 524 | dma_addr_t llis_bus; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 525 | struct pl08x_txd *txd; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 526 | u32 llis_max_words; |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 527 | size_t bytes; |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 528 | u32 clli; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 529 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 530 | ch = plchan->phychan; |
| 531 | txd = plchan->at; |
| 532 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 533 | if (!ch || !txd) |
| 534 | return 0; |
| 535 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 536 | /* |
Russell King - ARM Linux | db9f136 | 2011-01-03 22:38:32 +0000 | [diff] [blame] | 537 | * Follow the LLIs to get the number of remaining |
| 538 | * bytes in the currently active transaction. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 539 | */ |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 540 | clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 541 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 542 | /* First get the remaining bytes in the active transfer */ |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 543 | if (pl08x->vd->pl080s) |
| 544 | bytes = get_bytes_in_cctl_pl080s( |
| 545 | readl(ch->base + PL080_CH_CONTROL), |
| 546 | readl(ch->base + PL080S_CH_CONTROL2)); |
| 547 | else |
| 548 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 549 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 550 | if (!clli) |
| 551 | return bytes; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 552 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 553 | llis_va = txd->llis_va; |
| 554 | llis_bus = txd->llis_bus; |
| 555 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 556 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 557 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 558 | sizeof(u32) * llis_max_words); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 559 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 560 | /* |
| 561 | * Locate the next LLI - as this is an array, |
| 562 | * it's simple maths to find. |
| 563 | */ |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 564 | llis_va += (clli - llis_bus) / sizeof(u32); |
Russell King - ARM Linux | db9f136 | 2011-01-03 22:38:32 +0000 | [diff] [blame] | 565 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 566 | llis_va_limit = llis_va + llis_max_words; |
| 567 | |
| 568 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 569 | if (pl08x->vd->pl080s) |
| 570 | bytes += get_bytes_in_cctl_pl080s( |
| 571 | llis_va[PL080_LLI_CCTL], |
| 572 | llis_va[PL080S_LLI_CCTL2]); |
| 573 | else |
| 574 | bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]); |
Russell King - ARM Linux | db9f136 | 2011-01-03 22:38:32 +0000 | [diff] [blame] | 575 | |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 576 | /* |
| 577 | * A LLI pointer of 0 terminates the LLI list |
| 578 | */ |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 579 | if (!llis_va[PL080_LLI_LLI]) |
Tomasz Figa | 68a7faa | 2013-08-11 19:59:13 +0200 | [diff] [blame] | 580 | break; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 581 | } |
| 582 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 583 | return bytes; |
| 584 | } |
| 585 | |
| 586 | /* |
| 587 | * Allocate a physical channel for a virtual channel |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 588 | * |
| 589 | * Try to locate a physical channel to be used for this transfer. If all |
| 590 | * are taken return NULL and the requester will have to cope by using |
| 591 | * some fallback PIO mode or retrying later. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 592 | */ |
| 593 | static struct pl08x_phy_chan * |
| 594 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, |
| 595 | struct pl08x_dma_chan *virt_chan) |
| 596 | { |
| 597 | struct pl08x_phy_chan *ch = NULL; |
| 598 | unsigned long flags; |
| 599 | int i; |
| 600 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 601 | for (i = 0; i < pl08x->vd->channels; i++) { |
| 602 | ch = &pl08x->phy_chans[i]; |
| 603 | |
| 604 | spin_lock_irqsave(&ch->lock, flags); |
| 605 | |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 606 | if (!ch->locked && !ch->serving) { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 607 | ch->serving = virt_chan; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 608 | spin_unlock_irqrestore(&ch->lock, flags); |
| 609 | break; |
| 610 | } |
| 611 | |
| 612 | spin_unlock_irqrestore(&ch->lock, flags); |
| 613 | } |
| 614 | |
| 615 | if (i == pl08x->vd->channels) { |
| 616 | /* No physical channel available, cope with it */ |
| 617 | return NULL; |
| 618 | } |
| 619 | |
| 620 | return ch; |
| 621 | } |
| 622 | |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 623 | /* Mark the physical channel as free. Note, this write is atomic. */ |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 624 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
| 625 | struct pl08x_phy_chan *ch) |
| 626 | { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 627 | ch->serving = NULL; |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | /* |
| 631 | * Try to allocate a physical channel. When successful, assign it to |
| 632 | * this virtual channel, and initiate the next descriptor. The |
| 633 | * virtual channel lock must be held at this point. |
| 634 | */ |
| 635 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) |
| 636 | { |
| 637 | struct pl08x_driver_data *pl08x = plchan->host; |
| 638 | struct pl08x_phy_chan *ch; |
| 639 | |
| 640 | ch = pl08x_get_phy_channel(pl08x, plchan); |
| 641 | if (!ch) { |
| 642 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); |
| 643 | plchan->state = PL08X_CHAN_WAITING; |
| 644 | return; |
| 645 | } |
| 646 | |
| 647 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
| 648 | ch->id, plchan->name); |
| 649 | |
| 650 | plchan->phychan = ch; |
| 651 | plchan->state = PL08X_CHAN_RUNNING; |
| 652 | pl08x_start_next_txd(plchan); |
| 653 | } |
| 654 | |
| 655 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, |
| 656 | struct pl08x_dma_chan *plchan) |
| 657 | { |
| 658 | struct pl08x_driver_data *pl08x = plchan->host; |
| 659 | |
| 660 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", |
| 661 | ch->id, plchan->name); |
| 662 | |
| 663 | /* |
| 664 | * We do this without taking the lock; we're really only concerned |
| 665 | * about whether this pointer is NULL or not, and we're guaranteed |
| 666 | * that this will only be called when it _already_ is non-NULL. |
| 667 | */ |
| 668 | ch->serving = plchan; |
| 669 | plchan->phychan = ch; |
| 670 | plchan->state = PL08X_CHAN_RUNNING; |
| 671 | pl08x_start_next_txd(plchan); |
| 672 | } |
| 673 | |
| 674 | /* |
| 675 | * Free a physical DMA channel, potentially reallocating it to another |
| 676 | * virtual channel if we have any pending. |
| 677 | */ |
| 678 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) |
| 679 | { |
| 680 | struct pl08x_driver_data *pl08x = plchan->host; |
| 681 | struct pl08x_dma_chan *p, *next; |
| 682 | |
| 683 | retry: |
| 684 | next = NULL; |
| 685 | |
| 686 | /* Find a waiting virtual channel for the next transfer. */ |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 687 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 688 | if (p->state == PL08X_CHAN_WAITING) { |
| 689 | next = p; |
| 690 | break; |
| 691 | } |
| 692 | |
| 693 | if (!next) { |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 694 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 695 | if (p->state == PL08X_CHAN_WAITING) { |
| 696 | next = p; |
| 697 | break; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | /* Ensure that the physical channel is stopped */ |
| 702 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); |
| 703 | |
| 704 | if (next) { |
| 705 | bool success; |
| 706 | |
| 707 | /* |
| 708 | * Eww. We know this isn't going to deadlock |
| 709 | * but lockdep probably doesn't. |
| 710 | */ |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 711 | spin_lock(&next->vc.lock); |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 712 | /* Re-check the state now that we have the lock */ |
| 713 | success = next->state == PL08X_CHAN_WAITING; |
| 714 | if (success) |
| 715 | pl08x_phy_reassign_start(plchan->phychan, next); |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 716 | spin_unlock(&next->vc.lock); |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 717 | |
| 718 | /* If the state changed, try to find another channel */ |
| 719 | if (!success) |
| 720 | goto retry; |
| 721 | } else { |
| 722 | /* No more jobs, so free up the physical channel */ |
| 723 | pl08x_put_phy_channel(pl08x, plchan->phychan); |
| 724 | } |
| 725 | |
| 726 | plchan->phychan = NULL; |
| 727 | plchan->state = PL08X_CHAN_IDLE; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | /* |
| 731 | * LLI handling |
| 732 | */ |
| 733 | |
| 734 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) |
| 735 | { |
| 736 | switch (coded) { |
| 737 | case PL080_WIDTH_8BIT: |
| 738 | return 1; |
| 739 | case PL080_WIDTH_16BIT: |
| 740 | return 2; |
| 741 | case PL080_WIDTH_32BIT: |
| 742 | return 4; |
| 743 | default: |
| 744 | break; |
| 745 | } |
| 746 | BUG(); |
| 747 | return 0; |
| 748 | } |
| 749 | |
| 750 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, |
Russell King - ARM Linux | cace658 | 2011-01-03 22:37:31 +0000 | [diff] [blame] | 751 | size_t tsize) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 752 | { |
| 753 | u32 retbits = cctl; |
| 754 | |
Russell King - ARM Linux | e8b5e11 | 2011-01-03 22:30:24 +0000 | [diff] [blame] | 755 | /* Remove all src, dst and transfer size bits */ |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 756 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
| 757 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; |
| 758 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; |
| 759 | |
| 760 | /* Then set the bits according to the parameters */ |
| 761 | switch (srcwidth) { |
| 762 | case 1: |
| 763 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; |
| 764 | break; |
| 765 | case 2: |
| 766 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; |
| 767 | break; |
| 768 | case 4: |
| 769 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; |
| 770 | break; |
| 771 | default: |
| 772 | BUG(); |
| 773 | break; |
| 774 | } |
| 775 | |
| 776 | switch (dstwidth) { |
| 777 | case 1: |
| 778 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; |
| 779 | break; |
| 780 | case 2: |
| 781 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; |
| 782 | break; |
| 783 | case 4: |
| 784 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; |
| 785 | break; |
| 786 | default: |
| 787 | BUG(); |
| 788 | break; |
| 789 | } |
| 790 | |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 791 | tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 792 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; |
| 793 | return retbits; |
| 794 | } |
| 795 | |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 796 | struct pl08x_lli_build_data { |
| 797 | struct pl08x_txd *txd; |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 798 | struct pl08x_bus_data srcbus; |
| 799 | struct pl08x_bus_data dstbus; |
| 800 | size_t remainder; |
Russell King - ARM Linux | 25c94f7 | 2011-07-21 17:11:46 +0100 | [diff] [blame] | 801 | u32 lli_bus; |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 802 | }; |
| 803 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 804 | /* |
Viresh Kumar | 0532e6f | 2011-08-05 15:32:31 +0530 | [diff] [blame] | 805 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
| 806 | * victim in case src & dest are not similarly aligned. i.e. If after aligning |
| 807 | * masters address with width requirements of transfer (by sending few byte by |
| 808 | * byte data), slave is still not aligned, then its width will be reduced to |
| 809 | * BYTE. |
| 810 | * - prefers the destination bus if both available |
Viresh Kumar | 036f05f | 2011-08-05 15:32:41 +0530 | [diff] [blame] | 811 | * - prefers bus with fixed address (i.e. peripheral) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 812 | */ |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 813 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
| 814 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 815 | { |
| 816 | if (!(cctl & PL080_CONTROL_DST_INCR)) { |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 817 | *mbus = &bd->dstbus; |
| 818 | *sbus = &bd->srcbus; |
Viresh Kumar | 036f05f | 2011-08-05 15:32:41 +0530 | [diff] [blame] | 819 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
| 820 | *mbus = &bd->srcbus; |
| 821 | *sbus = &bd->dstbus; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 822 | } else { |
Viresh Kumar | 036f05f | 2011-08-05 15:32:41 +0530 | [diff] [blame] | 823 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 824 | *mbus = &bd->dstbus; |
| 825 | *sbus = &bd->srcbus; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 826 | } else { |
Viresh Kumar | 036f05f | 2011-08-05 15:32:41 +0530 | [diff] [blame] | 827 | *mbus = &bd->srcbus; |
| 828 | *sbus = &bd->dstbus; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 829 | } |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | /* |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 834 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 835 | */ |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 836 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
| 837 | struct pl08x_lli_build_data *bd, |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 838 | int num_llis, int len, u32 cctl, u32 cctl2) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 839 | { |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 840 | u32 offset = num_llis * pl08x->lli_words; |
| 841 | u32 *llis_va = bd->txd->llis_va + offset; |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 842 | dma_addr_t llis_bus = bd->txd->llis_bus; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 843 | |
| 844 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); |
| 845 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 846 | /* Advance the offset to next LLI. */ |
| 847 | offset += pl08x->lli_words; |
| 848 | |
| 849 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; |
| 850 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; |
| 851 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); |
| 852 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; |
| 853 | llis_va[PL080_LLI_CCTL] = cctl; |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 854 | if (pl08x->vd->pl080s) |
| 855 | llis_va[PL080S_LLI_CCTL2] = cctl2; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 856 | |
| 857 | if (cctl & PL080_CONTROL_SRC_INCR) |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 858 | bd->srcbus.addr += len; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 859 | if (cctl & PL080_CONTROL_DST_INCR) |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 860 | bd->dstbus.addr += len; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 861 | |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 862 | BUG_ON(bd->remainder < len); |
Russell King - ARM Linux | cace658 | 2011-01-03 22:37:31 +0000 | [diff] [blame] | 863 | |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 864 | bd->remainder -= len; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 865 | } |
| 866 | |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 867 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
| 868 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, |
| 869 | int num_llis, size_t *total_bytes) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 870 | { |
Viresh Kumar | 03af500 | 2011-08-05 15:32:39 +0530 | [diff] [blame] | 871 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 872 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); |
Viresh Kumar | 03af500 | 2011-08-05 15:32:39 +0530 | [diff] [blame] | 873 | (*total_bytes) += len; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 874 | } |
| 875 | |
Tomasz Figa | 48924e4 | 2013-08-11 19:59:16 +0200 | [diff] [blame] | 876 | #ifdef VERBOSE_DEBUG |
| 877 | static void pl08x_dump_lli(struct pl08x_driver_data *pl08x, |
| 878 | const u32 *llis_va, int num_llis) |
| 879 | { |
| 880 | int i; |
| 881 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 882 | if (pl08x->vd->pl080s) { |
Tomasz Figa | 48924e4 | 2013-08-11 19:59:16 +0200 | [diff] [blame] | 883 | dev_vdbg(&pl08x->adev->dev, |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 884 | "%-3s %-9s %-10s %-10s %-10s %-10s %s\n", |
| 885 | "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2"); |
| 886 | for (i = 0; i < num_llis; i++) { |
| 887 | dev_vdbg(&pl08x->adev->dev, |
| 888 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 889 | i, llis_va, llis_va[PL080_LLI_SRC], |
| 890 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], |
| 891 | llis_va[PL080_LLI_CCTL], |
| 892 | llis_va[PL080S_LLI_CCTL2]); |
| 893 | llis_va += pl08x->lli_words; |
| 894 | } |
| 895 | } else { |
| 896 | dev_vdbg(&pl08x->adev->dev, |
| 897 | "%-3s %-9s %-10s %-10s %-10s %s\n", |
| 898 | "lli", "", "csrc", "cdst", "clli", "cctl"); |
| 899 | for (i = 0; i < num_llis; i++) { |
| 900 | dev_vdbg(&pl08x->adev->dev, |
| 901 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 902 | i, llis_va, llis_va[PL080_LLI_SRC], |
| 903 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], |
| 904 | llis_va[PL080_LLI_CCTL]); |
| 905 | llis_va += pl08x->lli_words; |
| 906 | } |
Tomasz Figa | 48924e4 | 2013-08-11 19:59:16 +0200 | [diff] [blame] | 907 | } |
| 908 | } |
| 909 | #else |
| 910 | static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x, |
| 911 | const u32 *llis_va, int num_llis) {} |
| 912 | #endif |
| 913 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 914 | /* |
| 915 | * This fills in the table of LLIs for the transfer descriptor |
| 916 | * Note that we assume we never have to change the burst sizes |
| 917 | * Return 0 for error |
| 918 | */ |
| 919 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, |
| 920 | struct pl08x_txd *txd) |
| 921 | { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 922 | struct pl08x_bus_data *mbus, *sbus; |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 923 | struct pl08x_lli_build_data bd; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 924 | int num_llis = 0; |
Viresh Kumar | 03af500 | 2011-08-05 15:32:39 +0530 | [diff] [blame] | 925 | u32 cctl, early_bytes = 0; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 926 | size_t max_bytes_per_lli, total_bytes; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 927 | u32 *llis_va, *last_lli; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 928 | struct pl08x_sg *dsg; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 929 | |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 930 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 931 | if (!txd->llis_va) { |
| 932 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); |
| 933 | return 0; |
| 934 | } |
| 935 | |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 936 | bd.txd = txd; |
Russell King - ARM Linux | 25c94f7 | 2011-07-21 17:11:46 +0100 | [diff] [blame] | 937 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 938 | cctl = txd->cctl; |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 939 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 940 | /* Find maximum width of the source bus */ |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 941 | bd.srcbus.maxwidth = |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 942 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
| 943 | PL080_CONTROL_SWIDTH_SHIFT); |
| 944 | |
| 945 | /* Find maximum width of the destination bus */ |
Russell King - ARM Linux | 542361f | 2011-01-03 22:43:15 +0000 | [diff] [blame] | 946 | bd.dstbus.maxwidth = |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 947 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
| 948 | PL080_CONTROL_DWIDTH_SHIFT); |
| 949 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 950 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
| 951 | total_bytes = 0; |
| 952 | cctl = txd->cctl; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 953 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 954 | bd.srcbus.addr = dsg->src_addr; |
| 955 | bd.dstbus.addr = dsg->dst_addr; |
| 956 | bd.remainder = dsg->len; |
| 957 | bd.srcbus.buswidth = bd.srcbus.maxwidth; |
| 958 | bd.dstbus.buswidth = bd.dstbus.maxwidth; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 959 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 960 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 961 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 962 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
| 963 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", |
| 964 | bd.srcbus.buswidth, |
| 965 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", |
| 966 | bd.dstbus.buswidth, |
| 967 | bd.remainder); |
| 968 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", |
| 969 | mbus == &bd.srcbus ? "src" : "dst", |
| 970 | sbus == &bd.srcbus ? "src" : "dst"); |
Russell King - ARM Linux | fc74eb7 | 2011-07-21 17:12:06 +0100 | [diff] [blame] | 971 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 972 | /* |
| 973 | * Zero length is only allowed if all these requirements are |
| 974 | * met: |
| 975 | * - flow controller is peripheral. |
| 976 | * - src.addr is aligned to src.width |
| 977 | * - dst.addr is aligned to dst.width |
| 978 | * |
| 979 | * sg_len == 1 should be true, as there can be two cases here: |
| 980 | * |
| 981 | * - Memory addresses are contiguous and are not scattered. |
| 982 | * Here, Only one sg will be passed by user driver, with |
| 983 | * memory address and zero length. We pass this to controller |
| 984 | * and after the transfer it will receive the last burst |
| 985 | * request from peripheral and so transfer finishes. |
| 986 | * |
| 987 | * - Memory addresses are scattered and are not contiguous. |
| 988 | * Here, Obviously as DMA controller doesn't know when a lli's |
| 989 | * transfer gets over, it can't load next lli. So in this |
| 990 | * case, there has to be an assumption that only one lli is |
| 991 | * supported. Thus, we can't have scattered addresses. |
| 992 | */ |
| 993 | if (!bd.remainder) { |
| 994 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> |
| 995 | PL080_CONFIG_FLOW_CONTROL_SHIFT; |
| 996 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && |
Viresh Kumar | 0a23565 | 2011-08-05 15:32:42 +0530 | [diff] [blame] | 997 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 998 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
| 999 | __func__); |
| 1000 | return 0; |
| 1001 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1002 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1003 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
Julia Lawall | 880db3f | 2012-01-12 22:49:29 +0100 | [diff] [blame] | 1004 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1005 | dev_err(&pl08x->adev->dev, |
| 1006 | "%s src & dst address must be aligned to src" |
| 1007 | " & dst width if peripheral is flow controller", |
| 1008 | __func__); |
| 1009 | return 0; |
| 1010 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1011 | |
Viresh Kumar | 16a2e7d | 2011-08-05 15:32:37 +0530 | [diff] [blame] | 1012 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1013 | bd.dstbus.buswidth, 0); |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1014 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 1015 | 0, cctl, 0); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1016 | break; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1017 | } |
| 1018 | |
| 1019 | /* |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1020 | * Send byte by byte for following cases |
| 1021 | * - Less than a bus width available |
| 1022 | * - until master bus is aligned |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1023 | */ |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1024 | if (bd.remainder < mbus->buswidth) |
| 1025 | early_bytes = bd.remainder; |
| 1026 | else if ((mbus->addr) % (mbus->buswidth)) { |
| 1027 | early_bytes = mbus->buswidth - (mbus->addr) % |
| 1028 | (mbus->buswidth); |
| 1029 | if ((bd.remainder - early_bytes) < mbus->buswidth) |
| 1030 | early_bytes = bd.remainder; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1031 | } |
Viresh Kumar | 16a2e7d | 2011-08-05 15:32:37 +0530 | [diff] [blame] | 1032 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1033 | if (early_bytes) { |
| 1034 | dev_vdbg(&pl08x->adev->dev, |
| 1035 | "%s byte width LLIs (remain 0x%08x)\n", |
| 1036 | __func__, bd.remainder); |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1037 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
| 1038 | num_llis++, &total_bytes); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1039 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1040 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1041 | if (bd.remainder) { |
| 1042 | /* |
| 1043 | * Master now aligned |
| 1044 | * - if slave is not then we must set its width down |
| 1045 | */ |
| 1046 | if (sbus->addr % sbus->buswidth) { |
| 1047 | dev_dbg(&pl08x->adev->dev, |
| 1048 | "%s set down bus width to one byte\n", |
| 1049 | __func__); |
| 1050 | |
| 1051 | sbus->buswidth = 1; |
| 1052 | } |
| 1053 | |
| 1054 | /* |
| 1055 | * Bytes transferred = tsize * src width, not |
| 1056 | * MIN(buswidths) |
| 1057 | */ |
| 1058 | max_bytes_per_lli = bd.srcbus.buswidth * |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 1059 | pl08x->vd->max_transfer_size; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1060 | dev_vdbg(&pl08x->adev->dev, |
| 1061 | "%s max bytes per lli = %zu\n", |
| 1062 | __func__, max_bytes_per_lli); |
| 1063 | |
| 1064 | /* |
| 1065 | * Make largest possible LLIs until less than one bus |
| 1066 | * width left |
| 1067 | */ |
| 1068 | while (bd.remainder > (mbus->buswidth - 1)) { |
| 1069 | size_t lli_len, tsize, width; |
| 1070 | |
| 1071 | /* |
| 1072 | * If enough left try to send max possible, |
| 1073 | * otherwise try to send the remainder |
| 1074 | */ |
| 1075 | lli_len = min(bd.remainder, max_bytes_per_lli); |
| 1076 | |
| 1077 | /* |
| 1078 | * Check against maximum bus alignment: |
| 1079 | * Calculate actual transfer size in relation to |
| 1080 | * bus width an get a maximum remainder of the |
| 1081 | * highest bus width - 1 |
| 1082 | */ |
| 1083 | width = max(mbus->buswidth, sbus->buswidth); |
| 1084 | lli_len = (lli_len / width) * width; |
| 1085 | tsize = lli_len / bd.srcbus.buswidth; |
| 1086 | |
| 1087 | dev_vdbg(&pl08x->adev->dev, |
| 1088 | "%s fill lli with single lli chunk of " |
| 1089 | "size 0x%08zx (remainder 0x%08zx)\n", |
| 1090 | __func__, lli_len, bd.remainder); |
| 1091 | |
| 1092 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
| 1093 | bd.dstbus.buswidth, tsize); |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1094 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 1095 | lli_len, cctl, tsize); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1096 | total_bytes += lli_len; |
| 1097 | } |
| 1098 | |
| 1099 | /* |
| 1100 | * Send any odd bytes |
| 1101 | */ |
| 1102 | if (bd.remainder) { |
| 1103 | dev_vdbg(&pl08x->adev->dev, |
| 1104 | "%s align with boundary, send odd bytes (remain %zu)\n", |
| 1105 | __func__, bd.remainder); |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1106 | prep_byte_width_lli(pl08x, &bd, &cctl, |
| 1107 | bd.remainder, num_llis++, &total_bytes); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1108 | } |
| 1109 | } |
| 1110 | |
| 1111 | if (total_bytes != dsg->len) { |
| 1112 | dev_err(&pl08x->adev->dev, |
| 1113 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", |
| 1114 | __func__, total_bytes, dsg->len); |
| 1115 | return 0; |
| 1116 | } |
| 1117 | |
| 1118 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
| 1119 | dev_err(&pl08x->adev->dev, |
| 1120 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1121 | __func__, MAX_NUM_TSFR_LLIS); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1122 | return 0; |
| 1123 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1124 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1125 | |
Russell King - ARM Linux | b58b6b5 | 2011-01-03 22:34:48 +0000 | [diff] [blame] | 1126 | llis_va = txd->llis_va; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1127 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 1128 | /* The final LLI terminates the LLI. */ |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1129 | last_lli[PL080_LLI_LLI] = 0; |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 1130 | /* The final LLI element shall also fire an interrupt. */ |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1131 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1132 | |
Tomasz Figa | 48924e4 | 2013-08-11 19:59:16 +0200 | [diff] [blame] | 1133 | pl08x_dump_lli(pl08x, llis_va, num_llis); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1134 | |
| 1135 | return num_llis; |
| 1136 | } |
| 1137 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1138 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
| 1139 | struct pl08x_txd *txd) |
| 1140 | { |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1141 | struct pl08x_sg *dsg, *_dsg; |
| 1142 | |
Viresh Kumar | c120564 | 2011-08-05 15:32:44 +0530 | [diff] [blame] | 1143 | if (txd->llis_va) |
| 1144 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1145 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1146 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
| 1147 | list_del(&dsg->node); |
| 1148 | kfree(dsg); |
| 1149 | } |
| 1150 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1151 | kfree(txd); |
| 1152 | } |
| 1153 | |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1154 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
| 1155 | { |
| 1156 | struct device *dev = txd->vd.tx.chan->device->dev; |
| 1157 | struct pl08x_sg *dsg; |
| 1158 | |
| 1159 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { |
| 1160 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) |
| 1161 | list_for_each_entry(dsg, &txd->dsg_list, node) |
| 1162 | dma_unmap_single(dev, dsg->src_addr, dsg->len, |
| 1163 | DMA_TO_DEVICE); |
| 1164 | else { |
| 1165 | list_for_each_entry(dsg, &txd->dsg_list, node) |
| 1166 | dma_unmap_page(dev, dsg->src_addr, dsg->len, |
| 1167 | DMA_TO_DEVICE); |
| 1168 | } |
| 1169 | } |
| 1170 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { |
| 1171 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) |
| 1172 | list_for_each_entry(dsg, &txd->dsg_list, node) |
| 1173 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, |
| 1174 | DMA_FROM_DEVICE); |
| 1175 | else |
| 1176 | list_for_each_entry(dsg, &txd->dsg_list, node) |
| 1177 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, |
| 1178 | DMA_FROM_DEVICE); |
| 1179 | } |
| 1180 | } |
| 1181 | |
| 1182 | static void pl08x_desc_free(struct virt_dma_desc *vd) |
| 1183 | { |
| 1184 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); |
| 1185 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1186 | |
| 1187 | if (!plchan->slave) |
| 1188 | pl08x_unmap_buffers(txd); |
| 1189 | |
| 1190 | if (!txd->done) |
| 1191 | pl08x_release_mux(plchan); |
| 1192 | |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1193 | pl08x_free_txd(plchan->host, txd); |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1194 | } |
| 1195 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1196 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
| 1197 | struct pl08x_dma_chan *plchan) |
| 1198 | { |
Russell King | ea16056 | 2012-05-25 13:10:36 +0100 | [diff] [blame] | 1199 | LIST_HEAD(head); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1200 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1201 | vchan_get_all_descriptors(&plchan->vc, &head); |
Akinobu Mita | 9199826 | 2012-10-28 00:49:31 +0900 | [diff] [blame] | 1202 | vchan_dma_desc_free_list(&plchan->vc, &head); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1203 | } |
| 1204 | |
| 1205 | /* |
| 1206 | * The DMA ENGINE API |
| 1207 | */ |
| 1208 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) |
| 1209 | { |
| 1210 | return 0; |
| 1211 | } |
| 1212 | |
| 1213 | static void pl08x_free_chan_resources(struct dma_chan *chan) |
| 1214 | { |
Russell King | a068682 | 2012-05-26 17:00:49 +0100 | [diff] [blame] | 1215 | /* Ensure all queued descriptors are freed */ |
| 1216 | vchan_free_chan_resources(to_virt_chan(chan)); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1217 | } |
| 1218 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1219 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
| 1220 | struct dma_chan *chan, unsigned long flags) |
| 1221 | { |
| 1222 | struct dma_async_tx_descriptor *retval = NULL; |
| 1223 | |
| 1224 | return retval; |
| 1225 | } |
| 1226 | |
| 1227 | /* |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 1228 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
| 1229 | * If slaves are relying on interrupts to signal completion this function |
| 1230 | * must not be called with interrupts disabled. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1231 | */ |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 1232 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
| 1233 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1234 | { |
| 1235 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1236 | struct virt_dma_desc *vd; |
| 1237 | unsigned long flags; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1238 | enum dma_status ret; |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1239 | size_t bytes = 0; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1240 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1241 | ret = dma_cookie_status(chan, cookie, txstate); |
| 1242 | if (ret == DMA_SUCCESS) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1243 | return ret; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1244 | |
| 1245 | /* |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1246 | * There's no point calculating the residue if there's |
| 1247 | * no txstate to store the value. |
| 1248 | */ |
| 1249 | if (!txstate) { |
| 1250 | if (plchan->state == PL08X_CHAN_PAUSED) |
| 1251 | ret = DMA_PAUSED; |
| 1252 | return ret; |
| 1253 | } |
| 1254 | |
| 1255 | spin_lock_irqsave(&plchan->vc.lock, flags); |
| 1256 | ret = dma_cookie_status(chan, cookie, txstate); |
| 1257 | if (ret != DMA_SUCCESS) { |
| 1258 | vd = vchan_find_desc(&plchan->vc, cookie); |
| 1259 | if (vd) { |
| 1260 | /* On the issued list, so hasn't been processed yet */ |
| 1261 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); |
| 1262 | struct pl08x_sg *dsg; |
| 1263 | |
| 1264 | list_for_each_entry(dsg, &txd->dsg_list, node) |
| 1265 | bytes += dsg->len; |
| 1266 | } else { |
| 1267 | bytes = pl08x_getbytes_chan(plchan); |
| 1268 | } |
| 1269 | } |
| 1270 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
| 1271 | |
| 1272 | /* |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1273 | * This cookie not complete yet |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1274 | * Get number of bytes left in the active transactions and queue |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1275 | */ |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1276 | dma_set_residue(txstate, bytes); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1277 | |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1278 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
| 1279 | ret = DMA_PAUSED; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1280 | |
| 1281 | /* Whether waiting or running, we're in progress */ |
Russell King | 06e885b | 2012-05-26 15:05:52 +0100 | [diff] [blame] | 1282 | return ret; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1283 | } |
| 1284 | |
| 1285 | /* PrimeCell DMA extension */ |
| 1286 | struct burst_table { |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1287 | u32 burstwords; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1288 | u32 reg; |
| 1289 | }; |
| 1290 | |
| 1291 | static const struct burst_table burst_sizes[] = { |
| 1292 | { |
| 1293 | .burstwords = 256, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1294 | .reg = PL080_BSIZE_256, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1295 | }, |
| 1296 | { |
| 1297 | .burstwords = 128, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1298 | .reg = PL080_BSIZE_128, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1299 | }, |
| 1300 | { |
| 1301 | .burstwords = 64, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1302 | .reg = PL080_BSIZE_64, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1303 | }, |
| 1304 | { |
| 1305 | .burstwords = 32, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1306 | .reg = PL080_BSIZE_32, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1307 | }, |
| 1308 | { |
| 1309 | .burstwords = 16, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1310 | .reg = PL080_BSIZE_16, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1311 | }, |
| 1312 | { |
| 1313 | .burstwords = 8, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1314 | .reg = PL080_BSIZE_8, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1315 | }, |
| 1316 | { |
| 1317 | .burstwords = 4, |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1318 | .reg = PL080_BSIZE_4, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1319 | }, |
| 1320 | { |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1321 | .burstwords = 0, |
| 1322 | .reg = PL080_BSIZE_1, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1323 | }, |
| 1324 | }; |
| 1325 | |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1326 | /* |
| 1327 | * Given the source and destination available bus masks, select which |
| 1328 | * will be routed to each port. We try to have source and destination |
| 1329 | * on separate ports, but always respect the allowable settings. |
| 1330 | */ |
| 1331 | static u32 pl08x_select_bus(u8 src, u8 dst) |
| 1332 | { |
| 1333 | u32 cctl = 0; |
| 1334 | |
| 1335 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) |
| 1336 | cctl |= PL080_CONTROL_DST_AHB2; |
| 1337 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) |
| 1338 | cctl |= PL080_CONTROL_SRC_AHB2; |
| 1339 | |
| 1340 | return cctl; |
| 1341 | } |
| 1342 | |
Russell King - ARM Linux | f14c426 | 2011-07-21 17:12:47 +0100 | [diff] [blame] | 1343 | static u32 pl08x_cctl(u32 cctl) |
| 1344 | { |
| 1345 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | |
| 1346 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | |
| 1347 | PL080_CONTROL_PROT_MASK); |
| 1348 | |
| 1349 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ |
| 1350 | return cctl | PL080_CONTROL_PROT_SYS; |
| 1351 | } |
| 1352 | |
Russell King - ARM Linux | aa88cda | 2011-07-21 17:13:28 +0100 | [diff] [blame] | 1353 | static u32 pl08x_width(enum dma_slave_buswidth width) |
| 1354 | { |
| 1355 | switch (width) { |
| 1356 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 1357 | return PL080_WIDTH_8BIT; |
| 1358 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 1359 | return PL080_WIDTH_16BIT; |
| 1360 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 1361 | return PL080_WIDTH_32BIT; |
Vinod Koul | f32807f | 2011-07-25 19:22:01 +0530 | [diff] [blame] | 1362 | default: |
| 1363 | return ~0; |
Russell King - ARM Linux | aa88cda | 2011-07-21 17:13:28 +0100 | [diff] [blame] | 1364 | } |
Russell King - ARM Linux | aa88cda | 2011-07-21 17:13:28 +0100 | [diff] [blame] | 1365 | } |
| 1366 | |
Russell King - ARM Linux | 760596c6 | 2011-07-21 17:14:08 +0100 | [diff] [blame] | 1367 | static u32 pl08x_burst(u32 maxburst) |
| 1368 | { |
| 1369 | int i; |
| 1370 | |
| 1371 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) |
| 1372 | if (burst_sizes[i].burstwords <= maxburst) |
| 1373 | break; |
| 1374 | |
| 1375 | return burst_sizes[i].reg; |
| 1376 | } |
| 1377 | |
Russell King | 9862ba1 | 2012-05-16 11:16:03 +0100 | [diff] [blame] | 1378 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
| 1379 | enum dma_slave_buswidth addr_width, u32 maxburst) |
| 1380 | { |
| 1381 | u32 width, burst, cctl = 0; |
| 1382 | |
| 1383 | width = pl08x_width(addr_width); |
| 1384 | if (width == ~0) |
| 1385 | return ~0; |
| 1386 | |
| 1387 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; |
| 1388 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; |
| 1389 | |
| 1390 | /* |
| 1391 | * If this channel will only request single transfers, set this |
| 1392 | * down to ONE element. Also select one element if no maxburst |
| 1393 | * is specified. |
| 1394 | */ |
| 1395 | if (plchan->cd->single) |
| 1396 | maxburst = 1; |
| 1397 | |
| 1398 | burst = pl08x_burst(maxburst); |
| 1399 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; |
| 1400 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; |
| 1401 | |
| 1402 | return pl08x_cctl(cctl); |
| 1403 | } |
| 1404 | |
Russell King - ARM Linux | f0fd944 | 2011-01-03 22:45:57 +0000 | [diff] [blame] | 1405 | static int dma_set_runtime_config(struct dma_chan *chan, |
| 1406 | struct dma_slave_config *config) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1407 | { |
| 1408 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 1409 | struct pl08x_driver_data *pl08x = plchan->host; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1410 | |
Russell King - ARM Linux | b7f7586 | 2011-01-03 22:46:17 +0000 | [diff] [blame] | 1411 | if (!plchan->slave) |
| 1412 | return -EINVAL; |
| 1413 | |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1414 | /* Reject definitely invalid configurations */ |
| 1415 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 1416 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
Russell King - ARM Linux | f0fd944 | 2011-01-03 22:45:57 +0000 | [diff] [blame] | 1417 | return -EINVAL; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1418 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 1419 | if (config->device_fc && pl08x->vd->pl080s) { |
| 1420 | dev_err(&pl08x->adev->dev, |
| 1421 | "%s: PL080S does not support peripheral flow control\n", |
| 1422 | __func__); |
| 1423 | return -EINVAL; |
| 1424 | } |
| 1425 | |
Russell King | ed91c13 | 2012-05-16 11:02:40 +0100 | [diff] [blame] | 1426 | plchan->cfg = *config; |
| 1427 | |
Russell King - ARM Linux | f0fd944 | 2011-01-03 22:45:57 +0000 | [diff] [blame] | 1428 | return 0; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1429 | } |
| 1430 | |
| 1431 | /* |
| 1432 | * Slave transactions callback to the slave device to allow |
| 1433 | * synchronization of slave DMA signals with the DMAC enable |
| 1434 | */ |
| 1435 | static void pl08x_issue_pending(struct dma_chan *chan) |
| 1436 | { |
| 1437 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1438 | unsigned long flags; |
| 1439 | |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1440 | spin_lock_irqsave(&plchan->vc.lock, flags); |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1441 | if (vchan_issue_pending(&plchan->vc)) { |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 1442 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
| 1443 | pl08x_phy_alloc_and_start(plchan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1444 | } |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1445 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1446 | } |
| 1447 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1448 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
Russell King - ARM Linux | ac3cd20 | 2011-01-03 22:35:49 +0000 | [diff] [blame] | 1449 | { |
Viresh Kumar | b201c11 | 2011-08-05 15:32:29 +0530 | [diff] [blame] | 1450 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
Russell King - ARM Linux | ac3cd20 | 2011-01-03 22:35:49 +0000 | [diff] [blame] | 1451 | |
| 1452 | if (txd) { |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1453 | INIT_LIST_HEAD(&txd->dsg_list); |
Russell King - ARM Linux | 4983a04 | 2011-01-03 22:39:33 +0000 | [diff] [blame] | 1454 | |
| 1455 | /* Always enable error and terminal interrupts */ |
| 1456 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | |
| 1457 | PL080_CONFIG_TC_IRQ_MASK; |
Russell King - ARM Linux | ac3cd20 | 2011-01-03 22:35:49 +0000 | [diff] [blame] | 1458 | } |
| 1459 | return txd; |
| 1460 | } |
| 1461 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1462 | /* |
| 1463 | * Initialize a descriptor to be used by memcpy submit |
| 1464 | */ |
| 1465 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( |
| 1466 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 1467 | size_t len, unsigned long flags) |
| 1468 | { |
| 1469 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
| 1470 | struct pl08x_driver_data *pl08x = plchan->host; |
| 1471 | struct pl08x_txd *txd; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1472 | struct pl08x_sg *dsg; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1473 | int ret; |
| 1474 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1475 | txd = pl08x_get_txd(plchan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1476 | if (!txd) { |
| 1477 | dev_err(&pl08x->adev->dev, |
| 1478 | "%s no memory for descriptor\n", __func__); |
| 1479 | return NULL; |
| 1480 | } |
| 1481 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1482 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
| 1483 | if (!dsg) { |
| 1484 | pl08x_free_txd(pl08x, txd); |
| 1485 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", |
| 1486 | __func__); |
| 1487 | return NULL; |
| 1488 | } |
| 1489 | list_add_tail(&dsg->node, &txd->dsg_list); |
| 1490 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1491 | dsg->src_addr = src; |
| 1492 | dsg->dst_addr = dest; |
| 1493 | dsg->len = len; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1494 | |
| 1495 | /* Set platform data for m2m */ |
Russell King - ARM Linux | 4983a04 | 2011-01-03 22:39:33 +0000 | [diff] [blame] | 1496 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1497 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
Russell King - ARM Linux | c7da9a5 | 2011-01-03 22:40:53 +0000 | [diff] [blame] | 1498 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
Russell King - ARM Linux | 4983a04 | 2011-01-03 22:39:33 +0000 | [diff] [blame] | 1499 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1500 | /* Both to be incremented or the code will break */ |
Russell King - ARM Linux | 70b5ed6 | 2011-01-03 22:40:13 +0000 | [diff] [blame] | 1501 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
Russell King - ARM Linux | c7da9a5 | 2011-01-03 22:40:53 +0000 | [diff] [blame] | 1502 | |
Russell King - ARM Linux | c7da9a5 | 2011-01-03 22:40:53 +0000 | [diff] [blame] | 1503 | if (pl08x->vd->dualmaster) |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1504 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
| 1505 | pl08x->mem_buses); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1506 | |
Russell King | aa4afb7 | 2012-05-26 15:43:00 +0100 | [diff] [blame] | 1507 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
| 1508 | if (!ret) { |
| 1509 | pl08x_free_txd(pl08x, txd); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1510 | return NULL; |
Russell King | aa4afb7 | 2012-05-26 15:43:00 +0100 | [diff] [blame] | 1511 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1512 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1513 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1514 | } |
| 1515 | |
Russell King - ARM Linux | 3e2a037 | 2011-01-03 22:32:46 +0000 | [diff] [blame] | 1516 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1517 | struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1518 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 1519 | unsigned long flags, void *context) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1520 | { |
| 1521 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
| 1522 | struct pl08x_driver_data *pl08x = plchan->host; |
| 1523 | struct pl08x_txd *txd; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1524 | struct pl08x_sg *dsg; |
| 1525 | struct scatterlist *sg; |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1526 | enum dma_slave_buswidth addr_width; |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1527 | dma_addr_t slave_addr; |
Viresh Kumar | 0a23565 | 2011-08-05 15:32:42 +0530 | [diff] [blame] | 1528 | int ret, tmp; |
Russell King | 409ec8d | 2012-05-16 11:08:43 +0100 | [diff] [blame] | 1529 | u8 src_buses, dst_buses; |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1530 | u32 maxburst, cctl; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1531 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1532 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 1533 | __func__, sg_dma_len(sgl), plchan->name); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1534 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1535 | txd = pl08x_get_txd(plchan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1536 | if (!txd) { |
| 1537 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); |
| 1538 | return NULL; |
| 1539 | } |
| 1540 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1541 | /* |
| 1542 | * Set up addresses, the PrimeCell configured address |
| 1543 | * will take precedence since this may configure the |
| 1544 | * channel target address dynamically at runtime. |
| 1545 | */ |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1546 | if (direction == DMA_MEM_TO_DEV) { |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1547 | cctl = PL080_CONTROL_SRC_INCR; |
Russell King | ed91c13 | 2012-05-16 11:02:40 +0100 | [diff] [blame] | 1548 | slave_addr = plchan->cfg.dst_addr; |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1549 | addr_width = plchan->cfg.dst_addr_width; |
| 1550 | maxburst = plchan->cfg.dst_maxburst; |
Russell King | 409ec8d | 2012-05-16 11:08:43 +0100 | [diff] [blame] | 1551 | src_buses = pl08x->mem_buses; |
| 1552 | dst_buses = plchan->cd->periph_buses; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1553 | } else if (direction == DMA_DEV_TO_MEM) { |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1554 | cctl = PL080_CONTROL_DST_INCR; |
Russell King | ed91c13 | 2012-05-16 11:02:40 +0100 | [diff] [blame] | 1555 | slave_addr = plchan->cfg.src_addr; |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1556 | addr_width = plchan->cfg.src_addr_width; |
| 1557 | maxburst = plchan->cfg.src_maxburst; |
Russell King | 409ec8d | 2012-05-16 11:08:43 +0100 | [diff] [blame] | 1558 | src_buses = plchan->cd->periph_buses; |
| 1559 | dst_buses = pl08x->mem_buses; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1560 | } else { |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1561 | pl08x_free_txd(pl08x, txd); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1562 | dev_err(&pl08x->adev->dev, |
| 1563 | "%s direction unsupported\n", __func__); |
| 1564 | return NULL; |
| 1565 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1566 | |
Russell King | dc8d5f8 | 2012-05-16 12:20:55 +0100 | [diff] [blame] | 1567 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
Russell King | 800d683 | 2012-05-16 11:33:31 +0100 | [diff] [blame] | 1568 | if (cctl == ~0) { |
| 1569 | pl08x_free_txd(pl08x, txd); |
| 1570 | dev_err(&pl08x->adev->dev, |
| 1571 | "DMA slave configuration botched?\n"); |
| 1572 | return NULL; |
| 1573 | } |
| 1574 | |
Russell King | 409ec8d | 2012-05-16 11:08:43 +0100 | [diff] [blame] | 1575 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
| 1576 | |
Russell King | 95442b2 | 2012-05-16 11:05:09 +0100 | [diff] [blame] | 1577 | if (plchan->cfg.device_fc) |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1578 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
Viresh Kumar | 0a23565 | 2011-08-05 15:32:42 +0530 | [diff] [blame] | 1579 | PL080_FLOW_PER2MEM_PER; |
| 1580 | else |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1581 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
Viresh Kumar | 0a23565 | 2011-08-05 15:32:42 +0530 | [diff] [blame] | 1582 | PL080_FLOW_PER2MEM; |
| 1583 | |
| 1584 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
| 1585 | |
Russell King | c48d496 | 2012-05-25 11:48:51 +0100 | [diff] [blame] | 1586 | ret = pl08x_request_mux(plchan); |
| 1587 | if (ret < 0) { |
| 1588 | pl08x_free_txd(pl08x, txd); |
| 1589 | dev_dbg(&pl08x->adev->dev, |
| 1590 | "unable to mux for transfer on %s due to platform restrictions\n", |
| 1591 | plchan->name); |
| 1592 | return NULL; |
| 1593 | } |
| 1594 | |
| 1595 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", |
| 1596 | plchan->signal, plchan->name); |
| 1597 | |
| 1598 | /* Assign the flow control signal to this channel */ |
| 1599 | if (direction == DMA_MEM_TO_DEV) |
| 1600 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; |
| 1601 | else |
| 1602 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; |
| 1603 | |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1604 | for_each_sg(sgl, sg, sg_len, tmp) { |
| 1605 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
| 1606 | if (!dsg) { |
Russell King | c48d496 | 2012-05-25 11:48:51 +0100 | [diff] [blame] | 1607 | pl08x_release_mux(plchan); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1608 | pl08x_free_txd(pl08x, txd); |
| 1609 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", |
| 1610 | __func__); |
| 1611 | return NULL; |
| 1612 | } |
| 1613 | list_add_tail(&dsg->node, &txd->dsg_list); |
| 1614 | |
| 1615 | dsg->len = sg_dma_len(sg); |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1616 | if (direction == DMA_MEM_TO_DEV) { |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 1617 | dsg->src_addr = sg_dma_address(sg); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1618 | dsg->dst_addr = slave_addr; |
| 1619 | } else { |
| 1620 | dsg->src_addr = slave_addr; |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 1621 | dsg->dst_addr = sg_dma_address(sg); |
Viresh Kumar | b7f69d9 | 2011-08-05 15:32:43 +0530 | [diff] [blame] | 1622 | } |
| 1623 | } |
| 1624 | |
Russell King | aa4afb7 | 2012-05-26 15:43:00 +0100 | [diff] [blame] | 1625 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
| 1626 | if (!ret) { |
| 1627 | pl08x_release_mux(plchan); |
| 1628 | pl08x_free_txd(pl08x, txd); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1629 | return NULL; |
Russell King | aa4afb7 | 2012-05-26 15:43:00 +0100 | [diff] [blame] | 1630 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1631 | |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1632 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1633 | } |
| 1634 | |
| 1635 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 1636 | unsigned long arg) |
| 1637 | { |
| 1638 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); |
| 1639 | struct pl08x_driver_data *pl08x = plchan->host; |
| 1640 | unsigned long flags; |
| 1641 | int ret = 0; |
| 1642 | |
| 1643 | /* Controls applicable to inactive channels */ |
| 1644 | if (cmd == DMA_SLAVE_CONFIG) { |
Russell King - ARM Linux | f0fd944 | 2011-01-03 22:45:57 +0000 | [diff] [blame] | 1645 | return dma_set_runtime_config(chan, |
| 1646 | (struct dma_slave_config *)arg); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1647 | } |
| 1648 | |
| 1649 | /* |
| 1650 | * Anything succeeds on channels with no physical allocation and |
| 1651 | * no queued transfers. |
| 1652 | */ |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1653 | spin_lock_irqsave(&plchan->vc.lock, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1654 | if (!plchan->phychan && !plchan->at) { |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1655 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1656 | return 0; |
| 1657 | } |
| 1658 | |
| 1659 | switch (cmd) { |
| 1660 | case DMA_TERMINATE_ALL: |
| 1661 | plchan->state = PL08X_CHAN_IDLE; |
| 1662 | |
| 1663 | if (plchan->phychan) { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1664 | /* |
| 1665 | * Mark physical channel as free and free any slave |
| 1666 | * signal |
| 1667 | */ |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 1668 | pl08x_phy_free(plchan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1669 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1670 | /* Dequeue jobs and free LLIs */ |
| 1671 | if (plchan->at) { |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1672 | pl08x_desc_free(&plchan->at->vd); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1673 | plchan->at = NULL; |
| 1674 | } |
| 1675 | /* Dequeue jobs not yet fired as well */ |
| 1676 | pl08x_free_txd_list(pl08x, plchan); |
| 1677 | break; |
| 1678 | case DMA_PAUSE: |
| 1679 | pl08x_pause_phy_chan(plchan->phychan); |
| 1680 | plchan->state = PL08X_CHAN_PAUSED; |
| 1681 | break; |
| 1682 | case DMA_RESUME: |
| 1683 | pl08x_resume_phy_chan(plchan->phychan); |
| 1684 | plchan->state = PL08X_CHAN_RUNNING; |
| 1685 | break; |
| 1686 | default: |
| 1687 | /* Unknown command */ |
| 1688 | ret = -ENXIO; |
| 1689 | break; |
| 1690 | } |
| 1691 | |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1692 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1693 | |
| 1694 | return ret; |
| 1695 | } |
| 1696 | |
| 1697 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) |
| 1698 | { |
Russell King - ARM Linux | 7703eac | 2011-08-31 09:34:35 +0100 | [diff] [blame] | 1699 | struct pl08x_dma_chan *plchan; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1700 | char *name = chan_id; |
| 1701 | |
Russell King - ARM Linux | 7703eac | 2011-08-31 09:34:35 +0100 | [diff] [blame] | 1702 | /* Reject channels for devices not bound to this driver */ |
| 1703 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) |
| 1704 | return false; |
| 1705 | |
| 1706 | plchan = to_pl08x_chan(chan); |
| 1707 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1708 | /* Check that the channel is not taken! */ |
| 1709 | if (!strcmp(plchan->name, name)) |
| 1710 | return true; |
| 1711 | |
| 1712 | return false; |
| 1713 | } |
| 1714 | |
| 1715 | /* |
| 1716 | * Just check that the device is there and active |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 1717 | * TODO: turn this bit on/off depending on the number of physical channels |
| 1718 | * actually used, if it is zero... well shut it off. That will save some |
| 1719 | * power. Cut the clock at the same time. |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1720 | */ |
| 1721 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) |
| 1722 | { |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 1723 | /* The Nomadik variant does not have the config register */ |
| 1724 | if (pl08x->vd->nomadik) |
| 1725 | return; |
Viresh Kumar | 48a59ef | 2011-08-05 15:32:34 +0530 | [diff] [blame] | 1726 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1727 | } |
| 1728 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1729 | static irqreturn_t pl08x_irq(int irq, void *dev) |
| 1730 | { |
| 1731 | struct pl08x_driver_data *pl08x = dev; |
Viresh Kumar | 28da283 | 2011-08-05 15:32:36 +0530 | [diff] [blame] | 1732 | u32 mask = 0, err, tc, i; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1733 | |
Viresh Kumar | 28da283 | 2011-08-05 15:32:36 +0530 | [diff] [blame] | 1734 | /* check & clear - ERR & TC interrupts */ |
| 1735 | err = readl(pl08x->base + PL080_ERR_STATUS); |
| 1736 | if (err) { |
| 1737 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", |
| 1738 | __func__, err); |
| 1739 | writel(err, pl08x->base + PL080_ERR_CLEAR); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1740 | } |
Linus Walleij | d29bf01 | 2012-04-09 22:53:21 +0200 | [diff] [blame] | 1741 | tc = readl(pl08x->base + PL080_TC_STATUS); |
Viresh Kumar | 28da283 | 2011-08-05 15:32:36 +0530 | [diff] [blame] | 1742 | if (tc) |
| 1743 | writel(tc, pl08x->base + PL080_TC_CLEAR); |
| 1744 | |
| 1745 | if (!err && !tc) |
| 1746 | return IRQ_NONE; |
| 1747 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1748 | for (i = 0; i < pl08x->vd->channels; i++) { |
Viresh Kumar | 28da283 | 2011-08-05 15:32:36 +0530 | [diff] [blame] | 1749 | if (((1 << i) & err) || ((1 << i) & tc)) { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1750 | /* Locate physical channel */ |
| 1751 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; |
| 1752 | struct pl08x_dma_chan *plchan = phychan->serving; |
Russell King | a936e79 | 2012-05-25 10:51:19 +0100 | [diff] [blame] | 1753 | struct pl08x_txd *tx; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1754 | |
Viresh Kumar | 28da283 | 2011-08-05 15:32:36 +0530 | [diff] [blame] | 1755 | if (!plchan) { |
| 1756 | dev_err(&pl08x->adev->dev, |
| 1757 | "%s Error TC interrupt on unused channel: 0x%08x\n", |
| 1758 | __func__, i); |
| 1759 | continue; |
| 1760 | } |
| 1761 | |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1762 | spin_lock(&plchan->vc.lock); |
Russell King | a936e79 | 2012-05-25 10:51:19 +0100 | [diff] [blame] | 1763 | tx = plchan->at; |
| 1764 | if (tx) { |
| 1765 | plchan->at = NULL; |
Russell King | c48d496 | 2012-05-25 11:48:51 +0100 | [diff] [blame] | 1766 | /* |
| 1767 | * This descriptor is done, release its mux |
| 1768 | * reservation. |
| 1769 | */ |
| 1770 | pl08x_release_mux(plchan); |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1771 | tx->done = true; |
| 1772 | vchan_cookie_complete(&tx->vd); |
Russell King | c33b644 | 2012-05-25 15:41:13 +0100 | [diff] [blame] | 1773 | |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 1774 | /* |
| 1775 | * And start the next descriptor (if any), |
| 1776 | * otherwise free this channel. |
| 1777 | */ |
Russell King | 879f127 | 2012-05-26 14:27:40 +0100 | [diff] [blame] | 1778 | if (vchan_next_desc(&plchan->vc)) |
Russell King | c33b644 | 2012-05-25 15:41:13 +0100 | [diff] [blame] | 1779 | pl08x_start_next_txd(plchan); |
Russell King | a5a488d | 2012-05-26 13:54:15 +0100 | [diff] [blame] | 1780 | else |
| 1781 | pl08x_phy_free(plchan); |
Russell King | a936e79 | 2012-05-25 10:51:19 +0100 | [diff] [blame] | 1782 | } |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1783 | spin_unlock(&plchan->vc.lock); |
Russell King | a936e79 | 2012-05-25 10:51:19 +0100 | [diff] [blame] | 1784 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1785 | mask |= (1 << i); |
| 1786 | } |
| 1787 | } |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1788 | |
| 1789 | return mask ? IRQ_HANDLED : IRQ_NONE; |
| 1790 | } |
| 1791 | |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1792 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
| 1793 | { |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1794 | chan->slave = true; |
| 1795 | chan->name = chan->cd->bus_id; |
Russell King | ed91c13 | 2012-05-16 11:02:40 +0100 | [diff] [blame] | 1796 | chan->cfg.src_addr = chan->cd->addr; |
| 1797 | chan->cfg.dst_addr = chan->cd->addr; |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1798 | } |
| 1799 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1800 | /* |
| 1801 | * Initialise the DMAC memcpy/slave channels. |
| 1802 | * Make a local wrapper to hold required data |
| 1803 | */ |
| 1804 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 1805 | struct dma_device *dmadev, unsigned int channels, bool slave) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1806 | { |
| 1807 | struct pl08x_dma_chan *chan; |
| 1808 | int i; |
| 1809 | |
| 1810 | INIT_LIST_HEAD(&dmadev->channels); |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 1811 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1812 | /* |
| 1813 | * Register as many many memcpy as we have physical channels, |
| 1814 | * we won't always be able to use all but the code will have |
| 1815 | * to cope with that situation. |
| 1816 | */ |
| 1817 | for (i = 0; i < channels; i++) { |
Viresh Kumar | b201c11 | 2011-08-05 15:32:29 +0530 | [diff] [blame] | 1818 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1819 | if (!chan) { |
| 1820 | dev_err(&pl08x->adev->dev, |
| 1821 | "%s no memory for channel\n", __func__); |
| 1822 | return -ENOMEM; |
| 1823 | } |
| 1824 | |
| 1825 | chan->host = pl08x; |
| 1826 | chan->state = PL08X_CHAN_IDLE; |
Russell King | ad0de2a | 2012-05-25 11:15:15 +0100 | [diff] [blame] | 1827 | chan->signal = -1; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1828 | |
| 1829 | if (slave) { |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1830 | chan->cd = &pl08x->pd->slave_channels[i]; |
Russell King - ARM Linux | 121c847 | 2011-07-21 17:13:48 +0100 | [diff] [blame] | 1831 | pl08x_dma_slave_init(chan); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1832 | } else { |
| 1833 | chan->cd = &pl08x->pd->memcpy_channel; |
| 1834 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); |
| 1835 | if (!chan->name) { |
| 1836 | kfree(chan); |
| 1837 | return -ENOMEM; |
| 1838 | } |
| 1839 | } |
Viresh Kumar | 175a5e6 | 2011-08-05 15:32:32 +0530 | [diff] [blame] | 1840 | dev_dbg(&pl08x->adev->dev, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1841 | "initialize virtual channel \"%s\"\n", |
| 1842 | chan->name); |
| 1843 | |
Russell King | 1853613 | 2012-05-26 14:42:23 +0100 | [diff] [blame] | 1844 | chan->vc.desc_free = pl08x_desc_free; |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 1845 | vchan_init(&chan->vc, dmadev); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1846 | } |
| 1847 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", |
| 1848 | i, slave ? "slave" : "memcpy"); |
| 1849 | return i; |
| 1850 | } |
| 1851 | |
| 1852 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) |
| 1853 | { |
| 1854 | struct pl08x_dma_chan *chan = NULL; |
| 1855 | struct pl08x_dma_chan *next; |
| 1856 | |
| 1857 | list_for_each_entry_safe(chan, |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 1858 | next, &dmadev->channels, vc.chan.device_node) { |
| 1859 | list_del(&chan->vc.chan.device_node); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1860 | kfree(chan); |
| 1861 | } |
| 1862 | } |
| 1863 | |
| 1864 | #ifdef CONFIG_DEBUG_FS |
| 1865 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) |
| 1866 | { |
| 1867 | switch (state) { |
| 1868 | case PL08X_CHAN_IDLE: |
| 1869 | return "idle"; |
| 1870 | case PL08X_CHAN_RUNNING: |
| 1871 | return "running"; |
| 1872 | case PL08X_CHAN_PAUSED: |
| 1873 | return "paused"; |
| 1874 | case PL08X_CHAN_WAITING: |
| 1875 | return "waiting"; |
| 1876 | default: |
| 1877 | break; |
| 1878 | } |
| 1879 | return "UNKNOWN STATE"; |
| 1880 | } |
| 1881 | |
| 1882 | static int pl08x_debugfs_show(struct seq_file *s, void *data) |
| 1883 | { |
| 1884 | struct pl08x_driver_data *pl08x = s->private; |
| 1885 | struct pl08x_dma_chan *chan; |
| 1886 | struct pl08x_phy_chan *ch; |
| 1887 | unsigned long flags; |
| 1888 | int i; |
| 1889 | |
| 1890 | seq_printf(s, "PL08x physical channels:\n"); |
| 1891 | seq_printf(s, "CHANNEL:\tUSER:\n"); |
| 1892 | seq_printf(s, "--------\t-----\n"); |
| 1893 | for (i = 0; i < pl08x->vd->channels; i++) { |
| 1894 | struct pl08x_dma_chan *virt_chan; |
| 1895 | |
| 1896 | ch = &pl08x->phy_chans[i]; |
| 1897 | |
| 1898 | spin_lock_irqsave(&ch->lock, flags); |
| 1899 | virt_chan = ch->serving; |
| 1900 | |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 1901 | seq_printf(s, "%d\t\t%s%s\n", |
| 1902 | ch->id, |
| 1903 | virt_chan ? virt_chan->name : "(none)", |
| 1904 | ch->locked ? " LOCKED" : ""); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1905 | |
| 1906 | spin_unlock_irqrestore(&ch->lock, flags); |
| 1907 | } |
| 1908 | |
| 1909 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); |
| 1910 | seq_printf(s, "CHANNEL:\tSTATE:\n"); |
| 1911 | seq_printf(s, "--------\t------\n"); |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 1912 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
Russell King - ARM Linux | 3e2a037 | 2011-01-03 22:32:46 +0000 | [diff] [blame] | 1913 | seq_printf(s, "%s\t\t%s\n", chan->name, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1914 | pl08x_state_str(chan->state)); |
| 1915 | } |
| 1916 | |
| 1917 | seq_printf(s, "\nPL08x virtual slave channels:\n"); |
| 1918 | seq_printf(s, "CHANNEL:\tSTATE:\n"); |
| 1919 | seq_printf(s, "--------\t------\n"); |
Russell King | 01d8dc6 | 2012-05-26 14:04:29 +0100 | [diff] [blame] | 1920 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
Russell King - ARM Linux | 3e2a037 | 2011-01-03 22:32:46 +0000 | [diff] [blame] | 1921 | seq_printf(s, "%s\t\t%s\n", chan->name, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1922 | pl08x_state_str(chan->state)); |
| 1923 | } |
| 1924 | |
| 1925 | return 0; |
| 1926 | } |
| 1927 | |
| 1928 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) |
| 1929 | { |
| 1930 | return single_open(file, pl08x_debugfs_show, inode->i_private); |
| 1931 | } |
| 1932 | |
| 1933 | static const struct file_operations pl08x_debugfs_operations = { |
| 1934 | .open = pl08x_debugfs_open, |
| 1935 | .read = seq_read, |
| 1936 | .llseek = seq_lseek, |
| 1937 | .release = single_release, |
| 1938 | }; |
| 1939 | |
| 1940 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) |
| 1941 | { |
| 1942 | /* Expose a simple debugfs interface to view all clocks */ |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 1943 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
| 1944 | S_IFREG | S_IRUGO, NULL, pl08x, |
| 1945 | &pl08x_debugfs_operations); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1946 | } |
| 1947 | |
| 1948 | #else |
| 1949 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) |
| 1950 | { |
| 1951 | } |
| 1952 | #endif |
| 1953 | |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 1954 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1955 | { |
| 1956 | struct pl08x_driver_data *pl08x; |
Russell King - ARM Linux | f96ca9ec | 2011-01-03 22:35:08 +0000 | [diff] [blame] | 1957 | const struct vendor_data *vd = id->data; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 1958 | u32 tsfr_size; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1959 | int ret = 0; |
| 1960 | int i; |
| 1961 | |
| 1962 | ret = amba_request_regions(adev, NULL); |
| 1963 | if (ret) |
| 1964 | return ret; |
| 1965 | |
| 1966 | /* Create the driver state holder */ |
Viresh Kumar | b201c11 | 2011-08-05 15:32:29 +0530 | [diff] [blame] | 1967 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 1968 | if (!pl08x) { |
| 1969 | ret = -ENOMEM; |
| 1970 | goto out_no_pl08x; |
| 1971 | } |
| 1972 | |
| 1973 | /* Initialize memcpy engine */ |
| 1974 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); |
| 1975 | pl08x->memcpy.dev = &adev->dev; |
| 1976 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; |
| 1977 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; |
| 1978 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; |
| 1979 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; |
| 1980 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; |
| 1981 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; |
| 1982 | pl08x->memcpy.device_control = pl08x_control; |
| 1983 | |
| 1984 | /* Initialize slave engine */ |
| 1985 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); |
| 1986 | pl08x->slave.dev = &adev->dev; |
| 1987 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; |
| 1988 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; |
| 1989 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; |
| 1990 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; |
| 1991 | pl08x->slave.device_issue_pending = pl08x_issue_pending; |
| 1992 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; |
| 1993 | pl08x->slave.device_control = pl08x_control; |
| 1994 | |
| 1995 | /* Get the platform data */ |
| 1996 | pl08x->pd = dev_get_platdata(&adev->dev); |
| 1997 | if (!pl08x->pd) { |
| 1998 | dev_err(&adev->dev, "no platform data supplied\n"); |
Julia Lawall | 983d7be | 2012-08-14 14:58:32 +0200 | [diff] [blame] | 1999 | ret = -EINVAL; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2000 | goto out_no_platdata; |
| 2001 | } |
| 2002 | |
| 2003 | /* Assign useful pointers to the driver state */ |
| 2004 | pl08x->adev = adev; |
| 2005 | pl08x->vd = vd; |
| 2006 | |
Russell King - ARM Linux | 30749cb | 2011-01-03 22:41:13 +0000 | [diff] [blame] | 2007 | /* By default, AHB1 only. If dualmaster, from platform */ |
| 2008 | pl08x->lli_buses = PL08X_AHB1; |
| 2009 | pl08x->mem_buses = PL08X_AHB1; |
| 2010 | if (pl08x->vd->dualmaster) { |
| 2011 | pl08x->lli_buses = pl08x->pd->lli_buses; |
| 2012 | pl08x->mem_buses = pl08x->pd->mem_buses; |
| 2013 | } |
| 2014 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 2015 | if (vd->pl080s) |
| 2016 | pl08x->lli_words = PL080S_LLI_WORDS; |
| 2017 | else |
| 2018 | pl08x->lli_words = PL080_LLI_WORDS; |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 2019 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); |
| 2020 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2021 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
| 2022 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, |
Tomasz Figa | ba6785f | 2013-08-11 19:59:15 +0200 | [diff] [blame] | 2023 | tsfr_size, PL08X_ALIGN, 0); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2024 | if (!pl08x->pool) { |
| 2025 | ret = -ENOMEM; |
| 2026 | goto out_no_lli_pool; |
| 2027 | } |
| 2028 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2029 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
| 2030 | if (!pl08x->base) { |
| 2031 | ret = -ENOMEM; |
| 2032 | goto out_no_ioremap; |
| 2033 | } |
| 2034 | |
| 2035 | /* Turn on the PL08x */ |
| 2036 | pl08x_ensure_on(pl08x); |
| 2037 | |
Russell King - ARM Linux | 94ae852 | 2011-01-16 20:18:05 +0000 | [diff] [blame] | 2038 | /* Attach the interrupt handler */ |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2039 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
| 2040 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); |
| 2041 | |
| 2042 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, |
Russell King - ARM Linux | b05cd8f | 2011-01-03 22:33:26 +0000 | [diff] [blame] | 2043 | DRIVER_NAME, pl08x); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2044 | if (ret) { |
| 2045 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", |
| 2046 | __func__, adev->irq[0]); |
| 2047 | goto out_no_irq; |
| 2048 | } |
| 2049 | |
| 2050 | /* Initialize physical channels */ |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2051 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2052 | GFP_KERNEL); |
| 2053 | if (!pl08x->phy_chans) { |
| 2054 | dev_err(&adev->dev, "%s failed to allocate " |
| 2055 | "physical channel holders\n", |
| 2056 | __func__); |
Julia Lawall | 983d7be | 2012-08-14 14:58:32 +0200 | [diff] [blame] | 2057 | ret = -ENOMEM; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2058 | goto out_no_phychans; |
| 2059 | } |
| 2060 | |
| 2061 | for (i = 0; i < vd->channels; i++) { |
| 2062 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; |
| 2063 | |
| 2064 | ch->id = i; |
| 2065 | ch->base = pl08x->base + PL080_Cx_BASE(i); |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 2066 | ch->reg_config = ch->base + vd->config_offset; |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2067 | spin_lock_init(&ch->lock); |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2068 | |
| 2069 | /* |
| 2070 | * Nomadik variants can have channels that are locked |
| 2071 | * down for the secure world only. Lock up these channels |
| 2072 | * by perpetually serving a dummy virtual channel. |
| 2073 | */ |
| 2074 | if (vd->nomadik) { |
| 2075 | u32 val; |
| 2076 | |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 2077 | val = readl(ch->reg_config); |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2078 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
| 2079 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); |
| 2080 | ch->locked = true; |
| 2081 | } |
| 2082 | } |
| 2083 | |
Viresh Kumar | 175a5e6 | 2011-08-05 15:32:32 +0530 | [diff] [blame] | 2084 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
| 2085 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2086 | } |
| 2087 | |
| 2088 | /* Register as many memcpy channels as there are physical channels */ |
| 2089 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, |
| 2090 | pl08x->vd->channels, false); |
| 2091 | if (ret <= 0) { |
| 2092 | dev_warn(&pl08x->adev->dev, |
| 2093 | "%s failed to enumerate memcpy channels - %d\n", |
| 2094 | __func__, ret); |
| 2095 | goto out_no_memcpy; |
| 2096 | } |
| 2097 | pl08x->memcpy.chancnt = ret; |
| 2098 | |
| 2099 | /* Register slave channels */ |
| 2100 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, |
Viresh Kumar | 3e27ee8 | 2011-08-05 15:32:27 +0530 | [diff] [blame] | 2101 | pl08x->pd->num_slave_channels, true); |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2102 | if (ret <= 0) { |
| 2103 | dev_warn(&pl08x->adev->dev, |
| 2104 | "%s failed to enumerate slave channels - %d\n", |
| 2105 | __func__, ret); |
| 2106 | goto out_no_slave; |
| 2107 | } |
| 2108 | pl08x->slave.chancnt = ret; |
| 2109 | |
| 2110 | ret = dma_async_device_register(&pl08x->memcpy); |
| 2111 | if (ret) { |
| 2112 | dev_warn(&pl08x->adev->dev, |
| 2113 | "%s failed to register memcpy as an async device - %d\n", |
| 2114 | __func__, ret); |
| 2115 | goto out_no_memcpy_reg; |
| 2116 | } |
| 2117 | |
| 2118 | ret = dma_async_device_register(&pl08x->slave); |
| 2119 | if (ret) { |
| 2120 | dev_warn(&pl08x->adev->dev, |
| 2121 | "%s failed to register slave as an async device - %d\n", |
| 2122 | __func__, ret); |
| 2123 | goto out_no_slave_reg; |
| 2124 | } |
| 2125 | |
| 2126 | amba_set_drvdata(adev, pl08x); |
| 2127 | init_pl08x_debugfs(pl08x); |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 2128 | dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n", |
| 2129 | amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev), |
Russell King - ARM Linux | b05cd8f | 2011-01-03 22:33:26 +0000 | [diff] [blame] | 2130 | (unsigned long long)adev->res.start, adev->irq[0]); |
Viresh Kumar | b7b6018 | 2011-08-05 15:32:33 +0530 | [diff] [blame] | 2131 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2132 | return 0; |
| 2133 | |
| 2134 | out_no_slave_reg: |
| 2135 | dma_async_device_unregister(&pl08x->memcpy); |
| 2136 | out_no_memcpy_reg: |
| 2137 | pl08x_free_virtual_channels(&pl08x->slave); |
| 2138 | out_no_slave: |
| 2139 | pl08x_free_virtual_channels(&pl08x->memcpy); |
| 2140 | out_no_memcpy: |
| 2141 | kfree(pl08x->phy_chans); |
| 2142 | out_no_phychans: |
| 2143 | free_irq(adev->irq[0], pl08x); |
| 2144 | out_no_irq: |
| 2145 | iounmap(pl08x->base); |
| 2146 | out_no_ioremap: |
| 2147 | dma_pool_destroy(pl08x->pool); |
| 2148 | out_no_lli_pool: |
| 2149 | out_no_platdata: |
| 2150 | kfree(pl08x); |
| 2151 | out_no_pl08x: |
| 2152 | amba_release_regions(adev); |
| 2153 | return ret; |
| 2154 | } |
| 2155 | |
| 2156 | /* PL080 has 8 channels and the PL080 have just 2 */ |
| 2157 | static struct vendor_data vendor_pl080 = { |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 2158 | .config_offset = PL080_CH_CONFIG, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2159 | .channels = 8, |
| 2160 | .dualmaster = true, |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 2161 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2162 | }; |
| 2163 | |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2164 | static struct vendor_data vendor_nomadik = { |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 2165 | .config_offset = PL080_CH_CONFIG, |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2166 | .channels = 8, |
| 2167 | .dualmaster = true, |
| 2168 | .nomadik = true, |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 2169 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2170 | }; |
| 2171 | |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 2172 | static struct vendor_data vendor_pl080s = { |
| 2173 | .config_offset = PL080S_CH_CONFIG, |
| 2174 | .channels = 8, |
| 2175 | .pl080s = true, |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 2176 | .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK, |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 2177 | }; |
| 2178 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2179 | static struct vendor_data vendor_pl081 = { |
Tomasz Figa | d86ccea | 2013-08-11 19:59:14 +0200 | [diff] [blame] | 2180 | .config_offset = PL080_CH_CONFIG, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2181 | .channels = 2, |
| 2182 | .dualmaster = false, |
Tomasz Figa | 5110e51 | 2013-08-11 19:59:18 +0200 | [diff] [blame] | 2183 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2184 | }; |
| 2185 | |
| 2186 | static struct amba_id pl08x_ids[] = { |
Tomasz Figa | da1b6c0 | 2013-08-11 19:59:17 +0200 | [diff] [blame] | 2187 | /* Samsung PL080S variant */ |
| 2188 | { |
| 2189 | .id = 0x0a141080, |
| 2190 | .mask = 0xffffffff, |
| 2191 | .data = &vendor_pl080s, |
| 2192 | }, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2193 | /* PL080 */ |
| 2194 | { |
| 2195 | .id = 0x00041080, |
| 2196 | .mask = 0x000fffff, |
| 2197 | .data = &vendor_pl080, |
| 2198 | }, |
| 2199 | /* PL081 */ |
| 2200 | { |
| 2201 | .id = 0x00041081, |
| 2202 | .mask = 0x000fffff, |
| 2203 | .data = &vendor_pl081, |
| 2204 | }, |
| 2205 | /* Nomadik 8815 PL080 variant */ |
| 2206 | { |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2207 | .id = 0x00280080, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2208 | .mask = 0x00ffffff, |
Linus Walleij | affa115 | 2012-04-12 09:01:49 +0200 | [diff] [blame] | 2209 | .data = &vendor_nomadik, |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2210 | }, |
| 2211 | { 0, 0 }, |
| 2212 | }; |
| 2213 | |
Dave Martin | 037566d | 2011-10-05 15:15:20 +0100 | [diff] [blame] | 2214 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
| 2215 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2216 | static struct amba_driver pl08x_amba_driver = { |
| 2217 | .drv.name = DRIVER_NAME, |
| 2218 | .id_table = pl08x_ids, |
| 2219 | .probe = pl08x_probe, |
| 2220 | }; |
| 2221 | |
| 2222 | static int __init pl08x_init(void) |
| 2223 | { |
| 2224 | int retval; |
| 2225 | retval = amba_driver_register(&pl08x_amba_driver); |
| 2226 | if (retval) |
| 2227 | printk(KERN_WARNING DRIVER_NAME |
Russell King - ARM Linux | e8b5e11 | 2011-01-03 22:30:24 +0000 | [diff] [blame] | 2228 | "failed to register as an AMBA device (%d)\n", |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 2229 | retval); |
| 2230 | return retval; |
| 2231 | } |
| 2232 | subsys_initcall(pl08x_init); |