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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Ken Zhang420dd202013-01-08 14:28:20 -05004 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070053#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Kalyan Thota9284a272012-11-02 20:55:30 +053074#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053075#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
Ken Zhang4e83b932012-12-02 21:15:47 -050076 struct mdp_display_commit)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053077#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
Ken Zhang420dd202013-01-08 14:28:20 -050078#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Deva Ramasubramanian166b0982013-01-25 20:11:41 -080079#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
80 unsigned int)
Terence Hampson3e636aa2013-05-08 19:01:51 -040081#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
Kuogee Hsieha77eca62012-09-13 13:22:04 -070082
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070083#define FB_TYPE_3D_PANEL 0x10101010
84#define MDP_IMGTYPE2_START 0x10000
85#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070086
87enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088 NOTIFY_UPDATE_START,
89 NOTIFY_UPDATE_STOP,
90};
91
92enum {
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070093 NOTIFY_TYPE_NO_UPDATE,
94 NOTIFY_TYPE_SUSPEND,
95 NOTIFY_TYPE_UPDATE,
96};
97
98enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070099 MDP_RGB_565, /* RGB 565 planer */
100 MDP_XRGB_8888, /* RGB 888 padded */
101 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +0530102 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700103 MDP_ARGB_8888, /* ARGB 888 */
104 MDP_RGB_888, /* RGB 888 planer */
105 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
106 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
Pawan Kumar42acdef2013-03-21 19:55:49 +0530107 MDP_CBYCRY_H2V1, /* CbYCrY interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700108 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
109 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700110 MDP_Y_CRCB_H1V2,
111 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700112 MDP_RGBA_8888, /* ARGB 888 */
113 MDP_BGRA_8888, /* ABGR 888 */
114 MDP_RGBX_8888, /* RGBX 888 */
115 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
116 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
117 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530118 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700119 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
120 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
121 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700122 MDP_YCRCB_H1V1, /* YCrCb interleave */
123 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700124 MDP_BGR_565, /* BGR 565 planer */
Adrian Salido-Morenod559ef12012-07-12 20:16:14 -0700125 MDP_BGR_888, /* BGR 888 */
Adrian Salido-Moreno330c0bf2012-08-22 14:15:33 -0700126 MDP_Y_CBCR_H2V2_VENUS,
Pawan Kumar79854382013-02-14 15:27:12 +0530127 MDP_BGRX_8888, /* BGRX 8888 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700128 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800129 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700130 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700131 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700132};
133
134enum {
135 PMEM_IMG,
136 FB_IMG,
137};
138
Liyuan Lid9736632011-11-11 13:47:59 -0800139enum {
140 HSIC_HUE = 0,
141 HSIC_SAT,
142 HSIC_INT,
143 HSIC_CON,
144 NUM_HSIC_PARAM,
145};
146
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700147#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700148#define MDSS_MDP_RIGHT_MIXER 0x100
149
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150/* mdp_blit_req flag values */
151#define MDP_ROT_NOP 0
152#define MDP_FLIP_LR 0x1
153#define MDP_FLIP_UD 0x2
154#define MDP_ROT_90 0x4
155#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
156#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
157#define MDP_DITHER 0x8
158#define MDP_BLUR 0x10
159#define MDP_BLEND_FG_PREMULT 0x20000
Padmanabhan Komandurudd10bf12012-10-17 20:27:33 +0530160#define MDP_IS_FG 0x40000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700161#define MDP_DEINTERLACE 0x80000000
162#define MDP_SHARPENING 0x40000000
163#define MDP_NO_DMA_BARRIER_START 0x20000000
164#define MDP_NO_DMA_BARRIER_END 0x10000000
165#define MDP_NO_BLIT 0x08000000
166#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
167#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
168 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
169#define MDP_BLIT_SRC_GEM 0x04000000
170#define MDP_BLIT_DST_GEM 0x02000000
171#define MDP_BLIT_NON_CACHED 0x01000000
172#define MDP_OV_PIPE_SHARE 0x00800000
173#define MDP_DEINTERLACE_ODD 0x00400000
174#define MDP_OV_PLAY_NOWAIT 0x00200000
175#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700176#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530177#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800178#define MDP_BORDERFILL_SUPPORTED 0x00010000
179#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Adrian Salido-Moreno9a8485c2013-02-06 14:08:28 -0800180#define MDP_OV_PIPE_FORCE_DMA 0x00004000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800181#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Sree Sesha Aravind Vadrevu35143132013-03-12 02:32:06 -0700182#define MDP_BWC_EN 0x00000400
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700183#define MDP_DECIMATION_EN 0x00000800
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700184#define MDP_TRANSP_NOP 0xffffffff
185#define MDP_ALPHA_NOP 0xff
186
187#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
188#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
189#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
190#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
191#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
192/* Sentinel: Don't use! */
193#define MDP_FB_PAGE_PROTECTION_INVALID (5)
194/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
195#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700196
197struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700198 uint32_t x;
199 uint32_t y;
200 uint32_t w;
201 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700202};
203
204struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700205 uint32_t width;
206 uint32_t height;
207 uint32_t format;
208 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700209 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700210 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700211};
212
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700213/*
214 * {3x3} + {3} ccs matrix
215 */
216
217#define MDP_CCS_RGB2YUV 0
218#define MDP_CCS_YUV2RGB 1
219
220#define MDP_CCS_SIZE 9
221#define MDP_BV_SIZE 3
222
223struct mdp_ccs {
224 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
225 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
226 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
227};
228
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800229struct mdp_csc {
230 int id;
231 uint32_t csc_mv[9];
232 uint32_t csc_pre_bv[3];
233 uint32_t csc_post_bv[3];
234 uint32_t csc_pre_lv[6];
235 uint32_t csc_post_lv[6];
236};
237
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700238/* The version of the mdp_blit_req structure so that
239 * user applications can selectively decide which functionality
240 * to include
241 */
242
243#define MDP_BLIT_REQ_VERSION 2
244
Daniel Walkerda6df072010-04-23 16:04:20 -0700245struct mdp_blit_req {
246 struct mdp_img src;
247 struct mdp_img dst;
248 struct mdp_rect src_rect;
249 struct mdp_rect dst_rect;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700250 uint32_t alpha;
251 uint32_t transp_mask;
252 uint32_t flags;
253 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700254};
255
256struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700257 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700258 struct mdp_blit_req req[];
259};
260
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700261#define MSMFB_DATA_VERSION 2
262
263struct msmfb_data {
264 uint32_t offset;
265 int memory_id;
266 int id;
267 uint32_t flags;
268 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800269 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270};
271
272#define MSMFB_NEW_REQUEST -1
273
274struct msmfb_overlay_data {
275 uint32_t id;
276 struct msmfb_data data;
277 uint32_t version_key;
278 struct msmfb_data plane1_data;
279 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700280 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700281};
282
283struct msmfb_img {
284 uint32_t width;
285 uint32_t height;
286 uint32_t format;
287};
288
Vinay Kalia27020d12011-10-14 17:50:29 -0700289#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
290struct msmfb_writeback_data {
291 struct msmfb_data buf_info;
292 struct msmfb_img img;
293};
294
Ken Zhang77ce0192012-08-10 11:27:19 -0400295#define MDP_PP_OPS_ENABLE 0x1
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700296#define MDP_PP_OPS_READ 0x2
297#define MDP_PP_OPS_WRITE 0x4
Ken Zhang77ce0192012-08-10 11:27:19 -0400298#define MDP_PP_OPS_DISABLE 0x8
Ken Zhang824758e2012-08-15 11:02:21 -0400299#define MDP_PP_IGC_FLAG_ROM0 0x10
300#define MDP_PP_IGC_FLAG_ROM1 0x20
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700301
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700302#define MDSS_PP_DSPP_CFG 0x000
303#define MDSS_PP_SSPP_CFG 0x100
304#define MDSS_PP_LM_CFG 0x200
305#define MDSS_PP_WB_CFG 0x300
Ping Li8231ae42013-01-09 20:39:25 -0500306
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700307#define MDSS_PP_ARG_MASK 0x3C00
308#define MDSS_PP_ARG_NUM 4
Carl Vanderlip793aa582013-03-18 10:18:47 -0700309#define MDSS_PP_ARG_SHIFT 10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700310#define MDSS_PP_LOCATION_MASK 0x0300
311#define MDSS_PP_LOGICAL_MASK 0x00FF
Ping Li8231ae42013-01-09 20:39:25 -0500312
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700313#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
314#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
Ping Li8231ae42013-01-09 20:39:25 -0500315#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
316#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
317
318
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700319struct mdp_qseed_cfg {
320 uint32_t table_num;
321 uint32_t ops;
322 uint32_t len;
323 uint32_t *data;
324};
325
Ping Li87cca832013-01-30 18:27:52 -0500326struct mdp_sharp_cfg {
327 uint32_t flags;
328 uint32_t strength;
329 uint32_t edge_thr;
330 uint32_t smooth_thr;
331 uint32_t noise_thr;
332};
333
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700334struct mdp_qseed_cfg_data {
335 uint32_t block;
336 struct mdp_qseed_cfg qseed_data;
337};
338
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800339#define MDP_OVERLAY_PP_CSC_CFG 0x1
340#define MDP_OVERLAY_PP_QSEED_CFG 0x2
341#define MDP_OVERLAY_PP_PA_CFG 0x4
342#define MDP_OVERLAY_PP_IGC_CFG 0x8
Ping Li87cca832013-01-30 18:27:52 -0500343#define MDP_OVERLAY_PP_SHARP_CFG 0x10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700344#define MDP_OVERLAY_PP_HIST_CFG 0x20
Carl Vanderlip57027132013-03-18 13:53:16 -0700345#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700346
347#define MDP_CSC_FLAG_ENABLE 0x1
348#define MDP_CSC_FLAG_YUV_IN 0x2
349#define MDP_CSC_FLAG_YUV_OUT 0x4
350
351struct mdp_csc_cfg {
352 /* flags for enable CSC, toggling RGB,YUV input/output */
353 uint32_t flags;
354 uint32_t csc_mv[9];
355 uint32_t csc_pre_bv[3];
356 uint32_t csc_post_bv[3];
357 uint32_t csc_pre_lv[6];
358 uint32_t csc_post_lv[6];
359};
360
361struct mdp_csc_cfg_data {
362 uint32_t block;
363 struct mdp_csc_cfg csc_data;
364};
365
Ping Li58229242012-11-30 14:05:43 -0500366struct mdp_pa_cfg {
367 uint32_t flags;
368 uint32_t hue_adj;
369 uint32_t sat_adj;
370 uint32_t val_adj;
371 uint32_t cont_adj;
372};
373
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800374struct mdp_igc_lut_data {
375 uint32_t block;
376 uint32_t len, ops;
377 uint32_t *c0_c1_data;
378 uint32_t *c2_data;
379};
380
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700381struct mdp_histogram_cfg {
382 uint32_t ops;
383 uint32_t block;
384 uint8_t frame_cnt;
385 uint8_t bit_mask;
386 uint16_t num_bins;
387};
388
Carl Vanderlip57027132013-03-18 13:53:16 -0700389struct mdp_hist_lut_data {
390 uint32_t block;
391 uint32_t ops;
392 uint32_t len;
393 uint32_t *data;
394};
395
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700396struct mdp_overlay_pp_params {
397 uint32_t config_ops;
398 struct mdp_csc_cfg csc_cfg;
399 struct mdp_qseed_cfg qseed_cfg[2];
Ping Li58229242012-11-30 14:05:43 -0500400 struct mdp_pa_cfg pa_cfg;
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800401 struct mdp_igc_lut_data igc_cfg;
Ping Li87cca832013-01-30 18:27:52 -0500402 struct mdp_sharp_cfg sharp_cfg;
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700403 struct mdp_histogram_cfg hist_cfg;
Carl Vanderlip57027132013-03-18 13:53:16 -0700404 struct mdp_hist_lut_data hist_lut_cfg;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700405};
406
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700407struct mdp_overlay {
408 struct msmfb_img src;
409 struct mdp_rect src_rect;
410 struct mdp_rect dst_rect;
411 uint32_t z_order; /* stage number */
412 uint32_t is_fg; /* control alpha & transp */
413 uint32_t alpha;
414 uint32_t transp_mask;
415 uint32_t flags;
416 uint32_t id;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700417 uint32_t user_data[7];
418 uint8_t horz_deci;
419 uint8_t vert_deci;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700420 struct mdp_overlay_pp_params overlay_pp_cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700421};
422
423struct msmfb_overlay_3d {
424 uint32_t is_3d;
425 uint32_t width;
426 uint32_t height;
427};
428
429
430struct msmfb_overlay_blt {
431 uint32_t enable;
432 uint32_t offset;
433 uint32_t width;
434 uint32_t height;
435 uint32_t bpp;
436};
437
438struct mdp_histogram {
439 uint32_t frame_cnt;
440 uint32_t bin_cnt;
441 uint32_t *r;
442 uint32_t *g;
443 uint32_t *b;
444};
445
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700446enum {
447 DISPLAY_MISR_EDP,
448 DISPLAY_MISR_DSI0,
449 DISPLAY_MISR_DSI1,
450 DISPLAY_MISR_HDMI,
451 DISPLAY_MISR_LCDC,
452 DISPLAY_MISR_ATV,
453 DISPLAY_MISR_DSI_CMD,
454 DISPLAY_MISR_MAX
455};
456
457enum {
458 MISR_OP_NONE,
459 MISR_OP_SFM,
460 MISR_OP_MFM,
461 MISR_OP_BM,
462 MISR_OP_MAX
463};
464
465struct mdp_misr {
466 uint32_t block_id;
467 uint32_t frame_count;
468 uint32_t crc_op_mode;
469 uint32_t crc_value[32];
470};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800471
472/*
473
Ken Zhang6a431632012-08-08 16:46:22 -0400474 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800475
476 MDP_BLOCK_RESERVED is provided for backward compatibility and is
477 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
478 instead.
479
Ken Zhang6a431632012-08-08 16:46:22 -0400480 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
481 same for others.
482
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800483*/
484
485enum {
486 MDP_BLOCK_RESERVED = 0,
487 MDP_BLOCK_OVERLAY_0,
488 MDP_BLOCK_OVERLAY_1,
489 MDP_BLOCK_VG_1,
490 MDP_BLOCK_VG_2,
491 MDP_BLOCK_RGB_1,
492 MDP_BLOCK_RGB_2,
493 MDP_BLOCK_DMA_P,
494 MDP_BLOCK_DMA_S,
495 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700496 MDP_BLOCK_OVERLAY_2,
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700497 MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
Ken Zhang6a431632012-08-08 16:46:22 -0400498 MDP_LOGICAL_BLOCK_DISP_1,
499 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800500 MDP_BLOCK_MAX,
501};
502
Carl Vanderlipba093a22011-11-22 13:59:59 -0800503/*
504 * mdp_histogram_start_req is used to provide the parameters for
505 * histogram start request
506 */
507
508struct mdp_histogram_start_req {
509 uint32_t block;
510 uint8_t frame_cnt;
511 uint8_t bit_mask;
Carl Vanderlip16316322012-10-08 16:47:34 -0700512 uint16_t num_bins;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800513};
514
515/*
516 * mdp_histogram_data is used to return the histogram data, once
517 * the histogram is done/stopped/cance
518 */
519
520struct mdp_histogram_data {
521 uint32_t block;
Ken Zhang0f523bd2012-08-23 11:14:03 -0400522 uint32_t bin_cnt;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800523 uint32_t *c0;
524 uint32_t *c1;
525 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800526 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800527};
528
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800529struct mdp_pcc_coeff {
530 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
531};
532
533struct mdp_pcc_cfg_data {
534 uint32_t block;
535 uint32_t ops;
536 struct mdp_pcc_coeff r, g, b;
537};
538
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400539#define MDP_GAMUT_TABLE_NUM 8
540
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800541enum {
542 mdp_lut_igc,
543 mdp_lut_pgc,
544 mdp_lut_hist,
545 mdp_lut_max,
546};
547
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800548struct mdp_ar_gc_lut_data {
549 uint32_t x_start;
550 uint32_t slope;
551 uint32_t offset;
552};
553
554struct mdp_pgc_lut_data {
555 uint32_t block;
556 uint32_t flags;
557 uint8_t num_r_stages;
558 uint8_t num_g_stages;
559 uint8_t num_b_stages;
560 struct mdp_ar_gc_lut_data *r_data;
561 struct mdp_ar_gc_lut_data *g_data;
562 struct mdp_ar_gc_lut_data *b_data;
563};
564
565
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800566struct mdp_lut_cfg_data {
567 uint32_t lut_type;
568 union {
569 struct mdp_igc_lut_data igc_lut_data;
570 struct mdp_pgc_lut_data pgc_lut_data;
571 struct mdp_hist_lut_data hist_lut_data;
572 } data;
573};
574
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700575struct mdp_bl_scale_data {
576 uint32_t min_lvl;
577 uint32_t scale;
578};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700579
Ken Zhang77ce0192012-08-10 11:27:19 -0400580struct mdp_pa_cfg_data {
581 uint32_t block;
Ping Li58229242012-11-30 14:05:43 -0500582 struct mdp_pa_cfg pa_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400583};
584
Ken Zhang7fb85772012-08-18 14:51:33 -0400585struct mdp_dither_cfg_data {
586 uint32_t block;
587 uint32_t flags;
588 uint32_t g_y_depth;
589 uint32_t r_cr_depth;
590 uint32_t b_cb_depth;
591};
592
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400593struct mdp_gamut_cfg_data {
594 uint32_t block;
595 uint32_t flags;
596 uint32_t gamut_first;
597 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
598 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
599 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
600 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
601};
602
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700603struct mdp_calib_config_data {
604 uint32_t ops;
605 uint32_t addr;
606 uint32_t data;
607};
608
Arpita Banerjee676eea22013-06-04 19:43:24 -0700609struct mdp_calib_config_buffer {
610 uint32_t ops;
611 uint32_t size;
612 uint32_t *buffer;
613};
614
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700615#define MDSS_MAX_BL_BRIGHTNESS 255
616#define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1)
617
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700618#define MDSS_AD_MODE_AUTO_BL 0x0
619#define MDSS_AD_MODE_AUTO_STR 0x1
620#define MDSS_AD_MODE_TARG_STR 0x3
621#define MDSS_AD_MODE_MAN_STR 0x7
Carl Vanderlip819c5092013-05-19 12:08:33 -0700622#define MDSS_AD_MODE_CALIB 0xF
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700623
624#define MDP_PP_AD_INIT 0x10
625#define MDP_PP_AD_CFG 0x20
626
627struct mdss_ad_init {
628 uint32_t asym_lut[33];
629 uint32_t color_corr_lut[33];
630 uint8_t i_control[2];
631 uint16_t black_lvl;
632 uint16_t white_lvl;
633 uint8_t var;
634 uint8_t limit_ampl;
635 uint8_t i_dither;
636 uint8_t slope_max;
637 uint8_t slope_min;
638 uint8_t dither_ctl;
639 uint8_t format;
640 uint8_t auto_size;
641 uint16_t frame_w;
642 uint16_t frame_h;
643 uint8_t logo_v;
644 uint8_t logo_h;
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700645 uint32_t bl_lin_len;
646 uint32_t *bl_lin;
647 uint32_t *bl_lin_inv;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700648};
649
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700650#define MDSS_AD_BL_CTRL_MODE_EN 1
651#define MDSS_AD_BL_CTRL_MODE_DIS 0
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700652struct mdss_ad_cfg {
653 uint32_t mode;
654 uint32_t al_calib_lut[33];
655 uint16_t backlight_min;
656 uint16_t backlight_max;
657 uint16_t backlight_scale;
658 uint16_t amb_light_min;
659 uint16_t filter[2];
660 uint16_t calib[4];
661 uint8_t strength_limit;
662 uint8_t t_filter_recursion;
Carl Vanderlip956360e2013-04-04 20:57:17 -0700663 uint16_t stab_itr;
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700664 uint32_t bl_ctrl_mode;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700665};
666
667/* ops uses standard MDP_PP_* flags */
668struct mdss_ad_init_cfg {
669 uint32_t ops;
670 union {
671 struct mdss_ad_init init;
672 struct mdss_ad_cfg cfg;
673 } params;
674};
675
676/* mode uses MDSS_AD_MODE_* flags */
677struct mdss_ad_input {
678 uint32_t mode;
679 union {
680 uint32_t amb_light;
681 uint32_t strength;
Carl Vanderlip819c5092013-05-19 12:08:33 -0700682 uint32_t calib_bl;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700683 } in;
Carl Vanderlip16e79532013-04-02 11:12:16 -0700684 uint32_t output;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700685};
686
Carl Vanderlipa088b7c2013-05-17 13:52:53 -0700687#define MDSS_CALIB_MODE_BL 0x1
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700688struct mdss_calib_cfg {
689 uint32_t ops;
690 uint32_t calib_mask;
691};
692
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800693enum {
694 mdp_op_pcc_cfg,
695 mdp_op_csc_cfg,
696 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700697 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700698 mdp_bl_scale_cfg,
Ken Zhang77ce0192012-08-10 11:27:19 -0400699 mdp_op_pa_cfg,
Ken Zhang7fb85772012-08-18 14:51:33 -0400700 mdp_op_dither_cfg,
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400701 mdp_op_gamut_cfg,
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700702 mdp_op_calib_cfg,
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700703 mdp_op_ad_cfg,
704 mdp_op_ad_input,
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700705 mdp_op_calib_mode,
Arpita Banerjee676eea22013-06-04 19:43:24 -0700706 mdp_op_calib_buffer,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800707 mdp_op_max,
708};
709
Pawan Kumar9807ea12013-02-14 18:12:02 +0530710enum {
711 WB_FORMAT_NV12,
712 WB_FORMAT_RGB_565,
713 WB_FORMAT_RGB_888,
714 WB_FORMAT_xRGB_8888,
715 WB_FORMAT_ARGB_8888,
Pawan Kumaree811932013-07-09 15:45:01 +0530716 WB_FORMAT_BGRA_8888,
717 WB_FORMAT_BGRX_8888,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530718 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
719};
720
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800721struct msmfb_mdp_pp {
722 uint32_t op;
723 union {
724 struct mdp_pcc_cfg_data pcc_cfg_data;
725 struct mdp_csc_cfg_data csc_cfg_data;
726 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700727 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700728 struct mdp_bl_scale_data bl_scale_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400729 struct mdp_pa_cfg_data pa_cfg_data;
Ken Zhang7fb85772012-08-18 14:51:33 -0400730 struct mdp_dither_cfg_data dither_cfg_data;
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400731 struct mdp_gamut_cfg_data gamut_cfg_data;
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700732 struct mdp_calib_config_data calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700733 struct mdss_ad_init_cfg ad_init_cfg;
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700734 struct mdss_calib_cfg mdss_calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700735 struct mdss_ad_input ad_input;
Arpita Banerjee676eea22013-06-04 19:43:24 -0700736 struct mdp_calib_config_buffer calib_buffer;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800737 } data;
738};
739
Manoj Raoa8e39d92013-02-16 08:47:21 -0800740#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
Ken Zhang5cf85c02012-08-23 19:32:52 -0700741enum {
742 metadata_op_none,
743 metadata_op_base_blend,
Ken Zhang420dd202013-01-08 14:28:20 -0500744 metadata_op_frame_rate,
Manoj Raoa8e39d92013-02-16 08:47:21 -0800745 metadata_op_vic,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530746 metadata_op_wb_format,
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800747 metadata_op_get_caps,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700748 metadata_op_crc,
Ken Zhang5cf85c02012-08-23 19:32:52 -0700749 metadata_op_max
750};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800751
Ken Zhang5cf85c02012-08-23 19:32:52 -0700752struct mdp_blend_cfg {
753 uint32_t is_premultiplied;
754};
755
Pawan Kumar9807ea12013-02-14 18:12:02 +0530756struct mdp_mixer_cfg {
757 uint32_t writeback_format;
758 uint32_t alpha;
759};
760
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800761struct mdss_hw_caps {
762 uint32_t mdp_rev;
763 uint8_t rgb_pipes;
764 uint8_t vig_pipes;
765 uint8_t dma_pipes;
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700766 uint32_t features;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800767};
768
Ken Zhang5cf85c02012-08-23 19:32:52 -0700769struct msmfb_metadata {
770 uint32_t op;
771 uint32_t flags;
772 union {
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700773 struct mdp_misr misr_request;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700774 struct mdp_blend_cfg blend_cfg;
Pawan Kumar9807ea12013-02-14 18:12:02 +0530775 struct mdp_mixer_cfg mixer_cfg;
Ken Zhang420dd202013-01-08 14:28:20 -0500776 uint32_t panel_frame_rate;
Manoj Raoa8e39d92013-02-16 08:47:21 -0800777 uint32_t video_info_code;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800778 struct mdss_hw_caps caps;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700779 } data;
780};
Ken Zhang5295d802012-11-07 18:33:16 -0500781
Adrian Salido-Moreno1a74a492013-05-11 21:24:43 -0700782#define MDP_MAX_FENCE_FD 32
Ken Zhang5295d802012-11-07 18:33:16 -0500783#define MDP_BUF_SYNC_FLAG_WAIT 1
784
785struct mdp_buf_sync {
786 uint32_t flags;
787 uint32_t acq_fen_fd_cnt;
788 int *acq_fen_fd;
789 int *rel_fen_fd;
790};
791
Terence Hampson3e636aa2013-05-08 19:01:51 -0400792struct mdp_async_blit_req_list {
793 struct mdp_buf_sync sync;
794 uint32_t count;
795 struct mdp_blit_req req[];
796};
797
Ken Zhang4e83b932012-12-02 21:15:47 -0500798#define MDP_DISPLAY_COMMIT_OVERLAY 1
Ken Zhang5e8588d2012-10-01 11:46:42 -0700799struct mdp_buf_fence {
800 uint32_t flags;
801 uint32_t acq_fen_fd_cnt;
802 int acq_fen_fd[MDP_MAX_FENCE_FD];
803 int rel_fen_fd[MDP_MAX_FENCE_FD];
804};
805
Ken Zhang4e83b932012-12-02 21:15:47 -0500806
807struct mdp_display_commit {
808 uint32_t flags;
809 uint32_t wait_for_finish;
810 struct fb_var_screeninfo var;
Ken Zhang5e8588d2012-10-01 11:46:42 -0700811 struct mdp_buf_fence buf_fence;
Ken Zhang4e83b932012-12-02 21:15:47 -0500812};
813
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700814struct mdp_page_protection {
815 uint32_t page_protection;
816};
817
kuogee hsieh405dc302011-07-21 15:06:59 -0700818
819struct mdp_mixer_info {
820 int pndx;
821 int pnum;
822 int ptype;
823 int mixer_num;
824 int z_order;
825};
826
827#define MAX_PIPE_PER_MIXER 4
828
829struct msmfb_mixer_info_req {
830 int mixer_num;
831 int cnt;
832 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
833};
834
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700835enum {
836 DISPLAY_SUBSYSTEM_ID,
837 ROTATOR_SUBSYSTEM_ID,
838};
kuogee hsieh405dc302011-07-21 15:06:59 -0700839
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800840enum {
841 MDP_IOMMU_DOMAIN_CP,
842 MDP_IOMMU_DOMAIN_NS,
843};
844
Deva Ramasubramanian166b0982013-01-25 20:11:41 -0800845enum {
846 MDP_WRITEBACK_MIRROR_OFF,
847 MDP_WRITEBACK_MIRROR_ON,
848 MDP_WRITEBACK_MIRROR_PAUSE,
849 MDP_WRITEBACK_MIRROR_RESUME,
850};
851
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700852#ifdef __KERNEL__
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800853int msm_fb_get_iommu_domain(struct fb_info *info, int domain);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700854/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700855int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
856 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -0700857struct fb_info *msm_fb_get_writeback_fb(void);
858int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800859int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700860int msm_fb_writeback_queue_buffer(struct fb_info *info,
861 struct msmfb_data *data);
862int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
863 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800864int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700865int msm_fb_writeback_terminate(struct fb_info *info);
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800866int msm_fb_writeback_set_secure(struct fb_info *info, int enable);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700867#endif
868
869#endif /*_MSM_MDP_H_*/