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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
29#ifndef CMD_H
30#define CMD_H
31
32#include "intel.h"
33#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080034#include "view.h"
35
36struct intel_pipeline;
Chia-I Wuf2b6d722014-09-02 08:52:27 +080037struct intel_pipeline_shader;
Chia-I Wub2755562014-08-20 13:38:52 +080038struct intel_pipeline_delta;
39struct intel_viewport_state;
40struct intel_raster_state;
41struct intel_msaa_state;
42struct intel_blend_state;
43struct intel_ds_state;
44struct intel_dset;
45
Chia-I Wu00b51a82014-09-09 12:07:37 +080046struct intel_cmd_item;
Chia-I Wu958d1b72014-08-21 11:28:11 +080047struct intel_cmd_reloc;
48
Chia-I Wu8370b402014-08-29 12:28:37 +080049/*
50 * We know what workarounds are needed for intel_pipeline. These are mostly
51 * for intel_pipeline_delta.
52 */
53enum intel_cmd_wa_flags {
54 /*
55 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
56 *
57 * "Before any depth stall flush (including those produced by
58 * non-pipelined state commands), software needs to first send a
59 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
60 */
61 INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE = 1 << 0,
62
63 /*
64 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
65 *
66 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
67 * field set (DW1 Bit 1), must be issued prior to any change to the
68 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
69 *
70 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
71 *
72 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
73 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
74 * Pixel Scoreboard set is required to be issued."
75 */
76 INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL = 1 << 1,
77
78 /*
79 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
80 *
81 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
82 * stall needs to be sent just prior to any 3DSTATE_VS,
83 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
84 * 3DSTATE_BINDING_TABLE_POINTER_VS, 3DSTATE_SAMPLER_STATE_POINTER_VS
85 * command. Only one PIPE_CONTROL needs to be sent before any
86 * combination of VS associated 3DSTATE."
87 */
88 INTEL_CMD_WA_GEN7_PRE_VS_DEPTH_STALL_WRITE = 1 << 2,
89
90 /*
91 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
92 *
93 * "Due to an HW issue driver needs to send a pipe control with stall
94 * when ever there is state change in depth bias related state"
95 *
96 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
97 *
98 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
99 * in the ring after this instruction
100 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
101 */
102 INTEL_CMD_WA_GEN7_POST_COMMAND_CS_STALL = 1 << 3,
103
104 /*
105 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
106 *
107 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
108 * Enable bit set after all the following states are programmed:
109 *
110 * - 3DSTATE_PS
111 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
112 * - 3DSTATE_CONSTANT_PS
113 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
114 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
115 * - 3DSTATE_CC_STATE_POINTERS
116 * - 3DSTATE_BLEND_STATE_POINTERS
117 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
118 */
119 INTEL_CMD_WA_GEN7_POST_COMMAND_DEPTH_STALL = 1 << 4,
120};
121
Chia-I Wu68f319d2014-09-09 09:43:21 +0800122enum intel_cmd_writer_type {
123 INTEL_CMD_WRITER_BATCH,
124 INTEL_CMD_WRITER_STATE,
125 INTEL_CMD_WRITER_INSTRUCTION,
126
127 INTEL_CMD_WRITER_COUNT,
128};
129
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600130struct intel_cmd_shader {
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800131 const struct intel_pipeline_shader *shader;
Chia-I Wu72292b72014-09-09 10:48:33 +0800132 uint32_t kernel_offset;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600133};
134
Chia-I Wub2755562014-08-20 13:38:52 +0800135/*
136 * States bounded to the command buffer. We want to write states directly to
137 * the command buffer when possible, and reduce this struct.
138 */
139struct intel_cmd_bind {
140 struct {
141 const struct intel_pipeline *graphics;
142 const struct intel_pipeline *compute;
143 const struct intel_pipeline_delta *graphics_delta;
144 const struct intel_pipeline_delta *compute_delta;
145 } pipeline;
146
Courtney Goeltzenleuchterba305812014-08-28 17:27:47 -0600147 /*
148 * Currently active shaders for this command buffer.
149 * Provides data only available after shaders are bound to
150 * a command buffer, such as the kernel position in the kernel BO
151 */
152 struct intel_cmd_shader vs;
153 struct intel_cmd_shader fs;
154 struct intel_cmd_shader gs;
Chia-I Wu95959fb2014-09-02 11:01:03 +0800155 struct intel_cmd_shader tcs;
156 struct intel_cmd_shader tes;
157 struct intel_cmd_shader cs;
Courtney Goeltzenleuchterba305812014-08-28 17:27:47 -0600158
Chia-I Wub2755562014-08-20 13:38:52 +0800159 struct {
Chia-I Wu338fe642014-08-28 10:43:04 +0800160 XGL_UINT count;
161 XGL_UINT used;
162 struct intel_cmd_shader *shaderArray;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600163 } shaderCache;
164
165 struct {
Chia-I Wub2755562014-08-20 13:38:52 +0800166 const struct intel_viewport_state *viewport;
167 const struct intel_raster_state *raster;
168 const struct intel_msaa_state *msaa;
169 const struct intel_blend_state *blend;
170 const struct intel_ds_state *ds;
171 } state;
172
173 struct {
174 const struct intel_dset *graphics;
175 XGL_UINT graphics_offset;
176 const struct intel_dset *compute;
177 XGL_UINT compute_offset;
178 } dset;
179
180 struct {
181 struct intel_mem_view graphics;
182 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +0800183 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +0800184
185 struct {
186 const struct intel_mem *mem;
187 XGL_GPU_SIZE offset;
188 XGL_INDEX_TYPE type;
189 } index;
190
191 struct {
192 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
193 XGL_UINT rt_count;
194
195 const struct intel_ds_view *ds;
Chia-I Wu2e5ec9b2014-10-14 13:37:21 +0800196
197 XGL_UINT width, height;
Chia-I Wub2755562014-08-20 13:38:52 +0800198 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800199
Chia-I Wu707a29e2014-08-27 12:51:47 +0800200 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800201 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +0800202};
Chia-I Wu09142132014-08-11 15:42:55 +0800203
Chia-I Wue24c3292014-08-21 14:05:23 +0800204struct intel_cmd_writer {
Chia-I Wu72292b72014-09-09 10:48:33 +0800205 XGL_SIZE size;
Chia-I Wue24c3292014-08-21 14:05:23 +0800206 struct intel_bo *bo;
Chia-I Wu0f50ba82014-09-09 10:25:46 +0800207 void *ptr;
Chia-I Wue24c3292014-08-21 14:05:23 +0800208
Chia-I Wu72292b72014-09-09 10:48:33 +0800209 XGL_SIZE used;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800210
211 /* for decoding */
212 struct intel_cmd_item *items;
213 XGL_UINT item_alloc;
214 XGL_UINT item_used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800215};
216
Chia-I Wu730e5362014-08-19 12:15:09 +0800217struct intel_cmd {
218 struct intel_obj obj;
219
220 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800221 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800222 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800223
Chia-I Wu343b1372014-08-20 16:39:20 +0800224 struct intel_cmd_reloc *relocs;
225 XGL_UINT reloc_count;
226
Chia-I Wu730e5362014-08-19 12:15:09 +0800227 XGL_FLAGS flags;
228
Chia-I Wu68f319d2014-09-09 09:43:21 +0800229 struct intel_cmd_writer writers[INTEL_CMD_WRITER_COUNT];
Chia-I Wu730e5362014-08-19 12:15:09 +0800230
Chia-I Wu343b1372014-08-20 16:39:20 +0800231 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800232 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800233
234 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800235};
236
237static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
238{
239 return (struct intel_cmd *) cmd;
240}
241
242static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
243{
244 return (struct intel_cmd *) obj;
245}
246
247XGL_RESULT intel_cmd_create(struct intel_dev *dev,
248 const XGL_CMD_BUFFER_CREATE_INFO *info,
249 struct intel_cmd **cmd_ret);
250void intel_cmd_destroy(struct intel_cmd *cmd);
251
252XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
253XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
254
Chia-I Wu00b51a82014-09-09 12:07:37 +0800255void intel_cmd_decode(struct intel_cmd *cmd);
256
Chia-I Wue24c3292014-08-21 14:05:23 +0800257static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
258 XGL_GPU_SIZE *used)
259{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800260 const struct intel_cmd_writer *writer =
261 &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wue24c3292014-08-21 14:05:23 +0800262
263 if (used)
Chia-I Wu72292b72014-09-09 10:48:33 +0800264 *used = writer->used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800265
266 return writer->bo;
267}
268
Chia-I Wu09142132014-08-11 15:42:55 +0800269XGL_RESULT XGLAPI intelCreateCommandBuffer(
270 XGL_DEVICE device,
271 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
272 XGL_CMD_BUFFER* pCmdBuffer);
273
274XGL_RESULT XGLAPI intelBeginCommandBuffer(
275 XGL_CMD_BUFFER cmdBuffer,
276 XGL_FLAGS flags);
277
278XGL_RESULT XGLAPI intelEndCommandBuffer(
279 XGL_CMD_BUFFER cmdBuffer);
280
281XGL_RESULT XGLAPI intelResetCommandBuffer(
282 XGL_CMD_BUFFER cmdBuffer);
283
284XGL_VOID XGLAPI intelCmdBindPipeline(
285 XGL_CMD_BUFFER cmdBuffer,
286 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
287 XGL_PIPELINE pipeline);
288
289XGL_VOID XGLAPI intelCmdBindPipelineDelta(
290 XGL_CMD_BUFFER cmdBuffer,
291 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
292 XGL_PIPELINE_DELTA delta);
293
294XGL_VOID XGLAPI intelCmdBindStateObject(
295 XGL_CMD_BUFFER cmdBuffer,
296 XGL_STATE_BIND_POINT stateBindPoint,
297 XGL_STATE_OBJECT state);
298
299XGL_VOID XGLAPI intelCmdBindDescriptorSet(
300 XGL_CMD_BUFFER cmdBuffer,
301 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
302 XGL_UINT index,
303 XGL_DESCRIPTOR_SET descriptorSet,
304 XGL_UINT slotOffset);
305
306XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
307 XGL_CMD_BUFFER cmdBuffer,
308 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
309 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
310
311XGL_VOID XGLAPI intelCmdBindIndexData(
312 XGL_CMD_BUFFER cmdBuffer,
313 XGL_GPU_MEMORY mem,
314 XGL_GPU_SIZE offset,
315 XGL_INDEX_TYPE indexType);
316
317XGL_VOID XGLAPI intelCmdBindAttachments(
318 XGL_CMD_BUFFER cmdBuffer,
319 XGL_UINT colorAttachmentCount,
320 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
321 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
322
323XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
324 XGL_CMD_BUFFER cmdBuffer,
325 XGL_UINT transitionCount,
326 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
327
328XGL_VOID XGLAPI intelCmdPrepareImages(
329 XGL_CMD_BUFFER cmdBuffer,
330 XGL_UINT transitionCount,
331 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
332
333XGL_VOID XGLAPI intelCmdDraw(
334 XGL_CMD_BUFFER cmdBuffer,
335 XGL_UINT firstVertex,
336 XGL_UINT vertexCount,
337 XGL_UINT firstInstance,
338 XGL_UINT instanceCount);
339
340XGL_VOID XGLAPI intelCmdDrawIndexed(
341 XGL_CMD_BUFFER cmdBuffer,
342 XGL_UINT firstIndex,
343 XGL_UINT indexCount,
344 XGL_INT vertexOffset,
345 XGL_UINT firstInstance,
346 XGL_UINT instanceCount);
347
348XGL_VOID XGLAPI intelCmdDrawIndirect(
349 XGL_CMD_BUFFER cmdBuffer,
350 XGL_GPU_MEMORY mem,
351 XGL_GPU_SIZE offset,
352 XGL_UINT32 count,
353 XGL_UINT32 stride);
354
355XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
356 XGL_CMD_BUFFER cmdBuffer,
357 XGL_GPU_MEMORY mem,
358 XGL_GPU_SIZE offset,
359 XGL_UINT32 count,
360 XGL_UINT32 stride);
361
362XGL_VOID XGLAPI intelCmdDispatch(
363 XGL_CMD_BUFFER cmdBuffer,
364 XGL_UINT x,
365 XGL_UINT y,
366 XGL_UINT z);
367
368XGL_VOID XGLAPI intelCmdDispatchIndirect(
369 XGL_CMD_BUFFER cmdBuffer,
370 XGL_GPU_MEMORY mem,
371 XGL_GPU_SIZE offset);
372
373XGL_VOID XGLAPI intelCmdCopyMemory(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_GPU_MEMORY srcMem,
376 XGL_GPU_MEMORY destMem,
377 XGL_UINT regionCount,
378 const XGL_MEMORY_COPY* pRegions);
379
380XGL_VOID XGLAPI intelCmdCopyImage(
381 XGL_CMD_BUFFER cmdBuffer,
382 XGL_IMAGE srcImage,
383 XGL_IMAGE destImage,
384 XGL_UINT regionCount,
385 const XGL_IMAGE_COPY* pRegions);
386
387XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
388 XGL_CMD_BUFFER cmdBuffer,
389 XGL_GPU_MEMORY srcMem,
390 XGL_IMAGE destImage,
391 XGL_UINT regionCount,
392 const XGL_MEMORY_IMAGE_COPY* pRegions);
393
394XGL_VOID XGLAPI intelCmdCopyImageToMemory(
395 XGL_CMD_BUFFER cmdBuffer,
396 XGL_IMAGE srcImage,
397 XGL_GPU_MEMORY destMem,
398 XGL_UINT regionCount,
399 const XGL_MEMORY_IMAGE_COPY* pRegions);
400
401XGL_VOID XGLAPI intelCmdCloneImageData(
402 XGL_CMD_BUFFER cmdBuffer,
403 XGL_IMAGE srcImage,
404 XGL_IMAGE_STATE srcImageState,
405 XGL_IMAGE destImage,
406 XGL_IMAGE_STATE destImageState);
407
408XGL_VOID XGLAPI intelCmdUpdateMemory(
409 XGL_CMD_BUFFER cmdBuffer,
410 XGL_GPU_MEMORY destMem,
411 XGL_GPU_SIZE destOffset,
412 XGL_GPU_SIZE dataSize,
413 const XGL_UINT32* pData);
414
415XGL_VOID XGLAPI intelCmdFillMemory(
416 XGL_CMD_BUFFER cmdBuffer,
417 XGL_GPU_MEMORY destMem,
418 XGL_GPU_SIZE destOffset,
419 XGL_GPU_SIZE fillSize,
420 XGL_UINT32 data);
421
422XGL_VOID XGLAPI intelCmdClearColorImage(
423 XGL_CMD_BUFFER cmdBuffer,
424 XGL_IMAGE image,
425 const XGL_FLOAT color[4],
426 XGL_UINT rangeCount,
427 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
428
429XGL_VOID XGLAPI intelCmdClearColorImageRaw(
430 XGL_CMD_BUFFER cmdBuffer,
431 XGL_IMAGE image,
432 const XGL_UINT32 color[4],
433 XGL_UINT rangeCount,
434 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
435
436XGL_VOID XGLAPI intelCmdClearDepthStencil(
437 XGL_CMD_BUFFER cmdBuffer,
438 XGL_IMAGE image,
439 XGL_FLOAT depth,
440 XGL_UINT32 stencil,
441 XGL_UINT rangeCount,
442 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
443
444XGL_VOID XGLAPI intelCmdResolveImage(
445 XGL_CMD_BUFFER cmdBuffer,
446 XGL_IMAGE srcImage,
447 XGL_IMAGE destImage,
448 XGL_UINT rectCount,
449 const XGL_IMAGE_RESOLVE* pRects);
450
451XGL_VOID XGLAPI intelCmdSetEvent(
452 XGL_CMD_BUFFER cmdBuffer,
453 XGL_EVENT event);
454
455XGL_VOID XGLAPI intelCmdResetEvent(
456 XGL_CMD_BUFFER cmdBuffer,
457 XGL_EVENT event);
458
459XGL_VOID XGLAPI intelCmdMemoryAtomic(
460 XGL_CMD_BUFFER cmdBuffer,
461 XGL_GPU_MEMORY destMem,
462 XGL_GPU_SIZE destOffset,
463 XGL_UINT64 srcData,
464 XGL_ATOMIC_OP atomicOp);
465
466XGL_VOID XGLAPI intelCmdBeginQuery(
467 XGL_CMD_BUFFER cmdBuffer,
468 XGL_QUERY_POOL queryPool,
469 XGL_UINT slot,
470 XGL_FLAGS flags);
471
472XGL_VOID XGLAPI intelCmdEndQuery(
473 XGL_CMD_BUFFER cmdBuffer,
474 XGL_QUERY_POOL queryPool,
475 XGL_UINT slot);
476
477XGL_VOID XGLAPI intelCmdResetQueryPool(
478 XGL_CMD_BUFFER cmdBuffer,
479 XGL_QUERY_POOL queryPool,
480 XGL_UINT startQuery,
481 XGL_UINT queryCount);
482
483XGL_VOID XGLAPI intelCmdWriteTimestamp(
484 XGL_CMD_BUFFER cmdBuffer,
485 XGL_TIMESTAMP_TYPE timestampType,
486 XGL_GPU_MEMORY destMem,
487 XGL_GPU_SIZE destOffset);
488
489XGL_VOID XGLAPI intelCmdInitAtomicCounters(
490 XGL_CMD_BUFFER cmdBuffer,
491 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
492 XGL_UINT startCounter,
493 XGL_UINT counterCount,
494 const XGL_UINT32* pData);
495
496XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
497 XGL_CMD_BUFFER cmdBuffer,
498 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
499 XGL_UINT startCounter,
500 XGL_UINT counterCount,
501 XGL_GPU_MEMORY srcMem,
502 XGL_GPU_SIZE srcOffset);
503
504XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
505 XGL_CMD_BUFFER cmdBuffer,
506 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
507 XGL_UINT startCounter,
508 XGL_UINT counterCount,
509 XGL_GPU_MEMORY destMem,
510 XGL_GPU_SIZE destOffset);
511
512XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
513 XGL_CMD_BUFFER cmdBuffer,
514 const XGL_CHAR* pMarker);
515
516XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
517 XGL_CMD_BUFFER cmdBuffer);
518
519#endif /* CMD_H */