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gerrit-public.fairphone.software / toolchain / llvm-project / 13a0f83a05ff46341b722d9e6fabe3f32443a3e1 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: b3b2efbd9073ea5127fdbec0c4bdec53b01ba8c5 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]83 int Lat, list<int> Res = [1], int UOps = 1,
84 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]85 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]86 def : WriteRes<SchedRW, ExePorts> {
87 let Latency = Lat;
88 let ResourceCycles = Res;
89 let NumMicroOps = UOps;
90 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]91
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]92 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
93 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]94 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]95 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]97 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]98 }
99}
100
101// A folded store needs a cycle on port 4 for the store data, but it does not
102// need an extra port 2/3 cycle to recompute the address.
103def : WriteRes<WriteRMW, [BWPort4]>;
104
105// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]106defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
107defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
108defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000[diff] [blame]109defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]110def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]111
112def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
113
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]114// Bit counts.
115defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
116defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
117defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
118defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
119
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]120// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]121defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]122
Craig Topper89310f52018-03-29 20:41:39 +0000[diff] [blame]123// BMI1 BEXTR, BMI2 BZHI
124defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
125defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
126
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]127// Loads, stores, and moves, not folded with other operations.
128def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
129def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
130def : WriteRes<WriteMove, [BWPort0156]>;
131
132// Idioms that clear a register, like xorps %xmm0, %xmm0.
133// These can often bypass execution ports completely.
134def : WriteRes<WriteZero, []>;
135
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]136// Treat misc copies as a move.
137def : InstRW<[WriteMove], (instrs COPY)>;
138
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]139// Branches don't produce values, so they have no latency, but they still
140// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]141defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]142
143// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]144def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
145def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
146def : WriteRes<WriteFMove, [BWPort5]>;
147
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]148defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
149defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
150defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
151defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
152defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
153defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
154defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
155defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
156defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
157defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]158
159// FMA Scheduling helper class.
160// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
161
162// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]163def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
164def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
165def : WriteRes<WriteVecMove, [BWPort015]>;
166
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]167defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
168defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
169defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
Craig Topper13a0f832018-03-31 04:54:32 +0000[diff] [blame^]170defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]171defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
172defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
173defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
174defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]175
176// Vector bitwise operations.
177// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]178defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]179
180// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]181defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
182defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
183defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]184
185// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]186
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]187// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]188def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]189 let Latency = 11;
190 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]191 let ResourceCycles = [3];
192}
193def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]194 let Latency = 16;
195 let NumMicroOps = 4;
196 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]197}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]198
199// Packed Compare Explicit Length Strings, Return Mask
200def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
201 let Latency = 19;
202 let NumMicroOps = 9;
203 let ResourceCycles = [4,3,1,1];
204}
205def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
206 let Latency = 24;
207 let NumMicroOps = 10;
208 let ResourceCycles = [4,3,1,1,1];
209}
210
211// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]212def : WriteRes<WritePCmpIStrI, [BWPort0]> {
213 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]214 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]215 let ResourceCycles = [3];
216}
217def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]218 let Latency = 16;
219 let NumMicroOps = 4;
220 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]221}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]222
223// Packed Compare Explicit Length Strings, Return Index
224def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
225 let Latency = 18;
226 let NumMicroOps = 8;
227 let ResourceCycles = [4,3,1];
228}
229def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
230 let Latency = 23;
231 let NumMicroOps = 9;
232 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]233}
234
Simon Pilgrima2f26782018-03-27 20:38:54 +0000[diff] [blame]235// MOVMSK Instructions.
236def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
237def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
238def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
239
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]240// AES instructions.
241def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
242 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]243 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]244 let ResourceCycles = [1];
245}
246def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]247 let Latency = 12;
248 let NumMicroOps = 2;
249 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]250}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]251
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]252def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
253 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]254 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]255 let ResourceCycles = [2];
256}
257def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]258 let Latency = 19;
259 let NumMicroOps = 3;
260 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]261}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]262
263def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
264 let Latency = 29;
265 let NumMicroOps = 11;
266 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]267}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]268def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
269 let Latency = 33;
270 let NumMicroOps = 11;
271 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]272}
273
274// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]275defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]276
277// Catch-all for expensive system instructions.
278def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
279
280// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]281defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
282defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
283defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]284
285// Old microcoded instructions that nobody use.
286def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
287
288// Fence instructions.
289def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
290
291// Nop, not very useful expect it provides a model for nops!
292def : WriteRes<WriteNop, []>;
293
294////////////////////////////////////////////////////////////////////////////////
295// Horizontal add/sub instructions.
296////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]297
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]298defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
299defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]300
301// Remaining instrs.
302
303def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
304 let Latency = 1;
305 let NumMicroOps = 1;
306 let ResourceCycles = [1];
307}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]308def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
309 "MMX_MOVD64grr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]310 "MMX_PSLLDri",
311 "MMX_PSLLDrr",
312 "MMX_PSLLQri",
313 "MMX_PSLLQrr",
314 "MMX_PSLLWri",
315 "MMX_PSLLWrr",
316 "MMX_PSRADri",
317 "MMX_PSRADrr",
318 "MMX_PSRAWri",
319 "MMX_PSRAWrr",
320 "MMX_PSRLDri",
321 "MMX_PSRLDrr",
322 "MMX_PSRLQri",
323 "MMX_PSRLQrr",
324 "MMX_PSRLWri",
325 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]326 "(V?)MOVPDI2DIrr",
327 "(V?)MOVPQIto64rr",
328 "(V?)PSLLD(Y?)ri",
329 "(V?)PSLLQ(Y?)ri",
330 "VPSLLVQ(Y?)rr",
331 "(V?)PSLLW(Y?)ri",
332 "(V?)PSRAD(Y?)ri",
333 "(V?)PSRAW(Y?)ri",
334 "(V?)PSRLD(Y?)ri",
335 "(V?)PSRLQ(Y?)ri",
336 "VPSRLVQ(Y?)rr",
337 "(V?)PSRLW(Y?)ri",
338 "VTESTPD(Y?)rr",
339 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]340
341def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
342 let Latency = 1;
343 let NumMicroOps = 1;
344 let ResourceCycles = [1];
345}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]346def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
347 "COM_FST0r",
348 "UCOM_FPr",
349 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]350
351def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
352 let Latency = 1;
353 let NumMicroOps = 1;
354 let ResourceCycles = [1];
355}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]356def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]357 "MMX_MOVD64to64rr",
358 "MMX_MOVQ2DQrr",
359 "MMX_PALIGNRrri",
360 "MMX_PSHUFBrr",
361 "MMX_PSHUFWri",
362 "MMX_PUNPCKHBWirr",
363 "MMX_PUNPCKHDQirr",
364 "MMX_PUNPCKHWDirr",
365 "MMX_PUNPCKLBWirr",
366 "MMX_PUNPCKLDQirr",
367 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]368 "(V?)ANDNPD(Y?)rr",
369 "(V?)ANDNPS(Y?)rr",
370 "(V?)ANDPD(Y?)rr",
371 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]372 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]373 "(V?)INSERTPSrr",
374 "(V?)MOV64toPQIrr",
375 "(V?)MOVAPD(Y?)rr",
376 "(V?)MOVAPS(Y?)rr",
377 "(V?)MOVDDUP(Y?)rr",
378 "(V?)MOVDI2PDIrr",
379 "(V?)MOVHLPSrr",
380 "(V?)MOVLHPSrr",
381 "(V?)MOVSDrr",
382 "(V?)MOVSHDUP(Y?)rr",
383 "(V?)MOVSLDUP(Y?)rr",
384 "(V?)MOVSSrr",
385 "(V?)MOVUPD(Y?)rr",
386 "(V?)MOVUPS(Y?)rr",
387 "(V?)ORPD(Y?)rr",
388 "(V?)ORPS(Y?)rr",
389 "(V?)PACKSSDW(Y?)rr",
390 "(V?)PACKSSWB(Y?)rr",
391 "(V?)PACKUSDW(Y?)rr",
392 "(V?)PACKUSWB(Y?)rr",
393 "(V?)PALIGNR(Y?)rri",
394 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]395 "VPBROADCASTDrr",
396 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]397 "VPERMILPD(Y?)ri",
398 "VPERMILPD(Y?)rr",
399 "VPERMILPS(Y?)ri",
400 "VPERMILPS(Y?)rr",
401 "(V?)PMOVSXBDrr",
402 "(V?)PMOVSXBQrr",
403 "(V?)PMOVSXBWrr",
404 "(V?)PMOVSXDQrr",
405 "(V?)PMOVSXWDrr",
406 "(V?)PMOVSXWQrr",
407 "(V?)PMOVZXBDrr",
408 "(V?)PMOVZXBQrr",
409 "(V?)PMOVZXBWrr",
410 "(V?)PMOVZXDQrr",
411 "(V?)PMOVZXWDrr",
412 "(V?)PMOVZXWQrr",
413 "(V?)PSHUFB(Y?)rr",
414 "(V?)PSHUFD(Y?)ri",
415 "(V?)PSHUFHW(Y?)ri",
416 "(V?)PSHUFLW(Y?)ri",
417 "(V?)PSLLDQ(Y?)ri",
418 "(V?)PSRLDQ(Y?)ri",
419 "(V?)PUNPCKHBW(Y?)rr",
420 "(V?)PUNPCKHDQ(Y?)rr",
421 "(V?)PUNPCKHQDQ(Y?)rr",
422 "(V?)PUNPCKHWD(Y?)rr",
423 "(V?)PUNPCKLBW(Y?)rr",
424 "(V?)PUNPCKLDQ(Y?)rr",
425 "(V?)PUNPCKLQDQ(Y?)rr",
426 "(V?)PUNPCKLWD(Y?)rr",
427 "(V?)SHUFPD(Y?)rri",
428 "(V?)SHUFPS(Y?)rri",
429 "(V?)UNPCKHPD(Y?)rr",
430 "(V?)UNPCKHPS(Y?)rr",
431 "(V?)UNPCKLPD(Y?)rr",
432 "(V?)UNPCKLPS(Y?)rr",
433 "(V?)XORPD(Y?)rr",
434 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]435
436def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
437 let Latency = 1;
438 let NumMicroOps = 1;
439 let ResourceCycles = [1];
440}
441def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
442
443def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
444 let Latency = 1;
445 let NumMicroOps = 1;
446 let ResourceCycles = [1];
447}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]448def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
449 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]450
451def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
452 let Latency = 1;
453 let NumMicroOps = 1;
454 let ResourceCycles = [1];
455}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]456def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
457 "ADC(16|32|64)i",
458 "ADC(8|16|32|64)rr",
459 "ADCX(32|64)rr",
460 "ADOX(32|64)rr",
461 "BT(16|32|64)ri8",
462 "BT(16|32|64)rr",
463 "BTC(16|32|64)ri8",
464 "BTC(16|32|64)rr",
465 "BTR(16|32|64)ri8",
466 "BTR(16|32|64)rr",
467 "BTS(16|32|64)ri8",
468 "BTS(16|32|64)rr",
469 "CDQ",
470 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
471 "CQO",
472 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
473 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
474 "JMP_1",
475 "JMP_4",
476 "RORX(32|64)ri",
477 "SAR(8|16|32|64)r1",
478 "SAR(8|16|32|64)ri",
479 "SARX(32|64)rr",
480 "SBB(16|32|64)ri",
481 "SBB(16|32|64)i",
482 "SBB(8|16|32|64)rr",
483 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
484 "SHL(8|16|32|64)r1",
485 "SHL(8|16|32|64)ri",
486 "SHLX(32|64)rr",
487 "SHR(8|16|32|64)r1",
488 "SHR(8|16|32|64)ri",
489 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]490
491def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
492 let Latency = 1;
493 let NumMicroOps = 1;
494 let ResourceCycles = [1];
495}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]496def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
497 "BLSI(32|64)rr",
498 "BLSMSK(32|64)rr",
499 "BLSR(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]500 "LEA(16|32|64)(_32)?r",
501 "MMX_PABSBrr",
502 "MMX_PABSDrr",
503 "MMX_PABSWrr",
504 "MMX_PADDBirr",
505 "MMX_PADDDirr",
506 "MMX_PADDQirr",
507 "MMX_PADDSBirr",
508 "MMX_PADDSWirr",
509 "MMX_PADDUSBirr",
510 "MMX_PADDUSWirr",
511 "MMX_PADDWirr",
512 "MMX_PAVGBirr",
513 "MMX_PAVGWirr",
514 "MMX_PCMPEQBirr",
515 "MMX_PCMPEQDirr",
516 "MMX_PCMPEQWirr",
517 "MMX_PCMPGTBirr",
518 "MMX_PCMPGTDirr",
519 "MMX_PCMPGTWirr",
520 "MMX_PMAXSWirr",
521 "MMX_PMAXUBirr",
522 "MMX_PMINSWirr",
523 "MMX_PMINUBirr",
524 "MMX_PSIGNBrr",
525 "MMX_PSIGNDrr",
526 "MMX_PSIGNWrr",
527 "MMX_PSUBBirr",
528 "MMX_PSUBDirr",
529 "MMX_PSUBQirr",
530 "MMX_PSUBSBirr",
531 "MMX_PSUBSWirr",
532 "MMX_PSUBUSBirr",
533 "MMX_PSUBUSWirr",
534 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]535 "(V?)PABSB(Y?)rr",
536 "(V?)PABSD(Y?)rr",
537 "(V?)PABSW(Y?)rr",
538 "(V?)PADDB(Y?)rr",
539 "(V?)PADDD(Y?)rr",
540 "(V?)PADDQ(Y?)rr",
541 "(V?)PADDSB(Y?)rr",
542 "(V?)PADDSW(Y?)rr",
543 "(V?)PADDUSB(Y?)rr",
544 "(V?)PADDUSW(Y?)rr",
545 "(V?)PADDW(Y?)rr",
546 "(V?)PAVGB(Y?)rr",
547 "(V?)PAVGW(Y?)rr",
548 "(V?)PCMPEQB(Y?)rr",
549 "(V?)PCMPEQD(Y?)rr",
550 "(V?)PCMPEQQ(Y?)rr",
551 "(V?)PCMPEQW(Y?)rr",
552 "(V?)PCMPGTB(Y?)rr",
553 "(V?)PCMPGTD(Y?)rr",
554 "(V?)PCMPGTW(Y?)rr",
555 "(V?)PMAXSB(Y?)rr",
556 "(V?)PMAXSD(Y?)rr",
557 "(V?)PMAXSW(Y?)rr",
558 "(V?)PMAXUB(Y?)rr",
559 "(V?)PMAXUD(Y?)rr",
560 "(V?)PMAXUW(Y?)rr",
561 "(V?)PMINSB(Y?)rr",
562 "(V?)PMINSD(Y?)rr",
563 "(V?)PMINSW(Y?)rr",
564 "(V?)PMINUB(Y?)rr",
565 "(V?)PMINUD(Y?)rr",
566 "(V?)PMINUW(Y?)rr",
567 "(V?)PSIGNB(Y?)rr",
568 "(V?)PSIGND(Y?)rr",
569 "(V?)PSIGNW(Y?)rr",
570 "(V?)PSUBB(Y?)rr",
571 "(V?)PSUBD(Y?)rr",
572 "(V?)PSUBQ(Y?)rr",
573 "(V?)PSUBSB(Y?)rr",
574 "(V?)PSUBSW(Y?)rr",
575 "(V?)PSUBUSB(Y?)rr",
576 "(V?)PSUBUSW(Y?)rr",
577 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]578
579def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
580 let Latency = 1;
581 let NumMicroOps = 1;
582 let ResourceCycles = [1];
583}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]584def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]585 "MMX_PANDNirr",
586 "MMX_PANDirr",
587 "MMX_PORirr",
588 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]589 "(V?)BLENDPD(Y?)rri",
590 "(V?)BLENDPS(Y?)rri",
591 "(V?)MOVDQA(Y?)rr",
592 "(V?)MOVDQU(Y?)rr",
593 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]594 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]595 "(V?)PANDN(Y?)rr",
596 "(V?)PAND(Y?)rr",
597 "VPBLENDD(Y?)rri",
598 "(V?)POR(Y?)rr",
599 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]600
601def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
602 let Latency = 1;
603 let NumMicroOps = 1;
604 let ResourceCycles = [1];
605}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]606def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]607def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
608 "ADD(8|16|32|64)rr",
609 "ADD(8|16|32|64)i",
610 "AND(8|16|32|64)ri",
611 "AND(8|16|32|64)rr",
612 "AND(8|16|32|64)i",
613 "CBW",
614 "CLC",
615 "CMC",
616 "CMP(8|16|32|64)ri",
617 "CMP(8|16|32|64)rr",
618 "CMP(8|16|32|64)i",
619 "DEC(8|16|32|64)r",
620 "INC(8|16|32|64)r",
621 "LAHF",
622 "MOV(8|16|32|64)rr",
623 "MOV(8|16|32|64)ri",
624 "MOVSX(16|32|64)rr16",
625 "MOVSX(16|32|64)rr32",
626 "MOVSX(16|32|64)rr8",
627 "MOVZX(16|32|64)rr16",
628 "MOVZX(16|32|64)rr8",
629 "NEG(8|16|32|64)r",
630 "NOOP",
631 "NOT(8|16|32|64)r",
632 "OR(8|16|32|64)ri",
633 "OR(8|16|32|64)rr",
634 "OR(8|16|32|64)i",
635 "SAHF",
636 "SGDT64m",
637 "SIDT64m",
638 "SLDT64m",
639 "SMSW16m",
640 "STC",
641 "STRm",
642 "SUB(8|16|32|64)ri",
643 "SUB(8|16|32|64)rr",
644 "SUB(8|16|32|64)i",
645 "SYSCALL",
646 "TEST(8|16|32|64)rr",
647 "TEST(8|16|32|64)i",
648 "TEST(8|16|32|64)ri",
649 "XCHG(16|32|64)rr",
650 "XOR(8|16|32|64)ri",
651 "XOR(8|16|32|64)rr",
652 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]653
654def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
655 let Latency = 1;
656 let NumMicroOps = 2;
657 let ResourceCycles = [1,1];
658}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]659def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
660 "MMX_MOVD64from64rm",
661 "MMX_MOVD64mr",
662 "MMX_MOVNTQmr",
663 "MMX_MOVQ64mr",
664 "MOV(16|32|64)mr",
665 "MOV8mi",
666 "MOV8mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]667 "MOVNTI_64mr",
668 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]669 "ST_FP32m",
670 "ST_FP64m",
671 "ST_FP80m",
672 "VEXTRACTF128mr",
673 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]674 "(V?)MOVAPD(Y?)mr",
675 "(V?)MOVAPS(Y?)mr",
676 "(V?)MOVDQA(Y?)mr",
677 "(V?)MOVDQU(Y?)mr",
678 "(V?)MOVHPDmr",
679 "(V?)MOVHPSmr",
680 "(V?)MOVLPDmr",
681 "(V?)MOVLPSmr",
682 "(V?)MOVNTDQ(V?)mr",
683 "(V?)MOVNTPD(V?)mr",
684 "(V?)MOVNTPS(V?)mr",
685 "(V?)MOVPDI2DImr",
686 "(V?)MOVPQI2QImr",
687 "(V?)MOVPQIto64mr",
688 "(V?)MOVSDmr",
689 "(V?)MOVSSmr",
690 "(V?)MOVUPD(Y?)mr",
691 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]692
693def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
694 let Latency = 2;
695 let NumMicroOps = 2;
696 let ResourceCycles = [2];
697}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]698def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
699 "BLENDVPSrr0",
700 "MMX_PINSRWrr",
701 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]702 "VBLENDVPD(Y?)rr",
703 "VBLENDVPS(Y?)rr",
704 "VPBLENDVB(Y?)rr",
705 "(V?)PINSRBrr",
706 "(V?)PINSRDrr",
707 "(V?)PINSRQrr",
708 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]709
710def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
711 let Latency = 2;
712 let NumMicroOps = 2;
713 let ResourceCycles = [2];
714}
715def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
716
717def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
718 let Latency = 2;
719 let NumMicroOps = 2;
720 let ResourceCycles = [2];
721}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]722def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
723 "ROL(8|16|32|64)ri",
724 "ROR(8|16|32|64)r1",
725 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]726
727def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
728 let Latency = 2;
729 let NumMicroOps = 2;
730 let ResourceCycles = [2];
731}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]732def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
733 "MFENCE",
734 "WAIT",
735 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]736
737def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
738 let Latency = 2;
739 let NumMicroOps = 2;
740 let ResourceCycles = [1,1];
741}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]742def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
743 "VCVTPH2PS(Y?)rr",
744 "(V?)CVTPS2PDrr",
745 "(V?)CVTSS2SDrr",
746 "(V?)EXTRACTPSrr",
747 "(V?)PEXTRBrr",
748 "(V?)PEXTRDrr",
749 "(V?)PEXTRQrr",
750 "(V?)PEXTRWrr",
751 "(V?)PSLLDrr",
752 "(V?)PSLLQrr",
753 "(V?)PSLLWrr",
754 "(V?)PSRADrr",
755 "(V?)PSRAWrr",
756 "(V?)PSRLDrr",
757 "(V?)PSRLQrr",
758 "(V?)PSRLWrr",
759 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]760
761def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
762 let Latency = 2;
763 let NumMicroOps = 2;
764 let ResourceCycles = [1,1];
765}
766def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
767
768def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
769 let Latency = 2;
770 let NumMicroOps = 2;
771 let ResourceCycles = [1,1];
772}
773def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
774
775def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
776 let Latency = 2;
777 let NumMicroOps = 2;
778 let ResourceCycles = [1,1];
779}
780def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
781
782def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
783 let Latency = 2;
784 let NumMicroOps = 2;
785 let ResourceCycles = [1,1];
786}
Craig Topper89310f52018-03-29 20:41:39 +0000[diff] [blame]787def: InstRW<[BWWriteResGroup19], (instregex "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]788
789def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
790 let Latency = 2;
791 let NumMicroOps = 2;
792 let ResourceCycles = [1,1];
793}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]794def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]795def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]796def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
797 "ADC8ri",
798 "CMOV(A|BE)(16|32|64)rr",
799 "SBB8i8",
800 "SBB8ri",
801 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]802
803def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
804 let Latency = 2;
805 let NumMicroOps = 3;
806 let ResourceCycles = [1,1,1];
807}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]808def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
809 "(V?)PEXTRBmr",
810 "(V?)PEXTRDmr",
811 "(V?)PEXTRQmr",
812 "(V?)PEXTRWmr",
813 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]814
815def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
816 let Latency = 2;
817 let NumMicroOps = 3;
818 let ResourceCycles = [1,1,1];
819}
820def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
821
822def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
823 let Latency = 2;
824 let NumMicroOps = 3;
825 let ResourceCycles = [1,1,1];
826}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]827def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]828
829def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
830 let Latency = 2;
831 let NumMicroOps = 3;
832 let ResourceCycles = [1,1,1];
833}
834def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
835
836def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
837 let Latency = 2;
838 let NumMicroOps = 3;
839 let ResourceCycles = [1,1,1];
840}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]841def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]842def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
843 "PUSH64i8",
844 "STOSB",
845 "STOSL",
846 "STOSQ",
847 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]848
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]849def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
850 let Latency = 3;
851 let NumMicroOps = 1;
852 let ResourceCycles = [1];
853}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]854def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]855def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]856def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]857 "ADD_FST0r",
858 "ADD_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]859 "MMX_CVTPI2PSirr",
860 "PDEP(32|64)rr",
861 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]862 "SHLD(16|32|64)rri8",
863 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]864 "SUBR_FPrST0",
865 "SUBR_FST0r",
866 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]867 "SUB_FPrST0",
868 "SUB_FST0r",
869 "SUB_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]870 "(V?)ADDPD(Y?)rr",
871 "(V?)ADDPS(Y?)rr",
872 "(V?)ADDSDrr",
873 "(V?)ADDSSrr",
874 "(V?)ADDSUBPD(Y?)rr",
875 "(V?)ADDSUBPS(Y?)rr",
876 "(V?)CMPPD(Y?)rri",
877 "(V?)CMPPS(Y?)rri",
878 "(V?)CMPSDrr",
879 "(V?)CMPSSrr",
880 "(V?)COMISDrr",
881 "(V?)COMISSrr",
882 "(V?)CVTDQ2PS(Y?)rr",
883 "(V?)CVTPS2DQ(Y?)rr",
884 "(V?)CVTTPS2DQ(Y?)rr",
885 "(V?)MAX(C?)PD(Y?)rr",
886 "(V?)MAX(C?)PS(Y?)rr",
887 "(V?)MAX(C?)SDrr",
888 "(V?)MAX(C?)SSrr",
889 "(V?)MIN(C?)PD(Y?)rr",
890 "(V?)MIN(C?)PS(Y?)rr",
891 "(V?)MIN(C?)SDrr",
892 "(V?)MIN(C?)SSrr",
893 "(V?)SUBPD(Y?)rr",
894 "(V?)SUBPS(Y?)rr",
895 "(V?)SUBSDrr",
896 "(V?)SUBSSrr",
897 "(V?)UCOMISDrr",
898 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]899
900def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
901 let Latency = 3;
902 let NumMicroOps = 2;
903 let ResourceCycles = [1,1];
904}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]905def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]906
907def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
908 let Latency = 3;
909 let NumMicroOps = 1;
910 let ResourceCycles = [1];
911}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]912def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
913 "VBROADCASTSSYrr",
914 "VEXTRACTF128rr",
915 "VEXTRACTI128rr",
916 "VINSERTF128rr",
917 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]918 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]919 "VPBROADCASTDYrr",
920 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]921 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]922 "VPERM2F128rr",
923 "VPERM2I128rr",
924 "VPERMDYrr",
925 "VPERMPDYri",
926 "VPERMPSYrr",
927 "VPERMQYri",
928 "VPMOVSXBDYrr",
929 "VPMOVSXBQYrr",
930 "VPMOVSXBWYrr",
931 "VPMOVSXDQYrr",
932 "VPMOVSXWDYrr",
933 "VPMOVSXWQYrr",
934 "VPMOVZXBDYrr",
935 "VPMOVZXBQYrr",
936 "VPMOVZXBWYrr",
937 "VPMOVZXDQYrr",
938 "VPMOVZXWDYrr",
939 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]940
941def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
942 let Latency = 3;
943 let NumMicroOps = 1;
944 let ResourceCycles = [1];
945}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]946def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
947 "(V?)MULPS(Y?)rr",
948 "(V?)MULSDrr",
949 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]950
951def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
952 let Latency = 3;
953 let NumMicroOps = 3;
954 let ResourceCycles = [3];
955}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]956def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
957 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]958
959def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
960 let Latency = 3;
961 let NumMicroOps = 3;
962 let ResourceCycles = [2,1];
963}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]964def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
965 "VPSRAVD(Y?)rr",
966 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]967
968def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
969 let Latency = 3;
970 let NumMicroOps = 3;
971 let ResourceCycles = [2,1];
972}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]973def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
974 "MMX_PHADDSWrr",
975 "MMX_PHADDWrr",
976 "MMX_PHSUBDrr",
977 "MMX_PHSUBSWrr",
978 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]979 "(V?)PHADDD(Y?)rr",
980 "(V?)PHADDSW(Y?)rr",
981 "(V?)PHADDW(Y?)rr",
982 "(V?)PHSUBD(Y?)rr",
983 "(V?)PHSUBSW(Y?)rr",
984 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]985
986def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
987 let Latency = 3;
988 let NumMicroOps = 3;
989 let ResourceCycles = [2,1];
990}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]991def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
992 "MMX_PACKSSWBirr",
993 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]994
995def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
996 let Latency = 3;
997 let NumMicroOps = 3;
998 let ResourceCycles = [1,2];
999}
1000def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1001
1002def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1003 let Latency = 3;
1004 let NumMicroOps = 3;
1005 let ResourceCycles = [1,2];
1006}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1007def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1008 "RCL(8|16|32|64)ri",
1009 "RCR(8|16|32|64)r1",
1010 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1011
1012def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1013 let Latency = 3;
1014 let NumMicroOps = 3;
1015 let ResourceCycles = [2,1];
1016}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1017def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1018 "ROR(8|16|32|64)rCL",
1019 "SAR(8|16|32|64)rCL",
1020 "SHL(8|16|32|64)rCL",
1021 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1022
1023def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1024 let Latency = 3;
1025 let NumMicroOps = 4;
1026 let ResourceCycles = [1,1,1,1];
1027}
1028def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1029
1030def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1031 let Latency = 3;
1032 let NumMicroOps = 4;
1033 let ResourceCycles = [1,1,1,1];
1034}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1035def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1036 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1037
1038def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1039 let Latency = 4;
1040 let NumMicroOps = 2;
1041 let ResourceCycles = [1,1];
1042}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1043def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1044 "(V?)CVTSD2SIrr",
1045 "(V?)CVTSS2SI64rr",
1046 "(V?)CVTSS2SIrr",
1047 "(V?)CVTTSD2SI64rr",
1048 "(V?)CVTTSD2SIrr",
1049 "(V?)CVTTSS2SI64rr",
1050 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1051
1052def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1053 let Latency = 4;
1054 let NumMicroOps = 2;
1055 let ResourceCycles = [1,1];
1056}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1057def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1058 "VPSLLDYrr",
1059 "VPSLLQYrr",
1060 "VPSLLWYrr",
1061 "VPSRADYrr",
1062 "VPSRAWYrr",
1063 "VPSRLDYrr",
1064 "VPSRLQYrr",
1065 "VPSRLWYrr",
1066 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1067
1068def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1069 let Latency = 4;
1070 let NumMicroOps = 2;
1071 let ResourceCycles = [1,1];
1072}
1073def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1074
1075def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1076 let Latency = 4;
1077 let NumMicroOps = 2;
1078 let ResourceCycles = [1,1];
1079}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1080def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1081def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1082 "MMX_CVTPI2PDirr",
1083 "MMX_CVTPS2PIirr",
1084 "MMX_CVTTPD2PIirr",
1085 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1086 "(V?)CVTDQ2PDrr",
1087 "(V?)CVTPD2DQrr",
1088 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1089 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1090 "(V?)CVTSD2SSrr",
1091 "(V?)CVTSI642SDrr",
1092 "(V?)CVTSI2SDrr",
1093 "(V?)CVTSI2SSrr",
1094 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1095
1096def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1097 let Latency = 4;
1098 let NumMicroOps = 4;
1099}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1100def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1101
1102def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1103 let Latency = 4;
1104 let NumMicroOps = 3;
1105 let ResourceCycles = [1,1,1];
1106}
1107def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1108
1109def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1110 let Latency = 4;
1111 let NumMicroOps = 3;
1112 let ResourceCycles = [1,1,1];
1113}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1114def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1115 "ISTT_FP32m",
1116 "ISTT_FP64m",
1117 "IST_F16m",
1118 "IST_F32m",
1119 "IST_FP16m",
1120 "IST_FP32m",
1121 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1122 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1123
1124def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1125 let Latency = 4;
1126 let NumMicroOps = 4;
1127 let ResourceCycles = [4];
1128}
1129def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1130
1131def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1132 let Latency = 4;
1133 let NumMicroOps = 4;
1134 let ResourceCycles = [1,3];
1135}
1136def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1137
1138def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1139 let Latency = 5;
1140 let NumMicroOps = 1;
1141 let ResourceCycles = [1];
1142}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1143def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1144 "MMX_PMADDWDirr",
1145 "MMX_PMULHRSWrr",
1146 "MMX_PMULHUWirr",
1147 "MMX_PMULHWirr",
1148 "MMX_PMULLWirr",
1149 "MMX_PMULUDQirr",
1150 "MMX_PSADBWirr",
1151 "MUL_FPrST0",
1152 "MUL_FST0r",
1153 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1154 "(V?)PCMPGTQ(Y?)rr",
1155 "(V?)PHMINPOSUWrr",
1156 "(V?)PMADDUBSW(Y?)rr",
1157 "(V?)PMADDWD(Y?)rr",
1158 "(V?)PMULDQ(Y?)rr",
1159 "(V?)PMULHRSW(Y?)rr",
1160 "(V?)PMULHUW(Y?)rr",
1161 "(V?)PMULHW(Y?)rr",
1162 "(V?)PMULLW(Y?)rr",
1163 "(V?)PMULUDQ(Y?)rr",
1164 "(V?)PSADBW(Y?)rr",
1165 "(V?)RCPPSr",
1166 "(V?)RCPSSr",
1167 "(V?)RSQRTPSr",
1168 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1169
1170def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1171 let Latency = 5;
1172 let NumMicroOps = 1;
1173 let ResourceCycles = [1];
1174}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1175def: InstRW<[BWWriteResGroup48],
1176 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1177 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1178
1179def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1180 let Latency = 5;
1181 let NumMicroOps = 1;
1182 let ResourceCycles = [1];
1183}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1184def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1185 "MMX_MOVD64to64rm",
1186 "MMX_MOVQ64rm",
1187 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1188 "MOVSX(16|32|64)rm16",
1189 "MOVSX(16|32|64)rm32",
1190 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1191 "MOVZX(16|32|64)rm16",
1192 "MOVZX(16|32|64)rm8",
1193 "PREFETCHNTA",
1194 "PREFETCHT0",
1195 "PREFETCHT1",
1196 "PREFETCHT2",
1197 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1198 "(V?)LDDQUrm",
1199 "(V?)MOV64toPQIrm",
1200 "(V?)MOVAPDrm",
1201 "(V?)MOVAPSrm",
1202 "(V?)MOVDDUPrm",
1203 "(V?)MOVDI2PDIrm",
1204 "(V?)MOVDQArm",
1205 "(V?)MOVDQUrm",
1206 "(V?)MOVNTDQArm",
1207 "(V?)MOVQI2PQIrm",
1208 "(V?)MOVSDrm",
1209 "(V?)MOVSHDUPrm",
1210 "(V?)MOVSLDUPrm",
1211 "(V?)MOVSSrm",
1212 "(V?)MOVUPDrm",
1213 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1214 "VPBROADCASTDrm",
1215 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1216
1217def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1218 let Latency = 5;
1219 let NumMicroOps = 3;
1220 let ResourceCycles = [1,2];
1221}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1222def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1223 "(V?)HADDPD(Y?)rr",
1224 "(V?)HADDPS(Y?)rr",
1225 "(V?)HSUBPD(Y?)rr",
1226 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1227
1228def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1229 let Latency = 5;
1230 let NumMicroOps = 3;
1231 let ResourceCycles = [1,1,1];
1232}
1233def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1234
1235def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1236 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1237 let NumMicroOps = 3;
1238 let ResourceCycles = [1,1,1];
1239}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1240def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1241
1242def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1243 let Latency = 5;
1244 let NumMicroOps = 4;
1245 let ResourceCycles = [1,1,1,1];
1246}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1247def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1248 "VMASKMOVPS(Y?)mr",
1249 "VPMASKMOVD(Y?)mr",
1250 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1251
1252def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1253 let Latency = 5;
1254 let NumMicroOps = 5;
1255 let ResourceCycles = [1,4];
1256}
1257def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1258
1259def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1260 let Latency = 5;
1261 let NumMicroOps = 5;
1262 let ResourceCycles = [1,4];
1263}
1264def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1265
1266def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1267 let Latency = 5;
1268 let NumMicroOps = 5;
1269 let ResourceCycles = [2,3];
1270}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1271def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1272
1273def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1274 let Latency = 5;
1275 let NumMicroOps = 6;
1276 let ResourceCycles = [1,1,4];
1277}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1278def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1279
1280def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1281 let Latency = 6;
1282 let NumMicroOps = 1;
1283 let ResourceCycles = [1];
1284}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1285def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1286 "LD_F64m",
1287 "LD_F80m",
1288 "VBROADCASTF128",
1289 "VBROADCASTI128",
1290 "VBROADCASTSDYrm",
1291 "VBROADCASTSSYrm",
1292 "VLDDQUYrm",
1293 "VMOVAPDYrm",
1294 "VMOVAPSYrm",
1295 "VMOVDDUPYrm",
1296 "VMOVDQAYrm",
1297 "VMOVDQUYrm",
1298 "VMOVNTDQAYrm",
1299 "VMOVSHDUPYrm",
1300 "VMOVSLDUPYrm",
1301 "VMOVUPDYrm",
1302 "VMOVUPSYrm",
1303 "VPBROADCASTDYrm",
1304 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1305 "(V?)ROUNDPD(Y?)r",
1306 "(V?)ROUNDPS(Y?)r",
1307 "(V?)ROUNDSDr",
1308 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1309
1310def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1311 let Latency = 6;
1312 let NumMicroOps = 2;
1313 let ResourceCycles = [1,1];
1314}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1315def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1316 "MMX_PSLLQrm",
1317 "MMX_PSLLWrm",
1318 "MMX_PSRADrm",
1319 "MMX_PSRAWrm",
1320 "MMX_PSRLDrm",
1321 "MMX_PSRLQrm",
1322 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1323 "VCVTPH2PS(Y?)rm",
1324 "(V?)CVTPS2PDrm",
1325 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1326 "VPSLLVQrm",
1327 "VPSRLVQrm",
1328 "VTESTPDrm",
1329 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1330
1331def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1332 let Latency = 6;
1333 let NumMicroOps = 2;
1334 let ResourceCycles = [1,1];
1335}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1336def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1337 "VCVTPD2DQYrr",
1338 "VCVTPD2PSYrr",
1339 "VCVTPS2PHYrr",
1340 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1341
1342def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1343 let Latency = 6;
1344 let NumMicroOps = 2;
1345 let ResourceCycles = [1,1];
1346}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1347def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1348 "MMX_PINSRWrm",
1349 "MMX_PSHUFBrm",
1350 "MMX_PSHUFWmi",
1351 "MMX_PUNPCKHBWirm",
1352 "MMX_PUNPCKHDQirm",
1353 "MMX_PUNPCKHWDirm",
1354 "MMX_PUNPCKLBWirm",
1355 "MMX_PUNPCKLDQirm",
1356 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1357 "(V?)ANDNPDrm",
1358 "(V?)ANDNPSrm",
1359 "(V?)ANDPDrm",
1360 "(V?)ANDPSrm",
1361 "(V?)INSERTPSrm",
1362 "(V?)MOVHPDrm",
1363 "(V?)MOVHPSrm",
1364 "(V?)MOVLPDrm",
1365 "(V?)MOVLPSrm",
1366 "(V?)ORPDrm",
1367 "(V?)ORPSrm",
1368 "(V?)PACKSSDWrm",
1369 "(V?)PACKSSWBrm",
1370 "(V?)PACKUSDWrm",
1371 "(V?)PACKUSWBrm",
1372 "(V?)PALIGNRrmi",
1373 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1374 "VPERMILPDmi",
1375 "VPERMILPDrm",
1376 "VPERMILPSmi",
1377 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1378 "(V?)PINSRBrm",
1379 "(V?)PINSRDrm",
1380 "(V?)PINSRQrm",
1381 "(V?)PINSRWrm",
1382 "(V?)PMOVSXBDrm",
1383 "(V?)PMOVSXBQrm",
1384 "(V?)PMOVSXBWrm",
1385 "(V?)PMOVSXDQrm",
1386 "(V?)PMOVSXWDrm",
1387 "(V?)PMOVSXWQrm",
1388 "(V?)PMOVZXBDrm",
1389 "(V?)PMOVZXBQrm",
1390 "(V?)PMOVZXBWrm",
1391 "(V?)PMOVZXDQrm",
1392 "(V?)PMOVZXWDrm",
1393 "(V?)PMOVZXWQrm",
1394 "(V?)PSHUFBrm",
1395 "(V?)PSHUFDmi",
1396 "(V?)PSHUFHWmi",
1397 "(V?)PSHUFLWmi",
1398 "(V?)PUNPCKHBWrm",
1399 "(V?)PUNPCKHDQrm",
1400 "(V?)PUNPCKHQDQrm",
1401 "(V?)PUNPCKHWDrm",
1402 "(V?)PUNPCKLBWrm",
1403 "(V?)PUNPCKLDQrm",
1404 "(V?)PUNPCKLQDQrm",
1405 "(V?)PUNPCKLWDrm",
1406 "(V?)SHUFPDrmi",
1407 "(V?)SHUFPSrmi",
1408 "(V?)UNPCKHPDrm",
1409 "(V?)UNPCKHPSrm",
1410 "(V?)UNPCKLPDrm",
1411 "(V?)UNPCKLPSrm",
1412 "(V?)XORPDrm",
1413 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1414
1415def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1416 let Latency = 6;
1417 let NumMicroOps = 2;
1418 let ResourceCycles = [1,1];
1419}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1420def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1421 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1422
1423def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1424 let Latency = 6;
1425 let NumMicroOps = 2;
1426 let ResourceCycles = [1,1];
1427}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1428def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1429 "ADCX(32|64)rm",
1430 "ADOX(32|64)rm",
1431 "BT(16|32|64)mi8",
1432 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1433 "RORX(32|64)mi",
1434 "SARX(32|64)rm",
1435 "SBB(8|16|32|64)rm",
1436 "SHLX(32|64)rm",
1437 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1438
1439def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1440 let Latency = 6;
1441 let NumMicroOps = 2;
1442 let ResourceCycles = [1,1];
1443}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1444def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1445 "BLSI(32|64)rm",
1446 "BLSMSK(32|64)rm",
1447 "BLSR(32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1448 "MMX_PABSBrm",
1449 "MMX_PABSDrm",
1450 "MMX_PABSWrm",
1451 "MMX_PADDBirm",
1452 "MMX_PADDDirm",
1453 "MMX_PADDQirm",
1454 "MMX_PADDSBirm",
1455 "MMX_PADDSWirm",
1456 "MMX_PADDUSBirm",
1457 "MMX_PADDUSWirm",
1458 "MMX_PADDWirm",
1459 "MMX_PAVGBirm",
1460 "MMX_PAVGWirm",
1461 "MMX_PCMPEQBirm",
1462 "MMX_PCMPEQDirm",
1463 "MMX_PCMPEQWirm",
1464 "MMX_PCMPGTBirm",
1465 "MMX_PCMPGTDirm",
1466 "MMX_PCMPGTWirm",
1467 "MMX_PMAXSWirm",
1468 "MMX_PMAXUBirm",
1469 "MMX_PMINSWirm",
1470 "MMX_PMINUBirm",
1471 "MMX_PSIGNBrm",
1472 "MMX_PSIGNDrm",
1473 "MMX_PSIGNWrm",
1474 "MMX_PSUBBirm",
1475 "MMX_PSUBDirm",
1476 "MMX_PSUBQirm",
1477 "MMX_PSUBSBirm",
1478 "MMX_PSUBSWirm",
1479 "MMX_PSUBUSBirm",
1480 "MMX_PSUBUSWirm",
1481 "MMX_PSUBWirm",
1482 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1483 "(V?)PABSBrm",
1484 "(V?)PABSDrm",
1485 "(V?)PABSWrm",
1486 "(V?)PADDBrm",
1487 "(V?)PADDDrm",
1488 "(V?)PADDQrm",
1489 "(V?)PADDSBrm",
1490 "(V?)PADDSWrm",
1491 "(V?)PADDUSBrm",
1492 "(V?)PADDUSWrm",
1493 "(V?)PADDWrm",
1494 "(V?)PAVGBrm",
1495 "(V?)PAVGWrm",
1496 "(V?)PCMPEQBrm",
1497 "(V?)PCMPEQDrm",
1498 "(V?)PCMPEQQrm",
1499 "(V?)PCMPEQWrm",
1500 "(V?)PCMPGTBrm",
1501 "(V?)PCMPGTDrm",
1502 "(V?)PCMPGTWrm",
1503 "(V?)PMAXSBrm",
1504 "(V?)PMAXSDrm",
1505 "(V?)PMAXSWrm",
1506 "(V?)PMAXUBrm",
1507 "(V?)PMAXUDrm",
1508 "(V?)PMAXUWrm",
1509 "(V?)PMINSBrm",
1510 "(V?)PMINSDrm",
1511 "(V?)PMINSWrm",
1512 "(V?)PMINUBrm",
1513 "(V?)PMINUDrm",
1514 "(V?)PMINUWrm",
1515 "(V?)PSIGNBrm",
1516 "(V?)PSIGNDrm",
1517 "(V?)PSIGNWrm",
1518 "(V?)PSUBBrm",
1519 "(V?)PSUBDrm",
1520 "(V?)PSUBQrm",
1521 "(V?)PSUBSBrm",
1522 "(V?)PSUBSWrm",
1523 "(V?)PSUBUSBrm",
1524 "(V?)PSUBUSWrm",
1525 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1526
1527def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1528 let Latency = 6;
1529 let NumMicroOps = 2;
1530 let ResourceCycles = [1,1];
1531}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1532def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1533 "MMX_PANDirm",
1534 "MMX_PORirm",
1535 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1536 "(V?)BLENDPDrmi",
1537 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1538 "VINSERTF128rm",
1539 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1540 "(V?)PANDNrm",
1541 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1542 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1543 "(V?)PORrm",
1544 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1545
1546def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1547 let Latency = 6;
1548 let NumMicroOps = 2;
1549 let ResourceCycles = [1,1];
1550}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1551def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1552def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1553 "AND(8|16|32|64)rm",
1554 "CMP(8|16|32|64)mi",
1555 "CMP(8|16|32|64)mr",
1556 "CMP(8|16|32|64)rm",
1557 "OR(8|16|32|64)rm",
1558 "POP(16|32|64)rmr",
1559 "SUB(8|16|32|64)rm",
1560 "TEST(8|16|32|64)mr",
1561 "TEST(8|16|32|64)mi",
1562 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1563
1564def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1565 let Latency = 6;
1566 let NumMicroOps = 4;
1567 let ResourceCycles = [1,1,2];
1568}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1569def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1570 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1571
1572def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1573 let Latency = 6;
1574 let NumMicroOps = 4;
1575 let ResourceCycles = [1,1,1,1];
1576}
1577def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1578
1579def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1580 let Latency = 6;
1581 let NumMicroOps = 4;
1582 let ResourceCycles = [1,1,1,1];
1583}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1584def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1585 "BTR(16|32|64)mi8",
1586 "BTS(16|32|64)mi8",
1587 "SAR(8|16|32|64)m1",
1588 "SAR(8|16|32|64)mi",
1589 "SHL(8|16|32|64)m1",
1590 "SHL(8|16|32|64)mi",
1591 "SHR(8|16|32|64)m1",
1592 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1593
1594def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1595 let Latency = 6;
1596 let NumMicroOps = 4;
1597 let ResourceCycles = [1,1,1,1];
1598}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1599def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1600 "ADD(8|16|32|64)mr",
1601 "AND(8|16|32|64)mi",
1602 "AND(8|16|32|64)mr",
1603 "DEC(8|16|32|64)m",
1604 "INC(8|16|32|64)m",
1605 "NEG(8|16|32|64)m",
1606 "NOT(8|16|32|64)m",
1607 "OR(8|16|32|64)mi",
1608 "OR(8|16|32|64)mr",
1609 "POP(16|32|64)rmm",
1610 "PUSH(16|32|64)rmm",
1611 "SUB(8|16|32|64)mi",
1612 "SUB(8|16|32|64)mr",
1613 "XOR(8|16|32|64)mi",
1614 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1615
1616def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1617 let Latency = 6;
1618 let NumMicroOps = 6;
1619 let ResourceCycles = [1,5];
1620}
1621def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1622
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1623def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1624 let Latency = 7;
1625 let NumMicroOps = 2;
1626 let ResourceCycles = [1,1];
1627}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1628def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1629 "VPSLLQYrm",
1630 "VPSLLVQYrm",
1631 "VPSLLWYrm",
1632 "VPSRADYrm",
1633 "VPSRAWYrm",
1634 "VPSRLDYrm",
1635 "VPSRLQYrm",
1636 "VPSRLVQYrm",
1637 "VPSRLWYrm",
1638 "VTESTPDYrm",
1639 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1640
1641def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1642 let Latency = 7;
1643 let NumMicroOps = 2;
1644 let ResourceCycles = [1,1];
1645}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1646def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1647 "FCOM64m",
1648 "FCOMP32m",
1649 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1650
1651def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1652 let Latency = 7;
1653 let NumMicroOps = 2;
1654 let ResourceCycles = [1,1];
1655}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1656def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1657 "VANDNPSYrm",
1658 "VANDPDYrm",
1659 "VANDPSYrm",
1660 "VORPDYrm",
1661 "VORPSYrm",
1662 "VPACKSSDWYrm",
1663 "VPACKSSWBYrm",
1664 "VPACKUSDWYrm",
1665 "VPACKUSWBYrm",
1666 "VPALIGNRYrmi",
1667 "VPBLENDWYrmi",
1668 "VPERMILPDYmi",
1669 "VPERMILPDYrm",
1670 "VPERMILPSYmi",
1671 "VPERMILPSYrm",
1672 "VPSHUFBYrm",
1673 "VPSHUFDYmi",
1674 "VPSHUFHWYmi",
1675 "VPSHUFLWYmi",
1676 "VPUNPCKHBWYrm",
1677 "VPUNPCKHDQYrm",
1678 "VPUNPCKHQDQYrm",
1679 "VPUNPCKHWDYrm",
1680 "VPUNPCKLBWYrm",
1681 "VPUNPCKLDQYrm",
1682 "VPUNPCKLQDQYrm",
1683 "VPUNPCKLWDYrm",
1684 "VSHUFPDYrmi",
1685 "VSHUFPSYrmi",
1686 "VUNPCKHPDYrm",
1687 "VUNPCKHPSYrm",
1688 "VUNPCKLPDYrm",
1689 "VUNPCKLPSYrm",
1690 "VXORPDYrm",
1691 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1692
1693def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1694 let Latency = 7;
1695 let NumMicroOps = 2;
1696 let ResourceCycles = [1,1];
1697}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1698def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1699 "VPABSDYrm",
1700 "VPABSWYrm",
1701 "VPADDBYrm",
1702 "VPADDDYrm",
1703 "VPADDQYrm",
1704 "VPADDSBYrm",
1705 "VPADDSWYrm",
1706 "VPADDUSBYrm",
1707 "VPADDUSWYrm",
1708 "VPADDWYrm",
1709 "VPAVGBYrm",
1710 "VPAVGWYrm",
1711 "VPCMPEQBYrm",
1712 "VPCMPEQDYrm",
1713 "VPCMPEQQYrm",
1714 "VPCMPEQWYrm",
1715 "VPCMPGTBYrm",
1716 "VPCMPGTDYrm",
1717 "VPCMPGTWYrm",
1718 "VPMAXSBYrm",
1719 "VPMAXSDYrm",
1720 "VPMAXSWYrm",
1721 "VPMAXUBYrm",
1722 "VPMAXUDYrm",
1723 "VPMAXUWYrm",
1724 "VPMINSBYrm",
1725 "VPMINSDYrm",
1726 "VPMINSWYrm",
1727 "VPMINUBYrm",
1728 "VPMINUDYrm",
1729 "VPMINUWYrm",
1730 "VPSIGNBYrm",
1731 "VPSIGNDYrm",
1732 "VPSIGNWYrm",
1733 "VPSUBBYrm",
1734 "VPSUBDYrm",
1735 "VPSUBQYrm",
1736 "VPSUBSBYrm",
1737 "VPSUBSWYrm",
1738 "VPSUBUSBYrm",
1739 "VPSUBUSWYrm",
1740 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1741
1742def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1743 let Latency = 7;
1744 let NumMicroOps = 2;
1745 let ResourceCycles = [1,1];
1746}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1747def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1748 "VBLENDPSYrmi",
1749 "VPANDNYrm",
1750 "VPANDYrm",
1751 "VPBLENDDYrmi",
1752 "VPORYrm",
1753 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1754
1755def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1756 let Latency = 7;
1757 let NumMicroOps = 3;
1758 let ResourceCycles = [1,2];
1759}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1760def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1761
1762def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1763 let Latency = 7;
1764 let NumMicroOps = 3;
1765 let ResourceCycles = [2,1];
1766}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1767def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1768 "BLENDVPSrm0",
1769 "MMX_PACKSSDWirm",
1770 "MMX_PACKSSWBirm",
1771 "MMX_PACKUSWBirm",
1772 "PBLENDVBrm0",
1773 "VBLENDVPDrm",
1774 "VBLENDVPSrm",
1775 "VMASKMOVPDrm",
1776 "VMASKMOVPSrm",
1777 "VPBLENDVBrm",
1778 "VPMASKMOVDrm",
1779 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1780
1781def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1782 let Latency = 7;
1783 let NumMicroOps = 3;
1784 let ResourceCycles = [1,2];
1785}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1786def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
1787 "SCASB",
1788 "SCASL",
1789 "SCASQ",
1790 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1791
1792def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1793 let Latency = 7;
1794 let NumMicroOps = 3;
1795 let ResourceCycles = [1,1,1];
1796}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1797def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1798 "PSLLQrm",
1799 "PSLLWrm",
1800 "PSRADrm",
1801 "PSRAWrm",
1802 "PSRLDrm",
1803 "PSRLQrm",
1804 "PSRLWrm",
1805 "PTESTrm",
1806 "VPSLLDrm",
1807 "VPSLLQrm",
1808 "VPSLLWrm",
1809 "VPSRADrm",
1810 "VPSRAWrm",
1811 "VPSRLDrm",
1812 "VPSRLQrm",
1813 "VPSRLWrm",
1814 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1815
1816def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1817 let Latency = 7;
1818 let NumMicroOps = 3;
1819 let ResourceCycles = [1,1,1];
1820}
1821def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1822
1823def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1824 let Latency = 7;
1825 let NumMicroOps = 3;
1826 let ResourceCycles = [1,1,1];
1827}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1828def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1829
1830def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1831 let Latency = 7;
1832 let NumMicroOps = 3;
1833 let ResourceCycles = [1,1,1];
1834}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1835def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1836 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1837
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1838def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1839 let Latency = 7;
1840 let NumMicroOps = 3;
1841 let ResourceCycles = [1,1,1];
1842}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1843def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1844
1845def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1846 let Latency = 7;
1847 let NumMicroOps = 5;
1848 let ResourceCycles = [1,1,1,2];
1849}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1850def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1851 "ROL(8|16|32|64)mi",
1852 "ROR(8|16|32|64)m1",
1853 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1854
1855def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1856 let Latency = 7;
1857 let NumMicroOps = 5;
1858 let ResourceCycles = [1,1,1,2];
1859}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1860def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1861
1862def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1863 let Latency = 7;
1864 let NumMicroOps = 5;
1865 let ResourceCycles = [1,1,1,1,1];
1866}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1867def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1868 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1869
1870def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1871 let Latency = 7;
1872 let NumMicroOps = 7;
1873 let ResourceCycles = [2,2,1,2];
1874}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1875def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1876
1877def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1878 let Latency = 8;
1879 let NumMicroOps = 2;
1880 let ResourceCycles = [1,1];
1881}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1882def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1883def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]1884def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1885 "MMX_CVTPS2PIirm",
1886 "MMX_CVTTPS2PIirm",
1887 "PDEP(32|64)rm",
1888 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1889 "(V?)ADDPDrm",
1890 "(V?)ADDPSrm",
1891 "(V?)ADDSDrm",
1892 "(V?)ADDSSrm",
1893 "(V?)ADDSUBPDrm",
1894 "(V?)ADDSUBPSrm",
1895 "(V?)CMPPDrmi",
1896 "(V?)CMPPSrmi",
1897 "(V?)CMPSDrm",
1898 "(V?)CMPSSrm",
1899 "(V?)COMISDrm",
1900 "(V?)COMISSrm",
1901 "(V?)CVTDQ2PSrm",
1902 "(V?)CVTPS2DQrm",
1903 "(V?)CVTTPS2DQrm",
1904 "(V?)MAX(C?)PDrm",
1905 "(V?)MAX(C?)PSrm",
1906 "(V?)MAX(C?)SDrm",
1907 "(V?)MAX(C?)SSrm",
1908 "(V?)MIN(C?)PDrm",
1909 "(V?)MIN(C?)PSrm",
1910 "(V?)MIN(C?)SDrm",
1911 "(V?)MIN(C?)SSrm",
1912 "(V?)SUBPDrm",
1913 "(V?)SUBPSrm",
1914 "(V?)SUBSDrm",
1915 "(V?)SUBSSrm",
1916 "(V?)UCOMISDrm",
1917 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1918
1919def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1920 let Latency = 8;
1921 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1922 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1923}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1924def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1925
1926def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1927 let Latency = 8;
1928 let NumMicroOps = 5;
1929}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1930def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1931
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1932def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1933 let Latency = 8;
1934 let NumMicroOps = 2;
1935 let ResourceCycles = [1,1];
1936}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1937def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1938 "VPMOVSXBQYrm",
1939 "VPMOVSXBWYrm",
1940 "VPMOVSXDQYrm",
1941 "VPMOVSXWDYrm",
1942 "VPMOVSXWQYrm",
1943 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1944
1945def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1946 let Latency = 8;
1947 let NumMicroOps = 2;
1948 let ResourceCycles = [1,1];
1949}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1950def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1951 "(V?)MULPSrm",
1952 "(V?)MULSDrm",
1953 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1954
1955def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1956 let Latency = 8;
1957 let NumMicroOps = 3;
1958 let ResourceCycles = [2,1];
1959}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1960def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1961 "VBLENDVPSYrm",
1962 "VMASKMOVPDYrm",
1963 "VMASKMOVPSYrm",
1964 "VPBLENDVBYrm",
1965 "VPMASKMOVDYrm",
1966 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1967
1968def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1969 let Latency = 8;
1970 let NumMicroOps = 4;
1971 let ResourceCycles = [2,1,1];
1972}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1973def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1974 "VPSRAVDrm",
1975 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1976
1977def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1978 let Latency = 8;
1979 let NumMicroOps = 4;
1980 let ResourceCycles = [2,1,1];
1981}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1982def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1983 "MMX_PHADDSWrm",
1984 "MMX_PHADDWrm",
1985 "MMX_PHSUBDrm",
1986 "MMX_PHSUBSWrm",
1987 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1988 "(V?)PHADDDrm",
1989 "(V?)PHADDSWrm",
1990 "(V?)PHADDWrm",
1991 "(V?)PHSUBDrm",
1992 "(V?)PHSUBSWrm",
1993 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1994
1995def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1996 let Latency = 8;
1997 let NumMicroOps = 5;
1998 let ResourceCycles = [1,1,1,2];
1999}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2000def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2001 "RCL(8|16|32|64)mi",
2002 "RCR(8|16|32|64)m1",
2003 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2004
2005def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2006 let Latency = 8;
2007 let NumMicroOps = 5;
2008 let ResourceCycles = [1,1,2,1];
2009}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2010def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2011
2012def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2013 let Latency = 8;
2014 let NumMicroOps = 6;
2015 let ResourceCycles = [1,1,1,3];
2016}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2017def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2018 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2019
2020def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2021 let Latency = 8;
2022 let NumMicroOps = 6;
2023 let ResourceCycles = [1,1,1,2,1];
2024}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2025def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2026 "CMPXCHG(8|16|32|64)rm",
2027 "ROL(8|16|32|64)mCL",
2028 "SAR(8|16|32|64)mCL",
2029 "SBB(8|16|32|64)mi",
2030 "SBB(8|16|32|64)mr",
2031 "SHL(8|16|32|64)mCL",
2032 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2033
2034def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2035 let Latency = 9;
2036 let NumMicroOps = 2;
2037 let ResourceCycles = [1,1];
2038}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2039def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2040 "ADD_F64m",
2041 "ILD_F16m",
2042 "ILD_F32m",
2043 "ILD_F64m",
2044 "SUBR_F32m",
2045 "SUBR_F64m",
2046 "SUB_F32m",
2047 "SUB_F64m",
2048 "VADDPDYrm",
2049 "VADDPSYrm",
2050 "VADDSUBPDYrm",
2051 "VADDSUBPSYrm",
2052 "VCMPPDYrmi",
2053 "VCMPPSYrmi",
2054 "VCVTDQ2PSYrm",
2055 "VCVTPS2DQYrm",
2056 "VCVTTPS2DQYrm",
2057 "VMAX(C?)PDYrm",
2058 "VMAX(C?)PSYrm",
2059 "VMIN(C?)PDYrm",
2060 "VMIN(C?)PSYrm",
2061 "VSUBPDYrm",
2062 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2063
2064def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2065 let Latency = 9;
2066 let NumMicroOps = 2;
2067 let ResourceCycles = [1,1];
2068}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2069def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2070 "VPERM2I128rm",
2071 "VPERMDYrm",
2072 "VPERMPDYmi",
2073 "VPERMPSYrm",
2074 "VPERMQYmi",
2075 "VPMOVZXBDYrm",
2076 "VPMOVZXBQYrm",
2077 "VPMOVZXBWYrm",
2078 "VPMOVZXDQYrm",
2079 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2080
2081def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2082 let Latency = 9;
2083 let NumMicroOps = 2;
2084 let ResourceCycles = [1,1];
2085}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2086def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2087 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2088
2089def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2090 let Latency = 9;
2091 let NumMicroOps = 3;
2092 let ResourceCycles = [1,1,1];
2093}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2094def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2095
2096def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2097 let Latency = 9;
2098 let NumMicroOps = 3;
2099 let ResourceCycles = [1,1,1];
2100}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2101def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2102 "(V?)CVTSD2SIrm",
2103 "(V?)CVTSS2SI64rm",
2104 "(V?)CVTSS2SIrm",
2105 "(V?)CVTTSD2SI64rm",
2106 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2107 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2108 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2109
2110def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2111 let Latency = 9;
2112 let NumMicroOps = 3;
2113 let ResourceCycles = [1,1,1];
2114}
2115def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2116
2117def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2118 let Latency = 9;
2119 let NumMicroOps = 3;
2120 let ResourceCycles = [1,1,1];
2121}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2122def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2123def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2124 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2125 "CVTTPD2DQrm",
2126 "MMX_CVTPD2PIirm",
2127 "MMX_CVTPI2PDirm",
2128 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2129 "(V?)CVTDQ2PDrm",
2130 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2131
2132def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2133 let Latency = 9;
2134 let NumMicroOps = 3;
2135 let ResourceCycles = [1,1,1];
2136}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2137def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2138 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2139
2140def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2141 let Latency = 9;
2142 let NumMicroOps = 4;
2143 let ResourceCycles = [2,1,1];
2144}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2145def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2146 "VPSRAVDYrm",
2147 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2148
2149def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2150 let Latency = 9;
2151 let NumMicroOps = 4;
2152 let ResourceCycles = [2,1,1];
2153}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2154def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2155 "VPHADDSWYrm",
2156 "VPHADDWYrm",
2157 "VPHSUBDYrm",
2158 "VPHSUBSWYrm",
2159 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2160
2161def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2162 let Latency = 9;
2163 let NumMicroOps = 4;
2164 let ResourceCycles = [1,1,1,1];
2165}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2166def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2167 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2168
2169def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2170 let Latency = 9;
2171 let NumMicroOps = 5;
2172 let ResourceCycles = [1,1,3];
2173}
2174def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2175
2176def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2177 let Latency = 9;
2178 let NumMicroOps = 5;
2179 let ResourceCycles = [1,2,1,1];
2180}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2181def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2182 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2183
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2184def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2185 let Latency = 10;
2186 let NumMicroOps = 2;
2187 let ResourceCycles = [1,1];
2188}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2189def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2190 "MMX_PMADDWDirm",
2191 "MMX_PMULHRSWrm",
2192 "MMX_PMULHUWirm",
2193 "MMX_PMULHWirm",
2194 "MMX_PMULLWirm",
2195 "MMX_PMULUDQirm",
2196 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2197 "(V?)PCMPGTQrm",
2198 "(V?)PHMINPOSUWrm",
2199 "(V?)PMADDUBSWrm",
2200 "(V?)PMADDWDrm",
2201 "(V?)PMULDQrm",
2202 "(V?)PMULHRSWrm",
2203 "(V?)PMULHUWrm",
2204 "(V?)PMULHWrm",
2205 "(V?)PMULLWrm",
2206 "(V?)PMULUDQrm",
2207 "(V?)PSADBWrm",
2208 "(V?)RCPPSm",
2209 "(V?)RCPSSm",
2210 "(V?)RSQRTPSm",
2211 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2212
2213def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2214 let Latency = 10;
2215 let NumMicroOps = 2;
2216 let ResourceCycles = [1,1];
2217}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2218def: InstRW<[BWWriteResGroup116],
2219 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2220 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2221
2222def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2223 let Latency = 10;
2224 let NumMicroOps = 3;
2225 let ResourceCycles = [2,1];
2226}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2227def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2228 "FICOM32m",
2229 "FICOMP16m",
2230 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2231
2232def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2233 let Latency = 10;
2234 let NumMicroOps = 3;
2235 let ResourceCycles = [1,1,1];
2236}
2237def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2238
2239def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2240 let Latency = 10;
2241 let NumMicroOps = 4;
2242 let ResourceCycles = [1,2,1];
2243}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2244def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2245 "(V?)HADDPSrm",
2246 "(V?)HSUBPDrm",
2247 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2248
2249def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2250 let Latency = 10;
2251 let NumMicroOps = 4;
2252 let ResourceCycles = [1,1,1,1];
2253}
2254def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2255
2256def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2257 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2258 let NumMicroOps = 4;
2259 let ResourceCycles = [1,1,1,1];
2260}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2261def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2262
2263def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2264 let Latency = 11;
2265 let NumMicroOps = 1;
2266 let ResourceCycles = [1];
2267}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2268def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
2269 "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2270
2271def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2272 let Latency = 11;
2273 let NumMicroOps = 2;
2274 let ResourceCycles = [1,1];
2275}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2276def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2277 "MUL_F64m",
2278 "VPCMPGTQYrm",
2279 "VPMADDUBSWYrm",
2280 "VPMADDWDYrm",
2281 "VPMULDQYrm",
2282 "VPMULHRSWYrm",
2283 "VPMULHUWYrm",
2284 "VPMULHWYrm",
2285 "VPMULLWYrm",
2286 "VPMULUDQYrm",
2287 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2288
2289def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2290 let Latency = 11;
2291 let NumMicroOps = 2;
2292 let ResourceCycles = [1,1];
2293}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2294def: InstRW<[BWWriteResGroup124],
2295 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2296
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2297def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2298 let Latency = 11;
2299 let NumMicroOps = 3;
2300 let ResourceCycles = [2,1];
2301}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2302def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2303 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2304
2305def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2306 let Latency = 11;
2307 let NumMicroOps = 3;
2308 let ResourceCycles = [2,1];
2309}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2310def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2311 "(V?)ROUNDPSm",
2312 "(V?)ROUNDSDm",
2313 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2314
2315def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2316 let Latency = 11;
2317 let NumMicroOps = 3;
2318 let ResourceCycles = [1,1,1];
2319}
2320def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2321
2322def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2323 let Latency = 11;
2324 let NumMicroOps = 4;
2325 let ResourceCycles = [1,2,1];
2326}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2327def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2328 "VHADDPSYrm",
2329 "VHSUBPDYrm",
2330 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2331
2332def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2333 let Latency = 11;
2334 let NumMicroOps = 6;
2335 let ResourceCycles = [1,1,1,1,2];
2336}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2337def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2338 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2339
2340def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2341 let Latency = 11;
2342 let NumMicroOps = 7;
2343 let ResourceCycles = [2,2,3];
2344}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2345def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2346 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2347
2348def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2349 let Latency = 11;
2350 let NumMicroOps = 9;
2351 let ResourceCycles = [1,4,1,3];
2352}
2353def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2354
2355def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2356 let Latency = 11;
2357 let NumMicroOps = 11;
2358 let ResourceCycles = [2,9];
2359}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2360def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2361def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2362
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2363def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2364 let Latency = 12;
2365 let NumMicroOps = 3;
2366 let ResourceCycles = [2,1];
2367}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2368def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2369 "ADD_FI32m",
2370 "SUBR_FI16m",
2371 "SUBR_FI32m",
2372 "SUB_FI16m",
2373 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2374 "VROUNDPDYm",
2375 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2376
2377def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2378 let Latency = 12;
2379 let NumMicroOps = 4;
2380 let ResourceCycles = [1,2,1];
2381}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2382def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2383
2384def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2385 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2386 let NumMicroOps = 1;
2387 let ResourceCycles = [1];
2388}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2389def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr",
2390 "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2391
2392def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2393 let Latency = 13;
2394 let NumMicroOps = 4;
2395 let ResourceCycles = [1,2,1];
2396}
2397def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2398
2399def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
2400 let Latency = 14;
2401 let NumMicroOps = 1;
2402 let ResourceCycles = [1];
2403}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2404def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2405 "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2406
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2407def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2408 let Latency = 14;
2409 let NumMicroOps = 3;
2410 let ResourceCycles = [1,1,1];
2411}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2412def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2413 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2414
2415def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2416 let Latency = 14;
2417 let NumMicroOps = 4;
2418 let ResourceCycles = [2,1,1];
2419}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2420def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2421
2422def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2423 let Latency = 14;
2424 let NumMicroOps = 4;
2425 let ResourceCycles = [1,1,1,1];
2426}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2427def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2428
2429def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2430 let Latency = 14;
2431 let NumMicroOps = 8;
2432 let ResourceCycles = [2,2,1,3];
2433}
2434def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2435
2436def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2437 let Latency = 14;
2438 let NumMicroOps = 10;
2439 let ResourceCycles = [2,3,1,4];
2440}
2441def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2442
2443def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2444 let Latency = 14;
2445 let NumMicroOps = 12;
2446 let ResourceCycles = [2,1,4,5];
2447}
2448def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2449
2450def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2451 let Latency = 15;
2452 let NumMicroOps = 1;
2453 let ResourceCycles = [1];
2454}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2455def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2456 "DIVR_FST0r",
2457 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2458
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2459def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2460 let Latency = 15;
2461 let NumMicroOps = 10;
2462 let ResourceCycles = [1,1,1,4,1,2];
2463}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2464def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2465
2466def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
2467 let Latency = 16;
2468 let NumMicroOps = 2;
2469 let ResourceCycles = [1,1];
2470}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2471def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2472 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2473
2474def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2475 let Latency = 16;
2476 let NumMicroOps = 3;
2477 let ResourceCycles = [2,1];
2478}
2479def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2480
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2481def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2482 let Latency = 16;
2483 let NumMicroOps = 14;
2484 let ResourceCycles = [1,1,1,4,2,5];
2485}
2486def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2487
2488def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2489 let Latency = 16;
2490 let NumMicroOps = 16;
2491 let ResourceCycles = [16];
2492}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2493def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2494
2495def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
2496 let Latency = 17;
2497 let NumMicroOps = 3;
2498 let ResourceCycles = [2,1];
2499}
2500def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2501
2502def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2503 let Latency = 17;
2504 let NumMicroOps = 4;
2505 let ResourceCycles = [2,1,1];
2506}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2507def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2508 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2509
2510def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2511 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2512 let NumMicroOps = 2;
2513 let ResourceCycles = [1,1];
2514}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2515def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
2516 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2517
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2518def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2519 let Latency = 18;
2520 let NumMicroOps = 8;
2521 let ResourceCycles = [1,1,1,5];
2522}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2523def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2524def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2525
2526def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2527 let Latency = 18;
2528 let NumMicroOps = 11;
2529 let ResourceCycles = [2,1,1,3,1,3];
2530}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2531def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2532
2533def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
2534 let Latency = 19;
2535 let NumMicroOps = 2;
2536 let ResourceCycles = [1,1];
2537}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2538def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2539 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2540
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2541def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2542 let Latency = 19;
2543 let NumMicroOps = 5;
2544 let ResourceCycles = [2,1,1,1];
2545}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2546def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2547
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2548def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2549 let Latency = 20;
2550 let NumMicroOps = 1;
2551 let ResourceCycles = [1];
2552}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2553def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2554 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2555 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2556
2557def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2558 let Latency = 20;
2559 let NumMicroOps = 5;
2560 let ResourceCycles = [2,1,1,1];
2561}
2562def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2563
2564def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2565 let Latency = 20;
2566 let NumMicroOps = 8;
2567 let ResourceCycles = [1,1,1,1,1,1,2];
2568}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2569def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2570 "INSL",
2571 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2572
2573def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2574 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2575 let NumMicroOps = 1;
2576 let ResourceCycles = [1];
2577}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2578def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr",
2579 "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2580
2581def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2582 let Latency = 21;
2583 let NumMicroOps = 2;
2584 let ResourceCycles = [1,1];
2585}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2586def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2587 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2588
2589def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
2590 let Latency = 21;
2591 let NumMicroOps = 3;
2592 let ResourceCycles = [2,1];
2593}
2594def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2595
2596def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2597 let Latency = 21;
2598 let NumMicroOps = 19;
2599 let ResourceCycles = [2,1,4,1,1,4,6];
2600}
2601def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2602
2603def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2604 let Latency = 22;
2605 let NumMicroOps = 18;
2606 let ResourceCycles = [1,1,16];
2607}
2608def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2609
2610def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
2611 let Latency = 23;
2612 let NumMicroOps = 3;
2613 let ResourceCycles = [2,1];
2614}
2615def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2616
2617def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2618 let Latency = 23;
2619 let NumMicroOps = 4;
2620 let ResourceCycles = [2,1,1];
2621}
2622def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2623
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2624def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2625 let Latency = 23;
2626 let NumMicroOps = 19;
2627 let ResourceCycles = [3,1,15];
2628}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2629def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2630
2631def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2632 let Latency = 24;
2633 let NumMicroOps = 3;
2634 let ResourceCycles = [1,1,1];
2635}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2636def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2637 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2638
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2639def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2640 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2641 let NumMicroOps = 2;
2642 let ResourceCycles = [1,1];
2643}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2644def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2645 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2646
2647def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2648 let Latency = 26;
2649 let NumMicroOps = 2;
2650 let ResourceCycles = [1,1];
2651}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2652def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2653 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2654
2655def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2656 let Latency = 27;
2657 let NumMicroOps = 4;
2658 let ResourceCycles = [2,1,1];
2659}
2660def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2661
2662def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2663 let Latency = 29;
2664 let NumMicroOps = 3;
2665 let ResourceCycles = [1,1,1];
2666}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2667def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2668 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2669
2670def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2671 let Latency = 29;
2672 let NumMicroOps = 4;
2673 let ResourceCycles = [2,1,1];
2674}
2675def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2676
2677def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2678 let Latency = 22;
2679 let NumMicroOps = 7;
2680 let ResourceCycles = [1,3,2,1];
2681}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2682def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2683
2684def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2685 let Latency = 23;
2686 let NumMicroOps = 9;
2687 let ResourceCycles = [1,3,4,1];
2688}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2689def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2690
2691def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2692 let Latency = 24;
2693 let NumMicroOps = 9;
2694 let ResourceCycles = [1,5,2,1];
2695}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2696def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2697
2698def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2699 let Latency = 25;
2700 let NumMicroOps = 7;
2701 let ResourceCycles = [1,3,2,1];
2702}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2703def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2704 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2705
2706def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2707 let Latency = 26;
2708 let NumMicroOps = 9;
2709 let ResourceCycles = [1,5,2,1];
2710}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2711def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2712
2713def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2714 let Latency = 26;
2715 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2716 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2717}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2718def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2719
2720def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2721 let Latency = 27;
2722 let NumMicroOps = 9;
2723 let ResourceCycles = [1,5,2,1];
2724}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2725def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2726
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2727def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2728 let Latency = 29;
2729 let NumMicroOps = 27;
2730 let ResourceCycles = [1,5,1,1,19];
2731}
2732def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2733
2734def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2735 let Latency = 30;
2736 let NumMicroOps = 28;
2737 let ResourceCycles = [1,6,1,1,19];
2738}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2739def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2740
2741def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2742 let Latency = 31;
2743 let NumMicroOps = 31;
2744 let ResourceCycles = [8,1,21,1];
2745}
2746def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2747
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2748def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
2749 let Latency = 34;
2750 let NumMicroOps = 3;
2751 let ResourceCycles = [2,1];
2752}
2753def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2754
2755def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2756 let Latency = 34;
2757 let NumMicroOps = 8;
2758 let ResourceCycles = [2,2,2,1,1];
2759}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2760def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2761
2762def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2763 let Latency = 34;
2764 let NumMicroOps = 23;
2765 let ResourceCycles = [1,5,3,4,10];
2766}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2767def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2768 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2769
2770def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2771 let Latency = 35;
2772 let NumMicroOps = 8;
2773 let ResourceCycles = [2,2,2,1,1];
2774}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2775def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2776
2777def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2778 let Latency = 35;
2779 let NumMicroOps = 23;
2780 let ResourceCycles = [1,5,2,1,4,10];
2781}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2782def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2783 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2784
2785def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2786 let Latency = 40;
2787 let NumMicroOps = 4;
2788 let ResourceCycles = [2,1,1];
2789}
2790def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2791
2792def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2793 let Latency = 42;
2794 let NumMicroOps = 22;
2795 let ResourceCycles = [2,20];
2796}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2797def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2798
2799def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2800 let Latency = 60;
2801 let NumMicroOps = 64;
2802 let ResourceCycles = [2,2,8,1,10,2,39];
2803}
2804def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2805
2806def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2807 let Latency = 63;
2808 let NumMicroOps = 88;
2809 let ResourceCycles = [4,4,31,1,2,1,45];
2810}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2811def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2812
2813def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2814 let Latency = 63;
2815 let NumMicroOps = 90;
2816 let ResourceCycles = [4,2,33,1,2,1,47];
2817}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2818def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2819
2820def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2821 let Latency = 75;
2822 let NumMicroOps = 15;
2823 let ResourceCycles = [6,3,6];
2824}
2825def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2826
2827def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2828 let Latency = 80;
2829 let NumMicroOps = 32;
2830 let ResourceCycles = [7,7,3,3,1,11];
2831}
2832def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2833
2834def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2835 let Latency = 115;
2836 let NumMicroOps = 100;
2837 let ResourceCycles = [9,9,11,8,1,11,21,30];
2838}
2839def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2840
2841} // SchedModel
2842