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gerrit-public.fairphone.software / toolchain / llvm-project / a2f26788a3a8192312a066f4782cad6c607fbdab / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: db7ae8a6fa6dbe0ad24a8eda42effc8bc550dad4 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]83 int Lat, list<int> Res = [1], int UOps = 1,
84 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]85 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]86 def : WriteRes<SchedRW, ExePorts> {
87 let Latency = Lat;
88 let ResourceCycles = Res;
89 let NumMicroOps = UOps;
90 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]91
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]92 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
93 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]94 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]95 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]97 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]98 }
99}
100
101// A folded store needs a cycle on port 4 for the store data, but it does not
102// need an extra port 2/3 cycle to recompute the address.
103def : WriteRes<WriteRMW, [BWPort4]>;
104
105// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]106defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
107defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
108defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000[diff] [blame]109defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]110def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]111
112def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
113
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]114// Bit counts.
115defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
116defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
117defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
118defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
119
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]120// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]121defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]122
123// Loads, stores, and moves, not folded with other operations.
124def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
125def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
126def : WriteRes<WriteMove, [BWPort0156]>;
127
128// Idioms that clear a register, like xorps %xmm0, %xmm0.
129// These can often bypass execution ports completely.
130def : WriteRes<WriteZero, []>;
131
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]132// Treat misc copies as a move.
133def : InstRW<[WriteMove], (instrs COPY)>;
134
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]135// Branches don't produce values, so they have no latency, but they still
136// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]137defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]138
139// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]140def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
141def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
142def : WriteRes<WriteFMove, [BWPort5]>;
143
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]144defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
145defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
146defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
147defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
148defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
149defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
150defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
151defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
152defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
153defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]154
155// FMA Scheduling helper class.
156// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
157
158// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]159def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
160def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
161def : WriteRes<WriteVecMove, [BWPort015]>;
162
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]163defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
164defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
165defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
166defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
167defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
168defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
169defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]170
171// Vector bitwise operations.
172// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]173defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]174
175// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]176defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
177defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
178defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]179
180// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]181
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]182// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]183def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]184 let Latency = 11;
185 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]186 let ResourceCycles = [3];
187}
188def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]189 let Latency = 16;
190 let NumMicroOps = 4;
191 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]192}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]193
194// Packed Compare Explicit Length Strings, Return Mask
195def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
196 let Latency = 19;
197 let NumMicroOps = 9;
198 let ResourceCycles = [4,3,1,1];
199}
200def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
201 let Latency = 24;
202 let NumMicroOps = 10;
203 let ResourceCycles = [4,3,1,1,1];
204}
205
206// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]207def : WriteRes<WritePCmpIStrI, [BWPort0]> {
208 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]209 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]210 let ResourceCycles = [3];
211}
212def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]213 let Latency = 16;
214 let NumMicroOps = 4;
215 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]216}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]217
218// Packed Compare Explicit Length Strings, Return Index
219def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
220 let Latency = 18;
221 let NumMicroOps = 8;
222 let ResourceCycles = [4,3,1];
223}
224def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
225 let Latency = 23;
226 let NumMicroOps = 9;
227 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]228}
229
Simon Pilgrima2f26782018-03-27 20:38:54 +0000[diff] [blame^]230// MOVMSK Instructions.
231def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
232def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
233def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
234
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]235// AES instructions.
236def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
237 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]238 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]239 let ResourceCycles = [1];
240}
241def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]242 let Latency = 12;
243 let NumMicroOps = 2;
244 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]245}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]246
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]247def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
248 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]249 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]250 let ResourceCycles = [2];
251}
252def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]253 let Latency = 19;
254 let NumMicroOps = 3;
255 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]256}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]257
258def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
259 let Latency = 29;
260 let NumMicroOps = 11;
261 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]262}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]263def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
264 let Latency = 33;
265 let NumMicroOps = 11;
266 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]267}
268
269// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]270defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]271
272// Catch-all for expensive system instructions.
273def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
274
275// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]276defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
277defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
278defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]279
280// Old microcoded instructions that nobody use.
281def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
282
283// Fence instructions.
284def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
285
286// Nop, not very useful expect it provides a model for nops!
287def : WriteRes<WriteNop, []>;
288
289////////////////////////////////////////////////////////////////////////////////
290// Horizontal add/sub instructions.
291////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]292
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]293defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
294defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]295
296// Remaining instrs.
297
298def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
299 let Latency = 1;
300 let NumMicroOps = 1;
301 let ResourceCycles = [1];
302}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]303def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
304 "MMX_MOVD64grr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]305 "MMX_PSLLDri",
306 "MMX_PSLLDrr",
307 "MMX_PSLLQri",
308 "MMX_PSLLQrr",
309 "MMX_PSLLWri",
310 "MMX_PSLLWrr",
311 "MMX_PSRADri",
312 "MMX_PSRADrr",
313 "MMX_PSRAWri",
314 "MMX_PSRAWrr",
315 "MMX_PSRLDri",
316 "MMX_PSRLDrr",
317 "MMX_PSRLQri",
318 "MMX_PSRLQrr",
319 "MMX_PSRLWri",
320 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]321 "(V?)MOVPDI2DIrr",
322 "(V?)MOVPQIto64rr",
323 "(V?)PSLLD(Y?)ri",
324 "(V?)PSLLQ(Y?)ri",
325 "VPSLLVQ(Y?)rr",
326 "(V?)PSLLW(Y?)ri",
327 "(V?)PSRAD(Y?)ri",
328 "(V?)PSRAW(Y?)ri",
329 "(V?)PSRLD(Y?)ri",
330 "(V?)PSRLQ(Y?)ri",
331 "VPSRLVQ(Y?)rr",
332 "(V?)PSRLW(Y?)ri",
333 "VTESTPD(Y?)rr",
334 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]335
336def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
337 let Latency = 1;
338 let NumMicroOps = 1;
339 let ResourceCycles = [1];
340}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]341def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
342 "COM_FST0r",
343 "UCOM_FPr",
344 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]345
346def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
347 let Latency = 1;
348 let NumMicroOps = 1;
349 let ResourceCycles = [1];
350}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]351def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]352 "MMX_MOVD64to64rr",
353 "MMX_MOVQ2DQrr",
354 "MMX_PALIGNRrri",
355 "MMX_PSHUFBrr",
356 "MMX_PSHUFWri",
357 "MMX_PUNPCKHBWirr",
358 "MMX_PUNPCKHDQirr",
359 "MMX_PUNPCKHWDirr",
360 "MMX_PUNPCKLBWirr",
361 "MMX_PUNPCKLDQirr",
362 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]363 "(V?)ANDNPD(Y?)rr",
364 "(V?)ANDNPS(Y?)rr",
365 "(V?)ANDPD(Y?)rr",
366 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]367 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]368 "(V?)INSERTPSrr",
369 "(V?)MOV64toPQIrr",
370 "(V?)MOVAPD(Y?)rr",
371 "(V?)MOVAPS(Y?)rr",
372 "(V?)MOVDDUP(Y?)rr",
373 "(V?)MOVDI2PDIrr",
374 "(V?)MOVHLPSrr",
375 "(V?)MOVLHPSrr",
376 "(V?)MOVSDrr",
377 "(V?)MOVSHDUP(Y?)rr",
378 "(V?)MOVSLDUP(Y?)rr",
379 "(V?)MOVSSrr",
380 "(V?)MOVUPD(Y?)rr",
381 "(V?)MOVUPS(Y?)rr",
382 "(V?)ORPD(Y?)rr",
383 "(V?)ORPS(Y?)rr",
384 "(V?)PACKSSDW(Y?)rr",
385 "(V?)PACKSSWB(Y?)rr",
386 "(V?)PACKUSDW(Y?)rr",
387 "(V?)PACKUSWB(Y?)rr",
388 "(V?)PALIGNR(Y?)rri",
389 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]390 "VPBROADCASTDrr",
391 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]392 "VPERMILPD(Y?)ri",
393 "VPERMILPD(Y?)rr",
394 "VPERMILPS(Y?)ri",
395 "VPERMILPS(Y?)rr",
396 "(V?)PMOVSXBDrr",
397 "(V?)PMOVSXBQrr",
398 "(V?)PMOVSXBWrr",
399 "(V?)PMOVSXDQrr",
400 "(V?)PMOVSXWDrr",
401 "(V?)PMOVSXWQrr",
402 "(V?)PMOVZXBDrr",
403 "(V?)PMOVZXBQrr",
404 "(V?)PMOVZXBWrr",
405 "(V?)PMOVZXDQrr",
406 "(V?)PMOVZXWDrr",
407 "(V?)PMOVZXWQrr",
408 "(V?)PSHUFB(Y?)rr",
409 "(V?)PSHUFD(Y?)ri",
410 "(V?)PSHUFHW(Y?)ri",
411 "(V?)PSHUFLW(Y?)ri",
412 "(V?)PSLLDQ(Y?)ri",
413 "(V?)PSRLDQ(Y?)ri",
414 "(V?)PUNPCKHBW(Y?)rr",
415 "(V?)PUNPCKHDQ(Y?)rr",
416 "(V?)PUNPCKHQDQ(Y?)rr",
417 "(V?)PUNPCKHWD(Y?)rr",
418 "(V?)PUNPCKLBW(Y?)rr",
419 "(V?)PUNPCKLDQ(Y?)rr",
420 "(V?)PUNPCKLQDQ(Y?)rr",
421 "(V?)PUNPCKLWD(Y?)rr",
422 "(V?)SHUFPD(Y?)rri",
423 "(V?)SHUFPS(Y?)rri",
424 "(V?)UNPCKHPD(Y?)rr",
425 "(V?)UNPCKHPS(Y?)rr",
426 "(V?)UNPCKLPD(Y?)rr",
427 "(V?)UNPCKLPS(Y?)rr",
428 "(V?)XORPD(Y?)rr",
429 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]430
431def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
432 let Latency = 1;
433 let NumMicroOps = 1;
434 let ResourceCycles = [1];
435}
436def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
437
438def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
439 let Latency = 1;
440 let NumMicroOps = 1;
441 let ResourceCycles = [1];
442}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]443def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
444 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]445
446def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
447 let Latency = 1;
448 let NumMicroOps = 1;
449 let ResourceCycles = [1];
450}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]451def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
452 "ADC(16|32|64)i",
453 "ADC(8|16|32|64)rr",
454 "ADCX(32|64)rr",
455 "ADOX(32|64)rr",
456 "BT(16|32|64)ri8",
457 "BT(16|32|64)rr",
458 "BTC(16|32|64)ri8",
459 "BTC(16|32|64)rr",
460 "BTR(16|32|64)ri8",
461 "BTR(16|32|64)rr",
462 "BTS(16|32|64)ri8",
463 "BTS(16|32|64)rr",
464 "CDQ",
465 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
466 "CQO",
467 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
468 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
469 "JMP_1",
470 "JMP_4",
471 "RORX(32|64)ri",
472 "SAR(8|16|32|64)r1",
473 "SAR(8|16|32|64)ri",
474 "SARX(32|64)rr",
475 "SBB(16|32|64)ri",
476 "SBB(16|32|64)i",
477 "SBB(8|16|32|64)rr",
478 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
479 "SHL(8|16|32|64)r1",
480 "SHL(8|16|32|64)ri",
481 "SHLX(32|64)rr",
482 "SHR(8|16|32|64)r1",
483 "SHR(8|16|32|64)ri",
484 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]485
486def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
487 let Latency = 1;
488 let NumMicroOps = 1;
489 let ResourceCycles = [1];
490}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]491def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
492 "BLSI(32|64)rr",
493 "BLSMSK(32|64)rr",
494 "BLSR(32|64)rr",
495 "BZHI(32|64)rr",
496 "LEA(16|32|64)(_32)?r",
497 "MMX_PABSBrr",
498 "MMX_PABSDrr",
499 "MMX_PABSWrr",
500 "MMX_PADDBirr",
501 "MMX_PADDDirr",
502 "MMX_PADDQirr",
503 "MMX_PADDSBirr",
504 "MMX_PADDSWirr",
505 "MMX_PADDUSBirr",
506 "MMX_PADDUSWirr",
507 "MMX_PADDWirr",
508 "MMX_PAVGBirr",
509 "MMX_PAVGWirr",
510 "MMX_PCMPEQBirr",
511 "MMX_PCMPEQDirr",
512 "MMX_PCMPEQWirr",
513 "MMX_PCMPGTBirr",
514 "MMX_PCMPGTDirr",
515 "MMX_PCMPGTWirr",
516 "MMX_PMAXSWirr",
517 "MMX_PMAXUBirr",
518 "MMX_PMINSWirr",
519 "MMX_PMINUBirr",
520 "MMX_PSIGNBrr",
521 "MMX_PSIGNDrr",
522 "MMX_PSIGNWrr",
523 "MMX_PSUBBirr",
524 "MMX_PSUBDirr",
525 "MMX_PSUBQirr",
526 "MMX_PSUBSBirr",
527 "MMX_PSUBSWirr",
528 "MMX_PSUBUSBirr",
529 "MMX_PSUBUSWirr",
530 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]531 "(V?)PABSB(Y?)rr",
532 "(V?)PABSD(Y?)rr",
533 "(V?)PABSW(Y?)rr",
534 "(V?)PADDB(Y?)rr",
535 "(V?)PADDD(Y?)rr",
536 "(V?)PADDQ(Y?)rr",
537 "(V?)PADDSB(Y?)rr",
538 "(V?)PADDSW(Y?)rr",
539 "(V?)PADDUSB(Y?)rr",
540 "(V?)PADDUSW(Y?)rr",
541 "(V?)PADDW(Y?)rr",
542 "(V?)PAVGB(Y?)rr",
543 "(V?)PAVGW(Y?)rr",
544 "(V?)PCMPEQB(Y?)rr",
545 "(V?)PCMPEQD(Y?)rr",
546 "(V?)PCMPEQQ(Y?)rr",
547 "(V?)PCMPEQW(Y?)rr",
548 "(V?)PCMPGTB(Y?)rr",
549 "(V?)PCMPGTD(Y?)rr",
550 "(V?)PCMPGTW(Y?)rr",
551 "(V?)PMAXSB(Y?)rr",
552 "(V?)PMAXSD(Y?)rr",
553 "(V?)PMAXSW(Y?)rr",
554 "(V?)PMAXUB(Y?)rr",
555 "(V?)PMAXUD(Y?)rr",
556 "(V?)PMAXUW(Y?)rr",
557 "(V?)PMINSB(Y?)rr",
558 "(V?)PMINSD(Y?)rr",
559 "(V?)PMINSW(Y?)rr",
560 "(V?)PMINUB(Y?)rr",
561 "(V?)PMINUD(Y?)rr",
562 "(V?)PMINUW(Y?)rr",
563 "(V?)PSIGNB(Y?)rr",
564 "(V?)PSIGND(Y?)rr",
565 "(V?)PSIGNW(Y?)rr",
566 "(V?)PSUBB(Y?)rr",
567 "(V?)PSUBD(Y?)rr",
568 "(V?)PSUBQ(Y?)rr",
569 "(V?)PSUBSB(Y?)rr",
570 "(V?)PSUBSW(Y?)rr",
571 "(V?)PSUBUSB(Y?)rr",
572 "(V?)PSUBUSW(Y?)rr",
573 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]574
575def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
576 let Latency = 1;
577 let NumMicroOps = 1;
578 let ResourceCycles = [1];
579}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]580def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]581 "MMX_PANDNirr",
582 "MMX_PANDirr",
583 "MMX_PORirr",
584 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]585 "(V?)BLENDPD(Y?)rri",
586 "(V?)BLENDPS(Y?)rri",
587 "(V?)MOVDQA(Y?)rr",
588 "(V?)MOVDQU(Y?)rr",
589 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]590 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]591 "(V?)PANDN(Y?)rr",
592 "(V?)PAND(Y?)rr",
593 "VPBLENDD(Y?)rri",
594 "(V?)POR(Y?)rr",
595 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]596
597def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
598 let Latency = 1;
599 let NumMicroOps = 1;
600 let ResourceCycles = [1];
601}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]602def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]603def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
604 "ADD(8|16|32|64)rr",
605 "ADD(8|16|32|64)i",
606 "AND(8|16|32|64)ri",
607 "AND(8|16|32|64)rr",
608 "AND(8|16|32|64)i",
609 "CBW",
610 "CLC",
611 "CMC",
612 "CMP(8|16|32|64)ri",
613 "CMP(8|16|32|64)rr",
614 "CMP(8|16|32|64)i",
615 "DEC(8|16|32|64)r",
616 "INC(8|16|32|64)r",
617 "LAHF",
618 "MOV(8|16|32|64)rr",
619 "MOV(8|16|32|64)ri",
620 "MOVSX(16|32|64)rr16",
621 "MOVSX(16|32|64)rr32",
622 "MOVSX(16|32|64)rr8",
623 "MOVZX(16|32|64)rr16",
624 "MOVZX(16|32|64)rr8",
625 "NEG(8|16|32|64)r",
626 "NOOP",
627 "NOT(8|16|32|64)r",
628 "OR(8|16|32|64)ri",
629 "OR(8|16|32|64)rr",
630 "OR(8|16|32|64)i",
631 "SAHF",
632 "SGDT64m",
633 "SIDT64m",
634 "SLDT64m",
635 "SMSW16m",
636 "STC",
637 "STRm",
638 "SUB(8|16|32|64)ri",
639 "SUB(8|16|32|64)rr",
640 "SUB(8|16|32|64)i",
641 "SYSCALL",
642 "TEST(8|16|32|64)rr",
643 "TEST(8|16|32|64)i",
644 "TEST(8|16|32|64)ri",
645 "XCHG(16|32|64)rr",
646 "XOR(8|16|32|64)ri",
647 "XOR(8|16|32|64)rr",
648 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]649
650def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
651 let Latency = 1;
652 let NumMicroOps = 2;
653 let ResourceCycles = [1,1];
654}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]655def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
656 "MMX_MOVD64from64rm",
657 "MMX_MOVD64mr",
658 "MMX_MOVNTQmr",
659 "MMX_MOVQ64mr",
660 "MOV(16|32|64)mr",
661 "MOV8mi",
662 "MOV8mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]663 "MOVNTI_64mr",
664 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]665 "ST_FP32m",
666 "ST_FP64m",
667 "ST_FP80m",
668 "VEXTRACTF128mr",
669 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]670 "(V?)MOVAPD(Y?)mr",
671 "(V?)MOVAPS(Y?)mr",
672 "(V?)MOVDQA(Y?)mr",
673 "(V?)MOVDQU(Y?)mr",
674 "(V?)MOVHPDmr",
675 "(V?)MOVHPSmr",
676 "(V?)MOVLPDmr",
677 "(V?)MOVLPSmr",
678 "(V?)MOVNTDQ(V?)mr",
679 "(V?)MOVNTPD(V?)mr",
680 "(V?)MOVNTPS(V?)mr",
681 "(V?)MOVPDI2DImr",
682 "(V?)MOVPQI2QImr",
683 "(V?)MOVPQIto64mr",
684 "(V?)MOVSDmr",
685 "(V?)MOVSSmr",
686 "(V?)MOVUPD(Y?)mr",
687 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]688
689def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
690 let Latency = 2;
691 let NumMicroOps = 2;
692 let ResourceCycles = [2];
693}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]694def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
695 "BLENDVPSrr0",
696 "MMX_PINSRWrr",
697 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]698 "VBLENDVPD(Y?)rr",
699 "VBLENDVPS(Y?)rr",
700 "VPBLENDVB(Y?)rr",
701 "(V?)PINSRBrr",
702 "(V?)PINSRDrr",
703 "(V?)PINSRQrr",
704 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]705
706def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
707 let Latency = 2;
708 let NumMicroOps = 2;
709 let ResourceCycles = [2];
710}
711def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
712
713def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
714 let Latency = 2;
715 let NumMicroOps = 2;
716 let ResourceCycles = [2];
717}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]718def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
719 "ROL(8|16|32|64)ri",
720 "ROR(8|16|32|64)r1",
721 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]722
723def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
724 let Latency = 2;
725 let NumMicroOps = 2;
726 let ResourceCycles = [2];
727}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]728def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
729 "MFENCE",
730 "WAIT",
731 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]732
733def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
734 let Latency = 2;
735 let NumMicroOps = 2;
736 let ResourceCycles = [1,1];
737}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]738def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
739 "VCVTPH2PS(Y?)rr",
740 "(V?)CVTPS2PDrr",
741 "(V?)CVTSS2SDrr",
742 "(V?)EXTRACTPSrr",
743 "(V?)PEXTRBrr",
744 "(V?)PEXTRDrr",
745 "(V?)PEXTRQrr",
746 "(V?)PEXTRWrr",
747 "(V?)PSLLDrr",
748 "(V?)PSLLQrr",
749 "(V?)PSLLWrr",
750 "(V?)PSRADrr",
751 "(V?)PSRAWrr",
752 "(V?)PSRLDrr",
753 "(V?)PSRLQrr",
754 "(V?)PSRLWrr",
755 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]756
757def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
758 let Latency = 2;
759 let NumMicroOps = 2;
760 let ResourceCycles = [1,1];
761}
762def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
763
764def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
765 let Latency = 2;
766 let NumMicroOps = 2;
767 let ResourceCycles = [1,1];
768}
769def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
770
771def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
772 let Latency = 2;
773 let NumMicroOps = 2;
774 let ResourceCycles = [1,1];
775}
776def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
777
778def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
779 let Latency = 2;
780 let NumMicroOps = 2;
781 let ResourceCycles = [1,1];
782}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]783def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
784 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]785
786def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
787 let Latency = 2;
788 let NumMicroOps = 2;
789 let ResourceCycles = [1,1];
790}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]791def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]792def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]793def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
794 "ADC8ri",
795 "CMOV(A|BE)(16|32|64)rr",
796 "SBB8i8",
797 "SBB8ri",
798 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]799
800def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
801 let Latency = 2;
802 let NumMicroOps = 3;
803 let ResourceCycles = [1,1,1];
804}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]805def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
806 "(V?)PEXTRBmr",
807 "(V?)PEXTRDmr",
808 "(V?)PEXTRQmr",
809 "(V?)PEXTRWmr",
810 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]811
812def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
813 let Latency = 2;
814 let NumMicroOps = 3;
815 let ResourceCycles = [1,1,1];
816}
817def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
818
819def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
820 let Latency = 2;
821 let NumMicroOps = 3;
822 let ResourceCycles = [1,1,1];
823}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]824def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]825
826def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
827 let Latency = 2;
828 let NumMicroOps = 3;
829 let ResourceCycles = [1,1,1];
830}
831def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
832
833def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
834 let Latency = 2;
835 let NumMicroOps = 3;
836 let ResourceCycles = [1,1,1];
837}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]838def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]839def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
840 "PUSH64i8",
841 "STOSB",
842 "STOSL",
843 "STOSQ",
844 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]845
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]846def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
847 let Latency = 3;
848 let NumMicroOps = 1;
849 let ResourceCycles = [1];
850}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]851def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]852def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]853def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]854 "ADD_FST0r",
855 "ADD_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]856 "MMX_CVTPI2PSirr",
857 "PDEP(32|64)rr",
858 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]859 "SHLD(16|32|64)rri8",
860 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]861 "SUBR_FPrST0",
862 "SUBR_FST0r",
863 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]864 "SUB_FPrST0",
865 "SUB_FST0r",
866 "SUB_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]867 "(V?)ADDPD(Y?)rr",
868 "(V?)ADDPS(Y?)rr",
869 "(V?)ADDSDrr",
870 "(V?)ADDSSrr",
871 "(V?)ADDSUBPD(Y?)rr",
872 "(V?)ADDSUBPS(Y?)rr",
873 "(V?)CMPPD(Y?)rri",
874 "(V?)CMPPS(Y?)rri",
875 "(V?)CMPSDrr",
876 "(V?)CMPSSrr",
877 "(V?)COMISDrr",
878 "(V?)COMISSrr",
879 "(V?)CVTDQ2PS(Y?)rr",
880 "(V?)CVTPS2DQ(Y?)rr",
881 "(V?)CVTTPS2DQ(Y?)rr",
882 "(V?)MAX(C?)PD(Y?)rr",
883 "(V?)MAX(C?)PS(Y?)rr",
884 "(V?)MAX(C?)SDrr",
885 "(V?)MAX(C?)SSrr",
886 "(V?)MIN(C?)PD(Y?)rr",
887 "(V?)MIN(C?)PS(Y?)rr",
888 "(V?)MIN(C?)SDrr",
889 "(V?)MIN(C?)SSrr",
890 "(V?)SUBPD(Y?)rr",
891 "(V?)SUBPS(Y?)rr",
892 "(V?)SUBSDrr",
893 "(V?)SUBSSrr",
894 "(V?)UCOMISDrr",
895 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]896
897def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
898 let Latency = 3;
899 let NumMicroOps = 2;
900 let ResourceCycles = [1,1];
901}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]902def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]903
904def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
905 let Latency = 3;
906 let NumMicroOps = 1;
907 let ResourceCycles = [1];
908}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]909def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
910 "VBROADCASTSSYrr",
911 "VEXTRACTF128rr",
912 "VEXTRACTI128rr",
913 "VINSERTF128rr",
914 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]915 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]916 "VPBROADCASTDYrr",
917 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]918 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]919 "VPERM2F128rr",
920 "VPERM2I128rr",
921 "VPERMDYrr",
922 "VPERMPDYri",
923 "VPERMPSYrr",
924 "VPERMQYri",
925 "VPMOVSXBDYrr",
926 "VPMOVSXBQYrr",
927 "VPMOVSXBWYrr",
928 "VPMOVSXDQYrr",
929 "VPMOVSXWDYrr",
930 "VPMOVSXWQYrr",
931 "VPMOVZXBDYrr",
932 "VPMOVZXBQYrr",
933 "VPMOVZXBWYrr",
934 "VPMOVZXDQYrr",
935 "VPMOVZXWDYrr",
936 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]937
938def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
939 let Latency = 3;
940 let NumMicroOps = 1;
941 let ResourceCycles = [1];
942}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]943def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
944 "(V?)MULPS(Y?)rr",
945 "(V?)MULSDrr",
946 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]947
948def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
949 let Latency = 3;
950 let NumMicroOps = 3;
951 let ResourceCycles = [3];
952}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]953def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
954 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]955
956def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
957 let Latency = 3;
958 let NumMicroOps = 3;
959 let ResourceCycles = [2,1];
960}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]961def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
962 "VPSRAVD(Y?)rr",
963 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]964
965def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
966 let Latency = 3;
967 let NumMicroOps = 3;
968 let ResourceCycles = [2,1];
969}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]970def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
971 "MMX_PHADDSWrr",
972 "MMX_PHADDWrr",
973 "MMX_PHSUBDrr",
974 "MMX_PHSUBSWrr",
975 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]976 "(V?)PHADDD(Y?)rr",
977 "(V?)PHADDSW(Y?)rr",
978 "(V?)PHADDW(Y?)rr",
979 "(V?)PHSUBD(Y?)rr",
980 "(V?)PHSUBSW(Y?)rr",
981 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]982
983def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
984 let Latency = 3;
985 let NumMicroOps = 3;
986 let ResourceCycles = [2,1];
987}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]988def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
989 "MMX_PACKSSWBirr",
990 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]991
992def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
993 let Latency = 3;
994 let NumMicroOps = 3;
995 let ResourceCycles = [1,2];
996}
997def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
998
999def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1000 let Latency = 3;
1001 let NumMicroOps = 3;
1002 let ResourceCycles = [1,2];
1003}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1004def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1005 "RCL(8|16|32|64)ri",
1006 "RCR(8|16|32|64)r1",
1007 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1008
1009def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1010 let Latency = 3;
1011 let NumMicroOps = 3;
1012 let ResourceCycles = [2,1];
1013}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1014def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1015 "ROR(8|16|32|64)rCL",
1016 "SAR(8|16|32|64)rCL",
1017 "SHL(8|16|32|64)rCL",
1018 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1019
1020def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1021 let Latency = 3;
1022 let NumMicroOps = 4;
1023 let ResourceCycles = [1,1,1,1];
1024}
1025def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1026
1027def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1028 let Latency = 3;
1029 let NumMicroOps = 4;
1030 let ResourceCycles = [1,1,1,1];
1031}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1032def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1033 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1034
1035def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1036 let Latency = 4;
1037 let NumMicroOps = 2;
1038 let ResourceCycles = [1,1];
1039}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1040def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1041 "(V?)CVTSD2SIrr",
1042 "(V?)CVTSS2SI64rr",
1043 "(V?)CVTSS2SIrr",
1044 "(V?)CVTTSD2SI64rr",
1045 "(V?)CVTTSD2SIrr",
1046 "(V?)CVTTSS2SI64rr",
1047 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1048
1049def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1050 let Latency = 4;
1051 let NumMicroOps = 2;
1052 let ResourceCycles = [1,1];
1053}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1054def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1055 "VPSLLDYrr",
1056 "VPSLLQYrr",
1057 "VPSLLWYrr",
1058 "VPSRADYrr",
1059 "VPSRAWYrr",
1060 "VPSRLDYrr",
1061 "VPSRLQYrr",
1062 "VPSRLWYrr",
1063 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1064
1065def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1066 let Latency = 4;
1067 let NumMicroOps = 2;
1068 let ResourceCycles = [1,1];
1069}
1070def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1071
1072def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1073 let Latency = 4;
1074 let NumMicroOps = 2;
1075 let ResourceCycles = [1,1];
1076}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1077def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1078def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1079 "MMX_CVTPI2PDirr",
1080 "MMX_CVTPS2PIirr",
1081 "MMX_CVTTPD2PIirr",
1082 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1083 "(V?)CVTDQ2PDrr",
1084 "(V?)CVTPD2DQrr",
1085 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1086 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1087 "(V?)CVTSD2SSrr",
1088 "(V?)CVTSI642SDrr",
1089 "(V?)CVTSI2SDrr",
1090 "(V?)CVTSI2SSrr",
1091 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1092
1093def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1094 let Latency = 4;
1095 let NumMicroOps = 4;
1096}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1097def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1098
1099def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1100 let Latency = 4;
1101 let NumMicroOps = 3;
1102 let ResourceCycles = [1,1,1];
1103}
1104def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1105
1106def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1107 let Latency = 4;
1108 let NumMicroOps = 3;
1109 let ResourceCycles = [1,1,1];
1110}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1111def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1112 "ISTT_FP32m",
1113 "ISTT_FP64m",
1114 "IST_F16m",
1115 "IST_F32m",
1116 "IST_FP16m",
1117 "IST_FP32m",
1118 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1119 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1120
1121def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1122 let Latency = 4;
1123 let NumMicroOps = 4;
1124 let ResourceCycles = [4];
1125}
1126def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1127
1128def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1129 let Latency = 4;
1130 let NumMicroOps = 4;
1131 let ResourceCycles = [1,3];
1132}
1133def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1134
1135def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1136 let Latency = 5;
1137 let NumMicroOps = 1;
1138 let ResourceCycles = [1];
1139}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1140def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1141 "MMX_PMADDWDirr",
1142 "MMX_PMULHRSWrr",
1143 "MMX_PMULHUWirr",
1144 "MMX_PMULHWirr",
1145 "MMX_PMULLWirr",
1146 "MMX_PMULUDQirr",
1147 "MMX_PSADBWirr",
1148 "MUL_FPrST0",
1149 "MUL_FST0r",
1150 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1151 "(V?)PCMPGTQ(Y?)rr",
1152 "(V?)PHMINPOSUWrr",
1153 "(V?)PMADDUBSW(Y?)rr",
1154 "(V?)PMADDWD(Y?)rr",
1155 "(V?)PMULDQ(Y?)rr",
1156 "(V?)PMULHRSW(Y?)rr",
1157 "(V?)PMULHUW(Y?)rr",
1158 "(V?)PMULHW(Y?)rr",
1159 "(V?)PMULLW(Y?)rr",
1160 "(V?)PMULUDQ(Y?)rr",
1161 "(V?)PSADBW(Y?)rr",
1162 "(V?)RCPPSr",
1163 "(V?)RCPSSr",
1164 "(V?)RSQRTPSr",
1165 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1166
1167def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1168 let Latency = 5;
1169 let NumMicroOps = 1;
1170 let ResourceCycles = [1];
1171}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1172def: InstRW<[BWWriteResGroup48],
1173 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1174 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1175
1176def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1177 let Latency = 5;
1178 let NumMicroOps = 1;
1179 let ResourceCycles = [1];
1180}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1181def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1182 "MMX_MOVD64to64rm",
1183 "MMX_MOVQ64rm",
1184 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1185 "MOVSX(16|32|64)rm16",
1186 "MOVSX(16|32|64)rm32",
1187 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1188 "MOVZX(16|32|64)rm16",
1189 "MOVZX(16|32|64)rm8",
1190 "PREFETCHNTA",
1191 "PREFETCHT0",
1192 "PREFETCHT1",
1193 "PREFETCHT2",
1194 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1195 "(V?)LDDQUrm",
1196 "(V?)MOV64toPQIrm",
1197 "(V?)MOVAPDrm",
1198 "(V?)MOVAPSrm",
1199 "(V?)MOVDDUPrm",
1200 "(V?)MOVDI2PDIrm",
1201 "(V?)MOVDQArm",
1202 "(V?)MOVDQUrm",
1203 "(V?)MOVNTDQArm",
1204 "(V?)MOVQI2PQIrm",
1205 "(V?)MOVSDrm",
1206 "(V?)MOVSHDUPrm",
1207 "(V?)MOVSLDUPrm",
1208 "(V?)MOVSSrm",
1209 "(V?)MOVUPDrm",
1210 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1211 "VPBROADCASTDrm",
1212 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1213
1214def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1215 let Latency = 5;
1216 let NumMicroOps = 3;
1217 let ResourceCycles = [1,2];
1218}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1219def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1220 "(V?)HADDPD(Y?)rr",
1221 "(V?)HADDPS(Y?)rr",
1222 "(V?)HSUBPD(Y?)rr",
1223 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1224
1225def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1226 let Latency = 5;
1227 let NumMicroOps = 3;
1228 let ResourceCycles = [1,1,1];
1229}
1230def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1231
1232def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1233 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1234 let NumMicroOps = 3;
1235 let ResourceCycles = [1,1,1];
1236}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1237def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1238
1239def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1240 let Latency = 5;
1241 let NumMicroOps = 4;
1242 let ResourceCycles = [1,1,1,1];
1243}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1244def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1245 "VMASKMOVPS(Y?)mr",
1246 "VPMASKMOVD(Y?)mr",
1247 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1248
1249def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1250 let Latency = 5;
1251 let NumMicroOps = 5;
1252 let ResourceCycles = [1,4];
1253}
1254def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1255
1256def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1257 let Latency = 5;
1258 let NumMicroOps = 5;
1259 let ResourceCycles = [1,4];
1260}
1261def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1262
1263def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1264 let Latency = 5;
1265 let NumMicroOps = 5;
1266 let ResourceCycles = [2,3];
1267}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1268def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1269
1270def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1271 let Latency = 5;
1272 let NumMicroOps = 6;
1273 let ResourceCycles = [1,1,4];
1274}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1275def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1276
1277def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1278 let Latency = 6;
1279 let NumMicroOps = 1;
1280 let ResourceCycles = [1];
1281}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1282def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1283 "LD_F64m",
1284 "LD_F80m",
1285 "VBROADCASTF128",
1286 "VBROADCASTI128",
1287 "VBROADCASTSDYrm",
1288 "VBROADCASTSSYrm",
1289 "VLDDQUYrm",
1290 "VMOVAPDYrm",
1291 "VMOVAPSYrm",
1292 "VMOVDDUPYrm",
1293 "VMOVDQAYrm",
1294 "VMOVDQUYrm",
1295 "VMOVNTDQAYrm",
1296 "VMOVSHDUPYrm",
1297 "VMOVSLDUPYrm",
1298 "VMOVUPDYrm",
1299 "VMOVUPSYrm",
1300 "VPBROADCASTDYrm",
1301 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1302 "(V?)ROUNDPD(Y?)r",
1303 "(V?)ROUNDPS(Y?)r",
1304 "(V?)ROUNDSDr",
1305 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1306
1307def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1308 let Latency = 6;
1309 let NumMicroOps = 2;
1310 let ResourceCycles = [1,1];
1311}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1312def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1313 "MMX_PSLLQrm",
1314 "MMX_PSLLWrm",
1315 "MMX_PSRADrm",
1316 "MMX_PSRAWrm",
1317 "MMX_PSRLDrm",
1318 "MMX_PSRLQrm",
1319 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1320 "VCVTPH2PS(Y?)rm",
1321 "(V?)CVTPS2PDrm",
1322 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1323 "VPSLLVQrm",
1324 "VPSRLVQrm",
1325 "VTESTPDrm",
1326 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1327
1328def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1329 let Latency = 6;
1330 let NumMicroOps = 2;
1331 let ResourceCycles = [1,1];
1332}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1333def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1334 "VCVTPD2DQYrr",
1335 "VCVTPD2PSYrr",
1336 "VCVTPS2PHYrr",
1337 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1338
1339def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1340 let Latency = 6;
1341 let NumMicroOps = 2;
1342 let ResourceCycles = [1,1];
1343}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1344def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1345 "MMX_PINSRWrm",
1346 "MMX_PSHUFBrm",
1347 "MMX_PSHUFWmi",
1348 "MMX_PUNPCKHBWirm",
1349 "MMX_PUNPCKHDQirm",
1350 "MMX_PUNPCKHWDirm",
1351 "MMX_PUNPCKLBWirm",
1352 "MMX_PUNPCKLDQirm",
1353 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1354 "(V?)ANDNPDrm",
1355 "(V?)ANDNPSrm",
1356 "(V?)ANDPDrm",
1357 "(V?)ANDPSrm",
1358 "(V?)INSERTPSrm",
1359 "(V?)MOVHPDrm",
1360 "(V?)MOVHPSrm",
1361 "(V?)MOVLPDrm",
1362 "(V?)MOVLPSrm",
1363 "(V?)ORPDrm",
1364 "(V?)ORPSrm",
1365 "(V?)PACKSSDWrm",
1366 "(V?)PACKSSWBrm",
1367 "(V?)PACKUSDWrm",
1368 "(V?)PACKUSWBrm",
1369 "(V?)PALIGNRrmi",
1370 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1371 "VPERMILPDmi",
1372 "VPERMILPDrm",
1373 "VPERMILPSmi",
1374 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1375 "(V?)PINSRBrm",
1376 "(V?)PINSRDrm",
1377 "(V?)PINSRQrm",
1378 "(V?)PINSRWrm",
1379 "(V?)PMOVSXBDrm",
1380 "(V?)PMOVSXBQrm",
1381 "(V?)PMOVSXBWrm",
1382 "(V?)PMOVSXDQrm",
1383 "(V?)PMOVSXWDrm",
1384 "(V?)PMOVSXWQrm",
1385 "(V?)PMOVZXBDrm",
1386 "(V?)PMOVZXBQrm",
1387 "(V?)PMOVZXBWrm",
1388 "(V?)PMOVZXDQrm",
1389 "(V?)PMOVZXWDrm",
1390 "(V?)PMOVZXWQrm",
1391 "(V?)PSHUFBrm",
1392 "(V?)PSHUFDmi",
1393 "(V?)PSHUFHWmi",
1394 "(V?)PSHUFLWmi",
1395 "(V?)PUNPCKHBWrm",
1396 "(V?)PUNPCKHDQrm",
1397 "(V?)PUNPCKHQDQrm",
1398 "(V?)PUNPCKHWDrm",
1399 "(V?)PUNPCKLBWrm",
1400 "(V?)PUNPCKLDQrm",
1401 "(V?)PUNPCKLQDQrm",
1402 "(V?)PUNPCKLWDrm",
1403 "(V?)SHUFPDrmi",
1404 "(V?)SHUFPSrmi",
1405 "(V?)UNPCKHPDrm",
1406 "(V?)UNPCKHPSrm",
1407 "(V?)UNPCKLPDrm",
1408 "(V?)UNPCKLPSrm",
1409 "(V?)XORPDrm",
1410 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1411
1412def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1413 let Latency = 6;
1414 let NumMicroOps = 2;
1415 let ResourceCycles = [1,1];
1416}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1417def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1418 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1419
1420def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1421 let Latency = 6;
1422 let NumMicroOps = 2;
1423 let ResourceCycles = [1,1];
1424}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1425def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1426 "ADCX(32|64)rm",
1427 "ADOX(32|64)rm",
1428 "BT(16|32|64)mi8",
1429 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1430 "RORX(32|64)mi",
1431 "SARX(32|64)rm",
1432 "SBB(8|16|32|64)rm",
1433 "SHLX(32|64)rm",
1434 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1435
1436def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1437 let Latency = 6;
1438 let NumMicroOps = 2;
1439 let ResourceCycles = [1,1];
1440}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1441def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1442 "BLSI(32|64)rm",
1443 "BLSMSK(32|64)rm",
1444 "BLSR(32|64)rm",
1445 "BZHI(32|64)rm",
1446 "MMX_PABSBrm",
1447 "MMX_PABSDrm",
1448 "MMX_PABSWrm",
1449 "MMX_PADDBirm",
1450 "MMX_PADDDirm",
1451 "MMX_PADDQirm",
1452 "MMX_PADDSBirm",
1453 "MMX_PADDSWirm",
1454 "MMX_PADDUSBirm",
1455 "MMX_PADDUSWirm",
1456 "MMX_PADDWirm",
1457 "MMX_PAVGBirm",
1458 "MMX_PAVGWirm",
1459 "MMX_PCMPEQBirm",
1460 "MMX_PCMPEQDirm",
1461 "MMX_PCMPEQWirm",
1462 "MMX_PCMPGTBirm",
1463 "MMX_PCMPGTDirm",
1464 "MMX_PCMPGTWirm",
1465 "MMX_PMAXSWirm",
1466 "MMX_PMAXUBirm",
1467 "MMX_PMINSWirm",
1468 "MMX_PMINUBirm",
1469 "MMX_PSIGNBrm",
1470 "MMX_PSIGNDrm",
1471 "MMX_PSIGNWrm",
1472 "MMX_PSUBBirm",
1473 "MMX_PSUBDirm",
1474 "MMX_PSUBQirm",
1475 "MMX_PSUBSBirm",
1476 "MMX_PSUBSWirm",
1477 "MMX_PSUBUSBirm",
1478 "MMX_PSUBUSWirm",
1479 "MMX_PSUBWirm",
1480 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1481 "(V?)PABSBrm",
1482 "(V?)PABSDrm",
1483 "(V?)PABSWrm",
1484 "(V?)PADDBrm",
1485 "(V?)PADDDrm",
1486 "(V?)PADDQrm",
1487 "(V?)PADDSBrm",
1488 "(V?)PADDSWrm",
1489 "(V?)PADDUSBrm",
1490 "(V?)PADDUSWrm",
1491 "(V?)PADDWrm",
1492 "(V?)PAVGBrm",
1493 "(V?)PAVGWrm",
1494 "(V?)PCMPEQBrm",
1495 "(V?)PCMPEQDrm",
1496 "(V?)PCMPEQQrm",
1497 "(V?)PCMPEQWrm",
1498 "(V?)PCMPGTBrm",
1499 "(V?)PCMPGTDrm",
1500 "(V?)PCMPGTWrm",
1501 "(V?)PMAXSBrm",
1502 "(V?)PMAXSDrm",
1503 "(V?)PMAXSWrm",
1504 "(V?)PMAXUBrm",
1505 "(V?)PMAXUDrm",
1506 "(V?)PMAXUWrm",
1507 "(V?)PMINSBrm",
1508 "(V?)PMINSDrm",
1509 "(V?)PMINSWrm",
1510 "(V?)PMINUBrm",
1511 "(V?)PMINUDrm",
1512 "(V?)PMINUWrm",
1513 "(V?)PSIGNBrm",
1514 "(V?)PSIGNDrm",
1515 "(V?)PSIGNWrm",
1516 "(V?)PSUBBrm",
1517 "(V?)PSUBDrm",
1518 "(V?)PSUBQrm",
1519 "(V?)PSUBSBrm",
1520 "(V?)PSUBSWrm",
1521 "(V?)PSUBUSBrm",
1522 "(V?)PSUBUSWrm",
1523 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1524
1525def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1526 let Latency = 6;
1527 let NumMicroOps = 2;
1528 let ResourceCycles = [1,1];
1529}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1530def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1531 "MMX_PANDirm",
1532 "MMX_PORirm",
1533 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1534 "(V?)BLENDPDrmi",
1535 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1536 "VINSERTF128rm",
1537 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1538 "(V?)PANDNrm",
1539 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1540 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1541 "(V?)PORrm",
1542 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1543
1544def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1545 let Latency = 6;
1546 let NumMicroOps = 2;
1547 let ResourceCycles = [1,1];
1548}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1549def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1550def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1551 "AND(8|16|32|64)rm",
1552 "CMP(8|16|32|64)mi",
1553 "CMP(8|16|32|64)mr",
1554 "CMP(8|16|32|64)rm",
1555 "OR(8|16|32|64)rm",
1556 "POP(16|32|64)rmr",
1557 "SUB(8|16|32|64)rm",
1558 "TEST(8|16|32|64)mr",
1559 "TEST(8|16|32|64)mi",
1560 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1561
1562def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1563 let Latency = 6;
1564 let NumMicroOps = 4;
1565 let ResourceCycles = [1,1,2];
1566}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1567def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1568 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1569
1570def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1571 let Latency = 6;
1572 let NumMicroOps = 4;
1573 let ResourceCycles = [1,1,1,1];
1574}
1575def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1576
1577def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1578 let Latency = 6;
1579 let NumMicroOps = 4;
1580 let ResourceCycles = [1,1,1,1];
1581}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1582def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1583 "BTR(16|32|64)mi8",
1584 "BTS(16|32|64)mi8",
1585 "SAR(8|16|32|64)m1",
1586 "SAR(8|16|32|64)mi",
1587 "SHL(8|16|32|64)m1",
1588 "SHL(8|16|32|64)mi",
1589 "SHR(8|16|32|64)m1",
1590 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1591
1592def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1593 let Latency = 6;
1594 let NumMicroOps = 4;
1595 let ResourceCycles = [1,1,1,1];
1596}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1597def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1598 "ADD(8|16|32|64)mr",
1599 "AND(8|16|32|64)mi",
1600 "AND(8|16|32|64)mr",
1601 "DEC(8|16|32|64)m",
1602 "INC(8|16|32|64)m",
1603 "NEG(8|16|32|64)m",
1604 "NOT(8|16|32|64)m",
1605 "OR(8|16|32|64)mi",
1606 "OR(8|16|32|64)mr",
1607 "POP(16|32|64)rmm",
1608 "PUSH(16|32|64)rmm",
1609 "SUB(8|16|32|64)mi",
1610 "SUB(8|16|32|64)mr",
1611 "XOR(8|16|32|64)mi",
1612 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1613
1614def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1615 let Latency = 6;
1616 let NumMicroOps = 6;
1617 let ResourceCycles = [1,5];
1618}
1619def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1620
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1621def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1622 let Latency = 7;
1623 let NumMicroOps = 2;
1624 let ResourceCycles = [1,1];
1625}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1626def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1627 "VPSLLQYrm",
1628 "VPSLLVQYrm",
1629 "VPSLLWYrm",
1630 "VPSRADYrm",
1631 "VPSRAWYrm",
1632 "VPSRLDYrm",
1633 "VPSRLQYrm",
1634 "VPSRLVQYrm",
1635 "VPSRLWYrm",
1636 "VTESTPDYrm",
1637 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1638
1639def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1640 let Latency = 7;
1641 let NumMicroOps = 2;
1642 let ResourceCycles = [1,1];
1643}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1644def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1645 "FCOM64m",
1646 "FCOMP32m",
1647 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1648
1649def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1650 let Latency = 7;
1651 let NumMicroOps = 2;
1652 let ResourceCycles = [1,1];
1653}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1654def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1655 "VANDNPSYrm",
1656 "VANDPDYrm",
1657 "VANDPSYrm",
1658 "VORPDYrm",
1659 "VORPSYrm",
1660 "VPACKSSDWYrm",
1661 "VPACKSSWBYrm",
1662 "VPACKUSDWYrm",
1663 "VPACKUSWBYrm",
1664 "VPALIGNRYrmi",
1665 "VPBLENDWYrmi",
1666 "VPERMILPDYmi",
1667 "VPERMILPDYrm",
1668 "VPERMILPSYmi",
1669 "VPERMILPSYrm",
1670 "VPSHUFBYrm",
1671 "VPSHUFDYmi",
1672 "VPSHUFHWYmi",
1673 "VPSHUFLWYmi",
1674 "VPUNPCKHBWYrm",
1675 "VPUNPCKHDQYrm",
1676 "VPUNPCKHQDQYrm",
1677 "VPUNPCKHWDYrm",
1678 "VPUNPCKLBWYrm",
1679 "VPUNPCKLDQYrm",
1680 "VPUNPCKLQDQYrm",
1681 "VPUNPCKLWDYrm",
1682 "VSHUFPDYrmi",
1683 "VSHUFPSYrmi",
1684 "VUNPCKHPDYrm",
1685 "VUNPCKHPSYrm",
1686 "VUNPCKLPDYrm",
1687 "VUNPCKLPSYrm",
1688 "VXORPDYrm",
1689 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1690
1691def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1692 let Latency = 7;
1693 let NumMicroOps = 2;
1694 let ResourceCycles = [1,1];
1695}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1696def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1697 "VPABSDYrm",
1698 "VPABSWYrm",
1699 "VPADDBYrm",
1700 "VPADDDYrm",
1701 "VPADDQYrm",
1702 "VPADDSBYrm",
1703 "VPADDSWYrm",
1704 "VPADDUSBYrm",
1705 "VPADDUSWYrm",
1706 "VPADDWYrm",
1707 "VPAVGBYrm",
1708 "VPAVGWYrm",
1709 "VPCMPEQBYrm",
1710 "VPCMPEQDYrm",
1711 "VPCMPEQQYrm",
1712 "VPCMPEQWYrm",
1713 "VPCMPGTBYrm",
1714 "VPCMPGTDYrm",
1715 "VPCMPGTWYrm",
1716 "VPMAXSBYrm",
1717 "VPMAXSDYrm",
1718 "VPMAXSWYrm",
1719 "VPMAXUBYrm",
1720 "VPMAXUDYrm",
1721 "VPMAXUWYrm",
1722 "VPMINSBYrm",
1723 "VPMINSDYrm",
1724 "VPMINSWYrm",
1725 "VPMINUBYrm",
1726 "VPMINUDYrm",
1727 "VPMINUWYrm",
1728 "VPSIGNBYrm",
1729 "VPSIGNDYrm",
1730 "VPSIGNWYrm",
1731 "VPSUBBYrm",
1732 "VPSUBDYrm",
1733 "VPSUBQYrm",
1734 "VPSUBSBYrm",
1735 "VPSUBSWYrm",
1736 "VPSUBUSBYrm",
1737 "VPSUBUSWYrm",
1738 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1739
1740def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1741 let Latency = 7;
1742 let NumMicroOps = 2;
1743 let ResourceCycles = [1,1];
1744}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1745def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1746 "VBLENDPSYrmi",
1747 "VPANDNYrm",
1748 "VPANDYrm",
1749 "VPBLENDDYrmi",
1750 "VPORYrm",
1751 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1752
1753def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1754 let Latency = 7;
1755 let NumMicroOps = 3;
1756 let ResourceCycles = [1,2];
1757}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1758def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1759
1760def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1761 let Latency = 7;
1762 let NumMicroOps = 3;
1763 let ResourceCycles = [2,1];
1764}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1765def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1766 "BLENDVPSrm0",
1767 "MMX_PACKSSDWirm",
1768 "MMX_PACKSSWBirm",
1769 "MMX_PACKUSWBirm",
1770 "PBLENDVBrm0",
1771 "VBLENDVPDrm",
1772 "VBLENDVPSrm",
1773 "VMASKMOVPDrm",
1774 "VMASKMOVPSrm",
1775 "VPBLENDVBrm",
1776 "VPMASKMOVDrm",
1777 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1778
1779def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1780 let Latency = 7;
1781 let NumMicroOps = 3;
1782 let ResourceCycles = [1,2];
1783}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1784def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
1785 "SCASB",
1786 "SCASL",
1787 "SCASQ",
1788 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1789
1790def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1791 let Latency = 7;
1792 let NumMicroOps = 3;
1793 let ResourceCycles = [1,1,1];
1794}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1795def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1796 "PSLLQrm",
1797 "PSLLWrm",
1798 "PSRADrm",
1799 "PSRAWrm",
1800 "PSRLDrm",
1801 "PSRLQrm",
1802 "PSRLWrm",
1803 "PTESTrm",
1804 "VPSLLDrm",
1805 "VPSLLQrm",
1806 "VPSLLWrm",
1807 "VPSRADrm",
1808 "VPSRAWrm",
1809 "VPSRLDrm",
1810 "VPSRLQrm",
1811 "VPSRLWrm",
1812 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1813
1814def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1815 let Latency = 7;
1816 let NumMicroOps = 3;
1817 let ResourceCycles = [1,1,1];
1818}
1819def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1820
1821def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1822 let Latency = 7;
1823 let NumMicroOps = 3;
1824 let ResourceCycles = [1,1,1];
1825}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1826def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1827
1828def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1829 let Latency = 7;
1830 let NumMicroOps = 3;
1831 let ResourceCycles = [1,1,1];
1832}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1833def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1834 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1835
1836def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
1837 let Latency = 7;
1838 let NumMicroOps = 3;
1839 let ResourceCycles = [1,1,1];
1840}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]1841def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1842
1843def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1844 let Latency = 7;
1845 let NumMicroOps = 3;
1846 let ResourceCycles = [1,1,1];
1847}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1848def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1849
1850def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1851 let Latency = 7;
1852 let NumMicroOps = 5;
1853 let ResourceCycles = [1,1,1,2];
1854}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1855def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1856 "ROL(8|16|32|64)mi",
1857 "ROR(8|16|32|64)m1",
1858 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1859
1860def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1861 let Latency = 7;
1862 let NumMicroOps = 5;
1863 let ResourceCycles = [1,1,1,2];
1864}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1865def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1866
1867def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1868 let Latency = 7;
1869 let NumMicroOps = 5;
1870 let ResourceCycles = [1,1,1,1,1];
1871}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1872def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1873 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1874
1875def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1876 let Latency = 7;
1877 let NumMicroOps = 7;
1878 let ResourceCycles = [2,2,1,2];
1879}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1880def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1881
1882def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1883 let Latency = 8;
1884 let NumMicroOps = 2;
1885 let ResourceCycles = [1,1];
1886}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1887def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1888def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]1889def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1890 "MMX_CVTPS2PIirm",
1891 "MMX_CVTTPS2PIirm",
1892 "PDEP(32|64)rm",
1893 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1894 "(V?)ADDPDrm",
1895 "(V?)ADDPSrm",
1896 "(V?)ADDSDrm",
1897 "(V?)ADDSSrm",
1898 "(V?)ADDSUBPDrm",
1899 "(V?)ADDSUBPSrm",
1900 "(V?)CMPPDrmi",
1901 "(V?)CMPPSrmi",
1902 "(V?)CMPSDrm",
1903 "(V?)CMPSSrm",
1904 "(V?)COMISDrm",
1905 "(V?)COMISSrm",
1906 "(V?)CVTDQ2PSrm",
1907 "(V?)CVTPS2DQrm",
1908 "(V?)CVTTPS2DQrm",
1909 "(V?)MAX(C?)PDrm",
1910 "(V?)MAX(C?)PSrm",
1911 "(V?)MAX(C?)SDrm",
1912 "(V?)MAX(C?)SSrm",
1913 "(V?)MIN(C?)PDrm",
1914 "(V?)MIN(C?)PSrm",
1915 "(V?)MIN(C?)SDrm",
1916 "(V?)MIN(C?)SSrm",
1917 "(V?)SUBPDrm",
1918 "(V?)SUBPSrm",
1919 "(V?)SUBSDrm",
1920 "(V?)SUBSSrm",
1921 "(V?)UCOMISDrm",
1922 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1923
1924def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1925 let Latency = 8;
1926 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1927 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1928}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1929def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1930
1931def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1932 let Latency = 8;
1933 let NumMicroOps = 5;
1934}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1935def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1936
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1937def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1938 let Latency = 8;
1939 let NumMicroOps = 2;
1940 let ResourceCycles = [1,1];
1941}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1942def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1943 "VPMOVSXBQYrm",
1944 "VPMOVSXBWYrm",
1945 "VPMOVSXDQYrm",
1946 "VPMOVSXWDYrm",
1947 "VPMOVSXWQYrm",
1948 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1949
1950def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1951 let Latency = 8;
1952 let NumMicroOps = 2;
1953 let ResourceCycles = [1,1];
1954}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1955def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1956 "(V?)MULPSrm",
1957 "(V?)MULSDrm",
1958 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1959
1960def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1961 let Latency = 8;
1962 let NumMicroOps = 3;
1963 let ResourceCycles = [2,1];
1964}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1965def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1966 "VBLENDVPSYrm",
1967 "VMASKMOVPDYrm",
1968 "VMASKMOVPSYrm",
1969 "VPBLENDVBYrm",
1970 "VPMASKMOVDYrm",
1971 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1972
1973def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1974 let Latency = 8;
1975 let NumMicroOps = 4;
1976 let ResourceCycles = [2,1,1];
1977}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1978def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1979 "VPSRAVDrm",
1980 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1981
1982def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1983 let Latency = 8;
1984 let NumMicroOps = 4;
1985 let ResourceCycles = [2,1,1];
1986}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1987def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1988 "MMX_PHADDSWrm",
1989 "MMX_PHADDWrm",
1990 "MMX_PHSUBDrm",
1991 "MMX_PHSUBSWrm",
1992 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1993 "(V?)PHADDDrm",
1994 "(V?)PHADDSWrm",
1995 "(V?)PHADDWrm",
1996 "(V?)PHSUBDrm",
1997 "(V?)PHSUBSWrm",
1998 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1999
2000def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2001 let Latency = 8;
2002 let NumMicroOps = 5;
2003 let ResourceCycles = [1,1,1,2];
2004}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2005def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2006 "RCL(8|16|32|64)mi",
2007 "RCR(8|16|32|64)m1",
2008 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2009
2010def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2011 let Latency = 8;
2012 let NumMicroOps = 5;
2013 let ResourceCycles = [1,1,2,1];
2014}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2015def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2016
2017def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2018 let Latency = 8;
2019 let NumMicroOps = 6;
2020 let ResourceCycles = [1,1,1,3];
2021}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2022def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2023 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2024
2025def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2026 let Latency = 8;
2027 let NumMicroOps = 6;
2028 let ResourceCycles = [1,1,1,2,1];
2029}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2030def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2031 "CMPXCHG(8|16|32|64)rm",
2032 "ROL(8|16|32|64)mCL",
2033 "SAR(8|16|32|64)mCL",
2034 "SBB(8|16|32|64)mi",
2035 "SBB(8|16|32|64)mr",
2036 "SHL(8|16|32|64)mCL",
2037 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2038
2039def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2040 let Latency = 9;
2041 let NumMicroOps = 2;
2042 let ResourceCycles = [1,1];
2043}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2044def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2045 "ADD_F64m",
2046 "ILD_F16m",
2047 "ILD_F32m",
2048 "ILD_F64m",
2049 "SUBR_F32m",
2050 "SUBR_F64m",
2051 "SUB_F32m",
2052 "SUB_F64m",
2053 "VADDPDYrm",
2054 "VADDPSYrm",
2055 "VADDSUBPDYrm",
2056 "VADDSUBPSYrm",
2057 "VCMPPDYrmi",
2058 "VCMPPSYrmi",
2059 "VCVTDQ2PSYrm",
2060 "VCVTPS2DQYrm",
2061 "VCVTTPS2DQYrm",
2062 "VMAX(C?)PDYrm",
2063 "VMAX(C?)PSYrm",
2064 "VMIN(C?)PDYrm",
2065 "VMIN(C?)PSYrm",
2066 "VSUBPDYrm",
2067 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2068
2069def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2070 let Latency = 9;
2071 let NumMicroOps = 2;
2072 let ResourceCycles = [1,1];
2073}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2074def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2075 "VPERM2I128rm",
2076 "VPERMDYrm",
2077 "VPERMPDYmi",
2078 "VPERMPSYrm",
2079 "VPERMQYmi",
2080 "VPMOVZXBDYrm",
2081 "VPMOVZXBQYrm",
2082 "VPMOVZXBWYrm",
2083 "VPMOVZXDQYrm",
2084 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2085
2086def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2087 let Latency = 9;
2088 let NumMicroOps = 2;
2089 let ResourceCycles = [1,1];
2090}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2091def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2092 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2093
2094def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2095 let Latency = 9;
2096 let NumMicroOps = 3;
2097 let ResourceCycles = [1,1,1];
2098}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2099def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2100
2101def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2102 let Latency = 9;
2103 let NumMicroOps = 3;
2104 let ResourceCycles = [1,1,1];
2105}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2106def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2107 "(V?)CVTSD2SIrm",
2108 "(V?)CVTSS2SI64rm",
2109 "(V?)CVTSS2SIrm",
2110 "(V?)CVTTSD2SI64rm",
2111 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2112 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2113 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2114
2115def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2116 let Latency = 9;
2117 let NumMicroOps = 3;
2118 let ResourceCycles = [1,1,1];
2119}
2120def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2121
2122def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2123 let Latency = 9;
2124 let NumMicroOps = 3;
2125 let ResourceCycles = [1,1,1];
2126}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2127def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2128def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2129 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2130 "CVTTPD2DQrm",
2131 "MMX_CVTPD2PIirm",
2132 "MMX_CVTPI2PDirm",
2133 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2134 "(V?)CVTDQ2PDrm",
2135 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2136
2137def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2138 let Latency = 9;
2139 let NumMicroOps = 3;
2140 let ResourceCycles = [1,1,1];
2141}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2142def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2143 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2144
2145def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2146 let Latency = 9;
2147 let NumMicroOps = 4;
2148 let ResourceCycles = [2,1,1];
2149}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2150def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2151 "VPSRAVDYrm",
2152 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2153
2154def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2155 let Latency = 9;
2156 let NumMicroOps = 4;
2157 let ResourceCycles = [2,1,1];
2158}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2159def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2160 "VPHADDSWYrm",
2161 "VPHADDWYrm",
2162 "VPHSUBDYrm",
2163 "VPHSUBSWYrm",
2164 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2165
2166def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2167 let Latency = 9;
2168 let NumMicroOps = 4;
2169 let ResourceCycles = [1,1,1,1];
2170}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2171def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2172 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2173
2174def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2175 let Latency = 9;
2176 let NumMicroOps = 5;
2177 let ResourceCycles = [1,1,3];
2178}
2179def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2180
2181def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2182 let Latency = 9;
2183 let NumMicroOps = 5;
2184 let ResourceCycles = [1,2,1,1];
2185}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2186def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2187 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2188
2189def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2190 let Latency = 10;
2191 let NumMicroOps = 2;
2192 let ResourceCycles = [2];
2193}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2194def: InstRW<[BWWriteResGroup114], (instregex "(V?)PMULLD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2195
2196def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2197 let Latency = 10;
2198 let NumMicroOps = 2;
2199 let ResourceCycles = [1,1];
2200}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2201def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2202 "MMX_PMADDWDirm",
2203 "MMX_PMULHRSWrm",
2204 "MMX_PMULHUWirm",
2205 "MMX_PMULHWirm",
2206 "MMX_PMULLWirm",
2207 "MMX_PMULUDQirm",
2208 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2209 "(V?)PCMPGTQrm",
2210 "(V?)PHMINPOSUWrm",
2211 "(V?)PMADDUBSWrm",
2212 "(V?)PMADDWDrm",
2213 "(V?)PMULDQrm",
2214 "(V?)PMULHRSWrm",
2215 "(V?)PMULHUWrm",
2216 "(V?)PMULHWrm",
2217 "(V?)PMULLWrm",
2218 "(V?)PMULUDQrm",
2219 "(V?)PSADBWrm",
2220 "(V?)RCPPSm",
2221 "(V?)RCPSSm",
2222 "(V?)RSQRTPSm",
2223 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2224
2225def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2226 let Latency = 10;
2227 let NumMicroOps = 2;
2228 let ResourceCycles = [1,1];
2229}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2230def: InstRW<[BWWriteResGroup116],
2231 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2232 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2233
2234def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2235 let Latency = 10;
2236 let NumMicroOps = 3;
2237 let ResourceCycles = [2,1];
2238}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2239def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2240 "FICOM32m",
2241 "FICOMP16m",
2242 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2243
2244def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2245 let Latency = 10;
2246 let NumMicroOps = 3;
2247 let ResourceCycles = [1,1,1];
2248}
2249def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2250
2251def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2252 let Latency = 10;
2253 let NumMicroOps = 4;
2254 let ResourceCycles = [1,2,1];
2255}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2256def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2257 "(V?)HADDPSrm",
2258 "(V?)HSUBPDrm",
2259 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2260
2261def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2262 let Latency = 10;
2263 let NumMicroOps = 4;
2264 let ResourceCycles = [1,1,1,1];
2265}
2266def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2267
2268def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2269 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2270 let NumMicroOps = 4;
2271 let ResourceCycles = [1,1,1,1];
2272}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2273def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2274
2275def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2276 let Latency = 11;
2277 let NumMicroOps = 1;
2278 let ResourceCycles = [1];
2279}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2280def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
2281 "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2282
2283def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2284 let Latency = 11;
2285 let NumMicroOps = 2;
2286 let ResourceCycles = [1,1];
2287}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2288def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2289 "MUL_F64m",
2290 "VPCMPGTQYrm",
2291 "VPMADDUBSWYrm",
2292 "VPMADDWDYrm",
2293 "VPMULDQYrm",
2294 "VPMULHRSWYrm",
2295 "VPMULHUWYrm",
2296 "VPMULHWYrm",
2297 "VPMULLWYrm",
2298 "VPMULUDQYrm",
2299 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2300
2301def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2302 let Latency = 11;
2303 let NumMicroOps = 2;
2304 let ResourceCycles = [1,1];
2305}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2306def: InstRW<[BWWriteResGroup124],
2307 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2308
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2309def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2310 let Latency = 11;
2311 let NumMicroOps = 3;
2312 let ResourceCycles = [2,1];
2313}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2314def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2315 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2316
2317def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2318 let Latency = 11;
2319 let NumMicroOps = 3;
2320 let ResourceCycles = [2,1];
2321}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2322def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2323 "(V?)ROUNDPSm",
2324 "(V?)ROUNDSDm",
2325 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2326
2327def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2328 let Latency = 11;
2329 let NumMicroOps = 3;
2330 let ResourceCycles = [1,1,1];
2331}
2332def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2333
2334def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2335 let Latency = 11;
2336 let NumMicroOps = 4;
2337 let ResourceCycles = [1,2,1];
2338}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2339def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2340 "VHADDPSYrm",
2341 "VHSUBPDYrm",
2342 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2343
2344def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2345 let Latency = 11;
2346 let NumMicroOps = 6;
2347 let ResourceCycles = [1,1,1,1,2];
2348}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2349def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2350 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2351
2352def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2353 let Latency = 11;
2354 let NumMicroOps = 7;
2355 let ResourceCycles = [2,2,3];
2356}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2357def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2358 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2359
2360def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2361 let Latency = 11;
2362 let NumMicroOps = 9;
2363 let ResourceCycles = [1,4,1,3];
2364}
2365def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2366
2367def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2368 let Latency = 11;
2369 let NumMicroOps = 11;
2370 let ResourceCycles = [2,9];
2371}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2372def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2373def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2374
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2375def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2376 let Latency = 12;
2377 let NumMicroOps = 3;
2378 let ResourceCycles = [2,1];
2379}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2380def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2381 "ADD_FI32m",
2382 "SUBR_FI16m",
2383 "SUBR_FI32m",
2384 "SUB_FI16m",
2385 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2386 "VROUNDPDYm",
2387 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2388
2389def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2390 let Latency = 12;
2391 let NumMicroOps = 4;
2392 let ResourceCycles = [1,2,1];
2393}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2394def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2395
2396def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2397 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2398 let NumMicroOps = 1;
2399 let ResourceCycles = [1];
2400}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2401def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr",
2402 "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2403
2404def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2405 let Latency = 13;
2406 let NumMicroOps = 4;
2407 let ResourceCycles = [1,2,1];
2408}
2409def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2410
2411def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
2412 let Latency = 14;
2413 let NumMicroOps = 1;
2414 let ResourceCycles = [1];
2415}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2416def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2417 "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2418
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2419def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2420 let Latency = 14;
2421 let NumMicroOps = 3;
2422 let ResourceCycles = [1,1,1];
2423}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2424def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2425 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2426
2427def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2428 let Latency = 14;
2429 let NumMicroOps = 4;
2430 let ResourceCycles = [2,1,1];
2431}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2432def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2433
2434def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2435 let Latency = 14;
2436 let NumMicroOps = 4;
2437 let ResourceCycles = [1,1,1,1];
2438}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2439def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2440
2441def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2442 let Latency = 14;
2443 let NumMicroOps = 8;
2444 let ResourceCycles = [2,2,1,3];
2445}
2446def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2447
2448def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2449 let Latency = 14;
2450 let NumMicroOps = 10;
2451 let ResourceCycles = [2,3,1,4];
2452}
2453def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2454
2455def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2456 let Latency = 14;
2457 let NumMicroOps = 12;
2458 let ResourceCycles = [2,1,4,5];
2459}
2460def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2461
2462def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2463 let Latency = 15;
2464 let NumMicroOps = 1;
2465 let ResourceCycles = [1];
2466}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2467def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2468 "DIVR_FST0r",
2469 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2470
2471def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
2472 let Latency = 15;
2473 let NumMicroOps = 3;
2474 let ResourceCycles = [2,1];
2475}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2476def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2477
2478def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2479 let Latency = 15;
2480 let NumMicroOps = 10;
2481 let ResourceCycles = [1,1,1,4,1,2];
2482}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2483def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2484
2485def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
2486 let Latency = 16;
2487 let NumMicroOps = 2;
2488 let ResourceCycles = [1,1];
2489}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2490def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2491 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2492
2493def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2494 let Latency = 16;
2495 let NumMicroOps = 3;
2496 let ResourceCycles = [2,1];
2497}
2498def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2499
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2500def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2501 let Latency = 16;
2502 let NumMicroOps = 14;
2503 let ResourceCycles = [1,1,1,4,2,5];
2504}
2505def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2506
2507def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2508 let Latency = 16;
2509 let NumMicroOps = 16;
2510 let ResourceCycles = [16];
2511}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2512def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2513
2514def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
2515 let Latency = 17;
2516 let NumMicroOps = 3;
2517 let ResourceCycles = [2,1];
2518}
2519def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2520
2521def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2522 let Latency = 17;
2523 let NumMicroOps = 4;
2524 let ResourceCycles = [2,1,1];
2525}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2526def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2527 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2528
2529def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2530 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2531 let NumMicroOps = 2;
2532 let ResourceCycles = [1,1];
2533}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2534def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
2535 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2536
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2537def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2538 let Latency = 18;
2539 let NumMicroOps = 8;
2540 let ResourceCycles = [1,1,1,5];
2541}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2542def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2543def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2544
2545def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2546 let Latency = 18;
2547 let NumMicroOps = 11;
2548 let ResourceCycles = [2,1,1,3,1,3];
2549}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2550def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2551
2552def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
2553 let Latency = 19;
2554 let NumMicroOps = 2;
2555 let ResourceCycles = [1,1];
2556}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2557def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2558 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2559
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2560def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2561 let Latency = 19;
2562 let NumMicroOps = 5;
2563 let ResourceCycles = [2,1,1,1];
2564}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2565def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2566
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2567def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2568 let Latency = 20;
2569 let NumMicroOps = 1;
2570 let ResourceCycles = [1];
2571}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2572def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2573 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2574 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2575
2576def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2577 let Latency = 20;
2578 let NumMicroOps = 5;
2579 let ResourceCycles = [2,1,1,1];
2580}
2581def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2582
2583def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2584 let Latency = 20;
2585 let NumMicroOps = 8;
2586 let ResourceCycles = [1,1,1,1,1,1,2];
2587}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2588def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2589 "INSL",
2590 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2591
2592def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2593 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2594 let NumMicroOps = 1;
2595 let ResourceCycles = [1];
2596}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2597def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr",
2598 "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2599
2600def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2601 let Latency = 21;
2602 let NumMicroOps = 2;
2603 let ResourceCycles = [1,1];
2604}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2605def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2606 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2607
2608def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
2609 let Latency = 21;
2610 let NumMicroOps = 3;
2611 let ResourceCycles = [2,1];
2612}
2613def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2614
2615def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2616 let Latency = 21;
2617 let NumMicroOps = 19;
2618 let ResourceCycles = [2,1,4,1,1,4,6];
2619}
2620def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2621
2622def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2623 let Latency = 22;
2624 let NumMicroOps = 18;
2625 let ResourceCycles = [1,1,16];
2626}
2627def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2628
2629def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
2630 let Latency = 23;
2631 let NumMicroOps = 3;
2632 let ResourceCycles = [2,1];
2633}
2634def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2635
2636def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2637 let Latency = 23;
2638 let NumMicroOps = 4;
2639 let ResourceCycles = [2,1,1];
2640}
2641def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2642
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2643def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2644 let Latency = 23;
2645 let NumMicroOps = 19;
2646 let ResourceCycles = [3,1,15];
2647}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2648def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2649
2650def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2651 let Latency = 24;
2652 let NumMicroOps = 3;
2653 let ResourceCycles = [1,1,1];
2654}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2655def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2656 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2657
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2658def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2659 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2660 let NumMicroOps = 2;
2661 let ResourceCycles = [1,1];
2662}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2663def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2664 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2665
2666def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2667 let Latency = 26;
2668 let NumMicroOps = 2;
2669 let ResourceCycles = [1,1];
2670}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2671def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2672 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2673
2674def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2675 let Latency = 27;
2676 let NumMicroOps = 4;
2677 let ResourceCycles = [2,1,1];
2678}
2679def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2680
2681def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2682 let Latency = 29;
2683 let NumMicroOps = 3;
2684 let ResourceCycles = [1,1,1];
2685}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2686def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2687 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2688
2689def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2690 let Latency = 29;
2691 let NumMicroOps = 4;
2692 let ResourceCycles = [2,1,1];
2693}
2694def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2695
2696def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2697 let Latency = 22;
2698 let NumMicroOps = 7;
2699 let ResourceCycles = [1,3,2,1];
2700}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2701def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2702
2703def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2704 let Latency = 23;
2705 let NumMicroOps = 9;
2706 let ResourceCycles = [1,3,4,1];
2707}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2708def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2709
2710def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2711 let Latency = 24;
2712 let NumMicroOps = 9;
2713 let ResourceCycles = [1,5,2,1];
2714}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2715def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2716
2717def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2718 let Latency = 25;
2719 let NumMicroOps = 7;
2720 let ResourceCycles = [1,3,2,1];
2721}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2722def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2723 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2724
2725def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2726 let Latency = 26;
2727 let NumMicroOps = 9;
2728 let ResourceCycles = [1,5,2,1];
2729}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2730def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2731
2732def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2733 let Latency = 26;
2734 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2735 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2736}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2737def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2738
2739def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2740 let Latency = 27;
2741 let NumMicroOps = 9;
2742 let ResourceCycles = [1,5,2,1];
2743}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2744def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2745
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2746def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2747 let Latency = 29;
2748 let NumMicroOps = 27;
2749 let ResourceCycles = [1,5,1,1,19];
2750}
2751def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2752
2753def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2754 let Latency = 30;
2755 let NumMicroOps = 28;
2756 let ResourceCycles = [1,6,1,1,19];
2757}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2758def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2759
2760def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2761 let Latency = 31;
2762 let NumMicroOps = 31;
2763 let ResourceCycles = [8,1,21,1];
2764}
2765def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2766
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2767def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
2768 let Latency = 34;
2769 let NumMicroOps = 3;
2770 let ResourceCycles = [2,1];
2771}
2772def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2773
2774def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2775 let Latency = 34;
2776 let NumMicroOps = 8;
2777 let ResourceCycles = [2,2,2,1,1];
2778}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2779def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2780
2781def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2782 let Latency = 34;
2783 let NumMicroOps = 23;
2784 let ResourceCycles = [1,5,3,4,10];
2785}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2786def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2787 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2788
2789def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2790 let Latency = 35;
2791 let NumMicroOps = 8;
2792 let ResourceCycles = [2,2,2,1,1];
2793}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2794def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2795
2796def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2797 let Latency = 35;
2798 let NumMicroOps = 23;
2799 let ResourceCycles = [1,5,2,1,4,10];
2800}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2801def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2802 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2803
2804def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2805 let Latency = 40;
2806 let NumMicroOps = 4;
2807 let ResourceCycles = [2,1,1];
2808}
2809def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2810
2811def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2812 let Latency = 42;
2813 let NumMicroOps = 22;
2814 let ResourceCycles = [2,20];
2815}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2816def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2817
2818def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2819 let Latency = 60;
2820 let NumMicroOps = 64;
2821 let ResourceCycles = [2,2,8,1,10,2,39];
2822}
2823def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2824
2825def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2826 let Latency = 63;
2827 let NumMicroOps = 88;
2828 let ResourceCycles = [4,4,31,1,2,1,45];
2829}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2830def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2831
2832def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2833 let Latency = 63;
2834 let NumMicroOps = 90;
2835 let ResourceCycles = [4,2,33,1,2,1,47];
2836}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2837def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2838
2839def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2840 let Latency = 75;
2841 let NumMicroOps = 15;
2842 let ResourceCycles = [6,3,6];
2843}
2844def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2845
2846def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2847 let Latency = 80;
2848 let NumMicroOps = 32;
2849 let ResourceCycles = [7,7,3,3,1,11];
2850}
2851def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2852
2853def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2854 let Latency = 115;
2855 let NumMicroOps = 100;
2856 let ResourceCycles = [9,9,11,8,1,11,21,30];
2857}
2858def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2859
2860} // SchedModel
2861