Matt Arsenault | 7836f89 | 2016-01-20 21:22:21 +0000 | [diff] [blame] | 1 | //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //==-----------------------------------------------------------------------===// |
| 9 | // |
| 10 | /// \file |
| 11 | /// \brief Defines an instruction selector for the AMDGPU target. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
Matt Arsenault | 592d068 | 2015-12-01 23:04:05 +0000 | [diff] [blame] | 14 | |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 15 | #include "AMDGPU.h" |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 16 | #include "AMDGPUArgumentUsageInfo.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 17 | #include "AMDGPUISelLowering.h" // For AMDGPUISD |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 18 | #include "AMDGPUInstrInfo.h" |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 19 | #include "AMDGPURegisterInfo.h" |
Tom Stellard | 2e59a45 | 2014-06-13 01:32:00 +0000 | [diff] [blame] | 20 | #include "AMDGPUSubtarget.h" |
Matt Arsenault | cc85223 | 2017-10-10 20:22:07 +0000 | [diff] [blame] | 21 | #include "AMDGPUTargetMachine.h" |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 22 | #include "SIDefines.h" |
Christian Konig | f82901a | 2013-02-26 17:52:23 +0000 | [diff] [blame] | 23 | #include "SIISelLowering.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 24 | #include "SIInstrInfo.h" |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 25 | #include "SIMachineFunctionInfo.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 26 | #include "SIRegisterInfo.h" |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 27 | #include "llvm/ADT/APInt.h" |
| 28 | #include "llvm/ADT/SmallVector.h" |
| 29 | #include "llvm/ADT/StringRef.h" |
Alexander Timofeev | 2e5eece | 2018-03-05 15:12:21 +0000 | [diff] [blame] | 30 | #include "llvm/Analysis/DivergenceAnalysis.h" |
Jan Vesely | f97de00 | 2016-05-13 20:39:29 +0000 | [diff] [blame] | 31 | #include "llvm/Analysis/ValueTracking.h" |
Tom Stellard | 58ac744 | 2014-04-29 23:12:48 +0000 | [diff] [blame] | 32 | #include "llvm/CodeGen/FunctionLoweringInfo.h" |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 33 | #include "llvm/CodeGen/ISDOpcodes.h" |
| 34 | #include "llvm/CodeGen/MachineFunction.h" |
| 35 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 36 | #include "llvm/CodeGen/MachineValueType.h" |
Benjamin Kramer | d78bb46 | 2013-05-23 17:10:37 +0000 | [diff] [blame] | 37 | #include "llvm/CodeGen/SelectionDAG.h" |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 38 | #include "llvm/CodeGen/SelectionDAGISel.h" |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 39 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
| 40 | #include "llvm/CodeGen/ValueTypes.h" |
| 41 | #include "llvm/IR/BasicBlock.h" |
| 42 | #include "llvm/IR/Instruction.h" |
| 43 | #include "llvm/MC/MCInstrDesc.h" |
| 44 | #include "llvm/Support/Casting.h" |
| 45 | #include "llvm/Support/CodeGen.h" |
| 46 | #include "llvm/Support/ErrorHandling.h" |
| 47 | #include "llvm/Support/MathExtras.h" |
| 48 | #include <cassert> |
| 49 | #include <cstdint> |
| 50 | #include <new> |
| 51 | #include <vector> |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 52 | |
| 53 | using namespace llvm; |
| 54 | |
Matt Arsenault | d275921 | 2016-02-13 01:24:08 +0000 | [diff] [blame] | 55 | namespace llvm { |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 56 | |
Matt Arsenault | d275921 | 2016-02-13 01:24:08 +0000 | [diff] [blame] | 57 | class R600InstrInfo; |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 58 | |
| 59 | } // end namespace llvm |
Matt Arsenault | d275921 | 2016-02-13 01:24:08 +0000 | [diff] [blame] | 60 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 61 | //===----------------------------------------------------------------------===// |
| 62 | // Instruction Selector Implementation |
| 63 | //===----------------------------------------------------------------------===// |
| 64 | |
| 65 | namespace { |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 66 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 67 | /// AMDGPU specific code to select AMDGPU machine instructions for |
| 68 | /// SelectionDAG operations. |
| 69 | class AMDGPUDAGToDAGISel : public SelectionDAGISel { |
| 70 | // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can |
| 71 | // make the right decision when generating code for different targets. |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 72 | const AMDGPUSubtarget *Subtarget; |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 73 | AMDGPUAS AMDGPUASI; |
Matt Arsenault | cc85223 | 2017-10-10 20:22:07 +0000 | [diff] [blame] | 74 | bool EnableLateStructurizeCFG; |
NAKAMURA Takumi | a9cb538 | 2015-09-22 11:14:39 +0000 | [diff] [blame] | 75 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 76 | public: |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 77 | explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr, |
| 78 | CodeGenOpt::Level OptLevel = CodeGenOpt::Default) |
| 79 | : SelectionDAGISel(*TM, OptLevel) { |
| 80 | AMDGPUASI = AMDGPU::getAMDGPUAS(*TM); |
Matt Arsenault | cc85223 | 2017-10-10 20:22:07 +0000 | [diff] [blame] | 81 | EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG; |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 82 | } |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 83 | ~AMDGPUDAGToDAGISel() override = default; |
Konstantin Zhuravlyov | 60a8373 | 2016-10-03 18:47:26 +0000 | [diff] [blame] | 84 | |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 85 | void getAnalysisUsage(AnalysisUsage &AU) const override { |
| 86 | AU.addRequired<AMDGPUArgumentUsageInfo>(); |
Alexander Timofeev | 2e5eece | 2018-03-05 15:12:21 +0000 | [diff] [blame] | 87 | AU.addRequired<DivergenceAnalysis>(); |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 88 | SelectionDAGISel::getAnalysisUsage(AU); |
| 89 | } |
| 90 | |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 91 | bool runOnMachineFunction(MachineFunction &MF) override; |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 92 | void Select(SDNode *N) override; |
Mehdi Amini | 117296c | 2016-10-01 02:56:57 +0000 | [diff] [blame] | 93 | StringRef getPassName() const override; |
Craig Topper | 5656db4 | 2014-04-29 07:57:24 +0000 | [diff] [blame] | 94 | void PostprocessISelDAG() override; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 95 | |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 96 | protected: |
| 97 | void SelectBuildVector(SDNode *N, unsigned RegClassID); |
| 98 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 99 | private: |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 100 | std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const; |
Matt Arsenault | f84e5d9 | 2017-01-31 03:07:46 +0000 | [diff] [blame] | 101 | bool isNoNanSrc(SDValue N) const; |
Matt Arsenault | fe26775 | 2016-07-28 00:32:02 +0000 | [diff] [blame] | 102 | bool isInlineImmediate(const SDNode *N) const; |
Vincent Lejeune | c689679 | 2013-06-04 23:17:15 +0000 | [diff] [blame] | 103 | bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs, |
Tom Stellard | 8402144 | 2013-07-23 01:48:24 +0000 | [diff] [blame] | 104 | const R600InstrInfo *TII); |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 105 | bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &); |
Vincent Lejeune | c689679 | 2013-06-04 23:17:15 +0000 | [diff] [blame] | 106 | bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &); |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 107 | |
Jan Vesely | 43b7b5b | 2016-04-07 19:23:11 +0000 | [diff] [blame] | 108 | bool isConstantLoad(const MemSDNode *N, int cbID) const; |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 109 | bool isUniformBr(const SDNode *N) const; |
| 110 | |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 111 | SDNode *glueCopyToM0(SDNode *N) const; |
| 112 | |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 113 | const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const; |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 114 | bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr); |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 115 | bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg, |
| 116 | SDValue& Offset); |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 117 | virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset); |
| 118 | virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset); |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 119 | bool isDSOffsetLegal(const SDValue &Base, unsigned Offset, |
| 120 | unsigned OffsetBits) const; |
| 121 | bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const; |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 122 | bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0, |
| 123 | SDValue &Offset1) const; |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 124 | bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 125 | SDValue &SOffset, SDValue &Offset, SDValue &Offen, |
| 126 | SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC, |
| 127 | SDValue &TFE) const; |
| 128 | bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 129 | SDValue &SOffset, SDValue &Offset, SDValue &GLC, |
| 130 | SDValue &SLC, SDValue &TFE) const; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 131 | bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 132 | SDValue &VAddr, SDValue &SOffset, SDValue &Offset, |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 133 | SDValue &SLC) const; |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 134 | bool SelectMUBUFScratchOffen(SDNode *Parent, |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 135 | SDValue Addr, SDValue &RSrc, SDValue &VAddr, |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 136 | SDValue &SOffset, SDValue &ImmOffset) const; |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 137 | bool SelectMUBUFScratchOffset(SDNode *Parent, |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 138 | SDValue Addr, SDValue &SRsrc, SDValue &Soffset, |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 139 | SDValue &Offset) const; |
| 140 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 141 | bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset, |
| 142 | SDValue &Offset, SDValue &GLC, SDValue &SLC, |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 143 | SDValue &TFE) const; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 144 | bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 145 | SDValue &Offset, SDValue &SLC) const; |
Jan Vesely | 43b7b5b | 2016-04-07 19:23:11 +0000 | [diff] [blame] | 146 | bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, |
| 147 | SDValue &Offset) const; |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 148 | bool SelectMUBUFConstant(SDValue Constant, |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 149 | SDValue &SOffset, |
| 150 | SDValue &ImmOffset) const; |
| 151 | bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset, |
| 152 | SDValue &ImmOffset) const; |
| 153 | bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset, |
| 154 | SDValue &ImmOffset, SDValue &VOffset) const; |
Matt Arsenault | 7757c59 | 2016-06-09 23:42:54 +0000 | [diff] [blame] | 155 | |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 156 | bool SelectFlatAtomic(SDValue Addr, SDValue &VAddr, |
| 157 | SDValue &Offset, SDValue &SLC) const; |
Matt Arsenault | 4e309b0 | 2017-07-29 01:03:53 +0000 | [diff] [blame] | 158 | bool SelectFlatAtomicSigned(SDValue Addr, SDValue &VAddr, |
| 159 | SDValue &Offset, SDValue &SLC) const; |
| 160 | |
| 161 | template <bool IsSigned> |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 162 | bool SelectFlatOffset(SDValue Addr, SDValue &VAddr, |
| 163 | SDValue &Offset, SDValue &SLC) const; |
Matt Arsenault | 7757c59 | 2016-06-09 23:42:54 +0000 | [diff] [blame] | 164 | |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 165 | bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset, |
| 166 | bool &Imm) const; |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 167 | SDValue Expand32BitAddress(SDValue Addr) const; |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 168 | bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset, |
| 169 | bool &Imm) const; |
| 170 | bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const; |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 171 | bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const; |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 172 | bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const; |
| 173 | bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const; |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 174 | bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const; |
Nicolai Haehnle | 7968c34 | 2016-07-12 08:12:16 +0000 | [diff] [blame] | 175 | bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const; |
Matt Arsenault | f84e5d9 | 2017-01-31 03:07:46 +0000 | [diff] [blame] | 176 | |
| 177 | bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 178 | bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 179 | bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
Matt Arsenault | df58e82 | 2017-04-25 21:17:38 +0000 | [diff] [blame] | 180 | bool SelectVOP3NoMods(SDValue In, SDValue &Src) const; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 181 | bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 182 | SDValue &Clamp, SDValue &Omod) const; |
Tom Stellard | db5a11f | 2015-07-13 15:47:57 +0000 | [diff] [blame] | 183 | bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 184 | SDValue &Clamp, SDValue &Omod) const; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 185 | |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 186 | bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 187 | SDValue &Clamp, |
| 188 | SDValue &Omod) const; |
Matt Arsenault | 1cffa4c | 2014-11-13 19:49:04 +0000 | [diff] [blame] | 189 | |
Dmitry Preobrazhensky | c512d44 | 2017-03-27 15:57:17 +0000 | [diff] [blame] | 190 | bool SelectVOP3OMods(SDValue In, SDValue &Src, |
| 191 | SDValue &Clamp, SDValue &Omod) const; |
| 192 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 193 | bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
| 194 | bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 195 | SDValue &Clamp) const; |
| 196 | |
Dmitry Preobrazhensky | abf2839 | 2017-07-21 13:54:11 +0000 | [diff] [blame] | 197 | bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
| 198 | bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 199 | SDValue &Clamp) const; |
| 200 | |
| 201 | bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
| 202 | bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods, |
| 203 | SDValue &Clamp) const; |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 204 | bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const; |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 205 | bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const; |
Dmitry Preobrazhensky | abf2839 | 2017-07-21 13:54:11 +0000 | [diff] [blame] | 206 | |
Matt Arsenault | e1cd482 | 2017-11-13 00:22:09 +0000 | [diff] [blame] | 207 | bool SelectHi16Elt(SDValue In, SDValue &Src) const; |
| 208 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 209 | void SelectADD_SUB_I64(SDNode *N); |
Matt Arsenault | ee3f0ac | 2017-01-30 18:11:38 +0000 | [diff] [blame] | 210 | void SelectUADDO_USUBO(SDNode *N); |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 211 | void SelectDIV_SCALE(SDNode *N); |
Matt Arsenault | 4f6318f | 2017-11-06 17:04:37 +0000 | [diff] [blame] | 212 | void SelectMAD_64_32(SDNode *N); |
Tom Stellard | 8485fa0 | 2016-12-07 02:42:15 +0000 | [diff] [blame] | 213 | void SelectFMA_W_CHAIN(SDNode *N); |
| 214 | void SelectFMUL_W_CHAIN(SDNode *N); |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 215 | |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 216 | SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val, |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 217 | uint32_t Offset, uint32_t Width); |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 218 | void SelectS_BFEFromShifts(SDNode *N); |
| 219 | void SelectS_BFE(SDNode *N); |
Matt Arsenault | 7b1dc2c | 2016-09-17 02:02:19 +0000 | [diff] [blame] | 220 | bool isCBranchSCC(const SDNode *N) const; |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 221 | void SelectBRCOND(SDNode *N); |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 222 | void SelectFMAD(SDNode *N); |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 223 | void SelectATOMIC_CMP_SWAP(SDNode *N); |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 224 | |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 225 | protected: |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 226 | // Include the pieces autogenerated from the target description. |
| 227 | #include "AMDGPUGenDAGISel.inc" |
| 228 | }; |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 229 | |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 230 | class R600DAGToDAGISel : public AMDGPUDAGToDAGISel { |
| 231 | public: |
| 232 | explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) : |
| 233 | AMDGPUDAGToDAGISel(TM, OptLevel) {} |
| 234 | |
| 235 | void Select(SDNode *N) override; |
| 236 | |
| 237 | bool SelectADDRIndirect(SDValue Addr, SDValue &Base, |
| 238 | SDValue &Offset) override; |
| 239 | bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, |
| 240 | SDValue &Offset) override; |
| 241 | }; |
| 242 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 243 | } // end anonymous namespace |
| 244 | |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 245 | INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "isel", |
| 246 | "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) |
| 247 | INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo) |
| 248 | INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel", |
| 249 | "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) |
| 250 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 251 | /// \brief This pass converts a legalized DAG into a AMDGPU-specific |
| 252 | // DAG, ready for instruction scheduling. |
Matt Arsenault | 7016f13 | 2017-08-03 22:30:46 +0000 | [diff] [blame] | 253 | FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM, |
Konstantin Zhuravlyov | 60a8373 | 2016-10-03 18:47:26 +0000 | [diff] [blame] | 254 | CodeGenOpt::Level OptLevel) { |
| 255 | return new AMDGPUDAGToDAGISel(TM, OptLevel); |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 256 | } |
| 257 | |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 258 | /// \brief This pass converts a legalized DAG into a R600-specific |
| 259 | // DAG, ready for instruction scheduling. |
| 260 | FunctionPass *llvm::createR600ISelDag(TargetMachine *TM, |
| 261 | CodeGenOpt::Level OptLevel) { |
| 262 | return new R600DAGToDAGISel(TM, OptLevel); |
| 263 | } |
| 264 | |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 265 | bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 266 | Subtarget = &MF.getSubtarget<AMDGPUSubtarget>(); |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 267 | return SelectionDAGISel::runOnMachineFunction(MF); |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 268 | } |
| 269 | |
Matt Arsenault | f84e5d9 | 2017-01-31 03:07:46 +0000 | [diff] [blame] | 270 | bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const { |
| 271 | if (TM.Options.NoNaNsFPMath) |
| 272 | return true; |
| 273 | |
| 274 | // TODO: Move into isKnownNeverNaN |
Amara Emerson | d28f0cd4 | 2017-05-01 15:17:51 +0000 | [diff] [blame] | 275 | if (N->getFlags().isDefined()) |
| 276 | return N->getFlags().hasNoNaNs(); |
Matt Arsenault | f84e5d9 | 2017-01-31 03:07:46 +0000 | [diff] [blame] | 277 | |
| 278 | return CurDAG->isKnownNeverNaN(N); |
| 279 | } |
| 280 | |
Matt Arsenault | fe26775 | 2016-07-28 00:32:02 +0000 | [diff] [blame] | 281 | bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const { |
| 282 | const SIInstrInfo *TII |
| 283 | = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo(); |
| 284 | |
| 285 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) |
| 286 | return TII->isInlineConstant(C->getAPIntValue()); |
| 287 | |
| 288 | if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) |
| 289 | return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt()); |
| 290 | |
| 291 | return false; |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 294 | /// \brief Determine the register class for \p OpNo |
| 295 | /// \returns The register class of the virtual register that will be used for |
| 296 | /// the given operand number \OpNo or NULL if the register class cannot be |
| 297 | /// determined. |
| 298 | const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N, |
| 299 | unsigned OpNo) const { |
Matt Arsenault | c507cdb | 2016-11-01 23:22:17 +0000 | [diff] [blame] | 300 | if (!N->isMachineOpcode()) { |
| 301 | if (N->getOpcode() == ISD::CopyToReg) { |
| 302 | unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); |
| 303 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 304 | MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo(); |
| 305 | return MRI.getRegClass(Reg); |
| 306 | } |
| 307 | |
| 308 | const SIRegisterInfo *TRI |
| 309 | = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo(); |
| 310 | return TRI->getPhysRegClass(Reg); |
| 311 | } |
| 312 | |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 313 | return nullptr; |
Matt Arsenault | c507cdb | 2016-11-01 23:22:17 +0000 | [diff] [blame] | 314 | } |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 315 | |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 316 | switch (N->getMachineOpcode()) { |
| 317 | default: { |
Eric Christopher | d913448 | 2014-08-04 21:25:23 +0000 | [diff] [blame] | 318 | const MCInstrDesc &Desc = |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 319 | Subtarget->getInstrInfo()->get(N->getMachineOpcode()); |
Alexey Samsonov | 3186eb3 | 2013-08-15 07:11:34 +0000 | [diff] [blame] | 320 | unsigned OpIdx = Desc.getNumDefs() + OpNo; |
| 321 | if (OpIdx >= Desc.getNumOperands()) |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 322 | return nullptr; |
Alexey Samsonov | 3186eb3 | 2013-08-15 07:11:34 +0000 | [diff] [blame] | 323 | int RegClass = Desc.OpInfo[OpIdx].RegClass; |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 324 | if (RegClass == -1) |
| 325 | return nullptr; |
| 326 | |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 327 | return Subtarget->getRegisterInfo()->getRegClass(RegClass); |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 328 | } |
| 329 | case AMDGPU::REG_SEQUENCE: { |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 330 | unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); |
Eric Christopher | d913448 | 2014-08-04 21:25:23 +0000 | [diff] [blame] | 331 | const TargetRegisterClass *SuperRC = |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 332 | Subtarget->getRegisterInfo()->getRegClass(RCID); |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 333 | |
| 334 | SDValue SubRegOp = N->getOperand(OpNo + 1); |
| 335 | unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 336 | return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, |
| 337 | SubRegIdx); |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | } |
| 341 | |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 342 | SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const { |
Matt Arsenault | 3f71c0e | 2017-11-29 00:55:57 +0000 | [diff] [blame] | 343 | if (cast<MemSDNode>(N)->getAddressSpace() != AMDGPUASI.LOCAL_ADDRESS || |
| 344 | !Subtarget->ldsRequiresM0Init()) |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 345 | return N; |
| 346 | |
| 347 | const SITargetLowering& Lowering = |
| 348 | *static_cast<const SITargetLowering*>(getTargetLowering()); |
| 349 | |
| 350 | // Write max value to m0 before each load operation |
| 351 | |
| 352 | SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N), |
| 353 | CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32)); |
| 354 | |
| 355 | SDValue Glue = M0.getValue(1); |
| 356 | |
| 357 | SmallVector <SDValue, 8> Ops; |
| 358 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
| 359 | Ops.push_back(N->getOperand(i)); |
| 360 | } |
| 361 | Ops.push_back(Glue); |
Matt Arsenault | e6667de | 2017-12-04 22:18:22 +0000 | [diff] [blame] | 362 | return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops); |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 363 | } |
| 364 | |
Matt Arsenault | 61cb6fa | 2015-11-11 00:01:36 +0000 | [diff] [blame] | 365 | static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) { |
Matt Arsenault | f1aebbf | 2015-11-02 23:30:48 +0000 | [diff] [blame] | 366 | switch (NumVectorElts) { |
| 367 | case 1: |
Marek Olsak | 79c0587 | 2016-11-25 17:37:09 +0000 | [diff] [blame] | 368 | return AMDGPU::SReg_32_XM0RegClassID; |
Matt Arsenault | f1aebbf | 2015-11-02 23:30:48 +0000 | [diff] [blame] | 369 | case 2: |
| 370 | return AMDGPU::SReg_64RegClassID; |
| 371 | case 4: |
| 372 | return AMDGPU::SReg_128RegClassID; |
| 373 | case 8: |
| 374 | return AMDGPU::SReg_256RegClassID; |
| 375 | case 16: |
| 376 | return AMDGPU::SReg_512RegClassID; |
| 377 | } |
| 378 | |
| 379 | llvm_unreachable("invalid vector size"); |
| 380 | } |
| 381 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 382 | static bool getConstantValue(SDValue N, uint32_t &Out) { |
| 383 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { |
| 384 | Out = C->getAPIntValue().getZExtValue(); |
| 385 | return true; |
| 386 | } |
| 387 | |
| 388 | if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) { |
| 389 | Out = C->getValueAPF().bitcastToAPInt().getZExtValue(); |
| 390 | return true; |
| 391 | } |
| 392 | |
| 393 | return false; |
| 394 | } |
| 395 | |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 396 | void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 397 | EVT VT = N->getValueType(0); |
| 398 | unsigned NumVectorElts = VT.getVectorNumElements(); |
| 399 | EVT EltVT = VT.getVectorElementType(); |
| 400 | const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo(); |
| 401 | SDLoc DL(N); |
| 402 | SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); |
| 403 | |
| 404 | if (NumVectorElts == 1) { |
| 405 | CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0), |
| 406 | RegClass); |
| 407 | return; |
| 408 | } |
| 409 | |
| 410 | assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not " |
| 411 | "supported yet"); |
| 412 | // 16 = Max Num Vector Elements |
| 413 | // 2 = 2 REG_SEQUENCE operands per element (value, subreg index) |
| 414 | // 1 = Vector Register Class |
| 415 | SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1); |
| 416 | |
| 417 | RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); |
| 418 | bool IsRegSeq = true; |
| 419 | unsigned NOps = N->getNumOperands(); |
| 420 | for (unsigned i = 0; i < NOps; i++) { |
| 421 | // XXX: Why is this here? |
| 422 | if (isa<RegisterSDNode>(N->getOperand(i))) { |
| 423 | IsRegSeq = false; |
| 424 | break; |
| 425 | } |
| 426 | RegSeqArgs[1 + (2 * i)] = N->getOperand(i); |
| 427 | RegSeqArgs[1 + (2 * i) + 1] = |
| 428 | CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, |
| 429 | MVT::i32); |
| 430 | } |
| 431 | if (NOps != NumVectorElts) { |
| 432 | // Fill in the missing undef elements if this was a scalar_to_vector. |
Tom Stellard | 03aa3ae | 2017-08-08 05:52:00 +0000 | [diff] [blame] | 433 | assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 434 | MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, |
| 435 | DL, EltVT); |
| 436 | for (unsigned i = NOps; i < NumVectorElts; ++i) { |
| 437 | RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); |
| 438 | RegSeqArgs[1 + (2 * i) + 1] = |
| 439 | CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | if (!IsRegSeq) |
| 444 | SelectCode(N); |
| 445 | CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs); |
| 446 | } |
| 447 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 448 | void AMDGPUDAGToDAGISel::Select(SDNode *N) { |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 449 | unsigned int Opc = N->getOpcode(); |
| 450 | if (N->isMachineOpcode()) { |
Tim Northover | 31d093c | 2013-09-22 08:21:56 +0000 | [diff] [blame] | 451 | N->setNodeId(-1); |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 452 | return; // Already selected. |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 453 | } |
Matt Arsenault | 78b8670 | 2014-04-18 05:19:26 +0000 | [diff] [blame] | 454 | |
Matt Arsenault | a9dbdca | 2016-04-12 14:05:04 +0000 | [diff] [blame] | 455 | if (isa<AtomicSDNode>(N) || |
Daniil Fukalov | d5fca55 | 2018-01-17 14:05:05 +0000 | [diff] [blame] | 456 | (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC || |
| 457 | Opc == AMDGPUISD::ATOMIC_LOAD_FADD || |
| 458 | Opc == AMDGPUISD::ATOMIC_LOAD_FMIN || |
| 459 | Opc == AMDGPUISD::ATOMIC_LOAD_FMAX)) |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 460 | N = glueCopyToM0(N); |
| 461 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 462 | switch (Opc) { |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 463 | default: |
| 464 | break; |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 465 | // We are selecting i64 ADD here instead of custom lower it during |
| 466 | // DAG legalization, so we can fold some i64 ADDs used for address |
| 467 | // calculation into the LOAD and STORE instructions. |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 468 | case ISD::ADDC: |
| 469 | case ISD::ADDE: |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 470 | case ISD::SUBC: |
| 471 | case ISD::SUBE: { |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 472 | if (N->getValueType(0) != MVT::i64) |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 473 | break; |
| 474 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 475 | SelectADD_SUB_I64(N); |
| 476 | return; |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 477 | } |
Matt Arsenault | ee3f0ac | 2017-01-30 18:11:38 +0000 | [diff] [blame] | 478 | case ISD::UADDO: |
| 479 | case ISD::USUBO: { |
| 480 | SelectUADDO_USUBO(N); |
| 481 | return; |
| 482 | } |
Tom Stellard | 8485fa0 | 2016-12-07 02:42:15 +0000 | [diff] [blame] | 483 | case AMDGPUISD::FMUL_W_CHAIN: { |
| 484 | SelectFMUL_W_CHAIN(N); |
| 485 | return; |
| 486 | } |
| 487 | case AMDGPUISD::FMA_W_CHAIN: { |
| 488 | SelectFMA_W_CHAIN(N); |
| 489 | return; |
| 490 | } |
| 491 | |
Matt Arsenault | 064c206 | 2014-06-11 17:40:32 +0000 | [diff] [blame] | 492 | case ISD::SCALAR_TO_VECTOR: |
Vincent Lejeune | 3b6f20e | 2013-03-05 15:04:49 +0000 | [diff] [blame] | 493 | case ISD::BUILD_VECTOR: { |
Tom Stellard | 8e5da41 | 2013-08-14 23:24:32 +0000 | [diff] [blame] | 494 | EVT VT = N->getValueType(0); |
| 495 | unsigned NumVectorElts = VT.getVectorNumElements(); |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 496 | |
| 497 | if (VT == MVT::v2i16 || VT == MVT::v2f16) { |
| 498 | if (Opc == ISD::BUILD_VECTOR) { |
| 499 | uint32_t LHSVal, RHSVal; |
| 500 | if (getConstantValue(N->getOperand(0), LHSVal) && |
| 501 | getConstantValue(N->getOperand(1), RHSVal)) { |
| 502 | uint32_t K = LHSVal | (RHSVal << 16); |
| 503 | CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, VT, |
| 504 | CurDAG->getTargetConstant(K, SDLoc(N), MVT::i32)); |
| 505 | return; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | break; |
| 510 | } |
| 511 | |
Tom Stellard | 03aa3ae | 2017-08-08 05:52:00 +0000 | [diff] [blame] | 512 | assert(VT.getVectorElementType().bitsEq(MVT::i32)); |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 513 | unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); |
| 514 | SelectBuildVector(N, RegClassID); |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 515 | return; |
Vincent Lejeune | 3b6f20e | 2013-03-05 15:04:49 +0000 | [diff] [blame] | 516 | } |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 517 | case ISD::BUILD_PAIR: { |
| 518 | SDValue RC, SubReg0, SubReg1; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 519 | SDLoc DL(N); |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 520 | if (N->getValueType(0) == MVT::i128) { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 521 | RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32); |
| 522 | SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); |
| 523 | SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 524 | } else if (N->getValueType(0) == MVT::i64) { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 525 | RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32); |
| 526 | SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); |
| 527 | SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 528 | } else { |
| 529 | llvm_unreachable("Unhandled value type for BUILD_PAIR"); |
| 530 | } |
| 531 | const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, |
| 532 | N->getOperand(1), SubReg1 }; |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 533 | ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, |
| 534 | N->getValueType(0), Ops)); |
| 535 | return; |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 536 | } |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 537 | |
| 538 | case ISD::Constant: |
| 539 | case ISD::ConstantFP: { |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 540 | if (N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N)) |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 541 | break; |
| 542 | |
| 543 | uint64_t Imm; |
| 544 | if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N)) |
| 545 | Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue(); |
| 546 | else { |
Tom Stellard | 3cbe014 | 2014-04-07 19:31:13 +0000 | [diff] [blame] | 547 | ConstantSDNode *C = cast<ConstantSDNode>(N); |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 548 | Imm = C->getZExtValue(); |
| 549 | } |
| 550 | |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 551 | SDLoc DL(N); |
| 552 | SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, |
| 553 | CurDAG->getConstant(Imm & 0xFFFFFFFF, DL, |
| 554 | MVT::i32)); |
| 555 | SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, |
| 556 | CurDAG->getConstant(Imm >> 32, DL, MVT::i32)); |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 557 | const SDValue Ops[] = { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 558 | CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), |
| 559 | SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), |
| 560 | SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32) |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 561 | }; |
| 562 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 563 | ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, |
| 564 | N->getValueType(0), Ops)); |
| 565 | return; |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 566 | } |
Matt Arsenault | 4bf43d4 | 2015-09-25 17:27:08 +0000 | [diff] [blame] | 567 | case ISD::LOAD: |
Tom Stellard | 096b8c1 | 2015-02-04 20:49:49 +0000 | [diff] [blame] | 568 | case ISD::STORE: { |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame] | 569 | N = glueCopyToM0(N); |
Tom Stellard | 096b8c1 | 2015-02-04 20:49:49 +0000 | [diff] [blame] | 570 | break; |
| 571 | } |
Matt Arsenault | 78b8670 | 2014-04-18 05:19:26 +0000 | [diff] [blame] | 572 | |
| 573 | case AMDGPUISD::BFE_I32: |
| 574 | case AMDGPUISD::BFE_U32: { |
Matt Arsenault | 78b8670 | 2014-04-18 05:19:26 +0000 | [diff] [blame] | 575 | // There is a scalar version available, but unlike the vector version which |
| 576 | // has a separate operand for the offset and width, the scalar version packs |
| 577 | // the width and offset into a single operand. Try to move to the scalar |
| 578 | // version if the offsets are constant, so that we can try to keep extended |
| 579 | // loads of kernel arguments in SGPRs. |
| 580 | |
| 581 | // TODO: Technically we could try to pattern match scalar bitshifts of |
| 582 | // dynamic values, but it's probably not useful. |
| 583 | ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); |
| 584 | if (!Offset) |
| 585 | break; |
| 586 | |
| 587 | ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2)); |
| 588 | if (!Width) |
| 589 | break; |
| 590 | |
| 591 | bool Signed = Opc == AMDGPUISD::BFE_I32; |
| 592 | |
Matt Arsenault | 78b8670 | 2014-04-18 05:19:26 +0000 | [diff] [blame] | 593 | uint32_t OffsetVal = Offset->getZExtValue(); |
| 594 | uint32_t WidthVal = Width->getZExtValue(); |
| 595 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 596 | ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, |
| 597 | SDLoc(N), N->getOperand(0), OffsetVal, WidthVal)); |
| 598 | return; |
Matt Arsenault | 78b8670 | 2014-04-18 05:19:26 +0000 | [diff] [blame] | 599 | } |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 600 | case AMDGPUISD::DIV_SCALE: { |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 601 | SelectDIV_SCALE(N); |
| 602 | return; |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 603 | } |
Matt Arsenault | 4f6318f | 2017-11-06 17:04:37 +0000 | [diff] [blame] | 604 | case AMDGPUISD::MAD_I64_I32: |
| 605 | case AMDGPUISD::MAD_U64_U32: { |
| 606 | SelectMAD_64_32(N); |
| 607 | return; |
| 608 | } |
Tom Stellard | 3457a84 | 2014-10-09 19:06:00 +0000 | [diff] [blame] | 609 | case ISD::CopyToReg: { |
| 610 | const SITargetLowering& Lowering = |
| 611 | *static_cast<const SITargetLowering*>(getTargetLowering()); |
Matt Arsenault | 0d0d6c2 | 2017-04-12 21:58:23 +0000 | [diff] [blame] | 612 | N = Lowering.legalizeTargetIndependentNode(N, *CurDAG); |
Tom Stellard | 3457a84 | 2014-10-09 19:06:00 +0000 | [diff] [blame] | 613 | break; |
| 614 | } |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 615 | case ISD::AND: |
| 616 | case ISD::SRL: |
| 617 | case ISD::SRA: |
Matt Arsenault | 7e8de01 | 2016-04-22 22:59:16 +0000 | [diff] [blame] | 618 | case ISD::SIGN_EXTEND_INREG: |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 619 | if (N->getValueType(0) != MVT::i32) |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 620 | break; |
| 621 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 622 | SelectS_BFE(N); |
| 623 | return; |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 624 | case ISD::BRCOND: |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 625 | SelectBRCOND(N); |
| 626 | return; |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 627 | case ISD::FMAD: |
| 628 | SelectFMAD(N); |
| 629 | return; |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 630 | case AMDGPUISD::ATOMIC_CMP_SWAP: |
| 631 | SelectATOMIC_CMP_SWAP(N); |
| 632 | return; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 633 | } |
Tom Stellard | 3457a84 | 2014-10-09 19:06:00 +0000 | [diff] [blame] | 634 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 635 | SelectCode(N); |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 636 | } |
| 637 | |
Jan Vesely | 43b7b5b | 2016-04-07 19:23:11 +0000 | [diff] [blame] | 638 | bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const { |
| 639 | if (!N->readMem()) |
| 640 | return false; |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 641 | if (CbId == -1) |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 642 | return N->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS || |
| 643 | N->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS_32BIT; |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 644 | |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 645 | return N->getAddressSpace() == AMDGPUASI.CONSTANT_BUFFER_0 + CbId; |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 648 | bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const { |
| 649 | const BasicBlock *BB = FuncInfo->MBB->getBasicBlock(); |
Nicolai Haehnle | 05b127d | 2016-04-14 17:42:35 +0000 | [diff] [blame] | 650 | const Instruction *Term = BB->getTerminator(); |
| 651 | return Term->getMetadata("amdgpu.uniform") || |
| 652 | Term->getMetadata("structurizecfg.uniform"); |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 653 | } |
| 654 | |
Mehdi Amini | 117296c | 2016-10-01 02:56:57 +0000 | [diff] [blame] | 655 | StringRef AMDGPUDAGToDAGISel::getPassName() const { |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 656 | return "AMDGPU DAG->DAG Pattern Instruction Selection"; |
| 657 | } |
| 658 | |
Tom Stellard | 41fc785 | 2013-07-23 01:48:42 +0000 | [diff] [blame] | 659 | //===----------------------------------------------------------------------===// |
| 660 | // Complex Patterns |
| 661 | //===----------------------------------------------------------------------===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 662 | |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 663 | bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr, |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 664 | SDValue& IntPtr) { |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 665 | if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 666 | IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr), |
| 667 | true); |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 668 | return true; |
| 669 | } |
| 670 | return false; |
| 671 | } |
| 672 | |
| 673 | bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr, |
| 674 | SDValue& BaseReg, SDValue &Offset) { |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 675 | if (!isa<ConstantSDNode>(Addr)) { |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 676 | BaseReg = Addr; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 677 | Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true); |
Tom Stellard | 365366f | 2013-01-23 02:09:06 +0000 | [diff] [blame] | 678 | return true; |
| 679 | } |
| 680 | return false; |
| 681 | } |
| 682 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 683 | bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 684 | SDValue &Offset) { |
| 685 | return false; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 686 | } |
| 687 | |
Tom Stellard | f3b2a1e | 2013-02-06 17:32:29 +0000 | [diff] [blame] | 688 | bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, |
| 689 | SDValue &Offset) { |
| 690 | ConstantSDNode *C; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 691 | SDLoc DL(Addr); |
Tom Stellard | f3b2a1e | 2013-02-06 17:32:29 +0000 | [diff] [blame] | 692 | |
| 693 | if ((C = dyn_cast<ConstantSDNode>(Addr))) { |
| 694 | Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 695 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
Jan Vesely | 06200bd | 2017-01-06 21:00:46 +0000 | [diff] [blame] | 696 | } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) && |
| 697 | (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) { |
| 698 | Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32); |
| 699 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
Tom Stellard | f3b2a1e | 2013-02-06 17:32:29 +0000 | [diff] [blame] | 700 | } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) && |
| 701 | (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) { |
| 702 | Base = Addr.getOperand(0); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 703 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
Tom Stellard | f3b2a1e | 2013-02-06 17:32:29 +0000 | [diff] [blame] | 704 | } else { |
| 705 | Base = Addr; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 706 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | f3b2a1e | 2013-02-06 17:32:29 +0000 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | return true; |
| 710 | } |
Christian Konig | d910b7d | 2013-02-26 17:52:16 +0000 | [diff] [blame] | 711 | |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 712 | // FIXME: Should only handle addcarry/subcarry |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 713 | void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) { |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 714 | SDLoc DL(N); |
| 715 | SDValue LHS = N->getOperand(0); |
| 716 | SDValue RHS = N->getOperand(1); |
| 717 | |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 718 | unsigned Opcode = N->getOpcode(); |
| 719 | bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); |
| 720 | bool ProduceCarry = |
| 721 | ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 722 | bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; |
Matt Arsenault | b8b5153 | 2014-06-23 18:00:38 +0000 | [diff] [blame] | 723 | |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 724 | SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); |
| 725 | SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 726 | |
| 727 | SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, |
| 728 | DL, MVT::i32, LHS, Sub0); |
| 729 | SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, |
| 730 | DL, MVT::i32, LHS, Sub1); |
| 731 | |
| 732 | SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, |
| 733 | DL, MVT::i32, RHS, Sub0); |
| 734 | SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, |
| 735 | DL, MVT::i32, RHS, Sub1); |
| 736 | |
| 737 | SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue); |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 738 | |
Tom Stellard | 80942a1 | 2014-09-05 14:07:59 +0000 | [diff] [blame] | 739 | unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32; |
Matt Arsenault | b8b5153 | 2014-06-23 18:00:38 +0000 | [diff] [blame] | 740 | unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; |
| 741 | |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 742 | SDNode *AddLo; |
| 743 | if (!ConsumeCarry) { |
| 744 | SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) }; |
| 745 | AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args); |
| 746 | } else { |
| 747 | SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) }; |
| 748 | AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args); |
| 749 | } |
| 750 | SDValue AddHiArgs[] = { |
| 751 | SDValue(Hi0, 0), |
| 752 | SDValue(Hi1, 0), |
| 753 | SDValue(AddLo, 1) |
| 754 | }; |
| 755 | SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs); |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 756 | |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 757 | SDValue RegSequenceArgs[] = { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 758 | CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 759 | SDValue(AddLo,0), |
| 760 | Sub0, |
| 761 | SDValue(AddHi,0), |
| 762 | Sub1, |
| 763 | }; |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 764 | SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, |
| 765 | MVT::i64, RegSequenceArgs); |
| 766 | |
| 767 | if (ProduceCarry) { |
| 768 | // Replace the carry-use |
Nirav Dave | 5f0ab71 | 2018-03-17 19:24:54 +0000 | [diff] [blame] | 769 | CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1)); |
Nicolai Haehnle | 67624af | 2016-10-14 10:30:00 +0000 | [diff] [blame] | 770 | } |
| 771 | |
| 772 | // Replace the remaining uses. |
Nirav Dave | 5f0ab71 | 2018-03-17 19:24:54 +0000 | [diff] [blame] | 773 | CurDAG->ReplaceAllUsesWith(N, RegSequence); |
| 774 | CurDAG->RemoveDeadNode(N); |
Matt Arsenault | 9fa3f93 | 2014-06-23 18:00:34 +0000 | [diff] [blame] | 775 | } |
| 776 | |
Matt Arsenault | ee3f0ac | 2017-01-30 18:11:38 +0000 | [diff] [blame] | 777 | void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) { |
| 778 | // The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned |
| 779 | // carry out despite the _i32 name. These were renamed in VI to _U32. |
| 780 | // FIXME: We should probably rename the opcodes here. |
| 781 | unsigned Opc = N->getOpcode() == ISD::UADDO ? |
| 782 | AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64; |
| 783 | |
| 784 | CurDAG->SelectNodeTo(N, Opc, N->getVTList(), |
| 785 | { N->getOperand(0), N->getOperand(1) }); |
| 786 | } |
| 787 | |
Tom Stellard | 8485fa0 | 2016-12-07 02:42:15 +0000 | [diff] [blame] | 788 | void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) { |
| 789 | SDLoc SL(N); |
| 790 | // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod |
| 791 | SDValue Ops[10]; |
| 792 | |
| 793 | SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]); |
| 794 | SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]); |
| 795 | SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]); |
| 796 | Ops[8] = N->getOperand(0); |
| 797 | Ops[9] = N->getOperand(4); |
| 798 | |
| 799 | CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops); |
| 800 | } |
| 801 | |
| 802 | void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) { |
| 803 | SDLoc SL(N); |
NAKAMURA Takumi | 6f43bd4 | 2017-10-18 13:31:28 +0000 | [diff] [blame] | 804 | // src0_modifiers, src0, src1_modifiers, src1, clamp, omod |
Tom Stellard | 8485fa0 | 2016-12-07 02:42:15 +0000 | [diff] [blame] | 805 | SDValue Ops[8]; |
| 806 | |
| 807 | SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]); |
| 808 | SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]); |
| 809 | Ops[6] = N->getOperand(0); |
| 810 | Ops[7] = N->getOperand(3); |
| 811 | |
| 812 | CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops); |
| 813 | } |
| 814 | |
Matt Arsenault | 044f1d1 | 2015-02-14 04:24:28 +0000 | [diff] [blame] | 815 | // We need to handle this here because tablegen doesn't support matching |
| 816 | // instructions with multiple outputs. |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 817 | void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) { |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 818 | SDLoc SL(N); |
| 819 | EVT VT = N->getValueType(0); |
| 820 | |
| 821 | assert(VT == MVT::f32 || VT == MVT::f64); |
| 822 | |
| 823 | unsigned Opc |
| 824 | = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32; |
| 825 | |
Matt Arsenault | 3b99f12 | 2017-01-19 06:04:12 +0000 | [diff] [blame] | 826 | SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; |
| 827 | CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops); |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 828 | } |
| 829 | |
Matt Arsenault | 4f6318f | 2017-11-06 17:04:37 +0000 | [diff] [blame] | 830 | // We need to handle this here because tablegen doesn't support matching |
| 831 | // instructions with multiple outputs. |
| 832 | void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) { |
| 833 | SDLoc SL(N); |
| 834 | bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32; |
| 835 | unsigned Opc = Signed ? AMDGPU::V_MAD_I64_I32 : AMDGPU::V_MAD_U64_U32; |
| 836 | |
| 837 | SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1); |
| 838 | SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), |
| 839 | Clamp }; |
| 840 | CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops); |
| 841 | } |
| 842 | |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 843 | bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset, |
| 844 | unsigned OffsetBits) const { |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 845 | if ((OffsetBits == 16 && !isUInt<16>(Offset)) || |
| 846 | (OffsetBits == 8 && !isUInt<8>(Offset))) |
| 847 | return false; |
| 848 | |
Matt Arsenault | 706f930 | 2015-07-06 16:01:58 +0000 | [diff] [blame] | 849 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS || |
| 850 | Subtarget->unsafeDSOffsetFoldingEnabled()) |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 851 | return true; |
| 852 | |
| 853 | // On Southern Islands instruction with a negative base value and an offset |
| 854 | // don't seem to work. |
| 855 | return CurDAG->SignBitIsZero(Base); |
| 856 | } |
| 857 | |
| 858 | bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base, |
| 859 | SDValue &Offset) const { |
Tom Stellard | 92b24f3 | 2016-04-29 14:34:26 +0000 | [diff] [blame] | 860 | SDLoc DL(Addr); |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 861 | if (CurDAG->isBaseWithConstantOffset(Addr)) { |
| 862 | SDValue N0 = Addr.getOperand(0); |
| 863 | SDValue N1 = Addr.getOperand(1); |
| 864 | ConstantSDNode *C1 = cast<ConstantSDNode>(N1); |
| 865 | if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) { |
| 866 | // (add n0, c0) |
| 867 | Base = N0; |
Tom Stellard | 92b24f3 | 2016-04-29 14:34:26 +0000 | [diff] [blame] | 868 | Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 869 | return true; |
| 870 | } |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 871 | } else if (Addr.getOpcode() == ISD::SUB) { |
| 872 | // sub C, x -> add (sub 0, x), C |
| 873 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) { |
| 874 | int64_t ByteOffset = C->getSExtValue(); |
| 875 | if (isUInt<16>(ByteOffset)) { |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 876 | SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 877 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 878 | // XXX - This is kind of hacky. Create a dummy sub node so we can check |
| 879 | // the known bits in isDSOffsetLegal. We need to emit the selected node |
| 880 | // here, so this is thrown away. |
| 881 | SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32, |
| 882 | Zero, Addr.getOperand(1)); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 883 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 884 | if (isDSOffsetLegal(Sub, ByteOffset, 16)) { |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 885 | // FIXME: Select to VOP3 version for with-carry. |
| 886 | unsigned SubOp = Subtarget->hasAddNoCarry() ? |
| 887 | AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; |
| 888 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 889 | MachineSDNode *MachineSub |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 890 | = CurDAG->getMachineNode(SubOp, DL, MVT::i32, |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 891 | Zero, Addr.getOperand(1)); |
| 892 | |
| 893 | Base = SDValue(MachineSub, 0); |
Tom Stellard | 26a2ab7 | 2016-06-10 00:01:04 +0000 | [diff] [blame] | 894 | Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16); |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 895 | return true; |
| 896 | } |
| 897 | } |
| 898 | } |
| 899 | } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) { |
| 900 | // If we have a constant address, prefer to put the constant into the |
| 901 | // offset. This can save moves to load the constant address since multiple |
| 902 | // operations can share the zero base address register, and enables merging |
| 903 | // into read2 / write2 instructions. |
| 904 | |
| 905 | SDLoc DL(Addr); |
| 906 | |
Matt Arsenault | e775f5f | 2014-10-14 17:21:19 +0000 | [diff] [blame] | 907 | if (isUInt<16>(CAddr->getZExtValue())) { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 908 | SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | c8d7920 | 2014-10-15 21:08:59 +0000 | [diff] [blame] | 909 | MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 910 | DL, MVT::i32, Zero); |
Tom Stellard | c8d7920 | 2014-10-15 21:08:59 +0000 | [diff] [blame] | 911 | Base = SDValue(MovZero, 0); |
Tom Stellard | 26a2ab7 | 2016-06-10 00:01:04 +0000 | [diff] [blame] | 912 | Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16); |
Matt Arsenault | e775f5f | 2014-10-14 17:21:19 +0000 | [diff] [blame] | 913 | return true; |
| 914 | } |
| 915 | } |
| 916 | |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 917 | // default case |
| 918 | Base = Addr; |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 919 | Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16); |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 920 | return true; |
| 921 | } |
| 922 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 923 | // TODO: If offset is too big, put low 16-bit into offset. |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 924 | bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, |
| 925 | SDValue &Offset0, |
| 926 | SDValue &Offset1) const { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 927 | SDLoc DL(Addr); |
| 928 | |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 929 | if (CurDAG->isBaseWithConstantOffset(Addr)) { |
| 930 | SDValue N0 = Addr.getOperand(0); |
| 931 | SDValue N1 = Addr.getOperand(1); |
| 932 | ConstantSDNode *C1 = cast<ConstantSDNode>(N1); |
| 933 | unsigned DWordOffset0 = C1->getZExtValue() / 4; |
| 934 | unsigned DWordOffset1 = DWordOffset0 + 1; |
| 935 | // (add n0, c0) |
| 936 | if (isDSOffsetLegal(N0, DWordOffset1, 8)) { |
| 937 | Base = N0; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 938 | Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); |
| 939 | Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 940 | return true; |
| 941 | } |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 942 | } else if (Addr.getOpcode() == ISD::SUB) { |
| 943 | // sub C, x -> add (sub 0, x), C |
| 944 | if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) { |
| 945 | unsigned DWordOffset0 = C->getZExtValue() / 4; |
| 946 | unsigned DWordOffset1 = DWordOffset0 + 1; |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 947 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 948 | if (isUInt<8>(DWordOffset0)) { |
| 949 | SDLoc DL(Addr); |
| 950 | SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); |
| 951 | |
| 952 | // XXX - This is kind of hacky. Create a dummy sub node so we can check |
| 953 | // the known bits in isDSOffsetLegal. We need to emit the selected node |
| 954 | // here, so this is thrown away. |
| 955 | SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32, |
| 956 | Zero, Addr.getOperand(1)); |
| 957 | |
| 958 | if (isDSOffsetLegal(Sub, DWordOffset1, 8)) { |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 959 | unsigned SubOp = Subtarget->hasAddNoCarry() ? |
| 960 | AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; |
| 961 | |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 962 | MachineSDNode *MachineSub |
Matt Arsenault | 84445dd | 2017-11-30 22:51:26 +0000 | [diff] [blame] | 963 | = CurDAG->getMachineNode(SubOp, DL, MVT::i32, |
Matt Arsenault | 966a94f | 2015-09-08 19:34:22 +0000 | [diff] [blame] | 964 | Zero, Addr.getOperand(1)); |
| 965 | |
| 966 | Base = SDValue(MachineSub, 0); |
| 967 | Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); |
| 968 | Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); |
| 969 | return true; |
| 970 | } |
| 971 | } |
| 972 | } |
| 973 | } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) { |
Matt Arsenault | 1a74aff | 2014-10-15 18:06:43 +0000 | [diff] [blame] | 974 | unsigned DWordOffset0 = CAddr->getZExtValue() / 4; |
| 975 | unsigned DWordOffset1 = DWordOffset0 + 1; |
| 976 | assert(4 * DWordOffset0 == CAddr->getZExtValue()); |
| 977 | |
| 978 | if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 979 | SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Matt Arsenault | 1a74aff | 2014-10-15 18:06:43 +0000 | [diff] [blame] | 980 | MachineSDNode *MovZero |
| 981 | = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 982 | DL, MVT::i32, Zero); |
Matt Arsenault | 1a74aff | 2014-10-15 18:06:43 +0000 | [diff] [blame] | 983 | Base = SDValue(MovZero, 0); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 984 | Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); |
| 985 | Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); |
Matt Arsenault | 1a74aff | 2014-10-15 18:06:43 +0000 | [diff] [blame] | 986 | return true; |
| 987 | } |
| 988 | } |
| 989 | |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 990 | // default case |
Matt Arsenault | 0efdd06 | 2016-09-09 22:29:28 +0000 | [diff] [blame] | 991 | |
| 992 | // FIXME: This is broken on SI where we still need to check if the base |
| 993 | // pointer is positive here. |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 994 | Base = Addr; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 995 | Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8); |
| 996 | Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 997 | return true; |
| 998 | } |
| 999 | |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1000 | bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr, |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1001 | SDValue &VAddr, SDValue &SOffset, |
| 1002 | SDValue &Offset, SDValue &Offen, |
| 1003 | SDValue &Idxen, SDValue &Addr64, |
| 1004 | SDValue &GLC, SDValue &SLC, |
| 1005 | SDValue &TFE) const { |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1006 | // Subtarget prefers to use flat instruction |
| 1007 | if (Subtarget->useFlatForGlobal()) |
| 1008 | return false; |
| 1009 | |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1010 | SDLoc DL(Addr); |
| 1011 | |
Jan Vesely | 43b7b5b | 2016-04-07 19:23:11 +0000 | [diff] [blame] | 1012 | if (!GLC.getNode()) |
| 1013 | GLC = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1014 | if (!SLC.getNode()) |
| 1015 | SLC = CurDAG->getTargetConstant(0, DL, MVT::i1); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1016 | TFE = CurDAG->getTargetConstant(0, DL, MVT::i1); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1017 | |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1018 | Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1019 | Offen = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1020 | Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1021 | SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1022 | |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1023 | if (CurDAG->isBaseWithConstantOffset(Addr)) { |
| 1024 | SDValue N0 = Addr.getOperand(0); |
| 1025 | SDValue N1 = Addr.getOperand(1); |
| 1026 | ConstantSDNode *C1 = cast<ConstantSDNode>(N1); |
| 1027 | |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1028 | if (N0.getOpcode() == ISD::ADD) { |
| 1029 | // (add (add N2, N3), C1) -> addr64 |
| 1030 | SDValue N2 = N0.getOperand(0); |
| 1031 | SDValue N3 = N0.getOperand(1); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1032 | Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1); |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1033 | Ptr = N2; |
| 1034 | VAddr = N3; |
| 1035 | } else { |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1036 | // (add N0, C1) -> offset |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1037 | VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1038 | Ptr = N0; |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1039 | } |
| 1040 | |
Marek Olsak | ffadcb7 | 2017-11-09 01:52:17 +0000 | [diff] [blame] | 1041 | if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue())) { |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1042 | Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); |
| 1043 | return true; |
| 1044 | } |
| 1045 | |
| 1046 | if (isUInt<32>(C1->getZExtValue())) { |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1047 | // Illegal offset, store it in soffset. |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1048 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1049 | SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1050 | CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)), |
| 1051 | 0); |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1052 | return true; |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1053 | } |
| 1054 | } |
Tom Stellard | 94b7231 | 2015-02-11 00:34:35 +0000 | [diff] [blame] | 1055 | |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1056 | if (Addr.getOpcode() == ISD::ADD) { |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1057 | // (add N0, N1) -> addr64 |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1058 | SDValue N0 = Addr.getOperand(0); |
| 1059 | SDValue N1 = Addr.getOperand(1); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1060 | Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1061 | Ptr = N0; |
| 1062 | VAddr = N1; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1063 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1064 | return true; |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 1065 | } |
| 1066 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1067 | // default case -> offset |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1068 | VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1069 | Ptr = Addr; |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1070 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1071 | |
| 1072 | return true; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1073 | } |
| 1074 | |
| 1075 | bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 1076 | SDValue &VAddr, SDValue &SOffset, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 1077 | SDValue &Offset, SDValue &GLC, |
| 1078 | SDValue &SLC, SDValue &TFE) const { |
| 1079 | SDValue Ptr, Offen, Idxen, Addr64; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1080 | |
Tom Stellard | 70580f8 | 2015-07-20 14:28:41 +0000 | [diff] [blame] | 1081 | // addr64 bit was removed for volcanic islands. |
| 1082 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) |
| 1083 | return false; |
| 1084 | |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1085 | if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64, |
| 1086 | GLC, SLC, TFE)) |
| 1087 | return false; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1088 | |
| 1089 | ConstantSDNode *C = cast<ConstantSDNode>(Addr64); |
| 1090 | if (C->getSExtValue()) { |
| 1091 | SDLoc DL(Addr); |
Matt Arsenault | 485defe | 2014-11-05 19:01:17 +0000 | [diff] [blame] | 1092 | |
| 1093 | const SITargetLowering& Lowering = |
| 1094 | *static_cast<const SITargetLowering*>(getTargetLowering()); |
| 1095 | |
| 1096 | SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1097 | return true; |
| 1098 | } |
Matt Arsenault | 485defe | 2014-11-05 19:01:17 +0000 | [diff] [blame] | 1099 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1100 | return false; |
| 1101 | } |
| 1102 | |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1103 | bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 1104 | SDValue &VAddr, SDValue &SOffset, |
NAKAMURA Takumi | 0a7d0ad | 2015-09-22 11:15:07 +0000 | [diff] [blame] | 1105 | SDValue &Offset, |
| 1106 | SDValue &SLC) const { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1107 | SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1); |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 1108 | SDValue GLC, TFE; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1109 | |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 1110 | return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE); |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1111 | } |
| 1112 | |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1113 | static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) { |
| 1114 | auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>(); |
| 1115 | return PSV && PSV->isStack(); |
Matt Arsenault | ac0fc84 | 2016-09-17 16:09:55 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1118 | std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const { |
| 1119 | const MachineFunction &MF = CurDAG->getMachineFunction(); |
| 1120 | const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); |
| 1121 | |
| 1122 | if (auto FI = dyn_cast<FrameIndexSDNode>(N)) { |
| 1123 | SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(), |
| 1124 | FI->getValueType(0)); |
| 1125 | |
| 1126 | // If we can resolve this to a frame index access, this is relative to the |
| 1127 | // frame pointer SGPR. |
| 1128 | return std::make_pair(TFI, CurDAG->getRegister(Info->getFrameOffsetReg(), |
| 1129 | MVT::i32)); |
| 1130 | } |
| 1131 | |
| 1132 | // If we don't know this private access is a local stack object, it needs to |
| 1133 | // be relative to the entry point's scratch wave offset register. |
| 1134 | return std::make_pair(N, CurDAG->getRegister(Info->getScratchWaveOffsetReg(), |
| 1135 | MVT::i32)); |
| 1136 | } |
| 1137 | |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 1138 | bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent, |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1139 | SDValue Addr, SDValue &Rsrc, |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1140 | SDValue &VAddr, SDValue &SOffset, |
| 1141 | SDValue &ImmOffset) const { |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1142 | |
| 1143 | SDLoc DL(Addr); |
| 1144 | MachineFunction &MF = CurDAG->getMachineFunction(); |
Matt Arsenault | 0e3d389 | 2015-11-30 21:15:53 +0000 | [diff] [blame] | 1145 | const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1146 | |
Matt Arsenault | 0e3d389 | 2015-11-30 21:15:53 +0000 | [diff] [blame] | 1147 | Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1148 | |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1149 | if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) { |
| 1150 | unsigned Imm = CAddr->getZExtValue(); |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1151 | |
| 1152 | SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32); |
| 1153 | MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, |
| 1154 | DL, MVT::i32, HighBits); |
| 1155 | VAddr = SDValue(MovHighBits, 0); |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1156 | |
| 1157 | // In a call sequence, stores to the argument stack area are relative to the |
| 1158 | // stack pointer. |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 1159 | const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Parent)->getPointerInfo(); |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1160 | unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ? |
| 1161 | Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg(); |
| 1162 | |
| 1163 | SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32); |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1164 | ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16); |
| 1165 | return true; |
| 1166 | } |
| 1167 | |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1168 | if (CurDAG->isBaseWithConstantOffset(Addr)) { |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1169 | // (add n0, c1) |
| 1170 | |
Tom Stellard | 78655fc | 2015-07-16 19:40:09 +0000 | [diff] [blame] | 1171 | SDValue N0 = Addr.getOperand(0); |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1172 | SDValue N1 = Addr.getOperand(1); |
Matt Arsenault | cd09961 | 2016-02-24 04:55:29 +0000 | [diff] [blame] | 1173 | |
Matt Arsenault | caf0ed4 | 2017-11-30 00:52:40 +0000 | [diff] [blame] | 1174 | // Offsets in vaddr must be positive if range checking is enabled. |
Matt Arsenault | 45b9818 | 2017-11-15 00:45:43 +0000 | [diff] [blame] | 1175 | // |
Matt Arsenault | caf0ed4 | 2017-11-30 00:52:40 +0000 | [diff] [blame] | 1176 | // The total computation of vaddr + soffset + offset must not overflow. If |
| 1177 | // vaddr is negative, even if offset is 0 the sgpr offset add will end up |
Matt Arsenault | 45b9818 | 2017-11-15 00:45:43 +0000 | [diff] [blame] | 1178 | // overflowing. |
Matt Arsenault | caf0ed4 | 2017-11-30 00:52:40 +0000 | [diff] [blame] | 1179 | // |
| 1180 | // Prior to gfx9, MUBUF instructions with the vaddr offset enabled would |
| 1181 | // always perform a range check. If a negative vaddr base index was used, |
| 1182 | // this would fail the range check. The overall address computation would |
| 1183 | // compute a valid address, but this doesn't happen due to the range |
| 1184 | // check. For out-of-bounds MUBUF loads, a 0 is returned. |
| 1185 | // |
| 1186 | // Therefore it should be safe to fold any VGPR offset on gfx9 into the |
| 1187 | // MUBUF vaddr, but not on older subtargets which can only do this if the |
| 1188 | // sign bit is known 0. |
Matt Arsenault | cd09961 | 2016-02-24 04:55:29 +0000 | [diff] [blame] | 1189 | ConstantSDNode *C1 = cast<ConstantSDNode>(N1); |
Matt Arsenault | 45b9818 | 2017-11-15 00:45:43 +0000 | [diff] [blame] | 1190 | if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue()) && |
Matt Arsenault | caf0ed4 | 2017-11-30 00:52:40 +0000 | [diff] [blame] | 1191 | (!Subtarget->privateMemoryResourceIsRangeChecked() || |
| 1192 | CurDAG->SignBitIsZero(N0))) { |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1193 | std::tie(VAddr, SOffset) = foldFrameIndex(N0); |
Matt Arsenault | cd09961 | 2016-02-24 04:55:29 +0000 | [diff] [blame] | 1194 | ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); |
| 1195 | return true; |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1196 | } |
| 1197 | } |
| 1198 | |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1199 | // (node) |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1200 | std::tie(VAddr, SOffset) = foldFrameIndex(Addr); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1201 | ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1202 | return true; |
| 1203 | } |
| 1204 | |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 1205 | bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Parent, |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1206 | SDValue Addr, |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1207 | SDValue &SRsrc, |
| 1208 | SDValue &SOffset, |
| 1209 | SDValue &Offset) const { |
| 1210 | ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr); |
Marek Olsak | ffadcb7 | 2017-11-09 01:52:17 +0000 | [diff] [blame] | 1211 | if (!CAddr || !SIInstrInfo::isLegalMUBUFImmOffset(CAddr->getZExtValue())) |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1212 | return false; |
| 1213 | |
| 1214 | SDLoc DL(Addr); |
| 1215 | MachineFunction &MF = CurDAG->getMachineFunction(); |
| 1216 | const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); |
| 1217 | |
| 1218 | SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1219 | |
Matt Arsenault | b81495d | 2017-09-20 05:01:53 +0000 | [diff] [blame] | 1220 | const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Parent)->getPointerInfo(); |
Matt Arsenault | 156d3ae | 2017-05-17 21:02:58 +0000 | [diff] [blame] | 1221 | unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ? |
| 1222 | Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg(); |
| 1223 | |
| 1224 | // FIXME: Get from MachinePointerInfo? We should only be using the frame |
| 1225 | // offset if we know this is in a call sequence. |
| 1226 | SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32); |
| 1227 | |
Matt Arsenault | 0774ea2 | 2017-04-24 19:40:59 +0000 | [diff] [blame] | 1228 | Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16); |
| 1229 | return true; |
| 1230 | } |
| 1231 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1232 | bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, |
| 1233 | SDValue &SOffset, SDValue &Offset, |
| 1234 | SDValue &GLC, SDValue &SLC, |
| 1235 | SDValue &TFE) const { |
| 1236 | SDValue Ptr, VAddr, Offen, Idxen, Addr64; |
Tom Stellard | 794c8c0 | 2014-12-02 17:05:41 +0000 | [diff] [blame] | 1237 | const SIInstrInfo *TII = |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 1238 | static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo()); |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1239 | |
Changpeng Fang | b41574a | 2015-12-22 20:55:23 +0000 | [diff] [blame] | 1240 | if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64, |
| 1241 | GLC, SLC, TFE)) |
| 1242 | return false; |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1243 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1244 | if (!cast<ConstantSDNode>(Offen)->getSExtValue() && |
| 1245 | !cast<ConstantSDNode>(Idxen)->getSExtValue() && |
| 1246 | !cast<ConstantSDNode>(Addr64)->getSExtValue()) { |
Tom Stellard | 794c8c0 | 2014-12-02 17:05:41 +0000 | [diff] [blame] | 1247 | uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1248 | APInt::getAllOnesValue(32).getZExtValue(); // Size |
| 1249 | SDLoc DL(Addr); |
Matt Arsenault | f3cd451 | 2014-11-05 19:01:19 +0000 | [diff] [blame] | 1250 | |
| 1251 | const SITargetLowering& Lowering = |
| 1252 | *static_cast<const SITargetLowering*>(getTargetLowering()); |
| 1253 | |
| 1254 | SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 1255 | return true; |
| 1256 | } |
| 1257 | return false; |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 1258 | } |
| 1259 | |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1260 | bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, |
Jan Vesely | 43b7b5b | 2016-04-07 19:23:11 +0000 | [diff] [blame] | 1261 | SDValue &Soffset, SDValue &Offset |
| 1262 | ) const { |
| 1263 | SDValue GLC, SLC, TFE; |
| 1264 | |
| 1265 | return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE); |
| 1266 | } |
| 1267 | bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1268 | SDValue &Soffset, SDValue &Offset, |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1269 | SDValue &SLC) const { |
| 1270 | SDValue GLC, TFE; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 1271 | |
| 1272 | return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE); |
| 1273 | } |
| 1274 | |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1275 | bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant, |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1276 | SDValue &SOffset, |
| 1277 | SDValue &ImmOffset) const { |
| 1278 | SDLoc DL(Constant); |
Nicolai Haehnle | 312b64f | 2017-10-10 12:22:23 +0000 | [diff] [blame] | 1279 | const uint32_t Align = 4; |
| 1280 | const uint32_t MaxImm = alignDown(4095, Align); |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1281 | uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue(); |
| 1282 | uint32_t Overflow = 0; |
| 1283 | |
Nicolai Haehnle | 312b64f | 2017-10-10 12:22:23 +0000 | [diff] [blame] | 1284 | if (Imm > MaxImm) { |
| 1285 | if (Imm <= MaxImm + 64) { |
| 1286 | // Use an SOffset inline constant for 4..64 |
| 1287 | Overflow = Imm - MaxImm; |
| 1288 | Imm = MaxImm; |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1289 | } else { |
| 1290 | // Try to keep the same value in SOffset for adjacent loads, so that |
| 1291 | // the corresponding register contents can be re-used. |
| 1292 | // |
Nicolai Haehnle | 312b64f | 2017-10-10 12:22:23 +0000 | [diff] [blame] | 1293 | // Load values with all low-bits (except for alignment bits) set into |
| 1294 | // SOffset, so that a larger range of values can be covered using |
| 1295 | // s_movk_i32. |
| 1296 | // |
| 1297 | // Atomic operations fail to work correctly when individual address |
| 1298 | // components are unaligned, even if their sum is aligned. |
| 1299 | uint32_t High = (Imm + Align) & ~4095; |
| 1300 | uint32_t Low = (Imm + Align) & 4095; |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1301 | Imm = Low; |
Nicolai Haehnle | 312b64f | 2017-10-10 12:22:23 +0000 | [diff] [blame] | 1302 | Overflow = High - Align; |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1303 | } |
| 1304 | } |
| 1305 | |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1306 | // There is a hardware bug in SI and CI which prevents address clamping in |
| 1307 | // MUBUF instructions from working correctly with SOffsets. The immediate |
| 1308 | // offset is unaffected. |
| 1309 | if (Overflow > 0 && |
| 1310 | Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS) |
| 1311 | return false; |
| 1312 | |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1313 | ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16); |
| 1314 | |
| 1315 | if (Overflow <= 64) |
| 1316 | SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32); |
| 1317 | else |
| 1318 | SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, |
| 1319 | CurDAG->getTargetConstant(Overflow, DL, MVT::i32)), |
| 1320 | 0); |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1321 | |
| 1322 | return true; |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset, |
| 1326 | SDValue &SOffset, |
| 1327 | SDValue &ImmOffset) const { |
| 1328 | SDLoc DL(Offset); |
| 1329 | |
| 1330 | if (!isa<ConstantSDNode>(Offset)) |
| 1331 | return false; |
| 1332 | |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1333 | return SelectMUBUFConstant(Offset, SOffset, ImmOffset); |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1334 | } |
| 1335 | |
| 1336 | bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset, |
| 1337 | SDValue &SOffset, |
| 1338 | SDValue &ImmOffset, |
| 1339 | SDValue &VOffset) const { |
| 1340 | SDLoc DL(Offset); |
| 1341 | |
| 1342 | // Don't generate an unnecessary voffset for constant offsets. |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1343 | if (isa<ConstantSDNode>(Offset)) { |
| 1344 | SDValue Tmp1, Tmp2; |
| 1345 | |
| 1346 | // When necessary, use a voffset in <= CI anyway to work around a hardware |
| 1347 | // bug. |
| 1348 | if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS || |
| 1349 | SelectMUBUFConstant(Offset, Tmp1, Tmp2)) |
| 1350 | return false; |
| 1351 | } |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1352 | |
| 1353 | if (CurDAG->isBaseWithConstantOffset(Offset)) { |
| 1354 | SDValue N0 = Offset.getOperand(0); |
| 1355 | SDValue N1 = Offset.getOperand(1); |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1356 | if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 && |
| 1357 | SelectMUBUFConstant(N1, SOffset, ImmOffset)) { |
| 1358 | VOffset = N0; |
| 1359 | return true; |
| 1360 | } |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1361 | } |
| 1362 | |
Nicolai Haehnle | a609259 | 2016-06-15 07:13:05 +0000 | [diff] [blame] | 1363 | SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); |
| 1364 | ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); |
| 1365 | VOffset = Offset; |
| 1366 | |
Nicolai Haehnle | 3003ba0 | 2016-03-18 16:24:20 +0000 | [diff] [blame] | 1367 | return true; |
| 1368 | } |
| 1369 | |
Matt Arsenault | 4e309b0 | 2017-07-29 01:03:53 +0000 | [diff] [blame] | 1370 | template <bool IsSigned> |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1371 | bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDValue Addr, |
| 1372 | SDValue &VAddr, |
| 1373 | SDValue &Offset, |
| 1374 | SDValue &SLC) const { |
| 1375 | int64_t OffsetVal = 0; |
| 1376 | |
| 1377 | if (Subtarget->hasFlatInstOffsets() && |
| 1378 | CurDAG->isBaseWithConstantOffset(Addr)) { |
| 1379 | SDValue N0 = Addr.getOperand(0); |
| 1380 | SDValue N1 = Addr.getOperand(1); |
Matt Arsenault | 4e309b0 | 2017-07-29 01:03:53 +0000 | [diff] [blame] | 1381 | int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue(); |
| 1382 | |
| 1383 | if ((IsSigned && isInt<13>(COffsetVal)) || |
| 1384 | (!IsSigned && isUInt<12>(COffsetVal))) { |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1385 | Addr = N0; |
| 1386 | OffsetVal = COffsetVal; |
| 1387 | } |
| 1388 | } |
| 1389 | |
Matt Arsenault | 7757c59 | 2016-06-09 23:42:54 +0000 | [diff] [blame] | 1390 | VAddr = Addr; |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1391 | Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16); |
Matt Arsenault | 47ccafe | 2017-05-11 17:38:33 +0000 | [diff] [blame] | 1392 | SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1); |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1393 | |
Matt Arsenault | 7757c59 | 2016-06-09 23:42:54 +0000 | [diff] [blame] | 1394 | return true; |
| 1395 | } |
| 1396 | |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1397 | bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDValue Addr, |
| 1398 | SDValue &VAddr, |
| 1399 | SDValue &Offset, |
| 1400 | SDValue &SLC) const { |
Matt Arsenault | 4e309b0 | 2017-07-29 01:03:53 +0000 | [diff] [blame] | 1401 | return SelectFlatOffset<false>(Addr, VAddr, Offset, SLC); |
| 1402 | } |
| 1403 | |
| 1404 | bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDValue Addr, |
| 1405 | SDValue &VAddr, |
| 1406 | SDValue &Offset, |
| 1407 | SDValue &SLC) const { |
| 1408 | return SelectFlatOffset<true>(Addr, VAddr, Offset, SLC); |
Matt Arsenault | db7c6a8 | 2017-06-12 16:53:51 +0000 | [diff] [blame] | 1409 | } |
| 1410 | |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1411 | bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, |
| 1412 | SDValue &Offset, bool &Imm) const { |
| 1413 | |
| 1414 | // FIXME: Handle non-constant offsets. |
| 1415 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode); |
| 1416 | if (!C) |
| 1417 | return false; |
| 1418 | |
| 1419 | SDLoc SL(ByteOffsetNode); |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1420 | AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration(); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1421 | int64_t ByteOffset = C->getSExtValue(); |
Tom Stellard | 08efb7e | 2017-01-27 18:41:14 +0000 | [diff] [blame] | 1422 | int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1423 | |
Tom Stellard | 08efb7e | 2017-01-27 18:41:14 +0000 | [diff] [blame] | 1424 | if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) { |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1425 | Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32); |
| 1426 | Imm = true; |
| 1427 | return true; |
| 1428 | } |
| 1429 | |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1430 | if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset)) |
| 1431 | return false; |
| 1432 | |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1433 | if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) { |
| 1434 | // 32-bit Immediates are supported on Sea Islands. |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1435 | Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32); |
| 1436 | } else { |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1437 | SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32); |
| 1438 | Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, |
| 1439 | C32Bit), 0); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1440 | } |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1441 | Imm = false; |
| 1442 | return true; |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1443 | } |
| 1444 | |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 1445 | SDValue AMDGPUDAGToDAGISel::Expand32BitAddress(SDValue Addr) const { |
| 1446 | if (Addr.getValueType() != MVT::i32) |
| 1447 | return Addr; |
| 1448 | |
| 1449 | // Zero-extend a 32-bit address. |
| 1450 | SDLoc SL(Addr); |
| 1451 | |
| 1452 | const MachineFunction &MF = CurDAG->getMachineFunction(); |
| 1453 | const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); |
| 1454 | unsigned AddrHiVal = Info->get32BitAddressHighBits(); |
| 1455 | SDValue AddrHi = CurDAG->getTargetConstant(AddrHiVal, SL, MVT::i32); |
| 1456 | |
| 1457 | const SDValue Ops[] = { |
| 1458 | CurDAG->getTargetConstant(AMDGPU::SReg_64_XEXECRegClassID, SL, MVT::i32), |
| 1459 | Addr, |
| 1460 | CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32), |
| 1461 | SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, AddrHi), |
| 1462 | 0), |
| 1463 | CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32), |
| 1464 | }; |
| 1465 | |
| 1466 | return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64, |
| 1467 | Ops), 0); |
| 1468 | } |
| 1469 | |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1470 | bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, |
| 1471 | SDValue &Offset, bool &Imm) const { |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1472 | SDLoc SL(Addr); |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 1473 | |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1474 | if (CurDAG->isBaseWithConstantOffset(Addr)) { |
| 1475 | SDValue N0 = Addr.getOperand(0); |
| 1476 | SDValue N1 = Addr.getOperand(1); |
| 1477 | |
| 1478 | if (SelectSMRDOffset(N1, Offset, Imm)) { |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 1479 | SBase = Expand32BitAddress(N0); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1480 | return true; |
| 1481 | } |
| 1482 | } |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 1483 | SBase = Expand32BitAddress(Addr); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1484 | Offset = CurDAG->getTargetConstant(0, SL, MVT::i32); |
| 1485 | Imm = true; |
| 1486 | return true; |
| 1487 | } |
| 1488 | |
| 1489 | bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, |
| 1490 | SDValue &Offset) const { |
| 1491 | bool Imm; |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1492 | return SelectSMRD(Addr, SBase, Offset, Imm) && Imm; |
| 1493 | } |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1494 | |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1495 | bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, |
| 1496 | SDValue &Offset) const { |
| 1497 | |
| 1498 | if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS) |
| 1499 | return false; |
| 1500 | |
| 1501 | bool Imm; |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1502 | if (!SelectSMRD(Addr, SBase, Offset, Imm)) |
| 1503 | return false; |
| 1504 | |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1505 | return !Imm && isa<ConstantSDNode>(Offset); |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1506 | } |
| 1507 | |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1508 | bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase, |
| 1509 | SDValue &Offset) const { |
| 1510 | bool Imm; |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1511 | return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm && |
| 1512 | !isa<ConstantSDNode>(Offset); |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1513 | } |
| 1514 | |
| 1515 | bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr, |
| 1516 | SDValue &Offset) const { |
| 1517 | bool Imm; |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1518 | return SelectSMRDOffset(Addr, Offset, Imm) && Imm; |
| 1519 | } |
Tom Stellard | dee26a2 | 2015-08-06 19:28:30 +0000 | [diff] [blame] | 1520 | |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1521 | bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr, |
| 1522 | SDValue &Offset) const { |
| 1523 | if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS) |
| 1524 | return false; |
| 1525 | |
| 1526 | bool Imm; |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1527 | if (!SelectSMRDOffset(Addr, Offset, Imm)) |
| 1528 | return false; |
| 1529 | |
Marek Olsak | 8973a0a | 2017-05-24 14:53:50 +0000 | [diff] [blame] | 1530 | return !Imm && isa<ConstantSDNode>(Offset); |
Tom Stellard | 217361c | 2015-08-06 19:28:38 +0000 | [diff] [blame] | 1531 | } |
| 1532 | |
Nicolai Haehnle | 7968c34 | 2016-07-12 08:12:16 +0000 | [diff] [blame] | 1533 | bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index, |
| 1534 | SDValue &Base, |
| 1535 | SDValue &Offset) const { |
Matt Arsenault | 1322b6f | 2016-07-09 01:13:56 +0000 | [diff] [blame] | 1536 | SDLoc DL(Index); |
| 1537 | |
| 1538 | if (CurDAG->isBaseWithConstantOffset(Index)) { |
| 1539 | SDValue N0 = Index.getOperand(0); |
| 1540 | SDValue N1 = Index.getOperand(1); |
| 1541 | ConstantSDNode *C1 = cast<ConstantSDNode>(N1); |
| 1542 | |
| 1543 | // (add n0, c0) |
| 1544 | Base = N0; |
| 1545 | Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32); |
| 1546 | return true; |
| 1547 | } |
| 1548 | |
Nicolai Haehnle | 7968c34 | 2016-07-12 08:12:16 +0000 | [diff] [blame] | 1549 | if (isa<ConstantSDNode>(Index)) |
| 1550 | return false; |
Matt Arsenault | 1322b6f | 2016-07-09 01:13:56 +0000 | [diff] [blame] | 1551 | |
| 1552 | Base = Index; |
| 1553 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); |
| 1554 | return true; |
| 1555 | } |
| 1556 | |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1557 | SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL, |
| 1558 | SDValue Val, uint32_t Offset, |
| 1559 | uint32_t Width) { |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1560 | // Transformation function, pack the offset and width of a BFE into |
| 1561 | // the format expected by the S_BFE_I32 / S_BFE_U32. In the second |
| 1562 | // source, bits [5:0] contain the offset and bits [22:16] the width. |
| 1563 | uint32_t PackedVal = Offset | (Width << 16); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1564 | SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32); |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1565 | |
| 1566 | return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst); |
| 1567 | } |
| 1568 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1569 | void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) { |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1570 | // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c) |
| 1571 | // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c) |
| 1572 | // Predicate: 0 < b <= c < 32 |
| 1573 | |
| 1574 | const SDValue &Shl = N->getOperand(0); |
| 1575 | ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1)); |
| 1576 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); |
| 1577 | |
| 1578 | if (B && C) { |
| 1579 | uint32_t BVal = B->getZExtValue(); |
| 1580 | uint32_t CVal = C->getZExtValue(); |
| 1581 | |
| 1582 | if (0 < BVal && BVal <= CVal && CVal < 32) { |
| 1583 | bool Signed = N->getOpcode() == ISD::SRA; |
| 1584 | unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32; |
| 1585 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1586 | ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal, |
| 1587 | 32 - CVal)); |
| 1588 | return; |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1589 | } |
| 1590 | } |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1591 | SelectCode(N); |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1592 | } |
| 1593 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1594 | void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) { |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1595 | switch (N->getOpcode()) { |
| 1596 | case ISD::AND: |
| 1597 | if (N->getOperand(0).getOpcode() == ISD::SRL) { |
| 1598 | // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)" |
| 1599 | // Predicate: isMask(mask) |
| 1600 | const SDValue &Srl = N->getOperand(0); |
| 1601 | ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); |
| 1602 | ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1)); |
| 1603 | |
| 1604 | if (Shift && Mask) { |
| 1605 | uint32_t ShiftVal = Shift->getZExtValue(); |
| 1606 | uint32_t MaskVal = Mask->getZExtValue(); |
| 1607 | |
| 1608 | if (isMask_32(MaskVal)) { |
| 1609 | uint32_t WidthVal = countPopulation(MaskVal); |
| 1610 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1611 | ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), |
| 1612 | Srl.getOperand(0), ShiftVal, WidthVal)); |
| 1613 | return; |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1614 | } |
| 1615 | } |
| 1616 | } |
| 1617 | break; |
| 1618 | case ISD::SRL: |
| 1619 | if (N->getOperand(0).getOpcode() == ISD::AND) { |
| 1620 | // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)" |
| 1621 | // Predicate: isMask(mask >> b) |
| 1622 | const SDValue &And = N->getOperand(0); |
| 1623 | ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1)); |
| 1624 | ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1)); |
| 1625 | |
| 1626 | if (Shift && Mask) { |
| 1627 | uint32_t ShiftVal = Shift->getZExtValue(); |
| 1628 | uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; |
| 1629 | |
| 1630 | if (isMask_32(MaskVal)) { |
| 1631 | uint32_t WidthVal = countPopulation(MaskVal); |
| 1632 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1633 | ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), |
| 1634 | And.getOperand(0), ShiftVal, WidthVal)); |
| 1635 | return; |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1636 | } |
| 1637 | } |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1638 | } else if (N->getOperand(0).getOpcode() == ISD::SHL) { |
| 1639 | SelectS_BFEFromShifts(N); |
| 1640 | return; |
| 1641 | } |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1642 | break; |
| 1643 | case ISD::SRA: |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1644 | if (N->getOperand(0).getOpcode() == ISD::SHL) { |
| 1645 | SelectS_BFEFromShifts(N); |
| 1646 | return; |
| 1647 | } |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1648 | break; |
Matt Arsenault | 7e8de01 | 2016-04-22 22:59:16 +0000 | [diff] [blame] | 1649 | |
| 1650 | case ISD::SIGN_EXTEND_INREG: { |
| 1651 | // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8 |
| 1652 | SDValue Src = N->getOperand(0); |
| 1653 | if (Src.getOpcode() != ISD::SRL) |
| 1654 | break; |
| 1655 | |
| 1656 | const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1)); |
| 1657 | if (!Amt) |
| 1658 | break; |
| 1659 | |
| 1660 | unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1661 | ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0), |
| 1662 | Amt->getZExtValue(), Width)); |
| 1663 | return; |
Matt Arsenault | 7e8de01 | 2016-04-22 22:59:16 +0000 | [diff] [blame] | 1664 | } |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1665 | } |
| 1666 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1667 | SelectCode(N); |
Marek Olsak | 9b72868 | 2015-03-24 13:40:27 +0000 | [diff] [blame] | 1668 | } |
| 1669 | |
Matt Arsenault | 7b1dc2c | 2016-09-17 02:02:19 +0000 | [diff] [blame] | 1670 | bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const { |
| 1671 | assert(N->getOpcode() == ISD::BRCOND); |
| 1672 | if (!N->hasOneUse()) |
| 1673 | return false; |
| 1674 | |
| 1675 | SDValue Cond = N->getOperand(1); |
| 1676 | if (Cond.getOpcode() == ISD::CopyToReg) |
| 1677 | Cond = Cond.getOperand(2); |
| 1678 | |
| 1679 | if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse()) |
| 1680 | return false; |
| 1681 | |
| 1682 | MVT VT = Cond.getOperand(0).getSimpleValueType(); |
| 1683 | if (VT == MVT::i32) |
| 1684 | return true; |
| 1685 | |
| 1686 | if (VT == MVT::i64) { |
| 1687 | auto ST = static_cast<const SISubtarget *>(Subtarget); |
| 1688 | |
| 1689 | ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); |
| 1690 | return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64(); |
| 1691 | } |
| 1692 | |
| 1693 | return false; |
| 1694 | } |
| 1695 | |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1696 | void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) { |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 1697 | SDValue Cond = N->getOperand(1); |
| 1698 | |
Matt Arsenault | 327188a | 2016-12-15 21:57:11 +0000 | [diff] [blame] | 1699 | if (Cond.isUndef()) { |
| 1700 | CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other, |
| 1701 | N->getOperand(2), N->getOperand(0)); |
| 1702 | return; |
| 1703 | } |
| 1704 | |
Matt Arsenault | d674e0a | 2017-10-10 20:34:49 +0000 | [diff] [blame] | 1705 | bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N); |
| 1706 | unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ; |
| 1707 | unsigned CondReg = UseSCCBr ? AMDGPU::SCC : AMDGPU::VCC; |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 1708 | SDLoc SL(N); |
| 1709 | |
Tim Renouf | 6eaad1e | 2018-01-09 21:34:43 +0000 | [diff] [blame] | 1710 | if (!UseSCCBr) { |
| 1711 | // This is the case that we are selecting to S_CBRANCH_VCCNZ. We have not |
| 1712 | // analyzed what generates the vcc value, so we do not know whether vcc |
| 1713 | // bits for disabled lanes are 0. Thus we need to mask out bits for |
| 1714 | // disabled lanes. |
| 1715 | // |
| 1716 | // For the case that we select S_CBRANCH_SCC1 and it gets |
| 1717 | // changed to S_CBRANCH_VCCNZ in SIFixSGPRCopies, SIFixSGPRCopies calls |
| 1718 | // SIInstrInfo::moveToVALU which inserts the S_AND). |
| 1719 | // |
| 1720 | // We could add an analysis of what generates the vcc value here and omit |
| 1721 | // the S_AND when is unnecessary. But it would be better to add a separate |
| 1722 | // pass after SIFixSGPRCopies to do the unnecessary S_AND removal, so it |
| 1723 | // catches both cases. |
| 1724 | Cond = SDValue(CurDAG->getMachineNode(AMDGPU::S_AND_B64, SL, MVT::i1, |
| 1725 | CurDAG->getRegister(AMDGPU::EXEC, MVT::i1), |
| 1726 | Cond), |
| 1727 | 0); |
| 1728 | } |
| 1729 | |
Matt Arsenault | d674e0a | 2017-10-10 20:34:49 +0000 | [diff] [blame] | 1730 | SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); |
| 1731 | CurDAG->SelectNodeTo(N, BrOp, MVT::Other, |
Justin Bogner | 95927c0 | 2016-05-12 21:03:32 +0000 | [diff] [blame] | 1732 | N->getOperand(2), // Basic Block |
Matt Arsenault | f530e8b | 2016-11-07 19:09:33 +0000 | [diff] [blame] | 1733 | VCC.getValue(0)); |
Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 1734 | } |
| 1735 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 1736 | void AMDGPUDAGToDAGISel::SelectFMAD(SDNode *N) { |
| 1737 | MVT VT = N->getSimpleValueType(0); |
| 1738 | if (VT != MVT::f32 || !Subtarget->hasMadMixInsts()) { |
| 1739 | SelectCode(N); |
| 1740 | return; |
| 1741 | } |
| 1742 | |
| 1743 | SDValue Src0 = N->getOperand(0); |
| 1744 | SDValue Src1 = N->getOperand(1); |
| 1745 | SDValue Src2 = N->getOperand(2); |
| 1746 | unsigned Src0Mods, Src1Mods, Src2Mods; |
| 1747 | |
| 1748 | // Avoid using v_mad_mix_f32 unless there is actually an operand using the |
| 1749 | // conversion from f16. |
| 1750 | bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods); |
| 1751 | bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods); |
| 1752 | bool Sel2 = SelectVOP3PMadMixModsImpl(Src2, Src2, Src2Mods); |
| 1753 | |
| 1754 | assert(!Subtarget->hasFP32Denormals() && |
| 1755 | "fmad selected with denormals enabled"); |
| 1756 | // TODO: We can select this with f32 denormals enabled if all the sources are |
| 1757 | // converted from f16 (in which case fmad isn't legal). |
| 1758 | |
| 1759 | if (Sel0 || Sel1 || Sel2) { |
| 1760 | // For dummy operands. |
| 1761 | SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32); |
| 1762 | SDValue Ops[] = { |
| 1763 | CurDAG->getTargetConstant(Src0Mods, SDLoc(), MVT::i32), Src0, |
| 1764 | CurDAG->getTargetConstant(Src1Mods, SDLoc(), MVT::i32), Src1, |
| 1765 | CurDAG->getTargetConstant(Src2Mods, SDLoc(), MVT::i32), Src2, |
| 1766 | CurDAG->getTargetConstant(0, SDLoc(), MVT::i1), |
| 1767 | Zero, Zero |
| 1768 | }; |
| 1769 | |
| 1770 | CurDAG->SelectNodeTo(N, AMDGPU::V_MAD_MIX_F32, MVT::f32, Ops); |
| 1771 | } else { |
| 1772 | SelectCode(N); |
| 1773 | } |
| 1774 | } |
| 1775 | |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1776 | // This is here because there isn't a way to use the generated sub0_sub1 as the |
| 1777 | // subreg index to EXTRACT_SUBREG in tablegen. |
| 1778 | void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) { |
| 1779 | MemSDNode *Mem = cast<MemSDNode>(N); |
| 1780 | unsigned AS = Mem->getAddressSpace(); |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 1781 | if (AS == AMDGPUASI.FLAT_ADDRESS) { |
Matt Arsenault | 7757c59 | 2016-06-09 23:42:54 +0000 | [diff] [blame] | 1782 | SelectCode(N); |
| 1783 | return; |
| 1784 | } |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1785 | |
| 1786 | MVT VT = N->getSimpleValueType(0); |
| 1787 | bool Is32 = (VT == MVT::i32); |
| 1788 | SDLoc SL(N); |
| 1789 | |
| 1790 | MachineSDNode *CmpSwap = nullptr; |
| 1791 | if (Subtarget->hasAddr64()) { |
Vitaly Buka | 7450398 | 2017-10-15 05:35:02 +0000 | [diff] [blame] | 1792 | SDValue SRsrc, VAddr, SOffset, Offset, SLC; |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1793 | |
| 1794 | if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) { |
Matt Arsenault | e5456ce | 2017-07-20 21:06:04 +0000 | [diff] [blame] | 1795 | unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN : |
| 1796 | AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN; |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1797 | SDValue CmpVal = Mem->getOperand(2); |
| 1798 | |
| 1799 | // XXX - Do we care about glue operands? |
| 1800 | |
| 1801 | SDValue Ops[] = { |
| 1802 | CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain() |
| 1803 | }; |
| 1804 | |
| 1805 | CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops); |
| 1806 | } |
| 1807 | } |
| 1808 | |
| 1809 | if (!CmpSwap) { |
| 1810 | SDValue SRsrc, SOffset, Offset, SLC; |
| 1811 | if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) { |
Matt Arsenault | e5456ce | 2017-07-20 21:06:04 +0000 | [diff] [blame] | 1812 | unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN : |
| 1813 | AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN; |
Matt Arsenault | 8870181 | 2016-06-09 23:42:48 +0000 | [diff] [blame] | 1814 | |
| 1815 | SDValue CmpVal = Mem->getOperand(2); |
| 1816 | SDValue Ops[] = { |
| 1817 | CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain() |
| 1818 | }; |
| 1819 | |
| 1820 | CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops); |
| 1821 | } |
| 1822 | } |
| 1823 | |
| 1824 | if (!CmpSwap) { |
| 1825 | SelectCode(N); |
| 1826 | return; |
| 1827 | } |
| 1828 | |
| 1829 | MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1); |
| 1830 | *MMOs = Mem->getMemOperand(); |
| 1831 | CmpSwap->setMemRefs(MMOs, MMOs + 1); |
| 1832 | |
| 1833 | unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; |
| 1834 | SDValue Extract |
| 1835 | = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0)); |
| 1836 | |
| 1837 | ReplaceUses(SDValue(N, 0), Extract); |
| 1838 | ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1)); |
| 1839 | CurDAG->RemoveDeadNode(N); |
| 1840 | } |
| 1841 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 1842 | bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src, |
| 1843 | unsigned &Mods) const { |
| 1844 | Mods = 0; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1845 | Src = In; |
| 1846 | |
| 1847 | if (Src.getOpcode() == ISD::FNEG) { |
| 1848 | Mods |= SISrcMods::NEG; |
| 1849 | Src = Src.getOperand(0); |
| 1850 | } |
| 1851 | |
| 1852 | if (Src.getOpcode() == ISD::FABS) { |
| 1853 | Mods |= SISrcMods::ABS; |
| 1854 | Src = Src.getOperand(0); |
| 1855 | } |
| 1856 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1857 | return true; |
| 1858 | } |
| 1859 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 1860 | bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src, |
| 1861 | SDValue &SrcMods) const { |
| 1862 | unsigned Mods; |
| 1863 | if (SelectVOP3ModsImpl(In, Src, Mods)) { |
| 1864 | SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32); |
| 1865 | return true; |
| 1866 | } |
| 1867 | |
| 1868 | return false; |
| 1869 | } |
| 1870 | |
Matt Arsenault | f84e5d9 | 2017-01-31 03:07:46 +0000 | [diff] [blame] | 1871 | bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, |
| 1872 | SDValue &SrcMods) const { |
| 1873 | SelectVOP3Mods(In, Src, SrcMods); |
| 1874 | return isNoNanSrc(Src); |
| 1875 | } |
| 1876 | |
Matt Arsenault | df58e82 | 2017-04-25 21:17:38 +0000 | [diff] [blame] | 1877 | bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const { |
| 1878 | if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) |
| 1879 | return false; |
| 1880 | |
| 1881 | Src = In; |
| 1882 | return true; |
Tom Stellard | db5a11f | 2015-07-13 15:47:57 +0000 | [diff] [blame] | 1883 | } |
| 1884 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1885 | bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src, |
| 1886 | SDValue &SrcMods, SDValue &Clamp, |
| 1887 | SDValue &Omod) const { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1888 | SDLoc DL(In); |
Matt Arsenault | df58e82 | 2017-04-25 21:17:38 +0000 | [diff] [blame] | 1889 | Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1890 | Omod = CurDAG->getTargetConstant(0, DL, MVT::i1); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1891 | |
| 1892 | return SelectVOP3Mods(In, Src, SrcMods); |
| 1893 | } |
| 1894 | |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1895 | bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, |
| 1896 | SDValue &SrcMods, |
| 1897 | SDValue &Clamp, |
| 1898 | SDValue &Omod) const { |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 1899 | Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32); |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1900 | return SelectVOP3Mods(In, Src, SrcMods); |
| 1901 | } |
| 1902 | |
Dmitry Preobrazhensky | c512d44 | 2017-03-27 15:57:17 +0000 | [diff] [blame] | 1903 | bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src, |
| 1904 | SDValue &Clamp, SDValue &Omod) const { |
| 1905 | Src = In; |
| 1906 | |
| 1907 | SDLoc DL(In); |
Matt Arsenault | df58e82 | 2017-04-25 21:17:38 +0000 | [diff] [blame] | 1908 | Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1); |
| 1909 | Omod = CurDAG->getTargetConstant(0, DL, MVT::i1); |
Dmitry Preobrazhensky | c512d44 | 2017-03-27 15:57:17 +0000 | [diff] [blame] | 1910 | |
| 1911 | return true; |
| 1912 | } |
| 1913 | |
Matt Arsenault | 98f2946 | 2017-05-17 20:30:58 +0000 | [diff] [blame] | 1914 | static SDValue stripBitcast(SDValue Val) { |
| 1915 | return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val; |
| 1916 | } |
| 1917 | |
| 1918 | // Figure out if this is really an extract of the high 16-bits of a dword. |
| 1919 | static bool isExtractHiElt(SDValue In, SDValue &Out) { |
| 1920 | In = stripBitcast(In); |
| 1921 | if (In.getOpcode() != ISD::TRUNCATE) |
| 1922 | return false; |
| 1923 | |
| 1924 | SDValue Srl = In.getOperand(0); |
| 1925 | if (Srl.getOpcode() == ISD::SRL) { |
| 1926 | if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { |
| 1927 | if (ShiftAmt->getZExtValue() == 16) { |
| 1928 | Out = stripBitcast(Srl.getOperand(0)); |
| 1929 | return true; |
| 1930 | } |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | return false; |
| 1935 | } |
| 1936 | |
| 1937 | // Look through operations that obscure just looking at the low 16-bits of the |
| 1938 | // same register. |
| 1939 | static SDValue stripExtractLoElt(SDValue In) { |
| 1940 | if (In.getOpcode() == ISD::TRUNCATE) { |
| 1941 | SDValue Src = In.getOperand(0); |
| 1942 | if (Src.getValueType().getSizeInBits() == 32) |
| 1943 | return stripBitcast(Src); |
| 1944 | } |
| 1945 | |
| 1946 | return In; |
| 1947 | } |
| 1948 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 1949 | bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src, |
| 1950 | SDValue &SrcMods) const { |
| 1951 | unsigned Mods = 0; |
| 1952 | Src = In; |
| 1953 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 1954 | if (Src.getOpcode() == ISD::FNEG) { |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1955 | Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI); |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 1956 | Src = Src.getOperand(0); |
| 1957 | } |
| 1958 | |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1959 | if (Src.getOpcode() == ISD::BUILD_VECTOR) { |
| 1960 | unsigned VecMods = Mods; |
| 1961 | |
Matt Arsenault | 98f2946 | 2017-05-17 20:30:58 +0000 | [diff] [blame] | 1962 | SDValue Lo = stripBitcast(Src.getOperand(0)); |
| 1963 | SDValue Hi = stripBitcast(Src.getOperand(1)); |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1964 | |
| 1965 | if (Lo.getOpcode() == ISD::FNEG) { |
Matt Arsenault | 98f2946 | 2017-05-17 20:30:58 +0000 | [diff] [blame] | 1966 | Lo = stripBitcast(Lo.getOperand(0)); |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1967 | Mods ^= SISrcMods::NEG; |
| 1968 | } |
| 1969 | |
| 1970 | if (Hi.getOpcode() == ISD::FNEG) { |
Matt Arsenault | 98f2946 | 2017-05-17 20:30:58 +0000 | [diff] [blame] | 1971 | Hi = stripBitcast(Hi.getOperand(0)); |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1972 | Mods ^= SISrcMods::NEG_HI; |
| 1973 | } |
| 1974 | |
Matt Arsenault | 98f2946 | 2017-05-17 20:30:58 +0000 | [diff] [blame] | 1975 | if (isExtractHiElt(Lo, Lo)) |
| 1976 | Mods |= SISrcMods::OP_SEL_0; |
| 1977 | |
| 1978 | if (isExtractHiElt(Hi, Hi)) |
| 1979 | Mods |= SISrcMods::OP_SEL_1; |
| 1980 | |
| 1981 | Lo = stripExtractLoElt(Lo); |
| 1982 | Hi = stripExtractLoElt(Hi); |
| 1983 | |
Matt Arsenault | 786eeea | 2017-05-17 20:00:00 +0000 | [diff] [blame] | 1984 | if (Lo == Hi && !isInlineImmediate(Lo.getNode())) { |
| 1985 | // Really a scalar input. Just select from the low half of the register to |
| 1986 | // avoid packing. |
| 1987 | |
| 1988 | Src = Lo; |
| 1989 | SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32); |
| 1990 | return true; |
| 1991 | } |
| 1992 | |
| 1993 | Mods = VecMods; |
| 1994 | } |
| 1995 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 1996 | // Packed instructions do not have abs modifiers. |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 1997 | Mods |= SISrcMods::OP_SEL_1; |
| 1998 | |
| 1999 | SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32); |
| 2000 | return true; |
| 2001 | } |
| 2002 | |
| 2003 | bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src, |
| 2004 | SDValue &SrcMods, |
| 2005 | SDValue &Clamp) const { |
| 2006 | SDLoc SL(In); |
| 2007 | |
| 2008 | // FIXME: Handle clamp and op_sel |
| 2009 | Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32); |
| 2010 | |
| 2011 | return SelectVOP3PMods(In, Src, SrcMods); |
| 2012 | } |
| 2013 | |
Dmitry Preobrazhensky | abf2839 | 2017-07-21 13:54:11 +0000 | [diff] [blame] | 2014 | bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src, |
| 2015 | SDValue &SrcMods) const { |
| 2016 | Src = In; |
| 2017 | // FIXME: Handle op_sel |
| 2018 | SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32); |
| 2019 | return true; |
| 2020 | } |
| 2021 | |
| 2022 | bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src, |
| 2023 | SDValue &SrcMods, |
| 2024 | SDValue &Clamp) const { |
| 2025 | SDLoc SL(In); |
| 2026 | |
| 2027 | // FIXME: Handle clamp |
| 2028 | Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32); |
| 2029 | |
| 2030 | return SelectVOP3OpSel(In, Src, SrcMods); |
| 2031 | } |
| 2032 | |
| 2033 | bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src, |
| 2034 | SDValue &SrcMods) const { |
| 2035 | // FIXME: Handle op_sel |
| 2036 | return SelectVOP3Mods(In, Src, SrcMods); |
| 2037 | } |
| 2038 | |
| 2039 | bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src, |
| 2040 | SDValue &SrcMods, |
| 2041 | SDValue &Clamp) const { |
| 2042 | SDLoc SL(In); |
| 2043 | |
| 2044 | // FIXME: Handle clamp |
| 2045 | Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32); |
| 2046 | |
| 2047 | return SelectVOP3OpSelMods(In, Src, SrcMods); |
| 2048 | } |
| 2049 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 2050 | // The return value is not whether the match is possible (which it always is), |
| 2051 | // but whether or not it a conversion is really used. |
| 2052 | bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, |
| 2053 | unsigned &Mods) const { |
| 2054 | Mods = 0; |
| 2055 | SelectVOP3ModsImpl(In, Src, Mods); |
| 2056 | |
| 2057 | if (Src.getOpcode() == ISD::FP_EXTEND) { |
| 2058 | Src = Src.getOperand(0); |
| 2059 | assert(Src.getValueType() == MVT::f16); |
| 2060 | Src = stripBitcast(Src); |
| 2061 | |
Matt Arsenault | 550c66d | 2017-10-13 20:45:49 +0000 | [diff] [blame] | 2062 | // Be careful about folding modifiers if we already have an abs. fneg is |
| 2063 | // applied last, so we don't want to apply an earlier fneg. |
| 2064 | if ((Mods & SISrcMods::ABS) == 0) { |
| 2065 | unsigned ModsTmp; |
| 2066 | SelectVOP3ModsImpl(Src, Src, ModsTmp); |
| 2067 | |
| 2068 | if ((ModsTmp & SISrcMods::NEG) != 0) |
| 2069 | Mods ^= SISrcMods::NEG; |
| 2070 | |
| 2071 | if ((ModsTmp & SISrcMods::ABS) != 0) |
| 2072 | Mods |= SISrcMods::ABS; |
| 2073 | } |
| 2074 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 2075 | // op_sel/op_sel_hi decide the source type and source. |
| 2076 | // If the source's op_sel_hi is set, it indicates to do a conversion from fp16. |
| 2077 | // If the sources's op_sel is set, it picks the high half of the source |
| 2078 | // register. |
| 2079 | |
| 2080 | Mods |= SISrcMods::OP_SEL_1; |
Matt Arsenault | 550c66d | 2017-10-13 20:45:49 +0000 | [diff] [blame] | 2081 | if (isExtractHiElt(Src, Src)) { |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 2082 | Mods |= SISrcMods::OP_SEL_0; |
| 2083 | |
Matt Arsenault | 550c66d | 2017-10-13 20:45:49 +0000 | [diff] [blame] | 2084 | // TODO: Should we try to look for neg/abs here? |
| 2085 | } |
| 2086 | |
Matt Arsenault | d7e2303 | 2017-09-07 18:05:07 +0000 | [diff] [blame] | 2087 | return true; |
| 2088 | } |
| 2089 | |
| 2090 | return false; |
| 2091 | } |
| 2092 | |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 2093 | bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src, |
| 2094 | SDValue &SrcMods) const { |
| 2095 | unsigned Mods = 0; |
| 2096 | SelectVOP3PMadMixModsImpl(In, Src, Mods); |
| 2097 | SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32); |
| 2098 | return true; |
| 2099 | } |
| 2100 | |
Matt Arsenault | e1cd482 | 2017-11-13 00:22:09 +0000 | [diff] [blame] | 2101 | // TODO: Can we identify things like v_mad_mixhi_f16? |
| 2102 | bool AMDGPUDAGToDAGISel::SelectHi16Elt(SDValue In, SDValue &Src) const { |
| 2103 | if (In.isUndef()) { |
| 2104 | Src = In; |
| 2105 | return true; |
| 2106 | } |
| 2107 | |
| 2108 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) { |
| 2109 | SDLoc SL(In); |
| 2110 | SDValue K = CurDAG->getTargetConstant(C->getZExtValue() << 16, SL, MVT::i32); |
| 2111 | MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, |
| 2112 | SL, MVT::i32, K); |
| 2113 | Src = SDValue(MovK, 0); |
| 2114 | return true; |
| 2115 | } |
| 2116 | |
| 2117 | if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(In)) { |
| 2118 | SDLoc SL(In); |
| 2119 | SDValue K = CurDAG->getTargetConstant( |
| 2120 | C->getValueAPF().bitcastToAPInt().getZExtValue() << 16, SL, MVT::i32); |
| 2121 | MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, |
| 2122 | SL, MVT::i32, K); |
| 2123 | Src = SDValue(MovK, 0); |
| 2124 | return true; |
| 2125 | } |
| 2126 | |
| 2127 | return isExtractHiElt(In, Src); |
| 2128 | } |
| 2129 | |
Christian Konig | d910b7d | 2013-02-26 17:52:16 +0000 | [diff] [blame] | 2130 | void AMDGPUDAGToDAGISel::PostprocessISelDAG() { |
Bill Wendling | a3cd350 | 2013-06-19 21:36:55 +0000 | [diff] [blame] | 2131 | const AMDGPUTargetLowering& Lowering = |
Matt Arsenault | 209a7b9 | 2014-04-18 07:40:20 +0000 | [diff] [blame] | 2132 | *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2133 | bool IsModified = false; |
| 2134 | do { |
| 2135 | IsModified = false; |
Matt Arsenault | 68f0505 | 2017-12-04 22:18:27 +0000 | [diff] [blame] | 2136 | |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2137 | // Go over all selected nodes and try to fold them a bit more |
Matt Arsenault | 68f0505 | 2017-12-04 22:18:27 +0000 | [diff] [blame] | 2138 | SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin(); |
| 2139 | while (Position != CurDAG->allnodes_end()) { |
| 2140 | SDNode *Node = &*Position++; |
| 2141 | MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(Node); |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2142 | if (!MachineNode) |
| 2143 | continue; |
Christian Konig | d910b7d | 2013-02-26 17:52:16 +0000 | [diff] [blame] | 2144 | |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2145 | SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); |
Matt Arsenault | 68f0505 | 2017-12-04 22:18:27 +0000 | [diff] [blame] | 2146 | if (ResNode != Node) { |
| 2147 | if (ResNode) |
| 2148 | ReplaceUses(Node, ResNode); |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2149 | IsModified = true; |
| 2150 | } |
Tom Stellard | 2183b70 | 2013-06-03 17:39:46 +0000 | [diff] [blame] | 2151 | } |
Vincent Lejeune | ab3baf8 | 2013-09-12 23:44:44 +0000 | [diff] [blame] | 2152 | CurDAG->RemoveDeadNodes(); |
| 2153 | } while (IsModified); |
Christian Konig | d910b7d | 2013-02-26 17:52:16 +0000 | [diff] [blame] | 2154 | } |
Tom Stellard | 2028769 | 2017-08-08 04:57:55 +0000 | [diff] [blame] | 2155 | |
| 2156 | void R600DAGToDAGISel::Select(SDNode *N) { |
| 2157 | unsigned int Opc = N->getOpcode(); |
| 2158 | if (N->isMachineOpcode()) { |
| 2159 | N->setNodeId(-1); |
| 2160 | return; // Already selected. |
| 2161 | } |
| 2162 | |
| 2163 | switch (Opc) { |
| 2164 | default: break; |
| 2165 | case AMDGPUISD::BUILD_VERTICAL_VECTOR: |
| 2166 | case ISD::SCALAR_TO_VECTOR: |
| 2167 | case ISD::BUILD_VECTOR: { |
| 2168 | EVT VT = N->getValueType(0); |
| 2169 | unsigned NumVectorElts = VT.getVectorNumElements(); |
| 2170 | unsigned RegClassID; |
| 2171 | // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG |
| 2172 | // that adds a 128 bits reg copy when going through TwoAddressInstructions |
| 2173 | // pass. We want to avoid 128 bits copies as much as possible because they |
| 2174 | // can't be bundled by our scheduler. |
| 2175 | switch(NumVectorElts) { |
| 2176 | case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break; |
| 2177 | case 4: |
| 2178 | if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR) |
| 2179 | RegClassID = AMDGPU::R600_Reg128VerticalRegClassID; |
| 2180 | else |
| 2181 | RegClassID = AMDGPU::R600_Reg128RegClassID; |
| 2182 | break; |
| 2183 | default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR"); |
| 2184 | } |
| 2185 | SelectBuildVector(N, RegClassID); |
| 2186 | return; |
| 2187 | } |
| 2188 | } |
| 2189 | |
| 2190 | SelectCode(N); |
| 2191 | } |
| 2192 | |
| 2193 | bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, |
| 2194 | SDValue &Offset) { |
| 2195 | ConstantSDNode *C; |
| 2196 | SDLoc DL(Addr); |
| 2197 | |
| 2198 | if ((C = dyn_cast<ConstantSDNode>(Addr))) { |
| 2199 | Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32); |
| 2200 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
| 2201 | } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) && |
| 2202 | (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) { |
| 2203 | Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32); |
| 2204 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
| 2205 | } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) && |
| 2206 | (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) { |
| 2207 | Base = Addr.getOperand(0); |
| 2208 | Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); |
| 2209 | } else { |
| 2210 | Base = Addr; |
| 2211 | Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); |
| 2212 | } |
| 2213 | |
| 2214 | return true; |
| 2215 | } |
| 2216 | |
| 2217 | bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, |
| 2218 | SDValue &Offset) { |
| 2219 | ConstantSDNode *IMMOffset; |
| 2220 | |
| 2221 | if (Addr.getOpcode() == ISD::ADD |
| 2222 | && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) |
| 2223 | && isInt<16>(IMMOffset->getZExtValue())) { |
| 2224 | |
| 2225 | Base = Addr.getOperand(0); |
| 2226 | Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr), |
| 2227 | MVT::i32); |
| 2228 | return true; |
| 2229 | // If the pointer address is constant, we can move it to the offset field. |
| 2230 | } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr)) |
| 2231 | && isInt<16>(IMMOffset->getZExtValue())) { |
| 2232 | Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), |
| 2233 | SDLoc(CurDAG->getEntryNode()), |
| 2234 | AMDGPU::ZERO, MVT::i32); |
| 2235 | Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr), |
| 2236 | MVT::i32); |
| 2237 | return true; |
| 2238 | } |
| 2239 | |
| 2240 | // Default case, no offset |
| 2241 | Base = Addr; |
| 2242 | Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); |
| 2243 | return true; |
| 2244 | } |