Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	10	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	11	#include "MCTargetDesc/ARMAddressingModes.h"
				12	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
				15	#include "llvm/MC/MCExpr.h"
				16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	21	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	22	#include "llvm/Support/LEB128.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	23	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	24	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	25	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	26
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	27	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	28
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	29	#define DEBUG_TYPE "arm-disassembler"
				30
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	31	typedef MCDisassembler::DecodeStatus DecodeStatus;
				32
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	33	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	34	// Handles the condition code status of instructions in IT blocks
				35	class ITStatus
				36	{
				37	public:
				38	// Returns the condition code for instruction in IT block
				39	unsigned getITCC() {
				40	unsigned CC = ARMCC::AL;
				41	if (instrInITBlock())
				42	CC = ITStates.back();
				43	return CC;
				44	}
				45
				46	// Advances the IT block state to the next T or E
				47	void advanceITState() {
				48	ITStates.pop_back();
				49	}
				50
				51	// Returns true if the current instruction is in an IT block
				52	bool instrInITBlock() {
				53	return !ITStates.empty();
				54	}
				55
				56	// Returns true if current instruction is the last instruction in an IT block
				57	bool instrLastInITBlock() {
				58	return ITStates.size() == 1;
				59	}
				60
				61	// Called when decoding an IT instruction. Sets the IT state for the following
				62	// instructions that for the IT block. Firstcond and Mask correspond to the
				63	// fields in the IT instruction encoding.
				64	void setITState(char Firstcond, char Mask) {
				65	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	66	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	67	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	68	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				69	assert(NumTZ <= 3 && "Invalid IT mask!");
				70	// push condition codes onto the stack the correct order for the pops
				71	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				72	bool T = ((Mask >> Pos) & 1) == CondBit0;
				73	if (T)
				74	ITStates.push_back(CCBits);
				75	else
				76	ITStates.push_back(CCBits ^ 1);
				77	}
				78	ITStates.push_back(CCBits);
				79	}
				80
				81	private:
				82	std::vector<unsigned char> ITStates;
				83	};
				84	}
				85
				86	namespace {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	87	/// ARM disassembler for all ARM platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	class ARMDisassembler : public MCDisassembler {
				89	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	90	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				91	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	92	}
				93
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	94	~ARMDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	96	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	97	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	98	raw_ostream &VStream,
				99	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	100	};
				101
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	102	/// Thumb disassembler for all Thumb platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	103	class ThumbDisassembler : public MCDisassembler {
				104	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	105	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				106	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	}
				108
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	109	~ThumbDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	110
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	111	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	112	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	113	raw_ostream &VStream,
				114	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	115
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	117	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	118	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	119	void UpdateThumbVFPPredicate(MCInst&) const;
				120	};
				121	}
				122
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	123	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	124	switch (In) {
				125	case MCDisassembler::Success:
				126	// Out stays the same.
				127	return true;
				128	case MCDisassembler::SoftFail:
				129	Out = In;
				130	return true;
				131	case MCDisassembler::Fail:
				132	Out = In;
				133	return false;
				134	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	135	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	136	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	137
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	138
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	139	// Forward declare these because the autogenerated code will reference them.
				140	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	141	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	142	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	143	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	144	unsigned RegNo, uint64_t Address,
				145	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	146	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				147	unsigned RegNo, uint64_t Address,
				148	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	149	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	150	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	151	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	153	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	154	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	155	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				156	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	157	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	158	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	159	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	160	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo,
				165	uint64_t Address,
				166	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	167	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	169	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	171	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	172	unsigned RegNo, uint64_t Address,
				173	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	174
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	175	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	177	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	179	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	181	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	183	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	191	unsigned Insn,
				192	uint64_t Address,
				193	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
				202
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Adddress,
				206	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	215	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				216	uint64_t Address, const void *Decoder);
				217	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				218	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	219	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	221	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	223	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	225	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	227	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				228	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	229	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	231	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	233	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				234	uint64_t Address, const void *Decoder);
				235	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				236	uint64_t Address, const void *Decoder);
				237	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				238	uint64_t Address, const void *Decoder);
				239	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				240	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	241	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	243	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	245	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	247	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	249	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	250	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	251	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	252	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	253	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	254	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	255	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	256	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	257	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	258	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	259	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	260	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	261	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	262	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	263	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	264	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	265	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	266	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	267	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	268	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	269	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	270	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	271	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	272	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	273	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				274	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	275	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	276	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	277	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				278	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	279	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	280	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	281	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	282	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	283	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	284	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	285	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	286	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	287	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	288	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	289	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	290	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	291	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	292	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	293	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	294	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	295	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	296	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	297	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	298	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	299	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	300	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	301	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	302	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	303	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	304	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	305	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	306	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	307	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	308	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	309	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	310	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	311	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	312	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	313	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	314	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	315	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	316	uint64_t Address, const void *Decoder);
				317
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	318
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	319	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	320	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	321	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	322	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	323	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	324	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	325	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	326	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	327	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	328	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	329	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	330	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	331	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	332	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	333	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	334	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	335	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	336	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	337	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	338	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	339	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				340	uint64_t Address, const void* Decoder);
				341	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				342	uint64_t Address, const void* Decoder);
				343	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				344	uint64_t Address, const void* Decoder);
				345	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				346	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	347	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	348	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	349	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	350	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	351	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	352	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	353	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	354	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	355	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	356	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	357	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	358	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	359	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	360	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	361	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	362	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	363	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				364	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	365	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	366	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	367	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	368	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	369	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	370	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	371	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	372	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	373	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	374	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	375	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	376	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	377	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	378	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	379	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	380	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	381	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	382	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	385	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	386	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	387	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	388	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	389	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	390	uint64_t Address, const void *Decoder);
				391
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	394	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				395	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	396	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	397
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	398	static MCDisassembler *createARMDisassembler(const Target &T,
				399	const MCSubtargetInfo &STI,
				400	MCContext &Ctx) {
				401	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	402	}
				403
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	404	static MCDisassembler *createThumbDisassembler(const Target &T,
				405	const MCSubtargetInfo &STI,
				406	MCContext &Ctx) {
				407	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	408	}
				409
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	410	// Post-decoding checks
				411	static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
				412	uint64_t Address, raw_ostream &OS,
				413	raw_ostream &CS,
				414	uint32_t Insn,
				415	DecodeStatus Result)
				416	{
				417	switch (MI.getOpcode()) {
				418	case ARM::HVC: {
				419	// HVC is undefined if condition = 0xf otherwise upredictable
				420	// if condition != 0xe
				421	uint32_t Cond = (Insn >> 28) & 0xF;
				422	if (Cond == 0xF)
				423	return MCDisassembler::Fail;
				424	if (Cond != 0xE)
				425	return MCDisassembler::SoftFail;
				426	return Result;
				427	}
				428	default: return Result;
				429	}
				430	}
				431
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	432	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	433	ArrayRef<uint8_t> Bytes,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	434	uint64_t Address, raw_ostream &OS,
				435	raw_ostream &CS) const {
				436	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	437
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	438	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	439	"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
				440	"mode!");
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	441
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	442	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	443	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	444	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	445	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	446	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447
				448	// Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	449	uint32_t Insn =
				450	(Bytes[3] << 24) \| (Bytes[2] << 16) \| (Bytes[1] << 8) \| (Bytes[0] << 0);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	451
				452	// Calling the auto-generated decoder function.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	453	DecodeStatus Result =
				454	decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
				455	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	456	Size = 4;
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	457	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	458	}
				459
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	460	// VFP and NEON instructions, similarly, are shared between ARM
				461	// and Thumb modes.
				462	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	463	Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
				464	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	465	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	466	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	467	}
				468
				469	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	470	Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
				471	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	472	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	473	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	474	}
				475
				476	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	477	Result =
				478	decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
				479	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	480	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	481	// Add a fake predicate operand, because we share these instruction
				482	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	483	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				484	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	485	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	486	}
				487
				488	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	489	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	491	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	492	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	// Add a fake predicate operand, because we share these instruction
				494	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	495	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				496	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	497	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	498	}
				499
				500	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	501	Result =
				502	decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
				503	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	504	Size = 4;
				505	// Add a fake predicate operand, because we share these instruction
				506	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	507	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				508	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	509	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	510	}
				511
				512	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	513	Result =
				514	decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
				515	if (Result != MCDisassembler::Fail) {
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	516	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	517	return Result;
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	518	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	519
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	520	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	521	Result =
				522	decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
				523	if (Result != MCDisassembler::Fail) {
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	524	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	525	return Result;
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	526	}
				527
				528	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	529	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	530	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	531	}
				532
				533	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	534	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	535	}
				536
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	537	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				538	/// immediate Value in the MCInst. The immediate Value has had any PC
				539	/// adjustment made by the caller. If the instruction is a branch instruction
				540	/// then isBranch is true, else false. If the getOpInfo() function was set as
				541	/// part of the setupForSymbolicDisassembly() call then that function is called
				542	/// to get any symbolic information at the Address for this instruction. If
				543	/// that returns non-zero then the symbolic information it returns is used to
				544	/// create an MCExpr and that is added as an operand to the MCInst. If
				545	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				546	/// Value is done and if a symbol is found an MCExpr is created with that, else
				547	/// an MCExpr with Value is created. This function returns true if it adds an
				548	/// operand to the MCInst and false otherwise.
				549	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				550	bool isBranch, uint64_t InstSize,
				551	MCInst &MI, const void *Decoder) {
				552	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	553	// FIXME: Does it make sense for value to be negative?
				554	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				555	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	556	}
				557
				558	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				559	/// referenced by a load instruction with the base register that is the Pc.
				560	/// These can often be values in a literal pool near the Address of the
				561	/// instruction. The Address of the instruction and its immediate Value are
				562	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	563	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	564	/// the referenced address is that of a symbol. Or it will return a pointer to
				565	/// a literal 'C' string if the referenced address of the literal pool's entry
				566	/// is an address into a section with 'C' string literals.
				567	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	568	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	569	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	570	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	571	}
				572
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	573	// Thumb1 instructions don't have explicit S bits. Rather, they
				574	// implicitly set CPSR. Since it's not represented in the encoding, the
				575	// auto-generated decoder won't inject the CPSR operand. We need to fix
				576	// that as a post-pass.
				577	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				578	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	579	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	580	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	581	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				582	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	583	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	584	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	585	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	586	return;
				587	}
				588	}
				589
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	590	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	591	}
				592
				593	// Most Thumb instructions don't have explicit predicates in the
				594	// encoding, but rather get their predicates from IT context. We need
				595	// to fix up the predicate operands using this context information as a
				596	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	597	MCDisassembler::DecodeStatus
				598	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	599	MCDisassembler::DecodeStatus S = Success;
				600
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	601	// A few instructions actually have predicates encoded in them. Don't
				602	// try to overwrite it if we're seeing one of those.
				603	switch (MI.getOpcode()) {
				604	case ARM::tBcc:
				605	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	606	case ARM::tCBZ:
				607	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	608	case ARM::tCPS:
				609	case ARM::t2CPS3p:
				610	case ARM::t2CPS2p:
				611	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	612	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	613	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	614	// Some instructions (mostly conditional branches) are not
				615	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	616	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	617	S = SoftFail;
				618	else
				619	return Success;
				620	break;
				621	case ARM::tB:
				622	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	623	case ARM::t2TBB:
				624	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	625	// Some instructions (mostly unconditional branches) can
				626	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	627	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	628	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	629	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	630	default:
				631	break;
				632	}
				633
				634	// If we're in an IT block, base the predicate on that. Otherwise,
				635	// assume a predicate of AL.
				636	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	637	CC = ITBlock.getITCC();
				638	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	639	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	640	if (ITBlock.instrInITBlock())
				641	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	642
				643	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	644	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	645	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	646	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				647	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	648	if (OpInfo[i].isPredicate()) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	649	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	++I;
				651	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	652	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	653	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	654	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	655	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	656	}
				657	}
				658
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	659	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	660	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	661	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	662	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	663	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	664	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	665
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	666	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	667	}
				668
				669	// Thumb VFP instructions are a special case. Because we share their
				670	// encodings between ARM and Thumb modes, and they are predicable in ARM
				671	// mode, the auto-generated decoder will give them an (incorrect)
				672	// predicate operand. We need to rewrite these operands based on the IT
				673	// context as a post-pass.
				674	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				675	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	676	CC = ITBlock.getITCC();
				677	if (ITBlock.instrInITBlock())
				678	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	679
				680	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				681	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	682	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				683	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	684	if (OpInfo[i].isPredicate() ) {
				685	I->setImm(CC);
				686	++I;
				687	if (CC == ARMCC::AL)
				688	I->setReg(0);
				689	else
				690	I->setReg(ARM::CPSR);
				691	return;
				692	}
				693	}
				694	}
				695
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	696	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	697	ArrayRef<uint8_t> Bytes,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	698	uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	699	raw_ostream &OS,
				700	raw_ostream &CS) const {
				701	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	702
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	703	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	704	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				705
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	706	// We want to read exactly 2 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	707	if (Bytes.size() < 2) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	708	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	709	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	710	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	711
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	712	uint16_t Insn16 = (Bytes[1] << 8) \| Bytes[0];
				713	DecodeStatus Result =
				714	decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
				715	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	716	Size = 2;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	717	Check(Result, AddThumbPredicate(MI));
				718	return Result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	719	}
				720
				721	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	722	Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
				723	STI);
				724	if (Result) {
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	725	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	726	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	727	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	728	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	729	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	730	}
				731
				732	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	733	Result =
				734	decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
				735	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	737
				738	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				739	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	740	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	741	Result = MCDisassembler::SoftFail;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	742
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	743	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	744
				745	// If we find an IT instruction, we need to parse its condition
				746	// code and mask operands so that we can apply them correctly
				747	// to the subsequent instructions.
				748	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	749
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	750	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	751	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	752	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	753	}
				754
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	755	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	756	}
				757
				758	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	759	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	760	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	761	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	762	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	763
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	764	uint32_t Insn32 =
				765	(Bytes[3] << 8) \| (Bytes[2] << 0) \| (Bytes[1] << 24) \| (Bytes[0] << 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	767	Result =
				768	decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
				769	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	770	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	771	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	772	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	773	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	774	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	775	}
				776
				777	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	778	Result =
				779	decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
				780	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	781	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	782	Check(Result, AddThumbPredicate(MI));
				783	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	784	}
				785
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	786	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	787	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	788	Result =
				789	decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
				790	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	791	Size = 4;
				792	UpdateThumbVFPPredicate(MI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	793	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	794	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	795	}
				796
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	797	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	798	Result =
				799	decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
				800	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	801	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	802	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	803	}
				804
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	805	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	806	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	807	Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
				808	STI);
				809	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	810	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	811	Check(Result, AddThumbPredicate(MI));
				812	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	813	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	814	}
				815
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	816	if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	817	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	818	uint32_t NEONLdStInsn = Insn32;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	819	NEONLdStInsn &= 0xF0FFFFFF;
				820	NEONLdStInsn \|= 0x04000000;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	821	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	822	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	823	if (Result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	824	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	825	Check(Result, AddThumbPredicate(MI));
				826	return Result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	827	}
				828	}
				829
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	830	if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	831	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	832	uint32_t NEONDataInsn = Insn32;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	833	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				834	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				835	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	836	Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	837	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	838	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	839	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	840	Check(Result, AddThumbPredicate(MI));
				841	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	842	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	843
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	844	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	845	uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	846	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				847	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				848	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	849	Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	850	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	851	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	852	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	853	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	854	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	855
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	856	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	857	uint32_t NEONv8Insn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	858	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	859	Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	860	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	861	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	862	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	863	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	864	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	865	}
				866
				867	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	868	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	870	}
				871
				872
				873	extern "C" void LLVMInitializeARMDisassembler() {
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	874	TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	875	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	876	TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	877	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	878	TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	879	createThumbDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	880	TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	881	createThumbDisassembler);
				882	}
				883
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	884	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	885	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				886	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				887	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				888	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				889	};
				890
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	891	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	892	uint64_t Address, const void *Decoder) {
				893	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	894	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	895
				896	unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	897	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	898	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	899	}
				900
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	901	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	902	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	903	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	904	DecodeStatus S = MCDisassembler::Success;
				905
				906	if (RegNo == 15)
				907	S = MCDisassembler::SoftFail;
				908
				909	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				910
				911	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	912	}
				913
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	914	static DecodeStatus
				915	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				916	uint64_t Address, const void *Decoder) {
				917	DecodeStatus S = MCDisassembler::Success;
				918
				919	if (RegNo == 15)
				920	{
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	921	Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	922	return MCDisassembler::Success;
				923	}
				924
				925	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				926	return S;
				927	}
				928
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	929	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	930	uint64_t Address, const void *Decoder) {
				931	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	932	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	933	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				934	}
				935
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	936	static const uint16_t GPRPairDecoderTable[] = {
				937	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				938	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				939	};
				940
				941	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				942	uint64_t Address, const void *Decoder) {
				943	DecodeStatus S = MCDisassembler::Success;
				944
				945	if (RegNo > 13)
				946	return MCDisassembler::Fail;
				947
				948	if ((RegNo & 1) \|\| RegNo == 0xe)
				949	S = MCDisassembler::SoftFail;
				950
				951	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	952	Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	953	return S;
				954	}
				955
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	956	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	957	uint64_t Address, const void *Decoder) {
				958	unsigned Register = 0;
				959	switch (RegNo) {
				960	case 0:
				961	Register = ARM::R0;
				962	break;
				963	case 1:
				964	Register = ARM::R1;
				965	break;
				966	case 2:
				967	Register = ARM::R2;
				968	break;
				969	case 3:
				970	Register = ARM::R3;
				971	break;
				972	case 9:
				973	Register = ARM::R9;
				974	break;
				975	case 12:
				976	Register = ARM::R12;
				977	break;
				978	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	979	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	982	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	983	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	984	}
				985
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	986	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	987	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	988	DecodeStatus S = MCDisassembler::Success;
				989	if (RegNo == 13 \|\| RegNo == 15)
				990	S = MCDisassembler::SoftFail;
				991	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				992	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	993	}
				994
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	995	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	996	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				997	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				998	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				999	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				1000	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				1001	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				1002	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				1003	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				1004	};
				1005
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1006	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1007	uint64_t Address, const void *Decoder) {
				1008	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1009	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1010
				1011	unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1012	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1013	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1014	}
				1015
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1016	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1017	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1018	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1019	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1020	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1021	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1022	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1023	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1024	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1025	};
				1026
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1027	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1028	uint64_t Address, const void *Decoder) {
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	1029	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				1030	.getFeatureBits();
				1031	bool hasD16 = featureBits & ARM::FeatureD16;
Oliver Stannard	9e89d8c	2014-11-05 12:06:39 +0000	[diff] [blame]	1032
				1033	if (RegNo > 31 \|\| (hasD16 && RegNo > 15))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1034	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1035
				1036	unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1037	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1038	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1039	}
				1040
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1041	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1042	uint64_t Address, const void *Decoder) {
				1043	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1044	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1045	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1046	}
				1047
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1048	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1049	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1050	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1051	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1052	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1053	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1054	}
				1055
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1056	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1057	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1058	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1059	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1060	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1061	};
				1062
				1063
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1064	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1065	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1066	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1067	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1068	RegNo >>= 1;
				1069
				1070	unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1071	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1072	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1073	}
				1074
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1075	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1076	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1077	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1078	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1079	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1080	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1081	ARM::Q15
				1082	};
				1083
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1084	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1085	uint64_t Address, const void *Decoder) {
				1086	if (RegNo > 30)
				1087	return MCDisassembler::Fail;
				1088
				1089	unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1090	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1091	return MCDisassembler::Success;
				1092	}
				1093
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1094	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1095	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1096	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1097	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1098	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1099	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1100	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1101	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1102	ARM::D28_D30, ARM::D29_D31
				1103	};
				1104
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1105	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1106	unsigned RegNo,
				1107	uint64_t Address,
				1108	const void *Decoder) {
				1109	if (RegNo > 29)
				1110	return MCDisassembler::Fail;
				1111
				1112	unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1113	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1114	return MCDisassembler::Success;
				1115	}
				1116
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1117	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1118	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1119	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1120	// AL predicate is not allowed on Thumb1 branches.
				1121	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1122	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1123	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1124	if (Val == ARMCC::AL) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1125	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1126	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1127	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1128	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1129	}
				1130
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1131	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1132	uint64_t Address, const void *Decoder) {
				1133	if (Val)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1134	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1135	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1136	Inst.addOperand(MCOperand::createReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1137	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1138	}
				1139
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1140	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1141	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1142	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1143
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1144	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1145	unsigned type = fieldFromInstruction(Val, 5, 2);
				1146	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1147
				1148	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1149	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1150	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1151
				1152	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1153	switch (type) {
				1154	case 0:
				1155	Shift = ARM_AM::lsl;
				1156	break;
				1157	case 1:
				1158	Shift = ARM_AM::lsr;
				1159	break;
				1160	case 2:
				1161	Shift = ARM_AM::asr;
				1162	break;
				1163	case 3:
				1164	Shift = ARM_AM::ror;
				1165	break;
				1166	}
				1167
				1168	if (Shift == ARM_AM::ror && imm == 0)
				1169	Shift = ARM_AM::rrx;
				1170
				1171	unsigned Op = Shift \| (imm << 3);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1172	Inst.addOperand(MCOperand::createImm(Op));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1173
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1174	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1175	}
				1176
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1177	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1178	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1179	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1181	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1182	unsigned type = fieldFromInstruction(Val, 5, 2);
				1183	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1184
				1185	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1186	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1187	return MCDisassembler::Fail;
				1188	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1189	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1190
				1191	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1192	switch (type) {
				1193	case 0:
				1194	Shift = ARM_AM::lsl;
				1195	break;
				1196	case 1:
				1197	Shift = ARM_AM::lsr;
				1198	break;
				1199	case 2:
				1200	Shift = ARM_AM::asr;
				1201	break;
				1202	case 3:
				1203	Shift = ARM_AM::ror;
				1204	break;
				1205	}
				1206
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1207	Inst.addOperand(MCOperand::createImm(Shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1208
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1209	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1210	}
				1211
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1212	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1213	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1214	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1215
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1216	bool NeedDisjointWriteback = false;
				1217	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1218	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1219	default:
				1220	break;
				1221	case ARM::LDMIA_UPD:
				1222	case ARM::LDMDB_UPD:
				1223	case ARM::LDMIB_UPD:
				1224	case ARM::LDMDA_UPD:
				1225	case ARM::t2LDMIA_UPD:
				1226	case ARM::t2LDMDB_UPD:
				1227	case ARM::t2STMIA_UPD:
				1228	case ARM::t2STMDB_UPD:
				1229	NeedDisjointWriteback = true;
				1230	WritebackReg = Inst.getOperand(0).getReg();
				1231	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1232	}
				1233
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1234	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1235	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1236	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1237	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1238	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1239	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1240	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1241	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1242	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1243	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1244	}
				1245
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1246	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1247	}
				1248
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1249	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1250	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1251	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1252
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1253	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1254	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1255
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1256	// In case of unpredictable encoding, tweak the operands.
				1257	if (regs == 0 \|\| (Vd + regs) > 32) {
				1258	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1259	regs = std::max( 1u, regs);
				1260	S = MCDisassembler::SoftFail;
				1261	}
				1262
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1263	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1264	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1265	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1266	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1267	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1268	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1269
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1270	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1271	}
				1272
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1273	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1274	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1275	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1276
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1277	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1278	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1279
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1280	// In case of unpredictable encoding, tweak the operands.
				1281	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1282	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1283	regs = std::max( 1u, regs);
				1284	regs = std::min(16u, regs);
				1285	S = MCDisassembler::SoftFail;
				1286	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1287
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1288	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1289	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1290	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1291	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1292	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1293	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1294
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1295	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1296	}
				1297
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1298	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1299	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1300	// This operand encodes a mask of contiguous zeros between a specified MSB
				1301	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1302	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1303	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1304	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1305	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1306	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1307
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1308	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1309	if (lsb > msb) {
				1310	Check(S, MCDisassembler::SoftFail);
				1311	// The check above will cause the warning for the "potentially undefined
				1312	// instruction encoding" but we can't build a bad MCOperand value here
				1313	// with a lsb > msb or else printing the MCInst will cause a crash.
				1314	lsb = msb;
				1315	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1316
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1317	uint32_t msb_mask = 0xFFFFFFFF;
				1318	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1319	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1320
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1321	Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1322	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1323	}
				1324
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1325	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1326	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1327	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1328
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1329	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1330	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1331	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1332	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1333	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1334	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1335
				1336	switch (Inst.getOpcode()) {
				1337	case ARM::LDC_OFFSET:
				1338	case ARM::LDC_PRE:
				1339	case ARM::LDC_POST:
				1340	case ARM::LDC_OPTION:
				1341	case ARM::LDCL_OFFSET:
				1342	case ARM::LDCL_PRE:
				1343	case ARM::LDCL_POST:
				1344	case ARM::LDCL_OPTION:
				1345	case ARM::STC_OFFSET:
				1346	case ARM::STC_PRE:
				1347	case ARM::STC_POST:
				1348	case ARM::STC_OPTION:
				1349	case ARM::STCL_OFFSET:
				1350	case ARM::STCL_PRE:
				1351	case ARM::STCL_POST:
				1352	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1353	case ARM::t2LDC_OFFSET:
				1354	case ARM::t2LDC_PRE:
				1355	case ARM::t2LDC_POST:
				1356	case ARM::t2LDC_OPTION:
				1357	case ARM::t2LDCL_OFFSET:
				1358	case ARM::t2LDCL_PRE:
				1359	case ARM::t2LDCL_POST:
				1360	case ARM::t2LDCL_OPTION:
				1361	case ARM::t2STC_OFFSET:
				1362	case ARM::t2STC_PRE:
				1363	case ARM::t2STC_POST:
				1364	case ARM::t2STC_OPTION:
				1365	case ARM::t2STCL_OFFSET:
				1366	case ARM::t2STCL_PRE:
				1367	case ARM::t2STCL_POST:
				1368	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1369	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1370	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1371	break;
				1372	default:
				1373	break;
				1374	}
				1375
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	1376	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				1377	.getFeatureBits();
				1378	if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1379	return MCDisassembler::Fail;
				1380
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1381	Inst.addOperand(MCOperand::createImm(coproc));
				1382	Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1383	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1384	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1385
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1386	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1387	case ARM::t2LDC2_OFFSET:
				1388	case ARM::t2LDC2L_OFFSET:
				1389	case ARM::t2LDC2_PRE:
				1390	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1391	case ARM::t2STC2_OFFSET:
				1392	case ARM::t2STC2L_OFFSET:
				1393	case ARM::t2STC2_PRE:
				1394	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1395	case ARM::LDC2_OFFSET:
				1396	case ARM::LDC2L_OFFSET:
				1397	case ARM::LDC2_PRE:
				1398	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::STC2_OFFSET:
				1400	case ARM::STC2L_OFFSET:
				1401	case ARM::STC2_PRE:
				1402	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1403	case ARM::t2LDC_OFFSET:
				1404	case ARM::t2LDCL_OFFSET:
				1405	case ARM::t2LDC_PRE:
				1406	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1407	case ARM::t2STC_OFFSET:
				1408	case ARM::t2STCL_OFFSET:
				1409	case ARM::t2STC_PRE:
				1410	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1411	case ARM::LDC_OFFSET:
				1412	case ARM::LDCL_OFFSET:
				1413	case ARM::LDC_PRE:
				1414	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1415	case ARM::STC_OFFSET:
				1416	case ARM::STCL_OFFSET:
				1417	case ARM::STC_PRE:
				1418	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1419	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1420	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1421	break;
				1422	case ARM::t2LDC2_POST:
				1423	case ARM::t2LDC2L_POST:
				1424	case ARM::t2STC2_POST:
				1425	case ARM::t2STC2L_POST:
				1426	case ARM::LDC2_POST:
				1427	case ARM::LDC2L_POST:
				1428	case ARM::STC2_POST:
				1429	case ARM::STC2L_POST:
				1430	case ARM::t2LDC_POST:
				1431	case ARM::t2LDCL_POST:
				1432	case ARM::t2STC_POST:
				1433	case ARM::t2STCL_POST:
				1434	case ARM::LDC_POST:
				1435	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1436	case ARM::STC_POST:
				1437	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1438	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1439	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1440	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1441	// The 'option' variant doesn't encode 'U' in the immediate since
				1442	// the immediate is unsigned [0,255].
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1443	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1444	break;
				1445	}
				1446
				1447	switch (Inst.getOpcode()) {
				1448	case ARM::LDC_OFFSET:
				1449	case ARM::LDC_PRE:
				1450	case ARM::LDC_POST:
				1451	case ARM::LDC_OPTION:
				1452	case ARM::LDCL_OFFSET:
				1453	case ARM::LDCL_PRE:
				1454	case ARM::LDCL_POST:
				1455	case ARM::LDCL_OPTION:
				1456	case ARM::STC_OFFSET:
				1457	case ARM::STC_PRE:
				1458	case ARM::STC_POST:
				1459	case ARM::STC_OPTION:
				1460	case ARM::STCL_OFFSET:
				1461	case ARM::STCL_PRE:
				1462	case ARM::STCL_POST:
				1463	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1464	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1465	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1466	break;
				1467	default:
				1468	break;
				1469	}
				1470
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1471	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1472	}
				1473
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1474	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1475	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1476	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1477	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1478
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1479	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1480	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1481	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1482	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1483	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1484	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1485	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1486	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1487
				1488	// On stores, the writeback operand precedes Rt.
				1489	switch (Inst.getOpcode()) {
				1490	case ARM::STR_POST_IMM:
				1491	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1492	case ARM::STRB_POST_IMM:
				1493	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1494	case ARM::STRT_POST_REG:
				1495	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1496	case ARM::STRBT_POST_REG:
				1497	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1498	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1499	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1500	break;
				1501	default:
				1502	break;
				1503	}
				1504
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1505	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1506	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1507
				1508	// On loads, the writeback operand comes after Rt.
				1509	switch (Inst.getOpcode()) {
				1510	case ARM::LDR_POST_IMM:
				1511	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1512	case ARM::LDRB_POST_IMM:
				1513	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1514	case ARM::LDRBT_POST_REG:
				1515	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1516	case ARM::LDRT_POST_REG:
				1517	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1518	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1519	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1520	break;
				1521	default:
				1522	break;
				1523	}
				1524
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1525	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1526	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1527
				1528	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1529	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1530	Op = ARM_AM::sub;
				1531
				1532	bool writeback = (P == 0) \|\| (W == 1);
				1533	unsigned idx_mode = 0;
				1534	if (P && writeback)
				1535	idx_mode = ARMII::IndexModePre;
				1536	else if (!P && writeback)
				1537	idx_mode = ARMII::IndexModePost;
				1538
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1539	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1540	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1541
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1542	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1543	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1544	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1545	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1546	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1547	case 0:
				1548	Opc = ARM_AM::lsl;
				1549	break;
				1550	case 1:
				1551	Opc = ARM_AM::lsr;
				1552	break;
				1553	case 2:
				1554	Opc = ARM_AM::asr;
				1555	break;
				1556	case 3:
				1557	Opc = ARM_AM::ror;
				1558	break;
				1559	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1560	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1561	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1562	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1563	if (Opc == ARM_AM::ror && amt == 0)
				1564	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1565	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1566
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1567	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1568	} else {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1569	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1570	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1571	Inst.addOperand(MCOperand::createImm(tmp));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1572	}
				1573
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1574	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1575	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1576
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1577	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1578	}
				1579
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1580	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1581	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1582	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1583
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1584	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1585	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1586	unsigned type = fieldFromInstruction(Val, 5, 2);
				1587	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1588	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1589
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1590	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1591	switch (type) {
				1592	case 0:
				1593	ShOp = ARM_AM::lsl;
				1594	break;
				1595	case 1:
				1596	ShOp = ARM_AM::lsr;
				1597	break;
				1598	case 2:
				1599	ShOp = ARM_AM::asr;
				1600	break;
				1601	case 3:
				1602	ShOp = ARM_AM::ror;
				1603	break;
				1604	}
				1605
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1606	if (ShOp == ARM_AM::ror && imm == 0)
				1607	ShOp = ARM_AM::rrx;
				1608
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1609	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1610	return MCDisassembler::Fail;
				1611	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1612	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1613	unsigned shift;
				1614	if (U)
				1615	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1616	else
				1617	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1618	Inst.addOperand(MCOperand::createImm(shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1619
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1620	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1621	}
				1622
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1623	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1624	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1625	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1626	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1627
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1628	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1629	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1630	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1631	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1632	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1633	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1634	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1635	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1636	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1637	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1638
				1639	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1640
				1641	// For {LD,ST}RD, Rt must be even, else undefined.
				1642	switch (Inst.getOpcode()) {
				1643	case ARM::STRD:
				1644	case ARM::STRD_PRE:
				1645	case ARM::STRD_POST:
				1646	case ARM::LDRD:
				1647	case ARM::LDRD_PRE:
				1648	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1649	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1650	break;
				1651	default:
				1652	break;
				1653	}
				1654	switch (Inst.getOpcode()) {
				1655	case ARM::STRD:
				1656	case ARM::STRD_PRE:
				1657	case ARM::STRD_POST:
				1658	if (P == 0 && W == 1)
				1659	S = MCDisassembler::SoftFail;
				1660
				1661	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1662	S = MCDisassembler::SoftFail;
				1663	if (type && Rm == 15)
				1664	S = MCDisassembler::SoftFail;
				1665	if (Rt2 == 15)
				1666	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1667	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1668	S = MCDisassembler::SoftFail;
				1669	break;
				1670	case ARM::STRH:
				1671	case ARM::STRH_PRE:
				1672	case ARM::STRH_POST:
				1673	if (Rt == 15)
				1674	S = MCDisassembler::SoftFail;
				1675	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1676	S = MCDisassembler::SoftFail;
				1677	if (!type && Rm == 15)
				1678	S = MCDisassembler::SoftFail;
				1679	break;
				1680	case ARM::LDRD:
				1681	case ARM::LDRD_PRE:
				1682	case ARM::LDRD_POST:
				1683	if (type && Rn == 15){
				1684	if (Rt2 == 15)
				1685	S = MCDisassembler::SoftFail;
				1686	break;
				1687	}
				1688	if (P == 0 && W == 1)
				1689	S = MCDisassembler::SoftFail;
				1690	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1691	S = MCDisassembler::SoftFail;
				1692	if (!type && writeback && Rn == 15)
				1693	S = MCDisassembler::SoftFail;
				1694	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1695	S = MCDisassembler::SoftFail;
				1696	break;
				1697	case ARM::LDRH:
				1698	case ARM::LDRH_PRE:
				1699	case ARM::LDRH_POST:
				1700	if (type && Rn == 15){
				1701	if (Rt == 15)
				1702	S = MCDisassembler::SoftFail;
				1703	break;
				1704	}
				1705	if (Rt == 15)
				1706	S = MCDisassembler::SoftFail;
				1707	if (!type && Rm == 15)
				1708	S = MCDisassembler::SoftFail;
				1709	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1710	S = MCDisassembler::SoftFail;
				1711	break;
				1712	case ARM::LDRSH:
				1713	case ARM::LDRSH_PRE:
				1714	case ARM::LDRSH_POST:
				1715	case ARM::LDRSB:
				1716	case ARM::LDRSB_PRE:
				1717	case ARM::LDRSB_POST:
				1718	if (type && Rn == 15){
				1719	if (Rt == 15)
				1720	S = MCDisassembler::SoftFail;
				1721	break;
				1722	}
				1723	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1724	S = MCDisassembler::SoftFail;
				1725	if (!type && (Rt == 15 \|\| Rm == 15))
				1726	S = MCDisassembler::SoftFail;
				1727	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1728	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1729	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1730	default:
				1731	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1732	}
				1733
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1734	if (writeback) { // Writeback
				1735	if (P)
				1736	U \|= ARMII::IndexModePre << 9;
				1737	else
				1738	U \|= ARMII::IndexModePost << 9;
				1739
				1740	// On stores, the writeback operand precedes Rt.
				1741	switch (Inst.getOpcode()) {
				1742	case ARM::STRD:
				1743	case ARM::STRD_PRE:
				1744	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1745	case ARM::STRH:
				1746	case ARM::STRH_PRE:
				1747	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1748	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1749	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1750	break;
				1751	default:
				1752	break;
				1753	}
				1754	}
				1755
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1756	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1757	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1758	switch (Inst.getOpcode()) {
				1759	case ARM::STRD:
				1760	case ARM::STRD_PRE:
				1761	case ARM::STRD_POST:
				1762	case ARM::LDRD:
				1763	case ARM::LDRD_PRE:
				1764	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1765	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1766	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1767	break;
				1768	default:
				1769	break;
				1770	}
				1771
				1772	if (writeback) {
				1773	// On loads, the writeback operand comes after Rt.
				1774	switch (Inst.getOpcode()) {
				1775	case ARM::LDRD:
				1776	case ARM::LDRD_PRE:
				1777	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1778	case ARM::LDRH:
				1779	case ARM::LDRH_PRE:
				1780	case ARM::LDRH_POST:
				1781	case ARM::LDRSH:
				1782	case ARM::LDRSH_PRE:
				1783	case ARM::LDRSH_POST:
				1784	case ARM::LDRSB:
				1785	case ARM::LDRSB_PRE:
				1786	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1787	case ARM::LDRHTr:
				1788	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1789	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1790	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1791	break;
				1792	default:
				1793	break;
				1794	}
				1795	}
				1796
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1797	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1798	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1799
				1800	if (type) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1801	Inst.addOperand(MCOperand::createReg(0));
				1802	Inst.addOperand(MCOperand::createImm(U \| (imm << 4) \| Rm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1803	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1804	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1805	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1806	Inst.addOperand(MCOperand::createImm(U));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1807	}
				1808
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1809	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1810	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1811
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1812	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1813	}
				1814
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1815	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1816	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1817	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1818
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1819	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1820	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1821
				1822	switch (mode) {
				1823	case 0:
				1824	mode = ARM_AM::da;
				1825	break;
				1826	case 1:
				1827	mode = ARM_AM::ia;
				1828	break;
				1829	case 2:
				1830	mode = ARM_AM::db;
				1831	break;
				1832	case 3:
				1833	mode = ARM_AM::ib;
				1834	break;
				1835	}
				1836
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1837	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1838	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1839	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1840
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1841	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1842	}
				1843
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1844	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1845	uint64_t Address, const void *Decoder) {
				1846	DecodeStatus S = MCDisassembler::Success;
				1847
				1848	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1849	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1850	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1851	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1852
				1853	if (pred == 0xF)
				1854	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1855
				1856	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1857	return MCDisassembler::Fail;
				1858	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1859	return MCDisassembler::Fail;
				1860	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1861	return MCDisassembler::Fail;
				1862	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1863	return MCDisassembler::Fail;
				1864	return S;
				1865	}
				1866
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1867	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	unsigned Insn,
				1869	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1870	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1871
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1872	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1873	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1874	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1875
				1876	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1877	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1878	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1879	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1880	Inst.setOpcode(ARM::RFEDA);
				1881	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1882	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1883	Inst.setOpcode(ARM::RFEDA_UPD);
				1884	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1885	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1886	Inst.setOpcode(ARM::RFEDB);
				1887	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1888	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1889	Inst.setOpcode(ARM::RFEDB_UPD);
				1890	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1891	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1892	Inst.setOpcode(ARM::RFEIA);
				1893	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1894	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1895	Inst.setOpcode(ARM::RFEIA_UPD);
				1896	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1897	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1898	Inst.setOpcode(ARM::RFEIB);
				1899	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1900	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1901	Inst.setOpcode(ARM::RFEIB_UPD);
				1902	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1903	case ARM::STMDA:
				1904	Inst.setOpcode(ARM::SRSDA);
				1905	break;
				1906	case ARM::STMDA_UPD:
				1907	Inst.setOpcode(ARM::SRSDA_UPD);
				1908	break;
				1909	case ARM::STMDB:
				1910	Inst.setOpcode(ARM::SRSDB);
				1911	break;
				1912	case ARM::STMDB_UPD:
				1913	Inst.setOpcode(ARM::SRSDB_UPD);
				1914	break;
				1915	case ARM::STMIA:
				1916	Inst.setOpcode(ARM::SRSIA);
				1917	break;
				1918	case ARM::STMIA_UPD:
				1919	Inst.setOpcode(ARM::SRSIA_UPD);
				1920	break;
				1921	case ARM::STMIB:
				1922	Inst.setOpcode(ARM::SRSIB);
				1923	break;
				1924	case ARM::STMIB_UPD:
				1925	Inst.setOpcode(ARM::SRSIB_UPD);
				1926	break;
				1927	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1928	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1929	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1930
				1931	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1932	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1933	// Check SRS encoding constraints
				1934	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1935	fieldFromInstruction(Insn, 20, 1) == 0))
				1936	return MCDisassembler::Fail;
				1937
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1938	Inst.addOperand(
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1939	MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1940	return S;
				1941	}
				1942
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1943	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1944	}
				1945
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1946	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1947	return MCDisassembler::Fail;
				1948	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1949	return MCDisassembler::Fail; // Tied
				1950	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1951	return MCDisassembler::Fail;
				1952	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1953	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1954
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1955	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1956	}
				1957
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1958	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1959	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1960	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1961	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1962	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1963	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1964
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1965	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1966
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1967	// This decoder is called from multiple location that do not check
				1968	// the full encoding is valid before they do.
				1969	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1970	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1971	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1972	return MCDisassembler::Fail;
				1973
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1974	// imod == '01' --> UNPREDICTABLE
				1975	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1976	// return failure here. The '01' imod value is unprintable, so there's
				1977	// nothing useful we could do even if we returned UNPREDICTABLE.
				1978
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1979	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1980
				1981	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1982	Inst.setOpcode(ARM::CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1983	Inst.addOperand(MCOperand::createImm(imod));
				1984	Inst.addOperand(MCOperand::createImm(iflags));
				1985	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1986	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1987	Inst.setOpcode(ARM::CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1988	Inst.addOperand(MCOperand::createImm(imod));
				1989	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1990	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1991	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1992	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1993	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1994	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1995	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1996	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1997	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	1998	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1999	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2000	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2001
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2002	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2003	}
				2004
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2005	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2006	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2007	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				2008	unsigned M = fieldFromInstruction(Insn, 8, 1);
				2009	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2010	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2011
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2012	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2013
				2014	// imod == '01' --> UNPREDICTABLE
				2015	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2016	// return failure here. The '01' imod value is unprintable, so there's
				2017	// nothing useful we could do even if we returned UNPREDICTABLE.
				2018
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2019	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2020
				2021	if (imod && M) {
				2022	Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2023	Inst.addOperand(MCOperand::createImm(imod));
				2024	Inst.addOperand(MCOperand::createImm(iflags));
				2025	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2026	} else if (imod && !M) {
				2027	Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2028	Inst.addOperand(MCOperand::createImm(imod));
				2029	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2030	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2031	} else if (!imod && M) {
				2032	Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2033	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2034	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2035	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2036	// imod == '00' && M == '0' --> this is a HINT instruction
				2037	int imm = fieldFromInstruction(Insn, 0, 8);
				2038	// HINT are defined only for immediate in [0..4]
				2039	if(imm > 4) return MCDisassembler::Fail;
				2040	Inst.setOpcode(ARM::t2HINT);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2041	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2042	}
				2043
				2044	return S;
				2045	}
				2046
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2047	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2048	uint64_t Address, const void *Decoder) {
				2049	DecodeStatus S = MCDisassembler::Success;
				2050
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2051	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2052	unsigned imm = 0;
				2053
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2054	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2055	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2056	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2057	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2058
				2059	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2060	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2061	return MCDisassembler::Fail;
				2062	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2063	return MCDisassembler::Fail;
				2064
				2065	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2066	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2067
				2068	return S;
				2069	}
				2070
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2071	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2072	uint64_t Address, const void *Decoder) {
				2073	DecodeStatus S = MCDisassembler::Success;
				2074
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2075	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2076	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2077	unsigned imm = 0;
				2078
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2079	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2080	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2081
				2082	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2083	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2084	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2085
				2086	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2087	return MCDisassembler::Fail;
				2088
				2089	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2090	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2091
				2092	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2093	return MCDisassembler::Fail;
				2094
				2095	return S;
				2096	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2097
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2098	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2099	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2100	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2101
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2102	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2103	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2104	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2105	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2106	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2107
				2108	if (pred == 0xF)
				2109	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2110
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2111	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2112	return MCDisassembler::Fail;
				2113	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2114	return MCDisassembler::Fail;
				2115	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2116	return MCDisassembler::Fail;
				2117	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2118	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2119
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2120	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2121	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2122
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2123	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2124	}
				2125
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2126	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				2127	uint64_t Address, const void *Decoder) {
				2128	DecodeStatus S = MCDisassembler::Success;
				2129
				2130	unsigned Pred = fieldFromInstruction(Insn, 28, 4);
				2131	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2132	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2133
				2134	if (Pred == 0xF)
				2135	return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
				2136
				2137	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2138	return MCDisassembler::Fail;
				2139	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2140	return MCDisassembler::Fail;
				2141	if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
				2142	return MCDisassembler::Fail;
				2143
				2144	return S;
				2145	}
				2146
				2147	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				2148	uint64_t Address, const void *Decoder) {
				2149	DecodeStatus S = MCDisassembler::Success;
				2150
				2151	unsigned Imm = fieldFromInstruction(Insn, 9, 1);
				2152
				2153	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	2154	uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				2155	if ((FeatureBits & ARM::HasV8_1aOps) == 0 \|\|
				2156	(FeatureBits & ARM::HasV8Ops) == 0 )
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2157	return MCDisassembler::Fail;
				2158
				2159	// Decoder can be called from DecodeTST, which does not check the full
				2160	// encoding is valid.
				2161	if (fieldFromInstruction(Insn, 20,12) != 0xf11 \|\|
				2162	fieldFromInstruction(Insn, 4,4) != 0)
				2163	return MCDisassembler::Fail;
				2164	if (fieldFromInstruction(Insn, 10,10) != 0 \|\|
				2165	fieldFromInstruction(Insn, 0,4) != 0)
				2166	S = MCDisassembler::SoftFail;
				2167
				2168	Inst.setOpcode(ARM::SETPAN);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2169	Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2170
				2171	return S;
				2172	}
				2173
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2174	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2175	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2176	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2177
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2178	unsigned add = fieldFromInstruction(Val, 12, 1);
				2179	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2180	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2181
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2182	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2183	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2184
				2185	if (!add) imm *= -1;
				2186	if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2187	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2188	if (Rn == 15)
				2189	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2190
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2191	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2192	}
				2193
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2194	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2198	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2199	unsigned U = fieldFromInstruction(Val, 8, 1);
				2200	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2201
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2202	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2203	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2204
				2205	if (U)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2206	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2207	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2208	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2209
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2210	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2211	}
				2212
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2213	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2214	uint64_t Address, const void *Decoder) {
				2215	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2216	}
				2217
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2218	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2219	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2220	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2221	DecodeStatus Status = MCDisassembler::Success;
				2222
				2223	// Note the J1 and J2 values are from the encoded instruction. So here
				2224	// change them to I1 and I2 values via as documented:
				2225	// I1 = NOT(J1 EOR S);
				2226	// I2 = NOT(J2 EOR S);
				2227	// and build the imm32 with one trailing zero as documented:
				2228	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2229	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2230	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2231	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2232	unsigned I1 = !(J1 ^ S);
				2233	unsigned I2 = !(J2 ^ S);
				2234	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2235	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2236	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2237	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2238	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2239	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2240	Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2241
				2242	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2243	}
				2244
				2245	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2246	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2247	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2248	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2249
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2250	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2251	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2252
				2253	if (pred == 0xF) {
				2254	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2255	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2256	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2257	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2258	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2259	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2260	}
				2261
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2262	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2263	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2264	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2265	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2266	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2267
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2268	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2269	}
				2270
				2271
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2272	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2273	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2274	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2275
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2276	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2277	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2278
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2279	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2280	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2281	if (!align)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2282	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2283	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2284	Inst.addOperand(MCOperand::createImm(4 << align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2285
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2286	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2287	}
				2288
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2289	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2290	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2291	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2292
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2293	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2294	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2295	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2296	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2297	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2298	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2299
				2300	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2301	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2302	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2303	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2304	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2305	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2306	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2307	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2308	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2309	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2310	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2311	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2312	return MCDisassembler::Fail;
				2313	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2314	case ARM::VLD2b16:
				2315	case ARM::VLD2b32:
				2316	case ARM::VLD2b8:
				2317	case ARM::VLD2b16wb_fixed:
				2318	case ARM::VLD2b16wb_register:
				2319	case ARM::VLD2b32wb_fixed:
				2320	case ARM::VLD2b32wb_register:
				2321	case ARM::VLD2b8wb_fixed:
				2322	case ARM::VLD2b8wb_register:
				2323	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2324	return MCDisassembler::Fail;
				2325	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2326	default:
				2327	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2328	return MCDisassembler::Fail;
				2329	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2330
				2331	// Second output register
				2332	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2333	case ARM::VLD3d8:
				2334	case ARM::VLD3d16:
				2335	case ARM::VLD3d32:
				2336	case ARM::VLD3d8_UPD:
				2337	case ARM::VLD3d16_UPD:
				2338	case ARM::VLD3d32_UPD:
				2339	case ARM::VLD4d8:
				2340	case ARM::VLD4d16:
				2341	case ARM::VLD4d32:
				2342	case ARM::VLD4d8_UPD:
				2343	case ARM::VLD4d16_UPD:
				2344	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2345	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2346	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2347	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2348	case ARM::VLD3q8:
				2349	case ARM::VLD3q16:
				2350	case ARM::VLD3q32:
				2351	case ARM::VLD3q8_UPD:
				2352	case ARM::VLD3q16_UPD:
				2353	case ARM::VLD3q32_UPD:
				2354	case ARM::VLD4q8:
				2355	case ARM::VLD4q16:
				2356	case ARM::VLD4q32:
				2357	case ARM::VLD4q8_UPD:
				2358	case ARM::VLD4q16_UPD:
				2359	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2360	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2361	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2362	default:
				2363	break;
				2364	}
				2365
				2366	// Third output register
				2367	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2368	case ARM::VLD3d8:
				2369	case ARM::VLD3d16:
				2370	case ARM::VLD3d32:
				2371	case ARM::VLD3d8_UPD:
				2372	case ARM::VLD3d16_UPD:
				2373	case ARM::VLD3d32_UPD:
				2374	case ARM::VLD4d8:
				2375	case ARM::VLD4d16:
				2376	case ARM::VLD4d32:
				2377	case ARM::VLD4d8_UPD:
				2378	case ARM::VLD4d16_UPD:
				2379	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2380	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2381	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2382	break;
				2383	case ARM::VLD3q8:
				2384	case ARM::VLD3q16:
				2385	case ARM::VLD3q32:
				2386	case ARM::VLD3q8_UPD:
				2387	case ARM::VLD3q16_UPD:
				2388	case ARM::VLD3q32_UPD:
				2389	case ARM::VLD4q8:
				2390	case ARM::VLD4q16:
				2391	case ARM::VLD4q32:
				2392	case ARM::VLD4q8_UPD:
				2393	case ARM::VLD4q16_UPD:
				2394	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2395	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2396	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2397	break;
				2398	default:
				2399	break;
				2400	}
				2401
				2402	// Fourth output register
				2403	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2404	case ARM::VLD4d8:
				2405	case ARM::VLD4d16:
				2406	case ARM::VLD4d32:
				2407	case ARM::VLD4d8_UPD:
				2408	case ARM::VLD4d16_UPD:
				2409	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2410	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2411	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2412	break;
				2413	case ARM::VLD4q8:
				2414	case ARM::VLD4q16:
				2415	case ARM::VLD4q32:
				2416	case ARM::VLD4q8_UPD:
				2417	case ARM::VLD4q16_UPD:
				2418	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2419	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2420	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2421	break;
				2422	default:
				2423	break;
				2424	}
				2425
				2426	// Writeback operand
				2427	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2428	case ARM::VLD1d8wb_fixed:
				2429	case ARM::VLD1d16wb_fixed:
				2430	case ARM::VLD1d32wb_fixed:
				2431	case ARM::VLD1d64wb_fixed:
				2432	case ARM::VLD1d8wb_register:
				2433	case ARM::VLD1d16wb_register:
				2434	case ARM::VLD1d32wb_register:
				2435	case ARM::VLD1d64wb_register:
				2436	case ARM::VLD1q8wb_fixed:
				2437	case ARM::VLD1q16wb_fixed:
				2438	case ARM::VLD1q32wb_fixed:
				2439	case ARM::VLD1q64wb_fixed:
				2440	case ARM::VLD1q8wb_register:
				2441	case ARM::VLD1q16wb_register:
				2442	case ARM::VLD1q32wb_register:
				2443	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2444	case ARM::VLD1d8Twb_fixed:
				2445	case ARM::VLD1d8Twb_register:
				2446	case ARM::VLD1d16Twb_fixed:
				2447	case ARM::VLD1d16Twb_register:
				2448	case ARM::VLD1d32Twb_fixed:
				2449	case ARM::VLD1d32Twb_register:
				2450	case ARM::VLD1d64Twb_fixed:
				2451	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2452	case ARM::VLD1d8Qwb_fixed:
				2453	case ARM::VLD1d8Qwb_register:
				2454	case ARM::VLD1d16Qwb_fixed:
				2455	case ARM::VLD1d16Qwb_register:
				2456	case ARM::VLD1d32Qwb_fixed:
				2457	case ARM::VLD1d32Qwb_register:
				2458	case ARM::VLD1d64Qwb_fixed:
				2459	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2460	case ARM::VLD2d8wb_fixed:
				2461	case ARM::VLD2d16wb_fixed:
				2462	case ARM::VLD2d32wb_fixed:
				2463	case ARM::VLD2q8wb_fixed:
				2464	case ARM::VLD2q16wb_fixed:
				2465	case ARM::VLD2q32wb_fixed:
				2466	case ARM::VLD2d8wb_register:
				2467	case ARM::VLD2d16wb_register:
				2468	case ARM::VLD2d32wb_register:
				2469	case ARM::VLD2q8wb_register:
				2470	case ARM::VLD2q16wb_register:
				2471	case ARM::VLD2q32wb_register:
				2472	case ARM::VLD2b8wb_fixed:
				2473	case ARM::VLD2b16wb_fixed:
				2474	case ARM::VLD2b32wb_fixed:
				2475	case ARM::VLD2b8wb_register:
				2476	case ARM::VLD2b16wb_register:
				2477	case ARM::VLD2b32wb_register:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2478	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2479	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2480	case ARM::VLD3d8_UPD:
				2481	case ARM::VLD3d16_UPD:
				2482	case ARM::VLD3d32_UPD:
				2483	case ARM::VLD3q8_UPD:
				2484	case ARM::VLD3q16_UPD:
				2485	case ARM::VLD3q32_UPD:
				2486	case ARM::VLD4d8_UPD:
				2487	case ARM::VLD4d16_UPD:
				2488	case ARM::VLD4d32_UPD:
				2489	case ARM::VLD4q8_UPD:
				2490	case ARM::VLD4q16_UPD:
				2491	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2492	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2493	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2494	break;
				2495	default:
				2496	break;
				2497	}
				2498
				2499	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2500	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2501	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2502
				2503	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2504	switch (Inst.getOpcode()) {
				2505	default:
				2506	// The below have been updated to have explicit am6offset split
				2507	// between fixed and register offset. For those instructions not
				2508	// yet updated, we need to add an additional reg0 operand for the
				2509	// fixed variant.
				2510	//
				2511	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2512	if (Rm == 0xd) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2513	Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2514	break;
				2515	}
				2516	// Fall through to handle the register offset variant.
				2517	case ARM::VLD1d8wb_fixed:
				2518	case ARM::VLD1d16wb_fixed:
				2519	case ARM::VLD1d32wb_fixed:
				2520	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2521	case ARM::VLD1d8Twb_fixed:
				2522	case ARM::VLD1d16Twb_fixed:
				2523	case ARM::VLD1d32Twb_fixed:
				2524	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2525	case ARM::VLD1d8Qwb_fixed:
				2526	case ARM::VLD1d16Qwb_fixed:
				2527	case ARM::VLD1d32Qwb_fixed:
				2528	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2529	case ARM::VLD1d8wb_register:
				2530	case ARM::VLD1d16wb_register:
				2531	case ARM::VLD1d32wb_register:
				2532	case ARM::VLD1d64wb_register:
				2533	case ARM::VLD1q8wb_fixed:
				2534	case ARM::VLD1q16wb_fixed:
				2535	case ARM::VLD1q32wb_fixed:
				2536	case ARM::VLD1q64wb_fixed:
				2537	case ARM::VLD1q8wb_register:
				2538	case ARM::VLD1q16wb_register:
				2539	case ARM::VLD1q32wb_register:
				2540	case ARM::VLD1q64wb_register:
				2541	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2542	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2543	// increment and we need to add the register operand to the instruction.
				2544	if (Rm != 0xD && Rm != 0xF &&
				2545	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2546	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2547	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2548	case ARM::VLD2d8wb_fixed:
				2549	case ARM::VLD2d16wb_fixed:
				2550	case ARM::VLD2d32wb_fixed:
				2551	case ARM::VLD2b8wb_fixed:
				2552	case ARM::VLD2b16wb_fixed:
				2553	case ARM::VLD2b32wb_fixed:
				2554	case ARM::VLD2q8wb_fixed:
				2555	case ARM::VLD2q16wb_fixed:
				2556	case ARM::VLD2q32wb_fixed:
				2557	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2558	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2559
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2560	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2561	}
				2562
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2563	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2564	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2565	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2566	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2567	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2568	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2569	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2570
				2571	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2572	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2573	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2574	}
				2575
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2576	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2577	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2578	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2579	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2580
				2581	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2582	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2583	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2584	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2585
				2586	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2587	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2588	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2589	}
				2590
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2591	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2592	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2593	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2594	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2595
				2596	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2597	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2598
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2599	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2600	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2601	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2602	}
				2603
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2604	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2605	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2606	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2607	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2608
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2609	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2610	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2611	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2612	}
				2613
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2614	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2615	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2616	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2617
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2618	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2619	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2620	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2621	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2622	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2623	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2624
				2625	// Writeback Operand
				2626	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2627	case ARM::VST1d8wb_fixed:
				2628	case ARM::VST1d16wb_fixed:
				2629	case ARM::VST1d32wb_fixed:
				2630	case ARM::VST1d64wb_fixed:
				2631	case ARM::VST1d8wb_register:
				2632	case ARM::VST1d16wb_register:
				2633	case ARM::VST1d32wb_register:
				2634	case ARM::VST1d64wb_register:
				2635	case ARM::VST1q8wb_fixed:
				2636	case ARM::VST1q16wb_fixed:
				2637	case ARM::VST1q32wb_fixed:
				2638	case ARM::VST1q64wb_fixed:
				2639	case ARM::VST1q8wb_register:
				2640	case ARM::VST1q16wb_register:
				2641	case ARM::VST1q32wb_register:
				2642	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2643	case ARM::VST1d8Twb_fixed:
				2644	case ARM::VST1d16Twb_fixed:
				2645	case ARM::VST1d32Twb_fixed:
				2646	case ARM::VST1d64Twb_fixed:
				2647	case ARM::VST1d8Twb_register:
				2648	case ARM::VST1d16Twb_register:
				2649	case ARM::VST1d32Twb_register:
				2650	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2651	case ARM::VST1d8Qwb_fixed:
				2652	case ARM::VST1d16Qwb_fixed:
				2653	case ARM::VST1d32Qwb_fixed:
				2654	case ARM::VST1d64Qwb_fixed:
				2655	case ARM::VST1d8Qwb_register:
				2656	case ARM::VST1d16Qwb_register:
				2657	case ARM::VST1d32Qwb_register:
				2658	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2659	case ARM::VST2d8wb_fixed:
				2660	case ARM::VST2d16wb_fixed:
				2661	case ARM::VST2d32wb_fixed:
				2662	case ARM::VST2d8wb_register:
				2663	case ARM::VST2d16wb_register:
				2664	case ARM::VST2d32wb_register:
				2665	case ARM::VST2q8wb_fixed:
				2666	case ARM::VST2q16wb_fixed:
				2667	case ARM::VST2q32wb_fixed:
				2668	case ARM::VST2q8wb_register:
				2669	case ARM::VST2q16wb_register:
				2670	case ARM::VST2q32wb_register:
				2671	case ARM::VST2b8wb_fixed:
				2672	case ARM::VST2b16wb_fixed:
				2673	case ARM::VST2b32wb_fixed:
				2674	case ARM::VST2b8wb_register:
				2675	case ARM::VST2b16wb_register:
				2676	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2677	if (Rm == 0xF)
				2678	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2679	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2680	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2681	case ARM::VST3d8_UPD:
				2682	case ARM::VST3d16_UPD:
				2683	case ARM::VST3d32_UPD:
				2684	case ARM::VST3q8_UPD:
				2685	case ARM::VST3q16_UPD:
				2686	case ARM::VST3q32_UPD:
				2687	case ARM::VST4d8_UPD:
				2688	case ARM::VST4d16_UPD:
				2689	case ARM::VST4d32_UPD:
				2690	case ARM::VST4q8_UPD:
				2691	case ARM::VST4q16_UPD:
				2692	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2693	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2694	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2695	break;
				2696	default:
				2697	break;
				2698	}
				2699
				2700	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2701	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2702	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2703
				2704	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2705	switch (Inst.getOpcode()) {
				2706	default:
				2707	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2708	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2709	else if (Rm != 0xF) {
				2710	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2711	return MCDisassembler::Fail;
				2712	}
				2713	break;
				2714	case ARM::VST1d8wb_fixed:
				2715	case ARM::VST1d16wb_fixed:
				2716	case ARM::VST1d32wb_fixed:
				2717	case ARM::VST1d64wb_fixed:
				2718	case ARM::VST1q8wb_fixed:
				2719	case ARM::VST1q16wb_fixed:
				2720	case ARM::VST1q32wb_fixed:
				2721	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2722	case ARM::VST1d8Twb_fixed:
				2723	case ARM::VST1d16Twb_fixed:
				2724	case ARM::VST1d32Twb_fixed:
				2725	case ARM::VST1d64Twb_fixed:
				2726	case ARM::VST1d8Qwb_fixed:
				2727	case ARM::VST1d16Qwb_fixed:
				2728	case ARM::VST1d32Qwb_fixed:
				2729	case ARM::VST1d64Qwb_fixed:
				2730	case ARM::VST2d8wb_fixed:
				2731	case ARM::VST2d16wb_fixed:
				2732	case ARM::VST2d32wb_fixed:
				2733	case ARM::VST2q8wb_fixed:
				2734	case ARM::VST2q16wb_fixed:
				2735	case ARM::VST2q32wb_fixed:
				2736	case ARM::VST2b8wb_fixed:
				2737	case ARM::VST2b16wb_fixed:
				2738	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2739	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2740	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2741
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2742
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2743	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2744	switch (Inst.getOpcode()) {
				2745	case ARM::VST1q16:
				2746	case ARM::VST1q32:
				2747	case ARM::VST1q64:
				2748	case ARM::VST1q8:
				2749	case ARM::VST1q16wb_fixed:
				2750	case ARM::VST1q16wb_register:
				2751	case ARM::VST1q32wb_fixed:
				2752	case ARM::VST1q32wb_register:
				2753	case ARM::VST1q64wb_fixed:
				2754	case ARM::VST1q64wb_register:
				2755	case ARM::VST1q8wb_fixed:
				2756	case ARM::VST1q8wb_register:
				2757	case ARM::VST2d16:
				2758	case ARM::VST2d32:
				2759	case ARM::VST2d8:
				2760	case ARM::VST2d16wb_fixed:
				2761	case ARM::VST2d16wb_register:
				2762	case ARM::VST2d32wb_fixed:
				2763	case ARM::VST2d32wb_register:
				2764	case ARM::VST2d8wb_fixed:
				2765	case ARM::VST2d8wb_register:
				2766	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2767	return MCDisassembler::Fail;
				2768	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2769	case ARM::VST2b16:
				2770	case ARM::VST2b32:
				2771	case ARM::VST2b8:
				2772	case ARM::VST2b16wb_fixed:
				2773	case ARM::VST2b16wb_register:
				2774	case ARM::VST2b32wb_fixed:
				2775	case ARM::VST2b32wb_register:
				2776	case ARM::VST2b8wb_fixed:
				2777	case ARM::VST2b8wb_register:
				2778	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2779	return MCDisassembler::Fail;
				2780	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2781	default:
				2782	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2783	return MCDisassembler::Fail;
				2784	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2785
				2786	// Second input register
				2787	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2788	case ARM::VST3d8:
				2789	case ARM::VST3d16:
				2790	case ARM::VST3d32:
				2791	case ARM::VST3d8_UPD:
				2792	case ARM::VST3d16_UPD:
				2793	case ARM::VST3d32_UPD:
				2794	case ARM::VST4d8:
				2795	case ARM::VST4d16:
				2796	case ARM::VST4d32:
				2797	case ARM::VST4d8_UPD:
				2798	case ARM::VST4d16_UPD:
				2799	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2800	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2801	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2802	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2803	case ARM::VST3q8:
				2804	case ARM::VST3q16:
				2805	case ARM::VST3q32:
				2806	case ARM::VST3q8_UPD:
				2807	case ARM::VST3q16_UPD:
				2808	case ARM::VST3q32_UPD:
				2809	case ARM::VST4q8:
				2810	case ARM::VST4q16:
				2811	case ARM::VST4q32:
				2812	case ARM::VST4q8_UPD:
				2813	case ARM::VST4q16_UPD:
				2814	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2815	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2816	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2817	break;
				2818	default:
				2819	break;
				2820	}
				2821
				2822	// Third input register
				2823	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2824	case ARM::VST3d8:
				2825	case ARM::VST3d16:
				2826	case ARM::VST3d32:
				2827	case ARM::VST3d8_UPD:
				2828	case ARM::VST3d16_UPD:
				2829	case ARM::VST3d32_UPD:
				2830	case ARM::VST4d8:
				2831	case ARM::VST4d16:
				2832	case ARM::VST4d32:
				2833	case ARM::VST4d8_UPD:
				2834	case ARM::VST4d16_UPD:
				2835	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2836	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2837	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2838	break;
				2839	case ARM::VST3q8:
				2840	case ARM::VST3q16:
				2841	case ARM::VST3q32:
				2842	case ARM::VST3q8_UPD:
				2843	case ARM::VST3q16_UPD:
				2844	case ARM::VST3q32_UPD:
				2845	case ARM::VST4q8:
				2846	case ARM::VST4q16:
				2847	case ARM::VST4q32:
				2848	case ARM::VST4q8_UPD:
				2849	case ARM::VST4q16_UPD:
				2850	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2851	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2852	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2853	break;
				2854	default:
				2855	break;
				2856	}
				2857
				2858	// Fourth input register
				2859	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2860	case ARM::VST4d8:
				2861	case ARM::VST4d16:
				2862	case ARM::VST4d32:
				2863	case ARM::VST4d8_UPD:
				2864	case ARM::VST4d16_UPD:
				2865	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2866	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2867	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2868	break;
				2869	case ARM::VST4q8:
				2870	case ARM::VST4q16:
				2871	case ARM::VST4q32:
				2872	case ARM::VST4q8_UPD:
				2873	case ARM::VST4q16_UPD:
				2874	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2875	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2876	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2877	break;
				2878	default:
				2879	break;
				2880	}
				2881
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2882	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2883	}
				2884
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2885	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2886	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2887	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2888
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2889	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2890	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2891	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2892	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2893	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2894	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2895
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2896	if (size == 0 && align == 1)
				2897	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2898	align *= (1 << size);
				2899
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2900	switch (Inst.getOpcode()) {
				2901	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2902	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2903	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2904	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2905	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2906	return MCDisassembler::Fail;
				2907	break;
				2908	default:
				2909	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2910	return MCDisassembler::Fail;
				2911	break;
				2912	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2913	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2914	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2915	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2916	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2917
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2918	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2919	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2920	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2921
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2922	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2923	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2924	// increment and we need to add the register operand to the instruction.
				2925	if (Rm != 0xD && Rm != 0xF &&
				2926	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2927	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2928
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2929	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2930	}
				2931
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2932	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2933	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2934	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2935
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2936	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2937	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2938	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2939	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2940	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2941	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2942	align = 2size;
				2943
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2944	switch (Inst.getOpcode()) {
				2945	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2946	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2947	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2948	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2949	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2950	return MCDisassembler::Fail;
				2951	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2952	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2953	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2954	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2955	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2956	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2957	return MCDisassembler::Fail;
				2958	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2959	default:
				2960	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2961	return MCDisassembler::Fail;
				2962	break;
				2963	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2964
				2965	if (Rm != 0xF)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2966	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2967
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2968	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2969	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	2970	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2971
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2972	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2973	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2974	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2975	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2976
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2977	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2978	}
				2979
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2980	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2981	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2982	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2983
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2984	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2985	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2986	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2987	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2988	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2989
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2990	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2991	return MCDisassembler::Fail;
				2992	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2993	return MCDisassembler::Fail;
				2994	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2995	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2996	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2997	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2998	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2999	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3000
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3001	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3002	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3003	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3004
				3005	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3006	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3007	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3008	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3009	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3010	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3011
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3012	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3013	}
				3014
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3015	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3016	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3017	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3018
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3019	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3020	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3021	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3022	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3023	unsigned size = fieldFromInstruction(Insn, 6, 2);
				3024	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				3025	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3026
				3027	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	3028	if (align == 0)
				3029	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3030	align = 16;
				3031	} else {
				3032	if (size == 2) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3033	align *= 8;
				3034	} else {
				3035	size = 1 << size;
				3036	align = 4size;
				3037	}
				3038	}
				3039
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3040	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3041	return MCDisassembler::Fail;
				3042	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3043	return MCDisassembler::Fail;
				3044	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3045	return MCDisassembler::Fail;
				3046	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				3047	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3048	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3049	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3050	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3051	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3052
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3053	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3054	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3055	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3056
				3057	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3058	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3059	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3060	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3061	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3062	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3063
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3064	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3065	}
				3066
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3067	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3068	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3069	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3070	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3071
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3072	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3073	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3074	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3075	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3076	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3077	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3078	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3079	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3080
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3081	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3082	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3083	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3084	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3085	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3086	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3087	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3088
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3089	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3090
				3091	switch (Inst.getOpcode()) {
				3092	case ARM::VORRiv4i16:
				3093	case ARM::VORRiv2i32:
				3094	case ARM::VBICiv4i16:
				3095	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3096	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3097	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	break;
				3099	case ARM::VORRiv8i16:
				3100	case ARM::VORRiv4i32:
				3101	case ARM::VBICiv8i16:
				3102	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3103	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3104	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3105	break;
				3106	default:
				3107	break;
				3108	}
				3109
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3110	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3111	}
				3112
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3113	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3114	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3115	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3116
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3117	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3118	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3119	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3120	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3121	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3122
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3123	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3124	return MCDisassembler::Fail;
				3125	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3126	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3127	Inst.addOperand(MCOperand::createImm(8 << size));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3128
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3129	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3130	}
				3131
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3132	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3134	Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3135	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3136	}
				3137
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3138	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3139	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3140	Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3141	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3142	}
				3143
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3144	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3145	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3146	Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3147	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3148	}
				3149
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3150	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3151	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3152	Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3153	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3154	}
				3155
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3156	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3157	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3158	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3159
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3160	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3161	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3162	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3163	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3164	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3165	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3166	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3167
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3168	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3169	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3170	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3171	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3172	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3173	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3174
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3175	switch (Inst.getOpcode()) {
				3176	case ARM::VTBL2:
				3177	case ARM::VTBX2:
				3178	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3179	return MCDisassembler::Fail;
				3180	break;
				3181	default:
				3182	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3183	return MCDisassembler::Fail;
				3184	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3185
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3186	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3187	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3188
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3189	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190	}
				3191
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3192	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3193	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3194	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3195
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3196	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3197	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3198
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3199	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3200	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3201
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3202	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3203	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3204	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3205	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3206	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3207	case ARM::tADDrSPi:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3208	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3209	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3210	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3211
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3212	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3213	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3214	}
				3215
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3216	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3217	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3218	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3219	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3220	Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3221	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3222	}
				3223
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3224	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3225	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3226	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3227	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3228	Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3229	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3230	}
				3231
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3232	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3233	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3234	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3235	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3236	Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3237	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3238	}
				3239
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3240	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3241	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3242	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3243
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3244	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3245	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3246
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3247	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3248	return MCDisassembler::Fail;
				3249	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3250	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3251
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3252	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3253	}
				3254
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3255	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3256	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3257	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3258
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3259	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3260	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3261
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3262	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3263	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3264	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3265
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3266	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3267	}
				3268
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3269	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3270	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3271	unsigned imm = Val << 2;
				3272
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3273	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3274	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3275
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3276	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3277	}
				3278
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3279	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3280	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3281	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3282	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3283
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3284	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3285	}
				3286
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3287	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3288	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3289	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3290
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3291	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3292	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3293	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3294
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3295	// Thumb stores cannot use PC as dest register.
				3296	switch (Inst.getOpcode()) {
				3297	case ARM::t2STRHs:
				3298	case ARM::t2STRBs:
				3299	case ARM::t2STRs:
				3300	if (Rn == 15)
				3301	return MCDisassembler::Fail;
				3302	default:
				3303	break;
				3304	}
				3305
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3306	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3307	return MCDisassembler::Fail;
				3308	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3309	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3310	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3311
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3312	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3313	}
				3314
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3315	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3316	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3317	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3318
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3319	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3320	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3321
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	3322	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3323	.getFeatureBits();
				3324	bool hasMP = featureBits & ARM::FeatureMP;
				3325	bool hasV7Ops = featureBits & ARM::HasV7Ops;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3326
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3327	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3328	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3329	case ARM::t2LDRBs:
				3330	Inst.setOpcode(ARM::t2LDRBpci);
				3331	break;
				3332	case ARM::t2LDRHs:
				3333	Inst.setOpcode(ARM::t2LDRHpci);
				3334	break;
				3335	case ARM::t2LDRSHs:
				3336	Inst.setOpcode(ARM::t2LDRSHpci);
				3337	break;
				3338	case ARM::t2LDRSBs:
				3339	Inst.setOpcode(ARM::t2LDRSBpci);
				3340	break;
				3341	case ARM::t2LDRs:
				3342	Inst.setOpcode(ARM::t2LDRpci);
				3343	break;
				3344	case ARM::t2PLDs:
				3345	Inst.setOpcode(ARM::t2PLDpci);
				3346	break;
				3347	case ARM::t2PLIs:
				3348	Inst.setOpcode(ARM::t2PLIpci);
				3349	break;
				3350	default:
				3351	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3352	}
				3353
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3354	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3355	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3356
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3357	if (Rt == 15) {
				3358	switch (Inst.getOpcode()) {
				3359	case ARM::t2LDRSHs:
				3360	return MCDisassembler::Fail;
				3361	case ARM::t2LDRHs:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3362	Inst.setOpcode(ARM::t2PLDWs);
				3363	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3364	case ARM::t2LDRSBs:
				3365	Inst.setOpcode(ARM::t2PLIs);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3366	default:
				3367	break;
				3368	}
				3369	}
				3370
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3371	switch (Inst.getOpcode()) {
				3372	case ARM::t2PLDs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3373	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3374	case ARM::t2PLIs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3375	if (!hasV7Ops)
				3376	return MCDisassembler::Fail;
				3377	break;
				3378	case ARM::t2PLDWs:
				3379	if (!hasV7Ops \|\| !hasMP)
				3380	return MCDisassembler::Fail;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3381	break;
				3382	default:
				3383	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3384	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3385	}
				3386
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3387	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3388	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3389	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3390	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3391	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3392
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3393	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3394	}
				3395
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3396	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3397	uint64_t Address, const void* Decoder) {
				3398	DecodeStatus S = MCDisassembler::Success;
				3399
				3400	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3401	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3402	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3403	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3404	imm \|= (U << 8);
				3405	imm \|= (Rn << 9);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3406	unsigned add = fieldFromInstruction(Insn, 9, 1);
				3407
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	3408	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3409	.getFeatureBits();
				3410	bool hasMP = featureBits & ARM::FeatureMP;
				3411	bool hasV7Ops = featureBits & ARM::HasV7Ops;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3412
				3413	if (Rn == 15) {
				3414	switch (Inst.getOpcode()) {
				3415	case ARM::t2LDRi8:
				3416	Inst.setOpcode(ARM::t2LDRpci);
				3417	break;
				3418	case ARM::t2LDRBi8:
				3419	Inst.setOpcode(ARM::t2LDRBpci);
				3420	break;
				3421	case ARM::t2LDRSBi8:
				3422	Inst.setOpcode(ARM::t2LDRSBpci);
				3423	break;
				3424	case ARM::t2LDRHi8:
				3425	Inst.setOpcode(ARM::t2LDRHpci);
				3426	break;
				3427	case ARM::t2LDRSHi8:
				3428	Inst.setOpcode(ARM::t2LDRSHpci);
				3429	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3430	case ARM::t2PLDi8:
				3431	Inst.setOpcode(ARM::t2PLDpci);
				3432	break;
				3433	case ARM::t2PLIi8:
				3434	Inst.setOpcode(ARM::t2PLIpci);
				3435	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3436	default:
				3437	return MCDisassembler::Fail;
				3438	}
				3439	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3440	}
				3441
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3442	if (Rt == 15) {
				3443	switch (Inst.getOpcode()) {
				3444	case ARM::t2LDRSHi8:
				3445	return MCDisassembler::Fail;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3446	case ARM::t2LDRHi8:
				3447	if (!add)
				3448	Inst.setOpcode(ARM::t2PLDWi8);
				3449	break;
				3450	case ARM::t2LDRSBi8:
				3451	Inst.setOpcode(ARM::t2PLIi8);
				3452	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3453	default:
				3454	break;
				3455	}
				3456	}
				3457
				3458	switch (Inst.getOpcode()) {
				3459	case ARM::t2PLDi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3460	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3461	case ARM::t2PLIi8:
				3462	if (!hasV7Ops)
				3463	return MCDisassembler::Fail;
				3464	break;
				3465	case ARM::t2PLDWi8:
				3466	if (!hasV7Ops \|\| !hasMP)
				3467	return MCDisassembler::Fail;
				3468	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3469	default:
				3470	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3471	return MCDisassembler::Fail;
				3472	}
				3473
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3474	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3475	return MCDisassembler::Fail;
				3476	return S;
				3477	}
				3478
				3479	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3480	uint64_t Address, const void* Decoder) {
				3481	DecodeStatus S = MCDisassembler::Success;
				3482
				3483	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3484	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3485	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3486	imm \|= (Rn << 13);
				3487
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	3488	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3489	.getFeatureBits();
				3490	bool hasMP = (featureBits & ARM::FeatureMP);
				3491	bool hasV7Ops = (featureBits & ARM::HasV7Ops);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3492
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3493	if (Rn == 15) {
				3494	switch (Inst.getOpcode()) {
				3495	case ARM::t2LDRi12:
				3496	Inst.setOpcode(ARM::t2LDRpci);
				3497	break;
				3498	case ARM::t2LDRHi12:
				3499	Inst.setOpcode(ARM::t2LDRHpci);
				3500	break;
				3501	case ARM::t2LDRSHi12:
				3502	Inst.setOpcode(ARM::t2LDRSHpci);
				3503	break;
				3504	case ARM::t2LDRBi12:
				3505	Inst.setOpcode(ARM::t2LDRBpci);
				3506	break;
				3507	case ARM::t2LDRSBi12:
				3508	Inst.setOpcode(ARM::t2LDRSBpci);
				3509	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3510	case ARM::t2PLDi12:
				3511	Inst.setOpcode(ARM::t2PLDpci);
				3512	break;
				3513	case ARM::t2PLIi12:
				3514	Inst.setOpcode(ARM::t2PLIpci);
				3515	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3516	default:
				3517	return MCDisassembler::Fail;
				3518	}
				3519	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3520	}
				3521
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3522	if (Rt == 15) {
				3523	switch (Inst.getOpcode()) {
				3524	case ARM::t2LDRSHi12:
				3525	return MCDisassembler::Fail;
				3526	case ARM::t2LDRHi12:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3527	Inst.setOpcode(ARM::t2PLDWi12);
				3528	break;
				3529	case ARM::t2LDRSBi12:
				3530	Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3531	break;
				3532	default:
				3533	break;
				3534	}
				3535	}
				3536
				3537	switch (Inst.getOpcode()) {
				3538	case ARM::t2PLDi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3539	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3540	case ARM::t2PLIi12:
				3541	if (!hasV7Ops)
				3542	return MCDisassembler::Fail;
				3543	break;
				3544	case ARM::t2PLDWi12:
				3545	if (!hasV7Ops \|\| !hasMP)
				3546	return MCDisassembler::Fail;
				3547	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3548	default:
				3549	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3550	return MCDisassembler::Fail;
				3551	}
				3552
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3553	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3554	return MCDisassembler::Fail;
				3555	return S;
				3556	}
				3557
				3558	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3559	uint64_t Address, const void* Decoder) {
				3560	DecodeStatus S = MCDisassembler::Success;
				3561
				3562	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3563	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3564	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3565	imm \|= (Rn << 9);
				3566
				3567	if (Rn == 15) {
				3568	switch (Inst.getOpcode()) {
				3569	case ARM::t2LDRT:
				3570	Inst.setOpcode(ARM::t2LDRpci);
				3571	break;
				3572	case ARM::t2LDRBT:
				3573	Inst.setOpcode(ARM::t2LDRBpci);
				3574	break;
				3575	case ARM::t2LDRHT:
				3576	Inst.setOpcode(ARM::t2LDRHpci);
				3577	break;
				3578	case ARM::t2LDRSBT:
				3579	Inst.setOpcode(ARM::t2LDRSBpci);
				3580	break;
				3581	case ARM::t2LDRSHT:
				3582	Inst.setOpcode(ARM::t2LDRSHpci);
				3583	break;
				3584	default:
				3585	return MCDisassembler::Fail;
				3586	}
				3587	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3588	}
				3589
				3590	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3591	return MCDisassembler::Fail;
				3592	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3593	return MCDisassembler::Fail;
				3594	return S;
				3595	}
				3596
				3597	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3598	uint64_t Address, const void* Decoder) {
				3599	DecodeStatus S = MCDisassembler::Success;
				3600
				3601	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3602	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3603	int imm = fieldFromInstruction(Insn, 0, 12);
				3604
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	3605	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3606	.getFeatureBits();
				3607	bool hasV7Ops = (featureBits & ARM::HasV7Ops);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3608
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3609	if (Rt == 15) {
				3610	switch (Inst.getOpcode()) {
				3611	case ARM::t2LDRBpci:
				3612	case ARM::t2LDRHpci:
				3613	Inst.setOpcode(ARM::t2PLDpci);
				3614	break;
				3615	case ARM::t2LDRSBpci:
				3616	Inst.setOpcode(ARM::t2PLIpci);
				3617	break;
				3618	case ARM::t2LDRSHpci:
				3619	return MCDisassembler::Fail;
				3620	default:
				3621	break;
				3622	}
				3623	}
				3624
				3625	switch(Inst.getOpcode()) {
				3626	case ARM::t2PLDpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3627	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3628	case ARM::t2PLIpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3629	if (!hasV7Ops)
				3630	return MCDisassembler::Fail;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3631	break;
				3632	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3633	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3634	return MCDisassembler::Fail;
				3635	}
				3636
				3637	if (!U) {
				3638	// Special case for #-0.
				3639	if (imm == 0)
				3640	imm = INT32_MIN;
				3641	else
				3642	imm = -imm;
				3643	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3644	Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3645
				3646	return S;
				3647	}
				3648
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3649	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3650	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3651	if (Val == 0)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3652	Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3653	else {
				3654	int imm = Val & 0xFF;
				3655
				3656	if (!(Val & 0x100)) imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3657	Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3658	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3659
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3660	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3661	}
				3662
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3663	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3664	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3665	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3666
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3667	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3668	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3669
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3670	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3671	return MCDisassembler::Fail;
				3672	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3673	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3674
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3675	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3676	}
				3677
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3678	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3679	uint64_t Address, const void *Decoder) {
				3680	DecodeStatus S = MCDisassembler::Success;
				3681
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3682	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3683	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3684
				3685	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3686	return MCDisassembler::Fail;
				3687
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3688	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3689
				3690	return S;
				3691	}
				3692
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3693	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3694	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3695	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3696	if (Val == 0)
				3697	imm = INT32_MIN;
				3698	else if (!(Val & 0x100))
				3699	imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3700	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3701
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3702	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3703	}
				3704
				3705
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3706	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3707	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3708	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3709
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3710	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3711	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3712
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3713	// Thumb stores cannot use PC as dest register.
				3714	switch (Inst.getOpcode()) {
				3715	case ARM::t2STRT:
				3716	case ARM::t2STRBT:
				3717	case ARM::t2STRHT:
				3718	case ARM::t2STRi8:
				3719	case ARM::t2STRHi8:
				3720	case ARM::t2STRBi8:
				3721	if (Rn == 15)
				3722	return MCDisassembler::Fail;
				3723	break;
				3724	default:
				3725	break;
				3726	}
				3727
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3728	// Some instructions always use an additive offset.
				3729	switch (Inst.getOpcode()) {
				3730	case ARM::t2LDRT:
				3731	case ARM::t2LDRBT:
				3732	case ARM::t2LDRHT:
				3733	case ARM::t2LDRSBT:
				3734	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3735	case ARM::t2STRT:
				3736	case ARM::t2STRBT:
				3737	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3738	imm \|= 0x100;
				3739	break;
				3740	default:
				3741	break;
				3742	}
				3743
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3744	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3745	return MCDisassembler::Fail;
				3746	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3747	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3748
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3749	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3750	}
				3751
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3752	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3753	uint64_t Address, const void *Decoder) {
				3754	DecodeStatus S = MCDisassembler::Success;
				3755
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3756	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3757	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3758	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3759	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3760	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3761	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3762
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3763	if (Rn == 15) {
				3764	switch (Inst.getOpcode()) {
				3765	case ARM::t2LDR_PRE:
				3766	case ARM::t2LDR_POST:
				3767	Inst.setOpcode(ARM::t2LDRpci);
				3768	break;
				3769	case ARM::t2LDRB_PRE:
				3770	case ARM::t2LDRB_POST:
				3771	Inst.setOpcode(ARM::t2LDRBpci);
				3772	break;
				3773	case ARM::t2LDRH_PRE:
				3774	case ARM::t2LDRH_POST:
				3775	Inst.setOpcode(ARM::t2LDRHpci);
				3776	break;
				3777	case ARM::t2LDRSB_PRE:
				3778	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3779	if (Rt == 15)
				3780	Inst.setOpcode(ARM::t2PLIpci);
				3781	else
				3782	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3783	break;
				3784	case ARM::t2LDRSH_PRE:
				3785	case ARM::t2LDRSH_POST:
				3786	Inst.setOpcode(ARM::t2LDRSHpci);
				3787	break;
				3788	default:
				3789	return MCDisassembler::Fail;
				3790	}
				3791	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3792	}
				3793
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3794	if (!load) {
				3795	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3796	return MCDisassembler::Fail;
				3797	}
				3798
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3799	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3800	return MCDisassembler::Fail;
				3801
				3802	if (load) {
				3803	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3804	return MCDisassembler::Fail;
				3805	}
				3806
				3807	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3808	return MCDisassembler::Fail;
				3809
				3810	return S;
				3811	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3812
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3813	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3814	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3815	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3816
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3817	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3818	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3819
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3820	// Thumb stores cannot use PC as dest register.
				3821	switch (Inst.getOpcode()) {
				3822	case ARM::t2STRi12:
				3823	case ARM::t2STRBi12:
				3824	case ARM::t2STRHi12:
				3825	if (Rn == 15)
				3826	return MCDisassembler::Fail;
				3827	default:
				3828	break;
				3829	}
				3830
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3831	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3832	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3833	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3834
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3835	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3836	}
				3837
				3838
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3839	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3840	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3841	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3842
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3843	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3844	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3845	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3846
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3847	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3848	}
				3849
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3850	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3851	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3852	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3853
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3854	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3855	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3856	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3857
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3858	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3859	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3860	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3861	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3862	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3863	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3864	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3865
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3866	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3867	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3868	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3870	}
				3871
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3872	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3873	}
				3874
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3875	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3876	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3877	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3878	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3879
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3880	Inst.addOperand(MCOperand::createImm(imod));
				3881	Inst.addOperand(MCOperand::createImm(flags));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3882
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3883	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3884	}
				3885
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3886	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3887	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3888	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3889	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3890	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3891
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3892	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3893	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3894	Inst.addOperand(MCOperand::createImm(add));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3895
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3896	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3897	}
				3898
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3899	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3900	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3901	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3902	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3903	// the encoded instruction. So here change to I1 and I2 values via:
				3904	// I1 = NOT(J1 EOR S);
				3905	// I2 = NOT(J2 EOR S);
				3906	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3907	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3908	unsigned S = (Val >> 23) & 1;
				3909	unsigned J1 = (Val >> 22) & 1;
				3910	unsigned J2 = (Val >> 21) & 1;
				3911	unsigned I1 = !(J1 ^ S);
				3912	unsigned I2 = !(J2 ^ S);
				3913	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3914	int imm32 = SignExtend32<25>(tmp << 1);
				3915
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3916	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3917	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3918	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3919	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3920	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3921	}
				3922
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3923	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3924	uint64_t Address, const void *Decoder) {
				3925	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3926	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3927
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	3928	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3929	.getFeatureBits();
				3930	if ((featureBits & ARM::HasV8Ops) && !(Val == 14 \|\| Val == 15))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3931	return MCDisassembler::Fail;
				3932
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	3933	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3934	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3935	}
				3936
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3937	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3938	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3939	uint64_t Address, const void *Decoder) {
				3940	DecodeStatus S = MCDisassembler::Success;
				3941
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3942	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3943	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3944
				3945	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3946	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3947	return MCDisassembler::Fail;
				3948	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3949	return MCDisassembler::Fail;
				3950	return S;
				3951	}
				3952
				3953	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3954	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3955	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3956	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3957
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3958	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3959	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3960	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3961	switch (opc) {
				3962	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3963	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3964	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3965	Inst.setOpcode(ARM::t2DSB);
				3966	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3967	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3968	Inst.setOpcode(ARM::t2DMB);
				3969	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3970	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3971	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3972	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3973	}
				3974
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3975	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3976	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3977	}
				3978
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3979	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3980	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3981	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3982	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3983	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3984
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3985	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3986	return MCDisassembler::Fail;
				3987	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3988	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3989
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3990	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3991	}
				3992
				3993	// Decode a shifted immediate operand. These basically consist
				3994	// of an 8-bit value, and a 4-bit directive that specifies either
				3995	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3996	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3997	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3998	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3999	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4000	unsigned byte = fieldFromInstruction(Val, 8, 2);
				4001	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4002	switch (byte) {
				4003	case 0:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4004	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4005	break;
				4006	case 1:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4007	Inst.addOperand(MCOperand::createImm((imm << 16) \| imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4008	break;
				4009	case 2:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4010	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 8)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4011	break;
				4012	case 3:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4013	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 16) \|
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4014	(imm << 8) \| imm));
				4015	break;
				4016	}
				4017	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4018	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				4019	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4020	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4021	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4022	}
				4023
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4024	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4025	}
				4026
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4027	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4028	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4029	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4030	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	4031	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4032	Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4033	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4034	}
				4035
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4036	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	4037	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4038	// Val is passed in as S:J1:J2:imm10:imm11
				4039	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				4040	// the encoded instruction. So here change to I1 and I2 values via:
				4041	// I1 = NOT(J1 EOR S);
				4042	// I2 = NOT(J2 EOR S);
				4043	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	4044	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4045	unsigned S = (Val >> 23) & 1;
				4046	unsigned J1 = (Val >> 22) & 1;
				4047	unsigned J2 = (Val >> 21) & 1;
				4048	unsigned I1 = !(J1 ^ S);
				4049	unsigned I2 = !(J2 ^ S);
				4050	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				4051	int imm32 = SignExtend32<25>(tmp << 1);
				4052
				4053	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	4054	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4055	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4056	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4057	}
				4058
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4059	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4060	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	4061	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4062	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4063
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4064	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4065	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4066	}
				4067
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4068	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				4069	uint64_t Address, const void *Decoder) {
				4070	if (Val & ~0xf)
				4071	return MCDisassembler::Fail;
				4072
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4073	Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4074	return MCDisassembler::Success;
				4075	}
				4076
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4077	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4078	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4079	DecodeStatus S = MCDisassembler::Success;
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	4080	uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				4081	.getFeatureBits();
				4082	if (FeatureBits & ARM::FeatureMClass) {
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4083	unsigned ValLow = Val & 0xff;
				4084
				4085	// Validate the SYSm value first.
				4086	switch (ValLow) {
				4087	case 0: // apsr
				4088	case 1: // iapsr
				4089	case 2: // eapsr
				4090	case 3: // xpsr
				4091	case 5: // ipsr
				4092	case 6: // epsr
				4093	case 7: // iepsr
				4094	case 8: // msp
				4095	case 9: // psp
				4096	case 16: // primask
				4097	case 20: // control
				4098	break;
				4099	case 17: // basepri
				4100	case 18: // basepri_max
				4101	case 19: // faultmask
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	4102	if (!(FeatureBits & ARM::HasV7Ops))
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4103	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4104	return MCDisassembler::Fail;
				4105	break;
				4106	default:
				4107	return MCDisassembler::Fail;
				4108	}
				4109
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4110	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4111	unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	4112	if (!(FeatureBits & ARM::HasV7Ops)) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4113	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4114	// unpredictable.
				4115	if (Mask != 2)
				4116	S = MCDisassembler::SoftFail;
				4117	}
				4118	else {
				4119	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4120	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4121	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4122	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4123	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4124	// only if the processor includes the DSP extension.
				4125	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
Michael Kuperstein	c3434b3	2015-05-13 10:28:46 +0000	[diff] [blame]	4126	(!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4127	S = MCDisassembler::SoftFail;
				4128	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4129	}
				4130	} else {
				4131	// A/R class
				4132	if (Val == 0)
				4133	return MCDisassembler::Fail;
				4134	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4135	Inst.addOperand(MCOperand::createImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4136	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4137	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4138
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4139	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4140	uint64_t Address, const void *Decoder) {
				4141
				4142	unsigned R = fieldFromInstruction(Val, 5, 1);
				4143	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4144
				4145	// The table of encodings for these banked registers comes from B9.2.3 of the
				4146	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4147	// neater. So by fiat, these values are UNPREDICTABLE:
				4148	if (!R) {
				4149	if (SysM == 0x7 \|\| SysM == 0xf \|\| SysM == 0x18 \|\| SysM == 0x19 \|\|
				4150	SysM == 0x1a \|\| SysM == 0x1b)
				4151	return MCDisassembler::SoftFail;
				4152	} else {
				4153	if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
				4154	SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
				4155	return MCDisassembler::SoftFail;
				4156	}
				4157
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4158	Inst.addOperand(MCOperand::createImm(Val));
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4159	return MCDisassembler::Success;
				4160	}
				4161
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4162	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4163	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4164	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4165
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4166	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4167	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4168	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4169
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4170	if (Rn == 0xF)
				4171	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4172
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4173	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4174	return MCDisassembler::Fail;
				4175	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4176	return MCDisassembler::Fail;
				4177	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4178	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4179
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4180	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4181	}
				4182
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4183	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4184	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4185	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4186
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4187	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4188	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4189	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4190	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4191
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4192	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4193	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4194
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4195	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4196	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4197
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4198	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4199	return MCDisassembler::Fail;
				4200	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4201	return MCDisassembler::Fail;
				4202	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4203	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4205	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4206	}
				4207
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4208	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4209	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4210	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4211
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4212	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4213	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4214	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4215	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4216	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4217	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4218
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4219	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4220
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4221	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4222	return MCDisassembler::Fail;
				4223	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4224	return MCDisassembler::Fail;
				4225	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4226	return MCDisassembler::Fail;
				4227	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4228	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4229
				4230	return S;
				4231	}
				4232
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4233	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4234	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4235	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4236
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4237	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4238	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4239	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4240	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4241	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4242	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4243	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4244
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4245	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4246	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4247
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4248	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4249	return MCDisassembler::Fail;
				4250	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4251	return MCDisassembler::Fail;
				4252	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4253	return MCDisassembler::Fail;
				4254	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4255	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4256
				4257	return S;
				4258	}
				4259
				4260
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4261	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4262	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4263	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4264
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4265	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4266	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4267	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4268	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4269	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4270	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4271
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4272	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4273
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4274	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4275	return MCDisassembler::Fail;
				4276	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4277	return MCDisassembler::Fail;
				4278	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4279	return MCDisassembler::Fail;
				4280	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4281	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4282
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4283	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4284	}
				4285
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4286	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4287	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4288	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4289
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4290	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4291	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4292	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4293	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4294	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4295	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4296
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4297	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4298
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4299	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4300	return MCDisassembler::Fail;
				4301	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4302	return MCDisassembler::Fail;
				4303	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4304	return MCDisassembler::Fail;
				4305	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4306	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4307
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4308	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4309	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4310
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4311	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4312	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4313	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4314
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4315	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4316	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4317	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4318	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4319	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4320
				4321	unsigned align = 0;
				4322	unsigned index = 0;
				4323	switch (size) {
				4324	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4325	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4326	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4327	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4328	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4329	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4330	break;
				4331	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4332	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4333	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4334	index = fieldFromInstruction(Insn, 6, 2);
				4335	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4336	align = 2;
				4337	break;
				4338	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4339	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4340	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4341	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4342
				4343	switch (fieldFromInstruction(Insn, 4, 2)) {
				4344	case 0 :
				4345	align = 0; break;
				4346	case 3:
				4347	align = 4; break;
				4348	default:
				4349	return MCDisassembler::Fail;
				4350	}
				4351	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4352	}
				4353
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4354	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4355	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4356	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4357	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4358	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4359	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4360	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4361	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4362	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4363	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4364	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4365	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4366	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4367	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4368	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4369	}
				4370
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4371	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4372	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4373	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4374
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4375	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4376	}
				4377
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4378	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4379	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4380	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4381
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4382	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4383	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4384	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4385	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4386	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4387
				4388	unsigned align = 0;
				4389	unsigned index = 0;
				4390	switch (size) {
				4391	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4392	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4393	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4394	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4395	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4396	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4397	break;
				4398	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4399	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4400	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4401	index = fieldFromInstruction(Insn, 6, 2);
				4402	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4403	align = 2;
				4404	break;
				4405	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4406	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4407	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4408	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4409
				4410	switch (fieldFromInstruction(Insn, 4, 2)) {
				4411	case 0:
				4412	align = 0; break;
				4413	case 3:
				4414	align = 4; break;
				4415	default:
				4416	return MCDisassembler::Fail;
				4417	}
				4418	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4419	}
				4420
				4421	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4422	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4423	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4424	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4425	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4426	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4427	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4428	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4429	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4430	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4431	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4432	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4433	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4434	}
				4435
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4436	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4437	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4438	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4439
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4440	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4441	}
				4442
				4443
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4444	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4445	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4446	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4447
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4448	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4449	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4450	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4451	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4452	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4453
				4454	unsigned align = 0;
				4455	unsigned index = 0;
				4456	unsigned inc = 1;
				4457	switch (size) {
				4458	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4459	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4460	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4461	index = fieldFromInstruction(Insn, 5, 3);
				4462	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4463	align = 2;
				4464	break;
				4465	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4466	index = fieldFromInstruction(Insn, 6, 2);
				4467	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4468	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4469	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4470	inc = 2;
				4471	break;
				4472	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4473	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4474	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4475	index = fieldFromInstruction(Insn, 7, 1);
				4476	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4477	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4478	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4479	inc = 2;
				4480	break;
				4481	}
				4482
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4483	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4484	return MCDisassembler::Fail;
				4485	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4486	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4487	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4489	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4490	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4491	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4492	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4493	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4494	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4495	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4496	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4497	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4498	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4499	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4500	}
				4501
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4502	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4503	return MCDisassembler::Fail;
				4504	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4505	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4506	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4507
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4508	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4509	}
				4510
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4511	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4512	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4513	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4514
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4515	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4516	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4517	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4518	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4519	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4520
				4521	unsigned align = 0;
				4522	unsigned index = 0;
				4523	unsigned inc = 1;
				4524	switch (size) {
				4525	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4526	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4527	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4528	index = fieldFromInstruction(Insn, 5, 3);
				4529	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4530	align = 2;
				4531	break;
				4532	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4533	index = fieldFromInstruction(Insn, 6, 2);
				4534	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4535	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4536	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4537	inc = 2;
				4538	break;
				4539	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4540	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4541	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4542	index = fieldFromInstruction(Insn, 7, 1);
				4543	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4544	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4545	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4546	inc = 2;
				4547	break;
				4548	}
				4549
				4550	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4551	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4552	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4553	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4554	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4555	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4556	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4557	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4558	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4559	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4560	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4561	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4562	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4563	}
				4564
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4565	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4566	return MCDisassembler::Fail;
				4567	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4568	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4569	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4570
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4571	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4572	}
				4573
				4574
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4575	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4576	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4577	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4578
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4579	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4580	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4581	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4582	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4583	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4584
				4585	unsigned align = 0;
				4586	unsigned index = 0;
				4587	unsigned inc = 1;
				4588	switch (size) {
				4589	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4590	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4591	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4592	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4593	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4594	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4595	break;
				4596	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4597	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4598	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4599	index = fieldFromInstruction(Insn, 6, 2);
				4600	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4601	inc = 2;
				4602	break;
				4603	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4604	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4605	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4606	index = fieldFromInstruction(Insn, 7, 1);
				4607	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4608	inc = 2;
				4609	break;
				4610	}
				4611
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4612	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4613	return MCDisassembler::Fail;
				4614	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4615	return MCDisassembler::Fail;
				4616	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4617	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4618
				4619	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4620	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4621	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4622	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4623	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4624	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4625	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4626	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4627	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4628	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4629	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4630	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4631	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4632	}
				4633
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4634	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4635	return MCDisassembler::Fail;
				4636	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4637	return MCDisassembler::Fail;
				4638	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4639	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4640	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4641
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4642	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4643	}
				4644
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4645	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4646	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4647	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4648
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4649	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4650	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4651	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4652	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4653	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4654
				4655	unsigned align = 0;
				4656	unsigned index = 0;
				4657	unsigned inc = 1;
				4658	switch (size) {
				4659	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4660	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4661	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4662	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4663	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4664	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4665	break;
				4666	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4667	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4668	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4669	index = fieldFromInstruction(Insn, 6, 2);
				4670	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4671	inc = 2;
				4672	break;
				4673	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4674	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4675	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4676	index = fieldFromInstruction(Insn, 7, 1);
				4677	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4678	inc = 2;
				4679	break;
				4680	}
				4681
				4682	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4683	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4684	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4685	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4686	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4687	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4688	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4689	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4690	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4691	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4692	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4693	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4694	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4695	}
				4696
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4697	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4698	return MCDisassembler::Fail;
				4699	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4700	return MCDisassembler::Fail;
				4701	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4702	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4703	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4704
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4705	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4706	}
				4707
				4708
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4709	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4710	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4711	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4712
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4713	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4714	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4715	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4716	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4717	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4718
				4719	unsigned align = 0;
				4720	unsigned index = 0;
				4721	unsigned inc = 1;
				4722	switch (size) {
				4723	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4724	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4725	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4726	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4727	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4728	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4729	break;
				4730	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4731	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4732	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4733	index = fieldFromInstruction(Insn, 6, 2);
				4734	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4735	inc = 2;
				4736	break;
				4737	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4738	switch (fieldFromInstruction(Insn, 4, 2)) {
				4739	case 0:
				4740	align = 0; break;
				4741	case 3:
				4742	return MCDisassembler::Fail;
				4743	default:
				4744	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4745	}
				4746
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4747	index = fieldFromInstruction(Insn, 7, 1);
				4748	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4749	inc = 2;
				4750	break;
				4751	}
				4752
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4753	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4754	return MCDisassembler::Fail;
				4755	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4756	return MCDisassembler::Fail;
				4757	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4758	return MCDisassembler::Fail;
				4759	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4760	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4761
				4762	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4763	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4764	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4765	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4766	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4767	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4768	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4769	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4770	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4771	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4772	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4773	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4774	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4775	}
				4776
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4777	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4778	return MCDisassembler::Fail;
				4779	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4780	return MCDisassembler::Fail;
				4781	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4782	return MCDisassembler::Fail;
				4783	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4784	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4785	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4786
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4787	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4788	}
				4789
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4790	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4791	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4792	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4793
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4794	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4795	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4796	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4797	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4798	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4799
				4800	unsigned align = 0;
				4801	unsigned index = 0;
				4802	unsigned inc = 1;
				4803	switch (size) {
				4804	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4805	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4806	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4807	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4808	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4809	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4810	break;
				4811	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4812	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4813	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4814	index = fieldFromInstruction(Insn, 6, 2);
				4815	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4816	inc = 2;
				4817	break;
				4818	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4819	switch (fieldFromInstruction(Insn, 4, 2)) {
				4820	case 0:
				4821	align = 0; break;
				4822	case 3:
				4823	return MCDisassembler::Fail;
				4824	default:
				4825	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4826	}
				4827
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4828	index = fieldFromInstruction(Insn, 7, 1);
				4829	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4830	inc = 2;
				4831	break;
				4832	}
				4833
				4834	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4835	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4836	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4837	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4838	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4839	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4840	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4841	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4842	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4843	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4844	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4845	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4846	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4847	}
				4848
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4849	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4850	return MCDisassembler::Fail;
				4851	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4852	return MCDisassembler::Fail;
				4853	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4854	return MCDisassembler::Fail;
				4855	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4856	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4857	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4858
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4859	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4860	}
				4861
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4862	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4863	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4864	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4865	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4866	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4867	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4868	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4869	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4870
				4871	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4872	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4873
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4874	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4875	return MCDisassembler::Fail;
				4876	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4877	return MCDisassembler::Fail;
				4878	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4879	return MCDisassembler::Fail;
				4880	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4881	return MCDisassembler::Fail;
				4882	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4883	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4884
				4885	return S;
				4886	}
				4887
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4888	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4889	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4890	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4891	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4892	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4893	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4894	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4895	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4896
				4897	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4898	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4899
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4900	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4901	return MCDisassembler::Fail;
				4902	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4903	return MCDisassembler::Fail;
				4904	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4905	return MCDisassembler::Fail;
				4906	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4907	return MCDisassembler::Fail;
				4908	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4909	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4910
				4911	return S;
				4912	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4913
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4914	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4915	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4916	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4917	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4918	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4919
				4920	if (pred == 0xF) {
				4921	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4922	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4923	}
				4924
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4925	if (mask == 0x0)
				4926	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4927
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	4928	Inst.addOperand(MCOperand::createImm(pred));
				4929	Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4930	return S;
				4931	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4932
				4933	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4934	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4935	uint64_t Address, const void *Decoder) {
				4936	DecodeStatus S = MCDisassembler::Success;
				4937
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4938	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4939	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4940	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4941	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4942	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4943	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4944	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4945	bool writeback = (W == 1) \| (P == 0);
				4946
				4947	addr \|= (U << 8) \| (Rn << 9);
				4948
				4949	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4950	Check(S, MCDisassembler::SoftFail);
				4951	if (Rt == Rt2)
				4952	Check(S, MCDisassembler::SoftFail);
				4953
				4954	// Rt
				4955	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4956	return MCDisassembler::Fail;
				4957	// Rt2
				4958	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4959	return MCDisassembler::Fail;
				4960	// Writeback operand
				4961	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4962	return MCDisassembler::Fail;
				4963	// addr
				4964	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4965	return MCDisassembler::Fail;
				4966
				4967	return S;
				4968	}
				4969
				4970	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4971	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4972	uint64_t Address, const void *Decoder) {
				4973	DecodeStatus S = MCDisassembler::Success;
				4974
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4975	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4976	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4977	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4978	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4979	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4980	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4981	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4982	bool writeback = (W == 1) \| (P == 0);
				4983
				4984	addr \|= (U << 8) \| (Rn << 9);
				4985
				4986	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4987	Check(S, MCDisassembler::SoftFail);
				4988
				4989	// Writeback operand
				4990	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4991	return MCDisassembler::Fail;
				4992	// Rt
				4993	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4994	return MCDisassembler::Fail;
				4995	// Rt2
				4996	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4997	return MCDisassembler::Fail;
				4998	// addr
				4999	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5000	return MCDisassembler::Fail;
				5001
				5002	return S;
				5003	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5004
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5005	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5006	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5007	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				5008	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5009	if (sign1 != sign2) return MCDisassembler::Fail;
				5010
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5011	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				5012	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				5013	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5014	Val \|= sign1 << 12;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5015	Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5016
				5017	return MCDisassembler::Success;
				5018	}
				5019
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5020	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5021	uint64_t Address,
				5022	const void *Decoder) {
				5023	DecodeStatus S = MCDisassembler::Success;
				5024
				5025	// Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith	3131e85	2015-01-19 16:37:17 +0000	[diff] [blame]	5026	if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5027	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5028	return S;
				5029	}
				5030
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5031	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5032	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5033	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5034	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				5035	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5036	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5037
				5038	if (pred == 0xF)
				5039	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				5040
				5041	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	5042
				5043	if (Rt == Rn \|\| Rn == Rt2)
				5044	S = MCDisassembler::SoftFail;
				5045
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5046	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5047	return MCDisassembler::Fail;
				5048	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5049	return MCDisassembler::Fail;
				5050	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5051	return MCDisassembler::Fail;
				5052	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5053	return MCDisassembler::Fail;
				5054
				5055	return S;
				5056	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5057
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5058	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5059	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5060	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5061	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5062	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5063	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5064	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5065	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5066	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5067
				5068	DecodeStatus S = MCDisassembler::Success;
				5069
				5070	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	5071	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5072	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5073	Inst.setOpcode(ARM::VMOVv2f32);
				5074	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5075	}
				5076
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5077	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5078
				5079	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				5080	return MCDisassembler::Fail;
				5081	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5082	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5083	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5084
				5085	return S;
				5086	}
				5087
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5088	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5089	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5090	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5091	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5092	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5093	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5094	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5095	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5096	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5097
				5098	DecodeStatus S = MCDisassembler::Success;
				5099
				5100	// VMOVv4f32 is ambiguous with these decodings.
				5101	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5102	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5103	Inst.setOpcode(ARM::VMOVv4f32);
				5104	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5105	}
				5106
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5107	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5108
				5109	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5110	return MCDisassembler::Fail;
				5111	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5112	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5113	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5114
				5115	return S;
				5116	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5117
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5118	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5119	uint64_t Address, const void *Decoder) {
				5120	DecodeStatus S = MCDisassembler::Success;
				5121
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5122	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5123	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5124	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5125	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5126	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5127
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5128	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5129	S = MCDisassembler::SoftFail;
				5130
				5131	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5132	return MCDisassembler::Fail;
				5133	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5134	return MCDisassembler::Fail;
				5135	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5136	return MCDisassembler::Fail;
				5137	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5138	return MCDisassembler::Fail;
				5139	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5140	return MCDisassembler::Fail;
				5141
				5142	return S;
				5143	}
				5144
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5145	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				5146	uint64_t Address, const void *Decoder) {
				5147
				5148	DecodeStatus S = MCDisassembler::Success;
				5149
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5150	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5151	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5152	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5153	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5154	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5155
				5156	if ((cop & ~0x1) == 0xa)
				5157	return MCDisassembler::Fail;
				5158
				5159	if (Rt == Rt2)
				5160	S = MCDisassembler::SoftFail;
				5161
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5162	Inst.addOperand(MCOperand::createImm(cop));
				5163	Inst.addOperand(MCOperand::createImm(opc1));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5164	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5165	return MCDisassembler::Fail;
				5166	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5167	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame^]	5168	Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5169
				5170	return S;
				5171	}
				5172