| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// | 
|  | 2 | // | 
|  | 3 | //                     The LLVM Compiler Infrastructure | 
|  | 4 | // | 
|  | 5 | // This file was developed by the LLVM research group and is distributed under | 
|  | 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. | 
|  | 7 | // | 
|  | 8 | //===----------------------------------------------------------------------===// | 
|  | 9 | // | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 10 | // This file implements the VirtRegMap class. | 
|  | 11 | // | 
|  | 12 | // It also contains implementations of the the Spiller interface, which, given a | 
|  | 13 | // virtual register map and a machine function, eliminates all virtual | 
|  | 14 | // references by replacing them with physical register references - adding spill | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 15 | // code as necessary. | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 16 | // | 
|  | 17 | //===----------------------------------------------------------------------===// | 
|  | 18 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 19 | #define DEBUG_TYPE "spiller" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 20 | #include "VirtRegMap.h" | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" | 
|  | 24 | #include "llvm/CodeGen/SSARegMap.h" | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetMachine.h" | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" | 
| Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 27 | #include "llvm/Support/CommandLine.h" | 
|  | 28 | #include "llvm/Support/Debug.h" | 
| Chris Lattner | a4f0b3a | 2006-08-27 12:54:02 +0000 | [diff] [blame] | 29 | #include "llvm/Support/Compiler.h" | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 30 | #include "llvm/ADT/BitVector.h" | 
| Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/Statistic.h" | 
|  | 32 | #include "llvm/ADT/STLExtras.h" | 
| Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 33 | #include "llvm/ADT/SmallSet.h" | 
| Chris Lattner | 27f2916 | 2004-10-26 15:35:58 +0000 | [diff] [blame] | 34 | #include <algorithm> | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 35 | using namespace llvm; | 
|  | 36 |  | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 37 | STATISTIC(NumSpills, "Number of register spills"); | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 38 | STATISTIC(NumReMats, "Number of re-materialization"); | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 39 | STATISTIC(NumStores, "Number of stores added"); | 
|  | 40 | STATISTIC(NumLoads , "Number of loads added"); | 
|  | 41 | STATISTIC(NumReused, "Number of values reused"); | 
|  | 42 | STATISTIC(NumDSE   , "Number of dead stores elided"); | 
|  | 43 | STATISTIC(NumDCE   , "Number of copies elided"); | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 44 |  | 
| Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 45 | namespace { | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 46 | enum SpillerName { simple, local }; | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 47 |  | 
| Andrew Lenharth | ed41f1b | 2006-07-20 17:28:38 +0000 | [diff] [blame] | 48 | static cl::opt<SpillerName> | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 49 | SpillerOpt("spiller", | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 50 | cl::desc("Spiller to use: (default: local)"), | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 51 | cl::Prefix, | 
|  | 52 | cl::values(clEnumVal(simple, "  simple spiller"), | 
|  | 53 | clEnumVal(local,  "  local spiller"), | 
|  | 54 | clEnumValEnd), | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 55 | cl::init(local)); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 56 | } | 
|  | 57 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 58 | //===----------------------------------------------------------------------===// | 
|  | 59 | //  VirtRegMap implementation | 
|  | 60 | //===----------------------------------------------------------------------===// | 
|  | 61 |  | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 62 | VirtRegMap::VirtRegMap(MachineFunction &mf) | 
|  | 63 | : TII(*mf.getTarget().getInstrInfo()), MF(mf), | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 64 | Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), | 
|  | 65 | ReMatId(MAX_STACK_SLOT+1) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 66 | grow(); | 
|  | 67 | } | 
|  | 68 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 69 | void VirtRegMap::grow() { | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 70 | Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); | 
|  | 71 | Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 72 | } | 
|  | 73 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 74 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { | 
|  | 75 | assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 76 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 77 | "attempt to assign stack slot to already spilled register"); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 78 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); | 
|  | 79 | int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), | 
|  | 80 | RC->getAlignment()); | 
|  | 81 | Virt2StackSlotMap[virtReg] = frameIndex; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 82 | ++NumSpills; | 
|  | 83 | return frameIndex; | 
|  | 84 | } | 
|  | 85 |  | 
|  | 86 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { | 
|  | 87 | assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 88 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 89 | "attempt to assign stack slot to already spilled register"); | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 90 | Virt2StackSlotMap[virtReg] = frameIndex; | 
| Alkis Evlogimenos | 38af59a | 2004-05-29 20:38:05 +0000 | [diff] [blame] | 91 | } | 
|  | 92 |  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 93 | int VirtRegMap::assignVirtReMatId(unsigned virtReg) { | 
|  | 94 | assert(MRegisterInfo::isVirtualRegister(virtReg)); | 
|  | 95 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && | 
|  | 96 | "attempt to assign re-mat id to already spilled register"); | 
|  | 97 | Virt2StackSlotMap[virtReg] = ReMatId; | 
|  | 98 | ++NumReMats; | 
|  | 99 | return ReMatId++; | 
|  | 100 | } | 
|  | 101 |  | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 102 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 103 | unsigned OpNo, MachineInstr *NewMI) { | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 104 | // Move previous memory references folded to new instruction. | 
|  | 105 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 106 | for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 107 | E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { | 
|  | 108 | MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); | 
| Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 109 | MI2VirtMap.erase(I++); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 110 | } | 
| Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 111 |  | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 112 | ModRef MRInfo; | 
| Evan Cheng | 5c2a460 | 2006-12-08 08:02:34 +0000 | [diff] [blame] | 113 | const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor(); | 
|  | 114 | if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 || | 
| Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 115 | TID->findTiedToSrcOperand(OpNo) != -1) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 116 | // Folded a two-address operand. | 
|  | 117 | MRInfo = isModRef; | 
|  | 118 | } else if (OldMI->getOperand(OpNo).isDef()) { | 
|  | 119 | MRInfo = isMod; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 120 | } else { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 121 | MRInfo = isRef; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 122 | } | 
| Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 123 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 124 | // add new memory reference | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 125 | MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); | 
| Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 126 | } | 
|  | 127 |  | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 128 | void VirtRegMap::print(std::ostream &OS) const { | 
|  | 129 | const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 130 |  | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 131 | OS << "********** REGISTER MAP **********\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 132 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 133 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { | 
|  | 134 | if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) | 
|  | 135 | OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 136 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 137 | } | 
|  | 138 |  | 
|  | 139 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, | 
| Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 140 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) | 
|  | 141 | if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) | 
|  | 142 | OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; | 
|  | 143 | OS << '\n'; | 
| Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 144 | } | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 145 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 146 | void VirtRegMap::dump() const { | 
| Bill Wendling | 5c7e326 | 2006-12-17 05:15:13 +0000 | [diff] [blame] | 147 | print(DOUT); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 148 | } | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 149 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 150 |  | 
|  | 151 | //===----------------------------------------------------------------------===// | 
|  | 152 | // Simple Spiller Implementation | 
|  | 153 | //===----------------------------------------------------------------------===// | 
|  | 154 |  | 
|  | 155 | Spiller::~Spiller() {} | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 156 |  | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 157 | namespace { | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 158 | struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 159 | bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 160 | }; | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 161 | } | 
|  | 162 |  | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 163 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 164 | DOUT << "********** REWRITE MACHINE CODE **********\n"; | 
|  | 165 | DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; | 
| Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 166 | const TargetMachine &TM = MF.getTarget(); | 
|  | 167 | const MRegisterInfo &MRI = *TM.getRegisterInfo(); | 
|  | 168 | bool *PhysRegsUsed = MF.getUsedPhysregs(); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 169 |  | 
| Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 170 | // LoadedRegs - Keep track of which vregs are loaded, so that we only load | 
|  | 171 | // each vreg once (in the case where a spilled vreg is used by multiple | 
|  | 172 | // operands).  This is always smaller than the number of operands to the | 
|  | 173 | // current machine instr, so it should be small. | 
|  | 174 | std::vector<unsigned> LoadedRegs; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 175 |  | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 176 | for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); | 
|  | 177 | MBBI != E; ++MBBI) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 178 | DOUT << MBBI->getBasicBlock()->getName() << ":\n"; | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 179 | MachineBasicBlock &MBB = *MBBI; | 
|  | 180 | for (MachineBasicBlock::iterator MII = MBB.begin(), | 
|  | 181 | E = MBB.end(); MII != E; ++MII) { | 
|  | 182 | MachineInstr &MI = *MII; | 
|  | 183 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 184 | MachineOperand &MO = MI.getOperand(i); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 185 | if (MO.isRegister() && MO.getReg()) | 
|  | 186 | if (MRegisterInfo::isVirtualRegister(MO.getReg())) { | 
|  | 187 | unsigned VirtReg = MO.getReg(); | 
|  | 188 | unsigned PhysReg = VRM.getPhys(VirtReg); | 
|  | 189 | if (VRM.hasStackSlot(VirtReg)) { | 
|  | 190 | int StackSlot = VRM.getStackSlot(VirtReg); | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 191 | const TargetRegisterClass* RC = | 
|  | 192 | MF.getSSARegMap()->getRegClass(VirtReg); | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 193 |  | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 194 | if (MO.isUse() && | 
|  | 195 | std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) | 
|  | 196 | == LoadedRegs.end()) { | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 197 | MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 198 | LoadedRegs.push_back(VirtReg); | 
|  | 199 | ++NumLoads; | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 200 | DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 201 | } | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 202 |  | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 203 | if (MO.isDef()) { | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 204 | MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 205 | ++NumStores; | 
|  | 206 | } | 
| Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 207 | } | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 208 | PhysRegsUsed[PhysReg] = true; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 209 | MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 210 | } else { | 
|  | 211 | PhysRegsUsed[MO.getReg()] = true; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 212 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 213 | } | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 214 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 215 | DOUT << '\t' << MI; | 
| Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 216 | LoadedRegs.clear(); | 
| Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 217 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 218 | } | 
|  | 219 | return true; | 
|  | 220 | } | 
|  | 221 |  | 
|  | 222 | //===----------------------------------------------------------------------===// | 
|  | 223 | //  Local Spiller Implementation | 
|  | 224 | //===----------------------------------------------------------------------===// | 
|  | 225 |  | 
|  | 226 | namespace { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 227 | /// LocalSpiller - This spiller does a simple pass over the machine basic | 
|  | 228 | /// block to attempt to keep spills in registers as much as possible for | 
|  | 229 | /// blocks that have low register pressure (the vreg may be spilled due to | 
|  | 230 | /// register pressure in other blocks). | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 231 | class VISIBILITY_HIDDEN LocalSpiller : public Spiller { | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 232 | const MRegisterInfo *MRI; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 233 | const TargetInstrInfo *TII; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 234 | public: | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 235 | bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 236 | MRI = MF.getTarget().getRegisterInfo(); | 
|  | 237 | TII = MF.getTarget().getInstrInfo(); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 238 | DOUT << "\n**** Local spiller rewriting function '" | 
|  | 239 | << MF.getFunction()->getName() << "':\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 240 |  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 241 | std::vector<MachineInstr *> ReMatedMIs; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 242 | for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); | 
|  | 243 | MBB != E; ++MBB) | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 244 | RewriteMBB(*MBB, VRM, ReMatedMIs); | 
|  | 245 | for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i) | 
|  | 246 | delete ReMatedMIs[i]; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 247 | return true; | 
|  | 248 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 249 | private: | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 250 | void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, | 
|  | 251 | std::vector<MachineInstr*> &ReMatedMIs); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 252 | }; | 
|  | 253 | } | 
|  | 254 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 255 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from | 
|  | 256 | /// top down, keep track of which spills slots are available in each register. | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 257 | /// | 
|  | 258 | /// Note that not all physregs are created equal here.  In particular, some | 
|  | 259 | /// physregs are reloads that we are allowed to clobber or ignore at any time. | 
|  | 260 | /// Other physregs are values that the register allocated program is using that | 
|  | 261 | /// we cannot CHANGE, but we can read if we like.  We keep track of this on a | 
|  | 262 | /// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable | 
|  | 263 | /// entries.  The predicate 'canClobberPhysReg()' checks this bit and | 
|  | 264 | /// addAvailable sets it if. | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 265 | namespace { | 
|  | 266 | class VISIBILITY_HIDDEN AvailableSpills { | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 267 | const MRegisterInfo *MRI; | 
|  | 268 | const TargetInstrInfo *TII; | 
|  | 269 |  | 
|  | 270 | // SpillSlotsAvailable - This map keeps track of all of the spilled virtual | 
|  | 271 | // register values that are still available, due to being loaded or stored to, | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 272 | // but not invalidated yet. It also tracks the instructions that defined | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 273 | // or used the register. | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 274 | typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo; | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 275 | std::map<int, SSInfo> SpillSlotsAvailable; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 276 |  | 
|  | 277 | // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating | 
|  | 278 | // which stack slot values are currently held by a physreg.  This is used to | 
|  | 279 | // invalidate entries in SpillSlotsAvailable when a physreg is modified. | 
|  | 280 | std::multimap<unsigned, int> PhysRegsAvailable; | 
|  | 281 |  | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 282 | void disallowClobberPhysRegOnly(unsigned PhysReg); | 
|  | 283 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 284 | void ClobberPhysRegOnly(unsigned PhysReg); | 
|  | 285 | public: | 
|  | 286 | AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) | 
|  | 287 | : MRI(mri), TII(tii) { | 
|  | 288 | } | 
|  | 289 |  | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 290 | const MRegisterInfo *getRegInfo() const { return MRI; } | 
|  | 291 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 292 | /// getSpillSlotPhysReg - If the specified stack slot is available in a | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 293 | /// physical register, return that PhysReg, otherwise return 0. It also | 
|  | 294 | /// returns by reference the instruction that either defines or last uses | 
|  | 295 | /// the register. | 
|  | 296 | unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const { | 
|  | 297 | std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot); | 
|  | 298 | if (I != SpillSlotsAvailable.end()) { | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 299 | if (!I->second.second.empty()) | 
|  | 300 | SSMI = I->second.second.back(); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 301 | return I->second.first >> 1;  // Remove the CanClobber bit. | 
|  | 302 | } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 303 | return 0; | 
|  | 304 | } | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 305 |  | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 306 | /// addLastUse - Add the last use information of all stack slots whose | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 307 | /// values are available in the specific register. | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 308 | void addLastUse(unsigned PhysReg, MachineInstr *Use) { | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 309 | std::multimap<unsigned, int>::iterator I = | 
|  | 310 | PhysRegsAvailable.lower_bound(PhysReg); | 
|  | 311 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
|  | 312 | int Slot = I->second; | 
|  | 313 | I++; | 
|  | 314 |  | 
|  | 315 | std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot); | 
|  | 316 | assert(II != SpillSlotsAvailable.end() && "Slot not available!"); | 
|  | 317 | unsigned Val = II->second.first; | 
|  | 318 | assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!"); | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 319 | II->second.second.push_back(Use); | 
|  | 320 | } | 
|  | 321 | } | 
|  | 322 |  | 
|  | 323 | /// removeLastUse - Remove the last use information of all stack slots whose | 
|  | 324 | /// values are available in the specific register. | 
|  | 325 | void removeLastUse(unsigned PhysReg, MachineInstr *Use) { | 
|  | 326 | std::multimap<unsigned, int>::iterator I = | 
|  | 327 | PhysRegsAvailable.lower_bound(PhysReg); | 
|  | 328 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
|  | 329 | int Slot = I->second; | 
|  | 330 | I++; | 
|  | 331 |  | 
|  | 332 | std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot); | 
|  | 333 | assert(II != SpillSlotsAvailable.end() && "Slot not available!"); | 
|  | 334 | unsigned Val = II->second.first; | 
|  | 335 | assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!"); | 
|  | 336 | if (II->second.second.back() == Use) | 
|  | 337 | II->second.second.pop_back(); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 338 | } | 
|  | 339 | } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 340 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 341 | /// addAvailable - Mark that the specified stack slot is available in the | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 342 | /// specified physreg.  If CanClobber is true, the physreg can be modified at | 
|  | 343 | /// any time without changing the semantics of the program. | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 344 | void addAvailable(int Slot, MachineInstr *MI, unsigned Reg, | 
|  | 345 | bool CanClobber = true) { | 
| Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 346 | // If this stack slot is thought to be available in some other physreg, | 
|  | 347 | // remove its record. | 
|  | 348 | ModifyStackSlot(Slot); | 
|  | 349 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 350 | PhysRegsAvailable.insert(std::make_pair(Reg, Slot)); | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 351 | std::vector<MachineInstr*> DefUses; | 
|  | 352 | DefUses.push_back(MI); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 353 | SpillSlotsAvailable[Slot] = | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 354 | std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses); | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 355 |  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 356 | if (Slot > VirtRegMap::MAX_STACK_SLOT) | 
|  | 357 | DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1; | 
|  | 358 | else | 
|  | 359 | DOUT << "Remembering SS#" << Slot; | 
|  | 360 | DOUT << " in physreg " << MRI->getName(Reg) << "\n"; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 361 | } | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 362 |  | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 363 | /// canClobberPhysReg - Return true if the spiller is allowed to change the | 
|  | 364 | /// value of the specified stackslot register if it desires.  The specified | 
|  | 365 | /// stack slot must be available in a physreg for this query to make sense. | 
|  | 366 | bool canClobberPhysReg(int Slot) const { | 
|  | 367 | assert(SpillSlotsAvailable.count(Slot) && "Slot not available!"); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 368 | return SpillSlotsAvailable.find(Slot)->second.first & 1; | 
| Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 369 | } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 370 |  | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 371 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified | 
|  | 372 | /// stackslot register. The register is still available but is no longer | 
|  | 373 | /// allowed to be modifed. | 
|  | 374 | void disallowClobberPhysReg(unsigned PhysReg); | 
|  | 375 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 376 | /// ClobberPhysReg - This is called when the specified physreg changes | 
|  | 377 | /// value.  We use this to invalidate any info about stuff we thing lives in | 
|  | 378 | /// it and any of its aliases. | 
|  | 379 | void ClobberPhysReg(unsigned PhysReg); | 
|  | 380 |  | 
|  | 381 | /// ModifyStackSlot - This method is called when the value in a stack slot | 
|  | 382 | /// changes.  This removes information about which register the previous value | 
|  | 383 | /// for this slot lives in (as the previous value is dead now). | 
|  | 384 | void ModifyStackSlot(int Slot); | 
|  | 385 | }; | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 386 | } | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 387 |  | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 388 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified | 
|  | 389 | /// stackslot register. The register is still available but is no longer | 
|  | 390 | /// allowed to be modifed. | 
|  | 391 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { | 
|  | 392 | std::multimap<unsigned, int>::iterator I = | 
|  | 393 | PhysRegsAvailable.lower_bound(PhysReg); | 
|  | 394 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
|  | 395 | int Slot = I->second; | 
|  | 396 | I++; | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 397 | assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg && | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 398 | "Bidirectional map mismatch!"); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 399 | SpillSlotsAvailable[Slot].first &= ~1; | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 400 | DOUT << "PhysReg " << MRI->getName(PhysReg) | 
|  | 401 | << " copied, it is available for use but can no longer be modified\n"; | 
|  | 402 | } | 
|  | 403 | } | 
|  | 404 |  | 
|  | 405 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified | 
|  | 406 | /// stackslot register and its aliases. The register and its aliases may | 
|  | 407 | /// still available but is no longer allowed to be modifed. | 
|  | 408 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { | 
|  | 409 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) | 
|  | 410 | disallowClobberPhysRegOnly(*AS); | 
|  | 411 | disallowClobberPhysRegOnly(PhysReg); | 
|  | 412 | } | 
|  | 413 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 414 | /// ClobberPhysRegOnly - This is called when the specified physreg changes | 
|  | 415 | /// value.  We use this to invalidate any info about stuff we thing lives in it. | 
|  | 416 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { | 
|  | 417 | std::multimap<unsigned, int>::iterator I = | 
|  | 418 | PhysRegsAvailable.lower_bound(PhysReg); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 419 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 420 | int Slot = I->second; | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 421 | PhysRegsAvailable.erase(I++); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 422 | assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg && | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 423 | "Bidirectional map mismatch!"); | 
|  | 424 | SpillSlotsAvailable.erase(Slot); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 425 | DOUT << "PhysReg " << MRI->getName(PhysReg) | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 426 | << " clobbered, invalidating "; | 
|  | 427 | if (Slot > VirtRegMap::MAX_STACK_SLOT) | 
|  | 428 | DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; | 
|  | 429 | else | 
|  | 430 | DOUT << "SS#" << Slot << "\n"; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 431 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 432 | } | 
|  | 433 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 434 | /// ClobberPhysReg - This is called when the specified physreg changes | 
|  | 435 | /// value.  We use this to invalidate any info about stuff we thing lives in | 
|  | 436 | /// it and any of its aliases. | 
|  | 437 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 438 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 439 | ClobberPhysRegOnly(*AS); | 
|  | 440 | ClobberPhysRegOnly(PhysReg); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 441 | } | 
|  | 442 |  | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 443 | /// ModifyStackSlot - This method is called when the value in a stack slot | 
|  | 444 | /// changes.  This removes information about which register the previous value | 
|  | 445 | /// for this slot lives in (as the previous value is dead now). | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 446 | void AvailableSpills::ModifyStackSlot(int Slot) { | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 447 | std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot); | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 448 | if (It == SpillSlotsAvailable.end()) return; | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 449 | unsigned Reg = It->second.first >> 1; | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 450 | SpillSlotsAvailable.erase(It); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 451 |  | 
|  | 452 | // This register may hold the value of multiple stack slots, only remove this | 
|  | 453 | // stack slot from the set of values the register contains. | 
|  | 454 | std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); | 
|  | 455 | for (; ; ++I) { | 
|  | 456 | assert(I != PhysRegsAvailable.end() && I->first == Reg && | 
|  | 457 | "Map inverse broken!"); | 
|  | 458 | if (I->second == Slot) break; | 
|  | 459 | } | 
|  | 460 | PhysRegsAvailable.erase(I); | 
|  | 461 | } | 
|  | 462 |  | 
|  | 463 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 464 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 465 | // ReusedOp - For each reused operand, we keep track of a bit of information, in | 
|  | 466 | // case we need to rollback upon processing a new operand.  See comments below. | 
|  | 467 | namespace { | 
|  | 468 | struct ReusedOp { | 
|  | 469 | // The MachineInstr operand that reused an available value. | 
|  | 470 | unsigned Operand; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 471 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 472 | // StackSlot - The spill slot of the value being reused. | 
|  | 473 | unsigned StackSlot; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 474 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 475 | // PhysRegReused - The physical register the value was available in. | 
|  | 476 | unsigned PhysRegReused; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 477 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 478 | // AssignedPhysReg - The physreg that was assigned for use by the reload. | 
|  | 479 | unsigned AssignedPhysReg; | 
| Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 480 |  | 
|  | 481 | // VirtReg - The virtual register itself. | 
|  | 482 | unsigned VirtReg; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 483 |  | 
| Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 484 | ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, | 
|  | 485 | unsigned vreg) | 
|  | 486 | : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr), | 
|  | 487 | VirtReg(vreg) {} | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 488 | }; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 489 |  | 
|  | 490 | /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that | 
|  | 491 | /// is reused instead of reloaded. | 
| Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 492 | class VISIBILITY_HIDDEN ReuseInfo { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 493 | MachineInstr &MI; | 
|  | 494 | std::vector<ReusedOp> Reuses; | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 495 | BitVector PhysRegsClobbered; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 496 | public: | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 497 | ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 498 | PhysRegsClobbered.resize(mri->getNumRegs()); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 499 | } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 500 |  | 
|  | 501 | bool hasReuses() const { | 
|  | 502 | return !Reuses.empty(); | 
|  | 503 | } | 
|  | 504 |  | 
|  | 505 | /// addReuse - If we choose to reuse a virtual register that is already | 
|  | 506 | /// available instead of reloading it, remember that we did so. | 
|  | 507 | void addReuse(unsigned OpNo, unsigned StackSlot, | 
|  | 508 | unsigned PhysRegReused, unsigned AssignedPhysReg, | 
|  | 509 | unsigned VirtReg) { | 
|  | 510 | // If the reload is to the assigned register anyway, no undo will be | 
|  | 511 | // required. | 
|  | 512 | if (PhysRegReused == AssignedPhysReg) return; | 
|  | 513 |  | 
|  | 514 | // Otherwise, remember this. | 
|  | 515 | Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused, | 
|  | 516 | AssignedPhysReg, VirtReg)); | 
|  | 517 | } | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 518 |  | 
|  | 519 | void markClobbered(unsigned PhysReg) { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 520 | PhysRegsClobbered.set(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 521 | } | 
|  | 522 |  | 
|  | 523 | bool isClobbered(unsigned PhysReg) const { | 
| Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 524 | return PhysRegsClobbered.test(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 525 | } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 526 |  | 
|  | 527 | /// GetRegForReload - We are about to emit a reload into PhysReg.  If there | 
|  | 528 | /// is some other operand that is using the specified register, either pick | 
|  | 529 | /// a new register to use, or evict the previous reload and use this reg. | 
|  | 530 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, | 
|  | 531 | AvailableSpills &Spills, | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 532 | std::map<int, MachineInstr*> &MaybeDeadStores, | 
| Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 533 | SmallSet<unsigned, 8> &Rejected) { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 534 | if (Reuses.empty()) return PhysReg;  // This is most often empty. | 
|  | 535 |  | 
|  | 536 | for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { | 
|  | 537 | ReusedOp &Op = Reuses[ro]; | 
|  | 538 | // If we find some other reuse that was supposed to use this register | 
|  | 539 | // exactly for its reload, we can change this reload to use ITS reload | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 540 | // register. That is, unless its reload register has already been | 
|  | 541 | // considered and subsequently rejected because it has also been reused | 
|  | 542 | // by another operand. | 
|  | 543 | if (Op.PhysRegReused == PhysReg && | 
|  | 544 | Rejected.count(Op.AssignedPhysReg) == 0) { | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 545 | // Yup, use the reload register that we didn't use before. | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 546 | unsigned NewReg = Op.AssignedPhysReg; | 
|  | 547 | Rejected.insert(PhysReg); | 
|  | 548 | return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 549 | } else { | 
|  | 550 | // Otherwise, we might also have a problem if a previously reused | 
|  | 551 | // value aliases the new register.  If so, codegen the previous reload | 
|  | 552 | // and use this one. | 
|  | 553 | unsigned PRRU = Op.PhysRegReused; | 
|  | 554 | const MRegisterInfo *MRI = Spills.getRegInfo(); | 
|  | 555 | if (MRI->areAliases(PRRU, PhysReg)) { | 
|  | 556 | // Okay, we found out that an alias of a reused register | 
|  | 557 | // was used.  This isn't good because it means we have | 
|  | 558 | // to undo a previous reuse. | 
|  | 559 | MachineBasicBlock *MBB = MI->getParent(); | 
|  | 560 | const TargetRegisterClass *AliasRC = | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 561 | MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); | 
|  | 562 |  | 
|  | 563 | // Copy Op out of the vector and remove it, we're going to insert an | 
|  | 564 | // explicit load for it. | 
|  | 565 | ReusedOp NewOp = Op; | 
|  | 566 | Reuses.erase(Reuses.begin()+ro); | 
|  | 567 |  | 
|  | 568 | // Ok, we're going to try to reload the assigned physreg into the | 
|  | 569 | // slot that we were supposed to in the first place.  However, that | 
|  | 570 | // register could hold a reuse.  Check to see if it conflicts or | 
|  | 571 | // would prefer us to use a different register. | 
|  | 572 | unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 573 | MI, Spills, MaybeDeadStores, Rejected); | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 574 |  | 
|  | 575 | MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, | 
|  | 576 | NewOp.StackSlot, AliasRC); | 
|  | 577 | Spills.ClobberPhysReg(NewPhysReg); | 
|  | 578 | Spills.ClobberPhysReg(NewOp.PhysRegReused); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 579 |  | 
|  | 580 | // Any stores to this stack slot are not dead anymore. | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 581 | MaybeDeadStores.erase(NewOp.StackSlot); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 582 |  | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 583 | MI->getOperand(NewOp.Operand).setReg(NewPhysReg); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 584 |  | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 585 | Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 586 | ++NumLoads; | 
|  | 587 | DEBUG(MachineBasicBlock::iterator MII = MI; | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 588 | DOUT << '\t' << *prior(MII)); | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 589 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 590 | DOUT << "Reuse undone!\n"; | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 591 | --NumReused; | 
| Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 592 |  | 
|  | 593 | // Finally, PhysReg is now available, go ahead and use it. | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 594 | return PhysReg; | 
|  | 595 | } | 
|  | 596 | } | 
|  | 597 | } | 
|  | 598 | return PhysReg; | 
|  | 599 | } | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 600 |  | 
|  | 601 | /// GetRegForReload - Helper for the above GetRegForReload(). Add a | 
|  | 602 | /// 'Rejected' set to remember which registers have been considered and | 
|  | 603 | /// rejected for the reload. This avoids infinite looping in case like | 
|  | 604 | /// this: | 
|  | 605 | /// t1 := op t2, t3 | 
|  | 606 | /// t2 <- assigned r0 for use by the reload but ended up reuse r1 | 
|  | 607 | /// t3 <- assigned r1 for use by the reload but ended up reuse r0 | 
|  | 608 | /// t1 <- desires r1 | 
|  | 609 | ///       sees r1 is taken by t2, tries t2's reload register r0 | 
|  | 610 | ///       sees r0 is taken by t3, tries t3's reload register r1 | 
|  | 611 | ///       sees r1 is taken by t2, tries t2's reload register r0 ... | 
|  | 612 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, | 
|  | 613 | AvailableSpills &Spills, | 
|  | 614 | std::map<int, MachineInstr*> &MaybeDeadStores) { | 
| Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 615 | SmallSet<unsigned, 8> Rejected; | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 616 | return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected); | 
|  | 617 | } | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 618 | }; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 619 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 620 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 621 |  | 
|  | 622 | /// rewriteMBB - Keep track of which spills are available even after the | 
|  | 623 | /// register allocator is done with them.  If possible, avoid reloading vregs. | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 624 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, | 
|  | 625 | std::vector<MachineInstr*> &ReMatedMIs) { | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 626 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 627 | DOUT << MBB.getBasicBlock()->getName() << ":\n"; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 628 |  | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 629 | // Spills - Keep track of which spilled values are available in physregs so | 
|  | 630 | // that we can choose to reuse the physregs instead of emitting reloads. | 
|  | 631 | AvailableSpills Spills(MRI, TII); | 
|  | 632 |  | 
| Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 633 | // MaybeDeadStores - When we need to write a value back into a stack slot, | 
|  | 634 | // keep track of the inserted store.  If the stack slot value is never read | 
|  | 635 | // (because the value was used from some available register, for example), and | 
|  | 636 | // subsequently stored to, the original store is dead.  This map keeps track | 
|  | 637 | // of inserted stores that are not used.  If we see a subsequent store to the | 
|  | 638 | // same stack slot, the original store is deleted. | 
|  | 639 | std::map<int, MachineInstr*> MaybeDeadStores; | 
|  | 640 |  | 
| Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 641 | bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs(); | 
|  | 642 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 643 | for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); | 
|  | 644 | MII != E; ) { | 
|  | 645 | MachineInstr &MI = *MII; | 
|  | 646 | MachineBasicBlock::iterator NextMII = MII; ++NextMII; | 
|  | 647 |  | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 648 | /// ReusedOperands - Keep track of operand reuse in case we need to undo | 
|  | 649 | /// reuse. | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 650 | ReuseInfo ReusedOperands(MI, MRI); | 
|  | 651 |  | 
|  | 652 | // Loop over all of the implicit defs, clearing them from our available | 
|  | 653 | // sets. | 
| Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 654 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 655 |  | 
|  | 656 | // If this instruction is being rematerialized, just remove it! | 
|  | 657 | if (TID->Flags & M_REMATERIALIZIBLE) { | 
|  | 658 | bool Remove = true; | 
|  | 659 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
|  | 660 | MachineOperand &MO = MI.getOperand(i); | 
|  | 661 | if (!MO.isRegister() || MO.getReg() == 0) | 
|  | 662 | continue;   // Ignore non-register operands. | 
|  | 663 | if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) { | 
|  | 664 | Remove = false; | 
|  | 665 | break; | 
|  | 666 | } | 
|  | 667 | } | 
|  | 668 | if (Remove) { | 
|  | 669 | VRM.RemoveFromFoldedVirtMap(&MI); | 
|  | 670 | ReMatedMIs.push_back(MI.removeFromParent()); | 
|  | 671 | MII = NextMII; | 
|  | 672 | continue; | 
|  | 673 | } | 
|  | 674 | } | 
|  | 675 |  | 
| Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 676 | const unsigned *ImpDef = TID->ImplicitDefs; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 677 | if (ImpDef) { | 
|  | 678 | for ( ; *ImpDef; ++ImpDef) { | 
|  | 679 | PhysRegsUsed[*ImpDef] = true; | 
|  | 680 | ReusedOperands.markClobbered(*ImpDef); | 
|  | 681 | Spills.ClobberPhysReg(*ImpDef); | 
|  | 682 | } | 
|  | 683 | } | 
|  | 684 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 685 | // Process all of the spilled uses and all non spilled reg references. | 
|  | 686 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
|  | 687 | MachineOperand &MO = MI.getOperand(i); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 688 | if (!MO.isRegister() || MO.getReg() == 0) | 
|  | 689 | continue;   // Ignore non-register operands. | 
|  | 690 |  | 
|  | 691 | if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { | 
|  | 692 | // Ignore physregs for spilling, but remember that it is used by this | 
|  | 693 | // function. | 
| Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 694 | PhysRegsUsed[MO.getReg()] = true; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 695 | ReusedOperands.markClobbered(MO.getReg()); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 696 | continue; | 
|  | 697 | } | 
|  | 698 |  | 
|  | 699 | assert(MRegisterInfo::isVirtualRegister(MO.getReg()) && | 
|  | 700 | "Not a virtual or a physical register?"); | 
|  | 701 |  | 
|  | 702 | unsigned VirtReg = MO.getReg(); | 
|  | 703 | if (!VRM.hasStackSlot(VirtReg)) { | 
|  | 704 | // This virtual register was assigned a physreg! | 
|  | 705 | unsigned Phys = VRM.getPhys(VirtReg); | 
|  | 706 | PhysRegsUsed[Phys] = true; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 707 | if (MO.isDef()) | 
|  | 708 | ReusedOperands.markClobbered(Phys); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 709 | MI.getOperand(i).setReg(Phys); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 710 | continue; | 
|  | 711 | } | 
|  | 712 |  | 
|  | 713 | // This virtual register is now known to be a spilled value. | 
|  | 714 | if (!MO.isUse()) | 
|  | 715 | continue;  // Handle defs in the loop below (handle use&def here though) | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 716 |  | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 717 | bool doReMat = VRM.isReMaterialized(VirtReg); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 718 | int StackSlot = VRM.getStackSlot(VirtReg); | 
|  | 719 | unsigned PhysReg; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 720 |  | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 721 | // Check to see if this stack slot is available. | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 722 | MachineInstr *SSMI = NULL; | 
|  | 723 | if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 724 | // This spilled operand might be part of a two-address operand.  If this | 
|  | 725 | // is the case, then changing it will necessarily require changing the | 
|  | 726 | // def part of the instruction as well.  However, in some cases, we | 
|  | 727 | // aren't allowed to modify the reused register.  If none of these cases | 
|  | 728 | // apply, reuse it. | 
|  | 729 | bool CanReuse = true; | 
| Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 730 | int ti = TID->getOperandConstraint(i, TOI::TIED_TO); | 
| Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 731 | if (ti != -1 && | 
|  | 732 | MI.getOperand(ti).isReg() && | 
|  | 733 | MI.getOperand(ti).getReg() == VirtReg) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 734 | // Okay, we have a two address operand.  We can reuse this physreg as | 
| Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 735 | // long as we are allowed to clobber the value and there isn't an | 
|  | 736 | // earlier def that has already clobbered the physreg. | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 737 | CanReuse = Spills.canClobberPhysReg(StackSlot) && | 
|  | 738 | !ReusedOperands.isClobbered(PhysReg); | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 739 | } | 
|  | 740 |  | 
|  | 741 | if (CanReuse) { | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 742 | // If this stack slot value is already available, reuse it! | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 743 | if (StackSlot > VirtRegMap::MAX_STACK_SLOT) | 
|  | 744 | DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1; | 
|  | 745 | else | 
|  | 746 | DOUT << "Reusing SS#" << StackSlot; | 
|  | 747 | DOUT << " from physreg " | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 748 | << MRI->getName(PhysReg) << " for vreg" | 
|  | 749 | << VirtReg <<" instead of reloading into physreg " | 
|  | 750 | << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 751 | MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 752 |  | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 753 | // Extend the live range of the MI that last kill the register if | 
|  | 754 | // necessary. | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 755 | bool WasKill = false; | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 756 | if (SSMI) { | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 757 | int UIdx = SSMI->findRegisterUseOperand(PhysReg, true); | 
|  | 758 | if (UIdx != -1) { | 
|  | 759 | MachineOperand &MOK = SSMI->getOperand(UIdx); | 
|  | 760 | WasKill = MOK.isKill(); | 
|  | 761 | MOK.unsetIsKill(); | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 762 | } | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 763 | } | 
|  | 764 | if (ti == -1) { | 
|  | 765 | // Unless it's the use of a two-address code, transfer the kill | 
|  | 766 | // of the reused register to this use. | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 767 | if (WasKill) | 
|  | 768 | MI.getOperand(i).setIsKill(); | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 769 | Spills.addLastUse(PhysReg, &MI); | 
| Evan Cheng | 50d25d7 | 2007-02-23 21:47:50 +0000 | [diff] [blame] | 770 | } | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 771 |  | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 772 | // The only technical detail we have is that we don't know that | 
|  | 773 | // PhysReg won't be clobbered by a reloaded stack slot that occurs | 
|  | 774 | // later in the instruction.  In particular, consider 'op V1, V2'. | 
|  | 775 | // If V1 is available in physreg R0, we would choose to reuse it | 
|  | 776 | // here, instead of reloading it into the register the allocator | 
|  | 777 | // indicated (say R1).  However, V2 might have to be reloaded | 
|  | 778 | // later, and it might indicate that it needs to live in R0.  When | 
|  | 779 | // this occurs, we need to have information available that | 
|  | 780 | // indicates it is safe to use R1 for the reload instead of R0. | 
|  | 781 | // | 
|  | 782 | // To further complicate matters, we might conflict with an alias, | 
|  | 783 | // or R0 and R1 might not be compatible with each other.  In this | 
|  | 784 | // case, we actually insert a reload for V1 in R1, ensuring that | 
|  | 785 | // we can get at R0 or its alias. | 
|  | 786 | ReusedOperands.addReuse(i, StackSlot, PhysReg, | 
|  | 787 | VRM.getPhys(VirtReg), VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 788 | if (ti != -1) | 
|  | 789 | // Only mark it clobbered if this is a use&def operand. | 
|  | 790 | ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 791 | ++NumReused; | 
|  | 792 | continue; | 
|  | 793 | } | 
|  | 794 |  | 
|  | 795 | // Otherwise we have a situation where we have a two-address instruction | 
|  | 796 | // whose mod/ref operand needs to be reloaded.  This reload is already | 
|  | 797 | // available in some register "PhysReg", but if we used PhysReg as the | 
|  | 798 | // operand to our 2-addr instruction, the instruction would modify | 
|  | 799 | // PhysReg.  This isn't cool if something later uses PhysReg and expects | 
|  | 800 | // to get its initial value. | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 801 | // | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 802 | // To avoid this problem, and to avoid doing a load right after a store, | 
|  | 803 | // we emit a copy from PhysReg into the designated register for this | 
|  | 804 | // operand. | 
|  | 805 | unsigned DesignatedReg = VRM.getPhys(VirtReg); | 
|  | 806 | assert(DesignatedReg && "Must map virtreg to physreg!"); | 
|  | 807 |  | 
|  | 808 | // Note that, if we reused a register for a previous operand, the | 
|  | 809 | // register we want to reload into might not actually be | 
|  | 810 | // available.  If this occurs, use the register indicated by the | 
|  | 811 | // reuser. | 
|  | 812 | if (ReusedOperands.hasReuses()) | 
|  | 813 | DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, | 
|  | 814 | Spills, MaybeDeadStores); | 
|  | 815 |  | 
| Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 816 | // If the mapped designated register is actually the physreg we have | 
|  | 817 | // incoming, we don't need to inserted a dead copy. | 
|  | 818 | if (DesignatedReg == PhysReg) { | 
|  | 819 | // If this stack slot value is already available, reuse it! | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 820 | if (StackSlot > VirtRegMap::MAX_STACK_SLOT) | 
|  | 821 | DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1; | 
|  | 822 | else | 
|  | 823 | DOUT << "Reusing SS#" << StackSlot; | 
|  | 824 | DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 825 | << VirtReg | 
|  | 826 | << " instead of reloading into same physreg.\n"; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 827 | MI.getOperand(i).setReg(PhysReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 828 | ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 829 | ++NumReused; | 
|  | 830 | continue; | 
|  | 831 | } | 
|  | 832 |  | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 833 | const TargetRegisterClass* RC = | 
|  | 834 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); | 
|  | 835 |  | 
|  | 836 | PhysRegsUsed[DesignatedReg] = true; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 837 | ReusedOperands.markClobbered(DesignatedReg); | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 838 | MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 839 |  | 
|  | 840 | // Extend the live range of the MI that last kill the register if | 
|  | 841 | // necessary. | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 842 | bool WasKill = false; | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 843 | if (SSMI) { | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 844 | int UIdx = SSMI->findRegisterUseOperand(PhysReg, true); | 
|  | 845 | if (UIdx != -1) { | 
|  | 846 | MachineOperand &MOK = SSMI->getOperand(UIdx); | 
|  | 847 | WasKill = MOK.isKill(); | 
|  | 848 | MOK.unsetIsKill(); | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 849 | } | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 850 | } | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 851 | MachineInstr *CopyMI = prior(MII); | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 852 | if (WasKill) { | 
|  | 853 | // Transfer kill to the next use. | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 854 | int UIdx = CopyMI->findRegisterUseOperand(PhysReg); | 
|  | 855 | assert(UIdx != -1); | 
|  | 856 | MachineOperand &MOU = CopyMI->getOperand(UIdx); | 
|  | 857 | MOU.setIsKill(); | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 858 | } | 
|  | 859 | Spills.addLastUse(PhysReg, CopyMI); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 860 |  | 
| Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 861 | // This invalidates DesignatedReg. | 
|  | 862 | Spills.ClobberPhysReg(DesignatedReg); | 
|  | 863 |  | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 864 | Spills.addAvailable(StackSlot, &MI, DesignatedReg); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 865 | MI.getOperand(i).setReg(DesignatedReg); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 866 | DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 867 | ++NumReused; | 
|  | 868 | continue; | 
|  | 869 | } | 
|  | 870 |  | 
|  | 871 | // Otherwise, reload it and remember that we have it. | 
|  | 872 | PhysReg = VRM.getPhys(VirtReg); | 
| Chris Lattner | 172c362 | 2006-01-04 06:47:48 +0000 | [diff] [blame] | 873 | assert(PhysReg && "Must map virtreg to physreg!"); | 
| Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 874 | const TargetRegisterClass* RC = | 
|  | 875 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 876 |  | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 877 | // Note that, if we reused a register for a previous operand, the | 
|  | 878 | // register we want to reload into might not actually be | 
|  | 879 | // available.  If this occurs, use the register indicated by the | 
|  | 880 | // reuser. | 
| Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 881 | if (ReusedOperands.hasReuses()) | 
|  | 882 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, | 
|  | 883 | Spills, MaybeDeadStores); | 
|  | 884 |  | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 885 | PhysRegsUsed[PhysReg] = true; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 886 | ReusedOperands.markClobbered(PhysReg); | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 887 | if (doReMat) | 
|  | 888 | MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); | 
|  | 889 | else | 
|  | 890 | MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 891 | // This invalidates PhysReg. | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 892 | Spills.ClobberPhysReg(PhysReg); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 893 |  | 
|  | 894 | // Any stores to this stack slot are not dead anymore. | 
| Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 895 | if (!doReMat) | 
|  | 896 | MaybeDeadStores.erase(StackSlot); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 897 | Spills.addAvailable(StackSlot, &MI, PhysReg); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 898 | // Assumes this is the last use. IsKill will be unset if reg is reused | 
|  | 899 | // unless it's a two-address operand. | 
|  | 900 | if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) | 
|  | 901 | MI.getOperand(i).setIsKill(); | 
| Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 902 | ++NumLoads; | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 903 | MI.getOperand(i).setReg(PhysReg); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 904 | DOUT << '\t' << *prior(MII); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 905 | } | 
|  | 906 |  | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 907 | DOUT << '\t' << MI; | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 908 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 909 | // If we have folded references to memory operands, make sure we clear all | 
|  | 910 | // physical registers that may contain the value of the spilled virtual | 
|  | 911 | // register | 
| Chris Lattner | 8f1d640 | 2005-01-14 15:54:24 +0000 | [diff] [blame] | 912 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; | 
|  | 913 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 914 | DOUT << "Folded vreg: " << I->second.first << "  MR: " | 
|  | 915 | << I->second.second; | 
| Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 916 | unsigned VirtReg = I->second.first; | 
|  | 917 | VirtRegMap::ModRef MR = I->second.second; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 918 | if (!VRM.hasStackSlot(VirtReg)) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 919 | DOUT << ": No stack slot!\n"; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 920 | continue; | 
|  | 921 | } | 
|  | 922 | int SS = VRM.getStackSlot(VirtReg); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 923 | DOUT << " - StackSlot: " << SS << "\n"; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 924 |  | 
|  | 925 | // If this folded instruction is just a use, check to see if it's a | 
|  | 926 | // straight load from the virt reg slot. | 
|  | 927 | if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { | 
|  | 928 | int FrameIdx; | 
| Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 929 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 930 | if (FrameIdx == SS) { | 
|  | 931 | // If this spill slot is available, turn it into a copy (or nothing) | 
|  | 932 | // instead of leaving it as a load! | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 933 | MachineInstr *SSMI = NULL; | 
|  | 934 | if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 935 | DOUT << "Promoted Load To Copy: " << MI; | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 936 | MachineFunction &MF = *MBB.getParent(); | 
|  | 937 | if (DestReg != InReg) { | 
|  | 938 | MRI->copyRegToReg(MBB, &MI, DestReg, InReg, | 
|  | 939 | MF.getSSARegMap()->getRegClass(VirtReg)); | 
|  | 940 | // Revisit the copy so we make sure to notice the effects of the | 
|  | 941 | // operation on the destreg (either needing to RA it if it's | 
|  | 942 | // virtual or needing to clobber any values if it's physical). | 
|  | 943 | NextMII = &MI; | 
|  | 944 | --NextMII;  // backtrack to the copy. | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 945 | } else | 
|  | 946 | DOUT << "Removing now-noop copy: " << MI; | 
|  | 947 |  | 
| Evan Cheng | c0ba1bc | 2007-03-01 02:27:30 +0000 | [diff] [blame] | 948 | // Either way, the live range of the last kill of InReg has been | 
|  | 949 | // extended. Remove its kill. | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 950 | bool WasKill = false; | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 951 | if (SSMI) { | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 952 | int UIdx = SSMI->findRegisterUseOperand(InReg, true); | 
|  | 953 | if (UIdx != -1) { | 
|  | 954 | MachineOperand &MOK = SSMI->getOperand(UIdx); | 
|  | 955 | WasKill = MOK.isKill(); | 
|  | 956 | MOK.unsetIsKill(); | 
| Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 957 | } | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 958 | } | 
|  | 959 | if (NextMII != MBB.end()) { | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 960 | // If NextMII uses InReg and the use is not a two address | 
|  | 961 | // operand, mark it killed. | 
|  | 962 | int UIdx = NextMII->findRegisterUseOperand(InReg); | 
|  | 963 | if (UIdx != -1) { | 
|  | 964 | MachineOperand &MOU = NextMII->getOperand(UIdx); | 
|  | 965 | if (WasKill) { | 
|  | 966 | const TargetInstrDescriptor *NTID = | 
|  | 967 | NextMII->getInstrDescriptor(); | 
| Evan Cheng | 018d6e1 | 2007-03-27 00:48:28 +0000 | [diff] [blame] | 968 | if (UIdx >= NTID->numOperands || | 
|  | 969 | NTID->getOperandConstraint(UIdx, TOI::TIED_TO) == -1) | 
| Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 970 | MOU.setIsKill(); | 
|  | 971 | } | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 972 | Spills.addLastUse(InReg, &(*NextMII)); | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 973 | } | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 974 | } | 
| Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 975 |  | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 976 | VRM.RemoveFromFoldedVirtMap(&MI); | 
|  | 977 | MBB.erase(&MI); | 
|  | 978 | goto ProcessNextInst; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 979 | } | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 980 | } | 
|  | 981 | } | 
|  | 982 | } | 
|  | 983 |  | 
|  | 984 | // If this reference is not a use, any previous store is now dead. | 
|  | 985 | // Otherwise, the store to this stack slot is not dead anymore. | 
|  | 986 | std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); | 
|  | 987 | if (MDSI != MaybeDeadStores.end()) { | 
|  | 988 | if (MR & VirtRegMap::isRef)   // Previous store is not dead. | 
|  | 989 | MaybeDeadStores.erase(MDSI); | 
|  | 990 | else { | 
|  | 991 | // If we get here, the store is dead, nuke it now. | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 992 | assert(VirtRegMap::isMod && "Can't be modref!"); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 993 | DOUT << "Removed dead store:\t" << *MDSI->second; | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 994 | MBB.erase(MDSI->second); | 
| Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 995 | VRM.RemoveFromFoldedVirtMap(MDSI->second); | 
| Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 996 | MaybeDeadStores.erase(MDSI); | 
|  | 997 | ++NumDSE; | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 998 | } | 
|  | 999 | } | 
|  | 1000 |  | 
|  | 1001 | // If the spill slot value is available, and this is a new definition of | 
|  | 1002 | // the value, the value is not available anymore. | 
|  | 1003 | if (MR & VirtRegMap::isMod) { | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1004 | // Notice that the value in this stack slot has been modified. | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1005 | Spills.ModifyStackSlot(SS); | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1006 |  | 
|  | 1007 | // If this is *just* a mod of the value, check to see if this is just a | 
|  | 1008 | // store to the spill slot (i.e. the spill got merged into the copy). If | 
|  | 1009 | // so, realize that the vreg is available now, and add the store to the | 
|  | 1010 | // MaybeDeadStore info. | 
|  | 1011 | int StackSlot; | 
|  | 1012 | if (!(MR & VirtRegMap::isRef)) { | 
|  | 1013 | if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { | 
|  | 1014 | assert(MRegisterInfo::isPhysicalRegister(SrcReg) && | 
|  | 1015 | "Src hasn't been allocated yet?"); | 
| Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1016 | // Okay, this is certainly a store of SrcReg to [StackSlot].  Mark | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1017 | // this as a potentially dead store in case there is a subsequent | 
|  | 1018 | // store into the stack slot without a read from it. | 
|  | 1019 | MaybeDeadStores[StackSlot] = &MI; | 
|  | 1020 |  | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1021 | // If the stack slot value was previously available in some other | 
|  | 1022 | // register, change it now.  Otherwise, make the register available, | 
|  | 1023 | // in PhysReg. | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1024 | Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); | 
| Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1025 | } | 
|  | 1026 | } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1027 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1028 | } | 
|  | 1029 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1030 | // Process all of the spilled defs. | 
|  | 1031 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | 
|  | 1032 | MachineOperand &MO = MI.getOperand(i); | 
|  | 1033 | if (MO.isRegister() && MO.getReg() && MO.isDef()) { | 
|  | 1034 | unsigned VirtReg = MO.getReg(); | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1035 |  | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1036 | if (!MRegisterInfo::isVirtualRegister(VirtReg)) { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1037 | // Check to see if this is a noop copy.  If so, eliminate the | 
|  | 1038 | // instruction before considering the dest reg to be changed. | 
|  | 1039 | unsigned Src, Dst; | 
|  | 1040 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { | 
|  | 1041 | ++NumDCE; | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1042 | DOUT << "Removing now-noop copy: " << MI; | 
| Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 1043 | Spills.removeLastUse(Src, &MI); | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1044 | MBB.erase(&MI); | 
|  | 1045 | VRM.RemoveFromFoldedVirtMap(&MI); | 
| Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 1046 | Spills.disallowClobberPhysReg(VirtReg); | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1047 | goto ProcessNextInst; | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1048 | } | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1049 |  | 
|  | 1050 | // If it's not a no-op copy, it clobbers the value in the destreg. | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1051 | Spills.ClobberPhysReg(VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1052 | ReusedOperands.markClobbered(VirtReg); | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1053 |  | 
|  | 1054 | // Check to see if this instruction is a load from a stack slot into | 
|  | 1055 | // a register.  If so, this provides the stack slot value in the reg. | 
|  | 1056 | int FrameIdx; | 
|  | 1057 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { | 
|  | 1058 | assert(DestReg == VirtReg && "Unknown load situation!"); | 
|  | 1059 |  | 
|  | 1060 | // Otherwise, if it wasn't available, remember that it is now! | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1061 | Spills.addAvailable(FrameIdx, &MI, DestReg); | 
| Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1062 | goto ProcessNextInst; | 
|  | 1063 | } | 
|  | 1064 |  | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1065 | continue; | 
| Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 1066 | } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1067 |  | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1068 | // The only vregs left are stack slot definitions. | 
|  | 1069 | int StackSlot = VRM.getStackSlot(VirtReg); | 
|  | 1070 | const TargetRegisterClass *RC = | 
|  | 1071 | MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1072 |  | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1073 | // If this def is part of a two-address operand, make sure to execute | 
|  | 1074 | // the store from the correct physical register. | 
|  | 1075 | unsigned PhysReg; | 
| Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 1076 | int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); | 
| Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 1077 | if (TiedOp != -1) | 
|  | 1078 | PhysReg = MI.getOperand(TiedOp).getReg(); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1079 | else { | 
| Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1080 | PhysReg = VRM.getPhys(VirtReg); | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1081 | if (ReusedOperands.isClobbered(PhysReg)) { | 
|  | 1082 | // Another def has taken the assigned physreg. It must have been a | 
|  | 1083 | // use&def which got it due to reuse. Undo the reuse! | 
|  | 1084 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, | 
|  | 1085 | Spills, MaybeDeadStores); | 
|  | 1086 | } | 
|  | 1087 | } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1088 |  | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1089 | PhysRegsUsed[PhysReg] = true; | 
| Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1090 | ReusedOperands.markClobbered(PhysReg); | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1091 | MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1092 | DOUT << "Store:\t" << *next(MII); | 
| Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 1093 | MI.getOperand(i).setReg(PhysReg); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1094 |  | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1095 | // If there is a dead store to this stack slot, nuke it now. | 
|  | 1096 | MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; | 
|  | 1097 | if (LastStore) { | 
| Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1098 | DOUT << "Removed dead store:\t" << *LastStore; | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1099 | ++NumDSE; | 
|  | 1100 | MBB.erase(LastStore); | 
| Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 1101 | VRM.RemoveFromFoldedVirtMap(LastStore); | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1102 | } | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1103 | LastStore = next(MII); | 
|  | 1104 |  | 
|  | 1105 | // If the stack slot value was previously available in some other | 
|  | 1106 | // register, change it now.  Otherwise, make the register available, | 
|  | 1107 | // in PhysReg. | 
| Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1108 | Spills.ModifyStackSlot(StackSlot); | 
|  | 1109 | Spills.ClobberPhysReg(PhysReg); | 
| Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1110 | Spills.addAvailable(StackSlot, LastStore, PhysReg); | 
| Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1111 | ++NumStores; | 
| Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1112 |  | 
|  | 1113 | // Check to see if this is a noop copy.  If so, eliminate the | 
|  | 1114 | // instruction before considering the dest reg to be changed. | 
|  | 1115 | { | 
|  | 1116 | unsigned Src, Dst; | 
|  | 1117 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { | 
|  | 1118 | ++NumDCE; | 
|  | 1119 | DOUT << "Removing now-noop copy: " << MI; | 
|  | 1120 | MBB.erase(&MI); | 
|  | 1121 | VRM.RemoveFromFoldedVirtMap(&MI); | 
|  | 1122 | goto ProcessNextInst; | 
|  | 1123 | } | 
|  | 1124 | } | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1125 | } | 
|  | 1126 | } | 
| Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1127 | ProcessNextInst: | 
| Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1128 | MII = NextMII; | 
|  | 1129 | } | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1130 | } | 
|  | 1131 |  | 
| Chris Lattner | f7da2c7 | 2006-08-24 22:43:55 +0000 | [diff] [blame] | 1132 |  | 
|  | 1133 |  | 
| Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1134 | llvm::Spiller* llvm::createSpiller() { | 
|  | 1135 | switch (SpillerOpt) { | 
|  | 1136 | default: assert(0 && "Unreachable!"); | 
|  | 1137 | case local: | 
|  | 1138 | return new LocalSpiller(); | 
|  | 1139 | case simple: | 
|  | 1140 | return new SimpleSpiller(); | 
|  | 1141 | } | 
| Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 1142 | } |