blob: d651f9d05f14d1d54b761b3de8d179448e4831e6 [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
65 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000066 grow();
67}
68
Chris Lattner8c4d88d2004-09-30 01:54:45 +000069void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000070 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
71 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000072}
73
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000077 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000078 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
79 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
80 RC->getAlignment());
81 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 ++NumSpills;
83 return frameIndex;
84}
85
86void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
87 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000088 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000090 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000091}
92
Evan Cheng2638e1a2007-03-20 08:13:50 +000093int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
94 assert(MRegisterInfo::isVirtualRegister(virtReg));
95 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
96 "attempt to assign re-mat id to already spilled register");
97 Virt2StackSlotMap[virtReg] = ReMatId;
98 ++NumReMats;
99 return ReMatId++;
100}
101
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000102void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000103 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000104 // Move previous memory references folded to new instruction.
105 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000106 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
108 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000109 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000110 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000111
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000112 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000113 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
114 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000115 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000116 // Folded a two-address operand.
117 MRInfo = isModRef;
118 } else if (OldMI->getOperand(OpNo).isDef()) {
119 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000120 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000121 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000122 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000123
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000125 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000126}
127
Chris Lattner7f690e62004-09-30 02:15:18 +0000128void VirtRegMap::print(std::ostream &OS) const {
129 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000130
Chris Lattner7f690e62004-09-30 02:15:18 +0000131 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000132 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000133 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
134 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
135 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000136
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000137 }
138
139 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
141 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
142 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
143 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000144}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000145
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000146void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000147 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000148}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000149
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000150
151//===----------------------------------------------------------------------===//
152// Simple Spiller Implementation
153//===----------------------------------------------------------------------===//
154
155Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000156
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000157namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000158 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000159 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000160 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000161}
162
Chris Lattner35f27052006-05-01 21:16:03 +0000163bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000164 DOUT << "********** REWRITE MACHINE CODE **********\n";
165 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000166 const TargetMachine &TM = MF.getTarget();
167 const MRegisterInfo &MRI = *TM.getRegisterInfo();
168 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169
Chris Lattner4ea1b822004-09-30 02:33:48 +0000170 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
171 // each vreg once (in the case where a spilled vreg is used by multiple
172 // operands). This is always smaller than the number of operands to the
173 // current machine instr, so it should be small.
174 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000175
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000176 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
177 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000178 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000179 MachineBasicBlock &MBB = *MBBI;
180 for (MachineBasicBlock::iterator MII = MBB.begin(),
181 E = MBB.end(); MII != E; ++MII) {
182 MachineInstr &MI = *MII;
183 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000184 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000185 if (MO.isRegister() && MO.getReg())
186 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
187 unsigned VirtReg = MO.getReg();
188 unsigned PhysReg = VRM.getPhys(VirtReg);
189 if (VRM.hasStackSlot(VirtReg)) {
190 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000191 const TargetRegisterClass* RC =
192 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000193
Chris Lattner886dd912005-04-04 21:35:34 +0000194 if (MO.isUse() &&
195 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
196 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000197 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 LoadedRegs.push_back(VirtReg);
199 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000200 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000201 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000202
Chris Lattner886dd912005-04-04 21:35:34 +0000203 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000205 ++NumStores;
206 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000207 }
Chris Lattner886dd912005-04-04 21:35:34 +0000208 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000209 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000210 } else {
211 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000212 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000213 }
Chris Lattner886dd912005-04-04 21:35:34 +0000214
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000215 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000216 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000217 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000218 }
219 return true;
220}
221
222//===----------------------------------------------------------------------===//
223// Local Spiller Implementation
224//===----------------------------------------------------------------------===//
225
226namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 /// LocalSpiller - This spiller does a simple pass over the machine basic
228 /// block to attempt to keep spills in registers as much as possible for
229 /// blocks that have low register pressure (the vreg may be spilled due to
230 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000231 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000232 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000233 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000234 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000235 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000236 MRI = MF.getTarget().getRegisterInfo();
237 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000238 DOUT << "\n**** Local spiller rewriting function '"
239 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000240
Evan Cheng2638e1a2007-03-20 08:13:50 +0000241 std::vector<MachineInstr *> ReMatedMIs;
Chris Lattner7fb64342004-10-01 19:04:51 +0000242 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
243 MBB != E; ++MBB)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000244 RewriteMBB(*MBB, VRM, ReMatedMIs);
245 for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i)
246 delete ReMatedMIs[i];
Chris Lattner7fb64342004-10-01 19:04:51 +0000247 return true;
248 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000249 private:
Evan Cheng2638e1a2007-03-20 08:13:50 +0000250 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
251 std::vector<MachineInstr*> &ReMatedMIs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000252 };
253}
254
Chris Lattner66cf80f2006-02-03 23:13:58 +0000255/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
256/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000257///
258/// Note that not all physregs are created equal here. In particular, some
259/// physregs are reloads that we are allowed to clobber or ignore at any time.
260/// Other physregs are values that the register allocated program is using that
261/// we cannot CHANGE, but we can read if we like. We keep track of this on a
262/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
263/// entries. The predicate 'canClobberPhysReg()' checks this bit and
264/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000265namespace {
266class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000267 const MRegisterInfo *MRI;
268 const TargetInstrInfo *TII;
269
270 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
271 // register values that are still available, due to being loaded or stored to,
Evan Cheng6b448092007-03-02 08:52:00 +0000272 // but not invalidated yet. It also tracks the instructions that defined
Evan Chengde4e9422007-02-25 09:51:27 +0000273 // or used the register.
Evan Cheng6b448092007-03-02 08:52:00 +0000274 typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo;
Evan Cheng91e23902007-02-23 01:13:26 +0000275 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000276
277 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
278 // which stack slot values are currently held by a physreg. This is used to
279 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
280 std::multimap<unsigned, int> PhysRegsAvailable;
281
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000282 void disallowClobberPhysRegOnly(unsigned PhysReg);
283
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284 void ClobberPhysRegOnly(unsigned PhysReg);
285public:
286 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
287 : MRI(mri), TII(tii) {
288 }
289
Evan Cheng91e23902007-02-23 01:13:26 +0000290 const MRegisterInfo *getRegInfo() const { return MRI; }
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000293 /// physical register, return that PhysReg, otherwise return 0. It also
294 /// returns by reference the instruction that either defines or last uses
295 /// the register.
296 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
297 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
298 if (I != SpillSlotsAvailable.end()) {
Evan Cheng6b448092007-03-02 08:52:00 +0000299 if (!I->second.second.empty())
300 SSMI = I->second.second.back();
Evan Cheng91e23902007-02-23 01:13:26 +0000301 return I->second.first >> 1; // Remove the CanClobber bit.
302 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000303 return 0;
304 }
Evan Chengde4e9422007-02-25 09:51:27 +0000305
Evan Cheng6b448092007-03-02 08:52:00 +0000306 /// addLastUse - Add the last use information of all stack slots whose
Evan Chengde4e9422007-02-25 09:51:27 +0000307 /// values are available in the specific register.
Evan Cheng6b448092007-03-02 08:52:00 +0000308 void addLastUse(unsigned PhysReg, MachineInstr *Use) {
Evan Chengde4e9422007-02-25 09:51:27 +0000309 std::multimap<unsigned, int>::iterator I =
310 PhysRegsAvailable.lower_bound(PhysReg);
311 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
312 int Slot = I->second;
313 I++;
314
315 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
316 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
317 unsigned Val = II->second.first;
318 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
Evan Cheng7cb33c82007-03-30 20:21:35 +0000319 // This can be true if there are multiple uses of the same register.
320 if (II->second.second.back() != Use)
321 II->second.second.push_back(Use);
Evan Cheng6b448092007-03-02 08:52:00 +0000322 }
323 }
324
325 /// removeLastUse - Remove the last use information of all stack slots whose
326 /// values are available in the specific register.
327 void removeLastUse(unsigned PhysReg, MachineInstr *Use) {
328 std::multimap<unsigned, int>::iterator I =
329 PhysRegsAvailable.lower_bound(PhysReg);
330 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
331 int Slot = I->second;
332 I++;
333
334 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
335 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
336 unsigned Val = II->second.first;
337 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
338 if (II->second.second.back() == Use)
339 II->second.second.pop_back();
Evan Chengde4e9422007-02-25 09:51:27 +0000340 }
341 }
Chris Lattner540fec62006-02-25 01:51:33 +0000342
Chris Lattner66cf80f2006-02-03 23:13:58 +0000343 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000344 /// specified physreg. If CanClobber is true, the physreg can be modified at
345 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000346 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
347 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000348 // If this stack slot is thought to be available in some other physreg,
349 // remove its record.
350 ModifyStackSlot(Slot);
351
Chris Lattner66cf80f2006-02-03 23:13:58 +0000352 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng6b448092007-03-02 08:52:00 +0000353 std::vector<MachineInstr*> DefUses;
354 DefUses.push_back(MI);
Evan Cheng91e23902007-02-23 01:13:26 +0000355 SpillSlotsAvailable[Slot] =
Evan Cheng6b448092007-03-02 08:52:00 +0000356 std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000357
Evan Cheng2638e1a2007-03-20 08:13:50 +0000358 if (Slot > VirtRegMap::MAX_STACK_SLOT)
359 DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1;
360 else
361 DOUT << "Remembering SS#" << Slot;
362 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000363 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000364
Chris Lattner593c9582006-02-03 23:28:46 +0000365 /// canClobberPhysReg - Return true if the spiller is allowed to change the
366 /// value of the specified stackslot register if it desires. The specified
367 /// stack slot must be available in a physreg for this query to make sense.
368 bool canClobberPhysReg(int Slot) const {
369 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000370 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000371 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000372
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000373 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
374 /// stackslot register. The register is still available but is no longer
375 /// allowed to be modifed.
376 void disallowClobberPhysReg(unsigned PhysReg);
377
Chris Lattner66cf80f2006-02-03 23:13:58 +0000378 /// ClobberPhysReg - This is called when the specified physreg changes
379 /// value. We use this to invalidate any info about stuff we thing lives in
380 /// it and any of its aliases.
381 void ClobberPhysReg(unsigned PhysReg);
382
383 /// ModifyStackSlot - This method is called when the value in a stack slot
384 /// changes. This removes information about which register the previous value
385 /// for this slot lives in (as the previous value is dead now).
386 void ModifyStackSlot(int Slot);
387};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000388}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000389
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000390/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
391/// stackslot register. The register is still available but is no longer
392/// allowed to be modifed.
393void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
394 std::multimap<unsigned, int>::iterator I =
395 PhysRegsAvailable.lower_bound(PhysReg);
396 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
397 int Slot = I->second;
398 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000399 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000400 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000401 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000402 DOUT << "PhysReg " << MRI->getName(PhysReg)
403 << " copied, it is available for use but can no longer be modified\n";
404 }
405}
406
407/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
408/// stackslot register and its aliases. The register and its aliases may
409/// still available but is no longer allowed to be modifed.
410void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
411 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
412 disallowClobberPhysRegOnly(*AS);
413 disallowClobberPhysRegOnly(PhysReg);
414}
415
Chris Lattner66cf80f2006-02-03 23:13:58 +0000416/// ClobberPhysRegOnly - This is called when the specified physreg changes
417/// value. We use this to invalidate any info about stuff we thing lives in it.
418void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
419 std::multimap<unsigned, int>::iterator I =
420 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000421 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000422 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000423 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000424 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000425 "Bidirectional map mismatch!");
426 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000427 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000428 << " clobbered, invalidating ";
429 if (Slot > VirtRegMap::MAX_STACK_SLOT)
430 DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
431 else
432 DOUT << "SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000433 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000434}
435
Chris Lattner66cf80f2006-02-03 23:13:58 +0000436/// ClobberPhysReg - This is called when the specified physreg changes
437/// value. We use this to invalidate any info about stuff we thing lives in
438/// it and any of its aliases.
439void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000440 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000441 ClobberPhysRegOnly(*AS);
442 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000443}
444
Chris Lattner07cf1412006-02-03 00:36:31 +0000445/// ModifyStackSlot - This method is called when the value in a stack slot
446/// changes. This removes information about which register the previous value
447/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000448void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000449 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000450 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000451 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000452 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000453
454 // This register may hold the value of multiple stack slots, only remove this
455 // stack slot from the set of values the register contains.
456 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
457 for (; ; ++I) {
458 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
459 "Map inverse broken!");
460 if (I->second == Slot) break;
461 }
462 PhysRegsAvailable.erase(I);
463}
464
465
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000466
Chris Lattner7fb64342004-10-01 19:04:51 +0000467// ReusedOp - For each reused operand, we keep track of a bit of information, in
468// case we need to rollback upon processing a new operand. See comments below.
469namespace {
470 struct ReusedOp {
471 // The MachineInstr operand that reused an available value.
472 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000473
Chris Lattner7fb64342004-10-01 19:04:51 +0000474 // StackSlot - The spill slot of the value being reused.
475 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000476
Chris Lattner7fb64342004-10-01 19:04:51 +0000477 // PhysRegReused - The physical register the value was available in.
478 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000479
Chris Lattner7fb64342004-10-01 19:04:51 +0000480 // AssignedPhysReg - The physreg that was assigned for use by the reload.
481 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000482
483 // VirtReg - The virtual register itself.
484 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000485
Chris Lattner8a61a752005-10-06 17:19:06 +0000486 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
487 unsigned vreg)
488 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
489 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000490 };
Chris Lattner540fec62006-02-25 01:51:33 +0000491
492 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
493 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000494 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000495 MachineInstr &MI;
496 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000497 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000498 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000499 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000500 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000501 }
Chris Lattner540fec62006-02-25 01:51:33 +0000502
503 bool hasReuses() const {
504 return !Reuses.empty();
505 }
506
507 /// addReuse - If we choose to reuse a virtual register that is already
508 /// available instead of reloading it, remember that we did so.
509 void addReuse(unsigned OpNo, unsigned StackSlot,
510 unsigned PhysRegReused, unsigned AssignedPhysReg,
511 unsigned VirtReg) {
512 // If the reload is to the assigned register anyway, no undo will be
513 // required.
514 if (PhysRegReused == AssignedPhysReg) return;
515
516 // Otherwise, remember this.
517 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
518 AssignedPhysReg, VirtReg));
519 }
Evan Chenge077ef62006-11-04 00:21:55 +0000520
521 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000522 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000523 }
524
525 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000526 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000527 }
Chris Lattner540fec62006-02-25 01:51:33 +0000528
529 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
530 /// is some other operand that is using the specified register, either pick
531 /// a new register to use, or evict the previous reload and use this reg.
532 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
533 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000534 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000535 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000536 if (Reuses.empty()) return PhysReg; // This is most often empty.
537
538 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
539 ReusedOp &Op = Reuses[ro];
540 // If we find some other reuse that was supposed to use this register
541 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000542 // register. That is, unless its reload register has already been
543 // considered and subsequently rejected because it has also been reused
544 // by another operand.
545 if (Op.PhysRegReused == PhysReg &&
546 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000547 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000548 unsigned NewReg = Op.AssignedPhysReg;
549 Rejected.insert(PhysReg);
550 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000551 } else {
552 // Otherwise, we might also have a problem if a previously reused
553 // value aliases the new register. If so, codegen the previous reload
554 // and use this one.
555 unsigned PRRU = Op.PhysRegReused;
556 const MRegisterInfo *MRI = Spills.getRegInfo();
557 if (MRI->areAliases(PRRU, PhysReg)) {
558 // Okay, we found out that an alias of a reused register
559 // was used. This isn't good because it means we have
560 // to undo a previous reuse.
561 MachineBasicBlock *MBB = MI->getParent();
562 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000563 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
564
565 // Copy Op out of the vector and remove it, we're going to insert an
566 // explicit load for it.
567 ReusedOp NewOp = Op;
568 Reuses.erase(Reuses.begin()+ro);
569
570 // Ok, we're going to try to reload the assigned physreg into the
571 // slot that we were supposed to in the first place. However, that
572 // register could hold a reuse. Check to see if it conflicts or
573 // would prefer us to use a different register.
574 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000575 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000576
577 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
578 NewOp.StackSlot, AliasRC);
579 Spills.ClobberPhysReg(NewPhysReg);
580 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000581
582 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000583 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000584
Chris Lattnere53f4a02006-05-04 17:52:23 +0000585 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000586
Evan Cheng91e23902007-02-23 01:13:26 +0000587 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000588 ++NumLoads;
589 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000590 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000591
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000592 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000593 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000594
595 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000596 return PhysReg;
597 }
598 }
599 }
600 return PhysReg;
601 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000602
603 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
604 /// 'Rejected' set to remember which registers have been considered and
605 /// rejected for the reload. This avoids infinite looping in case like
606 /// this:
607 /// t1 := op t2, t3
608 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
609 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
610 /// t1 <- desires r1
611 /// sees r1 is taken by t2, tries t2's reload register r0
612 /// sees r0 is taken by t3, tries t3's reload register r1
613 /// sees r1 is taken by t2, tries t2's reload register r0 ...
614 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
615 AvailableSpills &Spills,
616 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000617 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000618 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
619 }
Chris Lattner540fec62006-02-25 01:51:33 +0000620 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000621}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000622
Chris Lattner7fb64342004-10-01 19:04:51 +0000623
624/// rewriteMBB - Keep track of which spills are available even after the
625/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000626void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
627 std::vector<MachineInstr*> &ReMatedMIs) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000628
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000629 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000630
Chris Lattner66cf80f2006-02-03 23:13:58 +0000631 // Spills - Keep track of which spilled values are available in physregs so
632 // that we can choose to reuse the physregs instead of emitting reloads.
633 AvailableSpills Spills(MRI, TII);
634
Chris Lattner52b25db2004-10-01 19:47:12 +0000635 // MaybeDeadStores - When we need to write a value back into a stack slot,
636 // keep track of the inserted store. If the stack slot value is never read
637 // (because the value was used from some available register, for example), and
638 // subsequently stored to, the original store is dead. This map keeps track
639 // of inserted stores that are not used. If we see a subsequent store to the
640 // same stack slot, the original store is deleted.
641 std::map<int, MachineInstr*> MaybeDeadStores;
642
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000643 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
644
Chris Lattner7fb64342004-10-01 19:04:51 +0000645 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
646 MII != E; ) {
647 MachineInstr &MI = *MII;
648 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
649
Chris Lattner540fec62006-02-25 01:51:33 +0000650 /// ReusedOperands - Keep track of operand reuse in case we need to undo
651 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000652 ReuseInfo ReusedOperands(MI, MRI);
653
654 // Loop over all of the implicit defs, clearing them from our available
655 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000656 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng2638e1a2007-03-20 08:13:50 +0000657
658 // If this instruction is being rematerialized, just remove it!
659 if (TID->Flags & M_REMATERIALIZIBLE) {
660 bool Remove = true;
661 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
662 MachineOperand &MO = MI.getOperand(i);
663 if (!MO.isRegister() || MO.getReg() == 0)
664 continue; // Ignore non-register operands.
665 if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) {
666 Remove = false;
667 break;
668 }
669 }
670 if (Remove) {
671 VRM.RemoveFromFoldedVirtMap(&MI);
672 ReMatedMIs.push_back(MI.removeFromParent());
673 MII = NextMII;
674 continue;
675 }
676 }
677
Evan Cheng86facc22006-12-15 06:41:01 +0000678 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000679 if (ImpDef) {
680 for ( ; *ImpDef; ++ImpDef) {
681 PhysRegsUsed[*ImpDef] = true;
682 ReusedOperands.markClobbered(*ImpDef);
683 Spills.ClobberPhysReg(*ImpDef);
684 }
685 }
686
Chris Lattner7fb64342004-10-01 19:04:51 +0000687 // Process all of the spilled uses and all non spilled reg references.
688 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
689 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000690 if (!MO.isRegister() || MO.getReg() == 0)
691 continue; // Ignore non-register operands.
692
693 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
694 // Ignore physregs for spilling, but remember that it is used by this
695 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000696 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000697 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000698 continue;
699 }
700
701 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
702 "Not a virtual or a physical register?");
703
704 unsigned VirtReg = MO.getReg();
705 if (!VRM.hasStackSlot(VirtReg)) {
706 // This virtual register was assigned a physreg!
707 unsigned Phys = VRM.getPhys(VirtReg);
708 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000709 if (MO.isDef())
710 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000711 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000712 continue;
713 }
714
715 // This virtual register is now known to be a spilled value.
716 if (!MO.isUse())
717 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000718
Evan Cheng2638e1a2007-03-20 08:13:50 +0000719 bool doReMat = VRM.isReMaterialized(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000720 int StackSlot = VRM.getStackSlot(VirtReg);
721 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000722
Chris Lattner50ea01e2005-09-09 20:29:51 +0000723 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000724 MachineInstr *SSMI = NULL;
725 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000726 // This spilled operand might be part of a two-address operand. If this
727 // is the case, then changing it will necessarily require changing the
728 // def part of the instruction as well. However, in some cases, we
729 // aren't allowed to modify the reused register. If none of these cases
730 // apply, reuse it.
731 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000732 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000733 if (ti != -1 &&
734 MI.getOperand(ti).isReg() &&
735 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000736 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000737 // long as we are allowed to clobber the value and there isn't an
738 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000739 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
740 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000741 }
742
743 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000744 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000745 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
746 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
747 else
748 DOUT << "Reusing SS#" << StackSlot;
749 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000750 << MRI->getName(PhysReg) << " for vreg"
751 << VirtReg <<" instead of reloading into physreg "
752 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000753 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000754
Evan Cheng91e23902007-02-23 01:13:26 +0000755 // Extend the live range of the MI that last kill the register if
756 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000757 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000758 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000759 int UIdx = SSMI->findRegisterUseOperand(PhysReg, true);
760 if (UIdx != -1) {
761 MachineOperand &MOK = SSMI->getOperand(UIdx);
762 WasKill = MOK.isKill();
763 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000764 }
Evan Cheng6b448092007-03-02 08:52:00 +0000765 }
766 if (ti == -1) {
767 // Unless it's the use of a two-address code, transfer the kill
768 // of the reused register to this use.
Evan Chenga7288df2007-03-03 06:32:37 +0000769 if (WasKill)
770 MI.getOperand(i).setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000771 Spills.addLastUse(PhysReg, &MI);
Evan Cheng50d25d72007-02-23 21:47:50 +0000772 }
Evan Cheng91e23902007-02-23 01:13:26 +0000773
Chris Lattneraddc55a2006-04-28 01:46:50 +0000774 // The only technical detail we have is that we don't know that
775 // PhysReg won't be clobbered by a reloaded stack slot that occurs
776 // later in the instruction. In particular, consider 'op V1, V2'.
777 // If V1 is available in physreg R0, we would choose to reuse it
778 // here, instead of reloading it into the register the allocator
779 // indicated (say R1). However, V2 might have to be reloaded
780 // later, and it might indicate that it needs to live in R0. When
781 // this occurs, we need to have information available that
782 // indicates it is safe to use R1 for the reload instead of R0.
783 //
784 // To further complicate matters, we might conflict with an alias,
785 // or R0 and R1 might not be compatible with each other. In this
786 // case, we actually insert a reload for V1 in R1, ensuring that
787 // we can get at R0 or its alias.
788 ReusedOperands.addReuse(i, StackSlot, PhysReg,
789 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000790 if (ti != -1)
791 // Only mark it clobbered if this is a use&def operand.
792 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000793 ++NumReused;
794 continue;
795 }
796
797 // Otherwise we have a situation where we have a two-address instruction
798 // whose mod/ref operand needs to be reloaded. This reload is already
799 // available in some register "PhysReg", but if we used PhysReg as the
800 // operand to our 2-addr instruction, the instruction would modify
801 // PhysReg. This isn't cool if something later uses PhysReg and expects
802 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000803 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000804 // To avoid this problem, and to avoid doing a load right after a store,
805 // we emit a copy from PhysReg into the designated register for this
806 // operand.
807 unsigned DesignatedReg = VRM.getPhys(VirtReg);
808 assert(DesignatedReg && "Must map virtreg to physreg!");
809
810 // Note that, if we reused a register for a previous operand, the
811 // register we want to reload into might not actually be
812 // available. If this occurs, use the register indicated by the
813 // reuser.
814 if (ReusedOperands.hasReuses())
815 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
816 Spills, MaybeDeadStores);
817
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000818 // If the mapped designated register is actually the physreg we have
819 // incoming, we don't need to inserted a dead copy.
820 if (DesignatedReg == PhysReg) {
821 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000822 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
823 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
824 else
825 DOUT << "Reusing SS#" << StackSlot;
826 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000827 << VirtReg
828 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000829 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000830 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000831 ++NumReused;
832 continue;
833 }
834
Chris Lattneraddc55a2006-04-28 01:46:50 +0000835 const TargetRegisterClass* RC =
836 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
837
838 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000839 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000840 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000841
842 // Extend the live range of the MI that last kill the register if
843 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000844 bool WasKill = false;
Evan Chengde4e9422007-02-25 09:51:27 +0000845 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000846 int UIdx = SSMI->findRegisterUseOperand(PhysReg, true);
847 if (UIdx != -1) {
848 MachineOperand &MOK = SSMI->getOperand(UIdx);
849 WasKill = MOK.isKill();
850 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000851 }
Evan Chengde4e9422007-02-25 09:51:27 +0000852 }
Evan Cheng6b448092007-03-02 08:52:00 +0000853 MachineInstr *CopyMI = prior(MII);
Evan Chenga7288df2007-03-03 06:32:37 +0000854 if (WasKill) {
855 // Transfer kill to the next use.
Evan Chengad7ccf32007-03-26 22:40:42 +0000856 int UIdx = CopyMI->findRegisterUseOperand(PhysReg);
857 assert(UIdx != -1);
858 MachineOperand &MOU = CopyMI->getOperand(UIdx);
859 MOU.setIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000860 }
861 Spills.addLastUse(PhysReg, CopyMI);
Evan Chengde4e9422007-02-25 09:51:27 +0000862
Chris Lattneraddc55a2006-04-28 01:46:50 +0000863 // This invalidates DesignatedReg.
864 Spills.ClobberPhysReg(DesignatedReg);
865
Evan Cheng91e23902007-02-23 01:13:26 +0000866 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000867 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000868 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000869 ++NumReused;
870 continue;
871 }
872
873 // Otherwise, reload it and remember that we have it.
874 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000875 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000876 const TargetRegisterClass* RC =
877 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000878
Chris Lattner50ea01e2005-09-09 20:29:51 +0000879 // Note that, if we reused a register for a previous operand, the
880 // register we want to reload into might not actually be
881 // available. If this occurs, use the register indicated by the
882 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000883 if (ReusedOperands.hasReuses())
884 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
885 Spills, MaybeDeadStores);
886
Chris Lattner50ea01e2005-09-09 20:29:51 +0000887 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000888 ReusedOperands.markClobbered(PhysReg);
Evan Cheng2638e1a2007-03-20 08:13:50 +0000889 if (doReMat)
890 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
891 else
892 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000893 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000894 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000895
896 // Any stores to this stack slot are not dead anymore.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000897 if (!doReMat)
898 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000899 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000900 // Assumes this is the last use. IsKill will be unset if reg is reused
901 // unless it's a two-address operand.
902 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
903 MI.getOperand(i).setIsKill();
Chris Lattner50ea01e2005-09-09 20:29:51 +0000904 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000905 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000906 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000907 }
908
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000909 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000910
Chris Lattner7fb64342004-10-01 19:04:51 +0000911 // If we have folded references to memory operands, make sure we clear all
912 // physical registers that may contain the value of the spilled virtual
913 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000914 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
915 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000916 DOUT << "Folded vreg: " << I->second.first << " MR: "
917 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000918 unsigned VirtReg = I->second.first;
919 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000920 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000921 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000922 continue;
923 }
924 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000925 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000926
927 // If this folded instruction is just a use, check to see if it's a
928 // straight load from the virt reg slot.
929 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
930 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000931 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000932 if (FrameIdx == SS) {
933 // If this spill slot is available, turn it into a copy (or nothing)
934 // instead of leaving it as a load!
Evan Chengde4e9422007-02-25 09:51:27 +0000935 MachineInstr *SSMI = NULL;
936 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000937 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000938 MachineFunction &MF = *MBB.getParent();
939 if (DestReg != InReg) {
940 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
941 MF.getSSARegMap()->getRegClass(VirtReg));
942 // Revisit the copy so we make sure to notice the effects of the
943 // operation on the destreg (either needing to RA it if it's
944 // virtual or needing to clobber any values if it's physical).
945 NextMII = &MI;
946 --NextMII; // backtrack to the copy.
Evan Chengde4e9422007-02-25 09:51:27 +0000947 } else
948 DOUT << "Removing now-noop copy: " << MI;
949
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000950 // Either way, the live range of the last kill of InReg has been
951 // extended. Remove its kill.
Evan Chenga7288df2007-03-03 06:32:37 +0000952 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000953 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000954 int UIdx = SSMI->findRegisterUseOperand(InReg, true);
955 if (UIdx != -1) {
956 MachineOperand &MOK = SSMI->getOperand(UIdx);
957 WasKill = MOK.isKill();
958 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000959 }
Evan Cheng6b448092007-03-02 08:52:00 +0000960 }
961 if (NextMII != MBB.end()) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000962 // If NextMII uses InReg and the use is not a two address
963 // operand, mark it killed.
964 int UIdx = NextMII->findRegisterUseOperand(InReg);
965 if (UIdx != -1) {
966 MachineOperand &MOU = NextMII->getOperand(UIdx);
967 if (WasKill) {
968 const TargetInstrDescriptor *NTID =
969 NextMII->getInstrDescriptor();
Evan Cheng018d6e12007-03-27 00:48:28 +0000970 if (UIdx >= NTID->numOperands ||
971 NTID->getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
Evan Chengad7ccf32007-03-26 22:40:42 +0000972 MOU.setIsKill();
973 }
Evan Cheng6b448092007-03-02 08:52:00 +0000974 Spills.addLastUse(InReg, &(*NextMII));
Evan Chengde4e9422007-02-25 09:51:27 +0000975 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000976 }
Evan Chengde4e9422007-02-25 09:51:27 +0000977
Chris Lattner6ec36262006-10-12 17:45:38 +0000978 VRM.RemoveFromFoldedVirtMap(&MI);
979 MBB.erase(&MI);
980 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000981 }
Chris Lattnercea86882005-09-19 06:56:21 +0000982 }
983 }
984 }
985
986 // If this reference is not a use, any previous store is now dead.
987 // Otherwise, the store to this stack slot is not dead anymore.
988 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
989 if (MDSI != MaybeDeadStores.end()) {
990 if (MR & VirtRegMap::isRef) // Previous store is not dead.
991 MaybeDeadStores.erase(MDSI);
992 else {
993 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000994 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000995 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000996 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000997 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000998 MaybeDeadStores.erase(MDSI);
999 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001000 }
1001 }
1002
1003 // If the spill slot value is available, and this is a new definition of
1004 // the value, the value is not available anymore.
1005 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001006 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001007 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001008
1009 // If this is *just* a mod of the value, check to see if this is just a
1010 // store to the spill slot (i.e. the spill got merged into the copy). If
1011 // so, realize that the vreg is available now, and add the store to the
1012 // MaybeDeadStore info.
1013 int StackSlot;
1014 if (!(MR & VirtRegMap::isRef)) {
1015 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1016 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1017 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001018 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001019 // this as a potentially dead store in case there is a subsequent
1020 // store into the stack slot without a read from it.
1021 MaybeDeadStores[StackSlot] = &MI;
1022
Chris Lattnercd816392006-02-02 23:29:36 +00001023 // If the stack slot value was previously available in some other
1024 // register, change it now. Otherwise, make the register available,
1025 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001026 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001027 }
1028 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001029 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001030 }
1031
Chris Lattner7fb64342004-10-01 19:04:51 +00001032 // Process all of the spilled defs.
1033 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1034 MachineOperand &MO = MI.getOperand(i);
1035 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1036 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001037
Chris Lattner7fb64342004-10-01 19:04:51 +00001038 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001039 // Check to see if this is a noop copy. If so, eliminate the
1040 // instruction before considering the dest reg to be changed.
1041 unsigned Src, Dst;
1042 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1043 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001044 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng6b448092007-03-02 08:52:00 +00001045 Spills.removeLastUse(Src, &MI);
Chris Lattner29268692006-09-05 02:12:02 +00001046 MBB.erase(&MI);
1047 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001048 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001049 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001050 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001051
1052 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001053 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001054 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001055
1056 // Check to see if this instruction is a load from a stack slot into
1057 // a register. If so, this provides the stack slot value in the reg.
1058 int FrameIdx;
1059 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1060 assert(DestReg == VirtReg && "Unknown load situation!");
1061
1062 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001063 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001064 goto ProcessNextInst;
1065 }
1066
Chris Lattner29268692006-09-05 02:12:02 +00001067 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001068 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001069
Chris Lattner84e752a2006-02-03 03:06:49 +00001070 // The only vregs left are stack slot definitions.
1071 int StackSlot = VRM.getStackSlot(VirtReg);
1072 const TargetRegisterClass *RC =
1073 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001074
Chris Lattner29268692006-09-05 02:12:02 +00001075 // If this def is part of a two-address operand, make sure to execute
1076 // the store from the correct physical register.
1077 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001078 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001079 if (TiedOp != -1)
1080 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001081 else {
Chris Lattner29268692006-09-05 02:12:02 +00001082 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001083 if (ReusedOperands.isClobbered(PhysReg)) {
1084 // Another def has taken the assigned physreg. It must have been a
1085 // use&def which got it due to reuse. Undo the reuse!
1086 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1087 Spills, MaybeDeadStores);
1088 }
1089 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001090
Chris Lattner84e752a2006-02-03 03:06:49 +00001091 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +00001092 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001093 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001094 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001095 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001096
Chris Lattner84e752a2006-02-03 03:06:49 +00001097 // If there is a dead store to this stack slot, nuke it now.
1098 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1099 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001100 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001101 ++NumDSE;
1102 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001103 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001104 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001105 LastStore = next(MII);
1106
1107 // If the stack slot value was previously available in some other
1108 // register, change it now. Otherwise, make the register available,
1109 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001110 Spills.ModifyStackSlot(StackSlot);
1111 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001112 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001113 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001114
1115 // Check to see if this is a noop copy. If so, eliminate the
1116 // instruction before considering the dest reg to be changed.
1117 {
1118 unsigned Src, Dst;
1119 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1120 ++NumDCE;
1121 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng7cb33c82007-03-30 20:21:35 +00001122 Spills.removeLastUse(Src, &MI);
Evan Chengf50d09a2007-02-08 06:04:54 +00001123 MBB.erase(&MI);
1124 VRM.RemoveFromFoldedVirtMap(&MI);
1125 goto ProcessNextInst;
1126 }
1127 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001128 }
1129 }
Chris Lattnercea86882005-09-19 06:56:21 +00001130 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +00001131 MII = NextMII;
1132 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001133}
1134
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001135
1136
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001137llvm::Spiller* llvm::createSpiller() {
1138 switch (SpillerOpt) {
1139 default: assert(0 && "Unreachable!");
1140 case local:
1141 return new LocalSpiller();
1142 case simple:
1143 return new SimpleSpiller();
1144 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001145}