Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 43 | #define MDP_MIN_FETCH 9 |
| 44 | #define MDSS_MDP_MAX_FETCH 12 |
| 45 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 46 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 47 | |
| 48 | static int mdp_rev; |
| 49 | |
| 50 | void mdp_set_revision(int rev) |
| 51 | { |
| 52 | mdp_rev = rev; |
| 53 | } |
| 54 | |
| 55 | int mdp_get_revision() |
| 56 | { |
| 57 | return mdp_rev; |
| 58 | } |
| 59 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 60 | uint32_t mdss_mdp_intf_offset() |
| 61 | { |
| 62 | uint32_t mdss_mdp_intf_off; |
| 63 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 64 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 65 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 66 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 67 | mdss_mdp_intf_off = 0x59100; |
| 68 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 69 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 70 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 71 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 72 | |
| 73 | return mdss_mdp_intf_off; |
| 74 | } |
| 75 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 76 | void mdp_clk_gating_ctrl(void) |
| 77 | { |
| 78 | writel(0x40000000, MDP_CLK_CTRL0); |
| 79 | udelay(20); |
| 80 | writel(0x40000040, MDP_CLK_CTRL0); |
| 81 | writel(0x40000000, MDP_CLK_CTRL1); |
| 82 | writel(0x00400000, MDP_CLK_CTRL3); |
| 83 | udelay(20); |
| 84 | writel(0x00404000, MDP_CLK_CTRL3); |
| 85 | writel(0x40000000, MDP_CLK_CTRL4); |
| 86 | } |
| 87 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 88 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 89 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 90 | { |
| 91 | switch (pinfo->pipe_type) { |
| 92 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 93 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 94 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 95 | break; |
| 96 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 97 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 98 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 99 | break; |
| 100 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 101 | default: |
| 102 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 103 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 104 | break; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 109 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 110 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 111 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 112 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 113 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 114 | switch (pinfo->pipe_type) { |
| 115 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 116 | if (dual_pipe_single_ctl) |
| 117 | *ctl0_reg_val = 0x220D8; |
| 118 | else |
| 119 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 120 | *ctl1_reg_val = 0x24090; |
| 121 | break; |
| 122 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 123 | if (dual_pipe_single_ctl) |
| 124 | *ctl0_reg_val = 0x238C0; |
| 125 | else |
| 126 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 127 | *ctl1_reg_val = 0x25080; |
| 128 | break; |
| 129 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 130 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 131 | if (dual_pipe_single_ctl) |
| 132 | *ctl0_reg_val = 0x220C3; |
| 133 | else |
| 134 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 135 | *ctl1_reg_val = 0x24082; |
| 136 | break; |
| 137 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 138 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 139 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 140 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 141 | if (pinfo->dest == DISPLAY_2) { |
| 142 | *ctl0_reg_val |= BIT(31); |
| 143 | *ctl1_reg_val |= BIT(30); |
| 144 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 145 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 146 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 147 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 148 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
| 149 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 150 | if (pinfo->dest == DISPLAY_2) { |
| 151 | *ctl0_reg_val |= BIT(29); |
| 152 | *ctl1_reg_val |= BIT(30); |
| 153 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 154 | *ctl0_reg_val |= BIT(30); |
| 155 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 156 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 157 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 158 | } |
| 159 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 160 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 161 | *pinfo, uint32_t pipe_base) |
| 162 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 163 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 164 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 165 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 166 | uint32_t src_xy = 0, dst_xy = 0; |
| 167 | uint32_t height, width; |
| 168 | |
| 169 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 170 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 171 | |
| 172 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 173 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 174 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 175 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 176 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 177 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 178 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 179 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 180 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | stride = (fb->stride * fb->bpp/8); |
| 184 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 185 | if (fb_off == 0) { /* left */ |
| 186 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 187 | src_xy = dst_xy; |
| 188 | } else { /* right */ |
| 189 | dst_xy = (pinfo->border_top << 16); |
| 190 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 191 | } |
| 192 | |
| 193 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 194 | __func__, out_size, fb_off, src_xy, dst_xy); |
| 195 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 196 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 197 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 198 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 199 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 200 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 201 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 202 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 203 | |
| 204 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 205 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 206 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 207 | |
| 208 | /* bit(0) is set if hflip is required. |
| 209 | * bit(1) is set if vflip is required. |
| 210 | */ |
| 211 | if (pinfo->orientation & 0x1) |
| 212 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 213 | if (pinfo->orientation & 0x2) |
| 214 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
| 215 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 216 | } |
| 217 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 218 | static void mdss_vbif_setup() |
| 219 | { |
| 220 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 221 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 222 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 223 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 224 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 225 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 226 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 227 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 228 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 229 | |
| 230 | /* |
| 231 | * Following configuration is needed because on some versions, |
| 232 | * recommended reset values are not stored. |
| 233 | */ |
| 234 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 235 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 236 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 237 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 238 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 239 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 240 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 241 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 242 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 243 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 244 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 245 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 246 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 247 | } |
| 248 | } |
| 249 | } |
| 250 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 251 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 252 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 253 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 254 | uint32_t i, j; |
| 255 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 256 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 257 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 258 | /* max 3 MMB per register */ |
| 259 | reg_val |= client_id << (((j++) % 3) * 8); |
| 260 | if ((j % 3) == 0) { |
| 261 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 262 | free_smp_offset); |
| 263 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 264 | free_smp_offset); |
| 265 | reg_val = 0; |
| 266 | free_smp_offset += 4; |
| 267 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 270 | if (j % 3) { |
| 271 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 272 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 273 | free_smp_offset += 4; |
| 274 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 275 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 276 | return free_smp_offset; |
| 277 | } |
| 278 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 279 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 280 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 281 | { |
| 282 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 283 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 284 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 285 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
| 286 | switch (pinfo->pipe_type) { |
| 287 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 288 | *left_sspp_client_id = 0x7; /* 7 */ |
| 289 | *right_sspp_client_id = 0x11; /* 17 */ |
| 290 | break; |
| 291 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 292 | *left_sspp_client_id = 0x4; /* 4 */ |
| 293 | *right_sspp_client_id = 0xD; /* 13 */ |
| 294 | break; |
| 295 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 296 | default: |
| 297 | *left_sspp_client_id = 0x1; /* 1 */ |
| 298 | *right_sspp_client_id = 0x4; /* 4 */ |
| 299 | break; |
| 300 | } |
| 301 | } else { |
| 302 | switch (pinfo->pipe_type) { |
| 303 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 304 | *left_sspp_client_id = 0x10; /* 16 */ |
| 305 | *right_sspp_client_id = 0x11; /* 17 */ |
| 306 | break; |
| 307 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 308 | *left_sspp_client_id = 0xA; /* 10 */ |
| 309 | *right_sspp_client_id = 0xD; /* 13 */ |
| 310 | break; |
| 311 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 312 | default: |
| 313 | *left_sspp_client_id = 0x1; /* 1 */ |
| 314 | *right_sspp_client_id = 0x4; /* 4 */ |
| 315 | break; |
| 316 | } |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 321 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 322 | { |
| 323 | switch (pinfo->pipe_type) { |
| 324 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 325 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 326 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 327 | break; |
| 328 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 329 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 330 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 331 | break; |
| 332 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 333 | default: |
| 334 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 335 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 336 | break; |
| 337 | } |
| 338 | } |
| 339 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 340 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 341 | uint32_t right_pipe) |
| 342 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 343 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 344 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 345 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 346 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 347 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 348 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 349 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 350 | /* 8Kb per SMP on 8916 */ |
| 351 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 352 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 353 | /* 10Kb per SMP on 8939 */ |
| 354 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 355 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 356 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 357 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 358 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 359 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 360 | fixed_smp_cnt = 2; |
| 361 | else |
| 362 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 363 | } |
| 364 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 365 | mdp_select_pipe_client_id(pinfo, |
| 366 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 367 | |
| 368 | /* Each pipe driving half the screen */ |
| 369 | if (pinfo->lcdc.dual_pipe) |
| 370 | xres /= 2; |
| 371 | |
| 372 | /* bpp = bytes per pixel of input image */ |
| 373 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 374 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 375 | |
| 376 | if (smp_cnt > 4) { |
| 377 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 378 | smp_cnt); |
| 379 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 380 | } |
| 381 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 382 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 383 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 384 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 385 | |
| 386 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 387 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 388 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 389 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 390 | } |
| 391 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 392 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 393 | fixed_smp_cnt, free_smp_offset); |
| 394 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 395 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 396 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 397 | } |
| 398 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 399 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 400 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 401 | uint32_t hsync_period, vsync_period; |
| 402 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 403 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 404 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 405 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 406 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 407 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 408 | |
| 409 | if (pinfo == NULL) |
| 410 | return ERR_INVALID_ARGS; |
| 411 | |
| 412 | lcdc = &(pinfo->lcdc); |
| 413 | if (lcdc == NULL) |
| 414 | return ERR_INVALID_ARGS; |
| 415 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 416 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 417 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 418 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 419 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 420 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 421 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 422 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 423 | } |
| 424 | } |
| 425 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 426 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
| 427 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 428 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 429 | } |
| 430 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 431 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 432 | pinfo->fbc.comp_ratio = 1; |
| 433 | |
| 434 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 435 | itp.yres = pinfo->yres; |
| 436 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 437 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 438 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 439 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 440 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 441 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 442 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 443 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 444 | |
| 445 | itp.border_clr = pinfo->lcdc.border_clr; |
| 446 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 447 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 448 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 449 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 450 | itp.width + itp.h_front_porch; |
| 451 | |
| 452 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 453 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 454 | |
| 455 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 456 | itp.hsync_pulse_width + |
| 457 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 458 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 459 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 460 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 461 | display_vstart = (itp.vsync_pulse_width + |
| 462 | itp.v_back_porch) |
| 463 | * hsync_period + itp.hsync_skew; |
| 464 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 465 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 466 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 467 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 468 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 469 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 470 | } |
| 471 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 472 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 473 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 474 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 475 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 476 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 477 | intf_base); |
| 478 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 479 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 480 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 481 | intf_base); |
| 482 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 483 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 484 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 485 | intf_base); |
| 486 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 487 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 488 | intf_base); |
| 489 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 490 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 491 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 492 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 493 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 494 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 495 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 496 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 497 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 498 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 499 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 500 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 501 | } |
| 502 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 503 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 504 | uint32_t intf_base) |
| 505 | { |
| 506 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 507 | uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines; |
| 508 | uint32_t adjust_xres = 0; |
| 509 | |
| 510 | struct lcdc_panel_info *lcdc = NULL; |
| 511 | |
| 512 | if (pinfo == NULL) |
| 513 | return; |
| 514 | |
| 515 | lcdc = &(pinfo->lcdc); |
| 516 | if (lcdc == NULL) |
| 517 | return; |
| 518 | |
| 519 | /* |
| 520 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 521 | * Programmable fetch is not needed if vertical back porch |
| 522 | * is >= 9. |
| 523 | */ |
| 524 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
| 525 | lcdc->v_back_porch >= MDP_MIN_FETCH) |
| 526 | return; |
| 527 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 528 | adjust_xres = pinfo->xres; |
| 529 | if (pinfo->lcdc.split_display) |
| 530 | adjust_xres /= 2; |
| 531 | |
| 532 | /* |
| 533 | * Fetch should always be outside the active lines. If the fetching |
| 534 | * is programmed within active region, hardware behavior is unknown. |
| 535 | */ |
| 536 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 537 | lcdc->v_front_porch; |
| 538 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 539 | lcdc->h_front_porch; |
| 540 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 541 | |
| 542 | fetch_lines = v_total - vfp_start; |
| 543 | |
| 544 | /* |
| 545 | * In some cases, vertical front porch is too high. In such cases limit |
| 546 | * the mdp fetch lines as the last 12 lines of vertical front porch. |
| 547 | */ |
| 548 | if (fetch_lines > MDSS_MDP_MAX_FETCH) |
| 549 | fetch_lines = MDSS_MDP_MAX_FETCH; |
| 550 | |
| 551 | fetch_start = (v_total - fetch_lines) * h_total + 1; |
| 552 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 553 | writel(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 554 | writel(BIT(31), MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 555 | } |
| 556 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 557 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 558 | *pinfo) |
| 559 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 560 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 561 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 562 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 563 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 564 | width = fb->width; |
| 565 | |
| 566 | if (pinfo->lcdc.dual_pipe) |
| 567 | width /= 2; |
| 568 | |
| 569 | /* write active region size*/ |
| 570 | mdp_rgb_size = (height << 16) | width; |
| 571 | |
| 572 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 573 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 574 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 575 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 576 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 577 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 578 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 579 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 580 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 581 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 582 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 583 | switch (pinfo->pipe_type) { |
| 584 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 585 | left_staging_level = 0x0000200; |
| 586 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 587 | break; |
| 588 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 589 | left_staging_level = 0x0040000; |
| 590 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 591 | break; |
| 592 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 593 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 594 | left_staging_level = 0x1; |
| 595 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 596 | break; |
| 597 | } |
| 598 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 599 | /* Base layer for layer mixer 0 */ |
| 600 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 601 | |
| 602 | if (pinfo->lcdc.dual_pipe) { |
| 603 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 604 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 605 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 606 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 607 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 608 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 609 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 610 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 611 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 612 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 613 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 614 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 615 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 616 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 617 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 618 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 619 | } |
| 620 | } |
| 621 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 622 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 623 | { |
| 624 | uint32_t mode = 0; |
| 625 | uint32_t budget_ctl = 0; |
| 626 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 627 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 628 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 629 | |
| 630 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 631 | |
| 632 | if (!pinfo->fbc.enabled) |
| 633 | return; |
| 634 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 635 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 636 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 637 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 638 | width = pinfo->xres; |
| 639 | if (enc_mode) |
| 640 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 641 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 642 | if (pinfo->mipi.dual_dsi) |
| 643 | width /= 2; |
| 644 | |
| 645 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 646 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 647 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 648 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 649 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 650 | |
| 651 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 652 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 653 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 654 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 655 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n", |
| 656 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 657 | |
| 658 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 659 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 660 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 661 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 662 | ((fbc->lossy_mode_thd) << 8) | |
| 663 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 664 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 665 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 666 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 667 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 668 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 669 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 670 | |
| 671 | if (pinfo->mipi.dual_dsi) { |
| 672 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 673 | writel(budget_ctl, MDP_PP_1_BASE + |
| 674 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 675 | writel(lossy_mode, MDP_PP_1_BASE + |
| 676 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 677 | } |
| 678 | } |
| 679 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 680 | void mdss_qos_remapper_setup(void) |
| 681 | { |
| 682 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 683 | uint32_t map; |
| 684 | |
| 685 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 686 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 687 | MDSS_MDP_HW_REV_102)) |
| 688 | map = 0xE9; |
| 689 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 690 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 691 | map = 0xA5; |
| 692 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 693 | MDSS_MDP_HW_REV_106) || |
| 694 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 695 | MDSS_MDP_HW_REV_108)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 696 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 697 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 698 | MDSS_MDP_HW_REV_105) || |
| 699 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 700 | MDSS_MDP_HW_REV_109)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 701 | map = 0xA4; |
| 702 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 703 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 704 | map = 0xFA; |
| 705 | else |
| 706 | return; |
| 707 | |
| 708 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 709 | } |
| 710 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 711 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 712 | { |
| 713 | uint32_t mask, reg_val, i; |
| 714 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 715 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 716 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
| 717 | |
| 718 | mdp_select_pipe_xin_id(pinfo, |
| 719 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 720 | |
| 721 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
| 722 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) { |
| 723 | vbif_qos[0] = 2; |
| 724 | vbif_qos[1] = 2; |
| 725 | vbif_qos[2] = 2; |
| 726 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 727 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
| 728 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 729 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 730 | vbif_qos[1] = 2; |
| 731 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 732 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 733 | } else { |
| 734 | return; |
| 735 | } |
| 736 | |
| 737 | for (i = 0; i < 4; i++) { |
| 738 | reg_val = readl(VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 739 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 740 | reg_val &= ~(mask); |
| 741 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 742 | |
| 743 | if (pinfo->lcdc.dual_pipe) { |
| 744 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 745 | reg_val &= ~(mask); |
| 746 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 747 | } |
| 748 | writel(reg_val, VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 749 | } |
| 750 | } |
| 751 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 752 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 753 | int is_main_ctl) |
| 754 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 755 | uint32_t mctl_intf_sel; |
| 756 | uint32_t sctl_intf_sel; |
| 757 | |
| 758 | if ((pinfo->dest == DISPLAY_2) || |
| 759 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 760 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 761 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 762 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 763 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 764 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 765 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 766 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 767 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 768 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 769 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 770 | } |
| 771 | |
| 772 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 773 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 774 | uint32_t *intf_base, uint32_t *sintf_base) |
| 775 | { |
| 776 | if (pinfo->dest == DISPLAY_2) { |
| 777 | *intf_sel = BIT(16); |
| 778 | *sintf_sel = BIT(8); |
| 779 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 780 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 781 | } else { |
| 782 | *intf_sel = BIT(8); |
| 783 | *sintf_sel = BIT(16); |
| 784 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 785 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 786 | } |
| 787 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 788 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 789 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 790 | } |
| 791 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 792 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 793 | struct fbcon_config *fb) |
| 794 | { |
| 795 | int ret = NO_ERROR; |
| 796 | struct lcdc_panel_info *lcdc = NULL; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 797 | uint32_t intf_sel, sintf_sel; |
| 798 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 799 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 800 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 801 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 802 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 803 | |
| 804 | mdss_intf_tg_setup(pinfo, intf_base); |
| 805 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 806 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 807 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 808 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 809 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 810 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 811 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 812 | mdp_clk_gating_ctrl(); |
| 813 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 814 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 815 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 816 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 817 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 818 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 819 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 820 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 821 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 822 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 823 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 824 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 825 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 826 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 827 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 828 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 829 | |
| 830 | /* enable 3D mux for dual_pipe but single interface config */ |
| 831 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 832 | !pinfo->lcdc.split_display) |
| 833 | reg |= BIT(19) | BIT(20); |
| 834 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 835 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 836 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 837 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 838 | CTL_1 path should not be set since CTL_0 itself is going |
| 839 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 840 | if (pinfo->fbc.enabled) |
| 841 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 842 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 843 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 844 | if (!pinfo->lcdc.dst_split) { |
| 845 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 846 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 847 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 848 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 849 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 850 | |
| 851 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 852 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 853 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 854 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 855 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 856 | |
| 857 | return 0; |
| 858 | } |
| 859 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 860 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 861 | { |
| 862 | int ret = NO_ERROR; |
| 863 | struct lcdc_panel_info *lcdc = NULL; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 864 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 865 | |
| 866 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 867 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 868 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 869 | mdp_clk_gating_ctrl(); |
| 870 | |
| 871 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 872 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 873 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 874 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 875 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 876 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 877 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 878 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 879 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 880 | |
| 881 | mdss_layer_mixer_setup(fb, pinfo); |
| 882 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 883 | if (pinfo->lcdc.dual_pipe) |
| 884 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 885 | else |
| 886 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 887 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 888 | writel(0x9, MDP_DISP_INTF_SEL); |
| 889 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 890 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 891 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 892 | |
| 893 | return 0; |
| 894 | } |
| 895 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 896 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 897 | { |
| 898 | int ret = NO_ERROR; |
| 899 | struct lcdc_panel_info *lcdc = NULL; |
| 900 | uint32_t left_pipe, right_pipe; |
| 901 | |
| 902 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); |
| 903 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 904 | |
| 905 | mdp_clk_gating_ctrl(); |
| 906 | mdss_vbif_setup(); |
| 907 | |
| 908 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 909 | |
| 910 | mdss_qos_remapper_setup(); |
| 911 | |
| 912 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 913 | if (pinfo->lcdc.dual_pipe) |
| 914 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 915 | |
| 916 | mdss_layer_mixer_setup(fb, pinfo); |
| 917 | |
| 918 | if (pinfo->lcdc.dual_pipe) |
| 919 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 920 | else |
| 921 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 922 | |
| 923 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 924 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 925 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 926 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 927 | |
| 928 | return 0; |
| 929 | } |
| 930 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 931 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 932 | struct fbcon_config *fb) |
| 933 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 934 | uint32_t intf_sel, sintf_sel; |
| 935 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 936 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 937 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 938 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 939 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 940 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 941 | |
| 942 | if (pinfo == NULL) |
| 943 | return ERR_INVALID_ARGS; |
| 944 | |
| 945 | lcdc = &(pinfo->lcdc); |
| 946 | if (lcdc == NULL) |
| 947 | return ERR_INVALID_ARGS; |
| 948 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 949 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 950 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 951 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 952 | reg = BIT(1); /* Command mode */ |
| 953 | if (pinfo->lcdc.pipe_swap) |
| 954 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 955 | else |
| 956 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 957 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 958 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 959 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 960 | } |
| 961 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 962 | if (pinfo->lcdc.dst_split) { |
| 963 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 964 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 965 | } |
| 966 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 967 | mdp_clk_gating_ctrl(); |
| 968 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 969 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 970 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 971 | |
| 972 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 973 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 974 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 975 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 976 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 977 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 978 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 979 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 980 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 981 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 982 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 983 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 984 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 985 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 986 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 987 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 988 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 989 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 990 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 991 | if (pinfo->fbc.enabled) |
| 992 | mdss_fbc_cfg(pinfo); |
| 993 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 994 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 995 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 996 | if (!pinfo->lcdc.dst_split) { |
| 997 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 998 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 999 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1000 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1001 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1002 | return ret; |
| 1003 | } |
| 1004 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1005 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1006 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1007 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 1008 | uint32_t timing_engine_en; |
| 1009 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1010 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1011 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1012 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 1013 | |
| 1014 | if (pinfo->dest == DISPLAY_1) |
| 1015 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1016 | else |
| 1017 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1018 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1019 | |
| 1020 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1021 | } |
| 1022 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 1023 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1024 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 1025 | uint32_t timing_engine_en; |
| 1026 | |
| 1027 | if (pinfo->dest == DISPLAY_1) |
| 1028 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1029 | else |
| 1030 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1031 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1032 | if(!target_cont_splash_screen()) |
| 1033 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame^] | 1034 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1035 | mdelay(60); |
| 1036 | /* Ping-Pong done Tear Check Read/Write */ |
| 1037 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1038 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1039 | } |
| 1040 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1041 | writel(0x00000000, MDP_INTR_EN); |
| 1042 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1043 | return NO_ERROR; |
| 1044 | } |
| 1045 | |
| 1046 | int mdp_dsi_cmd_off() |
| 1047 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1048 | if(!target_cont_splash_screen()) |
| 1049 | { |
| 1050 | /* Ping-Pong done Tear Check Read/Write */ |
| 1051 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1052 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1053 | } |
| 1054 | writel(0x00000000, MDP_INTR_EN); |
| 1055 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1056 | return NO_ERROR; |
| 1057 | } |
| 1058 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1059 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1060 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1061 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1062 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1063 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1064 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1065 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1066 | return NO_ERROR; |
| 1067 | } |
| 1068 | |
| 1069 | void mdp_disable(void) |
| 1070 | { |
| 1071 | |
| 1072 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1073 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1074 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1075 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1076 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1077 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1078 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1079 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1080 | return NO_ERROR; |
| 1081 | } |
| 1082 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1083 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1084 | { |
| 1085 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1086 | |
| 1087 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1088 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1089 | |
| 1090 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1091 | |
| 1092 | return NO_ERROR; |
| 1093 | } |
| 1094 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1095 | int mdp_edp_off(void) |
| 1096 | { |
| 1097 | if (!target_cont_splash_screen()) { |
| 1098 | |
| 1099 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1100 | mdss_mdp_intf_offset()); |
| 1101 | mdelay(60); |
| 1102 | /* Ping-Pong done Tear Check Read/Write */ |
| 1103 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1104 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1105 | writel(0x00000000, MDP_INTR_EN); |
| 1106 | } |
| 1107 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1108 | writel(0x00000000, MDP_INTR_EN); |
| 1109 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1110 | return NO_ERROR; |
| 1111 | } |