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gerrit-public.fairphone.software / kernel / msm-4.19 / d129be27b8cffcec706b0ccf143c93fba8cc5726 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 4c1b4a8e3da6db48232cc38831466d4430f1d606 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame^]106 wkup_m3: wkup_m3@100000 {
107 compatible = "ti,am3352-wkup-m3";
108 reg = <0x100000 0x4000>,
109 <0x180000 0x2000>;
110 reg-names = "umem", "dmem";
111 ti,hwmods = "wkup_m3";
112 ti,pm-firmware = "am335x-pm-firmware.elf";
113 };
114
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]115 prcm: prcm@200000 {
116 compatible = "ti,am3-prcm";
117 reg = <0x200000 0x4000>;
118
119 prcm_clocks: clocks {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123
124 prcm_clockdomains: clockdomains {
125 };
126 };
127
128 scm: scm@210000 {
129 compatible = "ti,am3-scm", "simple-bus";
130 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]131 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]132 #size-cells = <1>;
133 ranges = <0 0x210000 0x2000>;
134
135 am33xx_pinmux: pinmux@800 {
136 compatible = "pinctrl-single";
137 reg = <0x800 0x238>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 pinctrl-single,register-width = <32>;
141 pinctrl-single,function-mask = <0x7f>;
142 };
143
144 scm_conf: scm_conf@0 {
145 compatible = "syscon";
146 reg = <0x0 0x800>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149
150 scm_clocks: clocks {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154 };
155
156 scm_clockdomains: clockdomains {
157 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]158 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]159 };
160
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]161 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]162 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]163 interrupt-controller;
164 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]165 reg = <0x48200000 0x1000>;
166 };
167
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]168 edma: edma@49000000 {
169 compatible = "ti,edma3";
170 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
171 reg = <0x49000000 0x10000>,
Thomas Gleixnercf7eb972014-04-13 20:44:46 +0200[diff] [blame]172 <0x44e10f90 0x40>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]173 interrupts = <12 13 14>;
174 #dma-cells = <1>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]175 };
176
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]177 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]178 compatible = "ti,omap4-gpio";
179 ti,hwmods = "gpio1";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]183 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]185 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]188 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap4-gpio";
190 ti,hwmods = "gpio2";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]194 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]195 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]197 };
198
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]199 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]200 compatible = "ti,omap4-gpio";
201 ti,hwmods = "gpio3";
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]205 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]206 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]207 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]208 };
209
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]210 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]211 compatible = "ti,omap4-gpio";
212 ti,hwmods = "gpio4";
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]216 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]218 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 };
220
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]221 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]222 compatible = "ti,omap3-uart";
223 ti,hwmods = "uart1";
224 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]225 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]227 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]228 dmas = <&edma 26>, <&edma 27>;
229 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]230 };
231
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]232 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]233 compatible = "ti,omap3-uart";
234 ti,hwmods = "uart2";
235 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]236 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]237 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]238 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]239 dmas = <&edma 28>, <&edma 29>;
240 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]241 };
242
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]243 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]244 compatible = "ti,omap3-uart";
245 ti,hwmods = "uart3";
246 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]247 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]248 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]249 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]250 dmas = <&edma 30>, <&edma 31>;
251 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]252 };
253
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]254 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]255 compatible = "ti,omap3-uart";
256 ti,hwmods = "uart4";
257 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]258 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]259 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]260 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]261 };
262
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]263 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]264 compatible = "ti,omap3-uart";
265 ti,hwmods = "uart5";
266 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]267 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]268 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]269 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]270 };
271
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]272 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]273 compatible = "ti,omap3-uart";
274 ti,hwmods = "uart6";
275 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]276 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]277 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]278 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]279 };
280
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]281 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]282 compatible = "ti,omap4-i2c";
283 #address-cells = <1>;
284 #size-cells = <0>;
285 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]286 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]287 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]288 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]289 };
290
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]291 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]292 compatible = "ti,omap4-i2c";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]296 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]297 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]298 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]299 };
300
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]301 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]302 compatible = "ti,omap4-i2c";
303 #address-cells = <1>;
304 #size-cells = <0>;
305 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]306 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]307 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]308 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]309 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]310
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]311 mmc1: mmc@48060000 {
312 compatible = "ti,omap4-hsmmc";
313 ti,hwmods = "mmc1";
314 ti,dual-volt;
315 ti,needs-special-reset;
316 ti,needs-special-hs-handling;
317 dmas = <&edma 24
318 &edma 25>;
319 dma-names = "tx", "rx";
320 interrupts = <64>;
321 interrupt-parent = <&intc>;
322 reg = <0x48060000 0x1000>;
323 status = "disabled";
324 };
325
326 mmc2: mmc@481d8000 {
327 compatible = "ti,omap4-hsmmc";
328 ti,hwmods = "mmc2";
329 ti,needs-special-reset;
330 dmas = <&edma 2
331 &edma 3>;
332 dma-names = "tx", "rx";
333 interrupts = <28>;
334 interrupt-parent = <&intc>;
335 reg = <0x481d8000 0x1000>;
336 status = "disabled";
337 };
338
339 mmc3: mmc@47810000 {
340 compatible = "ti,omap4-hsmmc";
341 ti,hwmods = "mmc3";
342 ti,needs-special-reset;
343 interrupts = <29>;
344 interrupt-parent = <&intc>;
345 reg = <0x47810000 0x1000>;
346 status = "disabled";
347 };
348
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]349 hwspinlock: spinlock@480ca000 {
350 compatible = "ti,omap4-hwspinlock";
351 reg = <0x480ca000 0x1000>;
352 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]353 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]354 };
355
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]356 wdt2: wdt@44e35000 {
357 compatible = "ti,omap3-wdt";
358 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]359 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]360 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]361 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]362
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]363 dcan0: can@481cc000 {
364 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]365 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]366 reg = <0x481cc000 0x2000>;
367 clocks = <&dcan0_fck>;
368 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]369 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]370 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]371 status = "disabled";
372 };
373
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]374 dcan1: can@481d0000 {
375 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]376 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]377 reg = <0x481d0000 0x2000>;
378 clocks = <&dcan1_fck>;
379 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]380 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]381 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]382 status = "disabled";
383 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]384
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]385 mailbox: mailbox@480C8000 {
386 compatible = "ti,omap4-mailbox";
387 reg = <0x480C8000 0x200>;
388 interrupts = <77>;
389 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]390 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]391 ti,mbox-num-users = <4>;
392 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]393 mbox_wkupm3: wkup_m3 {
394 ti,mbox-tx = <0 0 0>;
395 ti,mbox-rx = <0 0 3>;
396 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]397 };
398
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]399 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]400 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]401 reg = <0x44e31000 0x400>;
402 interrupts = <67>;
403 ti,hwmods = "timer1";
404 ti,timer-alwon;
405 };
406
407 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]408 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]409 reg = <0x48040000 0x400>;
410 interrupts = <68>;
411 ti,hwmods = "timer2";
412 };
413
414 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]415 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]416 reg = <0x48042000 0x400>;
417 interrupts = <69>;
418 ti,hwmods = "timer3";
419 };
420
421 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]422 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]423 reg = <0x48044000 0x400>;
424 interrupts = <92>;
425 ti,hwmods = "timer4";
426 ti,timer-pwm;
427 };
428
429 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]430 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]431 reg = <0x48046000 0x400>;
432 interrupts = <93>;
433 ti,hwmods = "timer5";
434 ti,timer-pwm;
435 };
436
437 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]438 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]439 reg = <0x48048000 0x400>;
440 interrupts = <94>;
441 ti,hwmods = "timer6";
442 ti,timer-pwm;
443 };
444
445 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]446 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]447 reg = <0x4804a000 0x400>;
448 interrupts = <95>;
449 ti,hwmods = "timer7";
450 ti,timer-pwm;
451 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]452
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]453 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]454 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]455 reg = <0x44e3e000 0x1000>;
456 interrupts = <75
457 76>;
458 ti,hwmods = "rtc";
459 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]460
461 spi0: spi@48030000 {
462 compatible = "ti,omap4-mcspi";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]466 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]467 ti,spi-num-cs = <2>;
468 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]469 dmas = <&edma 16
470 &edma 17
471 &edma 18
472 &edma 19>;
473 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]474 status = "disabled";
475 };
476
477 spi1: spi@481a0000 {
478 compatible = "ti,omap4-mcspi";
479 #address-cells = <1>;
480 #size-cells = <0>;
481 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]482 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]483 ti,spi-num-cs = <2>;
484 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]485 dmas = <&edma 42
486 &edma 43
487 &edma 44
488 &edma 45>;
489 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]490 status = "disabled";
491 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]492
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]493 usb: usb@47400000 {
494 compatible = "ti,am33xx-usb";
495 reg = <0x47400000 0x1000>;
496 ranges;
497 #address-cells = <1>;
498 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]499 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]500 status = "disabled";
501
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]502 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]503 compatible = "ti,am335x-usb-ctrl-module";
504 reg = <0x44e10620 0x10
505 0x44e10648 0x4>;
506 reg-names = "phy_ctrl", "wakeup";
507 status = "disabled";
508 };
509
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]510 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]511 compatible = "ti,am335x-usb-phy";
512 reg = <0x47401300 0x100>;
513 reg-names = "phy";
514 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]515 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]516 };
517
518 usb0: usb@47401000 {
519 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]520 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]521 reg = <0x47401400 0x400
522 0x47401000 0x200>;
523 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]524
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]525 interrupts = <18>;
526 interrupt-names = "mc";
527 dr_mode = "otg";
528 mentor,multipoint = <1>;
529 mentor,num-eps = <16>;
530 mentor,ram-bits = <12>;
531 mentor,power = <500>;
532 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]533
534 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
535 &cppi41dma 2 0 &cppi41dma 3 0
536 &cppi41dma 4 0 &cppi41dma 5 0
537 &cppi41dma 6 0 &cppi41dma 7 0
538 &cppi41dma 8 0 &cppi41dma 9 0
539 &cppi41dma 10 0 &cppi41dma 11 0
540 &cppi41dma 12 0 &cppi41dma 13 0
541 &cppi41dma 14 0 &cppi41dma 0 1
542 &cppi41dma 1 1 &cppi41dma 2 1
543 &cppi41dma 3 1 &cppi41dma 4 1
544 &cppi41dma 5 1 &cppi41dma 6 1
545 &cppi41dma 7 1 &cppi41dma 8 1
546 &cppi41dma 9 1 &cppi41dma 10 1
547 &cppi41dma 11 1 &cppi41dma 12 1
548 &cppi41dma 13 1 &cppi41dma 14 1>;
549 dma-names =
550 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
551 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
552 "rx14", "rx15",
553 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
554 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
555 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]556 };
557
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]558 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]559 compatible = "ti,am335x-usb-phy";
560 reg = <0x47401b00 0x100>;
561 reg-names = "phy";
562 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]563 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]564 };
565
566 usb1: usb@47401800 {
567 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]568 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]569 reg = <0x47401c00 0x400
570 0x47401800 0x200>;
571 reg-names = "mc", "control";
572 interrupts = <19>;
573 interrupt-names = "mc";
574 dr_mode = "otg";
575 mentor,multipoint = <1>;
576 mentor,num-eps = <16>;
577 mentor,ram-bits = <12>;
578 mentor,power = <500>;
579 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]580
581 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
582 &cppi41dma 17 0 &cppi41dma 18 0
583 &cppi41dma 19 0 &cppi41dma 20 0
584 &cppi41dma 21 0 &cppi41dma 22 0
585 &cppi41dma 23 0 &cppi41dma 24 0
586 &cppi41dma 25 0 &cppi41dma 26 0
587 &cppi41dma 27 0 &cppi41dma 28 0
588 &cppi41dma 29 0 &cppi41dma 15 1
589 &cppi41dma 16 1 &cppi41dma 17 1
590 &cppi41dma 18 1 &cppi41dma 19 1
591 &cppi41dma 20 1 &cppi41dma 21 1
592 &cppi41dma 22 1 &cppi41dma 23 1
593 &cppi41dma 24 1 &cppi41dma 25 1
594 &cppi41dma 26 1 &cppi41dma 27 1
595 &cppi41dma 28 1 &cppi41dma 29 1>;
596 dma-names =
597 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
598 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
599 "rx14", "rx15",
600 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
601 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
602 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]603 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]604
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]605 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]606 compatible = "ti,am3359-cppi41";
607 reg = <0x47400000 0x1000
608 0x47402000 0x1000
609 0x47403000 0x1000
610 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]611 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]612 interrupts = <17>;
613 interrupt-names = "glue";
614 #dma-cells = <2>;
615 #dma-channels = <30>;
616 #dma-requests = <256>;
617 status = "disabled";
618 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]619 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]620
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]621 epwmss0: epwmss@48300000 {
622 compatible = "ti,am33xx-pwmss";
623 reg = <0x48300000 0x10>;
624 ti,hwmods = "epwmss0";
625 #address-cells = <1>;
626 #size-cells = <1>;
627 status = "disabled";
628 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
629 0x48300180 0x48300180 0x80 /* EQEP */
630 0x48300200 0x48300200 0x80>; /* EHRPWM */
631
632 ecap0: ecap@48300100 {
633 compatible = "ti,am33xx-ecap";
634 #pwm-cells = <3>;
635 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]636 interrupts = <31>;
637 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]638 ti,hwmods = "ecap0";
639 status = "disabled";
640 };
641
642 ehrpwm0: ehrpwm@48300200 {
643 compatible = "ti,am33xx-ehrpwm";
644 #pwm-cells = <3>;
645 reg = <0x48300200 0x80>;
646 ti,hwmods = "ehrpwm0";
647 status = "disabled";
648 };
649 };
650
651 epwmss1: epwmss@48302000 {
652 compatible = "ti,am33xx-pwmss";
653 reg = <0x48302000 0x10>;
654 ti,hwmods = "epwmss1";
655 #address-cells = <1>;
656 #size-cells = <1>;
657 status = "disabled";
658 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
659 0x48302180 0x48302180 0x80 /* EQEP */
660 0x48302200 0x48302200 0x80>; /* EHRPWM */
661
662 ecap1: ecap@48302100 {
663 compatible = "ti,am33xx-ecap";
664 #pwm-cells = <3>;
665 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]666 interrupts = <47>;
667 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]668 ti,hwmods = "ecap1";
669 status = "disabled";
670 };
671
672 ehrpwm1: ehrpwm@48302200 {
673 compatible = "ti,am33xx-ehrpwm";
674 #pwm-cells = <3>;
675 reg = <0x48302200 0x80>;
676 ti,hwmods = "ehrpwm1";
677 status = "disabled";
678 };
679 };
680
681 epwmss2: epwmss@48304000 {
682 compatible = "ti,am33xx-pwmss";
683 reg = <0x48304000 0x10>;
684 ti,hwmods = "epwmss2";
685 #address-cells = <1>;
686 #size-cells = <1>;
687 status = "disabled";
688 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
689 0x48304180 0x48304180 0x80 /* EQEP */
690 0x48304200 0x48304200 0x80>; /* EHRPWM */
691
692 ecap2: ecap@48304100 {
693 compatible = "ti,am33xx-ecap";
694 #pwm-cells = <3>;
695 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]696 interrupts = <61>;
697 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]698 ti,hwmods = "ecap2";
699 status = "disabled";
700 };
701
702 ehrpwm2: ehrpwm@48304200 {
703 compatible = "ti,am33xx-ehrpwm";
704 #pwm-cells = <3>;
705 reg = <0x48304200 0x80>;
706 ti,hwmods = "ehrpwm2";
707 status = "disabled";
708 };
709 };
710
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]711 mac: ethernet@4a100000 {
712 compatible = "ti,cpsw";
713 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]714 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
715 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]716 cpdma_channels = <8>;
717 ale_entries = <1024>;
718 bd_ram_size = <0x2000>;
719 no_bd_ram = <0>;
720 rx_descs = <64>;
721 mac_control = <0x20>;
722 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]723 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]724 cpts_clock_mult = <0x80000000>;
725 cpts_clock_shift = <29>;
726 reg = <0x4a100000 0x800
727 0x4a101200 0x100>;
728 #address-cells = <1>;
729 #size-cells = <1>;
730 interrupt-parent = <&intc>;
731 /*
732 * c0_rx_thresh_pend
733 * c0_rx_pend
734 * c0_tx_pend
735 * c0_misc_pend
736 */
737 interrupts = <40 41 42 43>;
738 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]739 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]740 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]741
742 davinci_mdio: mdio@4a101000 {
743 compatible = "ti,davinci_mdio";
744 #address-cells = <1>;
745 #size-cells = <0>;
746 ti,hwmods = "davinci_mdio";
747 bus_freq = <1000000>;
748 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]749 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]750 };
751
752 cpsw_emac0: slave@4a100200 {
753 /* Filled in by U-Boot */
754 mac-address = [ 00 00 00 00 00 00 ];
755 };
756
757 cpsw_emac1: slave@4a100300 {
758 /* Filled in by U-Boot */
759 mac-address = [ 00 00 00 00 00 00 ];
760 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]761
762 phy_sel: cpsw-phy-sel@44e10650 {
763 compatible = "ti,am3352-cpsw-phy-sel";
764 reg= <0x44e10650 0x4>;
765 reg-names = "gmii-sel";
766 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]767 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]768
769 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]770 compatible = "mmio-sram";
771 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]772 };
773
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]774 elm: elm@48080000 {
775 compatible = "ti,am3352-elm";
776 reg = <0x48080000 0x2000>;
777 interrupts = <4>;
778 ti,hwmods = "elm";
779 status = "disabled";
780 };
781
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]782 lcdc: lcdc@4830e000 {
783 compatible = "ti,am33xx-tilcdc";
784 reg = <0x4830e000 0x1000>;
785 interrupt-parent = <&intc>;
786 interrupts = <36>;
787 ti,hwmods = "lcdc";
788 status = "disabled";
789 };
790
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]791 tscadc: tscadc@44e0d000 {
792 compatible = "ti,am3359-tscadc";
793 reg = <0x44e0d000 0x1000>;
794 interrupt-parent = <&intc>;
795 interrupts = <16>;
796 ti,hwmods = "adc_tsc";
797 status = "disabled";
798
799 tsc {
800 compatible = "ti,am3359-tsc";
801 };
802 am335x_adc: adc {
803 #io-channel-cells = <1>;
804 compatible = "ti,am3359-adc";
805 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]806 };
807
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]808 gpmc: gpmc@50000000 {
809 compatible = "ti,am3352-gpmc";
810 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]811 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]812 reg = <0x50000000 0x2000>;
813 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]814 gpmc,num-cs = <7>;
815 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]816 #address-cells = <2>;
817 #size-cells = <1>;
818 status = "disabled";
819 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]820
821 sham: sham@53100000 {
822 compatible = "ti,omap4-sham";
823 ti,hwmods = "sham";
824 reg = <0x53100000 0x200>;
825 interrupts = <109>;
826 dmas = <&edma 36>;
827 dma-names = "rx";
828 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]829
830 aes: aes@53500000 {
831 compatible = "ti,omap4-aes";
832 ti,hwmods = "aes";
833 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]834 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]835 dmas = <&edma 6>,
836 <&edma 5>;
837 dma-names = "tx", "rx";
838 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]839
840 mcasp0: mcasp@48038000 {
841 compatible = "ti,am33xx-mcasp-audio";
842 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]843 reg = <0x48038000 0x2000>,
844 <0x46000000 0x400000>;
845 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]846 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]847 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]848 status = "disabled";
849 dmas = <&edma 8>,
850 <&edma 9>;
851 dma-names = "tx", "rx";
852 };
853
854 mcasp1: mcasp@4803C000 {
855 compatible = "ti,am33xx-mcasp-audio";
856 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]857 reg = <0x4803C000 0x2000>,
858 <0x46400000 0x400000>;
859 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]860 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]861 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]862 status = "disabled";
863 dmas = <&edma 10>,
864 <&edma 11>;
865 dma-names = "tx", "rx";
866 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]867
868 rng: rng@48310000 {
869 compatible = "ti,omap4-rng";
870 ti,hwmods = "rng";
871 reg = <0x48310000 0x2000>;
872 interrupts = <111>;
873 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]874 };
875};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]876
877/include/ "am33xx-clocks.dtsi"