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gerrit-public.fairphone.software / kernel / msm-4.9 / 1e49f0281c6ca30ba5445db5931f5c00ab30c81f / . / arch / arm64 / boot / dts / qcom / sdm670.dtsi
blob: bb07c045906b7c1e922f363049b1b7225fd33031 [file] [log] [blame]
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]1/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "skeleton64.dtsi"
14#include <dt-bindings/interrupt-controller/arm-gic.h>
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]15#include <dt-bindings/clock/qcom,gcc-sdm845.h>
16#include <dt-bindings/clock/qcom,camcc-sdm845.h>
17#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
18#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
19#include <dt-bindings/clock/qcom,videocc-sdm845.h>
20#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
21#include <dt-bindings/clock/qcom,rpmh.h>
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]22#include <dt-bindings/soc/qcom,tcs-mbox.h>
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]23#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]24#include <dt-bindings/clock/qcom,aop-qmp.h>
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]25
Santosh Mardi903c95d2017-09-25 10:36:29 +0530[diff] [blame]26#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
27
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]28/ {
29 model = "Qualcomm Technologies, Inc. SDM670";
30 compatible = "qcom,sdm670";
31 qcom,msm-id = <336 0x0>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]32 interrupt-parent = <&pdc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]33
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]34 aliases {
35 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]36 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]37 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
Mukesh Kumar Savaliya7b272542017-07-10 19:35:29 +0530[diff] [blame]38 serial0 = &qupv3_se12_2uart;
39 spi0 = &qupv3_se8_spi;
40 i2c0 = &qupv3_se10_i2c;
41 i2c1 = &qupv3_se3_i2c;
42 hsuart0 = &qupv3_se6_4uart;
43 };
44
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]45 chosen {
Pavankumar Kondeti2c218d72017-10-03 19:31:31 +0530[diff] [blame]46 bootargs = "rcupdate.rcu_expedited=1 core_ctl_disable_cpumask=6-7";
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]47 };
48
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 CPU0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]59 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]60 cpu-release-addr = <0x0 0x90000000>;
61 next-level-cache = <&L2_0>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]62 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]63 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]64 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]65 L2_0: l2-cache {
66 compatible = "arm,arch-cache";
67 cache-size = <0x20000>;
68 cache-level = <2>;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "arm,arch-cache";
72 cache-size = <0x100000>;
73 cache-level = <3>;
74 };
75 };
76 L1_I_0: l1-icache {
77 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]78 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]79 };
80 L1_D_0: l1-dcache {
81 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]82 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]83 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]84 L1_TLB_0: l1-tlb {
85 qcom,dump-size = <0x3000>;
86 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]87 };
88
89 CPU1: cpu@100 {
90 device_type = "cpu";
91 compatible = "arm,armv8";
92 reg = <0x0 0x100>;
93 enable-method = "psci";
94 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]95 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]96 cpu-release-addr = <0x0 0x90000000>;
97 next-level-cache = <&L2_100>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]98 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]99 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]100 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]101 L2_100: l2-cache {
102 compatible = "arm,arch-cache";
103 cache-size = <0x20000>;
104 cache-level = <2>;
105 next-level-cache = <&L3_0>;
106 };
107 L1_I_100: l1-icache {
108 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]109 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]110 };
111 L1_D_100: l1-dcache {
112 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]113 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]114 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]115 L1_TLB_100: l1-tlb {
116 qcom,dump-size = <0x3000>;
117 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]118 };
119
120 CPU2: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x200>;
124 enable-method = "psci";
125 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]126 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]127 cpu-release-addr = <0x0 0x90000000>;
128 next-level-cache = <&L2_200>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]129 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]130 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]131 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]132 L2_200: l2-cache {
133 compatible = "arm,arch-cache";
134 cache-size = <0x20000>;
135 cache-level = <2>;
136 next-level-cache = <&L3_0>;
137 };
138 L1_I_200: l1-icache {
139 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]140 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]141 };
142 L1_D_200: l1-dcache {
143 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]144 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]145 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]146 L1_TLB_200: l1-tlb {
147 qcom,dump-size = <0x3000>;
148 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x0 0x300>;
155 enable-method = "psci";
156 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]157 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]158 cpu-release-addr = <0x0 0x90000000>;
159 next-level-cache = <&L2_300>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]160 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]161 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]162 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]163 L2_300: l2-cache {
164 compatible = "arm,arch-cache";
165 cache-size = <0x20000>;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 L1_I_300: l1-icache {
170 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]171 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]172 };
173 L1_D_300: l1-dcache {
174 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]175 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]176 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]177 L1_TLB_300: l1-tlb {
178 qcom,dump-size = <0x3000>;
179 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]180 };
181
182 CPU4: cpu@400 {
183 device_type = "cpu";
184 compatible = "arm,armv8";
185 reg = <0x0 0x400>;
186 enable-method = "psci";
187 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]188 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]189 cpu-release-addr = <0x0 0x90000000>;
190 next-level-cache = <&L2_400>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]191 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]192 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]193 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]194 L2_400: l2-cache {
195 compatible = "arm,arch-cache";
196 cache-size = <0x20000>;
197 cache-level = <2>;
198 next-level-cache = <&L3_0>;
199 };
200 L1_I_400: l1-icache {
201 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]202 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]203 };
204 L1_D_400: l1-dcache {
205 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]206 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]207 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]208 L1_TLB_400: l1-tlb {
209 qcom,dump-size = <0x3000>;
210 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]211 };
212
213 CPU5: cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x0 0x500>;
217 enable-method = "psci";
218 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]219 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]220 cpu-release-addr = <0x0 0x90000000>;
221 next-level-cache = <&L2_500>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]222 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]223 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]224 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]225 L2_500: l2-cache {
226 compatible = "arm,arch-cache";
227 cache-size = <0x20000>;
228 cache-level = <2>;
229 next-level-cache = <&L3_0>;
230 };
231 L1_I_500: l1-icache {
232 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]233 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]234 };
235 L1_D_500: l1-dcache {
236 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]237 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]238 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]239 L1_TLB_500: l1-tlb {
240 qcom,dump-size = <0x3000>;
241 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]242 };
243
244 CPU6: cpu@600 {
245 device_type = "cpu";
246 compatible = "arm,armv8";
247 reg = <0x0 0x600>;
248 enable-method = "psci";
249 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]250 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]251 cpu-release-addr = <0x0 0x90000000>;
252 next-level-cache = <&L2_600>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]253 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]254 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]255 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]256 L2_600: l2-cache {
257 compatible = "arm,arch-cache";
258 cache-size = <0x40000>;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
261 };
262 L1_I_600: l1-icache {
263 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]264 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]265 };
266 L1_D_600: l1-dcache {
267 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]268 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]269 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]270 L1_TLB_600: l1-tlb {
271 qcom,dump-size = <0x3c000>;
272 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]273 };
274
275 CPU7: cpu@700 {
276 device_type = "cpu";
277 compatible = "arm,armv8";
278 reg = <0x0 0x700>;
279 enable-method = "psci";
280 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]281 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]282 cpu-release-addr = <0x0 0x90000000>;
283 next-level-cache = <&L2_700>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]284 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]285 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]286 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]287 L2_700: l2-cache {
288 compatible = "arm,arch-cache";
289 cache-size = <0x40000>;
290 cache-level = <2>;
291 next-level-cache = <&L3_0>;
292 };
293 L1_I_700: l1-icache {
294 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]295 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]296 };
297 L1_D_700: l1-dcache {
298 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]299 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]300 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]301 L1_TLB_700: l1-tlb {
302 qcom,dump-size = <0x3c000>;
303 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]304 };
305
306 cpu-map {
307 cluster0 {
308 core0 {
309 cpu = <&CPU0>;
310 };
311
312 core1 {
313 cpu = <&CPU1>;
314 };
315
316 core2 {
317 cpu = <&CPU2>;
318 };
319
320 core3 {
321 cpu = <&CPU3>;
322 };
323
324 core4 {
325 cpu = <&CPU4>;
326 };
327
328 core5 {
329 cpu = <&CPU5>;
330 };
331 };
332 cluster1 {
333 core0 {
334 cpu = <&CPU6>;
335 };
336
337 core1 {
338 cpu = <&CPU7>;
339 };
340 };
341 };
342 };
343
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]344 energy_costs: energy-costs {
345 compatible = "sched-energy";
346
347 CPU_COST_0: core-cost0 {
348 busy-cost-data = <
349 300000 14
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]350 576000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]351 748800 31
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]352 998400 46
353 1209600 57
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]354 1324800 84
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]355 1516800 96
356 1612800 114
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]357 1708800 139
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]358 >;
359 idle-cost-data = <
360 12 10 8 6
361 >;
362 };
363 CPU_COST_1: core-cost1 {
364 busy-cost-data = <
365 300000 256
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]366 652800 307
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]367 825600 332
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]368 979200 382
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]369 1132800 408
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]370 1363200 448
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]371 1536000 586
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]372 1747200 641
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]373 1843200 659
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]374 1996800 696
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]375 2016000 865
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]376 2054400 876
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]377 2169600 900
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]378 2208000 924
379 2361600 948
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]380 2400000 1170
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]381 2457600 1200
382 2515200 1300
383 2611200 1400
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]384 >;
385 idle-cost-data = <
386 100 80 60 40
387 >;
388 };
389 CLUSTER_COST_0: cluster-cost0 {
390 busy-cost-data = <
391 300000 5
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]392 576000 7
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]393 748800 8
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]394 998400 9
395 1209600 10
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]396 1324800 13
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]397 1516800 15
398 1612800 16
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]399 1708800 19
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]400 >;
401 idle-cost-data = <
402 4 3 2 1
403 >;
404 };
405 CLUSTER_COST_1: cluster-cost1 {
406 busy-cost-data = <
407 300000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]408 652800 30
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]409 825600 33
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]410 979200 38
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]411 1132800 40
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]412 1363200 44
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]413 1536000 58
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]414 1747200 64
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]415 1843200 65
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]416 1996800 69
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]417 2016000 85
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]418 2054400 87
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]419 2169600 90
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]420 2208000 92
421 2361600 94
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]422 2400000 117
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]423 2457600 120
424 2515200 130
425 2611200 140
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]426 >;
427 idle-cost-data = <
428 4 3 2 1
429 >;
430 };
431 };
432
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]433 psci {
434 compatible = "arm,psci-1.0";
435 method = "smc";
436 };
437
438 soc: soc { };
439
Imran Khanb1066fa2017-08-01 17:20:22 +0530[diff] [blame]440 vendor: vendor {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 ranges = <0 0 0 0xffffffff>;
444 compatible = "simple-bus";
445 };
446
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]447 firmware: firmware {
448 android {
449 compatible = "android,firmware";
450
monisingfb2cb762017-12-19 14:40:49 +0530[diff] [blame]451 vbmeta {
452 compatible = "android,vbmeta";
453 parts = "vbmeta,boot,system,vendor,dtbo";
454 };
455
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]456 fstab {
457 compatible = "android,fstab";
458 vendor {
459 compatible = "android,vendor";
460 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
461 type = "ext4";
462 mnt_flags = "ro,barrier=1,discard";
AnilKumar Chimata0d646ab2017-10-25 22:09:03 +0530[diff] [blame]463 fsmgr_flags = "wait,slotselect,avb";
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]464 };
465 };
466 };
467 };
468
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]469 reserved-memory {
470 #address-cells = <2>;
471 #size-cells = <2>;
472 ranges;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]473
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]474 hyp_region: hyp_region@85700000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]475 compatible = "removed-dma-pool";
476 no-map;
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]477 reg = <0 0x85700000 0 0x600000>;
478 };
479
480 xbl_region: xbl_region@85e00000 {
481 compatible = "removed-dma-pool";
482 no-map;
483 reg = <0 0x85e00000 0 0x100000>;
484 };
485
486 removed_region: removed_region@85fc0000 {
487 compatible = "removed-dma-pool";
488 no-map;
489 reg = <0 0x85fc0000 0 0x2f40000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]490 };
491
492 pil_camera_mem: camera_region@8ab00000 {
493 compatible = "removed-dma-pool";
494 no-map;
495 reg = <0 0x8ab00000 0 0x500000>;
496 };
497
498 pil_modem_mem: modem_region@8b000000 {
499 compatible = "removed-dma-pool";
500 no-map;
501 reg = <0 0x8b000000 0 0x7e00000>;
502 };
503
504 pil_video_mem: pil_video_region@92e00000 {
505 compatible = "removed-dma-pool";
506 no-map;
507 reg = <0 0x92e00000 0 0x500000>;
508 };
509
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]510 wlan_msa_mem: wlan_msa_region@93300000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]511 compatible = "removed-dma-pool";
512 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]513 reg = <0 0x93300000 0 0x100000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]514 };
515
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]516 pil_cdsp_mem: cdsp_regions@93400000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]517 compatible = "removed-dma-pool";
518 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]519 reg = <0 0x93400000 0 0x800000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]520 };
521
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]522 pil_mba_mem: pil_mba_region@0x93c00000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]523 compatible = "removed-dma-pool";
524 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]525 reg = <0 0x93c00000 0 0x200000>;
526 };
527
528 pil_adsp_mem: pil_adsp_region@93e00000 {
529 compatible = "removed-dma-pool";
530 no-map;
531 reg = <0 0x93e00000 0 0x1e00000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]532 };
533
Prakash Gupta7c571ef2018-01-19 17:57:47 +0530[diff] [blame]534 pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
535 compatible = "removed-dma-pool";
536 no-map;
537 reg = <0 0x95c00000 0 0x10000>;
538 };
539
540 pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
541 compatible = "removed-dma-pool";
542 no-map;
543 reg = <0 0x95c10000 0 0x5000>;
544 };
545
546 pil_gpu_mem: gpu_region@0x95c15000 {
547 compatible = "removed-dma-pool";
548 no-map;
549 reg = <0 0x95c15000 0 0x2000>;
550 };
551
552 qseecom_mem: qseecom_region@0x9e400000 {
553 compatible = "shared-dma-pool";
554 no-map;
555 reg = <0 0x9e400000 0 0x1400000>;
556 };
557
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]558 adsp_mem: adsp_region {
559 compatible = "shared-dma-pool";
560 alloc-ranges = <0 0x00000000 0 0xffffffff>;
561 reusable;
562 alignment = <0 0x400000>;
Tharun Kumar Meruguf0bb40e2018-06-25 16:02:04 +0530[diff] [blame]563 size = <0 0x800000>;
564 };
565
566 sdsp_mem: sdsp_region {
567 compatible = "shared-dma-pool";
568 alloc-ranges = <0 0x00000000 0 0xffffffff>;
569 reusable;
570 alignment = <0 0x400000>;
571 size = <0 0x400000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]572 };
573
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]574 qseecom_ta_mem: qseecom_ta_region {
575 compatible = "shared-dma-pool";
576 alloc-ranges = <0 0x00000000 0 0xffffffff>;
577 reusable;
578 alignment = <0 0x400000>;
579 size = <0 0x1000000>;
580 };
581
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]582 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
583 compatible = "shared-dma-pool";
584 alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
585 reusable;
586 alignment = <0 0x400000>;
587 size = <0 0x800000>;
588 };
589
590 secure_display_memory: secure_display_region {
591 compatible = "shared-dma-pool";
592 alloc-ranges = <0 0x00000000 0 0xffffffff>;
593 reusable;
594 alignment = <0 0x400000>;
595 size = <0 0x5c00000>;
596 };
597
Jayant Shekhare3191272018-01-30 16:49:08 +0530[diff] [blame]598 cont_splash_memory: cont_splash_region@9c000000 {
599 reg = <0x0 0x9c000000 0x0 0x02400000>;
Jayant Shekharb59d1692017-11-10 14:21:40 +0530[diff] [blame]600 label = "cont_splash_region";
601 };
602
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]603 dump_mem: mem_dump_region {
604 compatible = "shared-dma-pool";
605 reusable;
606 size = <0 0x2400000>;
607 };
608
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]609 /* global autoconfigured region for contiguous allocations */
610 linux,cma {
611 compatible = "shared-dma-pool";
612 alloc-ranges = <0 0x00000000 0 0xffffffff>;
613 reusable;
614 alignment = <0 0x400000>;
615 size = <0 0x2000000>;
616 linux,cma-default;
617 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]618 };
619};
620
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]621#include "sdm670-ion.dtsi"
622
Dhoat Harpal92d63dea2017-06-06 21:20:26 +0530[diff] [blame]623#include "sdm670-smp2p.dtsi"
624
c_mtharuce962e42017-12-05 22:41:17 +0530[diff] [blame]625#include "msm-rdbg.dtsi"
626
Mukesh Kumar Savaliya065ca482017-06-06 14:44:45 +0530[diff] [blame]627#include "sdm670-qupv3.dtsi"
628
Saranya Chiduraf49fee12017-06-19 10:52:37 +0530[diff] [blame]629#include "sdm670-coresight.dtsi"
Manikanta Kanamarlapudid4abc602017-08-28 19:23:41 +0530[diff] [blame]630
631#include "sdm670-vidc.dtsi"
632
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]633#include "sdm670-sde-pll.dtsi"
634
635#include "sdm670-sde.dtsi"
636
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]637&soc {
638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges = <0 0 0 0xffffffff>;
641 compatible = "simple-bus";
642
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]643 jtag_mm0: jtagmm@7040000 {
644 compatible = "qcom,jtagv8-mm";
645 reg = <0x7040000 0x1000>;
646 reg-names = "etm-base";
647
648 clocks = <&clock_aop QDSS_CLK>;
649 clock-names = "core_clk";
650
651 qcom,coresight-jtagmm-cpu = <&CPU0>;
652 };
653
654 jtag_mm1: jtagmm@7140000 {
655 compatible = "qcom,jtagv8-mm";
656 reg = <0x7140000 0x1000>;
657 reg-names = "etm-base";
658
659 clocks = <&clock_aop QDSS_CLK>;
660 clock-names = "core_clk";
661
662 qom,coresight-jtagmm-cpu = <&CPU1>;
663 };
664
665 jtag_mm2: jtagmm@7240000 {
666 compatible = "qcom,jtagv8-mm";
667 reg = <0x7240000 0x1000>;
668 reg-names = "etm-base";
669
670 clocks = <&clock_aop QDSS_CLK>;
671 clock-names = "core_clk";
672
673 qcom,coresight-jtagmm-cpu = <&CPU2>;
674 };
675
676 jtag_mm3: jtagmm@7340000 {
677 compatible = "qcom,jtagv8-mm";
678 reg = <0x7340000 0x1000>;
679 reg-names = "etm-base";
680
681 clocks = <&clock_aop QDSS_CLK>;
682 clock-names = "core_clk";
683
684 qcom,coresight-jtagmm-cpu = <&CPU3>;
685 };
686
687 jtag_mm4: jtagmm@7440000 {
688 compatible = "qcom,jtagv8-mm";
689 reg = <0x7440000 0x1000>;
690 reg-names = "etm-base";
691
692 clocks = <&clock_aop QDSS_CLK>;
693 clock-names = "core_clk";
694
695 qcom,coresight-jtagmm-cpu = <&CPU4>;
696 };
697
698 jtag_mm5: jtagmm@7540000 {
699 compatible = "qcom,jtagv8-mm";
700 reg = <0x7540000 0x1000>;
701 reg-names = "etm-base";
702
703 clocks = <&clock_aop QDSS_CLK>;
704 clock-names = "core_clk";
705
706 qcom,coresight-jtagmm-cpu = <&CPU5>;
707 };
708
709 jtag_mm6: jtagmm@7640000 {
710 compatible = "qcom,jtagv8-mm";
711 reg = <0x7640000 0x1000>;
712 reg-names = "etm-base";
713
714 clocks = <&clock_aop QDSS_CLK>;
715 clock-names = "core_clk";
716
717 qcom,coresight-jtagmm-cpu = <&CPU6>;
718 };
719
720 jtag_mm7: jtagmm@7740000 {
721 compatible = "qcom,jtagv8-mm";
722 reg = <0x7740000 0x1000>;
723 reg-names = "etm-base";
724
725 clocks = <&clock_aop QDSS_CLK>;
726 clock-names = "core_clk";
727
728 qcom,coresight-jtagmm-cpu = <&CPU7>;
729 };
730
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]731 intc: interrupt-controller@17a00000 {
732 compatible = "arm,gic-v3";
733 #interrupt-cells = <3>;
734 interrupt-controller;
735 #redistributor-regions = <1>;
736 redistributor-stride = <0x0 0x20000>;
737 reg = <0x17a00000 0x10000>, /* GICD */
738 <0x17a60000 0x100000>; /* GICR * 8 */
739 interrupts = <1 9 4>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]740 interrupt-parent = <&intc>;
Gaurav Kohli34f87562018-05-11 12:26:16 +0530[diff] [blame]741 ignored-save-restore-irqs = <38>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]742 };
743
Raghavendra Kakarla04f032162017-12-08 19:11:54 +0530[diff] [blame]744 pdc: interrupt-controller@b220000{
745 compatible = "qcom,pdc-sdm670";
746 reg = <0xb220000 0x400>;
747 #interrupt-cells = <3>;
748 interrupt-parent = <&intc>;
749 interrupt-controller;
750 };
751
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]752 timer {
753 compatible = "arm,armv8-timer";
754 interrupts = <1 1 0xf08>,
755 <1 2 0xf08>,
756 <1 3 0xf08>,
757 <1 0 0xf08>;
758 clock-frequency = <19200000>;
759 };
760
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]761 qcom,memshare {
762 compatible = "qcom,memshare";
763
764 qcom,client_1 {
765 compatible = "qcom,memshare-peripheral";
766 qcom,peripheral-size = <0x0>;
767 qcom,client-id = <0>;
768 qcom,allocate-boot-time;
769 label = "modem";
770 };
771
772 qcom,client_2 {
773 compatible = "qcom,memshare-peripheral";
774 qcom,peripheral-size = <0x0>;
775 qcom,client-id = <2>;
776 label = "modem";
777 };
778
779 mem_client_3_size: qcom,client_3 {
780 compatible = "qcom,memshare-peripheral";
781 qcom,peripheral-size = <0x500000>;
782 qcom,client-id = <1>;
Manoj Prabhu B991f9222018-01-03 19:13:56 +0530[diff] [blame]783 qcom,allocate-boot-time;
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]784 label = "modem";
785 };
786 };
787
Lakshmi Sunkarabbd69892017-06-09 13:17:10 +0530[diff] [blame]788 qcom,sps {
789 compatible = "qcom,msm_sps_4k";
790 qcom,pipe-attr-ee;
791 };
792
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]793 qcom_cedev: qcedev@1de0000 {
794 compatible = "qcom,qcedev";
795 reg = <0x1de0000 0x20000>,
796 <0x1dc4000 0x24000>;
797 reg-names = "crypto-base","crypto-bam-base";
798 interrupts = <0 272 0>;
799 qcom,bam-pipe-pair = <3>;
800 qcom,ce-hw-instance = <0>;
801 qcom,ce-device = <0>;
802 qcom,ce-hw-shared;
803 qcom,bam-ee = <0>;
804 qcom,msm-bus,name = "qcedev-noc";
805 qcom,msm-bus,num-cases = <2>;
806 qcom,msm-bus,num-paths = <1>;
807 qcom,msm-bus,vectors-KBps =
808 <125 512 0 0>,
809 <125 512 393600 393600>;
810 clock-names = "core_clk_src", "core_clk",
811 "iface_clk", "bus_clk";
812 clocks = <&clock_gcc GCC_CE1_CLK>,
813 <&clock_gcc GCC_CE1_CLK>,
814 <&clock_gcc GCC_CE1_AHB_CLK>,
815 <&clock_gcc GCC_CE1_AXI_CLK>;
816 qcom,ce-opp-freq = <171430000>;
817 qcom,request-bw-before-clk;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]818 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]819 iommus = <&apps_smmu 0x706 0x1>,
820 <&apps_smmu 0x716 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]821 };
822
Tatenda Chipeperekwa8a77c8a2018-01-30 14:50:11 -0800[diff] [blame]823 qcom_msmhdcp: qcom,msm_hdcp {
824 compatible = "qcom,msm-hdcp";
825 };
826
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]827 qcom_crypto: qcrypto@1de0000 {
828 compatible = "qcom,qcrypto";
829 reg = <0x1de0000 0x20000>,
830 <0x1dc4000 0x24000>;
831 reg-names = "crypto-base","crypto-bam-base";
832 interrupts = <0 272 0>;
833 qcom,bam-pipe-pair = <2>;
834 qcom,ce-hw-instance = <0>;
835 qcom,ce-device = <0>;
836 qcom,bam-ee = <0>;
837 qcom,ce-hw-shared;
838 qcom,clk-mgmt-sus-res;
839 qcom,msm-bus,name = "qcrypto-noc";
840 qcom,msm-bus,num-cases = <2>;
841 qcom,msm-bus,num-paths = <1>;
842 qcom,msm-bus,vectors-KBps =
843 <125 512 0 0>,
844 <125 512 393600 393600>;
845 clock-names = "core_clk_src", "core_clk",
846 "iface_clk", "bus_clk";
847 clocks = <&clock_gcc GCC_CE1_CLK>,
848 <&clock_gcc GCC_CE1_CLK>,
849 <&clock_gcc GCC_CE1_AHB_CLK>,
850 <&clock_gcc GCC_CE1_AXI_CLK>;
851 qcom,ce-opp-freq = <171430000>;
852 qcom,request-bw-before-clk;
853 qcom,use-sw-aes-cbc-ecb-ctr-algo;
854 qcom,use-sw-aes-xts-algo;
855 qcom,use-sw-aes-ccm-algo;
856 qcom,use-sw-aead-algo;
857 qcom,use-sw-ahash-algo;
858 qcom,use-sw-hmac-algo;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]859 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]860 iommus = <&apps_smmu 0x704 0x1>,
861 <&apps_smmu 0x714 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]862 };
863
Abir Ghoshb849ab22017-09-19 13:03:11 +0530[diff] [blame]864 qcom,qbt1000 {
865 compatible = "qcom,qbt1000";
866 clock-names = "core", "iface";
867 clock-frequency = <25000000>;
868 qcom,ipc-gpio = <&tlmm 121 0>;
869 qcom,finger-detect-gpio = <&tlmm 122 0>;
870 };
871
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]872 qcom_seecom: qseecom@86d00000 {
873 compatible = "qcom,qseecom";
874 reg = <0x86d00000 0x2200000>;
875 reg-names = "secapp-region";
876 qcom,hlos-num-ce-hw-instances = <1>;
877 qcom,hlos-ce-hw-instance = <0>;
878 qcom,qsee-ce-hw-instance = <0>;
879 qcom,disk-encrypt-pipe-pair = <2>;
880 qcom,support-fde;
881 qcom,no-clock-support;
Neeraj Soni7c4254c2017-11-15 11:13:14 +0530[diff] [blame]882 qcom,fde-key-size;
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]883 qcom,appsbl-qseecom-support;
884 qcom,msm-bus,name = "qseecom-noc";
885 qcom,msm-bus,num-cases = <4>;
886 qcom,msm-bus,num-paths = <1>;
887 qcom,msm-bus,vectors-KBps =
888 <125 512 0 0>,
889 <125 512 200000 400000>,
890 <125 512 300000 800000>,
891 <125 512 400000 1000000>;
892 clock-names = "core_clk_src", "core_clk",
893 "iface_clk", "bus_clk";
894 clocks = <&clock_gcc GCC_CE1_CLK>,
895 <&clock_gcc GCC_CE1_CLK>,
896 <&clock_gcc GCC_CE1_AHB_CLK>,
897 <&clock_gcc GCC_CE1_AXI_CLK>;
898 qcom,ce-opp-freq = <171430000>;
899 qcom,qsee-reentrancy-support = <2>;
900 };
901
mohamed sunfeer732f7572017-09-19 19:51:11 +0530[diff] [blame]902 qcom_tzlog: tz-log@146bf720 {
903 compatible = "qcom,tz-log";
904 reg = <0x146bf720 0x3000>;
905 qcom,hyplog-enabled;
906 hyplog-address-offset = <0x410>;
907 hyplog-size-offset = <0x414>;
908 };
909
mohamed sunfeer2228b242017-09-19 19:10:08 +0530[diff] [blame]910 qcom_rng: qrng@793000{
911 compatible = "qcom,msm-rng";
912 reg = <0x793000 0x1000>;
913 qcom,msm-rng-iface-clk;
914 qcom,no-qrng-config;
915 qcom,msm-bus,name = "msm-rng-noc";
916 qcom,msm-bus,num-cases = <2>;
917 qcom,msm-bus,num-paths = <1>;
918 qcom,msm-bus,vectors-KBps =
919 <1 618 0 0>, /* No vote */
920 <1 618 0 800>; /* 100 KHz */
921 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
922 clock-names = "iface_clk";
923 };
924
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]925 thermal_zones: thermal-zones {};
Rama Krishna Phani Aa3c0e782017-07-17 20:09:15 +0530[diff] [blame]926
927 tsens0: tsens@c222000 {
928 compatible = "qcom,tsens24xx";
929 reg = <0xc222000 0x4>,
930 <0xc263000 0x1ff>;
931 reg-names = "tsens_srot_physical",
932 "tsens_tm_physical";
933 interrupts = <0 506 0>, <0 508 0>;
934 interrupt-names = "tsens-upper-lower", "tsens-critical";
935 #thermal-sensor-cells = <1>;
936 };
937
938 tsens1: tsens@c223000 {
939 compatible = "qcom,tsens24xx";
940 reg = <0xc223000 0x4>,
941 <0xc265000 0x1ff>;
942 reg-names = "tsens_srot_physical",
943 "tsens_tm_physical";
944 interrupts = <0 507 0>, <0 509 0>;
945 interrupt-names = "tsens-upper-lower", "tsens-critical";
946 #thermal-sensor-cells = <1>;
947 };
948
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]949 timer@0x17c90000{
950 #address-cells = <1>;
951 #size-cells = <1>;
952 ranges;
953 compatible = "arm,armv7-timer-mem";
954 reg = <0x17c90000 0x1000>;
955 clock-frequency = <19200000>;
956
957 frame@0x17ca0000 {
958 frame-number = <0>;
959 interrupts = <0 7 0x4>,
960 <0 6 0x4>;
961 reg = <0x17ca0000 0x1000>,
962 <0x17cb0000 0x1000>;
963 };
964
965 frame@17cc0000 {
966 frame-number = <1>;
967 interrupts = <0 8 0x4>;
968 reg = <0x17cc0000 0x1000>;
969 status = "disabled";
970 };
971
972 frame@17cd0000 {
973 frame-number = <2>;
974 interrupts = <0 9 0x4>;
975 reg = <0x17cd0000 0x1000>;
976 status = "disabled";
977 };
978
979 frame@17ce0000 {
980 frame-number = <3>;
981 interrupts = <0 10 0x4>;
982 reg = <0x17ce0000 0x1000>;
983 status = "disabled";
984 };
985
986 frame@17cf0000 {
987 frame-number = <4>;
988 interrupts = <0 11 0x4>;
989 reg = <0x17cf0000 0x1000>;
990 status = "disabled";
991 };
992
993 frame@17d00000 {
994 frame-number = <5>;
995 interrupts = <0 12 0x4>;
996 reg = <0x17d00000 0x1000>;
997 status = "disabled";
998 };
999
1000 frame@17d10000 {
1001 frame-number = <6>;
1002 interrupts = <0 13 0x4>;
1003 reg = <0x17d10000 0x1000>;
1004 status = "disabled";
1005 };
1006 };
1007
1008 restart@10ac000 {
1009 compatible = "qcom,pshold";
1010 reg = <0xC264000 0x4>,
1011 <0x1fd3000 0x4>;
1012 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1013 };
1014
Maulik Shah6bf7d5d2017-07-27 09:48:42 +0530[diff] [blame]1015 aop-msg-client {
1016 compatible = "qcom,debugfs-qmp-client";
1017 mboxes = <&qmp_aop 0>;
1018 mbox-names = "aop";
1019 };
1020
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1021 clock_rpmh: qcom,rpmhclk {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1022 compatible = "qcom,rpmh-clk-sdm670";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1023 #clock-cells = <1>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1024 mboxes = <&apps_rsc 0>;
1025 mbox-names = "apps";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1026 };
1027
1028 clock_gcc: qcom,gcc@100000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1029 compatible = "qcom,gcc-sdm670", "syscon";
1030 reg = <0x100000 0x1f0000>;
1031 reg-names = "cc_base";
1032 vdd_cx-supply = <&pm660l_s3_level>;
1033 vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1034 #clock-cells = <1>;
1035 #reset-cells = <1>;
1036 };
1037
1038 clock_videocc: qcom,videocc@ab00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1039 compatible = "qcom,video_cc-sdm670", "syscon";
1040 reg = <0xab00000 0x10000>;
1041 reg-names = "cc_base";
1042 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1043 #clock-cells = <1>;
1044 #reset-cells = <1>;
1045 };
1046
1047 clock_camcc: qcom,camcc@ad00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1048 compatible = "qcom,cam_cc-sdm670", "syscon";
1049 reg = <0xad00000 0x10000>;
1050 reg-names = "cc_base";
1051 vdd_cx-supply = <&pm660l_s3_level>;
1052 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1053 #clock-cells = <1>;
1054 #reset-cells = <1>;
Alok Pandey499587b2018-02-08 22:14:59 +0530[diff] [blame]1055 qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;
1056 qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;
1057 qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;
1058 qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;
1059 qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;
1060 qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;
1061 qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;
1062 qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;
1063 qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;
1064 qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;
1065 qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;
1066 qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;
1067 qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;
1068 qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1069 };
1070
1071 clock_dispcc: qcom,dispcc@af00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1072 compatible = "qcom,dispcc-sdm670", "syscon";
1073 reg = <0xaf00000 0x10000>;
1074 reg-names = "cc_base";
1075 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1076 #clock-cells = <1>;
1077 #reset-cells = <1>;
1078 };
1079
1080 clock_gpucc: qcom,gpucc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1081 compatible = "qcom,gpucc-sdm670", "syscon";
1082 reg = <0x5090000 0x9000>;
1083 reg-names = "cc_base";
1084 vdd_cx-supply = <&pm660l_s3_level>;
1085 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1086 qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1087 #clock-cells = <1>;
1088 #reset-cells = <1>;
1089 };
1090
1091 clock_gfx: qcom,gfxcc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1092 compatible = "qcom,gfxcc-sdm670";
1093 reg = <0x5090000 0x9000>;
1094 reg-names = "cc_base";
1095 vdd_gfx-supply = <&pm660l_s2_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1096 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1097 #clock-cells = <1>;
1098 #reset-cells = <1>;
1099 };
1100
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1101 cpucc_debug: syscon@17970018 {
1102 compatible = "syscon";
1103 reg = <0x17970018 0x4>;
1104 };
1105
1106 clock_debug: qcom,cc-debug {
1107 compatible = "qcom,debugcc-sdm845";
Shefali Jain582eb3b2018-04-24 11:46:58 +0530[diff] [blame]1108 qcom,cc-count = <6>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1109 qcom,gcc = <&clock_gcc>;
1110 qcom,videocc = <&clock_videocc>;
1111 qcom,camcc = <&clock_camcc>;
1112 qcom,dispcc = <&clock_dispcc>;
1113 qcom,gpucc = <&clock_gpucc>;
1114 qcom,cpucc = <&cpucc_debug>;
1115 clock-names = "xo_clk_src";
1116 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1117 #clock-cells = <1>;
1118 };
1119
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1120 clock_cpucc: qcom,cpucc@0x17d41000 {
1121 compatible = "qcom,clk-cpu-osm-sdm670";
1122 reg = <0x17d41000 0x1400>,
1123 <0x17d43000 0x1400>,
David Collins1e048402017-11-29 15:43:09 -0800[diff] [blame]1124 <0x17d45800 0x1400>;
1125 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda02617bd2017-11-10 16:03:43 -0800[diff] [blame]1126 vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
1127 vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1128
Odelu Kukatla86c179e2017-12-12 19:10:23 +0530[diff] [blame]1129 qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]1130 l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1131
1132 clock-names = "xo_ao";
1133 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1134 #clock-cells = <1>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1135 };
1136
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1137 clock_aop: qcom,aopclk {
Odelu Kukatla80f617f2017-09-15 19:30:25 +0530[diff] [blame]1138 compatible = "qcom,aop-qmp-clk-v1";
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1139 #clock-cells = <1>;
1140 mboxes = <&qmp_aop 0>;
1141 mbox-names = "qdss_clk";
1142 };
1143
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1144 slim_aud: slim@62dc0000 {
1145 cell-index = <1>;
1146 compatible = "qcom,slim-ngd";
1147 reg = <0x62dc0000 0x2c000>,
1148 <0x62d84000 0x2a000>;
1149 reg-names = "slimbus_physical", "slimbus_bam_physical";
1150 interrupts = <0 163 0>, <0 164 0>;
1151 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
1152 qcom,apps-ch-pipes = <0x780000>;
1153 qcom,ea-pc = <0x290>;
1154 status = "disabled";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1155 qcom,iommu-s1-bypass;
1156
1157 iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1158 compatible = "qcom,iommu-slim-ctrl-cb";
1159 iommus = <&apps_smmu 0x1826 0x0>,
1160 <&apps_smmu 0x182d 0x0>,
1161 <&apps_smmu 0x182e 0x1>,
1162 <&apps_smmu 0x1830 0x1>;
1163 };
1164
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1165 };
1166
1167 slim_qca: slim@62e40000 {
1168 cell-index = <3>;
1169 compatible = "qcom,slim-ngd";
1170 reg = <0x62e40000 0x2c000>,
1171 <0x62e04000 0x20000>;
1172 reg-names = "slimbus_physical", "slimbus_bam_physical";
1173 interrupts = <0 291 0>, <0 292 0>;
1174 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1175 status = "ok";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1176 qcom,iommu-s1-bypass;
1177
1178 iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1179 compatible = "qcom,iommu-slim-ctrl-cb";
1180 iommus = <&apps_smmu 0x1833 0x0>;
1181 };
1182
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1183 /* Slimbus Slave DT for WCN3990 */
1184 btfmslim_codec: wcn3990 {
1185 compatible = "qcom,btfmslim_slave";
1186 elemental-addr = [00 01 20 02 17 02];
1187 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
1188 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
1189 };
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1190 };
1191
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1192 wdog: qcom,wdt@17980000{
1193 compatible = "qcom,msm-watchdog";
1194 reg = <0x17980000 0x1000>;
1195 reg-names = "wdt-base";
Lingutla Chandrasekhar9fb9ba92017-10-08 21:59:19 +0530[diff] [blame]1196 interrupts = <0 0 0>, <0 1 0>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1197 qcom,bark-time = <11000>;
Neeraj Upadhyaydbc184d2017-12-07 16:05:39 +0530[diff] [blame]1198 qcom,pet-time = <9360>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1199 qcom,ipi-ping;
1200 qcom,wakeup-enable;
1201 };
1202
1203 qcom,msm-rtb {
1204 compatible = "qcom,msm-rtb";
1205 qcom,rtb-size = <0x100000>;
1206 };
1207
Lingutla Chandrasekhar4d78d722017-11-10 16:03:44 +0530[diff] [blame]1208 qcom,mpm2-sleep-counter@c221000 {
1209 compatible = "qcom,mpm2-sleep-counter";
1210 reg = <0x0c221000 0x1000>;
1211 clock-frequency = <32768>;
1212 };
1213
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1214 qcom,msm-imem@146bf000 {
1215 compatible = "qcom,msm-imem";
1216 reg = <0x146bf000 0x1000>;
1217 ranges = <0x0 0x146bf000 0x1000>;
1218 #address-cells = <1>;
1219 #size-cells = <1>;
1220
1221 mem_dump_table@10 {
1222 compatible = "qcom,msm-imem-mem_dump_table";
1223 reg = <0x10 8>;
1224 };
1225
Lingutla Chandrasekharfa5c13f2017-09-25 11:01:58 +0530[diff] [blame]1226 dload_type@1c {
1227 compatible = "qcom,msm-imem-dload-type";
1228 reg = <0x1c 0x4>;
1229 };
1230
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1231 restart_reason@65c {
1232 compatible = "qcom,msm-imem-restart_reason";
1233 reg = <0x65c 4>;
1234 };
1235
1236 pil@94c {
1237 compatible = "qcom,msm-imem-pil";
1238 reg = <0x94c 200>;
1239 };
1240
1241 kaslr_offset@6d0 {
1242 compatible = "qcom,msm-imem-kaslr_offset";
1243 reg = <0x6d0 12>;
1244 };
Lingutla Chandrasekhar3c51f0b2017-09-12 14:21:21 +0530[diff] [blame]1245
1246 boot_stats@6b0 {
1247 compatible = "qcom,msm-imem-boot_stats";
1248 reg = <0x6b0 0x20>;
1249 };
1250
1251 diag_dload@c8 {
1252 compatible = "qcom,msm-imem-diag-dload";
1253 reg = <0xc8 0xc8>;
1254 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1255 };
1256
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1257 gpi_dma0: qcom,gpi-dma@0x800000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1258 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1259 compatible = "qcom,gpi-dma";
1260 reg = <0x800000 0x60000>;
1261 reg-names = "gpi-top";
1262 interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
1263 <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
1264 <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
1265 <0 256 0>;
1266 qcom,max-num-gpii = <13>;
1267 qcom,gpii-mask = <0xfa>;
1268 qcom,ev-factor = <2>;
1269 iommus = <&apps_smmu 0x0016 0x0>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1270 qcom,smmu-cfg = <0x1>;
1271 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1272 status = "ok";
1273 };
1274
1275 gpi_dma1: qcom,gpi-dma@0xa00000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1276 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1277 compatible = "qcom,gpi-dma";
1278 reg = <0xa00000 0x60000>;
1279 reg-names = "gpi-top";
1280 interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,
1281 <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,
1282 <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>,
1283 <0 299 0>;
1284 qcom,max-num-gpii = <13>;
1285 qcom,gpii-mask = <0xfa>;
1286 qcom,ev-factor = <2>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1287 qcom,smmu-cfg = <0x1>;
1288 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1289 iommus = <&apps_smmu 0x06d6 0x0>;
1290 status = "ok";
1291 };
1292
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1293 cpuss_dump {
1294 compatible = "qcom,cpuss-dump";
1295 qcom,l1_i_cache0 {
1296 qcom,dump-node = <&L1_I_0>;
1297 qcom,dump-id = <0x60>;
1298 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1299 qcom,l1_i_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1300 qcom,dump-node = <&L1_I_100>;
1301 qcom,dump-id = <0x61>;
1302 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1303 qcom,l1_i_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1304 qcom,dump-node = <&L1_I_200>;
1305 qcom,dump-id = <0x62>;
1306 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1307 qcom,l1_i_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1308 qcom,dump-node = <&L1_I_300>;
1309 qcom,dump-id = <0x63>;
1310 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1311 qcom,l1_i_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1312 qcom,dump-node = <&L1_I_400>;
1313 qcom,dump-id = <0x64>;
1314 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1315 qcom,l1_i_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1316 qcom,dump-node = <&L1_I_500>;
1317 qcom,dump-id = <0x65>;
1318 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1319 qcom,l1_i_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1320 qcom,dump-node = <&L1_I_600>;
1321 qcom,dump-id = <0x66>;
1322 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1323 qcom,l1_i_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1324 qcom,dump-node = <&L1_I_700>;
1325 qcom,dump-id = <0x67>;
1326 };
1327 qcom,l1_d_cache0 {
1328 qcom,dump-node = <&L1_D_0>;
1329 qcom,dump-id = <0x80>;
1330 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1331 qcom,l1_d_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1332 qcom,dump-node = <&L1_D_100>;
1333 qcom,dump-id = <0x81>;
1334 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1335 qcom,l1_d_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1336 qcom,dump-node = <&L1_D_200>;
1337 qcom,dump-id = <0x82>;
1338 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1339 qcom,l1_d_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1340 qcom,dump-node = <&L1_D_300>;
1341 qcom,dump-id = <0x83>;
1342 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1343 qcom,l1_d_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1344 qcom,dump-node = <&L1_D_400>;
1345 qcom,dump-id = <0x84>;
1346 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1347 qcom,l1_d_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1348 qcom,dump-node = <&L1_D_500>;
1349 qcom,dump-id = <0x85>;
1350 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1351 qcom,l1_d_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1352 qcom,dump-node = <&L1_D_600>;
1353 qcom,dump-id = <0x86>;
1354 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1355 qcom,l1_d_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1356 qcom,dump-node = <&L1_D_700>;
1357 qcom,dump-id = <0x87>;
1358 };
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1359 qcom,llcc1_d_cache {
1360 qcom,dump-node = <&LLCC_1>;
1361 qcom,dump-id = <0x140>;
1362 };
1363 qcom,llcc2_d_cache {
1364 qcom,dump-node = <&LLCC_2>;
1365 qcom,dump-id = <0x141>;
1366 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1367 qcom,l1_tlb_dump0 {
1368 qcom,dump-node = <&L1_TLB_0>;
1369 qcom,dump-id = <0x20>;
1370 };
1371 qcom,l1_tlb_dump100 {
1372 qcom,dump-node = <&L1_TLB_100>;
1373 qcom,dump-id = <0x21>;
1374 };
1375 qcom,l1_tlb_dump200 {
1376 qcom,dump-node = <&L1_TLB_200>;
1377 qcom,dump-id = <0x22>;
1378 };
1379 qcom,l1_tlb_dump300 {
1380 qcom,dump-node = <&L1_TLB_300>;
1381 qcom,dump-id = <0x23>;
1382 };
1383 qcom,l1_tlb_dump400 {
1384 qcom,dump-node = <&L1_TLB_400>;
1385 qcom,dump-id = <0x24>;
1386 };
1387 qcom,l1_tlb_dump500 {
1388 qcom,dump-node = <&L1_TLB_500>;
1389 qcom,dump-id = <0x25>;
1390 };
1391 qcom,l1_tlb_dump600 {
1392 qcom,dump-node = <&L1_TLB_600>;
1393 qcom,dump-id = <0x26>;
1394 };
1395 qcom,l1_tlb_dump700 {
1396 qcom,dump-node = <&L1_TLB_700>;
1397 qcom,dump-id = <0x27>;
1398 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1399 };
1400
Vishwanath Raju Kb6e9cb22018-05-02 11:56:34 +0530[diff] [blame]1401 mem_dump: mem_dump {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1402 compatible = "qcom,mem-dump";
1403 memory-region = <&dump_mem>;
1404
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1405 rpmh {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1406 qcom,dump-size = <0x2000000>;
1407 qcom,dump-id = <0xec>;
1408 };
1409
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1410 rpm_sw {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1411 qcom,dump-size = <0x28000>;
1412 qcom,dump-id = <0xea>;
1413 };
1414
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1415 pmic {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1416 qcom,dump-size = <0x10000>;
1417 qcom,dump-id = <0xe4>;
1418 };
1419
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1420 tmc_etf {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1421 qcom,dump-size = <0x10000>;
1422 qcom,dump-id = <0xf0>;
1423 };
1424
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1425 tmc_etfswao {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1426 qcom,dump-size = <0x8400>;
1427 qcom,dump-id = <0xf1>;
1428 };
1429
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1430 tmc_etr_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1431 qcom,dump-size = <0x1000>;
1432 qcom,dump-id = <0x100>;
1433 };
1434
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1435 tmc_etf_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1436 qcom,dump-size = <0x1000>;
1437 qcom,dump-id = <0x101>;
1438 };
1439
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1440 etfswao_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1441 qcom,dump-size = <0x1000>;
1442 qcom,dump-id = <0x102>;
1443 };
1444
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1445 misc_data {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1446 qcom,dump-size = <0x1000>;
1447 qcom,dump-id = <0xe8>;
1448 };
1449
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1450 power_regs {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1451 qcom,dump-size = <0x100000>;
1452 qcom,dump-id = <0xed>;
1453 };
1454 };
1455
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1456 kryo3xx-erp {
1457 compatible = "arm,arm64-kryo3xx-cpu-erp";
1458 interrupts = <1 6 4>,
1459 <1 7 4>,
1460 <0 34 4>,
1461 <0 35 4>;
1462
1463 interrupt-names = "l1-l2-faultirq",
1464 "l1-l2-errirq",
1465 "l3-scu-errirq",
1466 "l3-scu-faultirq";
1467 };
1468
Dhoat Harpala24cb2c2017-06-06 20:39:54 +0530[diff] [blame]1469 qcom,ipc-spinlock@1f40000 {
1470 compatible = "qcom,ipc-spinlock-sfpb";
1471 reg = <0x1f40000 0x8000>;
1472 qcom,num-locks = <8>;
1473 };
1474
Dhoat Harpaldd9bfaf2017-06-06 20:43:16 +0530[diff] [blame]1475 qcom,smem@86000000 {
1476 compatible = "qcom,smem";
1477 reg = <0x86000000 0x200000>,
1478 <0x17911008 0x4>,
1479 <0x778000 0x7000>,
1480 <0x1fd4000 0x8>;
1481 reg-names = "smem", "irq-reg-base", "aux-mem1",
1482 "smem_targ_info_reg";
1483 qcom,mpu-enabled;
1484 };
1485
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1486 qmp_aop: qcom,qmp-aop@c300000 {
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1487 compatible = "qcom,qmp-mbox";
1488 label = "aop";
1489 reg = <0xc300000 0x100000>,
1490 <0x1799000c 0x4>;
1491 reg-names = "msgram", "irq-reg-base";
1492 qcom,irq-mask = <0x1>;
1493 interrupts = <0 389 1>;
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1494 priority = <0>;
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1495 mbox-desc-offset = <0x0>;
1496 #mbox-cells = <1>;
1497 };
1498
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1499 qcom,glink-smem-native-xprt-modem@86000000 {
1500 compatible = "qcom,glink-smem-native-xprt";
1501 reg = <0x86000000 0x200000>,
1502 <0x1799000c 0x4>;
1503 reg-names = "smem", "irq-reg-base";
1504 qcom,irq-mask = <0x1000>;
1505 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1506 label = "mpss";
1507 };
1508
1509 qcom,glink-smem-native-xprt-adsp@86000000 {
1510 compatible = "qcom,glink-smem-native-xprt";
1511 reg = <0x86000000 0x200000>,
1512 <0x1799000c 0x4>;
1513 reg-names = "smem", "irq-reg-base";
Dhoat Harpal3adebbe2017-07-06 15:59:13 +0530[diff] [blame]1514 qcom,irq-mask = <0x1000000>;
1515 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1516 label = "lpass";
1517 qcom,qos-config = <&glink_qos_adsp>;
1518 qcom,ramp-time = <0xaf>;
1519 };
1520
1521 glink_qos_adsp: qcom,glink-qos-config-adsp {
1522 compatible = "qcom,glink-qos-config";
1523 qcom,flow-info = <0x3c 0x0>,
1524 <0x3c 0x0>,
1525 <0x3c 0x0>,
1526 <0x3c 0x0>;
1527 qcom,mtu-size = <0x800>;
1528 qcom,tput-stats-cycle = <0xa>;
1529 };
1530
1531 glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1532 compatible = "qcom,glink-spi-xprt";
1533 label = "wdsp";
1534 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1535 qcom,qos-config = <&glink_qos_wdsp>;
1536 qcom,ramp-time = <0x10>,
1537 <0x20>,
1538 <0x30>,
1539 <0x40>;
1540 };
1541
1542 glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1543 compatible = "qcom,glink-fifo-config";
1544 qcom,out-read-idx-reg = <0x12000>;
1545 qcom,out-write-idx-reg = <0x12004>;
1546 qcom,in-read-idx-reg = <0x1200C>;
1547 qcom,in-write-idx-reg = <0x12010>;
1548 };
1549
1550 glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1551 compatible = "qcom,glink-qos-config";
1552 qcom,flow-info = <0x80 0x0>,
1553 <0x70 0x1>,
1554 <0x60 0x2>,
1555 <0x50 0x3>;
1556 qcom,mtu-size = <0x800>;
1557 qcom,tput-stats-cycle = <0xa>;
1558 };
1559
1560 qcom,glink-smem-native-xprt-cdsp@86000000 {
1561 compatible = "qcom,glink-smem-native-xprt";
1562 reg = <0x86000000 0x200000>,
1563 <0x1799000c 0x4>;
1564 reg-names = "smem", "irq-reg-base";
1565 qcom,irq-mask = <0x10>;
1566 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1567 label = "cdsp";
1568 };
1569
Dhoat Harpal9cb73cc2017-06-06 20:58:14 +0530[diff] [blame]1570 glink_mpss: qcom,glink-ssr-modem {
1571 compatible = "qcom,glink_ssr";
1572 label = "modem";
1573 qcom,edge = "mpss";
1574 qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>;
1575 qcom,xprt = "smem";
1576 };
1577
1578 glink_lpass: qcom,glink-ssr-adsp {
1579 compatible = "qcom,glink_ssr";
1580 label = "adsp";
1581 qcom,edge = "lpass";
1582 qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>;
1583 qcom,xprt = "smem";
1584 };
1585
1586 glink_cdsp: qcom,glink-ssr-cdsp {
1587 compatible = "qcom,glink_ssr";
1588 label = "cdsp";
1589 qcom,edge = "cdsp";
1590 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>;
1591 qcom,xprt = "smem";
1592 };
1593
Dhoat Harpal22dafa92017-06-06 21:03:34 +0530[diff] [blame]1594 qcom,ipc_router {
1595 compatible = "qcom,ipc_router";
1596 qcom,node-id = <1>;
1597 };
1598
1599 qcom,ipc_router_modem_xprt {
1600 compatible = "qcom,ipc_router_glink_xprt";
1601 qcom,ch-name = "IPCRTR";
1602 qcom,xprt-remote = "mpss";
1603 qcom,glink-xprt = "smem";
1604 qcom,xprt-linkid = <1>;
1605 qcom,xprt-version = <1>;
1606 qcom,fragmented-data;
1607 };
1608
1609 qcom,ipc_router_q6_xprt {
1610 compatible = "qcom,ipc_router_glink_xprt";
1611 qcom,ch-name = "IPCRTR";
1612 qcom,xprt-remote = "lpass";
1613 qcom,glink-xprt = "smem";
1614 qcom,xprt-linkid = <1>;
1615 qcom,xprt-version = <1>;
1616 qcom,fragmented-data;
1617 };
1618
1619 qcom,ipc_router_cdsp_xprt {
1620 compatible = "qcom,ipc_router_glink_xprt";
1621 qcom,ch-name = "IPCRTR";
1622 qcom,xprt-remote = "cdsp";
1623 qcom,glink-xprt = "smem";
1624 qcom,xprt-linkid = <1>;
1625 qcom,xprt-version = <1>;
1626 qcom,fragmented-data;
1627 };
1628
Dhoat Harpal11d34482017-06-06 21:00:14 +0530[diff] [blame]1629 qcom,glink_pkt {
1630 compatible = "qcom,glinkpkt";
1631
1632 qcom,glinkpkt-at-mdm0 {
1633 qcom,glinkpkt-transport = "smem";
1634 qcom,glinkpkt-edge = "mpss";
1635 qcom,glinkpkt-ch-name = "DS";
1636 qcom,glinkpkt-dev-name = "at_mdm0";
1637 };
1638
1639 qcom,glinkpkt-loopback_cntl {
1640 qcom,glinkpkt-transport = "lloop";
1641 qcom,glinkpkt-edge = "local";
1642 qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1643 qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1644 };
1645
1646 qcom,glinkpkt-loopback_data {
1647 qcom,glinkpkt-transport = "lloop";
1648 qcom,glinkpkt-edge = "local";
1649 qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1650 qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1651 };
1652
1653 qcom,glinkpkt-apr-apps2 {
1654 qcom,glinkpkt-transport = "smem";
1655 qcom,glinkpkt-edge = "adsp";
1656 qcom,glinkpkt-ch-name = "apr_apps2";
1657 qcom,glinkpkt-dev-name = "apr_apps2";
1658 };
1659
1660 qcom,glinkpkt-data40-cntl {
1661 qcom,glinkpkt-transport = "smem";
1662 qcom,glinkpkt-edge = "mpss";
1663 qcom,glinkpkt-ch-name = "DATA40_CNTL";
1664 qcom,glinkpkt-dev-name = "smdcntl8";
1665 };
1666
1667 qcom,glinkpkt-data1 {
1668 qcom,glinkpkt-transport = "smem";
1669 qcom,glinkpkt-edge = "mpss";
1670 qcom,glinkpkt-ch-name = "DATA1";
1671 qcom,glinkpkt-dev-name = "smd7";
1672 };
1673
1674 qcom,glinkpkt-data4 {
1675 qcom,glinkpkt-transport = "smem";
1676 qcom,glinkpkt-edge = "mpss";
1677 qcom,glinkpkt-ch-name = "DATA4";
1678 qcom,glinkpkt-dev-name = "smd8";
1679 };
1680
1681 qcom,glinkpkt-data11 {
1682 qcom,glinkpkt-transport = "smem";
1683 qcom,glinkpkt-edge = "mpss";
1684 qcom,glinkpkt-ch-name = "DATA11";
1685 qcom,glinkpkt-dev-name = "smd11";
1686 };
1687 };
1688
Gaurav Kohlid1131902018-02-21 13:21:25 +0530[diff] [blame]1689 qcom,chd_silver {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1690 compatible = "qcom,core-hang-detect";
1691 label = "silver";
1692 qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
1693 0x17e30058 0x17e40058 0x17e50058>;
1694 qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
1695 0x17e30060 0x17e40060 0x17e50060>;
1696 };
1697
1698 qcom,chd_gold {
1699 compatible = "qcom,core-hang-detect";
1700 label = "gold";
1701 qcom,threshold-arr = <0x17e60058 0x17e70058>;
1702 qcom,config-arr = <0x17e60060 0x17e70060>;
1703 };
1704
1705 qcom,ghd {
1706 compatible = "qcom,gladiator-hang-detect-v2";
1707 qcom,threshold-arr = <0x1799041c 0x17990420>;
1708 qcom,config-reg = <0x17990434>;
1709 };
1710
1711 qcom,msm-gladiator-v3@17900000 {
1712 compatible = "qcom,msm-gladiator-v3";
1713 reg = <0x17900000 0xd080>;
1714 reg-names = "gladiator_base";
1715 interrupts = <0 17 0>;
1716 };
1717
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1718 eud: qcom,msm-eud@88e0000 {
1719 compatible = "qcom,msm-eud";
1720 interrupt-names = "eud_irq";
1721 interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
1722 reg = <0x88e0000 0x2000>;
1723 reg-names = "eud_base";
Lingutla Chandrasekhar5422daf2017-10-26 11:27:32 +0530[diff] [blame]1724 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1725 clock-names = "cfg_ahb_clk";
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1726 };
1727
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1728 qcom,llcc@1100000 {
1729 compatible = "qcom,llcc-core", "syscon", "simple-mfd";
1730 reg = <0x1100000 0x250000>;
1731 reg-names = "llcc_base";
1732 qcom,llcc-banks-off = <0x0 0x80000 >;
1733 qcom,llcc-broadcast-off = <0x200000>;
1734
1735 llcc: qcom,sdm670-llcc {
1736 compatible = "qcom,sdm670-llcc";
1737 #cache-cells = <1>;
1738 max-slices = <32>;
1739 qcom,dump-size = <0x80000>;
1740 };
1741
Sankaran Nampoothiri0c5dac02017-11-06 11:53:52 +0530[diff] [blame]1742 qcom,llcc-perfmon {
1743 compatible = "qcom,llcc-perfmon";
1744 };
1745
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1746 qcom,llcc-erp {
1747 compatible = "qcom,llcc-erp";
1748 interrupt-names = "ecc_irq";
1749 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1750 };
1751
1752 qcom,llcc-amon {
1753 compatible = "qcom,llcc-amon";
1754 };
1755
1756 LLCC_1: llcc_1_dcache {
1757 qcom,dump-size = <0xd8000>;
1758 };
1759
1760 LLCC_2: llcc_2_dcache {
1761 qcom,dump-size = <0xd8000>;
1762 };
1763 };
1764
Maulik Shah210773d2017-06-15 09:49:12 +0530[diff] [blame]1765 cmd_db: qcom,cmd-db@c3f000c {
1766 compatible = "qcom,cmd-db";
1767 reg = <0xc3f000c 0x8>;
1768 };
1769
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]1770 apps_rsc: mailbox@179e0000 {
1771 compatible = "qcom,tcs-drv";
1772 label = "apps_rsc";
1773 reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
1774 interrupts = <0 5 0>;
1775 #mbox-cells = <1>;
1776 qcom,drv-id = <2>;
1777 qcom,tcs-config = <ACTIVE_TCS 2>,
1778 <SLEEP_TCS 3>,
1779 <WAKE_TCS 3>,
1780 <CONTROL_TCS 1>;
1781 };
1782
Maulik Shahda3941f2017-06-15 09:41:38 +0530[diff] [blame]1783 disp_rsc: mailbox@af20000 {
1784 compatible = "qcom,tcs-drv";
1785 label = "display_rsc";
1786 reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
1787 interrupts = <0 129 0>;
1788 #mbox-cells = <1>;
1789 qcom,drv-id = <0>;
1790 qcom,tcs-config = <SLEEP_TCS 1>,
1791 <WAKE_TCS 1>,
1792 <ACTIVE_TCS 0>,
1793 <CONTROL_TCS 1>;
1794 };
1795
Maulik Shah0dd203f2017-06-15 09:44:59 +0530[diff] [blame]1796 system_pm {
1797 compatible = "qcom,system-pm";
1798 mboxes = <&apps_rsc 0>;
1799 };
1800
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1801 dcc: dcc_v2@10a2000 {
Mao Jinlong1d656f92018-04-09 16:09:44 +0800[diff] [blame]1802 compatible = "qcom,dcc-v2";
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1803 reg = <0x10a2000 0x1000>,
1804 <0x10ae000 0x2000>;
1805 reg-names = "dcc-base", "dcc-ram-base";
Saranya Chidurac0a161c2017-08-28 13:06:10 +0530[diff] [blame]1806
1807 dcc-ram-offset = <0x6000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1808 };
1809
Tirupathi Reddy9ae4c892017-06-09 12:30:31 +0530[diff] [blame]1810 spmi_bus: qcom,spmi@c440000 {
1811 compatible = "qcom,spmi-pmic-arb";
1812 reg = <0xc440000 0x1100>,
1813 <0xc600000 0x2000000>,
1814 <0xe600000 0x100000>,
1815 <0xe700000 0xa0000>,
1816 <0xc40a000 0x26000>;
1817 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1818 interrupt-names = "periph_irq";
1819 interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
1820 qcom,ee = <0>;
1821 qcom,channel = <0>;
1822 #address-cells = <2>;
1823 #size-cells = <0>;
1824 interrupt-controller;
1825 #interrupt-cells = <4>;
1826 cell-index = <0>;
1827 };
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1828
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1829 ufs_ice: ufsice@1d90000 {
1830 compatible = "qcom,ice";
1831 reg = <0x1d90000 0x8000>;
1832 qcom,enable-ice-clk;
1833 clock-names = "ufs_core_clk", "bus_clk",
1834 "iface_clk", "ice_core_clk";
1835 clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
1836 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1837 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1838 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1839 qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
1840 vdd-hba-supply = <&ufs_phy_gdsc>;
1841 qcom,msm-bus,name = "ufs_ice_noc";
1842 qcom,msm-bus,num-cases = <2>;
1843 qcom,msm-bus,num-paths = <1>;
1844 qcom,msm-bus,vectors-KBps =
1845 <1 650 0 0>, /* No vote */
1846 <1 650 1000 0>; /* Max. bandwidth */
1847 qcom,bus-vector-names = "MIN",
1848 "MAX";
1849 qcom,instance-type = "ufs";
1850 };
1851
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1852 ufsphy_mem: ufsphy_mem@1d87000 {
1853 reg = <0x1d87000 0xe00>; /* PHY regs */
1854 reg-names = "phy_mem";
1855 #phy-cells = <0>;
1856
1857 lanes-per-direction = <1>;
1858
1859 clock-names = "ref_clk_src",
1860 "ref_clk",
1861 "ref_aux_clk";
1862 clocks = <&clock_rpmh RPMH_CXO_CLK>,
1863 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1864 <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
1865
1866 status = "disabled";
1867 };
1868
1869 ufshc_mem: ufshc@1d84000 {
1870 compatible = "qcom,ufshc";
1871 reg = <0x1d84000 0x3000>;
1872 interrupts = <0 265 0>;
1873 phys = <&ufsphy_mem>;
1874 phy-names = "ufsphy";
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1875 ufs-qcom-crypto = <&ufs_ice>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1876
1877 lanes-per-direction = <1>;
Sayali Lokhande1e49f022018-09-07 12:24:43 +0530[diff] [blame^]1878 spm-level = <5>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1879 dev-ref-clk-freq = <0>; /* 19.2 MHz */
1880
1881 clock-names =
1882 "core_clk",
1883 "bus_aggr_clk",
1884 "iface_clk",
1885 "core_clk_unipro",
1886 "core_clk_ice",
1887 "ref_clk",
1888 "tx_lane0_sync_clk",
1889 "rx_lane0_sync_clk";
1890 clocks =
1891 <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]1892 <&clock_gcc UFS_PHY_AXI_UFS_VOTE_CLK>,
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1893 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1894 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
1895 <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
1896 <&clock_rpmh RPMH_CXO_CLK>,
1897 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1898 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1899 freq-table-hz =
1900 <50000000 200000000>,
1901 <0 0>,
1902 <0 0>,
1903 <37500000 150000000>,
1904 <75000000 300000000>,
1905 <0 0>,
1906 <0 0>,
1907 <0 0>;
1908
Sayali Lokhandeaa3db742017-10-09 15:13:01 +0530[diff] [blame]1909 non-removable;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1910 qcom,msm-bus,name = "ufshc_mem";
1911 qcom,msm-bus,num-cases = <12>;
1912 qcom,msm-bus,num-paths = <2>;
1913 qcom,msm-bus,vectors-KBps =
1914 /*
1915 * During HS G3 UFS runs at nominal voltage corner, vote
1916 * higher bandwidth to push other buses in the data path
1917 * to run at nominal to achieve max throughput.
1918 * 4GBps pushes BIMC to run at nominal.
1919 * 200MBps pushes CNOC to run at nominal.
1920 * Vote for half of this bandwidth for HS G3 1-lane.
1921 * For max bandwidth, vote high enough to push the buses
1922 * to run in turbo voltage corner.
1923 */
1924 <123 512 0 0>, <1 757 0 0>, /* No vote */
1925 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
1926 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
1927 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
1928 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
1929 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
1930 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
1931 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
1932 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
1933 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
1934 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
1935 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
1936
1937 qcom,bus-vector-names = "MIN",
1938 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1939 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1940 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1941 "MAX";
1942
1943 /* PM QoS */
1944 qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]1945 qcom,pm-qos-cpu-group-latency-us = <67 67>;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1946 qcom,pm-qos-default-cpu = <0>;
1947
Sayali Lokhandebd53f6a2018-04-05 16:32:08 +0530[diff] [blame]1948 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
1949 pinctrl-0 = <&ufs_dev_reset_assert>;
1950 pinctrl-1 = <&ufs_dev_reset_deassert>;
1951
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1952 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
1953 reset-names = "core_reset";
1954
1955 status = "disabled";
1956 };
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1957
1958 qcom,lpass@62400000 {
1959 compatible = "qcom,pil-tz-generic";
1960 reg = <0x62400000 0x00100>;
1961 interrupts = <0 162 1>;
1962
1963 vdd_cx-supply = <&pm660l_l9_level>;
1964 qcom,proxy-reg-names = "vdd_cx";
1965 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
1966
1967 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1968 clock-names = "xo";
1969 qcom,proxy-clock-names = "xo";
1970
1971 qcom,pas-id = <1>;
1972 qcom,proxy-timeout-ms = <10000>;
1973 qcom,smem-id = <423>;
1974 qcom,sysmon-id = <1>;
1975 qcom,ssctl-instance-id = <0x14>;
1976 qcom,firmware-name = "adsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1977 qcom,signal-aop;
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1978 memory-region = <&pil_adsp_mem>;
1979
1980 /* GPIO inputs from lpass */
1981 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
1982 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
1983 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
1984 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
1985
1986 /* GPIO output to lpass */
1987 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1988
1989 mboxes = <&qmp_aop 0>;
1990 mbox-names = "adsp-pil";
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1991 status = "ok";
1992 };
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]1993
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]1994 qcom,rmtfs_sharedmem@0 {
1995 compatible = "qcom,sharedmem-uio";
1996 reg = <0x0 0x200000>;
1997 reg-names = "rmtfs";
1998 qcom,client-id = <0x00000001>;
Sahitya Tummala57f7b572017-10-23 10:29:03 +0530[diff] [blame]1999 qcom,guard-memory;
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]2000 };
2001
Mohammed Javidf97a10e2017-10-08 13:11:26 +0530[diff] [blame]2002 qcom,msm_gsi {
2003 compatible = "qcom,msm_gsi";
2004 };
2005
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2006 qcom,rmnet-ipa {
2007 compatible = "qcom,rmnet-ipa3";
2008 qcom,rmnet-ipa-ssr;
2009 qcom,ipa-loaduC;
2010 qcom,ipa-advertise-sg-support;
2011 qcom,ipa-napi-enable;
2012 };
2013
2014 ipa_hw: qcom,ipa@01e00000 {
2015 compatible = "qcom,ipa";
2016 reg = <0x1e00000 0x34000>,
2017 <0x1e04000 0x2c000>;
2018 reg-names = "ipa-base", "gsi-base";
2019 interrupts =
2020 <0 311 0>,
2021 <0 432 0>;
2022 interrupt-names = "ipa-irq", "gsi-irq";
2023 qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
Mohammed Javiddcefa282018-04-10 17:22:30 +0530[diff] [blame]2024 qcom,ipa-hw-mode = <0>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2025 qcom,ee = <0>;
2026 qcom,use-ipa-tethering-bridge;
2027 qcom,modem-cfg-emb-pipe-flt;
2028 qcom,ipa-wdi2;
2029 qcom,use-64-bit-dma-mask;
2030 qcom,arm-smmu;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2031 qcom,bandwidth-vote-for-ipa;
2032 qcom,msm-bus,name = "ipa";
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2033 qcom,msm-bus,num-cases = <5>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2034 qcom,msm-bus,num-paths = <4>;
2035 qcom,msm-bus,vectors-KBps =
2036 /* No vote */
2037 <90 512 0 0>,
2038 <90 585 0 0>,
2039 <1 676 0 0>,
2040 <143 777 0 0>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2041 /* SVS2 */
2042 <90 512 80000 600000>,
2043 <90 585 80000 350000>,
2044 <1 676 40000 40000>, /*gcc_config_noc_clk_src */
2045 <143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2046 /* SVS */
2047 <90 512 80000 640000>,
2048 <90 585 80000 640000>,
2049 <1 676 80000 80000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2050 <143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2051 /* NOMINAL */
2052 <90 512 206000 960000>,
2053 <90 585 206000 960000>,
2054 <1 676 206000 160000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2055 <143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2056 /* TURBO */
2057 <90 512 206000 3600000>,
2058 <90 585 206000 3600000>,
2059 <1 676 206000 300000>,
Mohammed Javid6c065482017-09-19 19:19:27 +0530[diff] [blame]2060 <143 777 0 355>; /* IB defined for IPA clk in MHz*/
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2061 qcom,bus-vector-names =
2062 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2063
2064 /* IPA RAM mmap */
2065 qcom,ipa-ram-mmap = <
2066 0x280 /* ofst_start; */
2067 0x0 /* nat_ofst; */
2068 0x0 /* nat_size; */
2069 0x288 /* v4_flt_hash_ofst; */
2070 0x78 /* v4_flt_hash_size; */
2071 0x4000 /* v4_flt_hash_size_ddr; */
2072 0x308 /* v4_flt_nhash_ofst; */
2073 0x78 /* v4_flt_nhash_size; */
2074 0x4000 /* v4_flt_nhash_size_ddr; */
2075 0x388 /* v6_flt_hash_ofst; */
2076 0x78 /* v6_flt_hash_size; */
2077 0x4000 /* v6_flt_hash_size_ddr; */
2078 0x408 /* v6_flt_nhash_ofst; */
2079 0x78 /* v6_flt_nhash_size; */
2080 0x4000 /* v6_flt_nhash_size_ddr; */
2081 0xf /* v4_rt_num_index; */
2082 0x0 /* v4_modem_rt_index_lo; */
2083 0x7 /* v4_modem_rt_index_hi; */
2084 0x8 /* v4_apps_rt_index_lo; */
2085 0xe /* v4_apps_rt_index_hi; */
2086 0x488 /* v4_rt_hash_ofst; */
2087 0x78 /* v4_rt_hash_size; */
2088 0x4000 /* v4_rt_hash_size_ddr; */
2089 0x508 /* v4_rt_nhash_ofst; */
2090 0x78 /* v4_rt_nhash_size; */
2091 0x4000 /* v4_rt_nhash_size_ddr; */
2092 0xf /* v6_rt_num_index; */
2093 0x0 /* v6_modem_rt_index_lo; */
2094 0x7 /* v6_modem_rt_index_hi; */
2095 0x8 /* v6_apps_rt_index_lo; */
2096 0xe /* v6_apps_rt_index_hi; */
2097 0x588 /* v6_rt_hash_ofst; */
2098 0x78 /* v6_rt_hash_size; */
2099 0x4000 /* v6_rt_hash_size_ddr; */
2100 0x608 /* v6_rt_nhash_ofst; */
2101 0x78 /* v6_rt_nhash_size; */
2102 0x4000 /* v6_rt_nhash_size_ddr; */
2103 0x688 /* modem_hdr_ofst; */
2104 0x140 /* modem_hdr_size; */
2105 0x7c8 /* apps_hdr_ofst; */
2106 0x0 /* apps_hdr_size; */
2107 0x800 /* apps_hdr_size_ddr; */
2108 0x7d0 /* modem_hdr_proc_ctx_ofst; */
2109 0x200 /* modem_hdr_proc_ctx_size; */
2110 0x9d0 /* apps_hdr_proc_ctx_ofst; */
2111 0x200 /* apps_hdr_proc_ctx_size; */
2112 0x0 /* apps_hdr_proc_ctx_size_ddr; */
2113 0x0 /* modem_comp_decomp_ofst; diff */
2114 0x0 /* modem_comp_decomp_size; diff */
2115 0xbd8 /* modem_ofst; */
2116 0x1024 /* modem_size; */
2117 0x2000 /* apps_v4_flt_hash_ofst; */
2118 0x0 /* apps_v4_flt_hash_size; */
2119 0x2000 /* apps_v4_flt_nhash_ofst; */
2120 0x0 /* apps_v4_flt_nhash_size; */
2121 0x2000 /* apps_v6_flt_hash_ofst; */
2122 0x0 /* apps_v6_flt_hash_size; */
2123 0x2000 /* apps_v6_flt_nhash_ofst; */
2124 0x0 /* apps_v6_flt_nhash_size; */
2125 0x80 /* uc_info_ofst; */
2126 0x200 /* uc_info_size; */
2127 0x2000 /* end_ofst; */
2128 0x2000 /* apps_v4_rt_hash_ofst; */
2129 0x0 /* apps_v4_rt_hash_size; */
2130 0x2000 /* apps_v4_rt_nhash_ofst; */
2131 0x0 /* apps_v4_rt_nhash_size; */
2132 0x2000 /* apps_v6_rt_hash_ofst; */
2133 0x0 /* apps_v6_rt_hash_size; */
2134 0x2000 /* apps_v6_rt_nhash_ofst; */
2135 0x0 /* apps_v6_rt_nhash_size; */
2136 0x1c00 /* uc_event_ring_ofst; */
2137 0x400 /* uc_event_ring_size; */
2138 >;
2139
2140 /* smp2p gpio information */
2141 qcom,smp2pgpio_map_ipa_1_out {
2142 compatible = "qcom,smp2pgpio-map-ipa-1-out";
2143 gpios = <&smp2pgpio_ipa_1_out 0 0>;
2144 };
2145
2146 qcom,smp2pgpio_map_ipa_1_in {
2147 compatible = "qcom,smp2pgpio-map-ipa-1-in";
2148 gpios = <&smp2pgpio_ipa_1_in 0 0>;
2149 };
2150
2151 ipa_smmu_ap: ipa_smmu_ap {
2152 compatible = "qcom,ipa-smmu-ap-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2153 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2154 iommus = <&apps_smmu 0x720 0x0>;
2155 qcom,iova-mapping = <0x20000000 0x40000000>;
2156 };
2157
2158 ipa_smmu_wlan: ipa_smmu_wlan {
2159 compatible = "qcom,ipa-smmu-wlan-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2160 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2161 iommus = <&apps_smmu 0x721 0x0>;
2162 };
2163
2164 ipa_smmu_uc: ipa_smmu_uc {
2165 compatible = "qcom,ipa-smmu-uc-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2166 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2167 iommus = <&apps_smmu 0x722 0x0>;
2168 qcom,iova-mapping = <0x40000000 0x20000000>;
2169 };
2170 };
2171
2172 qcom,ipa_fws {
2173 compatible = "qcom,pil-tz-generic";
2174 qcom,pas-id = <0xf>;
2175 qcom,firmware-name = "ipa_fws";
Mohammed Javid42445cb2018-02-01 18:22:17 +0530[diff] [blame]2176 qcom,pil-force-shutdown;
Mohammed Javide0dd2a32018-01-25 14:18:56 +0530[diff] [blame]2177 memory-region = <&pil_ipa_fw_mem>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2178 };
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2179
2180 pil_modem: qcom,mss@4080000 {
2181 compatible = "qcom,pil-q6v55-mss";
2182 reg = <0x4080000 0x100>,
2183 <0x1f63000 0x008>,
2184 <0x1f65000 0x008>,
2185 <0x1f64000 0x008>,
2186 <0x4180000 0x020>,
2187 <0xc2b0000 0x004>,
2188 <0xb2e0100 0x004>,
2189 <0x4180044 0x004>;
2190 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2191 "halt_nc", "rmb_base", "restart_reg",
2192 "pdc_sync", "alt_reset";
2193
2194 clocks = <&clock_rpmh RPMH_CXO_CLK>,
2195 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2196 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2197 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2198 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2199 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2200 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
2201 <&clock_gcc GCC_PRNG_AHB_CLK>;
2202 clock-names = "xo", "iface_clk", "bus_clk",
2203 "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2204 "mnoc_axi_clk", "prng_clk";
2205 qcom,proxy-clock-names = "xo", "prng_clk";
2206 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2207 "gpll0_mss_clk", "snoc_axi_clk",
2208 "mnoc_axi_clk";
2209
2210 interrupts = <0 266 1>;
2211 vdd_cx-supply = <&pm660l_s3_level>;
2212 vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
2213 vdd_mx-supply = <&pm660l_s1_level>;
2214 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Jitendra Sharma2e981ef2017-10-30 12:16:23 +0530[diff] [blame]2215 vdd_mss-supply = <&pm660_s5_level>;
2216 vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2217 qcom,firmware-name = "modem";
2218 qcom,pil-self-auth;
2219 qcom,sysmon-id = <0>;
Avaneesh Kumar Dwivedi8d336612017-11-09 16:48:25 +0530[diff] [blame]2220 qcom,minidump-id = <3>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2221 qcom,ssctl-instance-id = <0x12>;
2222 qcom,override-acc;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2223 qcom,signal-aop;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2224 qcom,qdsp6v65-1-0;
Jitendra Sharma93dd7fc2017-10-14 17:38:55 +0530[diff] [blame]2225 qcom,mss_pdc_offset = <9>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2226 status = "ok";
2227 memory-region = <&pil_modem_mem>;
2228 qcom,mem-protect-id = <0xF>;
Shadab Naseem60b870a2018-05-11 14:31:03 +0530[diff] [blame]2229 qcom,complete-ramdump;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2230
2231 /* GPIO inputs from mss */
2232 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2233 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2234 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2235 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2236 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2237
2238 /* GPIO output to mss */
2239 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2240
2241 mboxes = <&qmp_aop 0>;
2242 mbox-names = "mss-pil";
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2243 qcom,mba-mem@0 {
2244 compatible = "qcom,pil-mba-mem";
2245 memory-region = <&pil_mba_mem>;
2246 };
2247 };
Gaurav Kohli985a99d2017-07-25 18:46:45 +0530[diff] [blame]2248
2249 qcom,venus@aae0000 {
2250 compatible = "qcom,pil-tz-generic";
2251 reg = <0xaae0000 0x4000>;
2252
2253 vdd-supply = <&venus_gdsc>;
2254 qcom,proxy-reg-names = "vdd";
2255
2256 clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2257 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
2258 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2259 clock-names = "core_clk", "iface_clk", "bus_clk";
2260 qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
2261
2262 qcom,pas-id = <9>;
2263 qcom,msm-bus,name = "pil-venus";
2264 qcom,msm-bus,num-cases = <2>;
2265 qcom,msm-bus,num-paths = <1>;
2266 qcom,msm-bus,vectors-KBps =
2267 <63 512 0 0>,
2268 <63 512 0 304000>;
2269 qcom,proxy-timeout-ms = <100>;
2270 qcom,firmware-name = "venus";
2271 memory-region = <&pil_video_mem>;
2272 status = "ok";
2273 };
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2274
2275 qcom,turing@8300000 {
2276 compatible = "qcom,pil-tz-generic";
2277 reg = <0x8300000 0x100000>;
2278 interrupts = <0 578 1>;
2279
2280 vdd_cx-supply = <&pm660l_s3_level>;
2281 qcom,proxy-reg-names = "vdd_cx";
2282 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2283
2284 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2285 clock-names = "xo";
2286 qcom,proxy-clock-names = "xo";
2287
2288 qcom,pas-id = <18>;
2289 qcom,proxy-timeout-ms = <10000>;
2290 qcom,smem-id = <601>;
2291 qcom,sysmon-id = <7>;
2292 qcom,ssctl-instance-id = <0x17>;
2293 qcom,firmware-name = "cdsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2294 qcom,signal-aop;
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2295 memory-region = <&pil_cdsp_mem>;
2296
2297 /* GPIO inputs from turing */
2298 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2299 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2300 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2301 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2302
2303 /* GPIO output to turing*/
2304 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2305
2306 mboxes = <&qmp_aop 0>;
2307 mbox-names = "cdsp-pil";
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2308 status = "ok";
2309 };
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2310
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2311 sdcc1_ice: sdcc1ice@7c8000 {
2312 compatible = "qcom,ice";
2313 reg = <0x7c8000 0x8000>;
2314 qcom,enable-ice-clk;
2315 clock-names = "ice_core_clk_src", "ice_core_clk",
2316 "bus_clk", "iface_clk";
2317 clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
2318 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2319 <&clock_gcc GCC_SDCC1_APPS_CLK>,
2320 <&clock_gcc GCC_SDCC1_AHB_CLK>;
2321 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
2322 qcom,msm-bus,name = "sdcc_ice_noc";
2323 qcom,msm-bus,num-cases = <2>;
2324 qcom,msm-bus,num-paths = <1>;
2325 qcom,msm-bus,vectors-KBps =
2326 <150 512 0 0>, /* No vote */
2327 <150 512 1000 0>; /* Max. bandwidth */
2328 qcom,bus-vector-names = "MIN",
2329 "MAX";
2330 qcom,instance-type = "sdcc";
2331 };
2332
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2333 sdhc_1: sdhci@7c4000 {
2334 compatible = "qcom,sdhci-msm-v5";
2335 reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
2336 reg-names = "hc_mem", "cmdq_mem";
2337
2338 interrupts = <0 641 0>, <0 644 0>;
2339 interrupt-names = "hc_irq", "pwr_irq";
2340
2341 qcom,bus-width = <8>;
2342 qcom,large-address-bus;
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2343 sdhc-msm-crypto = <&sdcc1_ice>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2344
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2345 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2346 192000000 384000000>;
Vijay Viswanath01db23a2017-11-09 15:46:22 +0530[diff] [blame]2347 qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
2348 100000000 200000000 200000000>;
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2349 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2350
2351 qcom,devfreq,freq-table = <50000000 200000000>;
2352
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2353 qcom,msm-bus,name = "sdhc1";
2354 qcom,msm-bus,num-cases = <9>;
2355 qcom,msm-bus,num-paths = <2>;
2356 qcom,msm-bus,vectors-KBps =
2357 /* No vote */
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2358 <150 512 0 0>, <1 782 0 0>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2359 /* 400 KB/s*/
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2360 <150 512 1046 1600>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2361 <1 782 1600 1600>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2362 /* 20 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2363 <150 512 52286 80000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2364 <1 782 80000 80000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2365 /* 25 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2366 <150 512 65360 100000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2367 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2368 /* 50 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2369 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2370 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2371 /* 100 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2372 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2373 <1 782 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2374 /* 200 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2375 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2376 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2377 /* 400 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2378 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2379 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2380 /* Max. bandwidth */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2381 <150 512 1338562 4096000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2382 <1 782 1338562 4096000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2383 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2384 100000000 200000000 400000000 4294967295>;
2385
2386 /* PM QoS */
2387 qcom,pm-qos-irq-type = "affine_irq";
Vijay Viswanathcac6f862018-03-20 11:40:54 +0530[diff] [blame]2388 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2389 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2390 qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
2391 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2392
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2393 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2394 <&clock_gcc GCC_SDCC1_APPS_CLK>,
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2395 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]2396 <&clock_gcc UFS_PHY_AXI_EMMC_VOTE_CLK>;
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2397 clock-names = "iface_clk", "core_clk", "ice_core_clk",
2398 "bus_aggr_clk";
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2399
2400 qcom,ice-clk-rates = <300000000 75000000>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2401
Vijay Viswanathd4dcf5f2017-10-17 15:42:00 +0530[diff] [blame]2402 qcom,ddr-config = <0xC3040873>;
2403
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2404 qcom,nonremovable;
Asutosh Das3d37f972018-01-12 15:48:25 +0530[diff] [blame]2405 nvmem-cells = <&minor_rev>;
2406 nvmem-cell-names = "minor_rev";
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2407
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2408 status = "disabled";
2409 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2410
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2411 sdhc_2: sdhci@8804000 {
2412 compatible = "qcom,sdhci-msm-v5";
2413 reg = <0x8804000 0x1000>;
2414 reg-names = "hc_mem";
2415
2416 interrupts = <0 204 0>, <0 222 0>;
2417 interrupt-names = "hc_irq", "pwr_irq";
2418
2419 qcom,bus-width = <4>;
2420 qcom,large-address-bus;
2421
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2422 qcom,clk-rates = <400000 20000000 25000000
2423 50000000 100000000 201500000>;
2424 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2425 "SDR104";
2426
2427 qcom,devfreq,freq-table = <50000000 201500000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2428
2429 qcom,msm-bus,name = "sdhc2";
2430 qcom,msm-bus,num-cases = <8>;
2431 qcom,msm-bus,num-paths = <2>;
2432 qcom,msm-bus,vectors-KBps =
2433 /* No vote */
2434 <81 512 0 0>, <1 608 0 0>,
2435 /* 400 KB/s*/
2436 <81 512 1046 1600>,
2437 <1 608 1600 1600>,
2438 /* 20 MB/s */
2439 <81 512 52286 80000>,
2440 <1 608 80000 80000>,
2441 /* 25 MB/s */
2442 <81 512 65360 100000>,
2443 <1 608 100000 100000>,
2444 /* 50 MB/s */
2445 <81 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2446 <1 608 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2447 /* 100 MB/s */
2448 <81 512 261438 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2449 <1 608 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2450 /* 200 MB/s */
2451 <81 512 261438 400000>,
2452 <1 608 300000 300000>,
2453 /* Max. bandwidth */
2454 <81 512 1338562 4096000>,
2455 <1 608 1338562 4096000>;
2456 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2457 100000000 200000000 4294967295>;
2458
2459 /* PM QoS */
2460 qcom,pm-qos-irq-type = "affine_irq";
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2461 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2462 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2463 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2464
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2465 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
2466 <&clock_gcc GCC_SDCC2_APPS_CLK>;
2467 clock-names = "iface_clk", "core_clk";
2468
2469 status = "disabled";
2470 };
2471
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2472 qcom,msm-cdsp-loader {
2473 compatible = "qcom,cdsp-loader";
2474 qcom,proc-img-to-load = "cdsp";
2475 };
2476
2477 qcom,msm-adsprpc-mem {
2478 compatible = "qcom,msm-adsprpc-mem-region";
2479 memory-region = <&adsp_mem>;
Tharun Kumar Merugu8bb71292018-01-17 15:55:05 +0530[diff] [blame]2480 restrict-access;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2481 };
2482
2483 qcom,msm_fastrpc {
2484 compatible = "qcom,msm-fastrpc-compute";
Tharun Kumar Merugubbebad12017-12-21 16:33:03 +0530[diff] [blame]2485 qcom,adsp-remoteheap-vmid = <22 37>;
Tharun Kumar Merugu1cb19c62018-01-18 12:20:16 +0530[diff] [blame]2486 qcom,fastrpc-adsp-audio-pdr;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2487 qcom,fastrpc-adsp-sensors-pdr;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2488
2489 qcom,msm_fastrpc_compute_cb1 {
2490 compatible = "qcom,msm-fastrpc-compute-cb";
2491 label = "cdsprpc-smd";
2492 iommus = <&apps_smmu 0x1421 0x30>;
2493 dma-coherent;
2494 };
2495 qcom,msm_fastrpc_compute_cb2 {
2496 compatible = "qcom,msm-fastrpc-compute-cb";
2497 label = "cdsprpc-smd";
2498 iommus = <&apps_smmu 0x1422 0x30>;
2499 dma-coherent;
2500 };
2501 qcom,msm_fastrpc_compute_cb3 {
2502 compatible = "qcom,msm-fastrpc-compute-cb";
2503 label = "cdsprpc-smd";
2504 iommus = <&apps_smmu 0x1423 0x30>;
2505 dma-coherent;
2506 };
2507 qcom,msm_fastrpc_compute_cb4 {
2508 compatible = "qcom,msm-fastrpc-compute-cb";
2509 label = "cdsprpc-smd";
2510 iommus = <&apps_smmu 0x1424 0x30>;
2511 dma-coherent;
2512 };
2513 qcom,msm_fastrpc_compute_cb5 {
2514 compatible = "qcom,msm-fastrpc-compute-cb";
2515 label = "cdsprpc-smd";
2516 iommus = <&apps_smmu 0x1425 0x30>;
2517 dma-coherent;
2518 };
2519 qcom,msm_fastrpc_compute_cb6 {
2520 compatible = "qcom,msm-fastrpc-compute-cb";
2521 label = "cdsprpc-smd";
2522 iommus = <&apps_smmu 0x1426 0x30>;
2523 dma-coherent;
2524 };
2525 qcom,msm_fastrpc_compute_cb7 {
2526 compatible = "qcom,msm-fastrpc-compute-cb";
2527 label = "cdsprpc-smd";
2528 qcom,secure-context-bank;
2529 iommus = <&apps_smmu 0x1429 0x30>;
2530 dma-coherent;
2531 };
2532 qcom,msm_fastrpc_compute_cb8 {
2533 compatible = "qcom,msm-fastrpc-compute-cb";
2534 label = "cdsprpc-smd";
2535 qcom,secure-context-bank;
2536 iommus = <&apps_smmu 0x142A 0x30>;
2537 dma-coherent;
2538 };
2539 qcom,msm_fastrpc_compute_cb9 {
2540 compatible = "qcom,msm-fastrpc-compute-cb";
2541 label = "adsprpc-smd";
2542 iommus = <&apps_smmu 0x1803 0x0>;
2543 dma-coherent;
2544 };
2545 qcom,msm_fastrpc_compute_cb10 {
2546 compatible = "qcom,msm-fastrpc-compute-cb";
2547 label = "adsprpc-smd";
2548 iommus = <&apps_smmu 0x1804 0x0>;
2549 dma-coherent;
2550 };
2551 qcom,msm_fastrpc_compute_cb11 {
2552 compatible = "qcom,msm-fastrpc-compute-cb";
2553 label = "adsprpc-smd";
2554 iommus = <&apps_smmu 0x1805 0x0>;
2555 dma-coherent;
2556 };
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2557 qcom,msm_fastrpc_compute_cb12 {
2558 compatible = "qcom,msm-fastrpc-compute-cb";
2559 label = "adsprpc-smd";
2560 iommus = <&apps_smmu 0x1806 0x0>;
2561 dma-coherent;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2562 shared-cb;
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2563 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2564 };
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2565
Rupesh Tatiyaf2072952017-10-08 19:57:12 +0530[diff] [blame]2566 bluetooth: bt_wcn3990 {
2567 compatible = "qca,wcn3990";
2568 qca,bt-vdd-core-supply = <&pm660_l9>;
2569 qca,bt-vdd-pa-supply = <&pm660_l6>;
2570 qca,bt-vdd-ldo-supply = <&pm660_l19>;
2571
2572 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
2573 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
2574 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
2575
2576 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
2577 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
2578 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
2579 };
2580
Sarada Prasanna Garnayakd5ccc902018-02-22 15:54:50 +0530[diff] [blame]2581 icnss: qcom,icnss@18800000 {
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2582 compatible = "qcom,icnss";
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2583 reg = <0x18800000 0x800000>,
2584 <0xa0000000 0x10000000>,
2585 <0xb0000000 0x10000>;
2586 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
2587 iommus = <&apps_smmu 0x0040 0x1>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2588 interrupts = <0 414 0 /* CE0 */ >,
2589 <0 415 0 /* CE1 */ >,
2590 <0 416 0 /* CE2 */ >,
2591 <0 417 0 /* CE3 */ >,
2592 <0 418 0 /* CE4 */ >,
2593 <0 419 0 /* CE5 */ >,
2594 <0 420 0 /* CE6 */ >,
2595 <0 421 0 /* CE7 */ >,
2596 <0 422 0 /* CE8 */ >,
2597 <0 423 0 /* CE9 */ >,
2598 <0 424 0 /* CE10 */ >,
2599 <0 425 0 /* CE11 */ >;
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2600 vdd-0.8-cx-mx-supply = <&pm660_l5>;
2601 vdd-1.8-xo-supply = <&pm660_l9>;
2602 vdd-1.3-rfa-supply = <&pm660_l6>;
2603 vdd-3.3-ch0-supply = <&pm660_l19>;
Hardik Kantilal Patel25c05b42017-12-08 11:10:27 +0530[diff] [blame]2604 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2605 qcom,wlan-msa-memory = <0x100000>;
Anurag Chouhana4f55db2017-11-22 16:35:27 +0530[diff] [blame]2606 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
Hardik Kantilal Patel1697bd12018-03-05 14:46:29 +0530[diff] [blame]2607 qcom,gpio-force-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
2608 qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2609 qcom,smmu-s1-bypass;
2610 };
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2611
2612 cpubw: qcom,cpubw {
2613 compatible = "qcom,devbw";
2614 governor = "performance";
2615 qcom,src-dst-ports =
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2616 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2617 qcom,active-only;
2618 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2619 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2620 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2621 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2622 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2623 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2624 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2625 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2626 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2627 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2628 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2629 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2630 };
2631
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2632 bwmon: qcom,cpu-bwmon {
2633 compatible = "qcom,bimc-bwmon4";
2634 reg = <0x1436400 0x300>, <0x1436300 0x200>;
2635 reg-names = "base", "global_base";
2636 interrupts = <0 581 4>;
2637 qcom,mport = <0>;
Santosh Mardida0b0f82017-10-13 23:30:22 +0530[diff] [blame]2638 qcom,count-unit = <0x10000>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2639 qcom,hw-timer-hz = <19200000>;
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2640 qcom,target-dev = <&cpubw>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2641 };
2642
2643 memlat_cpu0: qcom,memlat-cpu0 {
2644 compatible = "qcom,devbw";
2645 governor = "powersave";
2646 qcom,src-dst-ports = <1 512>;
2647 qcom,active-only;
2648 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2649 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2650 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2651 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2652 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2653 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2654 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2655 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2656 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2657 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2658 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2659 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2660 };
2661
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2662 memlat_cpu6: qcom,memlat-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2663 compatible = "qcom,devbw";
2664 governor = "powersave";
2665 qcom,src-dst-ports = <1 512>;
2666 qcom,active-only;
2667 status = "ok";
2668 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2669 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2670 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2671 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2672 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2673 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2674 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2675 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2676 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2677 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2678 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2679 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2680 };
2681
Odelu Kukatlafe8d3302017-11-17 10:54:32 +0530[diff] [blame]2682 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
2683 compatible = "qcom,devbw";
2684 governor = "powersave";
2685 qcom,src-dst-ports = <139 627>;
2686 qcom,active-only;
2687 status = "ok";
2688 qcom,bw-tbl =
2689 < 1 >;
2690 };
2691
Odelu Kukatla95e7aea2018-02-27 15:46:39 +0530[diff] [blame]2692 bus_proxy_client: qcom,bus_proxy_client {
2693 compatible = "qcom,bus-proxy-client";
2694 qcom,msm-bus,name = "bus-proxy-client";
2695 qcom,msm-bus,num-cases = <2>;
2696 qcom,msm-bus,num-paths = <2>;
2697 qcom,msm-bus,vectors-KBps =
2698 <22 512 0 0>, <23 512 0 0>,
2699 <22 512 0 5000000>, <23 512 0 5000000>;
2700 qcom,msm-bus,active-only;
2701 status = "ok";
2702 };
2703
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2704 devfreq_memlat_0: qcom,cpu0-memlat-mon {
2705 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2706 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2707 qcom,target-dev = <&memlat_cpu0>;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2708 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2709 qcom,core-dev-table =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2710 < 748800 MHZ_TO_MBPS( 300, 4) >,
2711 < 998400 MHZ_TO_MBPS( 451, 4) >,
2712 < 1209600 MHZ_TO_MBPS( 547, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2713 < 1516800 MHZ_TO_MBPS( 768, 4) >,
2714 < 1708000 MHZ_TO_MBPS(1017, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2715 };
2716
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2717 devfreq_memlat_6: qcom,cpu6-memlat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2718 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2719 qcom,cpulist = <&CPU6 &CPU7>;
2720 qcom,target-dev = <&memlat_cpu6>;
2721 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2722 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2723 < 825600 MHZ_TO_MBPS( 300, 4) >,
2724 < 1132800 MHZ_TO_MBPS( 547, 4) >,
2725 < 1363200 MHZ_TO_MBPS(1017, 4) >,
2726 < 1996800 MHZ_TO_MBPS(1555, 4) >,
2727 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2728 };
2729
2730 l3_cpu0: qcom,l3-cpu0 {
2731 compatible = "devfreq-simple-dev";
2732 clock-names = "devfreq_clk";
2733 clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
2734 governor = "performance";
2735 };
2736
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2737 l3_cpu6: qcom,l3-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2738 compatible = "devfreq-simple-dev";
2739 clock-names = "devfreq_clk";
2740 clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
2741 governor = "performance";
2742 };
2743
2744 devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
2745 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2746 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2747 qcom,target-dev = <&l3_cpu0>;
2748 qcom,cachemiss-ev = <0x17>;
2749 qcom,core-dev-table =
Santosh Mardi10d45032017-11-02 17:25:54 +0530[diff] [blame]2750 < 576000 300000000 >,
Santosh Mardi831cc872018-01-11 14:52:32 +0530[diff] [blame]2751 < 998400 556800000 >,
2752 < 1209660 844800000 >,
2753 < 1516800 940800000 >,
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2754 < 1612800 1382400000 >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2755 < 1708000 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2756 };
2757
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2758 devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2759 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2760 qcom,cpulist = <&CPU6 &CPU7>;
2761 qcom,target-dev = <&l3_cpu6>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2762 qcom,cachemiss-ev = <0x17>;
2763 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2764 < 1132800 556800000 >,
2765 < 1363200 806400000 >,
2766 < 1747200 940800000 >,
2767 < 1996800 1190400000 >,
2768 < 2457600 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2769 };
2770
2771 mincpubw: qcom,mincpubw {
2772 compatible = "qcom,devbw";
2773 governor = "powersave";
2774 qcom,src-dst-ports = <1 512>;
2775 qcom,active-only;
2776 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2777 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2778 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2779 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2780 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2781 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2782 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2783 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2784 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2785 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2786 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2787 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2788 };
2789
2790 devfreq-cpufreq {
2791 mincpubw-cpufreq {
2792 target-dev = <&mincpubw>;
2793 cpu-to-dev-map-0 =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2794 < 748800 MHZ_TO_MBPS( 300, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2795 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2796 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2797 < 1708000 MHZ_TO_MBPS( 768, 4) >;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2798 cpu-to-dev-map-6 =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2799 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2800 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2801 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2802 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2803 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2804 };
2805 };
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2806
Jonathan Avilac7a6fd52017-10-12 15:24:05 -0700[diff] [blame]2807 mincpu0bw: qcom,mincpu0bw {
2808 compatible = "qcom,devbw";
2809 governor = "powersave";
2810 qcom,src-dst-ports = <1 512>;
2811 qcom,active-only;
2812 qcom,bw-tbl =
2813 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2814 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2815 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2816 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2817 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2818 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2819 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2820 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2821 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2822 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2823 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2824 };
2825
2826 mincpu6bw: qcom,mincpu6bw {
2827 compatible = "qcom,devbw";
2828 governor = "powersave";
2829 qcom,src-dst-ports = <1 512>;
2830 qcom,active-only;
2831 qcom,bw-tbl =
2832 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2833 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2834 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2835 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2836 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2837 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2838 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2839 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2840 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2841 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2842 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2843 };
2844
2845 devfreq_compute0: qcom,devfreq-compute0 {
2846 compatible = "qcom,arm-cpu-mon";
2847 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
2848 qcom,target-dev = <&mincpu0bw>;
2849 qcom,core-dev-table =
2850 < 748800 MHZ_TO_MBPS( 300, 4) >,
2851 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2852 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2853 < 1708000 MHZ_TO_MBPS( 768, 4) >;
2854 };
2855
2856 devfreq_compute6: qcom,devfreq-compute6 {
2857 compatible = "qcom,arm-cpu-mon";
2858 qcom,cpulist = <&CPU6 &CPU7>;
2859 qcom,target-dev = <&mincpu6bw>;
2860 qcom,core-dev-table =
2861 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2862 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2863 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2864 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2865 < 2457600 MHZ_TO_MBPS(1804, 4) >;
2866 };
2867
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]2868 l3_cdsp: qcom,l3-cdsp {
2869 compatible = "devfreq-simple-dev";
2870 clock-names = "devfreq_clk";
2871 clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;
2872 governor = "powersave";
2873 };
2874
Raghavendra Rao Ananta28dd4502017-10-18 10:28:31 -0700[diff] [blame]2875 cpu_pmu: cpu-pmu {
2876 compatible = "arm,armv8-pmuv3";
2877 qcom,irq-is-percpu;
2878 interrupts = <1 5 4>;
2879 };
2880
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2881 gpu_gx_domain_addr: syscon@0x5091508 {
2882 compatible = "syscon";
2883 reg = <0x5091508 0x4>;
2884 };
2885
2886 gpu_gx_sw_reset: syscon@0x5091008 {
2887 compatible = "syscon";
2888 reg = <0x5091008 0x4>;
2889 };
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2890
2891 qfprom: qfprom@0x780000 {
2892 compatible = "qcom,qfprom";
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2893 reg = <0x00784000 0x1000>;
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2894 #address-cells = <1>;
2895 #size-cells = <1>;
2896 ranges;
2897
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2898 minor_rev: minor_rev@0x78414c {
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2899 reg = <0x14c 0x4>;
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2900 bits = <0 30>; /* Access 30 bits from bit offset 0 */
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2901 };
2902 };
2903
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2904};
2905
Ashay Jaiswal81940302017-09-20 15:17:58 +0530[diff] [blame]2906#include "pm660.dtsi"
2907#include "pm660l.dtsi"
2908#include "sdm670-regulator.dtsi"
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2909#include "sdm670-pinctrl.dtsi"
Vijayanand Jittad48c4082017-06-07 15:07:51 +0530[diff] [blame]2910#include "msm-arm-smmu-sdm670.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2911#include "msm-gdsc-sdm845.dtsi"
Maulik Shahd313ea82017-06-14 13:10:52 +0530[diff] [blame]2912#include "sdm670-pm.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2913
2914&usb30_prim_gdsc {
2915 status = "ok";
2916};
2917
2918&ufs_phy_gdsc {
2919 status = "ok";
2920};
2921
2922&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
2923 status = "ok";
2924};
2925
2926&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
2927 status = "ok";
2928};
2929
2930&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
2931 status = "ok";
2932};
2933
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2934&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
2935 status = "ok";
2936};
2937
2938&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
2939 status = "ok";
2940};
2941
2942&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
2943 status = "ok";
2944};
2945
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2946&bps_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2947 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2948 status = "ok";
2949};
2950
2951&ife_0_gdsc {
2952 status = "ok";
2953};
2954
2955&ife_1_gdsc {
2956 status = "ok";
2957};
2958
2959&ipe_0_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2960 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2961 status = "ok";
2962};
2963
2964&ipe_1_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2965 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2966 status = "ok";
2967};
2968
2969&titan_top_gdsc {
2970 status = "ok";
2971};
2972
2973&mdss_core_gdsc {
2974 status = "ok";
Sandeep Pandaae888352017-11-15 13:15:31 +0530[diff] [blame]2975 proxy-supply = <&mdss_core_gdsc>;
2976 qcom,proxy-consumer-enable;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2977};
2978
2979&gpu_cx_gdsc {
Odelu Kukatla4abca302018-06-19 12:46:47 +0530[diff] [blame]2980 parent-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2981 status = "ok";
2982};
2983
2984&gpu_gx_gdsc {
2985 clock-names = "core_root_clk";
2986 clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
2987 qcom,force-enable-root-clk;
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2988 parent-supply = <&pm660l_s2_level>;
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2989 domain-addr = <&gpu_gx_domain_addr>;
2990 sw-reset = <&gpu_gx_sw_reset>;
2991 qcom,reset-aon-logic;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2992 status = "ok";
2993};
2994
2995&vcodec0_gdsc {
2996 qcom,support-hw-trigger;
2997 status = "ok";
2998};
2999
3000&vcodec1_gdsc {
3001 qcom,support-hw-trigger;
3002 status = "ok";
3003};
3004
3005&venus_gdsc {
3006 status = "ok";
3007};
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]3008
Sandeep Panda229db242017-10-03 11:32:29 +0530[diff] [blame]3009&mdss_dsi0 {
3010 qcom,core-supply-entries {
3011 #address-cells = <1>;
3012 #size-cells = <0>;
3013
3014 qcom,core-supply-entry@0 {
3015 reg = <0>;
3016 qcom,supply-name = "refgen";
3017 qcom,supply-min-voltage = <0>;
3018 qcom,supply-max-voltage = <0>;
3019 qcom,supply-enable-load = <0>;
3020 qcom,supply-disable-load = <0>;
3021 };
3022 };
3023};
3024
3025&mdss_dsi1 {
3026 qcom,core-supply-entries {
3027 #address-cells = <1>;
3028 #size-cells = <0>;
3029
3030 qcom,core-supply-entry@0 {
3031 reg = <0>;
3032 qcom,supply-name = "refgen";
3033 qcom,supply-min-voltage = <0>;
3034 qcom,supply-max-voltage = <0>;
3035 qcom,supply-enable-load = <0>;
3036 qcom,supply-disable-load = <0>;
3037 };
3038 };
3039};
3040
Padmanabhan Komanduru07137332017-10-20 12:53:23 +0530[diff] [blame]3041&sde_dp {
3042 qcom,core-supply-entries {
3043 #address-cells = <1>;
3044 #size-cells = <0>;
3045
3046 qcom,core-supply-entry@0 {
3047 reg = <0>;
3048 qcom,supply-name = "refgen";
3049 qcom,supply-min-voltage = <0>;
3050 qcom,supply-max-voltage = <0>;
3051 qcom,supply-enable-load = <0>;
3052 qcom,supply-disable-load = <0>;
3053 };
3054 };
3055};
3056
Rohit Kumar14051282017-07-12 11:18:48 +0530[diff] [blame]3057#include "sdm670-audio.dtsi"
Pratham Pratap9e420a32017-09-05 11:26:57 +0530[diff] [blame]3058#include "sdm670-usb.dtsi"
Rajesh Kemisettiba56c482017-08-31 18:12:35 +0530[diff] [blame]3059#include "sdm670-gpu.dtsi"
Suresh Vankadara402d0ca2017-10-26 22:54:54 +0530[diff] [blame]3060#include "sdm670-camera.dtsi"
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]3061#include "sdm670-thermal.dtsi"
Odelu Kukatlaf197e382017-07-04 19:47:35 +0530[diff] [blame]3062#include "sdm670-bus.dtsi"
Tirupathi Reddyf805ac72017-10-12 14:22:17 +0530[diff] [blame]3063
3064&pm660_div_clk {
3065 status = "ok";
3066};
Tirupathi Reddy53b92a62017-10-26 13:57:42 +0530[diff] [blame]3067
3068&qupv3_se10_i2c {
3069 nx30p6093: nx30p6093@36 {
3070 status = "disabled";
3071 compatible = "nxp,nx30p6093";
3072 reg = <0x36>;
3073 interrupt-parent = <&tlmm>;
3074 interrupts = <5 IRQ_TYPE_NONE>;
3075 nxp,long-wakeup-sec = <28800>; /* 8 hours */
3076 nxp,short-wakeup-ms = <180000>; /* 3 mins */
3077 pinctrl-names = "default";
3078 pinctrl-0 = <&nx30p6093_intr_default>;
3079 };
3080};