blob: c8ca98c2b480a41d57676ef21e97cd6612134110 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06009#include <linux/pci_hotplug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include <linux/slab.h>
11#include <linux/module.h>
12#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080013#include <linux/pci-aspm.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060014#include <asm-generic/pci-bridge.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090015#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
17#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
Stephen Hemminger0b950f02014-01-10 17:14:48 -070020static struct resource busn_resource = {
Yinghai Lu67cdc822012-05-17 18:51:12 -070021 .name = "PCI busn",
22 .start = 0,
23 .end = 255,
24 .flags = IORESOURCE_BUS,
25};
26
Linus Torvalds1da177e2005-04-16 15:20:36 -070027/* Ugh. Need to stop exporting this to modules. */
28LIST_HEAD(pci_root_buses);
29EXPORT_SYMBOL(pci_root_buses);
30
Yinghai Lu5cc62c22012-05-17 18:51:11 -070031static LIST_HEAD(pci_domain_busn_res_list);
32
33struct pci_domain_busn_res {
34 struct list_head list;
35 struct resource res;
36 int domain_nr;
37};
38
39static struct resource *get_pci_domain_busn_res(int domain_nr)
40{
41 struct pci_domain_busn_res *r;
42
43 list_for_each_entry(r, &pci_domain_busn_res_list, list)
44 if (r->domain_nr == domain_nr)
45 return &r->res;
46
47 r = kzalloc(sizeof(*r), GFP_KERNEL);
48 if (!r)
49 return NULL;
50
51 r->domain_nr = domain_nr;
52 r->res.start = 0;
53 r->res.end = 0xff;
54 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
55
56 list_add_tail(&r->list, &pci_domain_busn_res_list);
57
58 return &r->res;
59}
60
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080061static int find_anything(struct device *dev, void *data)
62{
63 return 1;
64}
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070066/*
67 * Some device drivers need know if pci is initiated.
68 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080069 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070070 */
71int no_pci_devices(void)
72{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080073 struct device *dev;
74 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070075
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080076 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
77 no_devices = (dev == NULL);
78 put_device(dev);
79 return no_devices;
80}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070081EXPORT_SYMBOL(no_pci_devices);
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 * PCI Bus Class
85 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040086static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070087{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040088 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070089
90 if (pci_bus->bridge)
91 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070092 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100093 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 kfree(pci_bus);
95}
96
97static struct class pcibus_class = {
98 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040099 .dev_release = &release_pcibus_dev,
Greg Kroah-Hartman56039e62013-07-24 15:05:17 -0700100 .dev_groups = pcibus_groups,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101};
102
103static int __init pcibus_class_init(void)
104{
105 return class_register(&pcibus_class);
106}
107postcore_initcall(pcibus_class_init);
108
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400109static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800110{
111 u64 size = mask & maxbase; /* Find the significant bits */
112 if (!size)
113 return 0;
114
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size = (size & ~(size-1)) - 1;
118
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base == maxbase && ((base | size) & mask) != mask)
122 return 0;
123
124 return size;
125}
126
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600127static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800128{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600129 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600130 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600131
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400132 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600133 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
134 flags |= IORESOURCE_IO;
135 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400136 }
137
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600138 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
139 flags |= IORESOURCE_MEM;
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400142
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600143 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
144 switch (mem_type) {
145 case PCI_BASE_ADDRESS_MEM_TYPE_32:
146 break;
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600148 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600151 flags |= IORESOURCE_MEM_64;
152 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600153 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600154 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600155 break;
156 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600157 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400158}
159
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100160#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
161
Yu Zhao0b400c72008-11-22 02:40:40 +0800162/**
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
168 *
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400170 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800171int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400172 struct resource *res, unsigned int pos)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400173{
174 u32 l, sz, mask;
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600175 u64 l64, sz64, mask64;
Jacob Pan253d2e52010-07-16 10:19:22 -0700176 u16 orig_cmd;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800177 struct pci_bus_region region, inverted_region;
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600178 bool bar_too_big = false, bar_too_high = false, bar_invalid = false;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400179
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200180 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400181
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600182 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700183 if (!dev->mmio_always_on) {
184 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100185 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
186 pci_write_config_word(dev, PCI_COMMAND,
187 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
188 }
Jacob Pan253d2e52010-07-16 10:19:22 -0700189 }
190
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400191 res->name = pci_name(dev);
192
193 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200194 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400195 pci_read_config_dword(dev, pos, &sz);
196 pci_write_config_dword(dev, pos, l);
197
198 /*
199 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
202 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400203 */
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600204 if (!sz || sz == 0xffffffff)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400205 goto fail;
206
207 /*
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
210 */
211 if (l == 0xffffffff)
212 l = 0;
213
214 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600215 res->flags = decode_bar(dev, l);
216 res->flags |= IORESOURCE_SIZEALIGN;
217 if (res->flags & IORESOURCE_IO) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400218 l &= PCI_BASE_ADDRESS_IO_MASK;
David S. Miller5aceca92011-05-23 17:12:22 -0700219 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400220 } else {
221 l &= PCI_BASE_ADDRESS_MEM_MASK;
222 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
223 }
224 } else {
225 res->flags |= (l & IORESOURCE_ROM_ENABLE);
226 l &= PCI_ROM_ADDRESS_MASK;
227 mask = (u32)PCI_ROM_ADDRESS_MASK;
228 }
229
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600230 if (res->flags & IORESOURCE_MEM_64) {
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600231 l64 = l;
232 sz64 = sz;
233 mask64 = mask | (u64)~0 << 32;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400234
235 pci_read_config_dword(dev, pos + 4, &l);
236 pci_write_config_dword(dev, pos + 4, ~0);
237 pci_read_config_dword(dev, pos + 4, &sz);
238 pci_write_config_dword(dev, pos + 4, l);
239
240 l64 |= ((u64)l << 32);
241 sz64 |= ((u64)sz << 32);
242
243 sz64 = pci_size(l64, sz64, mask64);
244
245 if (!sz64)
246 goto fail;
247
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600248 if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
249 sz64 > 0x100000000ULL) {
250 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
251 res->start = 0;
252 res->end = 0;
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600253 bar_too_big = true;
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600254 goto out;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600255 }
256
Bjorn Helgaasd1a313e2014-04-29 18:33:09 -0600257 if ((sizeof(dma_addr_t) < 8) && l) {
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600258 /* Above 32-bit boundary; try to reallocate */
Bjorn Helgaasc83bd902014-02-26 11:26:00 -0700259 res->flags |= IORESOURCE_UNSET;
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600260 res->start = 0;
261 res->end = sz64;
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600262 bar_too_high = true;
Bjorn Helgaas72dc5602014-04-29 18:42:49 -0600263 goto out;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400264 } else {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700265 region.start = l64;
266 region.end = l64 + sz64;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400267 }
268 } else {
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600269 sz = pci_size(l, sz, mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400270
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600271 if (!sz)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400272 goto fail;
273
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700274 region.start = l;
275 region.end = l + sz;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400276 }
277
Yinghai Lufc279852013-12-09 22:54:40 -0800278 pcibios_bus_to_resource(dev->bus, res, &region);
279 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800280
281 /*
282 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
283 * the corresponding resource address (the physical address used by
284 * the CPU. Converting that resource address back to a bus address
285 * should yield the original BAR value:
286 *
287 * resource_to_bus(bus_to_resource(A)) == A
288 *
289 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
290 * be claimed by the device.
291 */
292 if (inverted_region.start != region.start) {
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800293 res->flags |= IORESOURCE_UNSET;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800294 res->start = 0;
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600295 res->end = region.end - region.start;
296 bar_invalid = true;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800297 }
Kevin Hao96ddef22013-05-25 19:36:26 +0800298
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600299 goto out;
300
301
302fail:
303 res->flags = 0;
304out:
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100305 if (!dev->mmio_always_on &&
306 (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
Bjorn Helgaasbbffe432012-07-06 12:08:18 -0600307 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
308
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600309 if (bar_too_big)
Bjorn Helgaas23b13bc2014-04-14 15:25:54 -0600310 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
311 pos, (unsigned long long) sz64);
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600312 if (bar_too_high)
313 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
314 pos, (unsigned long long) l64);
Bjorn Helgaas26370fc2014-04-14 15:26:50 -0600315 if (bar_invalid)
316 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
317 pos, (unsigned long long) region.start);
Bjorn Helgaas31e9dd22014-04-29 18:37:47 -0600318 if (res->flags)
Kevin Hao33963e302013-05-25 19:36:25 +0800319 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600320
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600321 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800322}
323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
325{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400326 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400328 for (pos = 0; pos < howmany; pos++) {
329 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400331 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400335 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400337 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
338 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
339 IORESOURCE_SIZEALIGN;
340 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 }
342}
343
Bill Pemberton15856ad2012-11-21 15:35:00 -0500344static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345{
346 struct pci_dev *dev = child->self;
347 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600348 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700349 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600350 struct resource *res;
351
352 io_mask = PCI_IO_RANGE_MASK;
353 io_granularity = 0x1000;
354 if (dev->io_window_1k) {
355 /* Support 1K I/O space granularity */
356 io_mask = PCI_IO_1K_RANGE_MASK;
357 io_granularity = 0x400;
358 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 res = child->resource[0];
361 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
362 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600363 base = (io_base_lo & io_mask) << 8;
364 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
366 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
367 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600368
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
370 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600371 base |= ((unsigned long) io_base_hi << 16);
372 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 }
374
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600375 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700377 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600378 region.end = limit + io_granularity - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800379 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600380 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700382}
383
Bill Pemberton15856ad2012-11-21 15:35:00 -0500384static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700385{
386 struct pci_dev *dev = child->self;
387 u16 mem_base_lo, mem_limit_lo;
388 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700389 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700390 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
392 res = child->resource[1];
393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600397 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700399 region.start = base;
400 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800401 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600402 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700404}
405
Bill Pemberton15856ad2012-11-21 15:35:00 -0500406static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700407{
408 struct pci_dev *dev = child->self;
409 u16 mem_base_lo, mem_limit_lo;
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700410 u64 base64, limit64;
411 dma_addr_t base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700412 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700413 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414
415 res = child->resource[2];
416 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
417 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700418 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
419 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
422 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600423
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
425 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
426
427 /*
428 * Some bridges set the base > limit by default, and some
429 * (broken) BIOSes do not initialize them. If we find
430 * this, just assume they are not being used.
431 */
432 if (mem_base_hi <= mem_limit_hi) {
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700433 base64 |= (u64) mem_base_hi << 32;
434 limit64 |= (u64) mem_limit_hi << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 }
436 }
Yinghai Lu7fc986d2014-11-19 14:30:32 -0700437
438 base = (dma_addr_t) base64;
439 limit = (dma_addr_t) limit64;
440
441 if (base != base64) {
442 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
443 (unsigned long long) base64);
444 return;
445 }
446
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600447 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700448 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
449 IORESOURCE_MEM | IORESOURCE_PREFETCH;
450 if (res->flags & PCI_PREF_RANGE_TYPE_64)
451 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700452 region.start = base;
453 region.end = limit + 0xfffff;
Yinghai Lufc279852013-12-09 22:54:40 -0800454 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600455 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 }
457}
458
Bill Pemberton15856ad2012-11-21 15:35:00 -0500459void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700460{
461 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700462 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700463 int i;
464
465 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
466 return;
467
Yinghai Lub918c622012-05-17 18:51:11 -0700468 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
469 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700470 dev->transparent ? " (subtractive decode)" : "");
471
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700472 pci_bus_remove_resources(child);
473 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
474 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
475
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700476 pci_read_bridge_io(child);
477 pci_read_bridge_mmio(child);
478 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700479
480 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700481 pci_bus_for_each_resource(child->parent, res, i) {
Bjorn Helgaasd739a092014-04-14 16:10:54 -0600482 if (res && res->flags) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700483 pci_bus_add_resource(child, res,
484 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700485 dev_printk(KERN_DEBUG, &dev->dev,
486 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700487 res);
488 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700489 }
490 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700491}
492
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100493static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494{
495 struct pci_bus *b;
496
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100497 b = kzalloc(sizeof(*b), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600498 if (!b)
499 return NULL;
500
501 INIT_LIST_HEAD(&b->node);
502 INIT_LIST_HEAD(&b->children);
503 INIT_LIST_HEAD(&b->devices);
504 INIT_LIST_HEAD(&b->slots);
505 INIT_LIST_HEAD(&b->resources);
506 b->max_bus_speed = PCI_SPEED_UNKNOWN;
507 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100508#ifdef CONFIG_PCI_DOMAINS_GENERIC
509 if (parent)
510 b->domain_nr = parent->domain_nr;
511#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512 return b;
513}
514
Jiang Liu70efde22013-06-07 16:16:51 -0600515static void pci_release_host_bridge_dev(struct device *dev)
516{
517 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
518
519 if (bridge->release_fn)
520 bridge->release_fn(bridge);
521
522 pci_free_resource_list(&bridge->windows);
523
524 kfree(bridge);
525}
526
Yinghai Lu7b543662012-04-02 18:31:53 -0700527static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
528{
529 struct pci_host_bridge *bridge;
530
531 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600532 if (!bridge)
533 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -0700534
Bjorn Helgaas05013482013-06-05 14:22:11 -0600535 INIT_LIST_HEAD(&bridge->windows);
536 bridge->bus = b;
Yinghai Lu7b543662012-04-02 18:31:53 -0700537 return bridge;
538}
539
Stephen Hemminger0b950f02014-01-10 17:14:48 -0700540static const unsigned char pcix_bus_speed[] = {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500541 PCI_SPEED_UNKNOWN, /* 0 */
542 PCI_SPEED_66MHz_PCIX, /* 1 */
543 PCI_SPEED_100MHz_PCIX, /* 2 */
544 PCI_SPEED_133MHz_PCIX, /* 3 */
545 PCI_SPEED_UNKNOWN, /* 4 */
546 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
547 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
548 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
549 PCI_SPEED_UNKNOWN, /* 8 */
550 PCI_SPEED_66MHz_PCIX_266, /* 9 */
551 PCI_SPEED_100MHz_PCIX_266, /* A */
552 PCI_SPEED_133MHz_PCIX_266, /* B */
553 PCI_SPEED_UNKNOWN, /* C */
554 PCI_SPEED_66MHz_PCIX_533, /* D */
555 PCI_SPEED_100MHz_PCIX_533, /* E */
556 PCI_SPEED_133MHz_PCIX_533 /* F */
557};
558
Jacob Keller343e51a2013-07-31 06:53:16 +0000559const unsigned char pcie_link_speed[] = {
Matthew Wilcox3749c512009-12-13 08:11:32 -0500560 PCI_SPEED_UNKNOWN, /* 0 */
561 PCIE_SPEED_2_5GT, /* 1 */
562 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500563 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500564 PCI_SPEED_UNKNOWN, /* 4 */
565 PCI_SPEED_UNKNOWN, /* 5 */
566 PCI_SPEED_UNKNOWN, /* 6 */
567 PCI_SPEED_UNKNOWN, /* 7 */
568 PCI_SPEED_UNKNOWN, /* 8 */
569 PCI_SPEED_UNKNOWN, /* 9 */
570 PCI_SPEED_UNKNOWN, /* A */
571 PCI_SPEED_UNKNOWN, /* B */
572 PCI_SPEED_UNKNOWN, /* C */
573 PCI_SPEED_UNKNOWN, /* D */
574 PCI_SPEED_UNKNOWN, /* E */
575 PCI_SPEED_UNKNOWN /* F */
576};
577
578void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
579{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700580 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500581}
582EXPORT_SYMBOL_GPL(pcie_update_link_speed);
583
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500584static unsigned char agp_speeds[] = {
585 AGP_UNKNOWN,
586 AGP_1X,
587 AGP_2X,
588 AGP_4X,
589 AGP_8X
590};
591
592static enum pci_bus_speed agp_speed(int agp3, int agpstat)
593{
594 int index = 0;
595
596 if (agpstat & 4)
597 index = 3;
598 else if (agpstat & 2)
599 index = 2;
600 else if (agpstat & 1)
601 index = 1;
602 else
603 goto out;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700604
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500605 if (agp3) {
606 index += 2;
607 if (index == 5)
608 index = 0;
609 }
610
611 out:
612 return agp_speeds[index];
613}
614
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500615static void pci_set_bus_speed(struct pci_bus *bus)
616{
617 struct pci_dev *bridge = bus->self;
618 int pos;
619
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500620 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
621 if (!pos)
622 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
623 if (pos) {
624 u32 agpstat, agpcmd;
625
626 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
627 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
628
629 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
630 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
631 }
632
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500633 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
634 if (pos) {
635 u16 status;
636 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500637
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700638 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
639 &status);
640
641 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500642 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700643 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500644 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700645 } else if (status & PCI_X_SSTATUS_133MHZ) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400646 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500647 max = PCI_SPEED_133MHz_PCIX_ECC;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400648 else
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500649 max = PCI_SPEED_133MHz_PCIX;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500650 } else {
651 max = PCI_SPEED_66MHz_PCIX;
652 }
653
654 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700655 bus->cur_bus_speed = pcix_bus_speed[
656 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500657
658 return;
659 }
660
Yijing Wangfdfe1512013-09-05 15:55:29 +0800661 if (pci_is_pcie(bridge)) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500662 u32 linkcap;
663 u16 linksta;
664
Jiang Liu59875ae2012-07-24 17:20:06 +0800665 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700666 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500667
Jiang Liu59875ae2012-07-24 17:20:06 +0800668 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500669 pcie_update_link_speed(bus, linksta);
670 }
671}
672
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700673static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
674 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675{
676 struct pci_bus *child;
677 int i;
Yinghai Lu4f535092013-01-21 13:20:52 -0800678 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
680 /*
681 * Allocate a new bus, and inherit stuff from the parent..
682 */
Catalin Marinas670ba0c2014-09-29 15:29:26 +0100683 child = pci_alloc_bus(parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 if (!child)
685 return NULL;
686
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 child->parent = parent;
688 child->ops = parent->ops;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200689 child->msi = parent->msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200691 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400693 /* initialize some portions of the bus device, but don't register it
Yinghai Lu4f535092013-01-21 13:20:52 -0800694 * now as the parent is not properly set up yet.
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400695 */
696 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100697 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698
699 /*
700 * Set up the primary, secondary and subordinate
701 * bus numbers.
702 */
Yinghai Lub918c622012-05-17 18:51:11 -0700703 child->number = child->busn_res.start = busnr;
704 child->primary = parent->busn_res.start;
705 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706
Yinghai Lu4f535092013-01-21 13:20:52 -0800707 if (!bridge) {
708 child->dev.parent = parent->bridge;
709 goto add_dev;
710 }
Yu Zhao3789fa82008-11-22 02:41:07 +0800711
712 child->self = bridge;
713 child->bridge = get_device(&bridge->dev);
Yinghai Lu4f535092013-01-21 13:20:52 -0800714 child->dev.parent = child->bridge;
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000715 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500716 pci_set_bus_speed(child);
717
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800719 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
721 child->resource[i]->name = child->name;
722 }
723 bridge->subordinate = child;
724
Yinghai Lu4f535092013-01-21 13:20:52 -0800725add_dev:
726 ret = device_register(&child->dev);
727 WARN_ON(ret < 0);
728
Jiang Liu10a95742013-04-12 05:44:20 +0000729 pcibios_add_bus(child);
730
Yinghai Lu4f535092013-01-21 13:20:52 -0800731 /* Create legacy_io and legacy_mem files for this bus */
732 pci_create_legacy_files(child);
733
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 return child;
735}
736
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400737struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
738 int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739{
740 struct pci_bus *child;
741
742 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700743 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800744 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800746 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700747 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 return child;
749}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600750EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
Rajat Jainf3dbd802014-09-02 16:26:00 -0700752static void pci_enable_crs(struct pci_dev *pdev)
753{
754 u16 root_cap = 0;
755
756 /* Enable CRS Software Visibility if supported */
757 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
758 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
759 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
760 PCI_EXP_RTCTL_CRSSVE);
761}
762
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763/*
764 * If it's a bridge, configure it and scan the bus behind it.
765 * For CardBus bridges, we don't scan behind as the devices will
766 * be handled by the bridge driver itself.
767 *
768 * We need to process bridges in two passes -- first we scan those
769 * already configured by the BIOS and after we are done with all of
770 * them, we proceed to assigning numbers to the remaining buses in
771 * order to avoid overlaps between old and new bus numbers.
772 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500773int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774{
775 struct pci_bus *child;
776 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100777 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600779 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100780 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
782 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600783 primary = buses & 0xFF;
784 secondary = (buses >> 8) & 0xFF;
785 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600787 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
788 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100790 if (!primary && (primary != bus->number) && secondary && subordinate) {
791 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
792 primary = bus->number;
793 }
794
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100795 /* Check if setup is sensible at all */
796 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -0700797 (primary != bus->number || secondary <= bus->number ||
Bjorn Helgaas12d87062014-09-19 11:08:40 -0600798 secondary > subordinate)) {
Yinghai Lu1965f662012-09-10 17:19:33 -0700799 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
800 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100801 broken = 1;
802 }
803
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 /* Disable MasterAbortMode during probing to avoid reporting
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700805 of bus errors (in some architectures) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
807 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
808 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
809
Rajat Jainf3dbd802014-09-02 16:26:00 -0700810 pci_enable_crs(dev);
811
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600812 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
813 !is_cardbus && !broken) {
814 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 /*
816 * Bus already configured by firmware, process it in the first
817 * pass and just note the configuration.
818 */
819 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000820 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821
822 /*
Andreas Noever2ed85822014-01-23 21:59:22 +0100823 * The bus might already exist for two reasons: Either we are
824 * rescanning the bus or the bus is reachable through more than
825 * one bridge. The second case can happen with the i450NX
826 * chipset.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600828 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600829 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600830 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600831 if (!child)
832 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600833 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -0700834 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -0600835 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 }
837
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 cmax = pci_scan_child_bus(child);
Andreas Noeverc95b0bd2014-01-23 21:59:27 +0100839 if (cmax > subordinate)
840 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
841 subordinate, cmax);
842 /* subordinate should equal child->busn_res.end */
843 if (subordinate > max)
844 max = subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 } else {
846 /*
847 * We need to assign a number to this bus which we always
848 * do in the second pass.
849 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700850 if (!pass) {
Andreas Noever619c8c32014-01-23 21:59:23 +0100851 if (pcibios_assign_all_busses() || broken || is_cardbus)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700852 /* Temporarily disable forwarding of the
853 configuration cycles on all bridges in
854 this bus segment to avoid possible
855 conflicts in the second pass between two
856 bridges programmed with overlapping
857 bus ranges. */
858 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
859 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000860 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700861 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862
863 /* Clear errors */
864 pci_write_config_word(dev, PCI_STATUS, 0xffff);
865
Bjorn Helgaas7a0b33d2014-09-19 10:56:06 -0600866 /* Prevent assigning a bus number that already exists.
867 * This can happen when a bridge is hot-plugged, so in
868 * this case we only re-scan this bus. */
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800869 child = pci_find_bus(pci_domain_nr(bus), max+1);
870 if (!child) {
Andreas Noever9a4d7d82014-01-23 21:59:21 +0100871 child = pci_add_new_bus(bus, dev, max+1);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800872 if (!child)
873 goto out;
Bjorn Helgaas12d87062014-09-19 11:08:40 -0600874 pci_bus_insert_busn_res(child, max+1, 0xff);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800875 }
Andreas Noever9a4d7d82014-01-23 21:59:21 +0100876 max++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 buses = (buses & 0xff000000)
878 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -0700879 | ((unsigned int)(child->busn_res.start) << 8)
880 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881
882 /*
883 * yenta.c forces a secondary latency timer of 176.
884 * Copy that behaviour here.
885 */
886 if (is_cardbus) {
887 buses &= ~0xff000000;
888 buses |= CARDBUS_LATENCY_TIMER << 24;
889 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100890
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891 /*
892 * We need to blast all three values with a single write.
893 */
894 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
895
896 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700897 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 max = pci_scan_child_bus(child);
899 } else {
900 /*
901 * For CardBus bridges, we leave 4 bus numbers
902 * as cards with a PCI-to-PCI bridge can be
903 * inserted later.
904 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400905 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100906 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700907 if (pci_find_bus(pci_domain_nr(bus),
908 max+i+1))
909 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100910 while (parent->parent) {
911 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -0700912 (parent->busn_res.end > max) &&
913 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100914 j = 1;
915 }
916 parent = parent->parent;
917 }
918 if (j) {
919 /*
920 * Often, there are two cardbus bridges
921 * -- try to leave one valid bus number
922 * for each one.
923 */
924 i /= 2;
925 break;
926 }
927 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700928 max += i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929 }
930 /*
931 * Set the subordinate bus number to its real value.
932 */
Yinghai Lubc76b732012-05-17 18:51:13 -0700933 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
935 }
936
Gary Hadecb3576f2008-02-08 14:00:52 -0800937 sprintf(child->name,
938 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
939 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200941 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100942 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -0700943 if ((child->busn_res.end > bus->busn_res.end) ||
944 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +0100945 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -0700946 (child->busn_res.end < bus->number)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400947 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
Yinghai Lub918c622012-05-17 18:51:11 -0700948 &child->busn_res,
949 (bus->number > child->busn_res.end &&
950 bus->busn_res.end < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800951 "wholly" : "partially",
952 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700953 dev_name(&bus->dev),
Yinghai Lub918c622012-05-17 18:51:11 -0700954 &bus->busn_res);
Dominik Brodowski49887942005-12-08 16:53:12 +0100955 }
956 bus = bus->parent;
957 }
958
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000959out:
960 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
961
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962 return max;
963}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600964EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965
966/*
967 * Read interrupt line and base address registers.
968 * The architecture-dependent code can tweak these, of course.
969 */
970static void pci_read_irq(struct pci_dev *dev)
971{
972 unsigned char irq;
973
974 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800975 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 if (irq)
977 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
978 dev->irq = irq;
979}
980
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000981void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +0800982{
983 int pos;
984 u16 reg16;
985
986 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
987 if (!pos)
988 return;
Kenji Kaneshige0efea002009-11-05 12:05:11 +0900989 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +0800990 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +0800991 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -0500992 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
993 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yu Zhao480b93b2009-03-20 11:25:14 +0800994}
995
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000996void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -0700997{
Eric W. Biederman28760482009-09-09 14:09:24 -0700998 u32 reg32;
999
Jiang Liu59875ae2012-07-24 17:20:06 +08001000 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -07001001 if (reg32 & PCI_EXP_SLTCAP_HPC)
1002 pdev->is_hotplug_bridge = 1;
1003}
1004
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001005/**
Alex Williamson78916b02014-05-05 14:20:51 -06001006 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1007 * @dev: PCI device
1008 *
1009 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1010 * when forwarding a type1 configuration request the bridge must check that
1011 * the extended register address field is zero. The bridge is not permitted
1012 * to forward the transactions and must handle it as an Unsupported Request.
1013 * Some bridges do not follow this rule and simply drop the extended register
1014 * bits, resulting in the standard config space being aliased, every 256
1015 * bytes across the entire configuration space. Test for this condition by
1016 * comparing the first dword of each potential alias to the vendor/device ID.
1017 * Known offenders:
1018 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1019 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1020 */
1021static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1022{
1023#ifdef CONFIG_PCI_QUIRKS
1024 int pos;
1025 u32 header, tmp;
1026
1027 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1028
1029 for (pos = PCI_CFG_SPACE_SIZE;
1030 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1031 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1032 || header != tmp)
1033 return false;
1034 }
1035
1036 return true;
1037#else
1038 return false;
1039#endif
1040}
1041
1042/**
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001043 * pci_cfg_space_size - get the configuration space size of the PCI device.
1044 * @dev: PCI device
1045 *
1046 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1047 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1048 * access it. Maybe we don't have a way to generate extended config space
1049 * accesses, or the device is behind a reverse Express bridge. So we try
1050 * reading the dword at 0x100 which must either be 0 or a valid extended
1051 * capability header.
1052 */
1053static int pci_cfg_space_size_ext(struct pci_dev *dev)
1054{
1055 u32 status;
1056 int pos = PCI_CFG_SPACE_SIZE;
1057
1058 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1059 goto fail;
Alex Williamson78916b02014-05-05 14:20:51 -06001060 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001061 goto fail;
1062
1063 return PCI_CFG_SPACE_EXP_SIZE;
1064
1065 fail:
1066 return PCI_CFG_SPACE_SIZE;
1067}
1068
1069int pci_cfg_space_size(struct pci_dev *dev)
1070{
1071 int pos;
1072 u32 status;
1073 u16 class;
1074
1075 class = dev->class >> 8;
1076 if (class == PCI_CLASS_BRIDGE_HOST)
1077 return pci_cfg_space_size_ext(dev);
1078
1079 if (!pci_is_pcie(dev)) {
1080 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1081 if (!pos)
1082 goto fail;
1083
1084 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1085 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1086 goto fail;
1087 }
1088
1089 return pci_cfg_space_size_ext(dev);
1090
1091 fail:
1092 return PCI_CFG_SPACE_SIZE;
1093}
1094
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +02001095#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -08001096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097/**
1098 * pci_setup_device - fill in class and map information of a device
1099 * @dev: the device structure to fill
1100 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001101 * Initialize the device structure with information about the device's
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1103 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +08001104 * Returns 0 on success and negative if unknown type of device (not normal,
1105 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001107int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108{
1109 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +08001110 u8 hdr_type;
1111 struct pci_slot *slot;
Gabe Blackbc577d22009-10-06 10:45:19 -05001112 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001113 struct pci_bus_region region;
1114 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +08001115
1116 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1117 return -EIO;
1118
1119 dev->sysdata = dev->bus->sysdata;
1120 dev->dev.parent = dev->bus->bridge;
1121 dev->dev.bus = &pci_bus_type;
1122 dev->hdr_type = hdr_type & 0x7f;
1123 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +08001124 dev->error_state = pci_channel_io_normal;
1125 set_pcie_port_type(dev);
1126
1127 list_for_each_entry(slot, &dev->bus->slots, list)
1128 if (PCI_SLOT(dev->devfn) == slot->number)
1129 dev->slot = slot;
1130
1131 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1132 set this higher, assuming the system even supports it. */
1133 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -07001135 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1136 dev->bus->number, PCI_SLOT(dev->devfn),
1137 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138
1139 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -07001140 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001141 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001143 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1144 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145
Yu Zhao853346e2009-03-21 22:05:11 +08001146 /* need to have dev->class ready */
1147 dev->cfg_size = pci_cfg_space_size(dev);
1148
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001150 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
1152 /* Early fixups, before probing the BARs */
1153 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +08001154 /* device class may be changed after fixup */
1155 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156
1157 switch (dev->hdr_type) { /* header type */
1158 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1159 if (class == PCI_CLASS_BRIDGE_PCI)
1160 goto bad;
1161 pci_read_irq(dev);
1162 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1163 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1164 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001165
1166 /*
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001167 * Do the ugly legacy mode stuff here rather than broken chip
1168 * quirk code. Legacy mode ATA controllers have fixed
1169 * addresses. These are not always echoed in BAR0-3, and
1170 * BAR0-3 in a few cases contain junk!
Alan Cox368c73d2006-10-04 00:41:26 +01001171 */
1172 if (class == PCI_CLASS_STORAGE_IDE) {
1173 u8 progif;
1174 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1175 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001176 region.start = 0x1F0;
1177 region.end = 0x1F7;
1178 res = &dev->resource[0];
1179 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001180 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001181 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1182 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001183 region.start = 0x3F6;
1184 region.end = 0x3F6;
1185 res = &dev->resource[1];
1186 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001187 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001188 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1189 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001190 }
1191 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001192 region.start = 0x170;
1193 region.end = 0x177;
1194 res = &dev->resource[2];
1195 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001196 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001197 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1198 res);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001199 region.start = 0x376;
1200 region.end = 0x376;
1201 res = &dev->resource[3];
1202 res->flags = LEGACY_IO_RESOURCE;
Yinghai Lufc279852013-12-09 22:54:40 -08001203 pcibios_bus_to_resource(dev->bus, res, &region);
Bjorn Helgaas075eb9e2014-03-05 14:07:03 -07001204 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1205 res);
Alan Cox368c73d2006-10-04 00:41:26 +01001206 }
1207 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 break;
1209
1210 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1211 if (class != PCI_CLASS_BRIDGE_PCI)
1212 goto bad;
1213 /* The PCI-to-PCI bridge spec requires that subtractive
1214 decoding (i.e. transparent) bridge must have programming
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001215 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001216 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 dev->transparent = ((dev->class & 0xff) == 1);
1218 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001219 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001220 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1221 if (pos) {
1222 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1223 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1224 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 break;
1226
1227 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1228 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1229 goto bad;
1230 pci_read_irq(dev);
1231 pci_read_bases(dev, 1, 0);
1232 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1233 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1234 break;
1235
1236 default: /* unknown header */
Ryan Desfosses227f0642014-04-18 20:13:50 -04001237 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1238 dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001239 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240
1241 bad:
Ryan Desfosses227f0642014-04-18 20:13:50 -04001242 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1243 dev->class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 dev->class = PCI_CLASS_NOT_DEFINED;
1245 }
1246
1247 /* We found a fine healthy device, go go go... */
1248 return 0;
1249}
1250
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001251static struct hpp_type0 pci_default_type0 = {
1252 .revision = 1,
1253 .cache_line_size = 8,
1254 .latency_timer = 0x40,
1255 .enable_serr = 0,
1256 .enable_perr = 0,
1257};
1258
1259static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1260{
1261 u16 pci_cmd, pci_bctl;
1262
Bjorn Helgaasc6285fc2014-08-29 18:10:19 -06001263 if (!hpp)
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001264 hpp = &pci_default_type0;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001265
1266 if (hpp->revision > 1) {
1267 dev_warn(&dev->dev,
1268 "PCI settings rev %d not supported; using defaults\n",
1269 hpp->revision);
1270 hpp = &pci_default_type0;
1271 }
1272
1273 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1274 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1275 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1276 if (hpp->enable_serr)
1277 pci_cmd |= PCI_COMMAND_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001278 if (hpp->enable_perr)
1279 pci_cmd |= PCI_COMMAND_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001280 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1281
1282 /* Program bridge control value */
1283 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1284 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1285 hpp->latency_timer);
1286 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1287 if (hpp->enable_serr)
1288 pci_bctl |= PCI_BRIDGE_CTL_SERR;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001289 if (hpp->enable_perr)
1290 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001291 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1292 }
1293}
1294
1295static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1296{
1297 if (hpp)
1298 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1299}
1300
1301static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1302{
1303 int pos;
1304 u32 reg32;
1305
1306 if (!hpp)
1307 return;
1308
1309 if (hpp->revision > 1) {
1310 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1311 hpp->revision);
1312 return;
1313 }
1314
Bjorn Helgaas302328c2014-09-03 13:26:29 -06001315 /*
1316 * Don't allow _HPX to change MPS or MRRS settings. We manage
1317 * those to make sure they're consistent with the rest of the
1318 * platform.
1319 */
1320 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1321 PCI_EXP_DEVCTL_READRQ;
1322 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1323 PCI_EXP_DEVCTL_READRQ);
1324
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001325 /* Initialize Device Control Register */
1326 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1327 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1328
1329 /* Initialize Link Control Register */
Yinghai Lu7a1562d2014-11-11 12:09:46 -08001330 if (pcie_cap_has_lnkctl(dev))
Bjorn Helgaas589fcc22014-09-12 20:02:00 -06001331 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1332 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1333
1334 /* Find Advanced Error Reporting Enhanced Capability */
1335 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1336 if (!pos)
1337 return;
1338
1339 /* Initialize Uncorrectable Error Mask Register */
1340 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1341 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1342 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1343
1344 /* Initialize Uncorrectable Error Severity Register */
1345 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1346 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1347 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1348
1349 /* Initialize Correctable Error Mask Register */
1350 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1351 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1352 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1353
1354 /* Initialize Advanced Error Capabilities and Control Register */
1355 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1356 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1357 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1358
1359 /*
1360 * FIXME: The following two registers are not supported yet.
1361 *
1362 * o Secondary Uncorrectable Error Severity Register
1363 * o Secondary Uncorrectable Error Mask Register
1364 */
1365}
1366
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001367static void pci_configure_device(struct pci_dev *dev)
1368{
1369 struct hotplug_params hpp;
1370 int ret;
1371
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001372 memset(&hpp, 0, sizeof(hpp));
1373 ret = pci_get_hp_params(dev, &hpp);
1374 if (ret)
1375 return;
1376
1377 program_hpp_type2(dev, hpp.t2);
1378 program_hpp_type1(dev, hpp.t1);
1379 program_hpp_type0(dev, hpp.t0);
1380}
1381
Zhao, Yu201de562008-10-13 19:49:55 +08001382static void pci_release_capabilities(struct pci_dev *dev)
1383{
1384 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001385 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001386 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001387}
1388
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389/**
1390 * pci_release_dev - free a pci device structure when all users of it are finished.
1391 * @dev: device that's been disconnected
1392 *
1393 * Will be called only by the device core when all users of this pci device are
1394 * done.
1395 */
1396static void pci_release_dev(struct device *dev)
1397{
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001398 struct pci_dev *pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399
Rafael J. Wysocki04480092014-02-01 15:38:29 +01001400 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001401 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001402 pci_release_of_node(pci_dev);
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001403 pcibios_release_device(pci_dev);
Gu Zheng8b1fce02013-05-25 21:48:31 +08001404 pci_bus_put(pci_dev->bus);
Alex Williamson782a9852014-05-20 08:53:21 -06001405 kfree(pci_dev->driver_override);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406 kfree(pci_dev);
1407}
1408
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001409struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
Michael Ellerman65891212007-04-05 17:19:08 +10001410{
1411 struct pci_dev *dev;
1412
1413 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1414 if (!dev)
1415 return NULL;
1416
Michael Ellerman65891212007-04-05 17:19:08 +10001417 INIT_LIST_HEAD(&dev->bus_list);
Brian King88e7b162013-04-08 03:05:07 +00001418 dev->dev.type = &pci_dev_type;
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001419 dev->bus = pci_bus_get(bus);
Michael Ellerman65891212007-04-05 17:19:08 +10001420
1421 return dev;
1422}
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001423EXPORT_SYMBOL(pci_alloc_dev);
1424
Yinghai Luefdc87d2012-01-27 10:55:10 -08001425bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001426 int crs_timeout)
Yinghai Luefdc87d2012-01-27 10:55:10 -08001427{
1428 int delay = 1;
1429
1430 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1431 return false;
1432
1433 /* some broken boards return 0 or ~0 if a slot is empty: */
1434 if (*l == 0xffffffff || *l == 0x00000000 ||
1435 *l == 0x0000ffff || *l == 0xffff0000)
1436 return false;
1437
Rajat Jain89665a62014-09-08 14:19:49 -07001438 /*
1439 * Configuration Request Retry Status. Some root ports return the
1440 * actual device ID instead of the synthetic ID (0xFFFF) required
1441 * by the PCIe spec. Ignore the device ID and only check for
1442 * (vendor id == 1).
1443 */
1444 while ((*l & 0xffff) == 0x0001) {
Yinghai Luefdc87d2012-01-27 10:55:10 -08001445 if (!crs_timeout)
1446 return false;
1447
1448 msleep(delay);
1449 delay *= 2;
1450 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1451 return false;
1452 /* Card hasn't responded in 60 seconds? Must be stuck. */
1453 if (delay > crs_timeout) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001454 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1455 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1456 PCI_FUNC(devfn));
Yinghai Luefdc87d2012-01-27 10:55:10 -08001457 return false;
1458 }
1459 }
1460
1461 return true;
1462}
1463EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1464
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465/*
1466 * Read the config data for a PCI device, sanity-check it
1467 * and fill in the dev structure...
1468 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001469static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470{
1471 struct pci_dev *dev;
1472 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473
Yinghai Luefdc87d2012-01-27 10:55:10 -08001474 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475 return NULL;
1476
Gu Zheng8b1fce02013-05-25 21:48:31 +08001477 dev = pci_alloc_dev(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 if (!dev)
1479 return NULL;
1480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 dev->vendor = l & 0xffff;
1483 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001485 pci_set_of_node(dev);
1486
Yu Zhao480b93b2009-03-20 11:25:14 +08001487 if (pci_setup_device(dev)) {
Gu Zheng8b1fce02013-05-25 21:48:31 +08001488 pci_bus_put(dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489 kfree(dev);
1490 return NULL;
1491 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001492
1493 return dev;
1494}
1495
Zhao, Yu201de562008-10-13 19:49:55 +08001496static void pci_init_capabilities(struct pci_dev *dev)
1497{
1498 /* MSI/MSI-X list */
1499 pci_msi_init_pci_dev(dev);
1500
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001501 /* Buffers for saving PCIe and PCI-X capabilities */
1502 pci_allocate_cap_save_buffers(dev);
1503
Zhao, Yu201de562008-10-13 19:49:55 +08001504 /* Power Management */
1505 pci_pm_init(dev);
1506
1507 /* Vital Product Data */
1508 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001509
1510 /* Alternative Routing-ID Forwarding */
Yijing Wang31ab2472013-01-15 11:12:17 +08001511 pci_configure_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001512
1513 /* Single Root I/O Virtualization */
1514 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001515
1516 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001517 pci_enable_acs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001518}
1519
Sam Ravnborg96bde062007-03-26 21:53:30 -08001520void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001521{
Yinghai Lu4f535092013-01-21 13:20:52 -08001522 int ret;
1523
Bjorn Helgaas6cd33642014-08-27 14:29:47 -06001524 pci_configure_device(dev);
1525
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 device_initialize(&dev->dev);
1527 dev->dev.release = pci_release_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528
Yinghai Lu7629d192013-01-21 13:20:44 -08001529 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001531 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 dev->dev.coherent_dma_mask = 0xffffffffull;
1533
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001534 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001535 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001536
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 /* Fix up broken headers */
1538 pci_fixup_device(pci_fixup_header, dev);
1539
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001540 /* moved out from quirk header fixup code */
1541 pci_reassigndev_resource_alignment(dev);
1542
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001543 /* Clear the state_saved flag. */
1544 dev->state_saved = false;
1545
Zhao, Yu201de562008-10-13 19:49:55 +08001546 /* Initialize various capabilities */
1547 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001548
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 /*
1550 * Add the device to our list of discovered devices
1551 * and the bus list for fixup functions, etc.
1552 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001553 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001555 up_write(&pci_bus_sem);
Yinghai Lu4f535092013-01-21 13:20:52 -08001556
Yinghai Lu4f535092013-01-21 13:20:52 -08001557 ret = pcibios_add_device(dev);
1558 WARN_ON(ret < 0);
1559
1560 /* Notifier could use PCI capabilities */
1561 dev->match_driver = false;
1562 ret = device_add(&dev->dev);
1563 WARN_ON(ret < 0);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001564}
1565
Bjorn Helgaas10874f52014-04-14 16:11:40 -06001566struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001567{
1568 struct pci_dev *dev;
1569
Trent Piepho90bdb312009-03-20 14:56:00 -06001570 dev = pci_get_slot(bus, devfn);
1571 if (dev) {
1572 pci_dev_put(dev);
1573 return dev;
1574 }
1575
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001576 dev = pci_scan_device(bus, devfn);
1577 if (!dev)
1578 return NULL;
1579
1580 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581
1582 return dev;
1583}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001584EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001586static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001587{
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001588 int pos;
1589 u16 cap = 0;
1590 unsigned next_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001591
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001592 if (pci_ari_enabled(bus)) {
1593 if (!dev)
1594 return 0;
1595 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1596 if (!pos)
1597 return 0;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001598
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001599 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1600 next_fn = PCI_ARI_CAP_NFN(cap);
1601 if (next_fn <= fn)
1602 return 0; /* protect against malformed list */
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001603
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001604 return next_fn;
1605 }
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001606
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001607 /* dev may be NULL for non-contiguous multifunction devices */
1608 if (!dev || dev->multifunction)
1609 return (fn + 1) % 8;
1610
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001611 return 0;
1612}
1613
1614static int only_one_child(struct pci_bus *bus)
1615{
1616 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001617
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001618 if (!parent || !pci_is_pcie(parent))
1619 return 0;
Yijing Wang62f87c02012-07-24 17:20:03 +08001620 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001621 return 1;
Yijing Wang62f87c02012-07-24 17:20:03 +08001622 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001623 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001624 return 1;
1625 return 0;
1626}
1627
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628/**
1629 * pci_scan_slot - scan a PCI slot on a bus for devices.
1630 * @bus: PCI bus to scan
1631 * @devfn: slot number to scan (must have zero function.)
1632 *
1633 * Scan a PCI slot on the specified PCI bus for devices, adding
1634 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001635 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001636 *
1637 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001639int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001641 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001642 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001643
1644 if (only_one_child(bus) && (devfn > 0))
1645 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001647 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001648 if (!dev)
1649 return 0;
1650 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001651 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001653 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001654 dev = pci_scan_single_device(bus, devfn + fn);
1655 if (dev) {
1656 if (!dev->is_added)
1657 nr++;
1658 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 }
1660 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001661
Shaohua Li149e1632008-07-23 10:32:31 +08001662 /* only one slot has pcie device */
1663 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001664 pcie_aspm_init_link_state(bus->self);
1665
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666 return nr;
1667}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001668EXPORT_SYMBOL(pci_scan_slot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669
Jon Masonb03e7492011-07-20 15:20:54 -05001670static int pcie_find_smpss(struct pci_dev *dev, void *data)
1671{
1672 u8 *smpss = data;
1673
1674 if (!pci_is_pcie(dev))
1675 return 0;
1676
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001677 /*
1678 * We don't have a way to change MPS settings on devices that have
1679 * drivers attached. A hot-added device might support only the minimum
1680 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1681 * where devices may be hot-added, we limit the fabric MPS to 128 so
1682 * hot-added devices will work correctly.
1683 *
1684 * However, if we hot-add a device to a slot directly below a Root
1685 * Port, it's impossible for there to be other existing devices below
1686 * the port. We don't limit the MPS in this case because we can
1687 * reconfigure MPS on both the Root Port and the hot-added device,
1688 * and there are no other devices involved.
1689 *
1690 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
Jon Masonb03e7492011-07-20 15:20:54 -05001691 */
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001692 if (dev->is_hotplug_bridge &&
1693 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
Jon Masonb03e7492011-07-20 15:20:54 -05001694 *smpss = 0;
1695
1696 if (*smpss > dev->pcie_mpss)
1697 *smpss = dev->pcie_mpss;
1698
1699 return 0;
1700}
1701
1702static void pcie_write_mps(struct pci_dev *dev, int mps)
1703{
Jon Mason62f392e2011-10-14 14:56:14 -05001704 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001705
1706 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001707 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001708
Yijing Wang62f87c02012-07-24 17:20:03 +08001709 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1710 dev->bus->self)
Jon Mason62f392e2011-10-14 14:56:14 -05001711 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001712 * downstream communication will never be larger than
1713 * the MRRS. So, the MPS only needs to be configured
1714 * for the upstream communication. This being the case,
1715 * walk from the top down and set the MPS of the child
1716 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001717 *
1718 * Configure the device MPS with the smaller of the
1719 * device MPSS or the bridge MPS (which is assumed to be
1720 * properly configured at this point to the largest
1721 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001722 */
Jon Mason62f392e2011-10-14 14:56:14 -05001723 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001724 }
1725
1726 rc = pcie_set_mps(dev, mps);
1727 if (rc)
1728 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1729}
1730
Jon Mason62f392e2011-10-14 14:56:14 -05001731static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001732{
Jon Mason62f392e2011-10-14 14:56:14 -05001733 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001734
Jon Masoned2888e2011-09-08 16:41:18 -05001735 /* In the "safe" case, do not configure the MRRS. There appear to be
1736 * issues with setting MRRS to 0 on a number of devices.
1737 */
Jon Masoned2888e2011-09-08 16:41:18 -05001738 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1739 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001740
Jon Masoned2888e2011-09-08 16:41:18 -05001741 /* For Max performance, the MRRS must be set to the largest supported
1742 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001743 * device or the bus can support. This should already be properly
1744 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001745 */
Jon Mason62f392e2011-10-14 14:56:14 -05001746 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001747
1748 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001749 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001750 * If the MRRS value provided is not acceptable (e.g., too large),
1751 * shrink the value until it is acceptable to the HW.
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001752 */
Jon Masonb03e7492011-07-20 15:20:54 -05001753 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1754 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001755 if (!rc)
1756 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001757
Jon Mason62f392e2011-10-14 14:56:14 -05001758 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001759 mrrs /= 2;
1760 }
Jon Mason62f392e2011-10-14 14:56:14 -05001761
1762 if (mrrs < 128)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001763 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001764}
1765
Yijing Wang5895af72013-08-26 16:33:06 +08001766static void pcie_bus_detect_mps(struct pci_dev *dev)
1767{
1768 struct pci_dev *bridge = dev->bus->self;
1769 int mps, p_mps;
1770
1771 if (!bridge)
1772 return;
1773
1774 mps = pcie_get_mps(dev);
1775 p_mps = pcie_get_mps(bridge);
1776
1777 if (mps != p_mps)
1778 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1779 mps, pci_name(bridge), p_mps);
1780}
1781
Jon Masonb03e7492011-07-20 15:20:54 -05001782static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1783{
Jon Masona513a992011-10-14 14:56:16 -05001784 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001785
1786 if (!pci_is_pcie(dev))
1787 return 0;
1788
Yijing Wang5895af72013-08-26 16:33:06 +08001789 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1790 pcie_bus_detect_mps(dev);
1791 return 0;
1792 }
1793
Jon Masona513a992011-10-14 14:56:16 -05001794 mps = 128 << *(u8 *)data;
1795 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001796
1797 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05001798 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001799
Ryan Desfosses227f0642014-04-18 20:13:50 -04001800 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1801 pcie_get_mps(dev), 128 << dev->pcie_mpss,
Jon Masona513a992011-10-14 14:56:16 -05001802 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05001803
1804 return 0;
1805}
1806
Jon Masona513a992011-10-14 14:56:16 -05001807/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05001808 * parents then children fashion. If this changes, then this code will not
1809 * work as designed.
1810 */
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001811void pcie_bus_configure_settings(struct pci_bus *bus)
Jon Masonb03e7492011-07-20 15:20:54 -05001812{
Bjorn Helgaas1e358f92014-04-29 12:51:55 -06001813 u8 smpss = 0;
Jon Masonb03e7492011-07-20 15:20:54 -05001814
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001815 if (!bus->self)
1816 return;
1817
Jon Masonb03e7492011-07-20 15:20:54 -05001818 if (!pci_is_pcie(bus->self))
1819 return;
1820
Jon Mason5f39e672011-10-03 09:50:20 -05001821 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
Jon Mason33154722013-08-26 16:33:05 +08001822 * to be aware of the MPS of the destination. To work around this,
Jon Mason5f39e672011-10-03 09:50:20 -05001823 * simply force the MPS of the entire system to the smallest possible.
1824 */
1825 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1826 smpss = 0;
1827
Jon Masonb03e7492011-07-20 15:20:54 -05001828 if (pcie_bus_config == PCIE_BUS_SAFE) {
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001829 smpss = bus->self->pcie_mpss;
Jon Mason5f39e672011-10-03 09:50:20 -05001830
Jon Masonb03e7492011-07-20 15:20:54 -05001831 pcie_find_smpss(bus->self, &smpss);
1832 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1833 }
1834
1835 pcie_bus_configure_set(bus->self, &smpss);
1836 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1837}
Jon Masondebc3b72011-08-02 00:01:18 -05001838EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05001839
Bill Pemberton15856ad2012-11-21 15:35:00 -05001840unsigned int pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001841{
Yinghai Lub918c622012-05-17 18:51:11 -07001842 unsigned int devfn, pass, max = bus->busn_res.start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843 struct pci_dev *dev;
1844
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001845 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846
1847 /* Go find them, Rover! */
1848 for (devfn = 0; devfn < 0x100; devfn += 8)
1849 pci_scan_slot(bus, devfn);
1850
Yu Zhaoa28724b2009-03-20 11:25:13 +08001851 /* Reserve buses for SR-IOV capability. */
1852 max += pci_iov_bus_range(bus);
1853
Linus Torvalds1da177e2005-04-16 15:20:36 -07001854 /*
1855 * After performing arch-dependent fixup of the bus, look behind
1856 * all PCI-to-PCI bridges on this bus.
1857 */
Alex Chiang74710de2009-03-20 14:56:10 -06001858 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001859 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06001860 pcibios_fixup_bus(bus);
Jiang Liu981cf9e2013-04-12 05:44:16 +00001861 bus->is_added = 1;
Alex Chiang74710de2009-03-20 14:56:10 -06001862 }
1863
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001864 for (pass = 0; pass < 2; pass++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865 list_for_each_entry(dev, &bus->devices, bus_list) {
Yijing Wang6788a512014-05-04 12:23:38 +08001866 if (pci_is_bridge(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 max = pci_scan_bridge(bus, dev, max, pass);
1868 }
1869
1870 /*
1871 * We've scanned the bus and so we know all about what's on
1872 * the other side of any bridges that may be on this bus plus
1873 * any devices.
1874 *
1875 * Return how far we've got finding sub-buses.
1876 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001877 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878 return max;
1879}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001880EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001882/**
1883 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1884 * @bridge: Host bridge to set up.
1885 *
1886 * Default empty implementation. Replace with an architecture-specific setup
1887 * routine, if necessary.
1888 */
1889int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1890{
1891 return 0;
1892}
1893
Jiang Liu10a95742013-04-12 05:44:20 +00001894void __weak pcibios_add_bus(struct pci_bus *bus)
1895{
1896}
1897
1898void __weak pcibios_remove_bus(struct pci_bus *bus)
1899{
1900}
1901
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001902struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1903 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001905 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001906 struct pci_host_bridge *bridge;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001907 struct pci_bus *b, *b2;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001908 struct pci_host_bridge_window *window, *n;
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001909 struct resource *res;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001910 resource_size_t offset;
1911 char bus_addr[64];
1912 char *fmt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913
Catalin Marinas670ba0c2014-09-29 15:29:26 +01001914 b = pci_alloc_bus(NULL);
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001915 if (!b)
Yinghai Lu7b543662012-04-02 18:31:53 -07001916 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917
1918 b->sysdata = sysdata;
1919 b->ops = ops;
Yinghai Lu4f535092013-01-21 13:20:52 -08001920 b->number = b->busn_res.start = bus;
Catalin Marinas670ba0c2014-09-29 15:29:26 +01001921 pci_bus_assign_domain_nr(b, parent);
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001922 b2 = pci_find_bus(pci_domain_nr(b), bus);
1923 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001925 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926 goto err_out;
1927 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001928
Yinghai Lu7b543662012-04-02 18:31:53 -07001929 bridge = pci_alloc_host_bridge(b);
1930 if (!bridge)
1931 goto err_out;
1932
1933 bridge->dev.parent = parent;
Jiang Liu70efde22013-06-07 16:16:51 -06001934 bridge->dev.release = pci_release_host_bridge_dev;
Yinghai Lu7b543662012-04-02 18:31:53 -07001935 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001936 error = pcibios_root_bridge_prepare(bridge);
Jiang Liu343df772013-06-07 01:10:08 +08001937 if (error) {
1938 kfree(bridge);
1939 goto err_out;
1940 }
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001941
Yinghai Lu7b543662012-04-02 18:31:53 -07001942 error = device_register(&bridge->dev);
Jiang Liu343df772013-06-07 01:10:08 +08001943 if (error) {
1944 put_device(&bridge->dev);
1945 goto err_out;
1946 }
Yinghai Lu7b543662012-04-02 18:31:53 -07001947 b->bridge = get_device(&bridge->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001948 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001949 pci_set_bus_of_node(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950
Yinghai Lu0d358f22008-02-19 03:20:41 -08001951 if (!parent)
1952 set_dev_node(b->bridge, pcibus_to_node(b));
1953
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001954 b->dev.class = &pcibus_class;
1955 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001956 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001957 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 if (error)
1959 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960
Jiang Liu10a95742013-04-12 05:44:20 +00001961 pcibios_add_bus(b);
1962
Linus Torvalds1da177e2005-04-16 15:20:36 -07001963 /* Create legacy_io and legacy_mem files for this bus */
1964 pci_create_legacy_files(b);
1965
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001966 if (parent)
1967 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1968 else
1969 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1970
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001971 /* Add initial resources to the bus */
1972 list_for_each_entry_safe(window, n, resources, list) {
1973 list_move_tail(&window->list, &bridge->windows);
1974 res = window->res;
1975 offset = window->offset;
Yinghai Luf848ffb2012-05-17 18:51:12 -07001976 if (res->flags & IORESOURCE_BUS)
1977 pci_bus_insert_busn_res(b, bus, res->end);
1978 else
1979 pci_bus_add_resource(b, res, 0);
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001980 if (offset) {
1981 if (resource_type(res) == IORESOURCE_IO)
1982 fmt = " (bus address [%#06llx-%#06llx])";
1983 else
1984 fmt = " (bus address [%#010llx-%#010llx])";
1985 snprintf(bus_addr, sizeof(bus_addr), fmt,
1986 (unsigned long long) (res->start - offset),
1987 (unsigned long long) (res->end - offset));
1988 } else
1989 bus_addr[0] = '\0';
1990 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001991 }
1992
Bjorn Helgaasa5390aa2012-02-23 20:18:59 -07001993 down_write(&pci_bus_sem);
1994 list_add_tail(&b->node, &pci_root_buses);
1995 up_write(&pci_bus_sem);
1996
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997 return b;
1998
Linus Torvalds1da177e2005-04-16 15:20:36 -07001999class_dev_reg_err:
Yinghai Lu7b543662012-04-02 18:31:53 -07002000 put_device(&bridge->dev);
2001 device_unregister(&bridge->dev);
Yinghai Lu7b543662012-04-02 18:31:53 -07002002err_out:
2003 kfree(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004 return NULL;
2005}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002006
Yinghai Lu98a35832012-05-18 11:35:50 -06002007int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2008{
2009 struct resource *res = &b->busn_res;
2010 struct resource *parent_res, *conflict;
2011
2012 res->start = bus;
2013 res->end = bus_max;
2014 res->flags = IORESOURCE_BUS;
2015
2016 if (!pci_is_root_bus(b))
2017 parent_res = &b->parent->busn_res;
2018 else {
2019 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2020 res->flags |= IORESOURCE_PCI_FIXED;
2021 }
2022
Andreas Noeverced04d12014-01-23 21:59:24 +01002023 conflict = request_resource_conflict(parent_res, res);
Yinghai Lu98a35832012-05-18 11:35:50 -06002024
2025 if (conflict)
2026 dev_printk(KERN_DEBUG, &b->dev,
2027 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2028 res, pci_is_root_bus(b) ? "domain " : "",
2029 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06002030
2031 return conflict == NULL;
2032}
2033
2034int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2035{
2036 struct resource *res = &b->busn_res;
2037 struct resource old_res = *res;
2038 resource_size_t size;
2039 int ret;
2040
2041 if (res->start > bus_max)
2042 return -EINVAL;
2043
2044 size = bus_max - res->start + 1;
2045 ret = adjust_resource(res, res->start, size);
2046 dev_printk(KERN_DEBUG, &b->dev,
2047 "busn_res: %pR end %s updated to %02x\n",
2048 &old_res, ret ? "can not be" : "is", bus_max);
2049
2050 if (!ret && !res->parent)
2051 pci_bus_insert_busn_res(b, res->start, res->end);
2052
2053 return ret;
2054}
2055
2056void pci_bus_release_busn_res(struct pci_bus *b)
2057{
2058 struct resource *res = &b->busn_res;
2059 int ret;
2060
2061 if (!res->flags || !res->parent)
2062 return;
2063
2064 ret = release_resource(res);
2065 dev_printk(KERN_DEBUG, &b->dev,
2066 "busn_res: %pR %s released\n",
2067 res, ret ? "can not be" : "is");
2068}
2069
Bill Pemberton15856ad2012-11-21 15:35:00 -05002070struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002071 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2072{
Yinghai Lu4d99f522012-05-17 18:51:12 -07002073 struct pci_host_bridge_window *window;
2074 bool found = false;
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002075 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07002076 int max;
2077
2078 list_for_each_entry(window, resources, list)
2079 if (window->res->flags & IORESOURCE_BUS) {
2080 found = true;
2081 break;
2082 }
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002083
2084 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2085 if (!b)
2086 return NULL;
2087
Yinghai Lu4d99f522012-05-17 18:51:12 -07002088 if (!found) {
2089 dev_info(&b->dev,
2090 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2091 bus);
2092 pci_bus_insert_busn_res(b, bus, 255);
2093 }
2094
2095 max = pci_scan_child_bus(b);
2096
2097 if (!found)
2098 pci_bus_update_busn_res_end(b, max);
2099
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06002100 pci_bus_add_devices(b);
2101 return b;
2102}
2103EXPORT_SYMBOL(pci_scan_root_bus);
2104
Bjorn Helgaas7e00fe22011-10-28 16:26:05 -06002105/* Deprecated; use pci_scan_root_bus() instead */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002106struct pci_bus *pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002107 int bus, struct pci_ops *ops, void *sysdata)
2108{
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06002109 LIST_HEAD(resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002110 struct pci_bus *b;
2111
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06002112 pci_add_resource(&resources, &ioport_resource);
2113 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07002114 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06002115 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002116 if (b)
Yinghai Lu857c3b62012-05-17 18:51:12 -07002117 pci_scan_child_bus(b);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06002118 else
2119 pci_free_resource_list(&resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10002120 return b;
2121}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002122EXPORT_SYMBOL(pci_scan_bus_parented);
2123
Bill Pemberton15856ad2012-11-21 15:35:00 -05002124struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002125 void *sysdata)
2126{
2127 LIST_HEAD(resources);
2128 struct pci_bus *b;
2129
2130 pci_add_resource(&resources, &ioport_resource);
2131 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07002132 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002133 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2134 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07002135 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06002136 pci_bus_add_devices(b);
2137 } else {
2138 pci_free_resource_list(&resources);
2139 }
2140 return b;
2141}
2142EXPORT_SYMBOL(pci_scan_bus);
2143
Alex Chiang3ed4fd92009-03-20 14:56:25 -06002144/**
Yinghai Lu2f320522012-01-21 02:08:22 -08002145 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2146 * @bridge: PCI bridge for the bus to scan
2147 *
2148 * Scan a PCI bus and child buses for new devices, add them,
2149 * and enable them, resizing bridge mmio/io resource if necessary
2150 * and possible. The caller must ensure the child devices are already
2151 * removed for resizing to occur.
2152 *
2153 * Returns the max number of subordinate bus discovered.
2154 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002155unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
Yinghai Lu2f320522012-01-21 02:08:22 -08002156{
2157 unsigned int max;
2158 struct pci_bus *bus = bridge->subordinate;
2159
2160 max = pci_scan_child_bus(bus);
2161
2162 pci_assign_unassigned_bridge_resources(bridge);
2163
2164 pci_bus_add_devices(bus);
2165
2166 return max;
2167}
2168
Yinghai Lua5213a32012-10-30 14:31:21 -06002169/**
2170 * pci_rescan_bus - scan a PCI bus for devices.
2171 * @bus: PCI bus to scan
2172 *
2173 * Scan a PCI bus and child buses for new devices, adds them,
2174 * and enables them.
2175 *
2176 * Returns the max number of subordinate bus discovered.
2177 */
Bjorn Helgaas10874f52014-04-14 16:11:40 -06002178unsigned int pci_rescan_bus(struct pci_bus *bus)
Yinghai Lua5213a32012-10-30 14:31:21 -06002179{
2180 unsigned int max;
2181
2182 max = pci_scan_child_bus(bus);
2183 pci_assign_unassigned_bus_resources(bus);
2184 pci_bus_add_devices(bus);
2185
2186 return max;
2187}
2188EXPORT_SYMBOL_GPL(pci_rescan_bus);
2189
Rafael J. Wysocki9d169472014-01-10 15:22:18 +01002190/*
2191 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2192 * routines should always be executed under this mutex.
2193 */
2194static DEFINE_MUTEX(pci_rescan_remove_lock);
2195
2196void pci_lock_rescan_remove(void)
2197{
2198 mutex_lock(&pci_rescan_remove_lock);
2199}
2200EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2201
2202void pci_unlock_rescan_remove(void)
2203{
2204 mutex_unlock(&pci_rescan_remove_lock);
2205}
2206EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2207
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002208static int __init pci_sort_bf_cmp(const struct device *d_a,
2209 const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002210{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002211 const struct pci_dev *a = to_pci_dev(d_a);
2212 const struct pci_dev *b = to_pci_dev(d_b);
2213
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002214 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2215 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2216
2217 if (a->bus->number < b->bus->number) return -1;
2218 else if (a->bus->number > b->bus->number) return 1;
2219
2220 if (a->devfn < b->devfn) return -1;
2221 else if (a->devfn > b->devfn) return 1;
2222
2223 return 0;
2224}
2225
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08002226void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002227{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002228 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002229}