Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 30 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 32 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 33 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 34 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 36 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 37 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 38 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 39 | #include "i915_drv.h" |
| 40 | |
| 41 | #define DRM_I915_RING_DEBUG 1 |
| 42 | |
| 43 | |
| 44 | #if defined(CONFIG_DEBUG_FS) |
| 45 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 46 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 47 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 48 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 49 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 50 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 51 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 52 | static const char *yesno(int v) |
| 53 | { |
| 54 | return v ? "yes" : "no"; |
| 55 | } |
| 56 | |
| 57 | static int i915_capabilities(struct seq_file *m, void *data) |
| 58 | { |
| 59 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 60 | struct drm_device *dev = node->minor->dev; |
| 61 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 62 | |
| 63 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 65 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 66 | #define SEP_SEMICOLON ; |
| 67 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 68 | #undef PRINT_FLAG |
| 69 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 70 | |
| 71 | return 0; |
| 72 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 73 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 74 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 75 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 76 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 77 | return "P"; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 78 | else if (obj->pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 79 | return "p"; |
| 80 | else |
| 81 | return " "; |
| 82 | } |
| 83 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 84 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 85 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 86 | switch (obj->tiling_mode) { |
| 87 | default: |
| 88 | case I915_TILING_NONE: return " "; |
| 89 | case I915_TILING_X: return "X"; |
| 90 | case I915_TILING_Y: return "Y"; |
| 91 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 94 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 95 | { |
| 96 | return obj->has_global_gtt_mapping ? "g" : " "; |
| 97 | } |
| 98 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 99 | static void |
| 100 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 101 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 102 | struct i915_vma *vma; |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 103 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 104 | &obj->base, |
| 105 | get_pin_flag(obj), |
| 106 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 107 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 108 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 109 | obj->base.read_domains, |
| 110 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 111 | obj->last_read_seqno, |
| 112 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 113 | obj->last_fenced_seqno, |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 114 | i915_cache_level_str(obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 115 | obj->dirty ? " dirty" : "", |
| 116 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 117 | if (obj->base.name) |
| 118 | seq_printf(m, " (name: %d)", obj->base.name); |
Chris Wilson | c110a6d | 2012-08-11 15:41:02 +0100 | [diff] [blame] | 119 | if (obj->pin_count) |
| 120 | seq_printf(m, " (pinned x %d)", obj->pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 121 | if (obj->pin_display) |
| 122 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 124 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 125 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 126 | if (!i915_is_ggtt(vma->vm)) |
| 127 | seq_puts(m, " (pp"); |
| 128 | else |
| 129 | seq_puts(m, " (g"); |
| 130 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", |
| 131 | vma->node.start, vma->node.size); |
| 132 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 133 | if (obj->stolen) |
| 134 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 135 | if (obj->pin_mappable || obj->fault_mappable) { |
| 136 | char s[3], *t = s; |
| 137 | if (obj->pin_mappable) |
| 138 | *t++ = 'p'; |
| 139 | if (obj->fault_mappable) |
| 140 | *t++ = 'f'; |
| 141 | *t = '\0'; |
| 142 | seq_printf(m, " (%s mappable)", s); |
| 143 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 144 | if (obj->ring != NULL) |
| 145 | seq_printf(m, " (%s)", obj->ring->name); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 146 | } |
| 147 | |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 148 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
| 149 | { |
| 150 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); |
| 151 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 152 | seq_putc(m, ' '); |
| 153 | } |
| 154 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 155 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 156 | { |
| 157 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 158 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 159 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 160 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 161 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 162 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 163 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 164 | size_t total_obj_size, total_gtt_size; |
| 165 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 166 | |
| 167 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 168 | if (ret) |
| 169 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 170 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 171 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 172 | switch (list) { |
| 173 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 174 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 175 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 176 | break; |
| 177 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 178 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 179 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 180 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 181 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 182 | mutex_unlock(&dev->struct_mutex); |
| 183 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 184 | } |
| 185 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 186 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 187 | list_for_each_entry(vma, head, mm_list) { |
| 188 | seq_printf(m, " "); |
| 189 | describe_obj(m, vma->obj); |
| 190 | seq_printf(m, "\n"); |
| 191 | total_obj_size += vma->obj->base.size; |
| 192 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 193 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 194 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 195 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 196 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 197 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 198 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 202 | static int obj_rank_by_stolen(void *priv, |
| 203 | struct list_head *A, struct list_head *B) |
| 204 | { |
| 205 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 206 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 207 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 208 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 209 | |
| 210 | return a->stolen->start - b->stolen->start; |
| 211 | } |
| 212 | |
| 213 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 214 | { |
| 215 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 216 | struct drm_device *dev = node->minor->dev; |
| 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 218 | struct drm_i915_gem_object *obj; |
| 219 | size_t total_obj_size, total_gtt_size; |
| 220 | LIST_HEAD(stolen); |
| 221 | int count, ret; |
| 222 | |
| 223 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 224 | if (ret) |
| 225 | return ret; |
| 226 | |
| 227 | total_obj_size = total_gtt_size = count = 0; |
| 228 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 229 | if (obj->stolen == NULL) |
| 230 | continue; |
| 231 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 232 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 233 | |
| 234 | total_obj_size += obj->base.size; |
| 235 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 236 | count++; |
| 237 | } |
| 238 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 239 | if (obj->stolen == NULL) |
| 240 | continue; |
| 241 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 242 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 243 | |
| 244 | total_obj_size += obj->base.size; |
| 245 | count++; |
| 246 | } |
| 247 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 248 | seq_puts(m, "Stolen:\n"); |
| 249 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 250 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 251 | seq_puts(m, " "); |
| 252 | describe_obj(m, obj); |
| 253 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 254 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 255 | } |
| 256 | mutex_unlock(&dev->struct_mutex); |
| 257 | |
| 258 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 259 | count, total_obj_size, total_gtt_size); |
| 260 | return 0; |
| 261 | } |
| 262 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 263 | #define count_objects(list, member) do { \ |
| 264 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 265 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 266 | ++count; \ |
| 267 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 268 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 269 | ++mappable_count; \ |
| 270 | } \ |
| 271 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 272 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 273 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 274 | struct file_stats { |
| 275 | int count; |
| 276 | size_t total, active, inactive, unbound; |
| 277 | }; |
| 278 | |
| 279 | static int per_file_stats(int id, void *ptr, void *data) |
| 280 | { |
| 281 | struct drm_i915_gem_object *obj = ptr; |
| 282 | struct file_stats *stats = data; |
| 283 | |
| 284 | stats->count++; |
| 285 | stats->total += obj->base.size; |
| 286 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 287 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 288 | if (!list_empty(&obj->ring_list)) |
| 289 | stats->active += obj->base.size; |
| 290 | else |
| 291 | stats->inactive += obj->base.size; |
| 292 | } else { |
| 293 | if (!list_empty(&obj->global_list)) |
| 294 | stats->unbound += obj->base.size; |
| 295 | } |
| 296 | |
| 297 | return 0; |
| 298 | } |
| 299 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 300 | #define count_vmas(list, member) do { \ |
| 301 | list_for_each_entry(vma, list, member) { \ |
| 302 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 303 | ++count; \ |
| 304 | if (vma->obj->map_and_fenceable) { \ |
| 305 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 306 | ++mappable_count; \ |
| 307 | } \ |
| 308 | } \ |
| 309 | } while (0) |
| 310 | |
| 311 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 312 | { |
| 313 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 314 | struct drm_device *dev = node->minor->dev; |
| 315 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 316 | u32 count, mappable_count, purgeable_count; |
| 317 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 318 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 319 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 320 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 321 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 322 | int ret; |
| 323 | |
| 324 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 325 | if (ret) |
| 326 | return ret; |
| 327 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 328 | seq_printf(m, "%u objects, %zu bytes\n", |
| 329 | dev_priv->mm.object_count, |
| 330 | dev_priv->mm.object_memory); |
| 331 | |
| 332 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 333 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 334 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 335 | count, mappable_count, size, mappable_size); |
| 336 | |
| 337 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 338 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 339 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 340 | count, mappable_count, size, mappable_size); |
| 341 | |
| 342 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 343 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 344 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 345 | count, mappable_count, size, mappable_size); |
| 346 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 347 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 348 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 349 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 350 | if (obj->madv == I915_MADV_DONTNEED) |
| 351 | purgeable_size += obj->base.size, ++purgeable_count; |
| 352 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 353 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 354 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 355 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 356 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 357 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 358 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 359 | ++count; |
| 360 | } |
| 361 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 362 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 363 | ++mappable_count; |
| 364 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 365 | if (obj->madv == I915_MADV_DONTNEED) { |
| 366 | purgeable_size += obj->base.size; |
| 367 | ++purgeable_count; |
| 368 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 369 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 370 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 371 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 372 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 373 | mappable_count, mappable_size); |
| 374 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 375 | count, size); |
| 376 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 377 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 378 | dev_priv->gtt.base.total, |
| 379 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 380 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 381 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 382 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 383 | struct file_stats stats; |
| 384 | |
| 385 | memset(&stats, 0, sizeof(stats)); |
| 386 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
| 387 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", |
| 388 | get_pid_task(file->pid, PIDTYPE_PID)->comm, |
| 389 | stats.count, |
| 390 | stats.total, |
| 391 | stats.active, |
| 392 | stats.inactive, |
| 393 | stats.unbound); |
| 394 | } |
| 395 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 396 | mutex_unlock(&dev->struct_mutex); |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 401 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 402 | { |
| 403 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 404 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 405 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 406 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 407 | struct drm_i915_gem_object *obj; |
| 408 | size_t total_obj_size, total_gtt_size; |
| 409 | int count, ret; |
| 410 | |
| 411 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 412 | if (ret) |
| 413 | return ret; |
| 414 | |
| 415 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 416 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 417 | if (list == PINNED_LIST && obj->pin_count == 0) |
| 418 | continue; |
| 419 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 420 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 421 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 422 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 423 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 424 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 425 | count++; |
| 426 | } |
| 427 | |
| 428 | mutex_unlock(&dev->struct_mutex); |
| 429 | |
| 430 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 431 | count, total_obj_size, total_gtt_size); |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 436 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 437 | { |
| 438 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 439 | struct drm_device *dev = node->minor->dev; |
| 440 | unsigned long flags; |
| 441 | struct intel_crtc *crtc; |
| 442 | |
| 443 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 444 | const char pipe = pipe_name(crtc->pipe); |
| 445 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 446 | struct intel_unpin_work *work; |
| 447 | |
| 448 | spin_lock_irqsave(&dev->event_lock, flags); |
| 449 | work = crtc->unpin_work; |
| 450 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 451 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 452 | pipe, plane); |
| 453 | } else { |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 454 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 455 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 456 | pipe, plane); |
| 457 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 458 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 459 | pipe, plane); |
| 460 | } |
| 461 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 462 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 463 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 464 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 465 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 466 | |
| 467 | if (work->old_fb_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 468 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
| 469 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 470 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
| 471 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 472 | } |
| 473 | if (work->pending_flip_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 474 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
| 475 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 476 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
| 477 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 478 | } |
| 479 | } |
| 480 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 481 | } |
| 482 | |
| 483 | return 0; |
| 484 | } |
| 485 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 486 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 487 | { |
| 488 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 489 | struct drm_device *dev = node->minor->dev; |
| 490 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 491 | struct intel_ring_buffer *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 492 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 493 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 494 | |
| 495 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 496 | if (ret) |
| 497 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 498 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 499 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 500 | for_each_ring(ring, dev_priv, i) { |
| 501 | if (list_empty(&ring->request_list)) |
| 502 | continue; |
| 503 | |
| 504 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 505 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 506 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 507 | list) { |
| 508 | seq_printf(m, " %d @ %d\n", |
| 509 | gem_request->seqno, |
| 510 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 511 | } |
| 512 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 513 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 514 | mutex_unlock(&dev->struct_mutex); |
| 515 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 516 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 517 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 518 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 519 | return 0; |
| 520 | } |
| 521 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 522 | static void i915_ring_seqno_info(struct seq_file *m, |
| 523 | struct intel_ring_buffer *ring) |
| 524 | { |
| 525 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 526 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 527 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 528 | } |
| 529 | } |
| 530 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 531 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 532 | { |
| 533 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 534 | struct drm_device *dev = node->minor->dev; |
| 535 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 536 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 537 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 538 | |
| 539 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 540 | if (ret) |
| 541 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 542 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 543 | for_each_ring(ring, dev_priv, i) |
| 544 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 545 | |
| 546 | mutex_unlock(&dev->struct_mutex); |
| 547 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | |
| 552 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 553 | { |
| 554 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 555 | struct drm_device *dev = node->minor->dev; |
| 556 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 557 | struct intel_ring_buffer *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 558 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 559 | |
| 560 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 561 | if (ret) |
| 562 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 563 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 564 | if (IS_VALLEYVIEW(dev)) { |
| 565 | seq_printf(m, "Display IER:\t%08x\n", |
| 566 | I915_READ(VLV_IER)); |
| 567 | seq_printf(m, "Display IIR:\t%08x\n", |
| 568 | I915_READ(VLV_IIR)); |
| 569 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 570 | I915_READ(VLV_IIR_RW)); |
| 571 | seq_printf(m, "Display IMR:\t%08x\n", |
| 572 | I915_READ(VLV_IMR)); |
| 573 | for_each_pipe(pipe) |
| 574 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 575 | pipe_name(pipe), |
| 576 | I915_READ(PIPESTAT(pipe))); |
| 577 | |
| 578 | seq_printf(m, "Master IER:\t%08x\n", |
| 579 | I915_READ(VLV_MASTER_IER)); |
| 580 | |
| 581 | seq_printf(m, "Render IER:\t%08x\n", |
| 582 | I915_READ(GTIER)); |
| 583 | seq_printf(m, "Render IIR:\t%08x\n", |
| 584 | I915_READ(GTIIR)); |
| 585 | seq_printf(m, "Render IMR:\t%08x\n", |
| 586 | I915_READ(GTIMR)); |
| 587 | |
| 588 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 589 | I915_READ(GEN6_PMIER)); |
| 590 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 591 | I915_READ(GEN6_PMIIR)); |
| 592 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 593 | I915_READ(GEN6_PMIMR)); |
| 594 | |
| 595 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 596 | I915_READ(PORT_HOTPLUG_EN)); |
| 597 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 598 | I915_READ(VLV_DPFLIPSTAT)); |
| 599 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 600 | I915_READ(DPINVGTT)); |
| 601 | |
| 602 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 603 | seq_printf(m, "Interrupt enable: %08x\n", |
| 604 | I915_READ(IER)); |
| 605 | seq_printf(m, "Interrupt identity: %08x\n", |
| 606 | I915_READ(IIR)); |
| 607 | seq_printf(m, "Interrupt mask: %08x\n", |
| 608 | I915_READ(IMR)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 609 | for_each_pipe(pipe) |
| 610 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 611 | pipe_name(pipe), |
| 612 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 613 | } else { |
| 614 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 615 | I915_READ(DEIER)); |
| 616 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 617 | I915_READ(DEIIR)); |
| 618 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 619 | I915_READ(DEIMR)); |
| 620 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 621 | I915_READ(SDEIER)); |
| 622 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 623 | I915_READ(SDEIIR)); |
| 624 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 625 | I915_READ(SDEIMR)); |
| 626 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 627 | I915_READ(GTIER)); |
| 628 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 629 | I915_READ(GTIIR)); |
| 630 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 631 | I915_READ(GTIMR)); |
| 632 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 633 | seq_printf(m, "Interrupts received: %d\n", |
| 634 | atomic_read(&dev_priv->irq_received)); |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 635 | for_each_ring(ring, dev_priv, i) { |
Jesse Barnes | da64c6f | 2011-08-09 09:17:46 -0700 | [diff] [blame] | 636 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 637 | seq_printf(m, |
| 638 | "Graphics Interrupt mask (%s): %08x\n", |
| 639 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 640 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 641 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 642 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 643 | mutex_unlock(&dev->struct_mutex); |
| 644 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 645 | return 0; |
| 646 | } |
| 647 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 648 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 649 | { |
| 650 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 651 | struct drm_device *dev = node->minor->dev; |
| 652 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 653 | int i, ret; |
| 654 | |
| 655 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 656 | if (ret) |
| 657 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 658 | |
| 659 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 660 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 661 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 662 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 663 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 664 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 665 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 666 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 667 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 668 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 669 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 670 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 671 | } |
| 672 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 673 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 674 | return 0; |
| 675 | } |
| 676 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 677 | static int i915_hws_info(struct seq_file *m, void *data) |
| 678 | { |
| 679 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 680 | struct drm_device *dev = node->minor->dev; |
| 681 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 682 | struct intel_ring_buffer *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 683 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 684 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 685 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 686 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 687 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 688 | if (hws == NULL) |
| 689 | return 0; |
| 690 | |
| 691 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 692 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 693 | i * 4, |
| 694 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 695 | } |
| 696 | return 0; |
| 697 | } |
| 698 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 699 | static ssize_t |
| 700 | i915_error_state_write(struct file *filp, |
| 701 | const char __user *ubuf, |
| 702 | size_t cnt, |
| 703 | loff_t *ppos) |
| 704 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 705 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 706 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 707 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 708 | |
| 709 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 710 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 711 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 712 | if (ret) |
| 713 | return ret; |
| 714 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 715 | i915_destroy_error_state(dev); |
| 716 | mutex_unlock(&dev->struct_mutex); |
| 717 | |
| 718 | return cnt; |
| 719 | } |
| 720 | |
| 721 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 722 | { |
| 723 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 724 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 725 | |
| 726 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 727 | if (!error_priv) |
| 728 | return -ENOMEM; |
| 729 | |
| 730 | error_priv->dev = dev; |
| 731 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 732 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 733 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 734 | file->private_data = error_priv; |
| 735 | |
| 736 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 740 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 741 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 742 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 743 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 744 | kfree(error_priv); |
| 745 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 746 | return 0; |
| 747 | } |
| 748 | |
| 749 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 750 | size_t count, loff_t *pos) |
| 751 | { |
| 752 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 753 | struct drm_i915_error_state_buf error_str; |
| 754 | loff_t tmp_pos = 0; |
| 755 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 756 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 757 | |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 758 | ret = i915_error_state_buf_init(&error_str, count, *pos); |
| 759 | if (ret) |
| 760 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 761 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 762 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 763 | if (ret) |
| 764 | goto out; |
| 765 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 766 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 767 | error_str.buf, |
| 768 | error_str.bytes); |
| 769 | |
| 770 | if (ret_count < 0) |
| 771 | ret = ret_count; |
| 772 | else |
| 773 | *pos = error_str.start + ret_count; |
| 774 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 775 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 776 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | static const struct file_operations i915_error_state_fops = { |
| 780 | .owner = THIS_MODULE, |
| 781 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 782 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 783 | .write = i915_error_state_write, |
| 784 | .llseek = default_llseek, |
| 785 | .release = i915_error_state_release, |
| 786 | }; |
| 787 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 788 | static int |
| 789 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 790 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 791 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 792 | drm_i915_private_t *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 793 | int ret; |
| 794 | |
| 795 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 796 | if (ret) |
| 797 | return ret; |
| 798 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 799 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 800 | mutex_unlock(&dev->struct_mutex); |
| 801 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 802 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 803 | } |
| 804 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 805 | static int |
| 806 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 807 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 808 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 809 | int ret; |
| 810 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 811 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 812 | if (ret) |
| 813 | return ret; |
| 814 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 815 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 816 | mutex_unlock(&dev->struct_mutex); |
| 817 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 818 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 819 | } |
| 820 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 821 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 822 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 823 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 824 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 825 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
| 826 | { |
| 827 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 828 | struct drm_device *dev = node->minor->dev; |
| 829 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 830 | u16 crstanddelay; |
| 831 | int ret; |
| 832 | |
| 833 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 834 | if (ret) |
| 835 | return ret; |
| 836 | |
| 837 | crstanddelay = I915_READ16(CRSTANDVID); |
| 838 | |
| 839 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 840 | |
| 841 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); |
| 842 | |
| 843 | return 0; |
| 844 | } |
| 845 | |
| 846 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) |
| 847 | { |
| 848 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 849 | struct drm_device *dev = node->minor->dev; |
| 850 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 851 | int ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 852 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 853 | if (IS_GEN5(dev)) { |
| 854 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 855 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 856 | |
| 857 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 858 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 859 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 860 | MEMSTAT_VID_SHIFT); |
| 861 | seq_printf(m, "Current P-state: %d\n", |
| 862 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 863 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 864 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 865 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 866 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 867 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 868 | u32 rpupei, rpcurup, rpprevup; |
| 869 | u32 rpdownei, rpcurdown, rpprevdown; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 870 | int max_freq; |
| 871 | |
| 872 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 873 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 874 | if (ret) |
| 875 | return ret; |
| 876 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 877 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 878 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 879 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 880 | reqf &= ~GEN6_TURBO_DISABLE; |
| 881 | if (IS_HASWELL(dev)) |
| 882 | reqf >>= 24; |
| 883 | else |
| 884 | reqf >>= 25; |
| 885 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 886 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 887 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 888 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 889 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 890 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 891 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 892 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 893 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 894 | if (IS_HASWELL(dev)) |
| 895 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 896 | else |
| 897 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 898 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 899 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 900 | gen6_gt_force_wake_put(dev_priv); |
| 901 | mutex_unlock(&dev->struct_mutex); |
| 902 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 903 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 904 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 905 | seq_printf(m, "Render p-state ratio: %d\n", |
| 906 | (gt_perf_status & 0xff00) >> 8); |
| 907 | seq_printf(m, "Render p-state VID: %d\n", |
| 908 | gt_perf_status & 0xff); |
| 909 | seq_printf(m, "Render p-state limit: %d\n", |
| 910 | rp_state_limits & 0xff); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 911 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 912 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 913 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 914 | GEN6_CURICONT_MASK); |
| 915 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 916 | GEN6_CURBSYTAVG_MASK); |
| 917 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 918 | GEN6_CURBSYTAVG_MASK); |
| 919 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 920 | GEN6_CURIAVG_MASK); |
| 921 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 922 | GEN6_CURBSYTAVG_MASK); |
| 923 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 924 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 925 | |
| 926 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 927 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 928 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 929 | |
| 930 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 931 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 932 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 933 | |
| 934 | max_freq = rp_state_cap & 0xff; |
| 935 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 936 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 937 | |
| 938 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
| 939 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 940 | } else if (IS_VALLEYVIEW(dev)) { |
| 941 | u32 freq_sts, val; |
| 942 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 943 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 944 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 945 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 946 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 947 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 948 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 949 | seq_printf(m, "max GPU freq: %d MHz\n", |
| 950 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 951 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 952 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 953 | seq_printf(m, "min GPU freq: %d MHz\n", |
| 954 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 955 | |
| 956 | seq_printf(m, "current GPU freq: %d MHz\n", |
| 957 | vlv_gpu_freq(dev_priv->mem_freq, |
| 958 | (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 959 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 960 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 961 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 962 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 963 | |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | static int i915_delayfreq_table(struct seq_file *m, void *unused) |
| 968 | { |
| 969 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 970 | struct drm_device *dev = node->minor->dev; |
| 971 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 972 | u32 delayfreq; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 973 | int ret, i; |
| 974 | |
| 975 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 976 | if (ret) |
| 977 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 978 | |
| 979 | for (i = 0; i < 16; i++) { |
| 980 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 981 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
| 982 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 983 | } |
| 984 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 985 | mutex_unlock(&dev->struct_mutex); |
| 986 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 987 | return 0; |
| 988 | } |
| 989 | |
| 990 | static inline int MAP_TO_MV(int map) |
| 991 | { |
| 992 | return 1250 - (map * 25); |
| 993 | } |
| 994 | |
| 995 | static int i915_inttoext_table(struct seq_file *m, void *unused) |
| 996 | { |
| 997 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 998 | struct drm_device *dev = node->minor->dev; |
| 999 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1000 | u32 inttoext; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1001 | int ret, i; |
| 1002 | |
| 1003 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1004 | if (ret) |
| 1005 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1006 | |
| 1007 | for (i = 1; i <= 32; i++) { |
| 1008 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); |
| 1009 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); |
| 1010 | } |
| 1011 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1012 | mutex_unlock(&dev->struct_mutex); |
| 1013 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1014 | return 0; |
| 1015 | } |
| 1016 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1017 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1018 | { |
| 1019 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1020 | struct drm_device *dev = node->minor->dev; |
| 1021 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1022 | u32 rgvmodectl, rstdbyctl; |
| 1023 | u16 crstandvid; |
| 1024 | int ret; |
| 1025 | |
| 1026 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1027 | if (ret) |
| 1028 | return ret; |
| 1029 | |
| 1030 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1031 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1032 | crstandvid = I915_READ16(CRSTANDVID); |
| 1033 | |
| 1034 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1035 | |
| 1036 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1037 | "yes" : "no"); |
| 1038 | seq_printf(m, "Boost freq: %d\n", |
| 1039 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1040 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1041 | seq_printf(m, "HW control enabled: %s\n", |
| 1042 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1043 | seq_printf(m, "SW control enabled: %s\n", |
| 1044 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1045 | seq_printf(m, "Gated voltage change: %s\n", |
| 1046 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1047 | seq_printf(m, "Starting frequency: P%d\n", |
| 1048 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1049 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1050 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1051 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1052 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1053 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1054 | seq_printf(m, "Render standby enabled: %s\n", |
| 1055 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1056 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1057 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1058 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1059 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1060 | break; |
| 1061 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1062 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1063 | break; |
| 1064 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1065 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1066 | break; |
| 1067 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1068 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1069 | break; |
| 1070 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1071 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1072 | break; |
| 1073 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1074 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1075 | break; |
| 1076 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1077 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1078 | break; |
| 1079 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1080 | |
| 1081 | return 0; |
| 1082 | } |
| 1083 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1084 | static int gen6_drpc_info(struct seq_file *m) |
| 1085 | { |
| 1086 | |
| 1087 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1088 | struct drm_device *dev = node->minor->dev; |
| 1089 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1090 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1091 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1092 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1093 | |
| 1094 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1095 | if (ret) |
| 1096 | return ret; |
| 1097 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1098 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1099 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1100 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1101 | |
| 1102 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1103 | seq_puts(m, "RC information inaccurate because somebody " |
| 1104 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1105 | } else { |
| 1106 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1107 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1108 | udelay(10); |
| 1109 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1110 | } |
| 1111 | |
| 1112 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1113 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1114 | |
| 1115 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1116 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1117 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1118 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1119 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1120 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1121 | |
| 1122 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1123 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1124 | seq_printf(m, "HW control enabled: %s\n", |
| 1125 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1126 | seq_printf(m, "SW control enabled: %s\n", |
| 1127 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1128 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1129 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1130 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1131 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1132 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1133 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1134 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1135 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1136 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1137 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1138 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1139 | case GEN6_RC0: |
| 1140 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1141 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1142 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1143 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1144 | break; |
| 1145 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1146 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1147 | break; |
| 1148 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1149 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1150 | break; |
| 1151 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1152 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1153 | break; |
| 1154 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1155 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1156 | break; |
| 1157 | } |
| 1158 | |
| 1159 | seq_printf(m, "Core Power Down: %s\n", |
| 1160 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1161 | |
| 1162 | /* Not exactly sure what this is */ |
| 1163 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1164 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1165 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1166 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1167 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1168 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1169 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1170 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1171 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1172 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1173 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1174 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1175 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1176 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1177 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1178 | return 0; |
| 1179 | } |
| 1180 | |
| 1181 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1182 | { |
| 1183 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1184 | struct drm_device *dev = node->minor->dev; |
| 1185 | |
| 1186 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 1187 | return gen6_drpc_info(m); |
| 1188 | else |
| 1189 | return ironlake_drpc_info(m); |
| 1190 | } |
| 1191 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1192 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1193 | { |
| 1194 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1195 | struct drm_device *dev = node->minor->dev; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1197 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1198 | if (!I915_HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1199 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1200 | return 0; |
| 1201 | } |
| 1202 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1203 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1204 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1205 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1206 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1207 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1208 | case FBC_OK: |
| 1209 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1210 | break; |
| 1211 | case FBC_UNSUPPORTED: |
| 1212 | seq_puts(m, "unsupported by this chipset"); |
| 1213 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1214 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1215 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1216 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1217 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1218 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1219 | break; |
| 1220 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1221 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1222 | break; |
| 1223 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1224 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1225 | break; |
| 1226 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1227 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1228 | break; |
| 1229 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1230 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1231 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1232 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1233 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1234 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1235 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1236 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1237 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1238 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1239 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1240 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1241 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1242 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1243 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1244 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1245 | } |
| 1246 | return 0; |
| 1247 | } |
| 1248 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1249 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1250 | { |
| 1251 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1252 | struct drm_device *dev = node->minor->dev; |
| 1253 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1254 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1255 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1256 | seq_puts(m, "not supported\n"); |
| 1257 | return 0; |
| 1258 | } |
| 1259 | |
| 1260 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1261 | seq_puts(m, "enabled\n"); |
| 1262 | else |
| 1263 | seq_puts(m, "disabled\n"); |
| 1264 | |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1268 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1269 | { |
| 1270 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1271 | struct drm_device *dev = node->minor->dev; |
| 1272 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1273 | bool sr_enabled = false; |
| 1274 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1275 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1276 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1277 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1278 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1279 | else if (IS_I915GM(dev)) |
| 1280 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1281 | else if (IS_PINEVIEW(dev)) |
| 1282 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1283 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1284 | seq_printf(m, "self-refresh: %s\n", |
| 1285 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1286 | |
| 1287 | return 0; |
| 1288 | } |
| 1289 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1290 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1291 | { |
| 1292 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1293 | struct drm_device *dev = node->minor->dev; |
| 1294 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1295 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1296 | int ret; |
| 1297 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1298 | if (!IS_GEN5(dev)) |
| 1299 | return -ENODEV; |
| 1300 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1301 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1302 | if (ret) |
| 1303 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1304 | |
| 1305 | temp = i915_mch_val(dev_priv); |
| 1306 | chipset = i915_chipset_val(dev_priv); |
| 1307 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1308 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1309 | |
| 1310 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1311 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1312 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1313 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1314 | |
| 1315 | return 0; |
| 1316 | } |
| 1317 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1318 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1319 | { |
| 1320 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1321 | struct drm_device *dev = node->minor->dev; |
| 1322 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1323 | int ret; |
| 1324 | int gpu_freq, ia_freq; |
| 1325 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1326 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1327 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1328 | return 0; |
| 1329 | } |
| 1330 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1331 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1332 | if (ret) |
| 1333 | return ret; |
| 1334 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1335 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1336 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1337 | for (gpu_freq = dev_priv->rps.min_delay; |
| 1338 | gpu_freq <= dev_priv->rps.max_delay; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1339 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1340 | ia_freq = gpu_freq; |
| 1341 | sandybridge_pcode_read(dev_priv, |
| 1342 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1343 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1344 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1345 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1346 | ((ia_freq >> 0) & 0xff) * 100, |
| 1347 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1348 | } |
| 1349 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1350 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1351 | |
| 1352 | return 0; |
| 1353 | } |
| 1354 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1355 | static int i915_gfxec(struct seq_file *m, void *unused) |
| 1356 | { |
| 1357 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1358 | struct drm_device *dev = node->minor->dev; |
| 1359 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1360 | int ret; |
| 1361 | |
| 1362 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1363 | if (ret) |
| 1364 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1365 | |
| 1366 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); |
| 1367 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1368 | mutex_unlock(&dev->struct_mutex); |
| 1369 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1370 | return 0; |
| 1371 | } |
| 1372 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1373 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1374 | { |
| 1375 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1376 | struct drm_device *dev = node->minor->dev; |
| 1377 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1378 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1379 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1380 | int ret; |
| 1381 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1382 | if (data == NULL) |
| 1383 | return -ENOMEM; |
| 1384 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1385 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1386 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1387 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1388 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1389 | if (opregion->header) { |
| 1390 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1391 | seq_write(m, data, OPREGION_SIZE); |
| 1392 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1393 | |
| 1394 | mutex_unlock(&dev->struct_mutex); |
| 1395 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1396 | out: |
| 1397 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1398 | return 0; |
| 1399 | } |
| 1400 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1401 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1402 | { |
| 1403 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1404 | struct drm_device *dev = node->minor->dev; |
| 1405 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1406 | struct intel_fbdev *ifbdev; |
| 1407 | struct intel_framebuffer *fb; |
| 1408 | int ret; |
| 1409 | |
| 1410 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1411 | if (ret) |
| 1412 | return ret; |
| 1413 | |
| 1414 | ifbdev = dev_priv->fbdev; |
| 1415 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1416 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1417 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1418 | fb->base.width, |
| 1419 | fb->base.height, |
| 1420 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1421 | fb->base.bits_per_pixel, |
| 1422 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1423 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1424 | seq_putc(m, '\n'); |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1425 | mutex_unlock(&dev->mode_config.mutex); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1426 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1427 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1428 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
| 1429 | if (&fb->base == ifbdev->helper.fb) |
| 1430 | continue; |
| 1431 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1432 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1433 | fb->base.width, |
| 1434 | fb->base.height, |
| 1435 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1436 | fb->base.bits_per_pixel, |
| 1437 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1438 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1439 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1440 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1441 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1442 | |
| 1443 | return 0; |
| 1444 | } |
| 1445 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1446 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1447 | { |
| 1448 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1449 | struct drm_device *dev = node->minor->dev; |
| 1450 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1451 | struct intel_ring_buffer *ring; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1452 | struct i915_hw_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1453 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1454 | |
| 1455 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1456 | if (ret) |
| 1457 | return ret; |
| 1458 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1459 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1460 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1461 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1462 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1463 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1464 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1465 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1466 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1467 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1468 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1469 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1470 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1471 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
| 1472 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1473 | describe_ctx(m, ctx); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1474 | for_each_ring(ring, dev_priv, i) |
| 1475 | if (ring->default_context == ctx) |
| 1476 | seq_printf(m, "(default context %s) ", ring->name); |
| 1477 | |
| 1478 | describe_obj(m, ctx->obj); |
| 1479 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1480 | } |
| 1481 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1482 | mutex_unlock(&dev->mode_config.mutex); |
| 1483 | |
| 1484 | return 0; |
| 1485 | } |
| 1486 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1487 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1488 | { |
| 1489 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1490 | struct drm_device *dev = node->minor->dev; |
| 1491 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1492 | unsigned forcewake_count; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1493 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1494 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1495 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1496 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1497 | |
| 1498 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1499 | |
| 1500 | return 0; |
| 1501 | } |
| 1502 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1503 | static const char *swizzle_string(unsigned swizzle) |
| 1504 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1505 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1506 | case I915_BIT_6_SWIZZLE_NONE: |
| 1507 | return "none"; |
| 1508 | case I915_BIT_6_SWIZZLE_9: |
| 1509 | return "bit9"; |
| 1510 | case I915_BIT_6_SWIZZLE_9_10: |
| 1511 | return "bit9/bit10"; |
| 1512 | case I915_BIT_6_SWIZZLE_9_11: |
| 1513 | return "bit9/bit11"; |
| 1514 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1515 | return "bit9/bit10/bit11"; |
| 1516 | case I915_BIT_6_SWIZZLE_9_17: |
| 1517 | return "bit9/bit17"; |
| 1518 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1519 | return "bit9/bit10/bit17"; |
| 1520 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1521 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1522 | } |
| 1523 | |
| 1524 | return "bug"; |
| 1525 | } |
| 1526 | |
| 1527 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1528 | { |
| 1529 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1530 | struct drm_device *dev = node->minor->dev; |
| 1531 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1532 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1533 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1534 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1535 | if (ret) |
| 1536 | return ret; |
| 1537 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1538 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1539 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1540 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1541 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1542 | |
| 1543 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1544 | seq_printf(m, "DDC = 0x%08x\n", |
| 1545 | I915_READ(DCC)); |
| 1546 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1547 | I915_READ16(C0DRB3)); |
| 1548 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1549 | I915_READ16(C1DRB3)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1550 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1551 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1552 | I915_READ(MAD_DIMM_C0)); |
| 1553 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1554 | I915_READ(MAD_DIMM_C1)); |
| 1555 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1556 | I915_READ(MAD_DIMM_C2)); |
| 1557 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1558 | I915_READ(TILECTL)); |
| 1559 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1560 | I915_READ(ARB_MODE)); |
| 1561 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1562 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1563 | } |
| 1564 | mutex_unlock(&dev->struct_mutex); |
| 1565 | |
| 1566 | return 0; |
| 1567 | } |
| 1568 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1569 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 1570 | { |
| 1571 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1572 | struct drm_device *dev = node->minor->dev; |
| 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1574 | struct intel_ring_buffer *ring; |
| 1575 | int i, ret; |
| 1576 | |
| 1577 | |
| 1578 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1579 | if (ret) |
| 1580 | return ret; |
| 1581 | if (INTEL_INFO(dev)->gen == 6) |
| 1582 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 1583 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 1584 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1585 | seq_printf(m, "%s\n", ring->name); |
| 1586 | if (INTEL_INFO(dev)->gen == 7) |
| 1587 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 1588 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 1589 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 1590 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 1591 | } |
| 1592 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1593 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1594 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1595 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1596 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
| 1597 | } |
| 1598 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
| 1599 | mutex_unlock(&dev->struct_mutex); |
| 1600 | |
| 1601 | return 0; |
| 1602 | } |
| 1603 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1604 | static int i915_dpio_info(struct seq_file *m, void *data) |
| 1605 | { |
| 1606 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1607 | struct drm_device *dev = node->minor->dev; |
| 1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1609 | int ret; |
| 1610 | |
| 1611 | |
| 1612 | if (!IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1613 | seq_puts(m, "unsupported\n"); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1614 | return 0; |
| 1615 | } |
| 1616 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1617 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1618 | if (ret) |
| 1619 | return ret; |
| 1620 | |
| 1621 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); |
| 1622 | |
| 1623 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1624 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1625 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1626 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1627 | |
| 1628 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1629 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1630 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1631 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1632 | |
| 1633 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1634 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1635 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1636 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1637 | |
Ville Syrjälä | 4abb2c3 | 2013-06-14 14:02:53 +0300 | [diff] [blame] | 1638 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1639 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
Ville Syrjälä | 4abb2c3 | 2013-06-14 14:02:53 +0300 | [diff] [blame] | 1640 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1641 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1642 | |
| 1643 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1644 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1645 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1646 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1647 | |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 1651 | static int i915_llc(struct seq_file *m, void *data) |
| 1652 | { |
| 1653 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1654 | struct drm_device *dev = node->minor->dev; |
| 1655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1656 | |
| 1657 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 1658 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 1659 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 1660 | |
| 1661 | return 0; |
| 1662 | } |
| 1663 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1664 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 1665 | { |
| 1666 | struct drm_info_node *node = m->private; |
| 1667 | struct drm_device *dev = node->minor->dev; |
| 1668 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1669 | u32 psrstat, psrperf; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1670 | |
| 1671 | if (!IS_HASWELL(dev)) { |
| 1672 | seq_puts(m, "PSR not supported on this platform\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1673 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
| 1674 | seq_puts(m, "PSR enabled\n"); |
| 1675 | } else { |
| 1676 | seq_puts(m, "PSR disabled: "); |
| 1677 | switch (dev_priv->no_psr_reason) { |
| 1678 | case PSR_NO_SOURCE: |
| 1679 | seq_puts(m, "not supported on this platform"); |
| 1680 | break; |
| 1681 | case PSR_NO_SINK: |
| 1682 | seq_puts(m, "not supported by panel"); |
| 1683 | break; |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1684 | case PSR_MODULE_PARAM: |
| 1685 | seq_puts(m, "disabled by flag"); |
| 1686 | break; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1687 | case PSR_CRTC_NOT_ACTIVE: |
| 1688 | seq_puts(m, "crtc not active"); |
| 1689 | break; |
| 1690 | case PSR_PWR_WELL_ENABLED: |
| 1691 | seq_puts(m, "power well enabled"); |
| 1692 | break; |
| 1693 | case PSR_NOT_TILED: |
| 1694 | seq_puts(m, "not tiled"); |
| 1695 | break; |
| 1696 | case PSR_SPRITE_ENABLED: |
| 1697 | seq_puts(m, "sprite enabled"); |
| 1698 | break; |
| 1699 | case PSR_S3D_ENABLED: |
| 1700 | seq_puts(m, "stereo 3d enabled"); |
| 1701 | break; |
| 1702 | case PSR_INTERLACED_ENABLED: |
| 1703 | seq_puts(m, "interlaced enabled"); |
| 1704 | break; |
| 1705 | case PSR_HSW_NOT_DDIA: |
| 1706 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); |
| 1707 | break; |
| 1708 | default: |
| 1709 | seq_puts(m, "unknown reason"); |
| 1710 | } |
| 1711 | seq_puts(m, "\n"); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1712 | return 0; |
| 1713 | } |
| 1714 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1715 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
| 1716 | |
| 1717 | seq_puts(m, "PSR Current State: "); |
| 1718 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { |
| 1719 | case EDP_PSR_STATUS_STATE_IDLE: |
| 1720 | seq_puts(m, "Reset state\n"); |
| 1721 | break; |
| 1722 | case EDP_PSR_STATUS_STATE_SRDONACK: |
| 1723 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); |
| 1724 | break; |
| 1725 | case EDP_PSR_STATUS_STATE_SRDENT: |
| 1726 | seq_puts(m, "SRD entry\n"); |
| 1727 | break; |
| 1728 | case EDP_PSR_STATUS_STATE_BUFOFF: |
| 1729 | seq_puts(m, "Wait for buffer turn off\n"); |
| 1730 | break; |
| 1731 | case EDP_PSR_STATUS_STATE_BUFON: |
| 1732 | seq_puts(m, "Wait for buffer turn on\n"); |
| 1733 | break; |
| 1734 | case EDP_PSR_STATUS_STATE_AUXACK: |
| 1735 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); |
| 1736 | break; |
| 1737 | case EDP_PSR_STATUS_STATE_SRDOFFACK: |
| 1738 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); |
| 1739 | break; |
| 1740 | default: |
| 1741 | seq_puts(m, "Unknown\n"); |
| 1742 | break; |
| 1743 | } |
| 1744 | |
| 1745 | seq_puts(m, "Link Status: "); |
| 1746 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { |
| 1747 | case EDP_PSR_STATUS_LINK_FULL_OFF: |
| 1748 | seq_puts(m, "Link is fully off\n"); |
| 1749 | break; |
| 1750 | case EDP_PSR_STATUS_LINK_FULL_ON: |
| 1751 | seq_puts(m, "Link is fully on\n"); |
| 1752 | break; |
| 1753 | case EDP_PSR_STATUS_LINK_STANDBY: |
| 1754 | seq_puts(m, "Link is in standby\n"); |
| 1755 | break; |
| 1756 | default: |
| 1757 | seq_puts(m, "Unknown\n"); |
| 1758 | break; |
| 1759 | } |
| 1760 | |
| 1761 | seq_printf(m, "PSR Entry Count: %u\n", |
| 1762 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & |
| 1763 | EDP_PSR_STATUS_COUNT_MASK); |
| 1764 | |
| 1765 | seq_printf(m, "Max Sleep Timer Counter: %u\n", |
| 1766 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & |
| 1767 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); |
| 1768 | |
| 1769 | seq_printf(m, "Had AUX error: %s\n", |
| 1770 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); |
| 1771 | |
| 1772 | seq_printf(m, "Sending AUX: %s\n", |
| 1773 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); |
| 1774 | |
| 1775 | seq_printf(m, "Sending Idle: %s\n", |
| 1776 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); |
| 1777 | |
| 1778 | seq_printf(m, "Sending TP2 TP3: %s\n", |
| 1779 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); |
| 1780 | |
| 1781 | seq_printf(m, "Sending TP1: %s\n", |
| 1782 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); |
| 1783 | |
| 1784 | seq_printf(m, "Idle Count: %u\n", |
| 1785 | psrstat & EDP_PSR_STATUS_IDLE_MASK); |
| 1786 | |
| 1787 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; |
| 1788 | seq_printf(m, "Performance Counter: %u\n", psrperf); |
| 1789 | |
| 1790 | return 0; |
| 1791 | } |
| 1792 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1793 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 1794 | { |
| 1795 | struct drm_info_node *node = m->private; |
| 1796 | struct drm_device *dev = node->minor->dev; |
| 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1798 | u64 power; |
| 1799 | u32 units; |
| 1800 | |
| 1801 | if (INTEL_INFO(dev)->gen < 6) |
| 1802 | return -ENODEV; |
| 1803 | |
| 1804 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 1805 | power = (power & 0x1f00) >> 8; |
| 1806 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 1807 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 1808 | power *= units; |
| 1809 | |
| 1810 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1811 | |
| 1812 | return 0; |
| 1813 | } |
| 1814 | |
| 1815 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 1816 | { |
| 1817 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1818 | struct drm_device *dev = node->minor->dev; |
| 1819 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1820 | |
| 1821 | if (!IS_HASWELL(dev)) { |
| 1822 | seq_puts(m, "not supported\n"); |
| 1823 | return 0; |
| 1824 | } |
| 1825 | |
| 1826 | mutex_lock(&dev_priv->pc8.lock); |
| 1827 | seq_printf(m, "Requirements met: %s\n", |
| 1828 | yesno(dev_priv->pc8.requirements_met)); |
| 1829 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); |
| 1830 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); |
| 1831 | seq_printf(m, "IRQs disabled: %s\n", |
| 1832 | yesno(dev_priv->pc8.irqs_disabled)); |
| 1833 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); |
| 1834 | mutex_unlock(&dev_priv->pc8.lock); |
| 1835 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1836 | return 0; |
| 1837 | } |
| 1838 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1839 | static int |
| 1840 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1841 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1842 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1843 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1844 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1845 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1846 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1847 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1848 | } |
| 1849 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1850 | static int |
| 1851 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1852 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1853 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1854 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1855 | DRM_INFO("Manually setting wedged to %llu\n", val); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1856 | i915_handle_error(dev, val); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1857 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1858 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1859 | } |
| 1860 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1861 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 1862 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1863 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1864 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1865 | static int |
| 1866 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1867 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1868 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1869 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1870 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1871 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1872 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1873 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1874 | } |
| 1875 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1876 | static int |
| 1877 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1878 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1879 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1880 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1881 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1882 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1883 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1884 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1885 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1886 | if (ret) |
| 1887 | return ret; |
| 1888 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1889 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1890 | mutex_unlock(&dev->struct_mutex); |
| 1891 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1892 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1893 | } |
| 1894 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1895 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 1896 | i915_ring_stop_get, i915_ring_stop_set, |
| 1897 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1898 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1899 | #define DROP_UNBOUND 0x1 |
| 1900 | #define DROP_BOUND 0x2 |
| 1901 | #define DROP_RETIRE 0x4 |
| 1902 | #define DROP_ACTIVE 0x8 |
| 1903 | #define DROP_ALL (DROP_UNBOUND | \ |
| 1904 | DROP_BOUND | \ |
| 1905 | DROP_RETIRE | \ |
| 1906 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1907 | static int |
| 1908 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1909 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1910 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1911 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1912 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1913 | } |
| 1914 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1915 | static int |
| 1916 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1917 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1918 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1919 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1920 | struct drm_i915_gem_object *obj, *next; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 1921 | struct i915_address_space *vm; |
| 1922 | struct i915_vma *vma, *x; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1923 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1924 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1925 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1926 | |
| 1927 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 1928 | * on ioctls on -EAGAIN. */ |
| 1929 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1930 | if (ret) |
| 1931 | return ret; |
| 1932 | |
| 1933 | if (val & DROP_ACTIVE) { |
| 1934 | ret = i915_gpu_idle(dev); |
| 1935 | if (ret) |
| 1936 | goto unlock; |
| 1937 | } |
| 1938 | |
| 1939 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 1940 | i915_gem_retire_requests(dev); |
| 1941 | |
| 1942 | if (val & DROP_BOUND) { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 1943 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 1944 | list_for_each_entry_safe(vma, x, &vm->inactive_list, |
| 1945 | mm_list) { |
| 1946 | if (vma->obj->pin_count) |
| 1947 | continue; |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 1948 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 1949 | ret = i915_vma_unbind(vma); |
| 1950 | if (ret) |
| 1951 | goto unlock; |
| 1952 | } |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 1953 | } |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1954 | } |
| 1955 | |
| 1956 | if (val & DROP_UNBOUND) { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1957 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 1958 | global_list) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1959 | if (obj->pages_pin_count == 0) { |
| 1960 | ret = i915_gem_object_put_pages(obj); |
| 1961 | if (ret) |
| 1962 | goto unlock; |
| 1963 | } |
| 1964 | } |
| 1965 | |
| 1966 | unlock: |
| 1967 | mutex_unlock(&dev->struct_mutex); |
| 1968 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1969 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1970 | } |
| 1971 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1972 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 1973 | i915_drop_caches_get, i915_drop_caches_set, |
| 1974 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1975 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1976 | static int |
| 1977 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1978 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1979 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1980 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1981 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1982 | |
| 1983 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1984 | return -ENODEV; |
| 1985 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1986 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1987 | if (ret) |
| 1988 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1989 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1990 | if (IS_VALLEYVIEW(dev)) |
| 1991 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 1992 | dev_priv->rps.max_delay); |
| 1993 | else |
| 1994 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1995 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1996 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1997 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1998 | } |
| 1999 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2000 | static int |
| 2001 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2002 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2003 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2004 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2005 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2006 | |
| 2007 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2008 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2009 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2010 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2011 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2012 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2013 | if (ret) |
| 2014 | return ret; |
| 2015 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2016 | /* |
| 2017 | * Turbo will still be enabled, but won't go above the set value. |
| 2018 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2019 | if (IS_VALLEYVIEW(dev)) { |
| 2020 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 2021 | dev_priv->rps.max_delay = val; |
| 2022 | gen6_set_rps(dev, val); |
| 2023 | } else { |
| 2024 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 2025 | dev_priv->rps.max_delay = val; |
| 2026 | gen6_set_rps(dev, val); |
| 2027 | } |
| 2028 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2029 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2030 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2031 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2032 | } |
| 2033 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2034 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 2035 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2036 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2037 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2038 | static int |
| 2039 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2040 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2041 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2042 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2043 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2044 | |
| 2045 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2046 | return -ENODEV; |
| 2047 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2048 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2049 | if (ret) |
| 2050 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2051 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2052 | if (IS_VALLEYVIEW(dev)) |
| 2053 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 2054 | dev_priv->rps.min_delay); |
| 2055 | else |
| 2056 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2057 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2058 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2059 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2060 | } |
| 2061 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2062 | static int |
| 2063 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2064 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2065 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2066 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2067 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2068 | |
| 2069 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2070 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2071 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2072 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2073 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2074 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2075 | if (ret) |
| 2076 | return ret; |
| 2077 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2078 | /* |
| 2079 | * Turbo will still be enabled, but won't go below the set value. |
| 2080 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2081 | if (IS_VALLEYVIEW(dev)) { |
| 2082 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 2083 | dev_priv->rps.min_delay = val; |
| 2084 | valleyview_set_rps(dev, val); |
| 2085 | } else { |
| 2086 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 2087 | dev_priv->rps.min_delay = val; |
| 2088 | gen6_set_rps(dev, val); |
| 2089 | } |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2090 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2091 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2092 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2093 | } |
| 2094 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2095 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 2096 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2097 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2098 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2099 | static int |
| 2100 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2101 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2102 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2103 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2104 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2105 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2106 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2107 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2108 | return -ENODEV; |
| 2109 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2110 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2111 | if (ret) |
| 2112 | return ret; |
| 2113 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2114 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2115 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 2116 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2117 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2118 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2119 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2120 | } |
| 2121 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2122 | static int |
| 2123 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2124 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2125 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2126 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2127 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2128 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2129 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2130 | return -ENODEV; |
| 2131 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2132 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2133 | return -EINVAL; |
| 2134 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2135 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2136 | |
| 2137 | /* Update the cache sharing policy here as well */ |
| 2138 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2139 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 2140 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 2141 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 2142 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2143 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2144 | } |
| 2145 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2146 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 2147 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 2148 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2149 | |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2150 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 2151 | * allocated we need to hook into the minor for release. */ |
| 2152 | static int |
| 2153 | drm_add_fake_info_node(struct drm_minor *minor, |
| 2154 | struct dentry *ent, |
| 2155 | const void *key) |
| 2156 | { |
| 2157 | struct drm_info_node *node; |
| 2158 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame^] | 2159 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2160 | if (node == NULL) { |
| 2161 | debugfs_remove(ent); |
| 2162 | return -ENOMEM; |
| 2163 | } |
| 2164 | |
| 2165 | node->minor = minor; |
| 2166 | node->dent = ent; |
| 2167 | node->info_ent = (void *) key; |
Marcin Slusarz | b3e067c | 2011-11-09 22:20:35 +0100 | [diff] [blame] | 2168 | |
| 2169 | mutex_lock(&minor->debugfs_lock); |
| 2170 | list_add(&node->list, &minor->debugfs_list); |
| 2171 | mutex_unlock(&minor->debugfs_lock); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2172 | |
| 2173 | return 0; |
| 2174 | } |
| 2175 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2176 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 2177 | { |
| 2178 | struct drm_device *dev = inode->i_private; |
| 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2180 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2181 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2182 | return 0; |
| 2183 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2184 | gen6_gt_force_wake_get(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2185 | |
| 2186 | return 0; |
| 2187 | } |
| 2188 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2189 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2190 | { |
| 2191 | struct drm_device *dev = inode->i_private; |
| 2192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2193 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2194 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2195 | return 0; |
| 2196 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2197 | gen6_gt_force_wake_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2198 | |
| 2199 | return 0; |
| 2200 | } |
| 2201 | |
| 2202 | static const struct file_operations i915_forcewake_fops = { |
| 2203 | .owner = THIS_MODULE, |
| 2204 | .open = i915_forcewake_open, |
| 2205 | .release = i915_forcewake_release, |
| 2206 | }; |
| 2207 | |
| 2208 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 2209 | { |
| 2210 | struct drm_device *dev = minor->dev; |
| 2211 | struct dentry *ent; |
| 2212 | |
| 2213 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2214 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2215 | root, dev, |
| 2216 | &i915_forcewake_fops); |
| 2217 | if (IS_ERR(ent)) |
| 2218 | return PTR_ERR(ent); |
| 2219 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2220 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2221 | } |
| 2222 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2223 | static int i915_debugfs_create(struct dentry *root, |
| 2224 | struct drm_minor *minor, |
| 2225 | const char *name, |
| 2226 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2227 | { |
| 2228 | struct drm_device *dev = minor->dev; |
| 2229 | struct dentry *ent; |
| 2230 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2231 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2232 | S_IRUGO | S_IWUSR, |
| 2233 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2234 | fops); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2235 | if (IS_ERR(ent)) |
| 2236 | return PTR_ERR(ent); |
| 2237 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2238 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2239 | } |
| 2240 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2241 | static struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 2242 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2243 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 2244 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 2245 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2246 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2247 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 2248 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2249 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2250 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 2251 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 2252 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2253 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2254 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 2255 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 2256 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 2257 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2258 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
| 2259 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, |
| 2260 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
| 2261 | {"i915_inttoext_table", i915_inttoext_table, 0}, |
| 2262 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2263 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 2264 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2265 | {"i915_gfxec", i915_gfxec, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 2266 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 2267 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 2268 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2269 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 2270 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 2271 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2272 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2273 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2274 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 2275 | {"i915_dpio", i915_dpio_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2276 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2277 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2278 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2279 | {"i915_pc8_status", i915_pc8_status, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2280 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2281 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2282 | |
Ville Syrjälä | 2b4bd0e | 2013-08-07 15:11:52 +0300 | [diff] [blame] | 2283 | static struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2284 | const char *name; |
| 2285 | const struct file_operations *fops; |
| 2286 | } i915_debugfs_files[] = { |
| 2287 | {"i915_wedged", &i915_wedged_fops}, |
| 2288 | {"i915_max_freq", &i915_max_freq_fops}, |
| 2289 | {"i915_min_freq", &i915_min_freq_fops}, |
| 2290 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 2291 | {"i915_ring_stop", &i915_ring_stop_fops}, |
| 2292 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 2293 | {"i915_error_state", &i915_error_state_fops}, |
| 2294 | {"i915_next_seqno", &i915_next_seqno_fops}, |
| 2295 | }; |
| 2296 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2297 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2298 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2299 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2300 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2301 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 2302 | if (ret) |
| 2303 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2304 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2305 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 2306 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2307 | i915_debugfs_files[i].name, |
| 2308 | i915_debugfs_files[i].fops); |
| 2309 | if (ret) |
| 2310 | return ret; |
| 2311 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 2312 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2313 | return drm_debugfs_create_files(i915_debugfs_list, |
| 2314 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2315 | minor->debugfs_root, minor); |
| 2316 | } |
| 2317 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2318 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2319 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2320 | int i; |
| 2321 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2322 | drm_debugfs_remove_files(i915_debugfs_list, |
| 2323 | I915_DEBUGFS_ENTRIES, minor); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2324 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 2325 | 1, minor); |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2326 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 2327 | struct drm_info_list *info_list = |
| 2328 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 2329 | |
| 2330 | drm_debugfs_remove_files(info_list, 1, minor); |
| 2331 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2332 | } |
| 2333 | |
| 2334 | #endif /* CONFIG_DEBUG_FS */ |