sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 4 | /*--- This file (main_main.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 47 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 48 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 49 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 50 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 51 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 52 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 53 | #include "libvex_guest_ppc64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 54 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 55 | #include "main_globals.h" |
| 56 | #include "main_util.h" |
| 57 | #include "host_generic_regs.h" |
| 58 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 59 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 60 | #include "host_x86_defs.h" |
| 61 | #include "host_amd64_defs.h" |
| 62 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 63 | #include "host_arm_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 64 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 65 | #include "guest_generic_bb_to_IR.h" |
| 66 | #include "guest_x86_defs.h" |
| 67 | #include "guest_amd64_defs.h" |
| 68 | #include "guest_arm_defs.h" |
| 69 | #include "guest_ppc_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 70 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 71 | |
| 72 | /* This file contains the top level interface to the library. */ |
| 73 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 74 | /* --------- fwds ... --------- */ |
| 75 | |
| 76 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
| 77 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
| 78 | |
| 79 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 80 | /* --------- Initialise the library. --------- */ |
| 81 | |
| 82 | /* Exported to library client. */ |
| 83 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 84 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 85 | { |
| 86 | vcon->iropt_verbosity = 0; |
| 87 | vcon->iropt_level = 2; |
| 88 | vcon->iropt_precise_memory_exns = False; |
| 89 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 90 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 91 | vcon->guest_chase_thresh = 10; |
| 92 | } |
| 93 | |
| 94 | |
| 95 | /* Exported to library client. */ |
| 96 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 97 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 98 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 99 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 100 | void (*failure_exit) ( void ), |
| 101 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 102 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 103 | /* debug paranoia level */ |
| 104 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 105 | /* Are we supporting valgrind checking? */ |
| 106 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 107 | /* Control ... */ |
| 108 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 109 | ) |
| 110 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 111 | /* First off, do enough minimal setup so that the following |
| 112 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 113 | vex_failure_exit = failure_exit; |
| 114 | vex_log_bytes = log_bytes; |
| 115 | |
| 116 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 117 | vassert(!vex_initdone); |
| 118 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 119 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 120 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 121 | |
| 122 | vassert(vcon->iropt_verbosity >= 0); |
| 123 | vassert(vcon->iropt_level >= 0); |
| 124 | vassert(vcon->iropt_level <= 2); |
| 125 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 126 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 127 | vassert(vcon->guest_max_insns >= 1); |
| 128 | vassert(vcon->guest_max_insns <= 100); |
| 129 | vassert(vcon->guest_chase_thresh >= 0); |
| 130 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 131 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 132 | /* Check that Vex has been built with sizes of basic types as |
| 133 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 134 | a serious configuration error and should be corrected |
| 135 | immediately. If any of these assertions fail you can fully |
| 136 | expect Vex not to work properly, if at all. */ |
| 137 | |
| 138 | vassert(1 == sizeof(UChar)); |
| 139 | vassert(1 == sizeof(Char)); |
| 140 | vassert(2 == sizeof(UShort)); |
| 141 | vassert(2 == sizeof(Short)); |
| 142 | vassert(4 == sizeof(UInt)); |
| 143 | vassert(4 == sizeof(Int)); |
| 144 | vassert(8 == sizeof(ULong)); |
| 145 | vassert(8 == sizeof(Long)); |
| 146 | vassert(4 == sizeof(Float)); |
| 147 | vassert(8 == sizeof(Double)); |
| 148 | vassert(1 == sizeof(Bool)); |
| 149 | vassert(4 == sizeof(Addr32)); |
| 150 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 151 | vassert(16 == sizeof(U128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 152 | |
| 153 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 154 | vassert(sizeof(void*) == sizeof(int*)); |
| 155 | vassert(sizeof(void*) == sizeof(HWord)); |
| 156 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 157 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 158 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 159 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 160 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 161 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 162 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 163 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 164 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 165 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | |
| 169 | /* --------- Make a translation. --------- */ |
| 170 | |
| 171 | /* Exported to library client. */ |
| 172 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 173 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 174 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 175 | /* This the bundle of functions we need to do the back-end stuff |
| 176 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 177 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 178 | HReg* available_real_regs; |
| 179 | Int n_available_real_regs; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 180 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 181 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 182 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 183 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 184 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 185 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
| 186 | void (*ppInstr) ( HInstr*, Bool ); |
| 187 | void (*ppReg) ( HReg ); |
| 188 | HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, |
| 189 | VexAbiInfo* ); |
| 190 | Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); |
| 191 | IRExpr* (*specHelper) ( HChar*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 192 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 193 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 194 | DisOneInstrFn disInstrFn; |
| 195 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 196 | VexGuestLayout* guest_layout; |
| 197 | Bool host_is_bigendian = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 198 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 199 | HInstrArray* vcode; |
| 200 | HInstrArray* rcode; |
| 201 | Int i, j, k, out_used, guest_sizeB; |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 202 | Int offB_TISTART, offB_TILEN; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 203 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 204 | IRType guest_word_type; |
| 205 | IRType host_word_type; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 206 | Bool mode64; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 207 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 208 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 209 | available_real_regs = NULL; |
| 210 | n_available_real_regs = 0; |
| 211 | isMove = NULL; |
| 212 | getRegUsage = NULL; |
| 213 | mapRegs = NULL; |
| 214 | genSpill = NULL; |
| 215 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 216 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 217 | ppInstr = NULL; |
| 218 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 219 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 220 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 221 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 222 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 223 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 224 | guest_word_type = Ity_INVALID; |
| 225 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 226 | offB_TISTART = 0; |
| 227 | offB_TILEN = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 228 | mode64 = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 229 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 230 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 231 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 232 | vassert(vex_initdone); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 233 | vexSetAllocModeTEMP_and_clear(); |
| 234 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 235 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 236 | /* First off, check that the guest and host insn sets |
| 237 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 238 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 239 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 240 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 241 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 242 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 243 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 244 | &available_real_regs ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 245 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 246 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 247 | getRegUsage_X86Instr; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 248 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 249 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 250 | genSpill_X86; |
| 251 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 252 | genReload_X86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 253 | directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; |
| 254 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
| 255 | ppReg = (void(*)(HReg)) ppHRegX86; |
| 256 | iselSB = iselSB_X86; |
| 257 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 258 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 259 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 260 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 261 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 262 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 263 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 264 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 265 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 266 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 267 | &available_real_regs ); |
| 268 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 269 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 270 | getRegUsage_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 271 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 272 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 273 | genSpill_AMD64; |
| 274 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 275 | genReload_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 276 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 277 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 278 | iselSB = iselSB_AMD64; |
sewardj | 0528bb5 | 2005-12-15 15:45:20 +0000 | [diff] [blame] | 279 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 280 | host_is_bigendian = False; |
| 281 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 282 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 283 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 284 | break; |
| 285 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 286 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 287 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 288 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 289 | &available_real_regs, mode64 ); |
| 290 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 291 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 292 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 293 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 294 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 295 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 296 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 297 | iselSB = iselSB_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 298 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 299 | host_is_bigendian = True; |
| 300 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 301 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 302 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 303 | break; |
| 304 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 305 | case VexArchPPC64: |
| 306 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 307 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 308 | &available_real_regs, mode64 ); |
| 309 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 310 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 311 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 312 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 313 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 314 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 315 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 316 | iselSB = iselSB_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 317 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 318 | host_is_bigendian = True; |
| 319 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 320 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 321 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 322 | break; |
| 323 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 324 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 325 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 326 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 327 | &available_real_regs ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame^] | 328 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; |
| 329 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; |
| 330 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; |
| 331 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; |
| 332 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; |
| 333 | ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; |
| 334 | ppReg = (void(*)(HReg)) ppHRegARM; |
| 335 | iselSB = iselSB_ARM; |
| 336 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 337 | host_is_bigendian = False; |
| 338 | host_word_type = Ity_I32; |
| 339 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
| 340 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
| 341 | break; |
| 342 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 343 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 344 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 345 | } |
| 346 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 347 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 348 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 349 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 350 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 351 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 352 | disInstrFn = disInstr_X86; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 353 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 354 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 355 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 356 | guest_layout = &x86guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 357 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 358 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 359 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 360 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 361 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); |
| 362 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
| 363 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 364 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 365 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 366 | case VexArchAMD64: |
| 367 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 368 | disInstrFn = disInstr_AMD64; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 369 | specHelper = guest_amd64_spechelper; |
| 370 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 371 | guest_word_type = Ity_I64; |
| 372 | guest_layout = &amd64guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 373 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 374 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 375 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 376 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 377 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 378 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
| 379 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 380 | break; |
| 381 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 382 | case VexArchPPC32: |
| 383 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 384 | disInstrFn = disInstr_PPC; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 385 | specHelper = guest_ppc32_spechelper; |
| 386 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 387 | guest_word_type = Ity_I32; |
| 388 | guest_layout = &ppc32Guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 389 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 390 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 391 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 392 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 393 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 394 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
| 395 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 396 | break; |
| 397 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 398 | case VexArchPPC64: |
| 399 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 400 | disInstrFn = disInstr_PPC; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 401 | specHelper = guest_ppc64_spechelper; |
| 402 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 403 | guest_word_type = Ity_I64; |
| 404 | guest_layout = &ppc64Guest_layout; |
| 405 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 406 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 407 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 408 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 409 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
| 410 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 411 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 412 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 413 | break; |
| 414 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 415 | case VexArchARM: |
| 416 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 417 | disInstrFn = disInstr_ARM; |
| 418 | specHelper = guest_arm_spechelper; |
| 419 | guest_sizeB = sizeof(VexGuestARMState); |
| 420 | guest_word_type = Ity_I32; |
| 421 | guest_layout = &armGuest_layout; |
| 422 | offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); |
| 423 | offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); |
| 424 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
| 425 | vassert(0 == sizeof(VexGuestARMState) % 16); |
| 426 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); |
| 427 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); |
| 428 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 429 | break; |
| 430 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 431 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 432 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 433 | } |
| 434 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 435 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 436 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 437 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 438 | we are simulating one flavour of an architecture a different |
| 439 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 440 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 441 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 442 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 443 | vexAllocSanityCheck(); |
| 444 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 445 | if (vex_traceflags & VEX_TRACE_FE) |
| 446 | vex_printf("\n------------------------" |
| 447 | " Front end " |
| 448 | "------------------------\n\n"); |
| 449 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 450 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 451 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 452 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 453 | vta->guest_bytes, |
| 454 | vta->guest_bytes_addr, |
| 455 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 456 | host_is_bigendian, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 457 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 458 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 459 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 460 | guest_word_type, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 461 | vta->do_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 462 | vta->preamble_function, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 463 | offB_TISTART, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 464 | offB_TILEN ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 465 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 466 | vexAllocSanityCheck(); |
| 467 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 468 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 469 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 470 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 471 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 472 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 473 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 474 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 475 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 476 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 477 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 478 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 479 | } |
| 480 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 481 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 482 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 483 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 484 | vex_printf("can't show code due to extents > 1\n"); |
| 485 | } else { |
| 486 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 487 | UChar* p = (UChar*)vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 488 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 489 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 490 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 491 | guest_bytes_read ); |
| 492 | for (i = 0; i < guest_bytes_read; i++) { |
| 493 | UInt b = (UInt)p[i]; |
| 494 | vex_printf(" %02x", b ); |
| 495 | sum = (sum << 1) ^ b; |
| 496 | } |
| 497 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 498 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 502 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 503 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 504 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 505 | vexAllocSanityCheck(); |
| 506 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 507 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 508 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 509 | vta->guest_bytes_addr ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 510 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 511 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 512 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 513 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 514 | vex_printf("\n------------------------" |
| 515 | " After pre-instr IR optimisation " |
| 516 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 517 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 518 | vex_printf("\n"); |
| 519 | } |
| 520 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 521 | vexAllocSanityCheck(); |
| 522 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 523 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 524 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 525 | irsb = vta->instrument1(vta->callback_opaque, |
| 526 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 527 | vta->guest_extents, |
| 528 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 529 | vexAllocSanityCheck(); |
| 530 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 531 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 532 | irsb = vta->instrument2(vta->callback_opaque, |
| 533 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 534 | vta->guest_extents, |
| 535 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 536 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 537 | if (vex_traceflags & VEX_TRACE_INST) { |
| 538 | vex_printf("\n------------------------" |
| 539 | " After instrumentation " |
| 540 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 541 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 542 | vex_printf("\n"); |
| 543 | } |
| 544 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 545 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 546 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 547 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 548 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 549 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 550 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 551 | do_deadcode_BB( irsb ); |
| 552 | irsb = cprop_BB( irsb ); |
| 553 | do_deadcode_BB( irsb ); |
| 554 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 555 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 556 | } |
| 557 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 558 | vexAllocSanityCheck(); |
| 559 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 560 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 561 | vex_printf("\n------------------------" |
| 562 | " After post-instr IR optimisation " |
| 563 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 564 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 565 | vex_printf("\n"); |
| 566 | } |
| 567 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 568 | /* Turn it into virtual-registerised code. Build trees -- this |
| 569 | also throws away any dead bindings. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 570 | ado_treebuild_BB( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 571 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 572 | if (vta->finaltidy) { |
| 573 | irsb = vta->finaltidy(irsb); |
| 574 | } |
| 575 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 576 | vexAllocSanityCheck(); |
| 577 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 578 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 579 | vex_printf("\n------------------------" |
| 580 | " After tree-building " |
| 581 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 582 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 583 | vex_printf("\n"); |
| 584 | } |
| 585 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 586 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 587 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 588 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 589 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 590 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 591 | vex_printf("\n------------------------" |
| 592 | " Instruction selection " |
| 593 | "------------------------\n"); |
| 594 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 595 | vcode = iselSB ( irsb, vta->arch_host, &vta->archinfo_host, |
| 596 | &vta->abiinfo_both ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 597 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 598 | vexAllocSanityCheck(); |
| 599 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 600 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 601 | vex_printf("\n"); |
| 602 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 603 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 604 | for (i = 0; i < vcode->arr_used; i++) { |
| 605 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 606 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 607 | vex_printf("\n"); |
| 608 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 609 | vex_printf("\n"); |
| 610 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 611 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 612 | /* Register allocate. */ |
| 613 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 614 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 615 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 616 | genSpill, genReload, directReload, |
| 617 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 618 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 619 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 620 | vexAllocSanityCheck(); |
| 621 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 622 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 623 | vex_printf("\n------------------------" |
| 624 | " Register-allocated code " |
| 625 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 626 | for (i = 0; i < rcode->arr_used; i++) { |
| 627 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 628 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 629 | vex_printf("\n"); |
| 630 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 631 | vex_printf("\n"); |
| 632 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 633 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 634 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 635 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 636 | /* end HACK */ |
| 637 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 638 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 639 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 640 | vex_printf("\n------------------------" |
| 641 | " Assembly " |
| 642 | "------------------------\n\n"); |
| 643 | } |
| 644 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 645 | out_used = 0; /* tracks along the host_bytes array */ |
| 646 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 647 | if (vex_traceflags & VEX_TRACE_ASM) { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 648 | ppInstr(rcode->arr[i], mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 649 | vex_printf("\n"); |
| 650 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 651 | j = (*emit)( insn_bytes, 32, rcode->arr[i], mode64, vta->dispatch ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 652 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 653 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 654 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 655 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 656 | else |
| 657 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 658 | vex_printf("\n\n"); |
| 659 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 660 | if (out_used + j > vta->host_bytes_size) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 661 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 662 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 663 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 664 | } |
| 665 | for (k = 0; k < j; k++) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 666 | vta->host_bytes[out_used] = insn_bytes[k]; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 667 | out_used++; |
| 668 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 669 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 670 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 671 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 672 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 673 | vexAllocSanityCheck(); |
| 674 | |
| 675 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 676 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 677 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 678 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 682 | /* --------- Emulation warnings. --------- */ |
| 683 | |
| 684 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 685 | { |
| 686 | switch (ew) { |
| 687 | case EmWarn_NONE: |
| 688 | return "none"; |
| 689 | case EmWarn_X86_x87exns: |
| 690 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 691 | case EmWarn_X86_x87precision: |
| 692 | return "Selection of non-80-bit x87 FP precision"; |
| 693 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 694 | return "Unmasking SSE FP exceptions"; |
| 695 | case EmWarn_X86_fz: |
| 696 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 697 | case EmWarn_X86_daz: |
| 698 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 699 | case EmWarn_X86_acFlag: |
| 700 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 701 | case EmWarn_PPCexns: |
| 702 | return "Unmasking PPC32/64 FP exceptions"; |
| 703 | case EmWarn_PPC64_redir_overflow: |
| 704 | return "PPC64 function redirection stack overflow"; |
| 705 | case EmWarn_PPC64_redir_underflow: |
| 706 | return "PPC64 function redirection stack underflow"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 707 | default: |
| 708 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 709 | } |
| 710 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 711 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 712 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 713 | |
| 714 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 715 | { |
| 716 | switch (arch) { |
| 717 | case VexArch_INVALID: return "INVALID"; |
| 718 | case VexArchX86: return "X86"; |
| 719 | case VexArchAMD64: return "AMD64"; |
| 720 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 721 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 722 | case VexArchPPC64: return "PPC64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 723 | default: return "VexArch???"; |
| 724 | } |
| 725 | } |
| 726 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 727 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 728 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 729 | HChar* str = show_hwcaps(arch,hwcaps); |
| 730 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 731 | } |
| 732 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 733 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 734 | /* Write default settings info *vai. */ |
| 735 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 736 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 737 | vai->hwcaps = 0; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 738 | vai->ppc_cache_line_szB = 0; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 739 | } |
| 740 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 741 | /* Write default settings info *vbi. */ |
| 742 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 743 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 744 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 745 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 746 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 747 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 748 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
| 749 | vbi->guest_ppc_sc_continues_at_LR = False; |
| 750 | vbi->host_ppc_calls_use_fndescrs = False; |
| 751 | vbi->host_ppc32_regalign_int64_args = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 752 | } |
| 753 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 754 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 755 | /* Return a string showing the hwcaps in a nice way. The string will |
| 756 | be NULL for invalid combinations of flags, so these functions also |
| 757 | serve as a way to validate hwcaps values. */ |
| 758 | |
| 759 | static HChar* show_hwcaps_x86 ( UInt hwcaps ) |
| 760 | { |
| 761 | /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */ |
| 762 | if (hwcaps == 0) |
| 763 | return "x86-sse0"; |
| 764 | if (hwcaps == VEX_HWCAPS_X86_SSE1) |
| 765 | return "x86-sse1"; |
| 766 | if (hwcaps == (VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2)) |
| 767 | return "x86-sse1-sse2"; |
| 768 | if (hwcaps == (VEX_HWCAPS_X86_SSE1 |
| 769 | | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3)) |
| 770 | return "x86-sse1-sse2-sse3"; |
| 771 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 772 | return NULL; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 773 | } |
| 774 | |
| 775 | static HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
| 776 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 777 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 778 | don't expect to come across anything which can do SSE3 but can't |
| 779 | do CX16. Still, we can handle that case. */ |
| 780 | const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3; |
| 781 | const UInt CX16 = VEX_HWCAPS_AMD64_CX16; |
| 782 | UInt c = hwcaps; |
| 783 | if (c == 0) return "amd64-sse2"; |
| 784 | if (c == SSE3) return "amd64-sse3"; |
| 785 | if (c == CX16) return "amd64-sse2-cx16"; |
| 786 | if (c == (SSE3|CX16)) return "amd64-sse3-cx16"; |
| 787 | return NULL; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 788 | } |
| 789 | |
| 790 | static HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
| 791 | { |
| 792 | /* Monotonic with complications. Basically V > F > baseline, |
| 793 | but once you have F then you can have FX or GX too. */ |
| 794 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 795 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 796 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 797 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
| 798 | UInt c = hwcaps; |
| 799 | if (c == 0) return "ppc32-int"; |
| 800 | if (c == F) return "ppc32-int-flt"; |
| 801 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 802 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 803 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 804 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 805 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 806 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 807 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
| 808 | return NULL; |
| 809 | } |
| 810 | |
| 811 | static HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
| 812 | { |
| 813 | /* Monotonic with complications. Basically V > baseline(==F), |
| 814 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 815 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 816 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 817 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 818 | UInt c = hwcaps; |
| 819 | if (c == 0) return "ppc64-int-flt"; |
| 820 | if (c == FX) return "ppc64-int-flt-FX"; |
| 821 | if (c == GX) return "ppc64-int-flt-GX"; |
| 822 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 823 | if (c == V) return "ppc64-int-flt-vmx"; |
| 824 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 825 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 826 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
| 827 | return NULL; |
| 828 | } |
| 829 | |
| 830 | static HChar* show_hwcaps_arm ( UInt hwcaps ) |
| 831 | { |
| 832 | if (hwcaps == 0) return "arm-baseline"; |
| 833 | return NULL; |
| 834 | } |
| 835 | |
| 836 | /* ---- */ |
| 837 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
| 838 | { |
| 839 | switch (arch) { |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 840 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 841 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 842 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 843 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 844 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 845 | default: return NULL; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 850 | { |
| 851 | return show_hwcaps(arch,hwcaps) != NULL; |
| 852 | } |
| 853 | |
| 854 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 855 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 856 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 857 | /*---------------------------------------------------------------*/ |