blob: ef11bc6df2ac930ebc0bcd6ff652e1745102a5a4 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070035#include "fb.h"
Chia-I Wu09142132014-08-11 15:42:55 +080036
Chia-I Wu3c3edc02014-09-09 10:32:59 +080037/**
38 * Free all resources used by a writer. Note that the initial size is not
39 * reset.
40 */
41static void cmd_writer_reset(struct intel_cmd *cmd,
42 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080043{
Chia-I Wu68f319d2014-09-09 09:43:21 +080044 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080045
Chia-I Wu3c3edc02014-09-09 10:32:59 +080046 if (writer->ptr) {
47 intel_bo_unmap(writer->bo);
48 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080049 }
50
Chia-I Wu3c3edc02014-09-09 10:32:59 +080051 if (writer->bo) {
52 intel_bo_unreference(writer->bo);
53 writer->bo = NULL;
54 }
55
Chia-I Wue24c3292014-08-21 14:05:23 +080056 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080057
58 if (writer->items) {
59 icd_free(writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060060 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080061 writer->item_alloc = 0;
62 writer->item_used = 0;
63 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080064}
65
66/**
67 * Discard everything written so far.
68 */
69static void cmd_writer_discard(struct intel_cmd *cmd,
70 enum intel_cmd_writer_type which)
71{
72 struct intel_cmd_writer *writer = &cmd->writers[which];
73
74 intel_bo_truncate_relocs(writer->bo, 0);
75 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080076 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080077}
78
79static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
80 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +080081 XGL_SIZE size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080082{
83 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
84 [INTEL_CMD_WRITER_BATCH] = "batch",
85 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
86 };
87
Chia-I Wu72292b72014-09-09 10:48:33 +080088 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080089}
90
91/**
92 * Allocate and map the buffer for writing.
93 */
94static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
95 enum intel_cmd_writer_type which)
96{
97 struct intel_cmd_writer *writer = &cmd->writers[which];
98 struct intel_bo *bo;
99
100 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
101 if (bo) {
102 if (writer->bo)
103 intel_bo_unreference(writer->bo);
104 writer->bo = bo;
105 } else if (writer->bo) {
106 /* reuse the old bo */
107 cmd_writer_discard(cmd, which);
108 } else {
109 return XGL_ERROR_OUT_OF_GPU_MEMORY;
110 }
111
112 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800113 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800114
115 writer->ptr = intel_bo_map(writer->bo, true);
116 if (!writer->ptr)
117 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800118
119 return XGL_SUCCESS;
120}
121
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800122/**
123 * Unmap the buffer for submission.
124 */
125static void cmd_writer_unmap(struct intel_cmd *cmd,
126 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800127{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800128 struct intel_cmd_writer *writer = &cmd->writers[which];
129
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800130 intel_bo_unmap(writer->bo);
131 writer->ptr = NULL;
132}
133
134/**
135 * Grow a mapped writer to at least \p new_size. Failures are handled
136 * silently.
137 */
138void cmd_writer_grow(struct intel_cmd *cmd,
139 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800140 XGL_SIZE new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800141{
142 struct intel_cmd_writer *writer = &cmd->writers[which];
143 struct intel_bo *new_bo;
144 void *new_ptr;
145
146 if (new_size < writer->size << 1)
147 new_size = writer->size << 1;
148 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800149 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800150
151 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
152 if (!new_bo) {
153 cmd_writer_discard(cmd, which);
154 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
155 return;
156 }
157
158 /* map and copy the data over */
159 new_ptr = intel_bo_map(new_bo, true);
160 if (!new_ptr) {
161 intel_bo_unreference(new_bo);
162 cmd_writer_discard(cmd, which);
163 cmd->result = XGL_ERROR_UNKNOWN;
164 return;
165 }
166
Chia-I Wu72292b72014-09-09 10:48:33 +0800167 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800168
169 intel_bo_unmap(writer->bo);
170 intel_bo_unreference(writer->bo);
171
172 writer->size = new_size;
173 writer->bo = new_bo;
174 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800175}
176
Chia-I Wu00b51a82014-09-09 12:07:37 +0800177/**
178 * Record an item for later decoding.
179 */
180void cmd_writer_record(struct intel_cmd *cmd,
181 enum intel_cmd_writer_type which,
182 enum intel_cmd_item_type type,
183 XGL_SIZE offset, XGL_SIZE size)
184{
185 struct intel_cmd_writer *writer = &cmd->writers[which];
186 struct intel_cmd_item *item;
187
188 if (writer->item_used == writer->item_alloc) {
189 const unsigned new_alloc = (writer->item_alloc) ?
190 writer->item_alloc << 1 : 256;
191 struct intel_cmd_item *items;
192
193 items = icd_alloc(sizeof(writer->items[0]) * new_alloc,
194 0, XGL_SYSTEM_ALLOC_DEBUG);
195 if (!items) {
196 writer->item_used = 0;
197 cmd->result = XGL_ERROR_OUT_OF_MEMORY;
198 return;
199 }
200
201 memcpy(items, writer->items,
202 sizeof(writer->items[0]) * writer->item_alloc);
203
204 icd_free(writer->items);
205
206 writer->items = items;
207 writer->item_alloc = new_alloc;
208 }
209
210 item = &writer->items[writer->item_used++];
211 item->type = type;
212 item->offset = offset;
213 item->size = size;
214}
215
Chia-I Wu5e25c272014-08-21 20:19:12 +0800216static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800217 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800218 XGL_SIZE offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800219{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800220 struct intel_cmd_writer *writer = &cmd->writers[which];
221
Chia-I Wu72292b72014-09-09 10:48:33 +0800222 assert(offset + sizeof(val) <= writer->used);
223 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800224}
225
Chia-I Wu730e5362014-08-19 12:15:09 +0800226static void cmd_reset(struct intel_cmd *cmd)
227{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800228 XGL_UINT i;
229
230 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
231 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800232
Chia-I Wua57761b2014-10-14 14:27:44 +0800233 if (cmd->bind.shader_cache.entries)
234 icd_free(cmd->bind.shader_cache.entries);
235
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700236 icd_free(cmd->bind.render_pass); // TODO remove once CmdBindAttachment is removed
237
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800238 memset(&cmd->bind, 0, sizeof(cmd->bind));
239
Chia-I Wu343b1372014-08-20 16:39:20 +0800240 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800241 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800242}
243
244static void cmd_destroy(struct intel_obj *obj)
245{
246 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
247
248 intel_cmd_destroy(cmd);
249}
250
251XGL_RESULT intel_cmd_create(struct intel_dev *dev,
252 const XGL_CMD_BUFFER_CREATE_INFO *info,
253 struct intel_cmd **cmd_ret)
254{
Chia-I Wu63883292014-08-25 13:50:26 +0800255 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800256 struct intel_cmd *cmd;
257
Chia-I Wu63883292014-08-25 13:50:26 +0800258 switch (info->queueType) {
259 case XGL_QUEUE_TYPE_GRAPHICS:
260 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
261 break;
262 case XGL_QUEUE_TYPE_COMPUTE:
263 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
264 break;
265 case XGL_QUEUE_TYPE_DMA:
266 pipeline_select = -1;
267 break;
268 default:
269 return XGL_ERROR_INVALID_VALUE;
270 break;
271 }
272
Chia-I Wu730e5362014-08-19 12:15:09 +0800273 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
274 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
275 if (!cmd)
276 return XGL_ERROR_OUT_OF_MEMORY;
277
278 cmd->obj.destroy = cmd_destroy;
279
280 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800281 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800282 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800283
Chia-I Wue0cdd832014-08-25 12:38:56 +0800284 /*
285 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
286 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
287 * and end offsets, for each referenced memories.
288 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800289 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
290 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
291 4096, XGL_SYSTEM_ALLOC_INTERNAL);
292 if (!cmd->relocs) {
293 intel_cmd_destroy(cmd);
294 return XGL_ERROR_OUT_OF_MEMORY;
295 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800296
297 *cmd_ret = cmd;
298
299 return XGL_SUCCESS;
300}
301
302void intel_cmd_destroy(struct intel_cmd *cmd)
303{
304 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800305
306 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800307 intel_base_destroy(&cmd->obj.base);
308}
309
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700310XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, const XGL_CMD_BUFFER_BEGIN_INFO* info)
Chia-I Wu730e5362014-08-19 12:15:09 +0800311{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800312 XGL_RESULT ret;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800313 XGL_UINT i;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700314 XGL_FLAGS flags = 0;
315 XGL_CMD_BUFFER_BEGIN_INFO* next= (XGL_CMD_BUFFER_BEGIN_INFO*) info;
316 XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *ginfo;
Chia-I Wu730e5362014-08-19 12:15:09 +0800317
318 cmd_reset(cmd);
319
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700320 while (next != NULL) {
321 switch (next->sType) {
322 case XGL_STRUCTURE_TYPE_CMD_BUFFER_BEGIN_INFO:
323 flags = next->flags;
324 break;
325 case XGL_STRUCTURE_TYPE_CMD_BUFFER_GRAPHICS_BEGIN_INFO:
326 ginfo = (XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *) next;
327 cmd->bind.render_pass = (struct intel_render_pass *)
328 ginfo->renderPass;
329 break;
330 default:
331 return XGL_ERROR_INVALID_VALUE;
332 break;
333 }
334 next = (XGL_CMD_BUFFER_BEGIN_INFO*) next->pNext;
335 }
336
337 if (cmd->bind.render_pass == NULL) // TODO remove once CmmdBindAttachment is removed
338 cmd->bind.render_pass = icd_alloc(sizeof(struct intel_render_pass), 0,
339 XGL_SYSTEM_ALLOC_INTERNAL);
340
Chia-I Wu24565ee2014-08-21 20:24:31 +0800341 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800342 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800343 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800344 }
345
Chia-I Wu68f319d2014-09-09 09:43:21 +0800346 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800347 const XGL_UINT size = cmd->dev->gpu->max_batch_buffer_size / 2;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800348 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800349
350 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
351 divider *= 4;
352
Chia-I Wu68f319d2014-09-09 09:43:21 +0800353 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
354 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
Chia-I Wu72292b72014-09-09 10:48:33 +0800355 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800356 }
357
Chia-I Wu68f319d2014-09-09 09:43:21 +0800358 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800359 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800360 if (ret != XGL_SUCCESS) {
361 cmd_reset(cmd);
362 return ret;
363 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800364 }
365
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800366 cmd_batch_begin(cmd);
367
Chia-I Wu24565ee2014-08-21 20:24:31 +0800368 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800369}
370
371XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
372{
373 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800374 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800375
Chia-I Wub8762122014-12-01 22:51:03 +0800376 /* no matching intel_cmd_begin() */
377 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].ptr)
378 return XGL_ERROR_INCOMPLETE_COMMAND_BUFFER;
379
Chia-I Wue24c3292014-08-21 14:05:23 +0800380 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800381
Chia-I Wu343b1372014-08-20 16:39:20 +0800382 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800383 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800384 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800385 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800386 uint64_t presumed_offset;
387 int err;
388
Chia-I Wud7d1e482014-10-18 13:25:10 +0800389 /*
390 * Once a bo is used as a reloc target, libdrm_intel disallows more
391 * relocs to be added to it. That may happen when
392 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
393 * in another pass.
394 */
395 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
396 continue;
397
Chia-I Wu72292b72014-09-09 10:48:33 +0800398 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800399 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800400 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800401 if (err) {
402 cmd->result = XGL_ERROR_UNKNOWN;
403 break;
404 }
405
406 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800407 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800408 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800409 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800410 for (i = 0; i < cmd->reloc_used; i++) {
411 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
412 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
413 uint64_t presumed_offset;
414 int err;
415
416 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
417 continue;
418
419 err = intel_bo_add_reloc(writer->bo, reloc->offset,
420 cmd->writers[reloc->target].bo, reloc->target_offset,
421 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
422 &presumed_offset);
423 if (err) {
424 cmd->result = XGL_ERROR_UNKNOWN;
425 break;
426 }
427
428 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
429 cmd_writer_patch(cmd, reloc->which, reloc->offset,
430 (uint32_t) presumed_offset);
431 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800432
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800433 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
434 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800435
Chia-I Wu04966702014-08-20 15:05:03 +0800436 if (cmd->result != XGL_SUCCESS)
437 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800438
Chia-I Wu68f319d2014-09-09 09:43:21 +0800439 if (intel_winsys_can_submit_bo(winsys,
440 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800441 return XGL_SUCCESS;
442 else
443 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
444}
445
Chia-I Wu96177272015-01-03 15:27:41 +0800446ICD_EXPORT XGL_RESULT XGLAPI xglCreateCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800447 XGL_DEVICE device,
448 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
449 XGL_CMD_BUFFER* pCmdBuffer)
450{
Chia-I Wu730e5362014-08-19 12:15:09 +0800451 struct intel_dev *dev = intel_dev(device);
452
453 return intel_cmd_create(dev, pCreateInfo,
454 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800455}
456
Chia-I Wu96177272015-01-03 15:27:41 +0800457ICD_EXPORT XGL_RESULT XGLAPI xglBeginCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800458 XGL_CMD_BUFFER cmdBuffer,
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700459 const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu09142132014-08-11 15:42:55 +0800460{
Chia-I Wu730e5362014-08-19 12:15:09 +0800461 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
462
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700463 return intel_cmd_begin(cmd, info);
Chia-I Wu09142132014-08-11 15:42:55 +0800464}
465
Chia-I Wu96177272015-01-03 15:27:41 +0800466ICD_EXPORT XGL_RESULT XGLAPI xglEndCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800467 XGL_CMD_BUFFER cmdBuffer)
468{
Chia-I Wu730e5362014-08-19 12:15:09 +0800469 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
470
471 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800472}
473
Chia-I Wu96177272015-01-03 15:27:41 +0800474ICD_EXPORT XGL_RESULT XGLAPI xglResetCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800475 XGL_CMD_BUFFER cmdBuffer)
476{
Chia-I Wu730e5362014-08-19 12:15:09 +0800477 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
478
479 cmd_reset(cmd);
480
481 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800482}
483
Chia-I Wu96177272015-01-03 15:27:41 +0800484ICD_EXPORT XGL_VOID XGLAPI xglCmdMemoryAtomic(
Chia-I Wu09142132014-08-11 15:42:55 +0800485 XGL_CMD_BUFFER cmdBuffer,
486 XGL_GPU_MEMORY destMem,
487 XGL_GPU_SIZE destOffset,
488 XGL_UINT64 srcData,
489 XGL_ATOMIC_OP atomicOp)
490{
491}
492
Chia-I Wu96177272015-01-03 15:27:41 +0800493ICD_EXPORT XGL_VOID XGLAPI xglCmdInitAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800494 XGL_CMD_BUFFER cmdBuffer,
495 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
496 XGL_UINT startCounter,
497 XGL_UINT counterCount,
498 const XGL_UINT32* pData)
499{
500}
501
Chia-I Wu96177272015-01-03 15:27:41 +0800502ICD_EXPORT XGL_VOID XGLAPI xglCmdLoadAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800503 XGL_CMD_BUFFER cmdBuffer,
504 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
505 XGL_UINT startCounter,
506 XGL_UINT counterCount,
507 XGL_GPU_MEMORY srcMem,
508 XGL_GPU_SIZE srcOffset)
509{
510}
511
Chia-I Wu96177272015-01-03 15:27:41 +0800512ICD_EXPORT XGL_VOID XGLAPI xglCmdSaveAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800513 XGL_CMD_BUFFER cmdBuffer,
514 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
515 XGL_UINT startCounter,
516 XGL_UINT counterCount,
517 XGL_GPU_MEMORY destMem,
518 XGL_GPU_SIZE destOffset)
519{
520}
521
Chia-I Wu96177272015-01-03 15:27:41 +0800522ICD_EXPORT XGL_VOID XGLAPI xglCmdDbgMarkerBegin(
Chia-I Wu09142132014-08-11 15:42:55 +0800523 XGL_CMD_BUFFER cmdBuffer,
524 const XGL_CHAR* pMarker)
525{
526}
527
Chia-I Wu96177272015-01-03 15:27:41 +0800528ICD_EXPORT XGL_VOID XGLAPI xglCmdDbgMarkerEnd(
Chia-I Wu09142132014-08-11 15:42:55 +0800529 XGL_CMD_BUFFER cmdBuffer)
530{
531}