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gerrit-public.fairphone.software / toolchain / llvm-project / fbe3132f6768208e13d8ebe18b60b14e513ca8f2 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: ac6c232486e779ae2e85bbbd8db8bb58c98cbd8a [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]70def BWDivider : ProcResource<1>;
71// FP division and sqrt on port 0.
72def BWFPDivider : ProcResource<1>;
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]73
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]74// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75// cycles after the memory operand.
76def : ReadAdvance<ReadAfterLd, 5>;
77
78// Many SchedWrites are defined in pairs with and without a folded load.
79// Instructions with folded loads are usually micro-fused, so they only appear
80// as two micro-ops when queued in the reservation station.
81// This multiclass defines the resource usage for variants with and without
82// folded loads.
83multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]84 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]85 int Lat, list<int> Res = [1], int UOps = 1,
86 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]87 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]88 def : WriteRes<SchedRW, ExePorts> {
89 let Latency = Lat;
90 let ResourceCycles = Res;
91 let NumMicroOps = UOps;
92 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]93
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]94 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
95 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]97 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]98 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]99 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]100 }
101}
102
103// A folded store needs a cycle on port 4 for the store data, but it does not
104// need an extra port 2/3 cycle to recompute the address.
105def : WriteRes<WriteRMW, [BWPort4]>;
106
107// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]108defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
109defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
110defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000[diff] [blame]111defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]112def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]113
114def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
115
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]116// Bit counts.
117defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
118defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
119defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
120defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
121
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]122// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]123defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]124
Craig Topper89310f52018-03-29 20:41:39 +0000[diff] [blame]125// BMI1 BEXTR, BMI2 BZHI
126defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
127defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
128
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]129// Loads, stores, and moves, not folded with other operations.
130def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
131def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
132def : WriteRes<WriteMove, [BWPort0156]>;
133
134// Idioms that clear a register, like xorps %xmm0, %xmm0.
135// These can often bypass execution ports completely.
136def : WriteRes<WriteZero, []>;
137
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]138// Treat misc copies as a move.
139def : InstRW<[WriteMove], (instrs COPY)>;
140
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]141// Branches don't produce values, so they have no latency, but they still
142// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]143defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]144
145// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]146def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
147def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
148def : WriteRes<WriteFMove, [BWPort5]>;
149
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]150defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
151defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
152defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
153defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
154defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
155defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
156defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
157defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
158defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
159defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]160
161// FMA Scheduling helper class.
162// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
163
164// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]165def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
166def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
167def : WriteRes<WriteVecMove, [BWPort015]>;
168
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]169defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
170defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
171defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
Craig Topper13a0f832018-03-31 04:54:32 +0000[diff] [blame]172defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]173defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
174defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
175defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
176defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]177
178// Vector bitwise operations.
179// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]180defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]181
182// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]183defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
184defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
185defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]186
187// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]188
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]189// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]190def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]191 let Latency = 11;
192 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]193 let ResourceCycles = [3];
194}
195def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]196 let Latency = 16;
197 let NumMicroOps = 4;
198 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]199}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]200
201// Packed Compare Explicit Length Strings, Return Mask
202def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
203 let Latency = 19;
204 let NumMicroOps = 9;
205 let ResourceCycles = [4,3,1,1];
206}
207def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
208 let Latency = 24;
209 let NumMicroOps = 10;
210 let ResourceCycles = [4,3,1,1,1];
211}
212
213// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]214def : WriteRes<WritePCmpIStrI, [BWPort0]> {
215 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]216 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]217 let ResourceCycles = [3];
218}
219def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]220 let Latency = 16;
221 let NumMicroOps = 4;
222 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]223}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]224
225// Packed Compare Explicit Length Strings, Return Index
226def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
227 let Latency = 18;
228 let NumMicroOps = 8;
229 let ResourceCycles = [4,3,1];
230}
231def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
232 let Latency = 23;
233 let NumMicroOps = 9;
234 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]235}
236
Simon Pilgrima2f26782018-03-27 20:38:54 +0000[diff] [blame]237// MOVMSK Instructions.
238def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
239def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
240def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
241
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]242// AES instructions.
243def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
244 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]245 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]246 let ResourceCycles = [1];
247}
248def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]249 let Latency = 12;
250 let NumMicroOps = 2;
251 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]252}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]253
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]254def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
255 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]256 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]257 let ResourceCycles = [2];
258}
259def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]260 let Latency = 19;
261 let NumMicroOps = 3;
262 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]263}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]264
265def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
266 let Latency = 29;
267 let NumMicroOps = 11;
268 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]269}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]270def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
271 let Latency = 33;
272 let NumMicroOps = 11;
273 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]274}
275
276// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]277defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]278
279// Catch-all for expensive system instructions.
280def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
281
282// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]283defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
284defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
285defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]286
287// Old microcoded instructions that nobody use.
288def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
289
290// Fence instructions.
291def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
292
293// Nop, not very useful expect it provides a model for nops!
294def : WriteRes<WriteNop, []>;
295
296////////////////////////////////////////////////////////////////////////////////
297// Horizontal add/sub instructions.
298////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]299
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]300defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
301defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]302
303// Remaining instrs.
304
305def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
306 let Latency = 1;
307 let NumMicroOps = 1;
308 let ResourceCycles = [1];
309}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]310def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
311 "MMX_MOVD64grr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]312 "MMX_PSLLDri",
313 "MMX_PSLLDrr",
314 "MMX_PSLLQri",
315 "MMX_PSLLQrr",
316 "MMX_PSLLWri",
317 "MMX_PSLLWrr",
318 "MMX_PSRADri",
319 "MMX_PSRADrr",
320 "MMX_PSRAWri",
321 "MMX_PSRAWrr",
322 "MMX_PSRLDri",
323 "MMX_PSRLDrr",
324 "MMX_PSRLQri",
325 "MMX_PSRLQrr",
326 "MMX_PSRLWri",
327 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]328 "(V?)MOVPDI2DIrr",
329 "(V?)MOVPQIto64rr",
330 "(V?)PSLLD(Y?)ri",
331 "(V?)PSLLQ(Y?)ri",
332 "VPSLLVQ(Y?)rr",
333 "(V?)PSLLW(Y?)ri",
334 "(V?)PSRAD(Y?)ri",
335 "(V?)PSRAW(Y?)ri",
336 "(V?)PSRLD(Y?)ri",
337 "(V?)PSRLQ(Y?)ri",
338 "VPSRLVQ(Y?)rr",
339 "(V?)PSRLW(Y?)ri",
340 "VTESTPD(Y?)rr",
341 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]342
343def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
344 let Latency = 1;
345 let NumMicroOps = 1;
346 let ResourceCycles = [1];
347}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]348def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
349 "COM_FST0r",
350 "UCOM_FPr",
351 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]352
353def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
354 let Latency = 1;
355 let NumMicroOps = 1;
356 let ResourceCycles = [1];
357}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]358def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]359 "MMX_MOVD64to64rr",
360 "MMX_MOVQ2DQrr",
361 "MMX_PALIGNRrri",
362 "MMX_PSHUFBrr",
363 "MMX_PSHUFWri",
364 "MMX_PUNPCKHBWirr",
365 "MMX_PUNPCKHDQirr",
366 "MMX_PUNPCKHWDirr",
367 "MMX_PUNPCKLBWirr",
368 "MMX_PUNPCKLDQirr",
369 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]370 "(V?)ANDNPD(Y?)rr",
371 "(V?)ANDNPS(Y?)rr",
372 "(V?)ANDPD(Y?)rr",
373 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]374 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]375 "(V?)INSERTPSrr",
376 "(V?)MOV64toPQIrr",
377 "(V?)MOVAPD(Y?)rr",
378 "(V?)MOVAPS(Y?)rr",
379 "(V?)MOVDDUP(Y?)rr",
380 "(V?)MOVDI2PDIrr",
381 "(V?)MOVHLPSrr",
382 "(V?)MOVLHPSrr",
383 "(V?)MOVSDrr",
384 "(V?)MOVSHDUP(Y?)rr",
385 "(V?)MOVSLDUP(Y?)rr",
386 "(V?)MOVSSrr",
387 "(V?)MOVUPD(Y?)rr",
388 "(V?)MOVUPS(Y?)rr",
389 "(V?)ORPD(Y?)rr",
390 "(V?)ORPS(Y?)rr",
391 "(V?)PACKSSDW(Y?)rr",
392 "(V?)PACKSSWB(Y?)rr",
393 "(V?)PACKUSDW(Y?)rr",
394 "(V?)PACKUSWB(Y?)rr",
395 "(V?)PALIGNR(Y?)rri",
396 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]397 "VPBROADCASTDrr",
398 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]399 "VPERMILPD(Y?)ri",
400 "VPERMILPD(Y?)rr",
401 "VPERMILPS(Y?)ri",
402 "VPERMILPS(Y?)rr",
403 "(V?)PMOVSXBDrr",
404 "(V?)PMOVSXBQrr",
405 "(V?)PMOVSXBWrr",
406 "(V?)PMOVSXDQrr",
407 "(V?)PMOVSXWDrr",
408 "(V?)PMOVSXWQrr",
409 "(V?)PMOVZXBDrr",
410 "(V?)PMOVZXBQrr",
411 "(V?)PMOVZXBWrr",
412 "(V?)PMOVZXDQrr",
413 "(V?)PMOVZXWDrr",
414 "(V?)PMOVZXWQrr",
415 "(V?)PSHUFB(Y?)rr",
416 "(V?)PSHUFD(Y?)ri",
417 "(V?)PSHUFHW(Y?)ri",
418 "(V?)PSHUFLW(Y?)ri",
419 "(V?)PSLLDQ(Y?)ri",
420 "(V?)PSRLDQ(Y?)ri",
421 "(V?)PUNPCKHBW(Y?)rr",
422 "(V?)PUNPCKHDQ(Y?)rr",
423 "(V?)PUNPCKHQDQ(Y?)rr",
424 "(V?)PUNPCKHWD(Y?)rr",
425 "(V?)PUNPCKLBW(Y?)rr",
426 "(V?)PUNPCKLDQ(Y?)rr",
427 "(V?)PUNPCKLQDQ(Y?)rr",
428 "(V?)PUNPCKLWD(Y?)rr",
429 "(V?)SHUFPD(Y?)rri",
430 "(V?)SHUFPS(Y?)rri",
431 "(V?)UNPCKHPD(Y?)rr",
432 "(V?)UNPCKHPS(Y?)rr",
433 "(V?)UNPCKLPD(Y?)rr",
434 "(V?)UNPCKLPS(Y?)rr",
435 "(V?)XORPD(Y?)rr",
436 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]437
438def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
439 let Latency = 1;
440 let NumMicroOps = 1;
441 let ResourceCycles = [1];
442}
443def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
444
445def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
446 let Latency = 1;
447 let NumMicroOps = 1;
448 let ResourceCycles = [1];
449}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]450def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
451 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]452
453def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
454 let Latency = 1;
455 let NumMicroOps = 1;
456 let ResourceCycles = [1];
457}
Craig Topperfbe31322018-04-05 21:56:19 +0000[diff] [blame^]458def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]459def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
460 "ADC(16|32|64)i",
461 "ADC(8|16|32|64)rr",
462 "ADCX(32|64)rr",
463 "ADOX(32|64)rr",
464 "BT(16|32|64)ri8",
465 "BT(16|32|64)rr",
466 "BTC(16|32|64)ri8",
467 "BTC(16|32|64)rr",
468 "BTR(16|32|64)ri8",
469 "BTR(16|32|64)rr",
470 "BTS(16|32|64)ri8",
471 "BTS(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]472 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]473 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
474 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
475 "JMP_1",
476 "JMP_4",
477 "RORX(32|64)ri",
478 "SAR(8|16|32|64)r1",
479 "SAR(8|16|32|64)ri",
480 "SARX(32|64)rr",
481 "SBB(16|32|64)ri",
482 "SBB(16|32|64)i",
483 "SBB(8|16|32|64)rr",
484 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
485 "SHL(8|16|32|64)r1",
486 "SHL(8|16|32|64)ri",
487 "SHLX(32|64)rr",
488 "SHR(8|16|32|64)r1",
489 "SHR(8|16|32|64)ri",
490 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]491
492def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
493 let Latency = 1;
494 let NumMicroOps = 1;
495 let ResourceCycles = [1];
496}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]497def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
498 "BLSI(32|64)rr",
499 "BLSMSK(32|64)rr",
500 "BLSR(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]501 "LEA(16|32|64)(_32)?r",
502 "MMX_PABSBrr",
503 "MMX_PABSDrr",
504 "MMX_PABSWrr",
505 "MMX_PADDBirr",
506 "MMX_PADDDirr",
507 "MMX_PADDQirr",
508 "MMX_PADDSBirr",
509 "MMX_PADDSWirr",
510 "MMX_PADDUSBirr",
511 "MMX_PADDUSWirr",
512 "MMX_PADDWirr",
513 "MMX_PAVGBirr",
514 "MMX_PAVGWirr",
515 "MMX_PCMPEQBirr",
516 "MMX_PCMPEQDirr",
517 "MMX_PCMPEQWirr",
518 "MMX_PCMPGTBirr",
519 "MMX_PCMPGTDirr",
520 "MMX_PCMPGTWirr",
521 "MMX_PMAXSWirr",
522 "MMX_PMAXUBirr",
523 "MMX_PMINSWirr",
524 "MMX_PMINUBirr",
525 "MMX_PSIGNBrr",
526 "MMX_PSIGNDrr",
527 "MMX_PSIGNWrr",
528 "MMX_PSUBBirr",
529 "MMX_PSUBDirr",
530 "MMX_PSUBQirr",
531 "MMX_PSUBSBirr",
532 "MMX_PSUBSWirr",
533 "MMX_PSUBUSBirr",
534 "MMX_PSUBUSWirr",
535 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]536 "(V?)PABSB(Y?)rr",
537 "(V?)PABSD(Y?)rr",
538 "(V?)PABSW(Y?)rr",
539 "(V?)PADDB(Y?)rr",
540 "(V?)PADDD(Y?)rr",
541 "(V?)PADDQ(Y?)rr",
542 "(V?)PADDSB(Y?)rr",
543 "(V?)PADDSW(Y?)rr",
544 "(V?)PADDUSB(Y?)rr",
545 "(V?)PADDUSW(Y?)rr",
546 "(V?)PADDW(Y?)rr",
547 "(V?)PAVGB(Y?)rr",
548 "(V?)PAVGW(Y?)rr",
549 "(V?)PCMPEQB(Y?)rr",
550 "(V?)PCMPEQD(Y?)rr",
551 "(V?)PCMPEQQ(Y?)rr",
552 "(V?)PCMPEQW(Y?)rr",
553 "(V?)PCMPGTB(Y?)rr",
554 "(V?)PCMPGTD(Y?)rr",
555 "(V?)PCMPGTW(Y?)rr",
556 "(V?)PMAXSB(Y?)rr",
557 "(V?)PMAXSD(Y?)rr",
558 "(V?)PMAXSW(Y?)rr",
559 "(V?)PMAXUB(Y?)rr",
560 "(V?)PMAXUD(Y?)rr",
561 "(V?)PMAXUW(Y?)rr",
562 "(V?)PMINSB(Y?)rr",
563 "(V?)PMINSD(Y?)rr",
564 "(V?)PMINSW(Y?)rr",
565 "(V?)PMINUB(Y?)rr",
566 "(V?)PMINUD(Y?)rr",
567 "(V?)PMINUW(Y?)rr",
568 "(V?)PSIGNB(Y?)rr",
569 "(V?)PSIGND(Y?)rr",
570 "(V?)PSIGNW(Y?)rr",
571 "(V?)PSUBB(Y?)rr",
572 "(V?)PSUBD(Y?)rr",
573 "(V?)PSUBQ(Y?)rr",
574 "(V?)PSUBSB(Y?)rr",
575 "(V?)PSUBSW(Y?)rr",
576 "(V?)PSUBUSB(Y?)rr",
577 "(V?)PSUBUSW(Y?)rr",
578 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]579
580def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
581 let Latency = 1;
582 let NumMicroOps = 1;
583 let ResourceCycles = [1];
584}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]585def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]586 "MMX_PANDNirr",
587 "MMX_PANDirr",
588 "MMX_PORirr",
589 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]590 "(V?)BLENDPD(Y?)rri",
591 "(V?)BLENDPS(Y?)rri",
592 "(V?)MOVDQA(Y?)rr",
593 "(V?)MOVDQU(Y?)rr",
594 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]595 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]596 "(V?)PANDN(Y?)rr",
597 "(V?)PAND(Y?)rr",
598 "VPBLENDD(Y?)rri",
599 "(V?)POR(Y?)rr",
600 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]601
602def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
603 let Latency = 1;
604 let NumMicroOps = 1;
605 let ResourceCycles = [1];
606}
Craig Topperfbe31322018-04-05 21:56:19 +0000[diff] [blame^]607def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]608def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
609 "ADD(8|16|32|64)rr",
610 "ADD(8|16|32|64)i",
611 "AND(8|16|32|64)ri",
612 "AND(8|16|32|64)rr",
613 "AND(8|16|32|64)i",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]614 "CLC",
615 "CMC",
616 "CMP(8|16|32|64)ri",
617 "CMP(8|16|32|64)rr",
618 "CMP(8|16|32|64)i",
619 "DEC(8|16|32|64)r",
620 "INC(8|16|32|64)r",
621 "LAHF",
622 "MOV(8|16|32|64)rr",
623 "MOV(8|16|32|64)ri",
624 "MOVSX(16|32|64)rr16",
625 "MOVSX(16|32|64)rr32",
626 "MOVSX(16|32|64)rr8",
627 "MOVZX(16|32|64)rr16",
628 "MOVZX(16|32|64)rr8",
629 "NEG(8|16|32|64)r",
630 "NOOP",
631 "NOT(8|16|32|64)r",
632 "OR(8|16|32|64)ri",
633 "OR(8|16|32|64)rr",
634 "OR(8|16|32|64)i",
635 "SAHF",
636 "SGDT64m",
637 "SIDT64m",
638 "SLDT64m",
639 "SMSW16m",
640 "STC",
641 "STRm",
642 "SUB(8|16|32|64)ri",
643 "SUB(8|16|32|64)rr",
644 "SUB(8|16|32|64)i",
645 "SYSCALL",
646 "TEST(8|16|32|64)rr",
647 "TEST(8|16|32|64)i",
648 "TEST(8|16|32|64)ri",
649 "XCHG(16|32|64)rr",
650 "XOR(8|16|32|64)ri",
651 "XOR(8|16|32|64)rr",
652 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]653
654def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
655 let Latency = 1;
656 let NumMicroOps = 2;
657 let ResourceCycles = [1,1];
658}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]659def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
660 "MMX_MOVD64from64rm",
661 "MMX_MOVD64mr",
662 "MMX_MOVNTQmr",
663 "MMX_MOVQ64mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]664 "MOVNTI_64mr",
665 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]666 "ST_FP32m",
667 "ST_FP64m",
668 "ST_FP80m",
669 "VEXTRACTF128mr",
670 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]671 "(V?)MOVAPD(Y?)mr",
672 "(V?)MOVAPS(Y?)mr",
673 "(V?)MOVDQA(Y?)mr",
674 "(V?)MOVDQU(Y?)mr",
675 "(V?)MOVHPDmr",
676 "(V?)MOVHPSmr",
677 "(V?)MOVLPDmr",
678 "(V?)MOVLPSmr",
679 "(V?)MOVNTDQ(V?)mr",
680 "(V?)MOVNTPD(V?)mr",
681 "(V?)MOVNTPS(V?)mr",
682 "(V?)MOVPDI2DImr",
683 "(V?)MOVPQI2QImr",
684 "(V?)MOVPQIto64mr",
685 "(V?)MOVSDmr",
686 "(V?)MOVSSmr",
687 "(V?)MOVUPD(Y?)mr",
688 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]689
690def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
691 let Latency = 2;
692 let NumMicroOps = 2;
693 let ResourceCycles = [2];
694}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]695def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
696 "BLENDVPSrr0",
697 "MMX_PINSRWrr",
698 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]699 "VBLENDVPD(Y?)rr",
700 "VBLENDVPS(Y?)rr",
701 "VPBLENDVB(Y?)rr",
702 "(V?)PINSRBrr",
703 "(V?)PINSRDrr",
704 "(V?)PINSRQrr",
705 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]706
707def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
708 let Latency = 2;
709 let NumMicroOps = 2;
710 let ResourceCycles = [2];
711}
712def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
713
714def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
715 let Latency = 2;
716 let NumMicroOps = 2;
717 let ResourceCycles = [2];
718}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]719def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
720 "ROL(8|16|32|64)ri",
721 "ROR(8|16|32|64)r1",
722 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]723
724def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
725 let Latency = 2;
726 let NumMicroOps = 2;
727 let ResourceCycles = [2];
728}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]729def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
730 "MFENCE",
731 "WAIT",
732 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]733
734def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
735 let Latency = 2;
736 let NumMicroOps = 2;
737 let ResourceCycles = [1,1];
738}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]739def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
740 "VCVTPH2PS(Y?)rr",
741 "(V?)CVTPS2PDrr",
742 "(V?)CVTSS2SDrr",
743 "(V?)EXTRACTPSrr",
744 "(V?)PEXTRBrr",
745 "(V?)PEXTRDrr",
746 "(V?)PEXTRQrr",
747 "(V?)PEXTRWrr",
748 "(V?)PSLLDrr",
749 "(V?)PSLLQrr",
750 "(V?)PSLLWrr",
751 "(V?)PSRADrr",
752 "(V?)PSRAWrr",
753 "(V?)PSRLDrr",
754 "(V?)PSRLQrr",
755 "(V?)PSRLWrr",
756 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]757
758def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
759 let Latency = 2;
760 let NumMicroOps = 2;
761 let ResourceCycles = [1,1];
762}
763def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
764
765def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
766 let Latency = 2;
767 let NumMicroOps = 2;
768 let ResourceCycles = [1,1];
769}
770def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
771
772def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
773 let Latency = 2;
774 let NumMicroOps = 2;
775 let ResourceCycles = [1,1];
776}
777def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
778
779def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
780 let Latency = 2;
781 let NumMicroOps = 2;
782 let ResourceCycles = [1,1];
783}
Craig Topper498875f2018-04-04 17:54:19 +0000[diff] [blame]784def: InstRW<[BWWriteResGroup19], (instrs BSWAP64r)>;
785
786def BWWriteResGroup19_1 : SchedWriteRes<[BWPort15]> {
787 let Latency = 1;
788 let NumMicroOps = 1;
789 let ResourceCycles = [1];
790}
791def: InstRW<[BWWriteResGroup19_1], (instrs BSWAP32r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]792
793def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
794 let Latency = 2;
795 let NumMicroOps = 2;
796 let ResourceCycles = [1,1];
797}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]798def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]799def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]800def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
801 "ADC8ri",
802 "CMOV(A|BE)(16|32|64)rr",
803 "SBB8i8",
804 "SBB8ri",
805 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]806
807def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
808 let Latency = 2;
809 let NumMicroOps = 3;
810 let ResourceCycles = [1,1,1];
811}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]812def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
813 "(V?)PEXTRBmr",
814 "(V?)PEXTRDmr",
815 "(V?)PEXTRQmr",
816 "(V?)PEXTRWmr",
817 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]818
819def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
820 let Latency = 2;
821 let NumMicroOps = 3;
822 let ResourceCycles = [1,1,1];
823}
824def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
825
826def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
827 let Latency = 2;
828 let NumMicroOps = 3;
829 let ResourceCycles = [1,1,1];
830}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]831def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]832
833def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
834 let Latency = 2;
835 let NumMicroOps = 3;
836 let ResourceCycles = [1,1,1];
837}
838def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
839
840def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
841 let Latency = 2;
842 let NumMicroOps = 3;
843 let ResourceCycles = [1,1,1];
844}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]845def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]846def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
847 "PUSH64i8",
848 "STOSB",
849 "STOSL",
850 "STOSQ",
851 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]852
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]853def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
854 let Latency = 3;
855 let NumMicroOps = 1;
856 let ResourceCycles = [1];
857}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]858def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]859def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]860def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]861 "ADD_FST0r",
862 "ADD_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]863 "MMX_CVTPI2PSirr",
864 "PDEP(32|64)rr",
865 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]866 "SHLD(16|32|64)rri8",
867 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]868 "SUBR_FPrST0",
869 "SUBR_FST0r",
870 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]871 "SUB_FPrST0",
872 "SUB_FST0r",
873 "SUB_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]874 "(V?)ADDPD(Y?)rr",
875 "(V?)ADDPS(Y?)rr",
876 "(V?)ADDSDrr",
877 "(V?)ADDSSrr",
878 "(V?)ADDSUBPD(Y?)rr",
879 "(V?)ADDSUBPS(Y?)rr",
880 "(V?)CMPPD(Y?)rri",
881 "(V?)CMPPS(Y?)rri",
882 "(V?)CMPSDrr",
883 "(V?)CMPSSrr",
884 "(V?)COMISDrr",
885 "(V?)COMISSrr",
886 "(V?)CVTDQ2PS(Y?)rr",
887 "(V?)CVTPS2DQ(Y?)rr",
888 "(V?)CVTTPS2DQ(Y?)rr",
889 "(V?)MAX(C?)PD(Y?)rr",
890 "(V?)MAX(C?)PS(Y?)rr",
891 "(V?)MAX(C?)SDrr",
892 "(V?)MAX(C?)SSrr",
893 "(V?)MIN(C?)PD(Y?)rr",
894 "(V?)MIN(C?)PS(Y?)rr",
895 "(V?)MIN(C?)SDrr",
896 "(V?)MIN(C?)SSrr",
897 "(V?)SUBPD(Y?)rr",
898 "(V?)SUBPS(Y?)rr",
899 "(V?)SUBSDrr",
900 "(V?)SUBSSrr",
901 "(V?)UCOMISDrr",
902 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]903
904def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
905 let Latency = 3;
906 let NumMicroOps = 2;
907 let ResourceCycles = [1,1];
908}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]909def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]910
911def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
912 let Latency = 3;
913 let NumMicroOps = 1;
914 let ResourceCycles = [1];
915}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]916def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
917 "VBROADCASTSSYrr",
918 "VEXTRACTF128rr",
919 "VEXTRACTI128rr",
920 "VINSERTF128rr",
921 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]922 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]923 "VPBROADCASTDYrr",
924 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]925 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]926 "VPERM2F128rr",
927 "VPERM2I128rr",
928 "VPERMDYrr",
929 "VPERMPDYri",
930 "VPERMPSYrr",
931 "VPERMQYri",
932 "VPMOVSXBDYrr",
933 "VPMOVSXBQYrr",
934 "VPMOVSXBWYrr",
935 "VPMOVSXDQYrr",
936 "VPMOVSXWDYrr",
937 "VPMOVSXWQYrr",
938 "VPMOVZXBDYrr",
939 "VPMOVZXBQYrr",
940 "VPMOVZXBWYrr",
941 "VPMOVZXDQYrr",
942 "VPMOVZXWDYrr",
943 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]944
945def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
946 let Latency = 3;
947 let NumMicroOps = 1;
948 let ResourceCycles = [1];
949}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]950def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
951 "(V?)MULPS(Y?)rr",
952 "(V?)MULSDrr",
953 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]954
955def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
956 let Latency = 3;
957 let NumMicroOps = 3;
958 let ResourceCycles = [3];
959}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]960def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
961 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]962
963def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
964 let Latency = 3;
965 let NumMicroOps = 3;
966 let ResourceCycles = [2,1];
967}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]968def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
969 "VPSRAVD(Y?)rr",
970 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]971
972def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
973 let Latency = 3;
974 let NumMicroOps = 3;
975 let ResourceCycles = [2,1];
976}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]977def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
978 "MMX_PHADDSWrr",
979 "MMX_PHADDWrr",
980 "MMX_PHSUBDrr",
981 "MMX_PHSUBSWrr",
982 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]983 "(V?)PHADDD(Y?)rr",
984 "(V?)PHADDSW(Y?)rr",
985 "(V?)PHADDW(Y?)rr",
986 "(V?)PHSUBD(Y?)rr",
987 "(V?)PHSUBSW(Y?)rr",
988 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]989
990def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
991 let Latency = 3;
992 let NumMicroOps = 3;
993 let ResourceCycles = [2,1];
994}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]995def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
996 "MMX_PACKSSWBirr",
997 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]998
999def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
1000 let Latency = 3;
1001 let NumMicroOps = 3;
1002 let ResourceCycles = [1,2];
1003}
1004def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1005
1006def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1007 let Latency = 3;
1008 let NumMicroOps = 3;
1009 let ResourceCycles = [1,2];
1010}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1011def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1012 "RCL(8|16|32|64)ri",
1013 "RCR(8|16|32|64)r1",
1014 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1015
1016def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1017 let Latency = 3;
1018 let NumMicroOps = 3;
1019 let ResourceCycles = [2,1];
1020}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1021def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1022 "ROR(8|16|32|64)rCL",
1023 "SAR(8|16|32|64)rCL",
1024 "SHL(8|16|32|64)rCL",
1025 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1026
1027def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1028 let Latency = 3;
1029 let NumMicroOps = 4;
1030 let ResourceCycles = [1,1,1,1];
1031}
1032def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1033
1034def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1035 let Latency = 3;
1036 let NumMicroOps = 4;
1037 let ResourceCycles = [1,1,1,1];
1038}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1039def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1040 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1041
1042def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1043 let Latency = 4;
1044 let NumMicroOps = 2;
1045 let ResourceCycles = [1,1];
1046}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1047def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1048 "(V?)CVTSD2SIrr",
1049 "(V?)CVTSS2SI64rr",
1050 "(V?)CVTSS2SIrr",
1051 "(V?)CVTTSD2SI64rr",
1052 "(V?)CVTTSD2SIrr",
1053 "(V?)CVTTSS2SI64rr",
1054 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1055
1056def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1057 let Latency = 4;
1058 let NumMicroOps = 2;
1059 let ResourceCycles = [1,1];
1060}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1061def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1062 "VPSLLDYrr",
1063 "VPSLLQYrr",
1064 "VPSLLWYrr",
1065 "VPSRADYrr",
1066 "VPSRAWYrr",
1067 "VPSRLDYrr",
1068 "VPSRLQYrr",
1069 "VPSRLWYrr",
1070 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1071
1072def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1073 let Latency = 4;
1074 let NumMicroOps = 2;
1075 let ResourceCycles = [1,1];
1076}
1077def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1078
1079def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1080 let Latency = 4;
1081 let NumMicroOps = 2;
1082 let ResourceCycles = [1,1];
1083}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1084def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1085def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1086 "MMX_CVTPI2PDirr",
1087 "MMX_CVTPS2PIirr",
1088 "MMX_CVTTPD2PIirr",
1089 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1090 "(V?)CVTDQ2PDrr",
1091 "(V?)CVTPD2DQrr",
1092 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1093 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1094 "(V?)CVTSD2SSrr",
1095 "(V?)CVTSI642SDrr",
1096 "(V?)CVTSI2SDrr",
1097 "(V?)CVTSI2SSrr",
1098 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1099
1100def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1101 let Latency = 4;
1102 let NumMicroOps = 4;
1103}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1104def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1105
1106def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1107 let Latency = 4;
1108 let NumMicroOps = 3;
1109 let ResourceCycles = [1,1,1];
1110}
1111def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1112
1113def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1114 let Latency = 4;
1115 let NumMicroOps = 3;
1116 let ResourceCycles = [1,1,1];
1117}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1118def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1119 "ISTT_FP32m",
1120 "ISTT_FP64m",
1121 "IST_F16m",
1122 "IST_F32m",
1123 "IST_FP16m",
1124 "IST_FP32m",
1125 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1126 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1127
1128def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1129 let Latency = 4;
1130 let NumMicroOps = 4;
1131 let ResourceCycles = [4];
1132}
1133def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1134
1135def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1136 let Latency = 4;
1137 let NumMicroOps = 4;
1138 let ResourceCycles = [1,3];
1139}
1140def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1141
1142def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1143 let Latency = 5;
1144 let NumMicroOps = 1;
1145 let ResourceCycles = [1];
1146}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1147def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1148 "MMX_PMADDWDirr",
1149 "MMX_PMULHRSWrr",
1150 "MMX_PMULHUWirr",
1151 "MMX_PMULHWirr",
1152 "MMX_PMULLWirr",
1153 "MMX_PMULUDQirr",
1154 "MMX_PSADBWirr",
1155 "MUL_FPrST0",
1156 "MUL_FST0r",
1157 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1158 "(V?)PCMPGTQ(Y?)rr",
1159 "(V?)PHMINPOSUWrr",
1160 "(V?)PMADDUBSW(Y?)rr",
1161 "(V?)PMADDWD(Y?)rr",
1162 "(V?)PMULDQ(Y?)rr",
1163 "(V?)PMULHRSW(Y?)rr",
1164 "(V?)PMULHUW(Y?)rr",
1165 "(V?)PMULHW(Y?)rr",
1166 "(V?)PMULLW(Y?)rr",
1167 "(V?)PMULUDQ(Y?)rr",
1168 "(V?)PSADBW(Y?)rr",
1169 "(V?)RCPPSr",
1170 "(V?)RCPSSr",
1171 "(V?)RSQRTPSr",
1172 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1173
1174def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1175 let Latency = 5;
1176 let NumMicroOps = 1;
1177 let ResourceCycles = [1];
1178}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1179def: InstRW<[BWWriteResGroup48],
1180 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1181 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1182
1183def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1184 let Latency = 5;
1185 let NumMicroOps = 1;
1186 let ResourceCycles = [1];
1187}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1188def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1189 "MMX_MOVD64to64rm",
1190 "MMX_MOVQ64rm",
1191 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1192 "MOVSX(16|32|64)rm16",
1193 "MOVSX(16|32|64)rm32",
1194 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1195 "MOVZX(16|32|64)rm16",
1196 "MOVZX(16|32|64)rm8",
1197 "PREFETCHNTA",
1198 "PREFETCHT0",
1199 "PREFETCHT1",
1200 "PREFETCHT2",
1201 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1202 "(V?)LDDQUrm",
1203 "(V?)MOV64toPQIrm",
1204 "(V?)MOVAPDrm",
1205 "(V?)MOVAPSrm",
1206 "(V?)MOVDDUPrm",
1207 "(V?)MOVDI2PDIrm",
1208 "(V?)MOVDQArm",
1209 "(V?)MOVDQUrm",
1210 "(V?)MOVNTDQArm",
1211 "(V?)MOVQI2PQIrm",
1212 "(V?)MOVSDrm",
1213 "(V?)MOVSHDUPrm",
1214 "(V?)MOVSLDUPrm",
1215 "(V?)MOVSSrm",
1216 "(V?)MOVUPDrm",
1217 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1218 "VPBROADCASTDrm",
1219 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1220
1221def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1222 let Latency = 5;
1223 let NumMicroOps = 3;
1224 let ResourceCycles = [1,2];
1225}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1226def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1227 "(V?)HADDPD(Y?)rr",
1228 "(V?)HADDPS(Y?)rr",
1229 "(V?)HSUBPD(Y?)rr",
1230 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1231
1232def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1233 let Latency = 5;
1234 let NumMicroOps = 3;
1235 let ResourceCycles = [1,1,1];
1236}
1237def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1238
1239def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1240 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1241 let NumMicroOps = 3;
1242 let ResourceCycles = [1,1,1];
1243}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1244def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1245
1246def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1247 let Latency = 5;
1248 let NumMicroOps = 4;
1249 let ResourceCycles = [1,1,1,1];
1250}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1251def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1252 "VMASKMOVPS(Y?)mr",
1253 "VPMASKMOVD(Y?)mr",
1254 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1255
1256def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1257 let Latency = 5;
1258 let NumMicroOps = 5;
1259 let ResourceCycles = [1,4];
1260}
1261def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1262
1263def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1264 let Latency = 5;
1265 let NumMicroOps = 5;
1266 let ResourceCycles = [1,4];
1267}
1268def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1269
1270def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1271 let Latency = 5;
1272 let NumMicroOps = 5;
1273 let ResourceCycles = [2,3];
1274}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1275def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1276
1277def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1278 let Latency = 5;
1279 let NumMicroOps = 6;
1280 let ResourceCycles = [1,1,4];
1281}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1282def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1283
1284def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1285 let Latency = 6;
1286 let NumMicroOps = 1;
1287 let ResourceCycles = [1];
1288}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1289def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1290 "LD_F64m",
1291 "LD_F80m",
1292 "VBROADCASTF128",
1293 "VBROADCASTI128",
1294 "VBROADCASTSDYrm",
1295 "VBROADCASTSSYrm",
1296 "VLDDQUYrm",
1297 "VMOVAPDYrm",
1298 "VMOVAPSYrm",
1299 "VMOVDDUPYrm",
1300 "VMOVDQAYrm",
1301 "VMOVDQUYrm",
1302 "VMOVNTDQAYrm",
1303 "VMOVSHDUPYrm",
1304 "VMOVSLDUPYrm",
1305 "VMOVUPDYrm",
1306 "VMOVUPSYrm",
1307 "VPBROADCASTDYrm",
1308 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1309 "(V?)ROUNDPD(Y?)r",
1310 "(V?)ROUNDPS(Y?)r",
1311 "(V?)ROUNDSDr",
1312 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1313
1314def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1315 let Latency = 6;
1316 let NumMicroOps = 2;
1317 let ResourceCycles = [1,1];
1318}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1319def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1320 "MMX_PSLLQrm",
1321 "MMX_PSLLWrm",
1322 "MMX_PSRADrm",
1323 "MMX_PSRAWrm",
1324 "MMX_PSRLDrm",
1325 "MMX_PSRLQrm",
1326 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1327 "VCVTPH2PS(Y?)rm",
1328 "(V?)CVTPS2PDrm",
1329 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1330 "VPSLLVQrm",
1331 "VPSRLVQrm",
1332 "VTESTPDrm",
1333 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1334
1335def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1336 let Latency = 6;
1337 let NumMicroOps = 2;
1338 let ResourceCycles = [1,1];
1339}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1340def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1341 "VCVTPD2DQYrr",
1342 "VCVTPD2PSYrr",
1343 "VCVTPS2PHYrr",
1344 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1345
1346def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1347 let Latency = 6;
1348 let NumMicroOps = 2;
1349 let ResourceCycles = [1,1];
1350}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1351def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1352 "MMX_PINSRWrm",
1353 "MMX_PSHUFBrm",
1354 "MMX_PSHUFWmi",
1355 "MMX_PUNPCKHBWirm",
1356 "MMX_PUNPCKHDQirm",
1357 "MMX_PUNPCKHWDirm",
1358 "MMX_PUNPCKLBWirm",
1359 "MMX_PUNPCKLDQirm",
1360 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1361 "(V?)ANDNPDrm",
1362 "(V?)ANDNPSrm",
1363 "(V?)ANDPDrm",
1364 "(V?)ANDPSrm",
1365 "(V?)INSERTPSrm",
1366 "(V?)MOVHPDrm",
1367 "(V?)MOVHPSrm",
1368 "(V?)MOVLPDrm",
1369 "(V?)MOVLPSrm",
1370 "(V?)ORPDrm",
1371 "(V?)ORPSrm",
1372 "(V?)PACKSSDWrm",
1373 "(V?)PACKSSWBrm",
1374 "(V?)PACKUSDWrm",
1375 "(V?)PACKUSWBrm",
1376 "(V?)PALIGNRrmi",
1377 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1378 "VPERMILPDmi",
1379 "VPERMILPDrm",
1380 "VPERMILPSmi",
1381 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1382 "(V?)PINSRBrm",
1383 "(V?)PINSRDrm",
1384 "(V?)PINSRQrm",
1385 "(V?)PINSRWrm",
1386 "(V?)PMOVSXBDrm",
1387 "(V?)PMOVSXBQrm",
1388 "(V?)PMOVSXBWrm",
1389 "(V?)PMOVSXDQrm",
1390 "(V?)PMOVSXWDrm",
1391 "(V?)PMOVSXWQrm",
1392 "(V?)PMOVZXBDrm",
1393 "(V?)PMOVZXBQrm",
1394 "(V?)PMOVZXBWrm",
1395 "(V?)PMOVZXDQrm",
1396 "(V?)PMOVZXWDrm",
1397 "(V?)PMOVZXWQrm",
1398 "(V?)PSHUFBrm",
1399 "(V?)PSHUFDmi",
1400 "(V?)PSHUFHWmi",
1401 "(V?)PSHUFLWmi",
1402 "(V?)PUNPCKHBWrm",
1403 "(V?)PUNPCKHDQrm",
1404 "(V?)PUNPCKHQDQrm",
1405 "(V?)PUNPCKHWDrm",
1406 "(V?)PUNPCKLBWrm",
1407 "(V?)PUNPCKLDQrm",
1408 "(V?)PUNPCKLQDQrm",
1409 "(V?)PUNPCKLWDrm",
1410 "(V?)SHUFPDrmi",
1411 "(V?)SHUFPSrmi",
1412 "(V?)UNPCKHPDrm",
1413 "(V?)UNPCKHPSrm",
1414 "(V?)UNPCKLPDrm",
1415 "(V?)UNPCKLPSrm",
1416 "(V?)XORPDrm",
1417 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1418
1419def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1420 let Latency = 6;
1421 let NumMicroOps = 2;
1422 let ResourceCycles = [1,1];
1423}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1424def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1425 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1426
1427def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1428 let Latency = 6;
1429 let NumMicroOps = 2;
1430 let ResourceCycles = [1,1];
1431}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1432def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1433 "ADCX(32|64)rm",
1434 "ADOX(32|64)rm",
1435 "BT(16|32|64)mi8",
1436 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1437 "RORX(32|64)mi",
1438 "SARX(32|64)rm",
1439 "SBB(8|16|32|64)rm",
1440 "SHLX(32|64)rm",
1441 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1442
1443def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1444 let Latency = 6;
1445 let NumMicroOps = 2;
1446 let ResourceCycles = [1,1];
1447}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1448def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1449 "BLSI(32|64)rm",
1450 "BLSMSK(32|64)rm",
1451 "BLSR(32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1452 "MMX_PABSBrm",
1453 "MMX_PABSDrm",
1454 "MMX_PABSWrm",
1455 "MMX_PADDBirm",
1456 "MMX_PADDDirm",
1457 "MMX_PADDQirm",
1458 "MMX_PADDSBirm",
1459 "MMX_PADDSWirm",
1460 "MMX_PADDUSBirm",
1461 "MMX_PADDUSWirm",
1462 "MMX_PADDWirm",
1463 "MMX_PAVGBirm",
1464 "MMX_PAVGWirm",
1465 "MMX_PCMPEQBirm",
1466 "MMX_PCMPEQDirm",
1467 "MMX_PCMPEQWirm",
1468 "MMX_PCMPGTBirm",
1469 "MMX_PCMPGTDirm",
1470 "MMX_PCMPGTWirm",
1471 "MMX_PMAXSWirm",
1472 "MMX_PMAXUBirm",
1473 "MMX_PMINSWirm",
1474 "MMX_PMINUBirm",
1475 "MMX_PSIGNBrm",
1476 "MMX_PSIGNDrm",
1477 "MMX_PSIGNWrm",
1478 "MMX_PSUBBirm",
1479 "MMX_PSUBDirm",
1480 "MMX_PSUBQirm",
1481 "MMX_PSUBSBirm",
1482 "MMX_PSUBSWirm",
1483 "MMX_PSUBUSBirm",
1484 "MMX_PSUBUSWirm",
1485 "MMX_PSUBWirm",
1486 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1487 "(V?)PABSBrm",
1488 "(V?)PABSDrm",
1489 "(V?)PABSWrm",
1490 "(V?)PADDBrm",
1491 "(V?)PADDDrm",
1492 "(V?)PADDQrm",
1493 "(V?)PADDSBrm",
1494 "(V?)PADDSWrm",
1495 "(V?)PADDUSBrm",
1496 "(V?)PADDUSWrm",
1497 "(V?)PADDWrm",
1498 "(V?)PAVGBrm",
1499 "(V?)PAVGWrm",
1500 "(V?)PCMPEQBrm",
1501 "(V?)PCMPEQDrm",
1502 "(V?)PCMPEQQrm",
1503 "(V?)PCMPEQWrm",
1504 "(V?)PCMPGTBrm",
1505 "(V?)PCMPGTDrm",
1506 "(V?)PCMPGTWrm",
1507 "(V?)PMAXSBrm",
1508 "(V?)PMAXSDrm",
1509 "(V?)PMAXSWrm",
1510 "(V?)PMAXUBrm",
1511 "(V?)PMAXUDrm",
1512 "(V?)PMAXUWrm",
1513 "(V?)PMINSBrm",
1514 "(V?)PMINSDrm",
1515 "(V?)PMINSWrm",
1516 "(V?)PMINUBrm",
1517 "(V?)PMINUDrm",
1518 "(V?)PMINUWrm",
1519 "(V?)PSIGNBrm",
1520 "(V?)PSIGNDrm",
1521 "(V?)PSIGNWrm",
1522 "(V?)PSUBBrm",
1523 "(V?)PSUBDrm",
1524 "(V?)PSUBQrm",
1525 "(V?)PSUBSBrm",
1526 "(V?)PSUBSWrm",
1527 "(V?)PSUBUSBrm",
1528 "(V?)PSUBUSWrm",
1529 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1530
1531def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1532 let Latency = 6;
1533 let NumMicroOps = 2;
1534 let ResourceCycles = [1,1];
1535}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1536def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1537 "MMX_PANDirm",
1538 "MMX_PORirm",
1539 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1540 "(V?)BLENDPDrmi",
1541 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1542 "VINSERTF128rm",
1543 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1544 "(V?)PANDNrm",
1545 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1546 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1547 "(V?)PORrm",
1548 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1549
1550def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1551 let Latency = 6;
1552 let NumMicroOps = 2;
1553 let ResourceCycles = [1,1];
1554}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1555def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1556def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1557 "AND(8|16|32|64)rm",
1558 "CMP(8|16|32|64)mi",
1559 "CMP(8|16|32|64)mr",
1560 "CMP(8|16|32|64)rm",
1561 "OR(8|16|32|64)rm",
1562 "POP(16|32|64)rmr",
1563 "SUB(8|16|32|64)rm",
1564 "TEST(8|16|32|64)mr",
1565 "TEST(8|16|32|64)mi",
1566 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1567
1568def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1569 let Latency = 6;
1570 let NumMicroOps = 4;
1571 let ResourceCycles = [1,1,2];
1572}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1573def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1574 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1575
1576def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1577 let Latency = 6;
1578 let NumMicroOps = 4;
1579 let ResourceCycles = [1,1,1,1];
1580}
1581def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1582
1583def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1584 let Latency = 6;
1585 let NumMicroOps = 4;
1586 let ResourceCycles = [1,1,1,1];
1587}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1588def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1589 "BTR(16|32|64)mi8",
1590 "BTS(16|32|64)mi8",
1591 "SAR(8|16|32|64)m1",
1592 "SAR(8|16|32|64)mi",
1593 "SHL(8|16|32|64)m1",
1594 "SHL(8|16|32|64)mi",
1595 "SHR(8|16|32|64)m1",
1596 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1597
1598def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1599 let Latency = 6;
1600 let NumMicroOps = 4;
1601 let ResourceCycles = [1,1,1,1];
1602}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1603def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1604 "ADD(8|16|32|64)mr",
1605 "AND(8|16|32|64)mi",
1606 "AND(8|16|32|64)mr",
1607 "DEC(8|16|32|64)m",
1608 "INC(8|16|32|64)m",
1609 "NEG(8|16|32|64)m",
1610 "NOT(8|16|32|64)m",
1611 "OR(8|16|32|64)mi",
1612 "OR(8|16|32|64)mr",
1613 "POP(16|32|64)rmm",
1614 "PUSH(16|32|64)rmm",
1615 "SUB(8|16|32|64)mi",
1616 "SUB(8|16|32|64)mr",
1617 "XOR(8|16|32|64)mi",
1618 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1619
1620def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1621 let Latency = 6;
1622 let NumMicroOps = 6;
1623 let ResourceCycles = [1,5];
1624}
1625def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1626
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1627def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1628 let Latency = 7;
1629 let NumMicroOps = 2;
1630 let ResourceCycles = [1,1];
1631}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1632def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1633 "VPSLLQYrm",
1634 "VPSLLVQYrm",
1635 "VPSLLWYrm",
1636 "VPSRADYrm",
1637 "VPSRAWYrm",
1638 "VPSRLDYrm",
1639 "VPSRLQYrm",
1640 "VPSRLVQYrm",
1641 "VPSRLWYrm",
1642 "VTESTPDYrm",
1643 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1644
1645def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1646 let Latency = 7;
1647 let NumMicroOps = 2;
1648 let ResourceCycles = [1,1];
1649}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1650def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1651 "FCOM64m",
1652 "FCOMP32m",
1653 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1654
1655def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1656 let Latency = 7;
1657 let NumMicroOps = 2;
1658 let ResourceCycles = [1,1];
1659}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1660def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1661 "VANDNPSYrm",
1662 "VANDPDYrm",
1663 "VANDPSYrm",
1664 "VORPDYrm",
1665 "VORPSYrm",
1666 "VPACKSSDWYrm",
1667 "VPACKSSWBYrm",
1668 "VPACKUSDWYrm",
1669 "VPACKUSWBYrm",
1670 "VPALIGNRYrmi",
1671 "VPBLENDWYrmi",
1672 "VPERMILPDYmi",
1673 "VPERMILPDYrm",
1674 "VPERMILPSYmi",
1675 "VPERMILPSYrm",
1676 "VPSHUFBYrm",
1677 "VPSHUFDYmi",
1678 "VPSHUFHWYmi",
1679 "VPSHUFLWYmi",
1680 "VPUNPCKHBWYrm",
1681 "VPUNPCKHDQYrm",
1682 "VPUNPCKHQDQYrm",
1683 "VPUNPCKHWDYrm",
1684 "VPUNPCKLBWYrm",
1685 "VPUNPCKLDQYrm",
1686 "VPUNPCKLQDQYrm",
1687 "VPUNPCKLWDYrm",
1688 "VSHUFPDYrmi",
1689 "VSHUFPSYrmi",
1690 "VUNPCKHPDYrm",
1691 "VUNPCKHPSYrm",
1692 "VUNPCKLPDYrm",
1693 "VUNPCKLPSYrm",
1694 "VXORPDYrm",
1695 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1696
1697def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1698 let Latency = 7;
1699 let NumMicroOps = 2;
1700 let ResourceCycles = [1,1];
1701}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1702def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1703 "VPABSDYrm",
1704 "VPABSWYrm",
1705 "VPADDBYrm",
1706 "VPADDDYrm",
1707 "VPADDQYrm",
1708 "VPADDSBYrm",
1709 "VPADDSWYrm",
1710 "VPADDUSBYrm",
1711 "VPADDUSWYrm",
1712 "VPADDWYrm",
1713 "VPAVGBYrm",
1714 "VPAVGWYrm",
1715 "VPCMPEQBYrm",
1716 "VPCMPEQDYrm",
1717 "VPCMPEQQYrm",
1718 "VPCMPEQWYrm",
1719 "VPCMPGTBYrm",
1720 "VPCMPGTDYrm",
1721 "VPCMPGTWYrm",
1722 "VPMAXSBYrm",
1723 "VPMAXSDYrm",
1724 "VPMAXSWYrm",
1725 "VPMAXUBYrm",
1726 "VPMAXUDYrm",
1727 "VPMAXUWYrm",
1728 "VPMINSBYrm",
1729 "VPMINSDYrm",
1730 "VPMINSWYrm",
1731 "VPMINUBYrm",
1732 "VPMINUDYrm",
1733 "VPMINUWYrm",
1734 "VPSIGNBYrm",
1735 "VPSIGNDYrm",
1736 "VPSIGNWYrm",
1737 "VPSUBBYrm",
1738 "VPSUBDYrm",
1739 "VPSUBQYrm",
1740 "VPSUBSBYrm",
1741 "VPSUBSWYrm",
1742 "VPSUBUSBYrm",
1743 "VPSUBUSWYrm",
1744 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1745
1746def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1747 let Latency = 7;
1748 let NumMicroOps = 2;
1749 let ResourceCycles = [1,1];
1750}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1751def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1752 "VBLENDPSYrmi",
1753 "VPANDNYrm",
1754 "VPANDYrm",
1755 "VPBLENDDYrmi",
1756 "VPORYrm",
1757 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1758
1759def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1760 let Latency = 7;
1761 let NumMicroOps = 3;
1762 let ResourceCycles = [1,2];
1763}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1764def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1765
1766def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1767 let Latency = 7;
1768 let NumMicroOps = 3;
1769 let ResourceCycles = [2,1];
1770}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1771def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1772 "BLENDVPSrm0",
1773 "MMX_PACKSSDWirm",
1774 "MMX_PACKSSWBirm",
1775 "MMX_PACKUSWBirm",
1776 "PBLENDVBrm0",
1777 "VBLENDVPDrm",
1778 "VBLENDVPSrm",
1779 "VMASKMOVPDrm",
1780 "VMASKMOVPSrm",
1781 "VPBLENDVBrm",
1782 "VPMASKMOVDrm",
1783 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1784
1785def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1786 let Latency = 7;
1787 let NumMicroOps = 3;
1788 let ResourceCycles = [1,2];
1789}
Craig Topper3b0b96c2018-04-05 21:16:26 +0000[diff] [blame]1790def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1791 SCASB, SCASL, SCASQ, SCASW)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1792
1793def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1794 let Latency = 7;
1795 let NumMicroOps = 3;
1796 let ResourceCycles = [1,1,1];
1797}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1798def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1799 "PSLLQrm",
1800 "PSLLWrm",
1801 "PSRADrm",
1802 "PSRAWrm",
1803 "PSRLDrm",
1804 "PSRLQrm",
1805 "PSRLWrm",
1806 "PTESTrm",
1807 "VPSLLDrm",
1808 "VPSLLQrm",
1809 "VPSLLWrm",
1810 "VPSRADrm",
1811 "VPSRAWrm",
1812 "VPSRLDrm",
1813 "VPSRLQrm",
1814 "VPSRLWrm",
1815 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1816
1817def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1818 let Latency = 7;
1819 let NumMicroOps = 3;
1820 let ResourceCycles = [1,1,1];
1821}
1822def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1823
1824def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1825 let Latency = 7;
1826 let NumMicroOps = 3;
1827 let ResourceCycles = [1,1,1];
1828}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1829def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1830
1831def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1832 let Latency = 7;
1833 let NumMicroOps = 3;
1834 let ResourceCycles = [1,1,1];
1835}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1836def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1837 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1838
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1839def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1840 let Latency = 7;
1841 let NumMicroOps = 3;
1842 let ResourceCycles = [1,1,1];
1843}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1844def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1845
1846def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1847 let Latency = 7;
1848 let NumMicroOps = 5;
1849 let ResourceCycles = [1,1,1,2];
1850}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1851def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1852 "ROL(8|16|32|64)mi",
1853 "ROR(8|16|32|64)m1",
1854 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1855
1856def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1857 let Latency = 7;
1858 let NumMicroOps = 5;
1859 let ResourceCycles = [1,1,1,2];
1860}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1861def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1862
1863def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1864 let Latency = 7;
1865 let NumMicroOps = 5;
1866 let ResourceCycles = [1,1,1,1,1];
1867}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1868def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1869 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1870
1871def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1872 let Latency = 7;
1873 let NumMicroOps = 7;
1874 let ResourceCycles = [2,2,1,2];
1875}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1876def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1877
1878def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1879 let Latency = 8;
1880 let NumMicroOps = 2;
1881 let ResourceCycles = [1,1];
1882}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1883def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1884def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]1885def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1886 "MMX_CVTPS2PIirm",
1887 "MMX_CVTTPS2PIirm",
1888 "PDEP(32|64)rm",
1889 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1890 "(V?)ADDPDrm",
1891 "(V?)ADDPSrm",
1892 "(V?)ADDSDrm",
1893 "(V?)ADDSSrm",
1894 "(V?)ADDSUBPDrm",
1895 "(V?)ADDSUBPSrm",
1896 "(V?)CMPPDrmi",
1897 "(V?)CMPPSrmi",
1898 "(V?)CMPSDrm",
1899 "(V?)CMPSSrm",
1900 "(V?)COMISDrm",
1901 "(V?)COMISSrm",
1902 "(V?)CVTDQ2PSrm",
1903 "(V?)CVTPS2DQrm",
1904 "(V?)CVTTPS2DQrm",
1905 "(V?)MAX(C?)PDrm",
1906 "(V?)MAX(C?)PSrm",
1907 "(V?)MAX(C?)SDrm",
1908 "(V?)MAX(C?)SSrm",
1909 "(V?)MIN(C?)PDrm",
1910 "(V?)MIN(C?)PSrm",
1911 "(V?)MIN(C?)SDrm",
1912 "(V?)MIN(C?)SSrm",
1913 "(V?)SUBPDrm",
1914 "(V?)SUBPSrm",
1915 "(V?)SUBSDrm",
1916 "(V?)SUBSSrm",
1917 "(V?)UCOMISDrm",
1918 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1919
1920def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1921 let Latency = 8;
1922 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1923 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1924}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1925def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1926
1927def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1928 let Latency = 8;
1929 let NumMicroOps = 5;
1930}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1931def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1932
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1933def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1934 let Latency = 8;
1935 let NumMicroOps = 2;
1936 let ResourceCycles = [1,1];
1937}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1938def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1939 "VPMOVSXBQYrm",
1940 "VPMOVSXBWYrm",
1941 "VPMOVSXDQYrm",
1942 "VPMOVSXWDYrm",
1943 "VPMOVSXWQYrm",
1944 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1945
1946def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1947 let Latency = 8;
1948 let NumMicroOps = 2;
1949 let ResourceCycles = [1,1];
1950}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1951def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1952 "(V?)MULPSrm",
1953 "(V?)MULSDrm",
1954 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1955
1956def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1957 let Latency = 8;
1958 let NumMicroOps = 3;
1959 let ResourceCycles = [2,1];
1960}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1961def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1962 "VBLENDVPSYrm",
1963 "VMASKMOVPDYrm",
1964 "VMASKMOVPSYrm",
1965 "VPBLENDVBYrm",
1966 "VPMASKMOVDYrm",
1967 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1968
1969def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1970 let Latency = 8;
1971 let NumMicroOps = 4;
1972 let ResourceCycles = [2,1,1];
1973}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1974def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1975 "VPSRAVDrm",
1976 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1977
1978def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1979 let Latency = 8;
1980 let NumMicroOps = 4;
1981 let ResourceCycles = [2,1,1];
1982}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1983def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1984 "MMX_PHADDSWrm",
1985 "MMX_PHADDWrm",
1986 "MMX_PHSUBDrm",
1987 "MMX_PHSUBSWrm",
1988 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1989 "(V?)PHADDDrm",
1990 "(V?)PHADDSWrm",
1991 "(V?)PHADDWrm",
1992 "(V?)PHSUBDrm",
1993 "(V?)PHSUBSWrm",
1994 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1995
1996def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1997 let Latency = 8;
1998 let NumMicroOps = 5;
1999 let ResourceCycles = [1,1,1,2];
2000}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2001def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2002 "RCL(8|16|32|64)mi",
2003 "RCR(8|16|32|64)m1",
2004 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2005
2006def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2007 let Latency = 8;
2008 let NumMicroOps = 5;
2009 let ResourceCycles = [1,1,2,1];
2010}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2011def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2012
2013def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2014 let Latency = 8;
2015 let NumMicroOps = 6;
2016 let ResourceCycles = [1,1,1,3];
2017}
Craig Topper9f834812018-04-01 21:54:24 +0000[diff] [blame]2018def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2019
2020def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2021 let Latency = 8;
2022 let NumMicroOps = 6;
2023 let ResourceCycles = [1,1,1,2,1];
2024}
Craig Topper9f834812018-04-01 21:54:24 +0000[diff] [blame]2025def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
2026 "ADC(8|16|32|64)mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2027 "CMPXCHG(8|16|32|64)rm",
2028 "ROL(8|16|32|64)mCL",
2029 "SAR(8|16|32|64)mCL",
2030 "SBB(8|16|32|64)mi",
2031 "SBB(8|16|32|64)mr",
2032 "SHL(8|16|32|64)mCL",
2033 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2034
2035def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2036 let Latency = 9;
2037 let NumMicroOps = 2;
2038 let ResourceCycles = [1,1];
2039}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2040def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2041 "ADD_F64m",
2042 "ILD_F16m",
2043 "ILD_F32m",
2044 "ILD_F64m",
2045 "SUBR_F32m",
2046 "SUBR_F64m",
2047 "SUB_F32m",
2048 "SUB_F64m",
2049 "VADDPDYrm",
2050 "VADDPSYrm",
2051 "VADDSUBPDYrm",
2052 "VADDSUBPSYrm",
2053 "VCMPPDYrmi",
2054 "VCMPPSYrmi",
2055 "VCVTDQ2PSYrm",
2056 "VCVTPS2DQYrm",
2057 "VCVTTPS2DQYrm",
2058 "VMAX(C?)PDYrm",
2059 "VMAX(C?)PSYrm",
2060 "VMIN(C?)PDYrm",
2061 "VMIN(C?)PSYrm",
2062 "VSUBPDYrm",
2063 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2064
2065def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2066 let Latency = 9;
2067 let NumMicroOps = 2;
2068 let ResourceCycles = [1,1];
2069}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2070def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2071 "VPERM2I128rm",
2072 "VPERMDYrm",
2073 "VPERMPDYmi",
2074 "VPERMPSYrm",
2075 "VPERMQYmi",
2076 "VPMOVZXBDYrm",
2077 "VPMOVZXBQYrm",
2078 "VPMOVZXBWYrm",
2079 "VPMOVZXDQYrm",
2080 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2081
2082def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2083 let Latency = 9;
2084 let NumMicroOps = 2;
2085 let ResourceCycles = [1,1];
2086}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2087def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2088 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2089
2090def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2091 let Latency = 9;
2092 let NumMicroOps = 3;
2093 let ResourceCycles = [1,1,1];
2094}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2095def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2096
2097def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2098 let Latency = 9;
2099 let NumMicroOps = 3;
2100 let ResourceCycles = [1,1,1];
2101}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2102def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2103 "(V?)CVTSD2SIrm",
2104 "(V?)CVTSS2SI64rm",
2105 "(V?)CVTSS2SIrm",
2106 "(V?)CVTTSD2SI64rm",
2107 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2108 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2109 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2110
2111def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2112 let Latency = 9;
2113 let NumMicroOps = 3;
2114 let ResourceCycles = [1,1,1];
2115}
2116def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2117
2118def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2119 let Latency = 9;
2120 let NumMicroOps = 3;
2121 let ResourceCycles = [1,1,1];
2122}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2123def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2124def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2125 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2126 "CVTTPD2DQrm",
2127 "MMX_CVTPD2PIirm",
2128 "MMX_CVTPI2PDirm",
2129 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2130 "(V?)CVTDQ2PDrm",
2131 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2132
2133def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2134 let Latency = 9;
2135 let NumMicroOps = 3;
2136 let ResourceCycles = [1,1,1];
2137}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2138def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2139 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2140
2141def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2142 let Latency = 9;
2143 let NumMicroOps = 4;
2144 let ResourceCycles = [2,1,1];
2145}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2146def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2147 "VPSRAVDYrm",
2148 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2149
2150def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2151 let Latency = 9;
2152 let NumMicroOps = 4;
2153 let ResourceCycles = [2,1,1];
2154}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2155def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2156 "VPHADDSWYrm",
2157 "VPHADDWYrm",
2158 "VPHSUBDYrm",
2159 "VPHSUBSWYrm",
2160 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2161
2162def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2163 let Latency = 9;
2164 let NumMicroOps = 4;
2165 let ResourceCycles = [1,1,1,1];
2166}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2167def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2168 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2169
2170def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2171 let Latency = 9;
2172 let NumMicroOps = 5;
2173 let ResourceCycles = [1,1,3];
2174}
2175def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2176
2177def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2178 let Latency = 9;
2179 let NumMicroOps = 5;
2180 let ResourceCycles = [1,2,1,1];
2181}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2182def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2183 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2184
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2185def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2186 let Latency = 10;
2187 let NumMicroOps = 2;
2188 let ResourceCycles = [1,1];
2189}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2190def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2191 "MMX_PMADDWDirm",
2192 "MMX_PMULHRSWrm",
2193 "MMX_PMULHUWirm",
2194 "MMX_PMULHWirm",
2195 "MMX_PMULLWirm",
2196 "MMX_PMULUDQirm",
2197 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2198 "(V?)PCMPGTQrm",
2199 "(V?)PHMINPOSUWrm",
2200 "(V?)PMADDUBSWrm",
2201 "(V?)PMADDWDrm",
2202 "(V?)PMULDQrm",
2203 "(V?)PMULHRSWrm",
2204 "(V?)PMULHUWrm",
2205 "(V?)PMULHWrm",
2206 "(V?)PMULLWrm",
2207 "(V?)PMULUDQrm",
2208 "(V?)PSADBWrm",
2209 "(V?)RCPPSm",
2210 "(V?)RCPSSm",
2211 "(V?)RSQRTPSm",
2212 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2213
2214def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2215 let Latency = 10;
2216 let NumMicroOps = 2;
2217 let ResourceCycles = [1,1];
2218}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2219def: InstRW<[BWWriteResGroup116],
2220 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2221 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2222
2223def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2224 let Latency = 10;
2225 let NumMicroOps = 3;
2226 let ResourceCycles = [2,1];
2227}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2228def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2229 "FICOM32m",
2230 "FICOMP16m",
2231 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2232
2233def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2234 let Latency = 10;
2235 let NumMicroOps = 3;
2236 let ResourceCycles = [1,1,1];
2237}
2238def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2239
2240def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2241 let Latency = 10;
2242 let NumMicroOps = 4;
2243 let ResourceCycles = [1,2,1];
2244}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2245def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2246 "(V?)HADDPSrm",
2247 "(V?)HSUBPDrm",
2248 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2249
2250def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2251 let Latency = 10;
2252 let NumMicroOps = 4;
2253 let ResourceCycles = [1,1,1,1];
2254}
2255def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2256
2257def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2258 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2259 let NumMicroOps = 4;
2260 let ResourceCycles = [1,1,1,1];
2261}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2262def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2263
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2264def BWWriteResGroup122 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2265 let Latency = 11;
2266 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2267 let ResourceCycles = [1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2268}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2269def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr")>;
2270
2271def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2272 let Latency = 11;
2273 let NumMicroOps = 1;
2274 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
2275}
2276def: InstRW<[BWWriteResGroup122_1], (instregex "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2277
2278def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2279 let Latency = 11;
2280 let NumMicroOps = 2;
2281 let ResourceCycles = [1,1];
2282}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2283def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2284 "MUL_F64m",
2285 "VPCMPGTQYrm",
2286 "VPMADDUBSWYrm",
2287 "VPMADDWDYrm",
2288 "VPMULDQYrm",
2289 "VPMULHRSWYrm",
2290 "VPMULHUWYrm",
2291 "VPMULHWYrm",
2292 "VPMULLWYrm",
2293 "VPMULUDQYrm",
2294 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2295
2296def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2297 let Latency = 11;
2298 let NumMicroOps = 2;
2299 let ResourceCycles = [1,1];
2300}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2301def: InstRW<[BWWriteResGroup124],
2302 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2303
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2304def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2305 let Latency = 11;
2306 let NumMicroOps = 3;
2307 let ResourceCycles = [2,1];
2308}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2309def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2310 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2311
2312def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2313 let Latency = 11;
2314 let NumMicroOps = 3;
2315 let ResourceCycles = [2,1];
2316}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2317def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2318 "(V?)ROUNDPSm",
2319 "(V?)ROUNDSDm",
2320 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2321
2322def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2323 let Latency = 11;
2324 let NumMicroOps = 3;
2325 let ResourceCycles = [1,1,1];
2326}
2327def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2328
2329def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2330 let Latency = 11;
2331 let NumMicroOps = 4;
2332 let ResourceCycles = [1,2,1];
2333}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2334def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2335 "VHADDPSYrm",
2336 "VHSUBPDYrm",
2337 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2338
2339def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2340 let Latency = 11;
2341 let NumMicroOps = 6;
2342 let ResourceCycles = [1,1,1,1,2];
2343}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2344def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2345 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2346
2347def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2348 let Latency = 11;
2349 let NumMicroOps = 7;
2350 let ResourceCycles = [2,2,3];
2351}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2352def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2353 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2354
2355def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2356 let Latency = 11;
2357 let NumMicroOps = 9;
2358 let ResourceCycles = [1,4,1,3];
2359}
2360def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2361
2362def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2363 let Latency = 11;
2364 let NumMicroOps = 11;
2365 let ResourceCycles = [2,9];
2366}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2367def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2368def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2369
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2370def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2371 let Latency = 12;
2372 let NumMicroOps = 3;
2373 let ResourceCycles = [2,1];
2374}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2375def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2376 "ADD_FI32m",
2377 "SUBR_FI16m",
2378 "SUBR_FI32m",
2379 "SUB_FI16m",
2380 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2381 "VROUNDPDYm",
2382 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2383
2384def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2385 let Latency = 12;
2386 let NumMicroOps = 4;
2387 let ResourceCycles = [1,2,1];
2388}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2389def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2390
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2391def BWWriteResGroup137 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2392 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2393 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2394 let ResourceCycles = [1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2395}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2396def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr")>;
2397
2398def BWWriteResGroup137_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2399 let Latency = 11;
2400 let NumMicroOps = 1;
2401 let ResourceCycles = [1,4];
2402}
2403def: InstRW<[BWWriteResGroup137_1], (instregex "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2404
2405def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2406 let Latency = 13;
2407 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2408 let ResourceCycles = [1,2,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2409}
2410def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2411
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2412def BWWriteResGroup139 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2413 let Latency = 14;
2414 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2415 let ResourceCycles = [1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2416}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2417def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr")>;
2418
2419def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2420 let Latency = 14;
2421 let NumMicroOps = 1;
2422 let ResourceCycles = [1,4];
2423}
2424def: InstRW<[BWWriteResGroup139_1], (instregex "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2425
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2426def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2427 let Latency = 14;
2428 let NumMicroOps = 3;
2429 let ResourceCycles = [1,1,1];
2430}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2431def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2432 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2433
2434def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2435 let Latency = 14;
2436 let NumMicroOps = 4;
2437 let ResourceCycles = [2,1,1];
2438}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2439def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2440
2441def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2442 let Latency = 14;
2443 let NumMicroOps = 4;
2444 let ResourceCycles = [1,1,1,1];
2445}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2446def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2447
2448def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2449 let Latency = 14;
2450 let NumMicroOps = 8;
2451 let ResourceCycles = [2,2,1,3];
2452}
2453def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2454
2455def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2456 let Latency = 14;
2457 let NumMicroOps = 10;
2458 let ResourceCycles = [2,3,1,4];
2459}
2460def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2461
2462def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2463 let Latency = 14;
2464 let NumMicroOps = 12;
2465 let ResourceCycles = [2,1,4,5];
2466}
2467def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2468
2469def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2470 let Latency = 15;
2471 let NumMicroOps = 1;
2472 let ResourceCycles = [1];
2473}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2474def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2475 "DIVR_FST0r",
2476 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2477
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2478def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2479 let Latency = 15;
2480 let NumMicroOps = 10;
2481 let ResourceCycles = [1,1,1,4,1,2];
2482}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2483def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2484
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2485def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2486 let Latency = 16;
2487 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2488 let ResourceCycles = [1,1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2489}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2490def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2491 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2492
2493def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2494 let Latency = 16;
2495 let NumMicroOps = 3;
2496 let ResourceCycles = [2,1];
2497}
2498def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2499
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2500def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2501 let Latency = 16;
2502 let NumMicroOps = 14;
2503 let ResourceCycles = [1,1,1,4,2,5];
2504}
2505def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2506
2507def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2508 let Latency = 16;
2509 let NumMicroOps = 16;
2510 let ResourceCycles = [16];
2511}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2512def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2513
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2514def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2515 let Latency = 17;
2516 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2517 let ResourceCycles = [2,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2518}
2519def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2520
2521def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2522 let Latency = 17;
2523 let NumMicroOps = 4;
2524 let ResourceCycles = [2,1,1];
2525}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2526def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2527 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2528
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2529def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2530 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2531 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2532 let ResourceCycles = [1,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2533}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2534def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
2535 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2536
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2537def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2538 let Latency = 18;
2539 let NumMicroOps = 8;
2540 let ResourceCycles = [1,1,1,5];
2541}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2542def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2543def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2544
2545def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2546 let Latency = 18;
2547 let NumMicroOps = 11;
2548 let ResourceCycles = [2,1,1,3,1,3];
2549}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2550def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2551
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2552def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2553 let Latency = 19;
2554 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2555 let ResourceCycles = [1,1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2556}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2557def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2558 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2559
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2560def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2561 let Latency = 19;
2562 let NumMicroOps = 5;
2563 let ResourceCycles = [2,1,1,1];
2564}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2565def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2566
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2567def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2568 let Latency = 20;
2569 let NumMicroOps = 1;
2570 let ResourceCycles = [1];
2571}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2572def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2573 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2574 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2575
2576def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2577 let Latency = 20;
2578 let NumMicroOps = 5;
2579 let ResourceCycles = [2,1,1,1];
2580}
2581def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2582
2583def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2584 let Latency = 20;
2585 let NumMicroOps = 8;
2586 let ResourceCycles = [1,1,1,1,1,1,2];
2587}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2588def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2589 "INSL",
2590 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2591
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2592def BWWriteResGroup168 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2593 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2594 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2595 let ResourceCycles = [1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2596}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2597def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr")>;
2598
2599def BWWriteResGroup168_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2600 let Latency = 16;
2601 let NumMicroOps = 1;
2602 let ResourceCycles = [1,8];
2603}
2604def: InstRW<[BWWriteResGroup168_1], (instregex "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2605
2606def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2607 let Latency = 21;
2608 let NumMicroOps = 2;
2609 let ResourceCycles = [1,1];
2610}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2611def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2612 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2613
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2614def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2615 let Latency = 21;
2616 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2617 let ResourceCycles = [2,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2618}
2619def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2620
2621def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2622 let Latency = 21;
2623 let NumMicroOps = 19;
2624 let ResourceCycles = [2,1,4,1,1,4,6];
2625}
2626def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2627
2628def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2629 let Latency = 22;
2630 let NumMicroOps = 18;
2631 let ResourceCycles = [1,1,16];
2632}
2633def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2634
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2635def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2636 let Latency = 23;
2637 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2638 let ResourceCycles = [2,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2639}
2640def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2641
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2642def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2643 let Latency = 23;
2644 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2645 let ResourceCycles = [2,1,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2646}
2647def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2648
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2649def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2650 let Latency = 23;
2651 let NumMicroOps = 19;
2652 let ResourceCycles = [3,1,15];
2653}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2654def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2655
2656def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2657 let Latency = 24;
2658 let NumMicroOps = 3;
2659 let ResourceCycles = [1,1,1];
2660}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2661def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2662 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2663
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2664def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2665 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2666 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2667 let ResourceCycles = [1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2668}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2669def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2670 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2671
2672def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2673 let Latency = 26;
2674 let NumMicroOps = 2;
2675 let ResourceCycles = [1,1];
2676}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2677def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2678 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2679
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2680def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2681 let Latency = 27;
2682 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2683 let ResourceCycles = [2,1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2684}
2685def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2686
2687def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2688 let Latency = 29;
2689 let NumMicroOps = 3;
2690 let ResourceCycles = [1,1,1];
2691}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2692def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2693 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2694
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2695def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2696 let Latency = 29;
2697 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2698 let ResourceCycles = [2,1,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2699}
2700def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2701
2702def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2703 let Latency = 22;
2704 let NumMicroOps = 7;
2705 let ResourceCycles = [1,3,2,1];
2706}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2707def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2708
2709def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2710 let Latency = 23;
2711 let NumMicroOps = 9;
2712 let ResourceCycles = [1,3,4,1];
2713}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2714def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2715
2716def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2717 let Latency = 24;
2718 let NumMicroOps = 9;
2719 let ResourceCycles = [1,5,2,1];
2720}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2721def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2722
2723def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2724 let Latency = 25;
2725 let NumMicroOps = 7;
2726 let ResourceCycles = [1,3,2,1];
2727}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2728def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2729 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2730
2731def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2732 let Latency = 26;
2733 let NumMicroOps = 9;
2734 let ResourceCycles = [1,5,2,1];
2735}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2736def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2737
2738def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2739 let Latency = 26;
2740 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2741 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2742}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2743def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2744
2745def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2746 let Latency = 27;
2747 let NumMicroOps = 9;
2748 let ResourceCycles = [1,5,2,1];
2749}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2750def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2751
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2752def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2753 let Latency = 29;
2754 let NumMicroOps = 27;
2755 let ResourceCycles = [1,5,1,1,19];
2756}
2757def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2758
2759def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2760 let Latency = 30;
2761 let NumMicroOps = 28;
2762 let ResourceCycles = [1,6,1,1,19];
2763}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2764def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2765
2766def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2767 let Latency = 31;
2768 let NumMicroOps = 31;
2769 let ResourceCycles = [8,1,21,1];
2770}
2771def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2772
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2773def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
2774 let Latency = 29;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2775 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2776 let ResourceCycles = [2,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2777}
2778def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2779
2780def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2781 let Latency = 34;
2782 let NumMicroOps = 8;
2783 let ResourceCycles = [2,2,2,1,1];
2784}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2785def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2786
2787def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2788 let Latency = 34;
2789 let NumMicroOps = 23;
2790 let ResourceCycles = [1,5,3,4,10];
2791}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2792def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2793 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2794
2795def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2796 let Latency = 35;
2797 let NumMicroOps = 8;
2798 let ResourceCycles = [2,2,2,1,1];
2799}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2800def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2801
2802def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2803 let Latency = 35;
2804 let NumMicroOps = 23;
2805 let ResourceCycles = [1,5,2,1,4,10];
2806}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2807def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2808 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2809
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2810def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
2811 let Latency = 35;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2812 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2813 let ResourceCycles = [2,1,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2814}
2815def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2816
2817def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2818 let Latency = 42;
2819 let NumMicroOps = 22;
2820 let ResourceCycles = [2,20];
2821}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2822def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2823
2824def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2825 let Latency = 60;
2826 let NumMicroOps = 64;
2827 let ResourceCycles = [2,2,8,1,10,2,39];
2828}
2829def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2830
2831def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2832 let Latency = 63;
2833 let NumMicroOps = 88;
2834 let ResourceCycles = [4,4,31,1,2,1,45];
2835}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2836def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2837
2838def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2839 let Latency = 63;
2840 let NumMicroOps = 90;
2841 let ResourceCycles = [4,2,33,1,2,1,47];
2842}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2843def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2844
2845def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2846 let Latency = 75;
2847 let NumMicroOps = 15;
2848 let ResourceCycles = [6,3,6];
2849}
2850def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2851
2852def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2853 let Latency = 80;
2854 let NumMicroOps = 32;
2855 let ResourceCycles = [7,7,3,3,1,11];
2856}
2857def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2858
2859def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2860 let Latency = 115;
2861 let NumMicroOps = 100;
2862 let ResourceCycles = [9,9,11,8,1,11,21,30];
2863}
2864def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2865
2866} // SchedModel
2867