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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng549f27d32007-08-13 23:45:17 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL),
Evan Cheng2638e1a2007-03-20 08:13:50 +000067 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000072 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
73 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
76 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000077}
78
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
80 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000081 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000083 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
84 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
85 RC->getAlignment());
86 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 ++NumSpills;
88 return frameIndex;
89}
90
91void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
92 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000093 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000094 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000095 assert((frameIndex >= 0 ||
96 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
97 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000098 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000099}
100
Evan Cheng2638e1a2007-03-20 08:13:50 +0000101int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
102 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000103 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000104 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000105 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000106 return ReMatId++;
107}
108
Evan Cheng549f27d32007-08-13 23:45:17 +0000109void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
110 assert(MRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign re-mat id to already spilled register");
113 Virt2ReMatIdMap[virtReg] = id;
114}
115
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000117 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000118 // Move previous memory references folded to new instruction.
119 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000120 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
122 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000123 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000125
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000126 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000127 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
128 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000129 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000130 // Folded a two-address operand.
131 MRInfo = isModRef;
132 } else if (OldMI->getOperand(OpNo).isDef()) {
133 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000135 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000136 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000139 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000140}
141
Chris Lattner7f690e62004-09-30 02:15:18 +0000142void VirtRegMap::print(std::ostream &OS) const {
143 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000144
Chris Lattner7f690e62004-09-30 02:15:18 +0000145 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000147 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
148 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
149 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000150
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000151 }
152
153 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000154 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
155 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
156 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
157 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000158}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000159
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000160void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000161 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000162}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000163
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
165//===----------------------------------------------------------------------===//
166// Simple Spiller Implementation
167//===----------------------------------------------------------------------===//
168
169Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000170
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000171namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000172 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000173 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000174 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000175}
176
Chris Lattner35f27052006-05-01 21:16:03 +0000177bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000178 DOUT << "********** REWRITE MACHINE CODE **********\n";
179 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000180 const TargetMachine &TM = MF.getTarget();
181 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000182
Chris Lattner4ea1b822004-09-30 02:33:48 +0000183 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
184 // each vreg once (in the case where a spilled vreg is used by multiple
185 // operands). This is always smaller than the number of operands to the
186 // current machine instr, so it should be small.
187 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000188
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000189 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
190 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000191 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000192 MachineBasicBlock &MBB = *MBBI;
193 for (MachineBasicBlock::iterator MII = MBB.begin(),
194 E = MBB.end(); MII != E; ++MII) {
195 MachineInstr &MI = *MII;
196 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000197 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 if (MO.isRegister() && MO.getReg())
199 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
200 unsigned VirtReg = MO.getReg();
201 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000202 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000203 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 const TargetRegisterClass* RC =
205 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000206
Chris Lattner886dd912005-04-04 21:35:34 +0000207 if (MO.isUse() &&
208 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
209 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000210 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000211 LoadedRegs.push_back(VirtReg);
212 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000213 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000214 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000215
Chris Lattner886dd912005-04-04 21:35:34 +0000216 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000217 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 ++NumStores;
219 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000220 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000221 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000222 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000223 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000224 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
Chris Lattner886dd912005-04-04 21:35:34 +0000227
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000228 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000229 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000230 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 }
232 return true;
233}
234
235//===----------------------------------------------------------------------===//
236// Local Spiller Implementation
237//===----------------------------------------------------------------------===//
238
239namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000240 /// LocalSpiller - This spiller does a simple pass over the machine basic
241 /// block to attempt to keep spills in registers as much as possible for
242 /// blocks that have low register pressure (the vreg may be spilled due to
243 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000244 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000245 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000246 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000247 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000248 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000249 MRI = MF.getTarget().getRegisterInfo();
250 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000251 DOUT << "\n**** Local spiller rewriting function '"
252 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000253
Chris Lattner7fb64342004-10-01 19:04:51 +0000254 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
255 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000256 RewriteMBB(*MBB, VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000257 return true;
258 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000259 private:
Evan Cheng549f27d32007-08-13 23:45:17 +0000260 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000261 };
262}
263
Chris Lattner66cf80f2006-02-03 23:13:58 +0000264/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000265/// top down, keep track of which spills slots or remat are available in each
266/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000267///
268/// Note that not all physregs are created equal here. In particular, some
269/// physregs are reloads that we are allowed to clobber or ignore at any time.
270/// Other physregs are values that the register allocated program is using that
271/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000272/// per-stack-slot / remat id basis as the low bit in the value of the
273/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
274/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000275namespace {
276class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000277 const MRegisterInfo *MRI;
278 const TargetInstrInfo *TII;
279
Evan Cheng549f27d32007-08-13 23:45:17 +0000280 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
281 // or remat'ed virtual register values that are still available, due to being
282 // loaded or stored to, but not invalidated yet.
283 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284
Evan Cheng549f27d32007-08-13 23:45:17 +0000285 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
286 // indicating which stack slot values are currently held by a physreg. This
287 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
288 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289 std::multimap<unsigned, int> PhysRegsAvailable;
290
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000291 void disallowClobberPhysRegOnly(unsigned PhysReg);
292
Chris Lattner66cf80f2006-02-03 23:13:58 +0000293 void ClobberPhysRegOnly(unsigned PhysReg);
294public:
295 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
296 : MRI(mri), TII(tii) {
297 }
298
Evan Cheng91e23902007-02-23 01:13:26 +0000299 const MRegisterInfo *getRegInfo() const { return MRI; }
300
Evan Cheng549f27d32007-08-13 23:45:17 +0000301 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
302 /// available in a physical register, return that PhysReg, otherwise
303 /// return 0.
304 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
305 std::map<int, unsigned>::const_iterator I =
306 SpillSlotsOrReMatsAvailable.find(Slot);
307 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000308 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000309 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000310 return 0;
311 }
Evan Chengde4e9422007-02-25 09:51:27 +0000312
Evan Cheng549f27d32007-08-13 23:45:17 +0000313 /// addAvailable - Mark that the specified stack slot / remat is available in
314 /// the specified physreg. If CanClobber is true, the physreg can be modified
315 /// at any time without changing the semantics of the program.
316 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000317 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000318 // If this stack slot is thought to be available in some other physreg,
319 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000320 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000321
Evan Cheng549f27d32007-08-13 23:45:17 +0000322 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
Evan Cheng90a43c32007-08-15 20:20:34 +0000323 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000324
Evan Cheng549f27d32007-08-13 23:45:17 +0000325 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
326 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000327 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000328 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000329 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000330 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000331
Chris Lattner593c9582006-02-03 23:28:46 +0000332 /// canClobberPhysReg - Return true if the spiller is allowed to change the
333 /// value of the specified stackslot register if it desires. The specified
334 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000335 bool canClobberPhysReg(int SlotOrReMat) const {
Evan Cheng90a43c32007-08-15 20:20:34 +0000336 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
337 "Value not available!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000338 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000339 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000340
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000341 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
342 /// stackslot register. The register is still available but is no longer
343 /// allowed to be modifed.
344 void disallowClobberPhysReg(unsigned PhysReg);
345
Chris Lattner66cf80f2006-02-03 23:13:58 +0000346 /// ClobberPhysReg - This is called when the specified physreg changes
347 /// value. We use this to invalidate any info about stuff we thing lives in
348 /// it and any of its aliases.
349 void ClobberPhysReg(unsigned PhysReg);
350
Evan Cheng90a43c32007-08-15 20:20:34 +0000351 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
352 /// slot changes. This removes information about which register the previous
353 /// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000354 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000355};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000356}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000357
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000358/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
359/// stackslot register. The register is still available but is no longer
360/// allowed to be modifed.
361void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
362 std::multimap<unsigned, int>::iterator I =
363 PhysRegsAvailable.lower_bound(PhysReg);
364 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000365 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000366 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000367 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000368 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000369 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000370 DOUT << "PhysReg " << MRI->getName(PhysReg)
371 << " copied, it is available for use but can no longer be modified\n";
372 }
373}
374
375/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
376/// stackslot register and its aliases. The register and its aliases may
377/// still available but is no longer allowed to be modifed.
378void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
379 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
380 disallowClobberPhysRegOnly(*AS);
381 disallowClobberPhysRegOnly(PhysReg);
382}
383
Chris Lattner66cf80f2006-02-03 23:13:58 +0000384/// ClobberPhysRegOnly - This is called when the specified physreg changes
385/// value. We use this to invalidate any info about stuff we thing lives in it.
386void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
387 std::multimap<unsigned, int>::iterator I =
388 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000389 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000390 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000391 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000392 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000393 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000394 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000395 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000396 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000397 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
398 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000399 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000400 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000401 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000402}
403
Chris Lattner66cf80f2006-02-03 23:13:58 +0000404/// ClobberPhysReg - This is called when the specified physreg changes
405/// value. We use this to invalidate any info about stuff we thing lives in
406/// it and any of its aliases.
407void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000408 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000409 ClobberPhysRegOnly(*AS);
410 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000411}
412
Evan Cheng90a43c32007-08-15 20:20:34 +0000413/// ModifyStackSlotOrReMat - This method is called when the value in a stack
414/// slot changes. This removes information about which register the previous
415/// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000416void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
Evan Cheng90a43c32007-08-15 20:20:34 +0000417 std::map<int, unsigned>::iterator It =
418 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
Evan Cheng549f27d32007-08-13 23:45:17 +0000419 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000420 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000421 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000422
423 // This register may hold the value of multiple stack slots, only remove this
424 // stack slot from the set of values the register contains.
425 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
426 for (; ; ++I) {
427 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
428 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000429 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000430 }
431 PhysRegsAvailable.erase(I);
432}
433
434
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000435
Evan Cheng28bb4622007-07-11 19:17:18 +0000436/// InvalidateKills - MI is going to be deleted. If any of its operands are
437/// marked kill, then invalidate the information.
438static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000439 std::vector<MachineOperand*> &KillOps,
Evan Chengb6ca4b32007-08-14 23:25:37 +0000440 SmallVector<unsigned, 1> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000441 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
442 MachineOperand &MO = MI.getOperand(i);
443 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
444 continue;
445 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000446 if (KillRegs)
447 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000448 if (KillOps[Reg] == &MO) {
449 RegKills.reset(Reg);
450 KillOps[Reg] = NULL;
451 }
452 }
453}
454
Evan Chengb6ca4b32007-08-14 23:25:37 +0000455/// InvalidateRegDef - If the def operand of the specified def MI is now dead
456/// (since it's spill instruction is removed), mark it isDead. Also checks if
457/// the def MI has other definition operands that are not dead. Returns it by
458/// reference.
459static bool InvalidateRegDef(MachineBasicBlock::iterator I,
460 MachineInstr &NewDef, unsigned Reg,
461 bool &HasLiveDef) {
462 // Due to remat, it's possible this reg isn't being reused. That is,
463 // the def of this reg (by prev MI) is now dead.
464 MachineInstr *DefMI = I;
465 MachineOperand *DefOp = NULL;
466 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
467 MachineOperand &MO = DefMI->getOperand(i);
468 if (MO.isReg() && MO.isDef()) {
469 if (MO.getReg() == Reg)
470 DefOp = &MO;
471 else if (!MO.isDead())
472 HasLiveDef = true;
473 }
474 }
475 if (!DefOp)
476 return false;
477
478 bool FoundUse = false, Done = false;
479 MachineBasicBlock::iterator E = NewDef;
480 ++I; ++E;
481 for (; !Done && I != E; ++I) {
482 MachineInstr *NMI = I;
483 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
484 MachineOperand &MO = NMI->getOperand(j);
485 if (!MO.isReg() || MO.getReg() != Reg)
486 continue;
487 if (MO.isUse())
488 FoundUse = true;
489 Done = true; // Stop after scanning all the operands of this MI.
490 }
491 }
492 if (!FoundUse) {
493 // Def is dead!
494 DefOp->setIsDead();
495 return true;
496 }
497 return false;
498}
499
Evan Cheng28bb4622007-07-11 19:17:18 +0000500/// UpdateKills - Track and update kill info. If a MI reads a register that is
501/// marked kill, then it must be due to register reuse. Transfer the kill info
502/// over.
503static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
504 std::vector<MachineOperand*> &KillOps) {
505 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
506 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
507 MachineOperand &MO = MI.getOperand(i);
508 if (!MO.isReg() || !MO.isUse())
509 continue;
510 unsigned Reg = MO.getReg();
511 if (Reg == 0)
512 continue;
513
514 if (RegKills[Reg]) {
515 // That can't be right. Register is killed but not re-defined and it's
516 // being reused. Let's fix that.
517 KillOps[Reg]->unsetIsKill();
518 if (i < TID->numOperands &&
519 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
520 // Unless it's a two-address operand, this is the new kill.
521 MO.setIsKill();
522 }
523
524 if (MO.isKill()) {
525 RegKills.set(Reg);
526 KillOps[Reg] = &MO;
527 }
528 }
529
530 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
531 const MachineOperand &MO = MI.getOperand(i);
532 if (!MO.isReg() || !MO.isDef())
533 continue;
534 unsigned Reg = MO.getReg();
535 RegKills.reset(Reg);
536 KillOps[Reg] = NULL;
537 }
538}
539
540
Chris Lattner7fb64342004-10-01 19:04:51 +0000541// ReusedOp - For each reused operand, we keep track of a bit of information, in
542// case we need to rollback upon processing a new operand. See comments below.
543namespace {
544 struct ReusedOp {
545 // The MachineInstr operand that reused an available value.
546 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000547
Evan Cheng549f27d32007-08-13 23:45:17 +0000548 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
549 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000550
Chris Lattner7fb64342004-10-01 19:04:51 +0000551 // PhysRegReused - The physical register the value was available in.
552 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000553
Chris Lattner7fb64342004-10-01 19:04:51 +0000554 // AssignedPhysReg - The physreg that was assigned for use by the reload.
555 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000556
557 // VirtReg - The virtual register itself.
558 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000559
Chris Lattner8a61a752005-10-06 17:19:06 +0000560 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
561 unsigned vreg)
Evan Cheng90a43c32007-08-15 20:20:34 +0000562 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
563 AssignedPhysReg(apr), VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000564 };
Chris Lattner540fec62006-02-25 01:51:33 +0000565
566 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
567 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000568 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000569 MachineInstr &MI;
570 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000571 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000572 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000573 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000574 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000575 }
Chris Lattner540fec62006-02-25 01:51:33 +0000576
577 bool hasReuses() const {
578 return !Reuses.empty();
579 }
580
581 /// addReuse - If we choose to reuse a virtual register that is already
582 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000583 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000584 unsigned PhysRegReused, unsigned AssignedPhysReg,
585 unsigned VirtReg) {
586 // If the reload is to the assigned register anyway, no undo will be
587 // required.
588 if (PhysRegReused == AssignedPhysReg) return;
589
590 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000591 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000592 AssignedPhysReg, VirtReg));
593 }
Evan Chenge077ef62006-11-04 00:21:55 +0000594
595 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000596 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000597 }
598
599 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000600 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000601 }
Chris Lattner540fec62006-02-25 01:51:33 +0000602
603 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
604 /// is some other operand that is using the specified register, either pick
605 /// a new register to use, or evict the previous reload and use this reg.
606 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
607 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000608 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000609 SmallSet<unsigned, 8> &Rejected,
610 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000611 std::vector<MachineOperand*> &KillOps,
612 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000613 if (Reuses.empty()) return PhysReg; // This is most often empty.
614
615 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
616 ReusedOp &Op = Reuses[ro];
617 // If we find some other reuse that was supposed to use this register
618 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000619 // register. That is, unless its reload register has already been
620 // considered and subsequently rejected because it has also been reused
621 // by another operand.
622 if (Op.PhysRegReused == PhysReg &&
623 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000624 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000625 unsigned NewReg = Op.AssignedPhysReg;
626 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000627 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000628 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000629 } else {
630 // Otherwise, we might also have a problem if a previously reused
631 // value aliases the new register. If so, codegen the previous reload
632 // and use this one.
633 unsigned PRRU = Op.PhysRegReused;
634 const MRegisterInfo *MRI = Spills.getRegInfo();
635 if (MRI->areAliases(PRRU, PhysReg)) {
636 // Okay, we found out that an alias of a reused register
637 // was used. This isn't good because it means we have
638 // to undo a previous reuse.
639 MachineBasicBlock *MBB = MI->getParent();
640 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000641 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
642
643 // Copy Op out of the vector and remove it, we're going to insert an
644 // explicit load for it.
645 ReusedOp NewOp = Op;
646 Reuses.erase(Reuses.begin()+ro);
647
648 // Ok, we're going to try to reload the assigned physreg into the
649 // slot that we were supposed to in the first place. However, that
650 // register could hold a reuse. Check to see if it conflicts or
651 // would prefer us to use a different register.
652 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000653 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000654 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000655
Evan Cheng549f27d32007-08-13 23:45:17 +0000656 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
657 MRI->reMaterialize(*MBB, MI, NewPhysReg,
658 VRM.getReMaterializedMI(NewOp.VirtReg));
659 ++NumReMats;
660 } else {
661 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
662 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000663 // Any stores to this stack slot are not dead anymore.
664 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000665 ++NumLoads;
666 }
Chris Lattner28bad082006-02-25 02:17:31 +0000667 Spills.ClobberPhysReg(NewPhysReg);
668 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000669
Chris Lattnere53f4a02006-05-04 17:52:23 +0000670 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000671
Evan Cheng549f27d32007-08-13 23:45:17 +0000672 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000673 MachineBasicBlock::iterator MII = MI;
674 --MII;
675 UpdateKills(*MII, RegKills, KillOps);
676 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000677
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000678 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000679 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000680
681 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000682 return PhysReg;
683 }
684 }
685 }
686 return PhysReg;
687 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000688
689 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
690 /// 'Rejected' set to remember which registers have been considered and
691 /// rejected for the reload. This avoids infinite looping in case like
692 /// this:
693 /// t1 := op t2, t3
694 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
695 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
696 /// t1 <- desires r1
697 /// sees r1 is taken by t2, tries t2's reload register r0
698 /// sees r0 is taken by t3, tries t3's reload register r1
699 /// sees r1 is taken by t2, tries t2's reload register r0 ...
700 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
701 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000702 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000703 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000704 std::vector<MachineOperand*> &KillOps,
705 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000706 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000707 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000708 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000709 }
Chris Lattner540fec62006-02-25 01:51:33 +0000710 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000711}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000712
Chris Lattner7fb64342004-10-01 19:04:51 +0000713
714/// rewriteMBB - Keep track of which spills are available even after the
715/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000716void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000717 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000718
Evan Chengfff3e192007-08-14 09:11:18 +0000719 MachineFunction &MF = *MBB.getParent();
720
Chris Lattner66cf80f2006-02-03 23:13:58 +0000721 // Spills - Keep track of which spilled values are available in physregs so
722 // that we can choose to reuse the physregs instead of emitting reloads.
723 AvailableSpills Spills(MRI, TII);
724
Chris Lattner52b25db2004-10-01 19:47:12 +0000725 // MaybeDeadStores - When we need to write a value back into a stack slot,
726 // keep track of the inserted store. If the stack slot value is never read
727 // (because the value was used from some available register, for example), and
728 // subsequently stored to, the original store is dead. This map keeps track
729 // of inserted stores that are not used. If we see a subsequent store to the
730 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000731 std::vector<MachineInstr*> MaybeDeadStores;
732 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000733
Evan Chengb6ca4b32007-08-14 23:25:37 +0000734 // ReMatDefs - These are rematerializable def MIs which are not deleted.
735 SmallSet<MachineInstr*, 4> ReMatDefs;
736
Evan Cheng0c40d722007-07-11 05:28:39 +0000737 // Keep track of kill information.
738 BitVector RegKills(MRI->getNumRegs());
739 std::vector<MachineOperand*> KillOps;
740 KillOps.resize(MRI->getNumRegs(), NULL);
741
Chris Lattner7fb64342004-10-01 19:04:51 +0000742 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
743 MII != E; ) {
744 MachineInstr &MI = *MII;
745 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000746 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
747
748 bool Erased = false;
749 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000750
Chris Lattner540fec62006-02-25 01:51:33 +0000751 /// ReusedOperands - Keep track of operand reuse in case we need to undo
752 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000753 ReuseInfo ReusedOperands(MI, MRI);
754
755 // Loop over all of the implicit defs, clearing them from our available
756 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000757 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng0c40d722007-07-11 05:28:39 +0000758 if (TID->ImplicitDefs) {
759 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000760 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000761 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000762 ReusedOperands.markClobbered(*ImpDef);
763 Spills.ClobberPhysReg(*ImpDef);
764 }
765 }
766
Chris Lattner7fb64342004-10-01 19:04:51 +0000767 // Process all of the spilled uses and all non spilled reg references.
768 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
769 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000770 if (!MO.isRegister() || MO.getReg() == 0)
771 continue; // Ignore non-register operands.
772
773 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
774 // Ignore physregs for spilling, but remember that it is used by this
775 // function.
Evan Cheng6c087e52007-04-25 22:13:27 +0000776 MF.setPhysRegUsed(MO.getReg());
Evan Chenge077ef62006-11-04 00:21:55 +0000777 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000778 continue;
779 }
780
781 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
782 "Not a virtual or a physical register?");
783
784 unsigned VirtReg = MO.getReg();
Evan Cheng549f27d32007-08-13 23:45:17 +0000785 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000786 // This virtual register was assigned a physreg!
787 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000788 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000789 if (MO.isDef())
790 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000791 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000792 continue;
793 }
794
795 // This virtual register is now known to be a spilled value.
796 if (!MO.isUse())
797 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000798
Evan Cheng549f27d32007-08-13 23:45:17 +0000799 bool DoReMat = VRM.isReMaterialized(VirtReg);
800 int SSorRMId = DoReMat
801 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +0000802 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +0000803
Chris Lattner50ea01e2005-09-09 20:29:51 +0000804 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +0000805 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
806 if (!PhysReg && DoReMat) {
807 // This use is rematerializable. But perhaps the value is available in
808 // stack if the definition is not deleted. If so, check if we can
809 // reuse the value.
810 ReuseSlot = VRM.getStackSlot(VirtReg);
811 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
812 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
813 }
814 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000815 // This spilled operand might be part of a two-address operand. If this
816 // is the case, then changing it will necessarily require changing the
817 // def part of the instruction as well. However, in some cases, we
818 // aren't allowed to modify the reused register. If none of these cases
819 // apply, reuse it.
820 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000821 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000822 if (ti != -1 &&
823 MI.getOperand(ti).isReg() &&
824 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000825 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000826 // long as we are allowed to clobber the value and there isn't an
827 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +0000828 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +0000829 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000830 }
831
832 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000833 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000834 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
835 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000836 else
Evan Chengdc6be192007-08-14 05:42:54 +0000837 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000838 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000839 << MRI->getName(PhysReg) << " for vreg"
840 << VirtReg <<" instead of reloading into physreg "
841 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000842 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000843
844 // The only technical detail we have is that we don't know that
845 // PhysReg won't be clobbered by a reloaded stack slot that occurs
846 // later in the instruction. In particular, consider 'op V1, V2'.
847 // If V1 is available in physreg R0, we would choose to reuse it
848 // here, instead of reloading it into the register the allocator
849 // indicated (say R1). However, V2 might have to be reloaded
850 // later, and it might indicate that it needs to live in R0. When
851 // this occurs, we need to have information available that
852 // indicates it is safe to use R1 for the reload instead of R0.
853 //
854 // To further complicate matters, we might conflict with an alias,
855 // or R0 and R1 might not be compatible with each other. In this
856 // case, we actually insert a reload for V1 in R1, ensuring that
857 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +0000858 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +0000859 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000860 if (ti != -1)
861 // Only mark it clobbered if this is a use&def operand.
862 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000863 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +0000864
865 if (MI.getOperand(i).isKill() &&
866 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
867 // This was the last use and the spilled value is still available
868 // for reuse. That means the spill was unnecessary!
869 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
870 if (DeadStore) {
871 DOUT << "Removed dead store:\t" << *DeadStore;
872 InvalidateKills(*DeadStore, RegKills, KillOps);
873 MBB.erase(DeadStore);
874 VRM.RemoveFromFoldedVirtMap(DeadStore);
875 MaybeDeadStores[ReuseSlot] = NULL;
876 ++NumDSE;
877 }
878 }
Chris Lattneraddc55a2006-04-28 01:46:50 +0000879 continue;
880 }
881
882 // Otherwise we have a situation where we have a two-address instruction
883 // whose mod/ref operand needs to be reloaded. This reload is already
884 // available in some register "PhysReg", but if we used PhysReg as the
885 // operand to our 2-addr instruction, the instruction would modify
886 // PhysReg. This isn't cool if something later uses PhysReg and expects
887 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000888 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000889 // To avoid this problem, and to avoid doing a load right after a store,
890 // we emit a copy from PhysReg into the designated register for this
891 // operand.
892 unsigned DesignatedReg = VRM.getPhys(VirtReg);
893 assert(DesignatedReg && "Must map virtreg to physreg!");
894
895 // Note that, if we reused a register for a previous operand, the
896 // register we want to reload into might not actually be
897 // available. If this occurs, use the register indicated by the
898 // reuser.
899 if (ReusedOperands.hasReuses())
900 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000901 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000902
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000903 // If the mapped designated register is actually the physreg we have
904 // incoming, we don't need to inserted a dead copy.
905 if (DesignatedReg == PhysReg) {
906 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000907 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
908 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000909 else
Evan Chengdc6be192007-08-14 05:42:54 +0000910 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000911 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000912 << VirtReg
913 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000914 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000915 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000916 ++NumReused;
917 continue;
918 }
919
Evan Cheng6c087e52007-04-25 22:13:27 +0000920 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
921 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000922 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000923 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000924
Evan Cheng6b448092007-03-02 08:52:00 +0000925 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000926 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000927
Chris Lattneraddc55a2006-04-28 01:46:50 +0000928 // This invalidates DesignatedReg.
929 Spills.ClobberPhysReg(DesignatedReg);
930
Evan Chengdc6be192007-08-14 05:42:54 +0000931 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000932 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000934 ++NumReused;
935 continue;
936 }
937
938 // Otherwise, reload it and remember that we have it.
939 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000940 assert(PhysReg && "Must map virtreg to physreg!");
Evan Cheng6c087e52007-04-25 22:13:27 +0000941 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000942
Chris Lattner50ea01e2005-09-09 20:29:51 +0000943 // Note that, if we reused a register for a previous operand, the
944 // register we want to reload into might not actually be
945 // available. If this occurs, use the register indicated by the
946 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000947 if (ReusedOperands.hasReuses())
948 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000949 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000950
Evan Cheng6c087e52007-04-25 22:13:27 +0000951 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000952 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000953 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000954 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000955 ++NumReMats;
956 } else {
Evan Cheng549f27d32007-08-13 23:45:17 +0000957 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000958 ++NumLoads;
959 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000960 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000961 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000962
963 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +0000964 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +0000965 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000966 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000967 // Assumes this is the last use. IsKill will be unset if reg is reused
968 // unless it's a two-address operand.
969 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
970 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000971 MI.getOperand(i).setReg(PhysReg);
Evan Cheng0c40d722007-07-11 05:28:39 +0000972 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000973 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000974 }
975
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000976 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000977
Chris Lattner7fb64342004-10-01 19:04:51 +0000978 // If we have folded references to memory operands, make sure we clear all
979 // physical registers that may contain the value of the spilled virtual
980 // register
Evan Cheng90a43c32007-08-15 20:20:34 +0000981 SmallSet<int, 1> FoldedSS;
Chris Lattner8f1d6402005-01-14 15:54:24 +0000982 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000983 DOUT << "Folded vreg: " << I->second.first << " MR: "
984 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000985 unsigned VirtReg = I->second.first;
986 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng549f27d32007-08-13 23:45:17 +0000987 if (VRM.isAssignedReg(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000988 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000989 continue;
990 }
991 int SS = VRM.getStackSlot(VirtReg);
Evan Cheng90a43c32007-08-15 20:20:34 +0000992 FoldedSS.insert(SS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000993 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000994
995 // If this folded instruction is just a use, check to see if it's a
996 // straight load from the virt reg slot.
997 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
998 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000999 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +00001000 if (FrameIdx == SS) {
1001 // If this spill slot is available, turn it into a copy (or nothing)
1002 // instead of leaving it as a load!
Evan Cheng549f27d32007-08-13 23:45:17 +00001003 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001004 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +00001005 if (DestReg != InReg) {
1006 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
1007 MF.getSSARegMap()->getRegClass(VirtReg));
1008 // Revisit the copy so we make sure to notice the effects of the
1009 // operation on the destreg (either needing to RA it if it's
1010 // virtual or needing to clobber any values if it's physical).
1011 NextMII = &MI;
1012 --NextMII; // backtrack to the copy.
Evan Cheng0c40d722007-07-11 05:28:39 +00001013 BackTracked = true;
Evan Chengde4e9422007-02-25 09:51:27 +00001014 } else
1015 DOUT << "Removing now-noop copy: " << MI;
1016
Chris Lattner6ec36262006-10-12 17:45:38 +00001017 VRM.RemoveFromFoldedVirtMap(&MI);
1018 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001019 Erased = true;
Chris Lattner6ec36262006-10-12 17:45:38 +00001020 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001021 }
Chris Lattnercea86882005-09-19 06:56:21 +00001022 }
1023 }
1024 }
1025
1026 // If this reference is not a use, any previous store is now dead.
1027 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001028 MachineInstr* DeadStore = MaybeDeadStores[SS];
1029 if (DeadStore) {
1030 if (!(MR & VirtRegMap::isRef)) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001031 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +00001032 assert(VirtRegMap::isMod && "Can't be modref!");
Evan Chengfff3e192007-08-14 09:11:18 +00001033 DOUT << "Removed dead store:\t" << *DeadStore;
1034 InvalidateKills(*DeadStore, RegKills, KillOps);
1035 MBB.erase(DeadStore);
1036 VRM.RemoveFromFoldedVirtMap(DeadStore);
Chris Lattner35f27052006-05-01 21:16:03 +00001037 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001038 }
Evan Chengfff3e192007-08-14 09:11:18 +00001039 MaybeDeadStores[SS] = NULL;
Chris Lattnercea86882005-09-19 06:56:21 +00001040 }
1041
1042 // If the spill slot value is available, and this is a new definition of
1043 // the value, the value is not available anymore.
1044 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001045 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001046 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001047
1048 // If this is *just* a mod of the value, check to see if this is just a
1049 // store to the spill slot (i.e. the spill got merged into the copy). If
1050 // so, realize that the vreg is available now, and add the store to the
1051 // MaybeDeadStore info.
1052 int StackSlot;
1053 if (!(MR & VirtRegMap::isRef)) {
1054 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1055 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1056 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001057 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001058 // this as a potentially dead store in case there is a subsequent
1059 // store into the stack slot without a read from it.
1060 MaybeDeadStores[StackSlot] = &MI;
1061
Chris Lattnercd816392006-02-02 23:29:36 +00001062 // If the stack slot value was previously available in some other
1063 // register, change it now. Otherwise, make the register available,
1064 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001065 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001066 }
1067 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001068 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001069 }
1070
Chris Lattner7fb64342004-10-01 19:04:51 +00001071 // Process all of the spilled defs.
1072 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1073 MachineOperand &MO = MI.getOperand(i);
1074 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1075 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001076
Chris Lattner7fb64342004-10-01 19:04:51 +00001077 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001078 // Check to see if this is a noop copy. If so, eliminate the
1079 // instruction before considering the dest reg to be changed.
1080 unsigned Src, Dst;
1081 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1082 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001083 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001084 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001085 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001086 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001087 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001088 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001089 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001090
1091 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001092 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001093 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001094
1095 // Check to see if this instruction is a load from a stack slot into
1096 // a register. If so, this provides the stack slot value in the reg.
1097 int FrameIdx;
1098 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1099 assert(DestReg == VirtReg && "Unknown load situation!");
Evan Cheng90a43c32007-08-15 20:20:34 +00001100
1101 // If it is a folded reference, then it's not safe to clobber.
1102 bool Folded = FoldedSS.count(FrameIdx);
Chris Lattner6ec36262006-10-12 17:45:38 +00001103 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng90a43c32007-08-15 20:20:34 +00001104 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
Chris Lattner6ec36262006-10-12 17:45:38 +00001105 goto ProcessNextInst;
1106 }
1107
Chris Lattner29268692006-09-05 02:12:02 +00001108 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001109 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001110
Evan Chengb6ca4b32007-08-14 23:25:37 +00001111 bool DoReMat = VRM.isReMaterialized(VirtReg);
1112 if (DoReMat)
1113 ReMatDefs.insert(&MI);
1114
Chris Lattner84e752a2006-02-03 03:06:49 +00001115 // The only vregs left are stack slot definitions.
1116 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001117 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001118
Chris Lattner29268692006-09-05 02:12:02 +00001119 // If this def is part of a two-address operand, make sure to execute
1120 // the store from the correct physical register.
1121 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001122 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001123 if (TiedOp != -1)
1124 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001125 else {
Chris Lattner29268692006-09-05 02:12:02 +00001126 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001127 if (ReusedOperands.isClobbered(PhysReg)) {
1128 // Another def has taken the assigned physreg. It must have been a
1129 // use&def which got it due to reuse. Undo the reuse!
1130 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001131 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Evan Chenge077ef62006-11-04 00:21:55 +00001132 }
1133 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001134
Evan Cheng6c087e52007-04-25 22:13:27 +00001135 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001136 ReusedOperands.markClobbered(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001137 MI.getOperand(i).setReg(PhysReg);
Evan Chengb6ca4b32007-08-14 23:25:37 +00001138 if (!MO.isDead()) {
1139 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
1140 DOUT << "Store:\t" << *next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +00001141
Evan Chengb6ca4b32007-08-14 23:25:37 +00001142 // If there is a dead store to this stack slot, nuke it now.
1143 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1144 if (LastStore) {
1145 DOUT << "Removed dead store:\t" << *LastStore;
1146 ++NumDSE;
1147 SmallVector<unsigned, 1> KillRegs;
1148 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1149 MachineBasicBlock::iterator PrevMII = LastStore;
1150 bool CheckDef = PrevMII != MBB.begin();
1151 if (CheckDef)
1152 --PrevMII;
1153 MBB.erase(LastStore);
1154 VRM.RemoveFromFoldedVirtMap(LastStore);
1155 if (CheckDef) {
1156 // Look at defs of killed registers on the store. Mark the defs
1157 // as dead since the store has been deleted and they aren't
1158 // being reused.
1159 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1160 bool HasOtherDef = false;
1161 if (InvalidateRegDef(PrevMII, MI, KillRegs[j], HasOtherDef)) {
1162 MachineInstr *DeadDef = PrevMII;
1163 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1164 // FIXME: This assumes a remat def does not have side
1165 // effects.
1166 MBB.erase(DeadDef);
1167 VRM.RemoveFromFoldedVirtMap(DeadDef);
1168 ++NumDRM;
1169 }
1170 }
1171 }
1172 }
Evan Chengf50d09a2007-02-08 06:04:54 +00001173 }
Evan Chengb6ca4b32007-08-14 23:25:37 +00001174 LastStore = next(MII);
1175
1176 // If the stack slot value was previously available in some other
1177 // register, change it now. Otherwise, make the register available,
1178 // in PhysReg.
1179 Spills.ModifyStackSlotOrReMat(StackSlot);
1180 Spills.ClobberPhysReg(PhysReg);
1181 Spills.addAvailable(StackSlot, LastStore, PhysReg);
1182 ++NumStores;
1183
1184 // Check to see if this is a noop copy. If so, eliminate the
1185 // instruction before considering the dest reg to be changed.
1186 {
1187 unsigned Src, Dst;
1188 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1189 ++NumDCE;
1190 DOUT << "Removing now-noop copy: " << MI;
1191 MBB.erase(&MI);
1192 Erased = true;
1193 VRM.RemoveFromFoldedVirtMap(&MI);
1194 UpdateKills(*LastStore, RegKills, KillOps);
1195 goto ProcessNextInst;
1196 }
1197 }
1198 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001199 }
1200 }
Chris Lattnercea86882005-09-19 06:56:21 +00001201 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001202 if (!Erased && !BackTracked)
1203 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1204 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001205 MII = NextMII;
1206 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001207}
1208
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001209
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001210llvm::Spiller* llvm::createSpiller() {
1211 switch (SpillerOpt) {
1212 default: assert(0 && "Unreachable!");
1213 case local:
1214 return new LocalSpiller();
1215 case simple:
1216 return new SimpleSpiller();
1217 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001218}