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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng549f27d32007-08-13 23:45:17 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL),
Evan Cheng2638e1a2007-03-20 08:13:50 +000067 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000072 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
73 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
76 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000077}
78
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
80 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000081 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000083 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
84 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
85 RC->getAlignment());
86 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 ++NumSpills;
88 return frameIndex;
89}
90
91void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
92 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000093 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000094 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000095 assert((frameIndex >= 0 ||
96 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
97 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000098 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000099}
100
Evan Cheng2638e1a2007-03-20 08:13:50 +0000101int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
102 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000103 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000104 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000105 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000106 return ReMatId++;
107}
108
Evan Cheng549f27d32007-08-13 23:45:17 +0000109void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
110 assert(MRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign re-mat id to already spilled register");
113 Virt2ReMatIdMap[virtReg] = id;
114}
115
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000117 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000118 // Move previous memory references folded to new instruction.
119 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000120 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
122 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000123 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000125
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000126 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000127 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
128 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000129 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000130 // Folded a two-address operand.
131 MRInfo = isModRef;
132 } else if (OldMI->getOperand(OpNo).isDef()) {
133 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000135 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000136 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000139 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000140}
141
Chris Lattner7f690e62004-09-30 02:15:18 +0000142void VirtRegMap::print(std::ostream &OS) const {
143 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000144
Chris Lattner7f690e62004-09-30 02:15:18 +0000145 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000147 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
148 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
149 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000150
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000151 }
152
153 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000154 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
155 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
156 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
157 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000158}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000159
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000160void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000161 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000162}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000163
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
165//===----------------------------------------------------------------------===//
166// Simple Spiller Implementation
167//===----------------------------------------------------------------------===//
168
169Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000170
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000171namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000172 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000173 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000174 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000175}
176
Chris Lattner35f27052006-05-01 21:16:03 +0000177bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000178 DOUT << "********** REWRITE MACHINE CODE **********\n";
179 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000180 const TargetMachine &TM = MF.getTarget();
181 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000182
Chris Lattner4ea1b822004-09-30 02:33:48 +0000183 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
184 // each vreg once (in the case where a spilled vreg is used by multiple
185 // operands). This is always smaller than the number of operands to the
186 // current machine instr, so it should be small.
187 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000188
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000189 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
190 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000191 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000192 MachineBasicBlock &MBB = *MBBI;
193 for (MachineBasicBlock::iterator MII = MBB.begin(),
194 E = MBB.end(); MII != E; ++MII) {
195 MachineInstr &MI = *MII;
196 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000197 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 if (MO.isRegister() && MO.getReg())
199 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
200 unsigned VirtReg = MO.getReg();
201 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000202 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000203 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 const TargetRegisterClass* RC =
205 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000206
Chris Lattner886dd912005-04-04 21:35:34 +0000207 if (MO.isUse() &&
208 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
209 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000210 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000211 LoadedRegs.push_back(VirtReg);
212 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000213 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000214 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000215
Chris Lattner886dd912005-04-04 21:35:34 +0000216 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000217 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 ++NumStores;
219 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000220 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000221 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000222 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000223 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000224 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
Chris Lattner886dd912005-04-04 21:35:34 +0000227
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000228 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000229 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000230 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 }
232 return true;
233}
234
235//===----------------------------------------------------------------------===//
236// Local Spiller Implementation
237//===----------------------------------------------------------------------===//
238
239namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000240 /// LocalSpiller - This spiller does a simple pass over the machine basic
241 /// block to attempt to keep spills in registers as much as possible for
242 /// blocks that have low register pressure (the vreg may be spilled due to
243 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000244 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000245 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000246 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000247 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000248 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000249 MRI = MF.getTarget().getRegisterInfo();
250 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000251 DOUT << "\n**** Local spiller rewriting function '"
252 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000253
Chris Lattner7fb64342004-10-01 19:04:51 +0000254 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
255 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000256 RewriteMBB(*MBB, VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000257 return true;
258 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000259 private:
Evan Cheng549f27d32007-08-13 23:45:17 +0000260 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000261 };
262}
263
Chris Lattner66cf80f2006-02-03 23:13:58 +0000264/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000265/// top down, keep track of which spills slots or remat are available in each
266/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000267///
268/// Note that not all physregs are created equal here. In particular, some
269/// physregs are reloads that we are allowed to clobber or ignore at any time.
270/// Other physregs are values that the register allocated program is using that
271/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000272/// per-stack-slot / remat id basis as the low bit in the value of the
273/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
274/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000275namespace {
276class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000277 const MRegisterInfo *MRI;
278 const TargetInstrInfo *TII;
279
Evan Cheng549f27d32007-08-13 23:45:17 +0000280 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
281 // or remat'ed virtual register values that are still available, due to being
282 // loaded or stored to, but not invalidated yet.
283 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284
Evan Cheng549f27d32007-08-13 23:45:17 +0000285 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
286 // indicating which stack slot values are currently held by a physreg. This
287 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
288 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289 std::multimap<unsigned, int> PhysRegsAvailable;
290
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000291 void disallowClobberPhysRegOnly(unsigned PhysReg);
292
Chris Lattner66cf80f2006-02-03 23:13:58 +0000293 void ClobberPhysRegOnly(unsigned PhysReg);
294public:
295 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
296 : MRI(mri), TII(tii) {
297 }
298
Evan Cheng91e23902007-02-23 01:13:26 +0000299 const MRegisterInfo *getRegInfo() const { return MRI; }
300
Evan Cheng549f27d32007-08-13 23:45:17 +0000301 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
302 /// available in a physical register, return that PhysReg, otherwise
303 /// return 0.
304 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
305 std::map<int, unsigned>::const_iterator I =
306 SpillSlotsOrReMatsAvailable.find(Slot);
307 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000308 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000309 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000310 return 0;
311 }
Evan Chengde4e9422007-02-25 09:51:27 +0000312
Evan Cheng549f27d32007-08-13 23:45:17 +0000313 /// addAvailable - Mark that the specified stack slot / remat is available in
314 /// the specified physreg. If CanClobber is true, the physreg can be modified
315 /// at any time without changing the semantics of the program.
316 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000317 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000318 // If this stack slot is thought to be available in some other physreg,
319 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000320 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000321
Evan Cheng549f27d32007-08-13 23:45:17 +0000322 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
323 SpillSlotsOrReMatsAvailable[SlotOrReMat] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000324
Evan Cheng549f27d32007-08-13 23:45:17 +0000325 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
326 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000327 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000328 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000329 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000330 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000331
Chris Lattner593c9582006-02-03 23:28:46 +0000332 /// canClobberPhysReg - Return true if the spiller is allowed to change the
333 /// value of the specified stackslot register if it desires. The specified
334 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000335 bool canClobberPhysReg(int SlotOrReMat) const {
336 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && "Value not available!");
337 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000338 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000339
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000340 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
341 /// stackslot register. The register is still available but is no longer
342 /// allowed to be modifed.
343 void disallowClobberPhysReg(unsigned PhysReg);
344
Chris Lattner66cf80f2006-02-03 23:13:58 +0000345 /// ClobberPhysReg - This is called when the specified physreg changes
346 /// value. We use this to invalidate any info about stuff we thing lives in
347 /// it and any of its aliases.
348 void ClobberPhysReg(unsigned PhysReg);
349
Evan Cheng549f27d32007-08-13 23:45:17 +0000350 /// ModifyStackSlotOrReMat - This method is called when the value in a stack slot
Chris Lattner66cf80f2006-02-03 23:13:58 +0000351 /// changes. This removes information about which register the previous value
352 /// for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000353 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000354};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000355}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000356
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000357/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
358/// stackslot register. The register is still available but is no longer
359/// allowed to be modifed.
360void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
361 std::multimap<unsigned, int>::iterator I =
362 PhysRegsAvailable.lower_bound(PhysReg);
363 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000364 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000365 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000366 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000367 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000368 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000369 DOUT << "PhysReg " << MRI->getName(PhysReg)
370 << " copied, it is available for use but can no longer be modified\n";
371 }
372}
373
374/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
375/// stackslot register and its aliases. The register and its aliases may
376/// still available but is no longer allowed to be modifed.
377void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
378 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
379 disallowClobberPhysRegOnly(*AS);
380 disallowClobberPhysRegOnly(PhysReg);
381}
382
Chris Lattner66cf80f2006-02-03 23:13:58 +0000383/// ClobberPhysRegOnly - This is called when the specified physreg changes
384/// value. We use this to invalidate any info about stuff we thing lives in it.
385void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
386 std::multimap<unsigned, int>::iterator I =
387 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000388 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000389 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000390 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000391 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000392 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000393 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000394 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000395 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000396 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
397 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000398 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000399 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000400 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000401}
402
Chris Lattner66cf80f2006-02-03 23:13:58 +0000403/// ClobberPhysReg - This is called when the specified physreg changes
404/// value. We use this to invalidate any info about stuff we thing lives in
405/// it and any of its aliases.
406void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000407 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000408 ClobberPhysRegOnly(*AS);
409 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000410}
411
Evan Cheng549f27d32007-08-13 23:45:17 +0000412/// ModifyStackSlotOrReMat - This method is called when the value in a stack slot
Chris Lattner07cf1412006-02-03 00:36:31 +0000413/// changes. This removes information about which register the previous value
414/// for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000415void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
416 std::map<int, unsigned>::iterator It = SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
417 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000418 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000419 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000420
421 // This register may hold the value of multiple stack slots, only remove this
422 // stack slot from the set of values the register contains.
423 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
424 for (; ; ++I) {
425 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
426 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000427 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000428 }
429 PhysRegsAvailable.erase(I);
430}
431
432
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000433
Evan Cheng28bb4622007-07-11 19:17:18 +0000434/// InvalidateKills - MI is going to be deleted. If any of its operands are
435/// marked kill, then invalidate the information.
436static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000437 std::vector<MachineOperand*> &KillOps,
Evan Chengb6ca4b32007-08-14 23:25:37 +0000438 SmallVector<unsigned, 1> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000439 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
440 MachineOperand &MO = MI.getOperand(i);
441 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
442 continue;
443 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000444 if (KillRegs)
445 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000446 if (KillOps[Reg] == &MO) {
447 RegKills.reset(Reg);
448 KillOps[Reg] = NULL;
449 }
450 }
451}
452
Evan Chengb6ca4b32007-08-14 23:25:37 +0000453/// InvalidateRegDef - If the def operand of the specified def MI is now dead
454/// (since it's spill instruction is removed), mark it isDead. Also checks if
455/// the def MI has other definition operands that are not dead. Returns it by
456/// reference.
457static bool InvalidateRegDef(MachineBasicBlock::iterator I,
458 MachineInstr &NewDef, unsigned Reg,
459 bool &HasLiveDef) {
460 // Due to remat, it's possible this reg isn't being reused. That is,
461 // the def of this reg (by prev MI) is now dead.
462 MachineInstr *DefMI = I;
463 MachineOperand *DefOp = NULL;
464 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
465 MachineOperand &MO = DefMI->getOperand(i);
466 if (MO.isReg() && MO.isDef()) {
467 if (MO.getReg() == Reg)
468 DefOp = &MO;
469 else if (!MO.isDead())
470 HasLiveDef = true;
471 }
472 }
473 if (!DefOp)
474 return false;
475
476 bool FoundUse = false, Done = false;
477 MachineBasicBlock::iterator E = NewDef;
478 ++I; ++E;
479 for (; !Done && I != E; ++I) {
480 MachineInstr *NMI = I;
481 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
482 MachineOperand &MO = NMI->getOperand(j);
483 if (!MO.isReg() || MO.getReg() != Reg)
484 continue;
485 if (MO.isUse())
486 FoundUse = true;
487 Done = true; // Stop after scanning all the operands of this MI.
488 }
489 }
490 if (!FoundUse) {
491 // Def is dead!
492 DefOp->setIsDead();
493 return true;
494 }
495 return false;
496}
497
Evan Cheng28bb4622007-07-11 19:17:18 +0000498/// UpdateKills - Track and update kill info. If a MI reads a register that is
499/// marked kill, then it must be due to register reuse. Transfer the kill info
500/// over.
501static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
502 std::vector<MachineOperand*> &KillOps) {
503 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
504 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
505 MachineOperand &MO = MI.getOperand(i);
506 if (!MO.isReg() || !MO.isUse())
507 continue;
508 unsigned Reg = MO.getReg();
509 if (Reg == 0)
510 continue;
511
512 if (RegKills[Reg]) {
513 // That can't be right. Register is killed but not re-defined and it's
514 // being reused. Let's fix that.
515 KillOps[Reg]->unsetIsKill();
516 if (i < TID->numOperands &&
517 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
518 // Unless it's a two-address operand, this is the new kill.
519 MO.setIsKill();
520 }
521
522 if (MO.isKill()) {
523 RegKills.set(Reg);
524 KillOps[Reg] = &MO;
525 }
526 }
527
528 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
529 const MachineOperand &MO = MI.getOperand(i);
530 if (!MO.isReg() || !MO.isDef())
531 continue;
532 unsigned Reg = MO.getReg();
533 RegKills.reset(Reg);
534 KillOps[Reg] = NULL;
535 }
536}
537
538
Chris Lattner7fb64342004-10-01 19:04:51 +0000539// ReusedOp - For each reused operand, we keep track of a bit of information, in
540// case we need to rollback upon processing a new operand. See comments below.
541namespace {
542 struct ReusedOp {
543 // The MachineInstr operand that reused an available value.
544 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000545
Evan Cheng549f27d32007-08-13 23:45:17 +0000546 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
547 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000548
Chris Lattner7fb64342004-10-01 19:04:51 +0000549 // PhysRegReused - The physical register the value was available in.
550 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000551
Chris Lattner7fb64342004-10-01 19:04:51 +0000552 // AssignedPhysReg - The physreg that was assigned for use by the reload.
553 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000554
555 // VirtReg - The virtual register itself.
556 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000557
Chris Lattner8a61a752005-10-06 17:19:06 +0000558 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
559 unsigned vreg)
Evan Cheng549f27d32007-08-13 23:45:17 +0000560 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), AssignedPhysReg(apr),
Chris Lattner8a61a752005-10-06 17:19:06 +0000561 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000562 };
Chris Lattner540fec62006-02-25 01:51:33 +0000563
564 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
565 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000566 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000567 MachineInstr &MI;
568 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000569 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000570 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000571 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000572 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000573 }
Chris Lattner540fec62006-02-25 01:51:33 +0000574
575 bool hasReuses() const {
576 return !Reuses.empty();
577 }
578
579 /// addReuse - If we choose to reuse a virtual register that is already
580 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000581 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000582 unsigned PhysRegReused, unsigned AssignedPhysReg,
583 unsigned VirtReg) {
584 // If the reload is to the assigned register anyway, no undo will be
585 // required.
586 if (PhysRegReused == AssignedPhysReg) return;
587
588 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000589 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000590 AssignedPhysReg, VirtReg));
591 }
Evan Chenge077ef62006-11-04 00:21:55 +0000592
593 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000594 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000595 }
596
597 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000598 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000599 }
Chris Lattner540fec62006-02-25 01:51:33 +0000600
601 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
602 /// is some other operand that is using the specified register, either pick
603 /// a new register to use, or evict the previous reload and use this reg.
604 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
605 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000606 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000607 SmallSet<unsigned, 8> &Rejected,
608 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000609 std::vector<MachineOperand*> &KillOps,
610 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000611 if (Reuses.empty()) return PhysReg; // This is most often empty.
612
613 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
614 ReusedOp &Op = Reuses[ro];
615 // If we find some other reuse that was supposed to use this register
616 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000617 // register. That is, unless its reload register has already been
618 // considered and subsequently rejected because it has also been reused
619 // by another operand.
620 if (Op.PhysRegReused == PhysReg &&
621 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000622 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000623 unsigned NewReg = Op.AssignedPhysReg;
624 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000625 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000626 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000627 } else {
628 // Otherwise, we might also have a problem if a previously reused
629 // value aliases the new register. If so, codegen the previous reload
630 // and use this one.
631 unsigned PRRU = Op.PhysRegReused;
632 const MRegisterInfo *MRI = Spills.getRegInfo();
633 if (MRI->areAliases(PRRU, PhysReg)) {
634 // Okay, we found out that an alias of a reused register
635 // was used. This isn't good because it means we have
636 // to undo a previous reuse.
637 MachineBasicBlock *MBB = MI->getParent();
638 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000639 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
640
641 // Copy Op out of the vector and remove it, we're going to insert an
642 // explicit load for it.
643 ReusedOp NewOp = Op;
644 Reuses.erase(Reuses.begin()+ro);
645
646 // Ok, we're going to try to reload the assigned physreg into the
647 // slot that we were supposed to in the first place. However, that
648 // register could hold a reuse. Check to see if it conflicts or
649 // would prefer us to use a different register.
650 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000651 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000652 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000653
Evan Cheng549f27d32007-08-13 23:45:17 +0000654 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
655 MRI->reMaterialize(*MBB, MI, NewPhysReg,
656 VRM.getReMaterializedMI(NewOp.VirtReg));
657 ++NumReMats;
658 } else {
659 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
660 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000661 // Any stores to this stack slot are not dead anymore.
662 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000663 ++NumLoads;
664 }
Chris Lattner28bad082006-02-25 02:17:31 +0000665 Spills.ClobberPhysReg(NewPhysReg);
666 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000667
Chris Lattnere53f4a02006-05-04 17:52:23 +0000668 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000669
Evan Cheng549f27d32007-08-13 23:45:17 +0000670 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000671 MachineBasicBlock::iterator MII = MI;
672 --MII;
673 UpdateKills(*MII, RegKills, KillOps);
674 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000675
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000676 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000677 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000678
679 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000680 return PhysReg;
681 }
682 }
683 }
684 return PhysReg;
685 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000686
687 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
688 /// 'Rejected' set to remember which registers have been considered and
689 /// rejected for the reload. This avoids infinite looping in case like
690 /// this:
691 /// t1 := op t2, t3
692 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
693 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
694 /// t1 <- desires r1
695 /// sees r1 is taken by t2, tries t2's reload register r0
696 /// sees r0 is taken by t3, tries t3's reload register r1
697 /// sees r1 is taken by t2, tries t2's reload register r0 ...
698 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
699 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000700 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000701 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000702 std::vector<MachineOperand*> &KillOps,
703 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000704 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000705 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000706 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000707 }
Chris Lattner540fec62006-02-25 01:51:33 +0000708 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000709}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000710
Chris Lattner7fb64342004-10-01 19:04:51 +0000711
712/// rewriteMBB - Keep track of which spills are available even after the
713/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000714void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000715 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000716
Evan Chengfff3e192007-08-14 09:11:18 +0000717 MachineFunction &MF = *MBB.getParent();
718
Chris Lattner66cf80f2006-02-03 23:13:58 +0000719 // Spills - Keep track of which spilled values are available in physregs so
720 // that we can choose to reuse the physregs instead of emitting reloads.
721 AvailableSpills Spills(MRI, TII);
722
Chris Lattner52b25db2004-10-01 19:47:12 +0000723 // MaybeDeadStores - When we need to write a value back into a stack slot,
724 // keep track of the inserted store. If the stack slot value is never read
725 // (because the value was used from some available register, for example), and
726 // subsequently stored to, the original store is dead. This map keeps track
727 // of inserted stores that are not used. If we see a subsequent store to the
728 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000729 std::vector<MachineInstr*> MaybeDeadStores;
730 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000731
Evan Chengb6ca4b32007-08-14 23:25:37 +0000732 // ReMatDefs - These are rematerializable def MIs which are not deleted.
733 SmallSet<MachineInstr*, 4> ReMatDefs;
734
Evan Cheng0c40d722007-07-11 05:28:39 +0000735 // Keep track of kill information.
736 BitVector RegKills(MRI->getNumRegs());
737 std::vector<MachineOperand*> KillOps;
738 KillOps.resize(MRI->getNumRegs(), NULL);
739
Chris Lattner7fb64342004-10-01 19:04:51 +0000740 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
741 MII != E; ) {
742 MachineInstr &MI = *MII;
743 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000744 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
745
746 bool Erased = false;
747 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000748
Chris Lattner540fec62006-02-25 01:51:33 +0000749 /// ReusedOperands - Keep track of operand reuse in case we need to undo
750 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000751 ReuseInfo ReusedOperands(MI, MRI);
752
753 // Loop over all of the implicit defs, clearing them from our available
754 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000755 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng0c40d722007-07-11 05:28:39 +0000756 if (TID->ImplicitDefs) {
757 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000758 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000759 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000760 ReusedOperands.markClobbered(*ImpDef);
761 Spills.ClobberPhysReg(*ImpDef);
762 }
763 }
764
Chris Lattner7fb64342004-10-01 19:04:51 +0000765 // Process all of the spilled uses and all non spilled reg references.
766 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
767 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000768 if (!MO.isRegister() || MO.getReg() == 0)
769 continue; // Ignore non-register operands.
770
771 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
772 // Ignore physregs for spilling, but remember that it is used by this
773 // function.
Evan Cheng6c087e52007-04-25 22:13:27 +0000774 MF.setPhysRegUsed(MO.getReg());
Evan Chenge077ef62006-11-04 00:21:55 +0000775 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000776 continue;
777 }
778
779 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
780 "Not a virtual or a physical register?");
781
782 unsigned VirtReg = MO.getReg();
Evan Cheng549f27d32007-08-13 23:45:17 +0000783 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000784 // This virtual register was assigned a physreg!
785 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000786 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000787 if (MO.isDef())
788 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000789 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000790 continue;
791 }
792
793 // This virtual register is now known to be a spilled value.
794 if (!MO.isUse())
795 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000796
Evan Cheng549f27d32007-08-13 23:45:17 +0000797 bool DoReMat = VRM.isReMaterialized(VirtReg);
798 int SSorRMId = DoReMat
799 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +0000800 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +0000801
Chris Lattner50ea01e2005-09-09 20:29:51 +0000802 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +0000803 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
804 if (!PhysReg && DoReMat) {
805 // This use is rematerializable. But perhaps the value is available in
806 // stack if the definition is not deleted. If so, check if we can
807 // reuse the value.
808 ReuseSlot = VRM.getStackSlot(VirtReg);
809 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
810 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
811 }
812 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000813 // This spilled operand might be part of a two-address operand. If this
814 // is the case, then changing it will necessarily require changing the
815 // def part of the instruction as well. However, in some cases, we
816 // aren't allowed to modify the reused register. If none of these cases
817 // apply, reuse it.
818 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000819 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000820 if (ti != -1 &&
821 MI.getOperand(ti).isReg() &&
822 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000823 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000824 // long as we are allowed to clobber the value and there isn't an
825 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +0000826 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +0000827 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000828 }
829
830 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000831 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000832 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
833 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000834 else
Evan Chengdc6be192007-08-14 05:42:54 +0000835 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000836 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000837 << MRI->getName(PhysReg) << " for vreg"
838 << VirtReg <<" instead of reloading into physreg "
839 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000840 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000841
842 // The only technical detail we have is that we don't know that
843 // PhysReg won't be clobbered by a reloaded stack slot that occurs
844 // later in the instruction. In particular, consider 'op V1, V2'.
845 // If V1 is available in physreg R0, we would choose to reuse it
846 // here, instead of reloading it into the register the allocator
847 // indicated (say R1). However, V2 might have to be reloaded
848 // later, and it might indicate that it needs to live in R0. When
849 // this occurs, we need to have information available that
850 // indicates it is safe to use R1 for the reload instead of R0.
851 //
852 // To further complicate matters, we might conflict with an alias,
853 // or R0 and R1 might not be compatible with each other. In this
854 // case, we actually insert a reload for V1 in R1, ensuring that
855 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +0000856 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +0000857 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000858 if (ti != -1)
859 // Only mark it clobbered if this is a use&def operand.
860 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000861 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +0000862
863 if (MI.getOperand(i).isKill() &&
864 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
865 // This was the last use and the spilled value is still available
866 // for reuse. That means the spill was unnecessary!
867 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
868 if (DeadStore) {
869 DOUT << "Removed dead store:\t" << *DeadStore;
870 InvalidateKills(*DeadStore, RegKills, KillOps);
871 MBB.erase(DeadStore);
872 VRM.RemoveFromFoldedVirtMap(DeadStore);
873 MaybeDeadStores[ReuseSlot] = NULL;
874 ++NumDSE;
875 }
876 }
Chris Lattneraddc55a2006-04-28 01:46:50 +0000877 continue;
878 }
879
880 // Otherwise we have a situation where we have a two-address instruction
881 // whose mod/ref operand needs to be reloaded. This reload is already
882 // available in some register "PhysReg", but if we used PhysReg as the
883 // operand to our 2-addr instruction, the instruction would modify
884 // PhysReg. This isn't cool if something later uses PhysReg and expects
885 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000886 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000887 // To avoid this problem, and to avoid doing a load right after a store,
888 // we emit a copy from PhysReg into the designated register for this
889 // operand.
890 unsigned DesignatedReg = VRM.getPhys(VirtReg);
891 assert(DesignatedReg && "Must map virtreg to physreg!");
892
893 // Note that, if we reused a register for a previous operand, the
894 // register we want to reload into might not actually be
895 // available. If this occurs, use the register indicated by the
896 // reuser.
897 if (ReusedOperands.hasReuses())
898 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000899 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000900
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000901 // If the mapped designated register is actually the physreg we have
902 // incoming, we don't need to inserted a dead copy.
903 if (DesignatedReg == PhysReg) {
904 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000905 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
906 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000907 else
Evan Chengdc6be192007-08-14 05:42:54 +0000908 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000909 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000910 << VirtReg
911 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000912 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000913 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000914 ++NumReused;
915 continue;
916 }
917
Evan Cheng6c087e52007-04-25 22:13:27 +0000918 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
919 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000920 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000921 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000922
Evan Cheng6b448092007-03-02 08:52:00 +0000923 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000924 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000925
Chris Lattneraddc55a2006-04-28 01:46:50 +0000926 // This invalidates DesignatedReg.
927 Spills.ClobberPhysReg(DesignatedReg);
928
Evan Chengdc6be192007-08-14 05:42:54 +0000929 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000930 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000931 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000932 ++NumReused;
933 continue;
934 }
935
936 // Otherwise, reload it and remember that we have it.
937 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000938 assert(PhysReg && "Must map virtreg to physreg!");
Evan Cheng6c087e52007-04-25 22:13:27 +0000939 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000940
Chris Lattner50ea01e2005-09-09 20:29:51 +0000941 // Note that, if we reused a register for a previous operand, the
942 // register we want to reload into might not actually be
943 // available. If this occurs, use the register indicated by the
944 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000945 if (ReusedOperands.hasReuses())
946 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000947 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000948
Evan Cheng6c087e52007-04-25 22:13:27 +0000949 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000950 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000951 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000952 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000953 ++NumReMats;
954 } else {
Evan Cheng549f27d32007-08-13 23:45:17 +0000955 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000956 ++NumLoads;
957 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000958 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000959 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000960
961 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +0000962 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +0000963 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000964 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000965 // Assumes this is the last use. IsKill will be unset if reg is reused
966 // unless it's a two-address operand.
967 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
968 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000969 MI.getOperand(i).setReg(PhysReg);
Evan Cheng0c40d722007-07-11 05:28:39 +0000970 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000971 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000972 }
973
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000974 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000975
Chris Lattner7fb64342004-10-01 19:04:51 +0000976 // If we have folded references to memory operands, make sure we clear all
977 // physical registers that may contain the value of the spilled virtual
978 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000979 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000980 DOUT << "Folded vreg: " << I->second.first << " MR: "
981 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000982 unsigned VirtReg = I->second.first;
983 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng549f27d32007-08-13 23:45:17 +0000984 if (VRM.isAssignedReg(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000985 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000986 continue;
987 }
988 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000989 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000990
991 // If this folded instruction is just a use, check to see if it's a
992 // straight load from the virt reg slot.
993 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
994 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000995 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000996 if (FrameIdx == SS) {
997 // If this spill slot is available, turn it into a copy (or nothing)
998 // instead of leaving it as a load!
Evan Cheng549f27d32007-08-13 23:45:17 +0000999 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001000 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +00001001 if (DestReg != InReg) {
1002 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
1003 MF.getSSARegMap()->getRegClass(VirtReg));
1004 // Revisit the copy so we make sure to notice the effects of the
1005 // operation on the destreg (either needing to RA it if it's
1006 // virtual or needing to clobber any values if it's physical).
1007 NextMII = &MI;
1008 --NextMII; // backtrack to the copy.
Evan Cheng0c40d722007-07-11 05:28:39 +00001009 BackTracked = true;
Evan Chengde4e9422007-02-25 09:51:27 +00001010 } else
1011 DOUT << "Removing now-noop copy: " << MI;
1012
Chris Lattner6ec36262006-10-12 17:45:38 +00001013 VRM.RemoveFromFoldedVirtMap(&MI);
1014 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001015 Erased = true;
Chris Lattner6ec36262006-10-12 17:45:38 +00001016 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001017 }
Chris Lattnercea86882005-09-19 06:56:21 +00001018 }
1019 }
1020 }
1021
1022 // If this reference is not a use, any previous store is now dead.
1023 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001024 MachineInstr* DeadStore = MaybeDeadStores[SS];
1025 if (DeadStore) {
1026 if (!(MR & VirtRegMap::isRef)) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001027 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +00001028 assert(VirtRegMap::isMod && "Can't be modref!");
Evan Chengfff3e192007-08-14 09:11:18 +00001029 DOUT << "Removed dead store:\t" << *DeadStore;
1030 InvalidateKills(*DeadStore, RegKills, KillOps);
1031 MBB.erase(DeadStore);
1032 VRM.RemoveFromFoldedVirtMap(DeadStore);
Chris Lattner35f27052006-05-01 21:16:03 +00001033 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001034 }
Evan Chengfff3e192007-08-14 09:11:18 +00001035 MaybeDeadStores[SS] = NULL;
Chris Lattnercea86882005-09-19 06:56:21 +00001036 }
1037
1038 // If the spill slot value is available, and this is a new definition of
1039 // the value, the value is not available anymore.
1040 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001041 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001042 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001043
1044 // If this is *just* a mod of the value, check to see if this is just a
1045 // store to the spill slot (i.e. the spill got merged into the copy). If
1046 // so, realize that the vreg is available now, and add the store to the
1047 // MaybeDeadStore info.
1048 int StackSlot;
1049 if (!(MR & VirtRegMap::isRef)) {
1050 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1051 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1052 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001053 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001054 // this as a potentially dead store in case there is a subsequent
1055 // store into the stack slot without a read from it.
1056 MaybeDeadStores[StackSlot] = &MI;
1057
Chris Lattnercd816392006-02-02 23:29:36 +00001058 // If the stack slot value was previously available in some other
1059 // register, change it now. Otherwise, make the register available,
1060 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001061 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001062 }
1063 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001064 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001065 }
1066
Chris Lattner7fb64342004-10-01 19:04:51 +00001067 // Process all of the spilled defs.
1068 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1069 MachineOperand &MO = MI.getOperand(i);
1070 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1071 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001072
Chris Lattner7fb64342004-10-01 19:04:51 +00001073 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001074 // Check to see if this is a noop copy. If so, eliminate the
1075 // instruction before considering the dest reg to be changed.
1076 unsigned Src, Dst;
1077 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1078 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001079 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001080 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001081 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001082 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001083 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001084 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001085 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001086
1087 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001088 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001089 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001090
1091 // Check to see if this instruction is a load from a stack slot into
1092 // a register. If so, this provides the stack slot value in the reg.
1093 int FrameIdx;
1094 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1095 assert(DestReg == VirtReg && "Unknown load situation!");
1096
1097 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001098 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001099 goto ProcessNextInst;
1100 }
1101
Chris Lattner29268692006-09-05 02:12:02 +00001102 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001103 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001104
Evan Chengb6ca4b32007-08-14 23:25:37 +00001105 bool DoReMat = VRM.isReMaterialized(VirtReg);
1106 if (DoReMat)
1107 ReMatDefs.insert(&MI);
1108
Chris Lattner84e752a2006-02-03 03:06:49 +00001109 // The only vregs left are stack slot definitions.
1110 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001111 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001112
Chris Lattner29268692006-09-05 02:12:02 +00001113 // If this def is part of a two-address operand, make sure to execute
1114 // the store from the correct physical register.
1115 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001116 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001117 if (TiedOp != -1)
1118 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001119 else {
Chris Lattner29268692006-09-05 02:12:02 +00001120 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001121 if (ReusedOperands.isClobbered(PhysReg)) {
1122 // Another def has taken the assigned physreg. It must have been a
1123 // use&def which got it due to reuse. Undo the reuse!
1124 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001125 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Evan Chenge077ef62006-11-04 00:21:55 +00001126 }
1127 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001128
Evan Cheng6c087e52007-04-25 22:13:27 +00001129 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001130 ReusedOperands.markClobbered(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001131 MI.getOperand(i).setReg(PhysReg);
Evan Chengb6ca4b32007-08-14 23:25:37 +00001132 if (!MO.isDead()) {
1133 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
1134 DOUT << "Store:\t" << *next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +00001135
Evan Chengb6ca4b32007-08-14 23:25:37 +00001136 // If there is a dead store to this stack slot, nuke it now.
1137 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1138 if (LastStore) {
1139 DOUT << "Removed dead store:\t" << *LastStore;
1140 ++NumDSE;
1141 SmallVector<unsigned, 1> KillRegs;
1142 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1143 MachineBasicBlock::iterator PrevMII = LastStore;
1144 bool CheckDef = PrevMII != MBB.begin();
1145 if (CheckDef)
1146 --PrevMII;
1147 MBB.erase(LastStore);
1148 VRM.RemoveFromFoldedVirtMap(LastStore);
1149 if (CheckDef) {
1150 // Look at defs of killed registers on the store. Mark the defs
1151 // as dead since the store has been deleted and they aren't
1152 // being reused.
1153 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1154 bool HasOtherDef = false;
1155 if (InvalidateRegDef(PrevMII, MI, KillRegs[j], HasOtherDef)) {
1156 MachineInstr *DeadDef = PrevMII;
1157 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1158 // FIXME: This assumes a remat def does not have side
1159 // effects.
1160 MBB.erase(DeadDef);
1161 VRM.RemoveFromFoldedVirtMap(DeadDef);
1162 ++NumDRM;
1163 }
1164 }
1165 }
1166 }
Evan Chengf50d09a2007-02-08 06:04:54 +00001167 }
Evan Chengb6ca4b32007-08-14 23:25:37 +00001168 LastStore = next(MII);
1169
1170 // If the stack slot value was previously available in some other
1171 // register, change it now. Otherwise, make the register available,
1172 // in PhysReg.
1173 Spills.ModifyStackSlotOrReMat(StackSlot);
1174 Spills.ClobberPhysReg(PhysReg);
1175 Spills.addAvailable(StackSlot, LastStore, PhysReg);
1176 ++NumStores;
1177
1178 // Check to see if this is a noop copy. If so, eliminate the
1179 // instruction before considering the dest reg to be changed.
1180 {
1181 unsigned Src, Dst;
1182 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1183 ++NumDCE;
1184 DOUT << "Removing now-noop copy: " << MI;
1185 MBB.erase(&MI);
1186 Erased = true;
1187 VRM.RemoveFromFoldedVirtMap(&MI);
1188 UpdateKills(*LastStore, RegKills, KillOps);
1189 goto ProcessNextInst;
1190 }
1191 }
1192 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001193 }
1194 }
Chris Lattnercea86882005-09-19 06:56:21 +00001195 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001196 if (!Erased && !BackTracked)
1197 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1198 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001199 MII = NextMII;
1200 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001201}
1202
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001203
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001204llvm::Spiller* llvm::createSpiller() {
1205 switch (SpillerOpt) {
1206 default: assert(0 && "Unreachable!");
1207 case local:
1208 return new LocalSpiller();
1209 case simple:
1210 return new SimpleSpiller();
1211 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001212}