blob: 196e849cc583d44553d95eee612023554be4743d [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
65 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000066 grow();
67}
68
Chris Lattner8c4d88d2004-09-30 01:54:45 +000069void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000070 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
71 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000072}
73
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000077 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000078 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
79 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
80 RC->getAlignment());
81 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 ++NumSpills;
83 return frameIndex;
84}
85
86void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
87 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000088 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000090 assert((frameIndex >= 0 ||
91 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
92 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000093 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000094}
95
Evan Cheng2638e1a2007-03-20 08:13:50 +000096int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
97 assert(MRegisterInfo::isVirtualRegister(virtReg));
98 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
99 "attempt to assign re-mat id to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +0000100 const MachineInstr *DefMI = getReMaterializedMI(virtReg);
101 int FrameIdx;
102 if (TII.isLoadFromStackSlot((MachineInstr*)DefMI, FrameIdx)) {
103 // Load from stack slot is re-materialize as reload from the stack slot!
104 Virt2StackSlotMap[virtReg] = FrameIdx;
105 return FrameIdx;
106 }
Evan Cheng2638e1a2007-03-20 08:13:50 +0000107 Virt2StackSlotMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000108 return ReMatId++;
109}
110
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000112 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000113 // Move previous memory references folded to new instruction.
114 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000115 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
117 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000118 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000119 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000120
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000122 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
123 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000124 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000125 // Folded a two-address operand.
126 MRInfo = isModRef;
127 } else if (OldMI->getOperand(OpNo).isDef()) {
128 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000129 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000130 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000131 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000132
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000133 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000135}
136
Chris Lattner7f690e62004-09-30 02:15:18 +0000137void VirtRegMap::print(std::ostream &OS) const {
138 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000139
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000142 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
143 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
144 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000145
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 }
147
148 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000149 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
150 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
151 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
152 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000153}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000154
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000155void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000156 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000157}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000158
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000159
160//===----------------------------------------------------------------------===//
161// Simple Spiller Implementation
162//===----------------------------------------------------------------------===//
163
164Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000165
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000166namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000167 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000168 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000170}
171
Chris Lattner35f27052006-05-01 21:16:03 +0000172bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000173 DOUT << "********** REWRITE MACHINE CODE **********\n";
174 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000175 const TargetMachine &TM = MF.getTarget();
176 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000177
Chris Lattner4ea1b822004-09-30 02:33:48 +0000178 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
179 // each vreg once (in the case where a spilled vreg is used by multiple
180 // operands). This is always smaller than the number of operands to the
181 // current machine instr, so it should be small.
182 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000183
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000184 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
185 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000186 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000187 MachineBasicBlock &MBB = *MBBI;
188 for (MachineBasicBlock::iterator MII = MBB.begin(),
189 E = MBB.end(); MII != E; ++MII) {
190 MachineInstr &MI = *MII;
191 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000192 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000193 if (MO.isRegister() && MO.getReg())
194 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
195 unsigned VirtReg = MO.getReg();
196 unsigned PhysReg = VRM.getPhys(VirtReg);
197 if (VRM.hasStackSlot(VirtReg)) {
198 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000199 const TargetRegisterClass* RC =
200 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000201
Chris Lattner886dd912005-04-04 21:35:34 +0000202 if (MO.isUse() &&
203 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
204 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000205 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000206 LoadedRegs.push_back(VirtReg);
207 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000208 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000209 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000210
Chris Lattner886dd912005-04-04 21:35:34 +0000211 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000212 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000213 ++NumStores;
214 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000215 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000216 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000217 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000219 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000220 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 }
Chris Lattner886dd912005-04-04 21:35:34 +0000222
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000223 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000224 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
227 return true;
228}
229
230//===----------------------------------------------------------------------===//
231// Local Spiller Implementation
232//===----------------------------------------------------------------------===//
233
234namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000235 /// LocalSpiller - This spiller does a simple pass over the machine basic
236 /// block to attempt to keep spills in registers as much as possible for
237 /// blocks that have low register pressure (the vreg may be spilled due to
238 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000239 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000240 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000241 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000242 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000243 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000244 MRI = MF.getTarget().getRegisterInfo();
245 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000246 DOUT << "\n**** Local spiller rewriting function '"
247 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248
Evan Cheng2638e1a2007-03-20 08:13:50 +0000249 std::vector<MachineInstr *> ReMatedMIs;
Chris Lattner7fb64342004-10-01 19:04:51 +0000250 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
251 MBB != E; ++MBB)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000252 RewriteMBB(*MBB, VRM, ReMatedMIs);
253 for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i)
254 delete ReMatedMIs[i];
Chris Lattner7fb64342004-10-01 19:04:51 +0000255 return true;
256 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000257 private:
Evan Cheng2638e1a2007-03-20 08:13:50 +0000258 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
259 std::vector<MachineInstr*> &ReMatedMIs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000260 };
261}
262
Chris Lattner66cf80f2006-02-03 23:13:58 +0000263/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
264/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000265///
266/// Note that not all physregs are created equal here. In particular, some
267/// physregs are reloads that we are allowed to clobber or ignore at any time.
268/// Other physregs are values that the register allocated program is using that
269/// we cannot CHANGE, but we can read if we like. We keep track of this on a
270/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
271/// entries. The predicate 'canClobberPhysReg()' checks this bit and
272/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000273namespace {
274class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000275 const MRegisterInfo *MRI;
276 const TargetInstrInfo *TII;
277
278 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
279 // register values that are still available, due to being loaded or stored to,
Evan Chengb9591c62007-07-11 08:47:44 +0000280 // but not invalidated yet.
281 std::map<int, unsigned> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000282
283 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
284 // which stack slot values are currently held by a physreg. This is used to
285 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
286 std::multimap<unsigned, int> PhysRegsAvailable;
287
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000288 void disallowClobberPhysRegOnly(unsigned PhysReg);
289
Chris Lattner66cf80f2006-02-03 23:13:58 +0000290 void ClobberPhysRegOnly(unsigned PhysReg);
291public:
292 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
293 : MRI(mri), TII(tii) {
294 }
295
Evan Cheng91e23902007-02-23 01:13:26 +0000296 const MRegisterInfo *getRegInfo() const { return MRI; }
297
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Chengb9591c62007-07-11 08:47:44 +0000299 /// physical register, return that PhysReg, otherwise return 0.
300 unsigned getSpillSlotPhysReg(int Slot) const {
301 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
Evan Cheng91e23902007-02-23 01:13:26 +0000302 if (I != SpillSlotsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000303 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000304 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000305 return 0;
306 }
Evan Chengde4e9422007-02-25 09:51:27 +0000307
Chris Lattner66cf80f2006-02-03 23:13:58 +0000308 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000309 /// specified physreg. If CanClobber is true, the physreg can be modified at
310 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000311 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
312 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000313 // If this stack slot is thought to be available in some other physreg,
314 // remove its record.
315 ModifyStackSlot(Slot);
316
Chris Lattner66cf80f2006-02-03 23:13:58 +0000317 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Chengb9591c62007-07-11 08:47:44 +0000318 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000319
Evan Cheng2638e1a2007-03-20 08:13:50 +0000320 if (Slot > VirtRegMap::MAX_STACK_SLOT)
321 DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1;
322 else
323 DOUT << "Remembering SS#" << Slot;
324 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000325 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000326
Chris Lattner593c9582006-02-03 23:28:46 +0000327 /// canClobberPhysReg - Return true if the spiller is allowed to change the
328 /// value of the specified stackslot register if it desires. The specified
329 /// stack slot must be available in a physreg for this query to make sense.
330 bool canClobberPhysReg(int Slot) const {
331 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Chengb9591c62007-07-11 08:47:44 +0000332 return SpillSlotsAvailable.find(Slot)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000333 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000334
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000335 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
336 /// stackslot register. The register is still available but is no longer
337 /// allowed to be modifed.
338 void disallowClobberPhysReg(unsigned PhysReg);
339
Chris Lattner66cf80f2006-02-03 23:13:58 +0000340 /// ClobberPhysReg - This is called when the specified physreg changes
341 /// value. We use this to invalidate any info about stuff we thing lives in
342 /// it and any of its aliases.
343 void ClobberPhysReg(unsigned PhysReg);
344
345 /// ModifyStackSlot - This method is called when the value in a stack slot
346 /// changes. This removes information about which register the previous value
347 /// for this slot lives in (as the previous value is dead now).
348 void ModifyStackSlot(int Slot);
349};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000350}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000351
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000352/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
353/// stackslot register. The register is still available but is no longer
354/// allowed to be modifed.
355void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
356 std::multimap<unsigned, int>::iterator I =
357 PhysRegsAvailable.lower_bound(PhysReg);
358 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
359 int Slot = I->second;
360 I++;
Evan Chengb9591c62007-07-11 08:47:44 +0000361 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000362 "Bidirectional map mismatch!");
Evan Chengb9591c62007-07-11 08:47:44 +0000363 SpillSlotsAvailable[Slot] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000364 DOUT << "PhysReg " << MRI->getName(PhysReg)
365 << " copied, it is available for use but can no longer be modified\n";
366 }
367}
368
369/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
370/// stackslot register and its aliases. The register and its aliases may
371/// still available but is no longer allowed to be modifed.
372void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
373 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
374 disallowClobberPhysRegOnly(*AS);
375 disallowClobberPhysRegOnly(PhysReg);
376}
377
Chris Lattner66cf80f2006-02-03 23:13:58 +0000378/// ClobberPhysRegOnly - This is called when the specified physreg changes
379/// value. We use this to invalidate any info about stuff we thing lives in it.
380void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
381 std::multimap<unsigned, int>::iterator I =
382 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000383 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000384 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000385 PhysRegsAvailable.erase(I++);
Evan Chengb9591c62007-07-11 08:47:44 +0000386 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000387 "Bidirectional map mismatch!");
388 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000389 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000390 << " clobbered, invalidating ";
391 if (Slot > VirtRegMap::MAX_STACK_SLOT)
392 DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
393 else
394 DOUT << "SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000395 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000396}
397
Chris Lattner66cf80f2006-02-03 23:13:58 +0000398/// ClobberPhysReg - This is called when the specified physreg changes
399/// value. We use this to invalidate any info about stuff we thing lives in
400/// it and any of its aliases.
401void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000402 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000403 ClobberPhysRegOnly(*AS);
404 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000405}
406
Chris Lattner07cf1412006-02-03 00:36:31 +0000407/// ModifyStackSlot - This method is called when the value in a stack slot
408/// changes. This removes information about which register the previous value
409/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000410void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Chengb9591c62007-07-11 08:47:44 +0000411 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000412 if (It == SpillSlotsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000413 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000414 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000415
416 // This register may hold the value of multiple stack slots, only remove this
417 // stack slot from the set of values the register contains.
418 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
419 for (; ; ++I) {
420 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
421 "Map inverse broken!");
422 if (I->second == Slot) break;
423 }
424 PhysRegsAvailable.erase(I);
425}
426
427
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000428
Evan Cheng28bb4622007-07-11 19:17:18 +0000429/// InvalidateKills - MI is going to be deleted. If any of its operands are
430/// marked kill, then invalidate the information.
431static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
432 std::vector<MachineOperand*> &KillOps) {
433 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
434 MachineOperand &MO = MI.getOperand(i);
435 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
436 continue;
437 unsigned Reg = MO.getReg();
438 if (KillOps[Reg] == &MO) {
439 RegKills.reset(Reg);
440 KillOps[Reg] = NULL;
441 }
442 }
443}
444
445/// UpdateKills - Track and update kill info. If a MI reads a register that is
446/// marked kill, then it must be due to register reuse. Transfer the kill info
447/// over.
448static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
449 std::vector<MachineOperand*> &KillOps) {
450 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
451 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
452 MachineOperand &MO = MI.getOperand(i);
453 if (!MO.isReg() || !MO.isUse())
454 continue;
455 unsigned Reg = MO.getReg();
456 if (Reg == 0)
457 continue;
458
459 if (RegKills[Reg]) {
460 // That can't be right. Register is killed but not re-defined and it's
461 // being reused. Let's fix that.
462 KillOps[Reg]->unsetIsKill();
463 if (i < TID->numOperands &&
464 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
465 // Unless it's a two-address operand, this is the new kill.
466 MO.setIsKill();
467 }
468
469 if (MO.isKill()) {
470 RegKills.set(Reg);
471 KillOps[Reg] = &MO;
472 }
473 }
474
475 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
476 const MachineOperand &MO = MI.getOperand(i);
477 if (!MO.isReg() || !MO.isDef())
478 continue;
479 unsigned Reg = MO.getReg();
480 RegKills.reset(Reg);
481 KillOps[Reg] = NULL;
482 }
483}
484
485
Chris Lattner7fb64342004-10-01 19:04:51 +0000486// ReusedOp - For each reused operand, we keep track of a bit of information, in
487// case we need to rollback upon processing a new operand. See comments below.
488namespace {
489 struct ReusedOp {
490 // The MachineInstr operand that reused an available value.
491 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000492
Chris Lattner7fb64342004-10-01 19:04:51 +0000493 // StackSlot - The spill slot of the value being reused.
494 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000495
Chris Lattner7fb64342004-10-01 19:04:51 +0000496 // PhysRegReused - The physical register the value was available in.
497 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000498
Chris Lattner7fb64342004-10-01 19:04:51 +0000499 // AssignedPhysReg - The physreg that was assigned for use by the reload.
500 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000501
502 // VirtReg - The virtual register itself.
503 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000504
Chris Lattner8a61a752005-10-06 17:19:06 +0000505 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
506 unsigned vreg)
507 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
508 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000509 };
Chris Lattner540fec62006-02-25 01:51:33 +0000510
511 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
512 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000513 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000514 MachineInstr &MI;
515 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000516 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000517 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000518 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000519 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000520 }
Chris Lattner540fec62006-02-25 01:51:33 +0000521
522 bool hasReuses() const {
523 return !Reuses.empty();
524 }
525
526 /// addReuse - If we choose to reuse a virtual register that is already
527 /// available instead of reloading it, remember that we did so.
528 void addReuse(unsigned OpNo, unsigned StackSlot,
529 unsigned PhysRegReused, unsigned AssignedPhysReg,
530 unsigned VirtReg) {
531 // If the reload is to the assigned register anyway, no undo will be
532 // required.
533 if (PhysRegReused == AssignedPhysReg) return;
534
535 // Otherwise, remember this.
536 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
537 AssignedPhysReg, VirtReg));
538 }
Evan Chenge077ef62006-11-04 00:21:55 +0000539
540 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000541 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000542 }
543
544 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000545 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000546 }
Chris Lattner540fec62006-02-25 01:51:33 +0000547
548 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
549 /// is some other operand that is using the specified register, either pick
550 /// a new register to use, or evict the previous reload and use this reg.
551 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
552 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000553 std::map<int, MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000554 SmallSet<unsigned, 8> &Rejected,
555 BitVector &RegKills,
556 std::vector<MachineOperand*> &KillOps) {
Chris Lattner540fec62006-02-25 01:51:33 +0000557 if (Reuses.empty()) return PhysReg; // This is most often empty.
558
559 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
560 ReusedOp &Op = Reuses[ro];
561 // If we find some other reuse that was supposed to use this register
562 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000563 // register. That is, unless its reload register has already been
564 // considered and subsequently rejected because it has also been reused
565 // by another operand.
566 if (Op.PhysRegReused == PhysReg &&
567 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000568 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000569 unsigned NewReg = Op.AssignedPhysReg;
570 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000571 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
572 RegKills, KillOps);
Chris Lattner540fec62006-02-25 01:51:33 +0000573 } else {
574 // Otherwise, we might also have a problem if a previously reused
575 // value aliases the new register. If so, codegen the previous reload
576 // and use this one.
577 unsigned PRRU = Op.PhysRegReused;
578 const MRegisterInfo *MRI = Spills.getRegInfo();
579 if (MRI->areAliases(PRRU, PhysReg)) {
580 // Okay, we found out that an alias of a reused register
581 // was used. This isn't good because it means we have
582 // to undo a previous reuse.
583 MachineBasicBlock *MBB = MI->getParent();
584 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000585 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
586
587 // Copy Op out of the vector and remove it, we're going to insert an
588 // explicit load for it.
589 ReusedOp NewOp = Op;
590 Reuses.erase(Reuses.begin()+ro);
591
592 // Ok, we're going to try to reload the assigned physreg into the
593 // slot that we were supposed to in the first place. However, that
594 // register could hold a reuse. Check to see if it conflicts or
595 // would prefer us to use a different register.
596 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000597 MI, Spills, MaybeDeadStores,
598 Rejected, RegKills, KillOps);
Chris Lattner28bad082006-02-25 02:17:31 +0000599
600 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
601 NewOp.StackSlot, AliasRC);
602 Spills.ClobberPhysReg(NewPhysReg);
603 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000604
605 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000606 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000607
Chris Lattnere53f4a02006-05-04 17:52:23 +0000608 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000609
Evan Cheng91e23902007-02-23 01:13:26 +0000610 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000611 ++NumLoads;
Evan Cheng28bb4622007-07-11 19:17:18 +0000612 MachineBasicBlock::iterator MII = MI;
613 --MII;
614 UpdateKills(*MII, RegKills, KillOps);
615 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000616
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000617 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000618 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000619
620 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000621 return PhysReg;
622 }
623 }
624 }
625 return PhysReg;
626 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000627
628 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
629 /// 'Rejected' set to remember which registers have been considered and
630 /// rejected for the reload. This avoids infinite looping in case like
631 /// this:
632 /// t1 := op t2, t3
633 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
634 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
635 /// t1 <- desires r1
636 /// sees r1 is taken by t2, tries t2's reload register r0
637 /// sees r0 is taken by t3, tries t3's reload register r1
638 /// sees r1 is taken by t2, tries t2's reload register r0 ...
639 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
640 AvailableSpills &Spills,
Evan Cheng28bb4622007-07-11 19:17:18 +0000641 std::map<int, MachineInstr*> &MaybeDeadStores,
642 BitVector &RegKills,
643 std::vector<MachineOperand*> &KillOps) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000644 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000645 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
646 RegKills, KillOps);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000647 }
Chris Lattner540fec62006-02-25 01:51:33 +0000648 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000649}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000650
Chris Lattner7fb64342004-10-01 19:04:51 +0000651
652/// rewriteMBB - Keep track of which spills are available even after the
653/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000654void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
655 std::vector<MachineInstr*> &ReMatedMIs) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000656 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000657
Chris Lattner66cf80f2006-02-03 23:13:58 +0000658 // Spills - Keep track of which spilled values are available in physregs so
659 // that we can choose to reuse the physregs instead of emitting reloads.
660 AvailableSpills Spills(MRI, TII);
661
Chris Lattner52b25db2004-10-01 19:47:12 +0000662 // MaybeDeadStores - When we need to write a value back into a stack slot,
663 // keep track of the inserted store. If the stack slot value is never read
664 // (because the value was used from some available register, for example), and
665 // subsequently stored to, the original store is dead. This map keeps track
666 // of inserted stores that are not used. If we see a subsequent store to the
667 // same stack slot, the original store is deleted.
668 std::map<int, MachineInstr*> MaybeDeadStores;
669
Evan Cheng0c40d722007-07-11 05:28:39 +0000670 // Keep track of kill information.
671 BitVector RegKills(MRI->getNumRegs());
672 std::vector<MachineOperand*> KillOps;
673 KillOps.resize(MRI->getNumRegs(), NULL);
674
Evan Cheng6c087e52007-04-25 22:13:27 +0000675 MachineFunction &MF = *MBB.getParent();
Chris Lattner7fb64342004-10-01 19:04:51 +0000676 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
677 MII != E; ) {
678 MachineInstr &MI = *MII;
679 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000680 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
681
682 bool Erased = false;
683 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000684
Chris Lattner540fec62006-02-25 01:51:33 +0000685 /// ReusedOperands - Keep track of operand reuse in case we need to undo
686 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000687 ReuseInfo ReusedOperands(MI, MRI);
688
689 // Loop over all of the implicit defs, clearing them from our available
690 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000691 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng2638e1a2007-03-20 08:13:50 +0000692
693 // If this instruction is being rematerialized, just remove it!
Evan Cheng91935142007-04-04 07:40:01 +0000694 int FrameIdx;
Dan Gohman82a87a02007-06-19 01:48:05 +0000695 if (TII->isTriviallyReMaterializable(&MI) ||
696 TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Evan Cheng0c40d722007-07-11 05:28:39 +0000697 Erased = true;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000698 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
699 MachineOperand &MO = MI.getOperand(i);
700 if (!MO.isRegister() || MO.getReg() == 0)
701 continue; // Ignore non-register operands.
702 if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) {
Evan Cheng0c40d722007-07-11 05:28:39 +0000703 Erased = false;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000704 break;
705 }
706 }
Evan Cheng0c40d722007-07-11 05:28:39 +0000707 if (Erased) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000708 VRM.RemoveFromFoldedVirtMap(&MI);
709 ReMatedMIs.push_back(MI.removeFromParent());
Evan Cheng0c40d722007-07-11 05:28:39 +0000710 goto ProcessNextInst;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000711 }
712 }
713
Evan Cheng0c40d722007-07-11 05:28:39 +0000714 if (TID->ImplicitDefs) {
715 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000716 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000717 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000718 ReusedOperands.markClobbered(*ImpDef);
719 Spills.ClobberPhysReg(*ImpDef);
720 }
721 }
722
Chris Lattner7fb64342004-10-01 19:04:51 +0000723 // Process all of the spilled uses and all non spilled reg references.
724 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
725 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000726 if (!MO.isRegister() || MO.getReg() == 0)
727 continue; // Ignore non-register operands.
728
729 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
730 // Ignore physregs for spilling, but remember that it is used by this
731 // function.
Evan Cheng6c087e52007-04-25 22:13:27 +0000732 MF.setPhysRegUsed(MO.getReg());
Evan Chenge077ef62006-11-04 00:21:55 +0000733 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000734 continue;
735 }
736
737 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
738 "Not a virtual or a physical register?");
739
740 unsigned VirtReg = MO.getReg();
741 if (!VRM.hasStackSlot(VirtReg)) {
742 // This virtual register was assigned a physreg!
743 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000744 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000745 if (MO.isDef())
746 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000747 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000748 continue;
749 }
750
751 // This virtual register is now known to be a spilled value.
752 if (!MO.isUse())
753 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000754
Evan Cheng2638e1a2007-03-20 08:13:50 +0000755 bool doReMat = VRM.isReMaterialized(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000756 int StackSlot = VRM.getStackSlot(VirtReg);
757 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000758
Chris Lattner50ea01e2005-09-09 20:29:51 +0000759 // Check to see if this stack slot is available.
Evan Chengb9591c62007-07-11 08:47:44 +0000760 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner29268692006-09-05 02:12:02 +0000761 // This spilled operand might be part of a two-address operand. If this
762 // is the case, then changing it will necessarily require changing the
763 // def part of the instruction as well. However, in some cases, we
764 // aren't allowed to modify the reused register. If none of these cases
765 // apply, reuse it.
766 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000767 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000768 if (ti != -1 &&
769 MI.getOperand(ti).isReg() &&
770 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000771 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000772 // long as we are allowed to clobber the value and there isn't an
773 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000774 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
775 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000776 }
777
778 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000779 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000780 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
781 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
782 else
783 DOUT << "Reusing SS#" << StackSlot;
784 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000785 << MRI->getName(PhysReg) << " for vreg"
786 << VirtReg <<" instead of reloading into physreg "
787 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000788 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000789
790 // The only technical detail we have is that we don't know that
791 // PhysReg won't be clobbered by a reloaded stack slot that occurs
792 // later in the instruction. In particular, consider 'op V1, V2'.
793 // If V1 is available in physreg R0, we would choose to reuse it
794 // here, instead of reloading it into the register the allocator
795 // indicated (say R1). However, V2 might have to be reloaded
796 // later, and it might indicate that it needs to live in R0. When
797 // this occurs, we need to have information available that
798 // indicates it is safe to use R1 for the reload instead of R0.
799 //
800 // To further complicate matters, we might conflict with an alias,
801 // or R0 and R1 might not be compatible with each other. In this
802 // case, we actually insert a reload for V1 in R1, ensuring that
803 // we can get at R0 or its alias.
804 ReusedOperands.addReuse(i, StackSlot, PhysReg,
805 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000806 if (ti != -1)
807 // Only mark it clobbered if this is a use&def operand.
808 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000809 ++NumReused;
810 continue;
811 }
812
813 // Otherwise we have a situation where we have a two-address instruction
814 // whose mod/ref operand needs to be reloaded. This reload is already
815 // available in some register "PhysReg", but if we used PhysReg as the
816 // operand to our 2-addr instruction, the instruction would modify
817 // PhysReg. This isn't cool if something later uses PhysReg and expects
818 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000819 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000820 // To avoid this problem, and to avoid doing a load right after a store,
821 // we emit a copy from PhysReg into the designated register for this
822 // operand.
823 unsigned DesignatedReg = VRM.getPhys(VirtReg);
824 assert(DesignatedReg && "Must map virtreg to physreg!");
825
826 // Note that, if we reused a register for a previous operand, the
827 // register we want to reload into might not actually be
828 // available. If this occurs, use the register indicated by the
829 // reuser.
830 if (ReusedOperands.hasReuses())
831 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng28bb4622007-07-11 19:17:18 +0000832 Spills, MaybeDeadStores, RegKills, KillOps);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000833
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000834 // If the mapped designated register is actually the physreg we have
835 // incoming, we don't need to inserted a dead copy.
836 if (DesignatedReg == PhysReg) {
837 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000838 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
839 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
840 else
841 DOUT << "Reusing SS#" << StackSlot;
842 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000843 << VirtReg
844 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000845 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000846 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000847 ++NumReused;
848 continue;
849 }
850
Evan Cheng6c087e52007-04-25 22:13:27 +0000851 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
852 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000853 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000854 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000855
Evan Cheng6b448092007-03-02 08:52:00 +0000856 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000857 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000858
Chris Lattneraddc55a2006-04-28 01:46:50 +0000859 // This invalidates DesignatedReg.
860 Spills.ClobberPhysReg(DesignatedReg);
861
Evan Cheng91e23902007-02-23 01:13:26 +0000862 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000863 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000864 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000865 ++NumReused;
866 continue;
867 }
868
869 // Otherwise, reload it and remember that we have it.
870 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000871 assert(PhysReg && "Must map virtreg to physreg!");
Evan Cheng6c087e52007-04-25 22:13:27 +0000872 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000873
Chris Lattner50ea01e2005-09-09 20:29:51 +0000874 // Note that, if we reused a register for a previous operand, the
875 // register we want to reload into might not actually be
876 // available. If this occurs, use the register indicated by the
877 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000878 if (ReusedOperands.hasReuses())
879 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng28bb4622007-07-11 19:17:18 +0000880 Spills, MaybeDeadStores, RegKills, KillOps);
Chris Lattner540fec62006-02-25 01:51:33 +0000881
Evan Cheng6c087e52007-04-25 22:13:27 +0000882 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000883 ReusedOperands.markClobbered(PhysReg);
Evan Cheng91935142007-04-04 07:40:01 +0000884 if (doReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000885 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000886 ++NumReMats;
887 } else {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000888 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000889 ++NumLoads;
890 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000891 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000892 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000893
894 // Any stores to this stack slot are not dead anymore.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000895 if (!doReMat)
896 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000897 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000898 // Assumes this is the last use. IsKill will be unset if reg is reused
899 // unless it's a two-address operand.
900 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
901 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000902 MI.getOperand(i).setReg(PhysReg);
Evan Cheng0c40d722007-07-11 05:28:39 +0000903 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000904 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000905 }
906
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000907 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000908
Chris Lattner7fb64342004-10-01 19:04:51 +0000909 // If we have folded references to memory operands, make sure we clear all
910 // physical registers that may contain the value of the spilled virtual
911 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000912 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000913 DOUT << "Folded vreg: " << I->second.first << " MR: "
914 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000915 unsigned VirtReg = I->second.first;
916 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000917 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000918 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000919 continue;
920 }
921 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000922 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000923
924 // If this folded instruction is just a use, check to see if it's a
925 // straight load from the virt reg slot.
926 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
927 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000928 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000929 if (FrameIdx == SS) {
930 // If this spill slot is available, turn it into a copy (or nothing)
931 // instead of leaving it as a load!
Evan Chengb9591c62007-07-11 08:47:44 +0000932 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000934 if (DestReg != InReg) {
935 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
936 MF.getSSARegMap()->getRegClass(VirtReg));
937 // Revisit the copy so we make sure to notice the effects of the
938 // operation on the destreg (either needing to RA it if it's
939 // virtual or needing to clobber any values if it's physical).
940 NextMII = &MI;
941 --NextMII; // backtrack to the copy.
Evan Cheng0c40d722007-07-11 05:28:39 +0000942 BackTracked = true;
Evan Chengde4e9422007-02-25 09:51:27 +0000943 } else
944 DOUT << "Removing now-noop copy: " << MI;
945
Chris Lattner6ec36262006-10-12 17:45:38 +0000946 VRM.RemoveFromFoldedVirtMap(&MI);
947 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +0000948 Erased = true;
Chris Lattner6ec36262006-10-12 17:45:38 +0000949 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000950 }
Chris Lattnercea86882005-09-19 06:56:21 +0000951 }
952 }
953 }
954
955 // If this reference is not a use, any previous store is now dead.
956 // Otherwise, the store to this stack slot is not dead anymore.
957 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
958 if (MDSI != MaybeDeadStores.end()) {
959 if (MR & VirtRegMap::isRef) // Previous store is not dead.
960 MaybeDeadStores.erase(MDSI);
961 else {
962 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000963 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000964 DOUT << "Removed dead store:\t" << *MDSI->second;
Evan Cheng0c40d722007-07-11 05:28:39 +0000965 InvalidateKills(*MDSI->second, RegKills, KillOps);
Chris Lattner35f27052006-05-01 21:16:03 +0000966 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000967 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000968 MaybeDeadStores.erase(MDSI);
969 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000970 }
971 }
972
973 // If the spill slot value is available, and this is a new definition of
974 // the value, the value is not available anymore.
975 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000976 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000977 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000978
979 // If this is *just* a mod of the value, check to see if this is just a
980 // store to the spill slot (i.e. the spill got merged into the copy). If
981 // so, realize that the vreg is available now, and add the store to the
982 // MaybeDeadStore info.
983 int StackSlot;
984 if (!(MR & VirtRegMap::isRef)) {
985 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
986 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
987 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000988 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000989 // this as a potentially dead store in case there is a subsequent
990 // store into the stack slot without a read from it.
991 MaybeDeadStores[StackSlot] = &MI;
992
Chris Lattnercd816392006-02-02 23:29:36 +0000993 // If the stack slot value was previously available in some other
994 // register, change it now. Otherwise, make the register available,
995 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +0000996 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000997 }
998 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000999 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001000 }
1001
Chris Lattner7fb64342004-10-01 19:04:51 +00001002 // Process all of the spilled defs.
1003 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1004 MachineOperand &MO = MI.getOperand(i);
1005 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1006 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001007
Chris Lattner7fb64342004-10-01 19:04:51 +00001008 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001009 // Check to see if this is a noop copy. If so, eliminate the
1010 // instruction before considering the dest reg to be changed.
1011 unsigned Src, Dst;
1012 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1013 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001014 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001015 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001016 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001017 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001018 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001019 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001020 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001021
1022 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001023 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001024 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001025
1026 // Check to see if this instruction is a load from a stack slot into
1027 // a register. If so, this provides the stack slot value in the reg.
1028 int FrameIdx;
1029 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1030 assert(DestReg == VirtReg && "Unknown load situation!");
1031
1032 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001033 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001034 goto ProcessNextInst;
1035 }
1036
Chris Lattner29268692006-09-05 02:12:02 +00001037 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001038 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001039
Chris Lattner84e752a2006-02-03 03:06:49 +00001040 // The only vregs left are stack slot definitions.
1041 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001042 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001043
Chris Lattner29268692006-09-05 02:12:02 +00001044 // If this def is part of a two-address operand, make sure to execute
1045 // the store from the correct physical register.
1046 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001047 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001048 if (TiedOp != -1)
1049 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001050 else {
Chris Lattner29268692006-09-05 02:12:02 +00001051 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001052 if (ReusedOperands.isClobbered(PhysReg)) {
1053 // Another def has taken the assigned physreg. It must have been a
1054 // use&def which got it due to reuse. Undo the reuse!
1055 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng28bb4622007-07-11 19:17:18 +00001056 Spills, MaybeDeadStores, RegKills, KillOps);
Evan Chenge077ef62006-11-04 00:21:55 +00001057 }
1058 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001059
Evan Cheng6c087e52007-04-25 22:13:27 +00001060 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001061 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001062 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001063 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001064 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001065
Chris Lattner84e752a2006-02-03 03:06:49 +00001066 // If there is a dead store to this stack slot, nuke it now.
1067 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1068 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001069 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001070 ++NumDSE;
Evan Cheng0c40d722007-07-11 05:28:39 +00001071 InvalidateKills(*LastStore, RegKills, KillOps);
Chris Lattner84e752a2006-02-03 03:06:49 +00001072 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001073 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001074 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001075 LastStore = next(MII);
1076
1077 // If the stack slot value was previously available in some other
1078 // register, change it now. Otherwise, make the register available,
1079 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001080 Spills.ModifyStackSlot(StackSlot);
1081 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001082 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001083 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001084
1085 // Check to see if this is a noop copy. If so, eliminate the
1086 // instruction before considering the dest reg to be changed.
1087 {
1088 unsigned Src, Dst;
1089 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1090 ++NumDCE;
1091 DOUT << "Removing now-noop copy: " << MI;
1092 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001093 Erased = true;
Evan Chengf50d09a2007-02-08 06:04:54 +00001094 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng28bb4622007-07-11 19:17:18 +00001095 UpdateKills(*LastStore, RegKills, KillOps);
Evan Chengf50d09a2007-02-08 06:04:54 +00001096 goto ProcessNextInst;
1097 }
1098 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001099 }
1100 }
Chris Lattnercea86882005-09-19 06:56:21 +00001101 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001102 if (!Erased && !BackTracked)
1103 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1104 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001105 MII = NextMII;
1106 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001107}
1108
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001109
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001110llvm::Spiller* llvm::createSpiller() {
1111 switch (SpillerOpt) {
1112 default: assert(0 && "Unreachable!");
1113 case local:
1114 return new LocalSpiller();
1115 case simple:
1116 return new SimpleSpiller();
1117 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001118}