Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 10 | // This file implements the VirtRegMap class. |
| 11 | // |
| 12 | // It also contains implementations of the the Spiller interface, which, given a |
| 13 | // virtual register map and a machine function, eliminates all virtual |
| 14 | // references by replacing them with physical register references - adding spill |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 15 | // code as necessary. |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 16 | // |
| 17 | //===----------------------------------------------------------------------===// |
| 18 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 19 | #define DEBUG_TYPE "spiller" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 20 | #include "VirtRegMap.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/SSARegMap.h" |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetMachine.h" |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetInstrInfo.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 27 | #include "llvm/Support/CommandLine.h" |
| 28 | #include "llvm/Support/Debug.h" |
Chris Lattner | a4f0b3a | 2006-08-27 12:54:02 +0000 | [diff] [blame] | 29 | #include "llvm/Support/Compiler.h" |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 30 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/Statistic.h" |
| 32 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 33 | #include "llvm/ADT/SmallSet.h" |
Chris Lattner | 27f2916 | 2004-10-26 15:35:58 +0000 | [diff] [blame] | 34 | #include <algorithm> |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 35 | using namespace llvm; |
| 36 | |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 37 | STATISTIC(NumSpills, "Number of register spills"); |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 38 | STATISTIC(NumReMats, "Number of re-materialization"); |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 39 | STATISTIC(NumStores, "Number of stores added"); |
| 40 | STATISTIC(NumLoads , "Number of loads added"); |
| 41 | STATISTIC(NumReused, "Number of values reused"); |
| 42 | STATISTIC(NumDSE , "Number of dead stores elided"); |
| 43 | STATISTIC(NumDCE , "Number of copies elided"); |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 44 | |
Chris Lattner | cd3245a | 2006-12-19 22:41:21 +0000 | [diff] [blame] | 45 | namespace { |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 46 | enum SpillerName { simple, local }; |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 47 | |
Andrew Lenharth | ed41f1b | 2006-07-20 17:28:38 +0000 | [diff] [blame] | 48 | static cl::opt<SpillerName> |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 49 | SpillerOpt("spiller", |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 50 | cl::desc("Spiller to use: (default: local)"), |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 51 | cl::Prefix, |
| 52 | cl::values(clEnumVal(simple, " simple spiller"), |
| 53 | clEnumVal(local, " local spiller"), |
| 54 | clEnumValEnd), |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 55 | cl::init(local)); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 56 | } |
| 57 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 58 | //===----------------------------------------------------------------------===// |
| 59 | // VirtRegMap implementation |
| 60 | //===----------------------------------------------------------------------===// |
| 61 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 62 | VirtRegMap::VirtRegMap(MachineFunction &mf) |
| 63 | : TII(*mf.getTarget().getInstrInfo()), MF(mf), |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 64 | Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), |
| 65 | ReMatId(MAX_STACK_SLOT+1) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 66 | grow(); |
| 67 | } |
| 68 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 69 | void VirtRegMap::grow() { |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 70 | Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); |
| 71 | Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 72 | } |
| 73 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 74 | int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { |
| 75 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 76 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 77 | "attempt to assign stack slot to already spilled register"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 78 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); |
| 79 | int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 80 | RC->getAlignment()); |
| 81 | Virt2StackSlotMap[virtReg] = frameIndex; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 82 | ++NumSpills; |
| 83 | return frameIndex; |
| 84 | } |
| 85 | |
| 86 | void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { |
| 87 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 88 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 89 | "attempt to assign stack slot to already spilled register"); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 90 | assert((frameIndex >= 0 || |
| 91 | (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && |
| 92 | "illegal fixed frame index"); |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 93 | Virt2StackSlotMap[virtReg] = frameIndex; |
Alkis Evlogimenos | 38af59a | 2004-05-29 20:38:05 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 96 | int VirtRegMap::assignVirtReMatId(unsigned virtReg) { |
| 97 | assert(MRegisterInfo::isVirtualRegister(virtReg)); |
| 98 | assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && |
| 99 | "attempt to assign re-mat id to already spilled register"); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 100 | const MachineInstr *DefMI = getReMaterializedMI(virtReg); |
| 101 | int FrameIdx; |
| 102 | if (TII.isLoadFromStackSlot((MachineInstr*)DefMI, FrameIdx)) { |
| 103 | // Load from stack slot is re-materialize as reload from the stack slot! |
| 104 | Virt2StackSlotMap[virtReg] = FrameIdx; |
| 105 | return FrameIdx; |
| 106 | } |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 107 | Virt2StackSlotMap[virtReg] = ReMatId; |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 108 | return ReMatId++; |
| 109 | } |
| 110 | |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 111 | void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 112 | unsigned OpNo, MachineInstr *NewMI) { |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 113 | // Move previous memory references folded to new instruction. |
| 114 | MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 115 | for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 116 | E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { |
| 117 | MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 118 | MI2VirtMap.erase(I++); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 119 | } |
Chris Lattner | dbea973 | 2004-09-30 16:35:08 +0000 | [diff] [blame] | 120 | |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 121 | ModRef MRInfo; |
Evan Cheng | 5c2a460 | 2006-12-08 08:02:34 +0000 | [diff] [blame] | 122 | const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor(); |
| 123 | if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 || |
Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 124 | TID->findTiedToSrcOperand(OpNo) != -1) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 125 | // Folded a two-address operand. |
| 126 | MRInfo = isModRef; |
| 127 | } else if (OldMI->getOperand(OpNo).isDef()) { |
| 128 | MRInfo = isMod; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 129 | } else { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 130 | MRInfo = isRef; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 131 | } |
Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 132 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 133 | // add new memory reference |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 134 | MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); |
Alkis Evlogimenos | 5f37502 | 2004-03-01 20:05:10 +0000 | [diff] [blame] | 135 | } |
| 136 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 137 | void VirtRegMap::print(std::ostream &OS) const { |
| 138 | const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 139 | |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 140 | OS << "********** REGISTER MAP **********\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 141 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 142 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { |
| 143 | if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) |
| 144 | OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 145 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | for (unsigned i = MRegisterInfo::FirstVirtualRegister, |
Chris Lattner | 7f690e6 | 2004-09-30 02:15:18 +0000 | [diff] [blame] | 149 | e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) |
| 150 | if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) |
| 151 | OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; |
| 152 | OS << '\n'; |
Alkis Evlogimenos | 34d9bc9 | 2004-02-23 23:08:11 +0000 | [diff] [blame] | 153 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 154 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 155 | void VirtRegMap::dump() const { |
Bill Wendling | 5c7e326 | 2006-12-17 05:15:13 +0000 | [diff] [blame] | 156 | print(DOUT); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 157 | } |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 158 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 159 | |
| 160 | //===----------------------------------------------------------------------===// |
| 161 | // Simple Spiller Implementation |
| 162 | //===----------------------------------------------------------------------===// |
| 163 | |
| 164 | Spiller::~Spiller() {} |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 165 | |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 166 | namespace { |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 167 | struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 168 | bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 169 | }; |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 170 | } |
| 171 | |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 172 | bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 173 | DOUT << "********** REWRITE MACHINE CODE **********\n"; |
| 174 | DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; |
Chris Lattner | b0f31bf | 2005-01-23 22:45:13 +0000 | [diff] [blame] | 175 | const TargetMachine &TM = MF.getTarget(); |
| 176 | const MRegisterInfo &MRI = *TM.getRegisterInfo(); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 177 | |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 178 | // LoadedRegs - Keep track of which vregs are loaded, so that we only load |
| 179 | // each vreg once (in the case where a spilled vreg is used by multiple |
| 180 | // operands). This is always smaller than the number of operands to the |
| 181 | // current machine instr, so it should be small. |
| 182 | std::vector<unsigned> LoadedRegs; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 183 | |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 184 | for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); |
| 185 | MBBI != E; ++MBBI) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 186 | DOUT << MBBI->getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 187 | MachineBasicBlock &MBB = *MBBI; |
| 188 | for (MachineBasicBlock::iterator MII = MBB.begin(), |
| 189 | E = MBB.end(); MII != E; ++MII) { |
| 190 | MachineInstr &MI = *MII; |
| 191 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 192 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 193 | if (MO.isRegister() && MO.getReg()) |
| 194 | if (MRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 195 | unsigned VirtReg = MO.getReg(); |
| 196 | unsigned PhysReg = VRM.getPhys(VirtReg); |
| 197 | if (VRM.hasStackSlot(VirtReg)) { |
| 198 | int StackSlot = VRM.getStackSlot(VirtReg); |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 199 | const TargetRegisterClass* RC = |
| 200 | MF.getSSARegMap()->getRegClass(VirtReg); |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 201 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 202 | if (MO.isUse() && |
| 203 | std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) |
| 204 | == LoadedRegs.end()) { |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 205 | MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 206 | LoadedRegs.push_back(VirtReg); |
| 207 | ++NumLoads; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 208 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 209 | } |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 210 | |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 211 | if (MO.isDef()) { |
Chris Lattner | bf9716b | 2005-09-30 01:29:00 +0000 | [diff] [blame] | 212 | MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 213 | ++NumStores; |
| 214 | } |
Chris Lattner | 0fc27cc | 2004-09-30 02:59:33 +0000 | [diff] [blame] | 215 | } |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 216 | MF.setPhysRegUsed(PhysReg); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 217 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 218 | } else { |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 219 | MF.setPhysRegUsed(MO.getReg()); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 220 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 221 | } |
Chris Lattner | 886dd91 | 2005-04-04 21:35:34 +0000 | [diff] [blame] | 222 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 223 | DOUT << '\t' << MI; |
Chris Lattner | 4ea1b82 | 2004-09-30 02:33:48 +0000 | [diff] [blame] | 224 | LoadedRegs.clear(); |
Alkis Evlogimenos | dd420e0 | 2004-03-01 23:18:15 +0000 | [diff] [blame] | 225 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 226 | } |
| 227 | return true; |
| 228 | } |
| 229 | |
| 230 | //===----------------------------------------------------------------------===// |
| 231 | // Local Spiller Implementation |
| 232 | //===----------------------------------------------------------------------===// |
| 233 | |
| 234 | namespace { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 235 | /// LocalSpiller - This spiller does a simple pass over the machine basic |
| 236 | /// block to attempt to keep spills in registers as much as possible for |
| 237 | /// blocks that have low register pressure (the vreg may be spilled due to |
| 238 | /// register pressure in other blocks). |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 239 | class VISIBILITY_HIDDEN LocalSpiller : public Spiller { |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 240 | const MRegisterInfo *MRI; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 241 | const TargetInstrInfo *TII; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 242 | public: |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 243 | bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 244 | MRI = MF.getTarget().getRegisterInfo(); |
| 245 | TII = MF.getTarget().getInstrInfo(); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 246 | DOUT << "\n**** Local spiller rewriting function '" |
| 247 | << MF.getFunction()->getName() << "':\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 248 | |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 249 | std::vector<MachineInstr *> ReMatedMIs; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 250 | for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); |
| 251 | MBB != E; ++MBB) |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 252 | RewriteMBB(*MBB, VRM, ReMatedMIs); |
| 253 | for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i) |
| 254 | delete ReMatedMIs[i]; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 255 | return true; |
| 256 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 257 | private: |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 258 | void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, |
| 259 | std::vector<MachineInstr*> &ReMatedMIs); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 260 | }; |
| 261 | } |
| 262 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 263 | /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from |
| 264 | /// top down, keep track of which spills slots are available in each register. |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 265 | /// |
| 266 | /// Note that not all physregs are created equal here. In particular, some |
| 267 | /// physregs are reloads that we are allowed to clobber or ignore at any time. |
| 268 | /// Other physregs are values that the register allocated program is using that |
| 269 | /// we cannot CHANGE, but we can read if we like. We keep track of this on a |
| 270 | /// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable |
| 271 | /// entries. The predicate 'canClobberPhysReg()' checks this bit and |
| 272 | /// addAvailable sets it if. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 273 | namespace { |
| 274 | class VISIBILITY_HIDDEN AvailableSpills { |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 275 | const MRegisterInfo *MRI; |
| 276 | const TargetInstrInfo *TII; |
| 277 | |
| 278 | // SpillSlotsAvailable - This map keeps track of all of the spilled virtual |
| 279 | // register values that are still available, due to being loaded or stored to, |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 280 | // but not invalidated yet. It also tracks the instructions that defined |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 281 | // or used the register. |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 282 | typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo; |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 283 | std::map<int, SSInfo> SpillSlotsAvailable; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 284 | |
| 285 | // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating |
| 286 | // which stack slot values are currently held by a physreg. This is used to |
| 287 | // invalidate entries in SpillSlotsAvailable when a physreg is modified. |
| 288 | std::multimap<unsigned, int> PhysRegsAvailable; |
| 289 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 290 | void disallowClobberPhysRegOnly(unsigned PhysReg); |
| 291 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 292 | void ClobberPhysRegOnly(unsigned PhysReg); |
| 293 | public: |
| 294 | AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) |
| 295 | : MRI(mri), TII(tii) { |
| 296 | } |
| 297 | |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 298 | const MRegisterInfo *getRegInfo() const { return MRI; } |
| 299 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 300 | /// getSpillSlotPhysReg - If the specified stack slot is available in a |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 301 | /// physical register, return that PhysReg, otherwise return 0. It also |
| 302 | /// returns by reference the instruction that either defines or last uses |
| 303 | /// the register. |
| 304 | unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const { |
| 305 | std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot); |
| 306 | if (I != SpillSlotsAvailable.end()) { |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 307 | if (!I->second.second.empty()) |
| 308 | SSMI = I->second.second.back(); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 309 | return I->second.first >> 1; // Remove the CanClobber bit. |
| 310 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 311 | return 0; |
| 312 | } |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 313 | |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 314 | /// addLastUse - Add the last use information of all stack slots whose |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 315 | /// values are available in the specific register. |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 316 | void addLastUse(unsigned PhysReg, MachineInstr *Use) { |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 317 | std::multimap<unsigned, int>::iterator I = |
| 318 | PhysRegsAvailable.lower_bound(PhysReg); |
| 319 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
| 320 | int Slot = I->second; |
| 321 | I++; |
| 322 | |
| 323 | std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot); |
| 324 | assert(II != SpillSlotsAvailable.end() && "Slot not available!"); |
| 325 | unsigned Val = II->second.first; |
| 326 | assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!"); |
Evan Cheng | 7cb33c8 | 2007-03-30 20:21:35 +0000 | [diff] [blame] | 327 | // This can be true if there are multiple uses of the same register. |
| 328 | if (II->second.second.back() != Use) |
| 329 | II->second.second.push_back(Use); |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 330 | } |
| 331 | } |
| 332 | |
| 333 | /// removeLastUse - Remove the last use information of all stack slots whose |
| 334 | /// values are available in the specific register. |
| 335 | void removeLastUse(unsigned PhysReg, MachineInstr *Use) { |
| 336 | std::multimap<unsigned, int>::iterator I = |
| 337 | PhysRegsAvailable.lower_bound(PhysReg); |
| 338 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
| 339 | int Slot = I->second; |
| 340 | I++; |
| 341 | |
| 342 | std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot); |
| 343 | assert(II != SpillSlotsAvailable.end() && "Slot not available!"); |
| 344 | unsigned Val = II->second.first; |
| 345 | assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!"); |
| 346 | if (II->second.second.back() == Use) |
| 347 | II->second.second.pop_back(); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 348 | } |
| 349 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 350 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 351 | /// addAvailable - Mark that the specified stack slot is available in the |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 352 | /// specified physreg. If CanClobber is true, the physreg can be modified at |
| 353 | /// any time without changing the semantics of the program. |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 354 | void addAvailable(int Slot, MachineInstr *MI, unsigned Reg, |
| 355 | bool CanClobber = true) { |
Chris Lattner | 8666249 | 2006-02-03 23:50:46 +0000 | [diff] [blame] | 356 | // If this stack slot is thought to be available in some other physreg, |
| 357 | // remove its record. |
| 358 | ModifyStackSlot(Slot); |
| 359 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 360 | PhysRegsAvailable.insert(std::make_pair(Reg, Slot)); |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 361 | std::vector<MachineInstr*> DefUses; |
| 362 | DefUses.push_back(MI); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 363 | SpillSlotsAvailable[Slot] = |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 364 | std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses); |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 365 | |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 366 | if (Slot > VirtRegMap::MAX_STACK_SLOT) |
| 367 | DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1; |
| 368 | else |
| 369 | DOUT << "Remembering SS#" << Slot; |
| 370 | DOUT << " in physreg " << MRI->getName(Reg) << "\n"; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 371 | } |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 372 | |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 373 | /// canClobberPhysReg - Return true if the spiller is allowed to change the |
| 374 | /// value of the specified stackslot register if it desires. The specified |
| 375 | /// stack slot must be available in a physreg for this query to make sense. |
| 376 | bool canClobberPhysReg(int Slot) const { |
| 377 | assert(SpillSlotsAvailable.count(Slot) && "Slot not available!"); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 378 | return SpillSlotsAvailable.find(Slot)->second.first & 1; |
Chris Lattner | 593c958 | 2006-02-03 23:28:46 +0000 | [diff] [blame] | 379 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 380 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 381 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 382 | /// stackslot register. The register is still available but is no longer |
| 383 | /// allowed to be modifed. |
| 384 | void disallowClobberPhysReg(unsigned PhysReg); |
| 385 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 386 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 387 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 388 | /// it and any of its aliases. |
| 389 | void ClobberPhysReg(unsigned PhysReg); |
| 390 | |
| 391 | /// ModifyStackSlot - This method is called when the value in a stack slot |
| 392 | /// changes. This removes information about which register the previous value |
| 393 | /// for this slot lives in (as the previous value is dead now). |
| 394 | void ModifyStackSlot(int Slot); |
| 395 | }; |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 396 | } |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 397 | |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 398 | /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified |
| 399 | /// stackslot register. The register is still available but is no longer |
| 400 | /// allowed to be modifed. |
| 401 | void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { |
| 402 | std::multimap<unsigned, int>::iterator I = |
| 403 | PhysRegsAvailable.lower_bound(PhysReg); |
| 404 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
| 405 | int Slot = I->second; |
| 406 | I++; |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 407 | assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg && |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 408 | "Bidirectional map mismatch!"); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 409 | SpillSlotsAvailable[Slot].first &= ~1; |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 410 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
| 411 | << " copied, it is available for use but can no longer be modified\n"; |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | /// disallowClobberPhysReg - Unset the CanClobber bit of the specified |
| 416 | /// stackslot register and its aliases. The register and its aliases may |
| 417 | /// still available but is no longer allowed to be modifed. |
| 418 | void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { |
| 419 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
| 420 | disallowClobberPhysRegOnly(*AS); |
| 421 | disallowClobberPhysRegOnly(PhysReg); |
| 422 | } |
| 423 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 424 | /// ClobberPhysRegOnly - This is called when the specified physreg changes |
| 425 | /// value. We use this to invalidate any info about stuff we thing lives in it. |
| 426 | void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { |
| 427 | std::multimap<unsigned, int>::iterator I = |
| 428 | PhysRegsAvailable.lower_bound(PhysReg); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 429 | while (I != PhysRegsAvailable.end() && I->first == PhysReg) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 430 | int Slot = I->second; |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 431 | PhysRegsAvailable.erase(I++); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 432 | assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg && |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 433 | "Bidirectional map mismatch!"); |
| 434 | SpillSlotsAvailable.erase(Slot); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 435 | DOUT << "PhysReg " << MRI->getName(PhysReg) |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 436 | << " clobbered, invalidating "; |
| 437 | if (Slot > VirtRegMap::MAX_STACK_SLOT) |
| 438 | DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; |
| 439 | else |
| 440 | DOUT << "SS#" << Slot << "\n"; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 441 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 442 | } |
| 443 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 444 | /// ClobberPhysReg - This is called when the specified physreg changes |
| 445 | /// value. We use this to invalidate any info about stuff we thing lives in |
| 446 | /// it and any of its aliases. |
| 447 | void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 448 | for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 449 | ClobberPhysRegOnly(*AS); |
| 450 | ClobberPhysRegOnly(PhysReg); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 451 | } |
| 452 | |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 453 | /// ModifyStackSlot - This method is called when the value in a stack slot |
| 454 | /// changes. This removes information about which register the previous value |
| 455 | /// for this slot lives in (as the previous value is dead now). |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 456 | void AvailableSpills::ModifyStackSlot(int Slot) { |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 457 | std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot); |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 458 | if (It == SpillSlotsAvailable.end()) return; |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 459 | unsigned Reg = It->second.first >> 1; |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 460 | SpillSlotsAvailable.erase(It); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 461 | |
| 462 | // This register may hold the value of multiple stack slots, only remove this |
| 463 | // stack slot from the set of values the register contains. |
| 464 | std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); |
| 465 | for (; ; ++I) { |
| 466 | assert(I != PhysRegsAvailable.end() && I->first == Reg && |
| 467 | "Map inverse broken!"); |
| 468 | if (I->second == Slot) break; |
| 469 | } |
| 470 | PhysRegsAvailable.erase(I); |
| 471 | } |
| 472 | |
| 473 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 474 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 475 | // ReusedOp - For each reused operand, we keep track of a bit of information, in |
| 476 | // case we need to rollback upon processing a new operand. See comments below. |
| 477 | namespace { |
| 478 | struct ReusedOp { |
| 479 | // The MachineInstr operand that reused an available value. |
| 480 | unsigned Operand; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 481 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 482 | // StackSlot - The spill slot of the value being reused. |
| 483 | unsigned StackSlot; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 484 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 485 | // PhysRegReused - The physical register the value was available in. |
| 486 | unsigned PhysRegReused; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 487 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 488 | // AssignedPhysReg - The physreg that was assigned for use by the reload. |
| 489 | unsigned AssignedPhysReg; |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 490 | |
| 491 | // VirtReg - The virtual register itself. |
| 492 | unsigned VirtReg; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 493 | |
Chris Lattner | 8a61a75 | 2005-10-06 17:19:06 +0000 | [diff] [blame] | 494 | ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, |
| 495 | unsigned vreg) |
| 496 | : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr), |
| 497 | VirtReg(vreg) {} |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 498 | }; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 499 | |
| 500 | /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that |
| 501 | /// is reused instead of reloaded. |
Chris Lattner | f8c68f6 | 2006-06-28 22:17:39 +0000 | [diff] [blame] | 502 | class VISIBILITY_HIDDEN ReuseInfo { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 503 | MachineInstr &MI; |
| 504 | std::vector<ReusedOp> Reuses; |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 505 | BitVector PhysRegsClobbered; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 506 | public: |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 507 | ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 508 | PhysRegsClobbered.resize(mri->getNumRegs()); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 509 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 510 | |
| 511 | bool hasReuses() const { |
| 512 | return !Reuses.empty(); |
| 513 | } |
| 514 | |
| 515 | /// addReuse - If we choose to reuse a virtual register that is already |
| 516 | /// available instead of reloading it, remember that we did so. |
| 517 | void addReuse(unsigned OpNo, unsigned StackSlot, |
| 518 | unsigned PhysRegReused, unsigned AssignedPhysReg, |
| 519 | unsigned VirtReg) { |
| 520 | // If the reload is to the assigned register anyway, no undo will be |
| 521 | // required. |
| 522 | if (PhysRegReused == AssignedPhysReg) return; |
| 523 | |
| 524 | // Otherwise, remember this. |
| 525 | Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused, |
| 526 | AssignedPhysReg, VirtReg)); |
| 527 | } |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 528 | |
| 529 | void markClobbered(unsigned PhysReg) { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 530 | PhysRegsClobbered.set(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 531 | } |
| 532 | |
| 533 | bool isClobbered(unsigned PhysReg) const { |
Evan Cheng | 957840b | 2007-02-21 02:22:03 +0000 | [diff] [blame] | 534 | return PhysRegsClobbered.test(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 535 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 536 | |
| 537 | /// GetRegForReload - We are about to emit a reload into PhysReg. If there |
| 538 | /// is some other operand that is using the specified register, either pick |
| 539 | /// a new register to use, or evict the previous reload and use this reg. |
| 540 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 541 | AvailableSpills &Spills, |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 542 | std::map<int, MachineInstr*> &MaybeDeadStores, |
Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 543 | SmallSet<unsigned, 8> &Rejected) { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 544 | if (Reuses.empty()) return PhysReg; // This is most often empty. |
| 545 | |
| 546 | for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { |
| 547 | ReusedOp &Op = Reuses[ro]; |
| 548 | // If we find some other reuse that was supposed to use this register |
| 549 | // exactly for its reload, we can change this reload to use ITS reload |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 550 | // register. That is, unless its reload register has already been |
| 551 | // considered and subsequently rejected because it has also been reused |
| 552 | // by another operand. |
| 553 | if (Op.PhysRegReused == PhysReg && |
| 554 | Rejected.count(Op.AssignedPhysReg) == 0) { |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 555 | // Yup, use the reload register that we didn't use before. |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 556 | unsigned NewReg = Op.AssignedPhysReg; |
| 557 | Rejected.insert(PhysReg); |
| 558 | return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 559 | } else { |
| 560 | // Otherwise, we might also have a problem if a previously reused |
| 561 | // value aliases the new register. If so, codegen the previous reload |
| 562 | // and use this one. |
| 563 | unsigned PRRU = Op.PhysRegReused; |
| 564 | const MRegisterInfo *MRI = Spills.getRegInfo(); |
| 565 | if (MRI->areAliases(PRRU, PhysReg)) { |
| 566 | // Okay, we found out that an alias of a reused register |
| 567 | // was used. This isn't good because it means we have |
| 568 | // to undo a previous reuse. |
| 569 | MachineBasicBlock *MBB = MI->getParent(); |
| 570 | const TargetRegisterClass *AliasRC = |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 571 | MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); |
| 572 | |
| 573 | // Copy Op out of the vector and remove it, we're going to insert an |
| 574 | // explicit load for it. |
| 575 | ReusedOp NewOp = Op; |
| 576 | Reuses.erase(Reuses.begin()+ro); |
| 577 | |
| 578 | // Ok, we're going to try to reload the assigned physreg into the |
| 579 | // slot that we were supposed to in the first place. However, that |
| 580 | // register could hold a reuse. Check to see if it conflicts or |
| 581 | // would prefer us to use a different register. |
| 582 | unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 583 | MI, Spills, MaybeDeadStores, Rejected); |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 584 | |
| 585 | MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, |
| 586 | NewOp.StackSlot, AliasRC); |
| 587 | Spills.ClobberPhysReg(NewPhysReg); |
| 588 | Spills.ClobberPhysReg(NewOp.PhysRegReused); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 589 | |
| 590 | // Any stores to this stack slot are not dead anymore. |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 591 | MaybeDeadStores.erase(NewOp.StackSlot); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 592 | |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 593 | MI->getOperand(NewOp.Operand).setReg(NewPhysReg); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 594 | |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 595 | Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 596 | ++NumLoads; |
| 597 | DEBUG(MachineBasicBlock::iterator MII = MI; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 598 | DOUT << '\t' << *prior(MII)); |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 599 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 600 | DOUT << "Reuse undone!\n"; |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 601 | --NumReused; |
Chris Lattner | 28bad08 | 2006-02-25 02:17:31 +0000 | [diff] [blame] | 602 | |
| 603 | // Finally, PhysReg is now available, go ahead and use it. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 604 | return PhysReg; |
| 605 | } |
| 606 | } |
| 607 | } |
| 608 | return PhysReg; |
| 609 | } |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 610 | |
| 611 | /// GetRegForReload - Helper for the above GetRegForReload(). Add a |
| 612 | /// 'Rejected' set to remember which registers have been considered and |
| 613 | /// rejected for the reload. This avoids infinite looping in case like |
| 614 | /// this: |
| 615 | /// t1 := op t2, t3 |
| 616 | /// t2 <- assigned r0 for use by the reload but ended up reuse r1 |
| 617 | /// t3 <- assigned r1 for use by the reload but ended up reuse r0 |
| 618 | /// t1 <- desires r1 |
| 619 | /// sees r1 is taken by t2, tries t2's reload register r0 |
| 620 | /// sees r0 is taken by t3, tries t3's reload register r1 |
| 621 | /// sees r1 is taken by t2, tries t2's reload register r0 ... |
| 622 | unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, |
| 623 | AvailableSpills &Spills, |
| 624 | std::map<int, MachineInstr*> &MaybeDeadStores) { |
Chris Lattner | 08a4d5a | 2007-01-23 00:59:48 +0000 | [diff] [blame] | 625 | SmallSet<unsigned, 8> Rejected; |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 626 | return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected); |
| 627 | } |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 628 | }; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 629 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 630 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 631 | |
| 632 | /// rewriteMBB - Keep track of which spills are available even after the |
| 633 | /// register allocator is done with them. If possible, avoid reloading vregs. |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 634 | void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, |
| 635 | std::vector<MachineInstr*> &ReMatedMIs) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 636 | DOUT << MBB.getBasicBlock()->getName() << ":\n"; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 637 | |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 638 | // Spills - Keep track of which spilled values are available in physregs so |
| 639 | // that we can choose to reuse the physregs instead of emitting reloads. |
| 640 | AvailableSpills Spills(MRI, TII); |
| 641 | |
Chris Lattner | 52b25db | 2004-10-01 19:47:12 +0000 | [diff] [blame] | 642 | // MaybeDeadStores - When we need to write a value back into a stack slot, |
| 643 | // keep track of the inserted store. If the stack slot value is never read |
| 644 | // (because the value was used from some available register, for example), and |
| 645 | // subsequently stored to, the original store is dead. This map keeps track |
| 646 | // of inserted stores that are not used. If we see a subsequent store to the |
| 647 | // same stack slot, the original store is deleted. |
| 648 | std::map<int, MachineInstr*> MaybeDeadStores; |
| 649 | |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 650 | MachineFunction &MF = *MBB.getParent(); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 651 | for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); |
| 652 | MII != E; ) { |
| 653 | MachineInstr &MI = *MII; |
| 654 | MachineBasicBlock::iterator NextMII = MII; ++NextMII; |
| 655 | |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 656 | /// ReusedOperands - Keep track of operand reuse in case we need to undo |
| 657 | /// reuse. |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 658 | ReuseInfo ReusedOperands(MI, MRI); |
| 659 | |
| 660 | // Loop over all of the implicit defs, clearing them from our available |
| 661 | // sets. |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 662 | const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 663 | |
| 664 | // If this instruction is being rematerialized, just remove it! |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 665 | int FrameIdx; |
Dan Gohman | 82a87a0 | 2007-06-19 01:48:05 +0000 | [diff] [blame^] | 666 | if (TII->isTriviallyReMaterializable(&MI) || |
| 667 | TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 668 | bool Remove = true; |
| 669 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 670 | MachineOperand &MO = MI.getOperand(i); |
| 671 | if (!MO.isRegister() || MO.getReg() == 0) |
| 672 | continue; // Ignore non-register operands. |
| 673 | if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) { |
| 674 | Remove = false; |
| 675 | break; |
| 676 | } |
| 677 | } |
| 678 | if (Remove) { |
| 679 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 680 | ReMatedMIs.push_back(MI.removeFromParent()); |
| 681 | MII = NextMII; |
| 682 | continue; |
| 683 | } |
| 684 | } |
| 685 | |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 686 | const unsigned *ImpDef = TID->ImplicitDefs; |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 687 | if (ImpDef) { |
| 688 | for ( ; *ImpDef; ++ImpDef) { |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 689 | MF.setPhysRegUsed(*ImpDef); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 690 | ReusedOperands.markClobbered(*ImpDef); |
| 691 | Spills.ClobberPhysReg(*ImpDef); |
| 692 | } |
| 693 | } |
| 694 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 695 | // Process all of the spilled uses and all non spilled reg references. |
| 696 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 697 | MachineOperand &MO = MI.getOperand(i); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 698 | if (!MO.isRegister() || MO.getReg() == 0) |
| 699 | continue; // Ignore non-register operands. |
| 700 | |
| 701 | if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { |
| 702 | // Ignore physregs for spilling, but remember that it is used by this |
| 703 | // function. |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 704 | MF.setPhysRegUsed(MO.getReg()); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 705 | ReusedOperands.markClobbered(MO.getReg()); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 706 | continue; |
| 707 | } |
| 708 | |
| 709 | assert(MRegisterInfo::isVirtualRegister(MO.getReg()) && |
| 710 | "Not a virtual or a physical register?"); |
| 711 | |
| 712 | unsigned VirtReg = MO.getReg(); |
| 713 | if (!VRM.hasStackSlot(VirtReg)) { |
| 714 | // This virtual register was assigned a physreg! |
| 715 | unsigned Phys = VRM.getPhys(VirtReg); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 716 | MF.setPhysRegUsed(Phys); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 717 | if (MO.isDef()) |
| 718 | ReusedOperands.markClobbered(Phys); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 719 | MI.getOperand(i).setReg(Phys); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 720 | continue; |
| 721 | } |
| 722 | |
| 723 | // This virtual register is now known to be a spilled value. |
| 724 | if (!MO.isUse()) |
| 725 | continue; // Handle defs in the loop below (handle use&def here though) |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 726 | |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 727 | bool doReMat = VRM.isReMaterialized(VirtReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 728 | int StackSlot = VRM.getStackSlot(VirtReg); |
| 729 | unsigned PhysReg; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 730 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 731 | // Check to see if this stack slot is available. |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 732 | MachineInstr *SSMI = NULL; |
| 733 | if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 734 | // This spilled operand might be part of a two-address operand. If this |
| 735 | // is the case, then changing it will necessarily require changing the |
| 736 | // def part of the instruction as well. However, in some cases, we |
| 737 | // aren't allowed to modify the reused register. If none of these cases |
| 738 | // apply, reuse it. |
| 739 | bool CanReuse = true; |
Evan Cheng | 86facc2 | 2006-12-15 06:41:01 +0000 | [diff] [blame] | 740 | int ti = TID->getOperandConstraint(i, TOI::TIED_TO); |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 741 | if (ti != -1 && |
| 742 | MI.getOperand(ti).isReg() && |
| 743 | MI.getOperand(ti).getReg() == VirtReg) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 744 | // Okay, we have a two address operand. We can reuse this physreg as |
Evan Cheng | 3c82cab | 2007-01-19 22:40:14 +0000 | [diff] [blame] | 745 | // long as we are allowed to clobber the value and there isn't an |
| 746 | // earlier def that has already clobbered the physreg. |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 747 | CanReuse = Spills.canClobberPhysReg(StackSlot) && |
| 748 | !ReusedOperands.isClobbered(PhysReg); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 749 | } |
| 750 | |
| 751 | if (CanReuse) { |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 752 | // If this stack slot value is already available, reuse it! |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 753 | if (StackSlot > VirtRegMap::MAX_STACK_SLOT) |
| 754 | DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1; |
| 755 | else |
| 756 | DOUT << "Reusing SS#" << StackSlot; |
| 757 | DOUT << " from physreg " |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 758 | << MRI->getName(PhysReg) << " for vreg" |
| 759 | << VirtReg <<" instead of reloading into physreg " |
| 760 | << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 761 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 762 | |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 763 | // Extend the live range of the MI that last kill the register if |
| 764 | // necessary. |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 765 | bool WasKill = false; |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 766 | if (SSMI) { |
Evan Cheng | faa5107 | 2007-04-26 19:00:32 +0000 | [diff] [blame] | 767 | int UIdx = SSMI->findRegisterUseOperandIdx(PhysReg, true); |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 768 | if (UIdx != -1) { |
| 769 | MachineOperand &MOK = SSMI->getOperand(UIdx); |
| 770 | WasKill = MOK.isKill(); |
| 771 | MOK.unsetIsKill(); |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 772 | } |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 773 | } |
| 774 | if (ti == -1) { |
| 775 | // Unless it's the use of a two-address code, transfer the kill |
| 776 | // of the reused register to this use. |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 777 | if (WasKill) |
| 778 | MI.getOperand(i).setIsKill(); |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 779 | Spills.addLastUse(PhysReg, &MI); |
Evan Cheng | 50d25d7 | 2007-02-23 21:47:50 +0000 | [diff] [blame] | 780 | } |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 781 | |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 782 | // The only technical detail we have is that we don't know that |
| 783 | // PhysReg won't be clobbered by a reloaded stack slot that occurs |
| 784 | // later in the instruction. In particular, consider 'op V1, V2'. |
| 785 | // If V1 is available in physreg R0, we would choose to reuse it |
| 786 | // here, instead of reloading it into the register the allocator |
| 787 | // indicated (say R1). However, V2 might have to be reloaded |
| 788 | // later, and it might indicate that it needs to live in R0. When |
| 789 | // this occurs, we need to have information available that |
| 790 | // indicates it is safe to use R1 for the reload instead of R0. |
| 791 | // |
| 792 | // To further complicate matters, we might conflict with an alias, |
| 793 | // or R0 and R1 might not be compatible with each other. In this |
| 794 | // case, we actually insert a reload for V1 in R1, ensuring that |
| 795 | // we can get at R0 or its alias. |
| 796 | ReusedOperands.addReuse(i, StackSlot, PhysReg, |
| 797 | VRM.getPhys(VirtReg), VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 798 | if (ti != -1) |
| 799 | // Only mark it clobbered if this is a use&def operand. |
| 800 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 801 | ++NumReused; |
| 802 | continue; |
| 803 | } |
| 804 | |
| 805 | // Otherwise we have a situation where we have a two-address instruction |
| 806 | // whose mod/ref operand needs to be reloaded. This reload is already |
| 807 | // available in some register "PhysReg", but if we used PhysReg as the |
| 808 | // operand to our 2-addr instruction, the instruction would modify |
| 809 | // PhysReg. This isn't cool if something later uses PhysReg and expects |
| 810 | // to get its initial value. |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 811 | // |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 812 | // To avoid this problem, and to avoid doing a load right after a store, |
| 813 | // we emit a copy from PhysReg into the designated register for this |
| 814 | // operand. |
| 815 | unsigned DesignatedReg = VRM.getPhys(VirtReg); |
| 816 | assert(DesignatedReg && "Must map virtreg to physreg!"); |
| 817 | |
| 818 | // Note that, if we reused a register for a previous operand, the |
| 819 | // register we want to reload into might not actually be |
| 820 | // available. If this occurs, use the register indicated by the |
| 821 | // reuser. |
| 822 | if (ReusedOperands.hasReuses()) |
| 823 | DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, |
| 824 | Spills, MaybeDeadStores); |
| 825 | |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 826 | // If the mapped designated register is actually the physreg we have |
| 827 | // incoming, we don't need to inserted a dead copy. |
| 828 | if (DesignatedReg == PhysReg) { |
| 829 | // If this stack slot value is already available, reuse it! |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 830 | if (StackSlot > VirtRegMap::MAX_STACK_SLOT) |
| 831 | DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1; |
| 832 | else |
| 833 | DOUT << "Reusing SS#" << StackSlot; |
| 834 | DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 835 | << VirtReg |
| 836 | << " instead of reloading into same physreg.\n"; |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 837 | MI.getOperand(i).setReg(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 838 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | ba1fc3d | 2006-04-28 04:43:18 +0000 | [diff] [blame] | 839 | ++NumReused; |
| 840 | continue; |
| 841 | } |
| 842 | |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 843 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg); |
| 844 | MF.setPhysRegUsed(DesignatedReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 845 | ReusedOperands.markClobbered(DesignatedReg); |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 846 | MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 847 | |
| 848 | // Extend the live range of the MI that last kill the register if |
| 849 | // necessary. |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 850 | bool WasKill = false; |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 851 | if (SSMI) { |
Evan Cheng | faa5107 | 2007-04-26 19:00:32 +0000 | [diff] [blame] | 852 | int UIdx = SSMI->findRegisterUseOperandIdx(PhysReg, true); |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 853 | if (UIdx != -1) { |
| 854 | MachineOperand &MOK = SSMI->getOperand(UIdx); |
| 855 | WasKill = MOK.isKill(); |
| 856 | MOK.unsetIsKill(); |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 857 | } |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 858 | } |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 859 | MachineInstr *CopyMI = prior(MII); |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 860 | if (WasKill) { |
| 861 | // Transfer kill to the next use. |
Evan Cheng | faa5107 | 2007-04-26 19:00:32 +0000 | [diff] [blame] | 862 | int UIdx = CopyMI->findRegisterUseOperandIdx(PhysReg); |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 863 | assert(UIdx != -1); |
| 864 | MachineOperand &MOU = CopyMI->getOperand(UIdx); |
| 865 | MOU.setIsKill(); |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 866 | } |
| 867 | Spills.addLastUse(PhysReg, CopyMI); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 868 | |
Chris Lattner | addc55a | 2006-04-28 01:46:50 +0000 | [diff] [blame] | 869 | // This invalidates DesignatedReg. |
| 870 | Spills.ClobberPhysReg(DesignatedReg); |
| 871 | |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 872 | Spills.addAvailable(StackSlot, &MI, DesignatedReg); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 873 | MI.getOperand(i).setReg(DesignatedReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 874 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 875 | ++NumReused; |
| 876 | continue; |
| 877 | } |
| 878 | |
| 879 | // Otherwise, reload it and remember that we have it. |
| 880 | PhysReg = VRM.getPhys(VirtReg); |
Chris Lattner | 172c362 | 2006-01-04 06:47:48 +0000 | [diff] [blame] | 881 | assert(PhysReg && "Must map virtreg to physreg!"); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 882 | const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 883 | |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 884 | // Note that, if we reused a register for a previous operand, the |
| 885 | // register we want to reload into might not actually be |
| 886 | // available. If this occurs, use the register indicated by the |
| 887 | // reuser. |
Chris Lattner | 540fec6 | 2006-02-25 01:51:33 +0000 | [diff] [blame] | 888 | if (ReusedOperands.hasReuses()) |
| 889 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
| 890 | Spills, MaybeDeadStores); |
| 891 | |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 892 | MF.setPhysRegUsed(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 893 | ReusedOperands.markClobbered(PhysReg); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 894 | if (doReMat) { |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 895 | MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 896 | ++NumReMats; |
| 897 | } else { |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 898 | MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); |
Evan Cheng | 9193514 | 2007-04-04 07:40:01 +0000 | [diff] [blame] | 899 | ++NumLoads; |
| 900 | } |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 901 | // This invalidates PhysReg. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 902 | Spills.ClobberPhysReg(PhysReg); |
Chris Lattner | 50ea01e | 2005-09-09 20:29:51 +0000 | [diff] [blame] | 903 | |
| 904 | // Any stores to this stack slot are not dead anymore. |
Evan Cheng | 2638e1a | 2007-03-20 08:13:50 +0000 | [diff] [blame] | 905 | if (!doReMat) |
| 906 | MaybeDeadStores.erase(StackSlot); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 907 | Spills.addAvailable(StackSlot, &MI, PhysReg); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 908 | // Assumes this is the last use. IsKill will be unset if reg is reused |
| 909 | // unless it's a two-address operand. |
| 910 | if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) |
| 911 | MI.getOperand(i).setIsKill(); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 912 | MI.getOperand(i).setReg(PhysReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 913 | DOUT << '\t' << *prior(MII); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 914 | } |
| 915 | |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 916 | DOUT << '\t' << MI; |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 917 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 918 | // If we have folded references to memory operands, make sure we clear all |
| 919 | // physical registers that may contain the value of the spilled virtual |
| 920 | // register |
Chris Lattner | 8f1d640 | 2005-01-14 15:54:24 +0000 | [diff] [blame] | 921 | VirtRegMap::MI2VirtMapTy::const_iterator I, End; |
| 922 | for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 923 | DOUT << "Folded vreg: " << I->second.first << " MR: " |
| 924 | << I->second.second; |
Chris Lattner | bec6a9e | 2004-10-01 23:15:36 +0000 | [diff] [blame] | 925 | unsigned VirtReg = I->second.first; |
| 926 | VirtRegMap::ModRef MR = I->second.second; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 927 | if (!VRM.hasStackSlot(VirtReg)) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 928 | DOUT << ": No stack slot!\n"; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 929 | continue; |
| 930 | } |
| 931 | int SS = VRM.getStackSlot(VirtReg); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 932 | DOUT << " - StackSlot: " << SS << "\n"; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 933 | |
| 934 | // If this folded instruction is just a use, check to see if it's a |
| 935 | // straight load from the virt reg slot. |
| 936 | if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { |
| 937 | int FrameIdx; |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 938 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 939 | if (FrameIdx == SS) { |
| 940 | // If this spill slot is available, turn it into a copy (or nothing) |
| 941 | // instead of leaving it as a load! |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 942 | MachineInstr *SSMI = NULL; |
| 943 | if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 944 | DOUT << "Promoted Load To Copy: " << MI; |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 945 | if (DestReg != InReg) { |
| 946 | MRI->copyRegToReg(MBB, &MI, DestReg, InReg, |
| 947 | MF.getSSARegMap()->getRegClass(VirtReg)); |
| 948 | // Revisit the copy so we make sure to notice the effects of the |
| 949 | // operation on the destreg (either needing to RA it if it's |
| 950 | // virtual or needing to clobber any values if it's physical). |
| 951 | NextMII = &MI; |
| 952 | --NextMII; // backtrack to the copy. |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 953 | } else |
| 954 | DOUT << "Removing now-noop copy: " << MI; |
| 955 | |
Evan Cheng | c0ba1bc | 2007-03-01 02:27:30 +0000 | [diff] [blame] | 956 | // Either way, the live range of the last kill of InReg has been |
| 957 | // extended. Remove its kill. |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 958 | bool WasKill = false; |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 959 | if (SSMI) { |
Evan Cheng | faa5107 | 2007-04-26 19:00:32 +0000 | [diff] [blame] | 960 | int UIdx = SSMI->findRegisterUseOperandIdx(InReg, true); |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 961 | if (UIdx != -1) { |
| 962 | MachineOperand &MOK = SSMI->getOperand(UIdx); |
| 963 | WasKill = MOK.isKill(); |
| 964 | MOK.unsetIsKill(); |
Evan Cheng | a7288df | 2007-03-03 06:32:37 +0000 | [diff] [blame] | 965 | } |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 966 | } |
| 967 | if (NextMII != MBB.end()) { |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 968 | // If NextMII uses InReg and the use is not a two address |
| 969 | // operand, mark it killed. |
Evan Cheng | faa5107 | 2007-04-26 19:00:32 +0000 | [diff] [blame] | 970 | int UIdx = NextMII->findRegisterUseOperandIdx(InReg); |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 971 | if (UIdx != -1) { |
| 972 | MachineOperand &MOU = NextMII->getOperand(UIdx); |
| 973 | if (WasKill) { |
| 974 | const TargetInstrDescriptor *NTID = |
| 975 | NextMII->getInstrDescriptor(); |
Evan Cheng | 018d6e1 | 2007-03-27 00:48:28 +0000 | [diff] [blame] | 976 | if (UIdx >= NTID->numOperands || |
| 977 | NTID->getOperandConstraint(UIdx, TOI::TIED_TO) == -1) |
Evan Cheng | ad7ccf3 | 2007-03-26 22:40:42 +0000 | [diff] [blame] | 978 | MOU.setIsKill(); |
| 979 | } |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 980 | Spills.addLastUse(InReg, &(*NextMII)); |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 981 | } |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 982 | } |
Evan Cheng | de4e942 | 2007-02-25 09:51:27 +0000 | [diff] [blame] | 983 | |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 984 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 985 | MBB.erase(&MI); |
| 986 | goto ProcessNextInst; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 987 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 988 | } |
| 989 | } |
| 990 | } |
| 991 | |
| 992 | // If this reference is not a use, any previous store is now dead. |
| 993 | // Otherwise, the store to this stack slot is not dead anymore. |
| 994 | std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); |
| 995 | if (MDSI != MaybeDeadStores.end()) { |
| 996 | if (MR & VirtRegMap::isRef) // Previous store is not dead. |
| 997 | MaybeDeadStores.erase(MDSI); |
| 998 | else { |
| 999 | // If we get here, the store is dead, nuke it now. |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 1000 | assert(VirtRegMap::isMod && "Can't be modref!"); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1001 | DOUT << "Removed dead store:\t" << *MDSI->second; |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 1002 | MBB.erase(MDSI->second); |
Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 1003 | VRM.RemoveFromFoldedVirtMap(MDSI->second); |
Chris Lattner | 35f2705 | 2006-05-01 21:16:03 +0000 | [diff] [blame] | 1004 | MaybeDeadStores.erase(MDSI); |
| 1005 | ++NumDSE; |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1006 | } |
| 1007 | } |
| 1008 | |
| 1009 | // If the spill slot value is available, and this is a new definition of |
| 1010 | // the value, the value is not available anymore. |
| 1011 | if (MR & VirtRegMap::isMod) { |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1012 | // Notice that the value in this stack slot has been modified. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1013 | Spills.ModifyStackSlot(SS); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1014 | |
| 1015 | // If this is *just* a mod of the value, check to see if this is just a |
| 1016 | // store to the spill slot (i.e. the spill got merged into the copy). If |
| 1017 | // so, realize that the vreg is available now, and add the store to the |
| 1018 | // MaybeDeadStore info. |
| 1019 | int StackSlot; |
| 1020 | if (!(MR & VirtRegMap::isRef)) { |
| 1021 | if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { |
| 1022 | assert(MRegisterInfo::isPhysicalRegister(SrcReg) && |
| 1023 | "Src hasn't been allocated yet?"); |
Chris Lattner | 07cf141 | 2006-02-03 00:36:31 +0000 | [diff] [blame] | 1024 | // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1025 | // this as a potentially dead store in case there is a subsequent |
| 1026 | // store into the stack slot without a read from it. |
| 1027 | MaybeDeadStores[StackSlot] = &MI; |
| 1028 | |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1029 | // If the stack slot value was previously available in some other |
| 1030 | // register, change it now. Otherwise, make the register available, |
| 1031 | // in PhysReg. |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1032 | Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); |
Chris Lattner | cd81639 | 2006-02-02 23:29:36 +0000 | [diff] [blame] | 1033 | } |
| 1034 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1035 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1036 | } |
| 1037 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1038 | // Process all of the spilled defs. |
| 1039 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { |
| 1040 | MachineOperand &MO = MI.getOperand(i); |
| 1041 | if (MO.isRegister() && MO.getReg() && MO.isDef()) { |
| 1042 | unsigned VirtReg = MO.getReg(); |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1043 | |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1044 | if (!MRegisterInfo::isVirtualRegister(VirtReg)) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1045 | // Check to see if this is a noop copy. If so, eliminate the |
| 1046 | // instruction before considering the dest reg to be changed. |
| 1047 | unsigned Src, Dst; |
| 1048 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1049 | ++NumDCE; |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1050 | DOUT << "Removing now-noop copy: " << MI; |
Evan Cheng | 6b44809 | 2007-03-02 08:52:00 +0000 | [diff] [blame] | 1051 | Spills.removeLastUse(Src, &MI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1052 | MBB.erase(&MI); |
| 1053 | VRM.RemoveFromFoldedVirtMap(&MI); |
Evan Cheng | 7a0d51c | 2006-12-14 07:54:05 +0000 | [diff] [blame] | 1054 | Spills.disallowClobberPhysReg(VirtReg); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1055 | goto ProcessNextInst; |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1056 | } |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1057 | |
| 1058 | // If it's not a no-op copy, it clobbers the value in the destreg. |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1059 | Spills.ClobberPhysReg(VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1060 | ReusedOperands.markClobbered(VirtReg); |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1061 | |
| 1062 | // Check to see if this instruction is a load from a stack slot into |
| 1063 | // a register. If so, this provides the stack slot value in the reg. |
| 1064 | int FrameIdx; |
| 1065 | if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { |
| 1066 | assert(DestReg == VirtReg && "Unknown load situation!"); |
| 1067 | |
| 1068 | // Otherwise, if it wasn't available, remember that it is now! |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1069 | Spills.addAvailable(FrameIdx, &MI, DestReg); |
Chris Lattner | 6ec3626 | 2006-10-12 17:45:38 +0000 | [diff] [blame] | 1070 | goto ProcessNextInst; |
| 1071 | } |
| 1072 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1073 | continue; |
Misha Brukman | edf128a | 2005-04-21 22:36:52 +0000 | [diff] [blame] | 1074 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1075 | |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1076 | // The only vregs left are stack slot definitions. |
| 1077 | int StackSlot = VRM.getStackSlot(VirtReg); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1078 | const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1079 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1080 | // If this def is part of a two-address operand, make sure to execute |
| 1081 | // the store from the correct physical register. |
| 1082 | unsigned PhysReg; |
Evan Cheng | cc22a7a | 2006-12-08 18:45:48 +0000 | [diff] [blame] | 1083 | int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); |
Evan Cheng | 360c2dd | 2006-11-01 23:06:55 +0000 | [diff] [blame] | 1084 | if (TiedOp != -1) |
| 1085 | PhysReg = MI.getOperand(TiedOp).getReg(); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1086 | else { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1087 | PhysReg = VRM.getPhys(VirtReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1088 | if (ReusedOperands.isClobbered(PhysReg)) { |
| 1089 | // Another def has taken the assigned physreg. It must have been a |
| 1090 | // use&def which got it due to reuse. Undo the reuse! |
| 1091 | PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, |
| 1092 | Spills, MaybeDeadStores); |
| 1093 | } |
| 1094 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1095 | |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1096 | MF.setPhysRegUsed(PhysReg); |
Evan Cheng | e077ef6 | 2006-11-04 00:21:55 +0000 | [diff] [blame] | 1097 | ReusedOperands.markClobbered(PhysReg); |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1098 | MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1099 | DOUT << "Store:\t" << *next(MII); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 1100 | MI.getOperand(i).setReg(PhysReg); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1101 | |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1102 | // If there is a dead store to this stack slot, nuke it now. |
| 1103 | MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; |
| 1104 | if (LastStore) { |
Bill Wendling | b2b9c20 | 2006-11-17 02:09:07 +0000 | [diff] [blame] | 1105 | DOUT << "Removed dead store:\t" << *LastStore; |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1106 | ++NumDSE; |
| 1107 | MBB.erase(LastStore); |
Chris Lattner | 229924a | 2006-05-01 22:03:24 +0000 | [diff] [blame] | 1108 | VRM.RemoveFromFoldedVirtMap(LastStore); |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1109 | } |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1110 | LastStore = next(MII); |
| 1111 | |
| 1112 | // If the stack slot value was previously available in some other |
| 1113 | // register, change it now. Otherwise, make the register available, |
| 1114 | // in PhysReg. |
Chris Lattner | 66cf80f | 2006-02-03 23:13:58 +0000 | [diff] [blame] | 1115 | Spills.ModifyStackSlot(StackSlot); |
| 1116 | Spills.ClobberPhysReg(PhysReg); |
Evan Cheng | 91e2390 | 2007-02-23 01:13:26 +0000 | [diff] [blame] | 1117 | Spills.addAvailable(StackSlot, LastStore, PhysReg); |
Chris Lattner | 84e752a | 2006-02-03 03:06:49 +0000 | [diff] [blame] | 1118 | ++NumStores; |
Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1119 | |
| 1120 | // Check to see if this is a noop copy. If so, eliminate the |
| 1121 | // instruction before considering the dest reg to be changed. |
| 1122 | { |
| 1123 | unsigned Src, Dst; |
| 1124 | if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { |
| 1125 | ++NumDCE; |
| 1126 | DOUT << "Removing now-noop copy: " << MI; |
Evan Cheng | 7cb33c8 | 2007-03-30 20:21:35 +0000 | [diff] [blame] | 1127 | Spills.removeLastUse(Src, &MI); |
Evan Cheng | f50d09a | 2007-02-08 06:04:54 +0000 | [diff] [blame] | 1128 | MBB.erase(&MI); |
| 1129 | VRM.RemoveFromFoldedVirtMap(&MI); |
| 1130 | goto ProcessNextInst; |
| 1131 | } |
| 1132 | } |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1133 | } |
| 1134 | } |
Chris Lattner | cea8688 | 2005-09-19 06:56:21 +0000 | [diff] [blame] | 1135 | ProcessNextInst: |
Chris Lattner | 7fb6434 | 2004-10-01 19:04:51 +0000 | [diff] [blame] | 1136 | MII = NextMII; |
| 1137 | } |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1138 | } |
| 1139 | |
Chris Lattner | f7da2c7 | 2006-08-24 22:43:55 +0000 | [diff] [blame] | 1140 | |
| 1141 | |
Chris Lattner | 8c4d88d | 2004-09-30 01:54:45 +0000 | [diff] [blame] | 1142 | llvm::Spiller* llvm::createSpiller() { |
| 1143 | switch (SpillerOpt) { |
| 1144 | default: assert(0 && "Unreachable!"); |
| 1145 | case local: |
| 1146 | return new LocalSpiller(); |
| 1147 | case simple: |
| 1148 | return new SimpleSpiller(); |
| 1149 | } |
Alkis Evlogimenos | 0d6c5b6 | 2004-02-24 08:58:30 +0000 | [diff] [blame] | 1150 | } |