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gerrit-public.fairphone.software / kernel / msm-4.19 / a2abf904a6b594b93c0e73a36c98ecbaa7388463 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 0467846b4cc33cd0e5bf22c1973407fdc38248a9 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]106 wkup_m3: wkup_m3@100000 {
107 compatible = "ti,am3352-wkup-m3";
108 reg = <0x100000 0x4000>,
109 <0x180000 0x2000>;
110 reg-names = "umem", "dmem";
111 ti,hwmods = "wkup_m3";
112 ti,pm-firmware = "am335x-pm-firmware.elf";
113 };
114
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]115 prcm: prcm@200000 {
116 compatible = "ti,am3-prcm";
117 reg = <0x200000 0x4000>;
118
119 prcm_clocks: clocks {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123
124 prcm_clockdomains: clockdomains {
125 };
126 };
127
128 scm: scm@210000 {
129 compatible = "ti,am3-scm", "simple-bus";
130 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]131 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]132 #size-cells = <1>;
133 ranges = <0 0x210000 0x2000>;
134
135 am33xx_pinmux: pinmux@800 {
136 compatible = "pinctrl-single";
137 reg = <0x800 0x238>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 pinctrl-single,register-width = <32>;
141 pinctrl-single,function-mask = <0x7f>;
142 };
143
144 scm_conf: scm_conf@0 {
145 compatible = "syscon";
146 reg = <0x0 0x800>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149
150 scm_clocks: clocks {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154 };
155
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]156 wkup_m3_ipc: wkup_m3_ipc@1324 {
157 compatible = "ti,am3352-wkup-m3-ipc";
158 reg = <0x1324 0x24>;
159 interrupts = <78>;
160 ti,rproc = <&wkup_m3>;
161 mboxes = <&mailbox &mbox_wkupm3>;
162 };
163
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]164 edma_xbar: dma-router@f90 {
165 compatible = "ti,am335x-edma-crossbar";
166 reg = <0xf90 0x40>;
167 #dma-cells = <3>;
168 dma-requests = <32>;
169 dma-masters = <&edma>;
170 };
171
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]172 scm_clockdomains: clockdomains {
173 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]174 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]175 };
176
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]178 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]179 interrupt-controller;
180 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 reg = <0x48200000 0x1000>;
182 };
183
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]184 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]185 compatible = "ti,edma3-tpcc";
186 ti,hwmods = "tpcc";
187 reg = <0x49000000 0x10000>;
188 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]189 interrupts = <12 13 14>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]190 interrupt-names = "edma3_ccint", "emda3_mperr",
191 "edma3_ccerrint";
192 dma-requests = <64>;
193 #dma-cells = <2>;
194
195 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
196 <&edma_tptc2 0>;
197
198 ti,edma-memcpy-channels = <20 21>;
199 };
200
201 edma_tptc0: tptc@49800000 {
202 compatible = "ti,edma3-tptc";
203 ti,hwmods = "tptc0";
204 reg = <0x49800000 0x100000>;
205 interrupts = <112>;
206 interrupt-names = "edma3_tcerrint";
207 };
208
209 edma_tptc1: tptc@49900000 {
210 compatible = "ti,edma3-tptc";
211 ti,hwmods = "tptc1";
212 reg = <0x49900000 0x100000>;
213 interrupts = <113>;
214 interrupt-names = "edma3_tcerrint";
215 };
216
217 edma_tptc2: tptc@49a00000 {
218 compatible = "ti,edma3-tptc";
219 ti,hwmods = "tptc2";
220 reg = <0x49a00000 0x100000>;
221 interrupts = <114>;
222 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]223 };
224
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]225 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]226 compatible = "ti,omap4-gpio";
227 ti,hwmods = "gpio1";
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]231 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]232 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]233 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]234 };
235
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]236 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]237 compatible = "ti,omap4-gpio";
238 ti,hwmods = "gpio2";
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]242 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]243 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]244 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]245 };
246
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]247 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 compatible = "ti,omap4-gpio";
249 ti,hwmods = "gpio3";
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]253 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]254 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]255 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]256 };
257
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]258 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]259 compatible = "ti,omap4-gpio";
260 ti,hwmods = "gpio4";
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]264 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]265 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]266 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]267 };
268
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]269 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]270 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]271 ti,hwmods = "uart1";
272 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]273 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]274 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]275 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]276 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]277 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]278 };
279
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]280 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]281 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]282 ti,hwmods = "uart2";
283 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]284 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]285 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]286 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]287 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]288 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]289 };
290
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]291 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]292 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]293 ti,hwmods = "uart3";
294 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]295 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]296 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]297 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]298 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]299 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]300 };
301
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]302 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]303 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]304 ti,hwmods = "uart4";
305 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]306 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]307 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]308 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]309 };
310
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]311 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]312 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]313 ti,hwmods = "uart5";
314 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]315 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]316 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]317 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]318 };
319
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]320 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]321 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]322 ti,hwmods = "uart6";
323 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]324 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]325 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]326 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]327 };
328
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]329 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]330 compatible = "ti,omap4-i2c";
331 #address-cells = <1>;
332 #size-cells = <0>;
333 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]334 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]335 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]336 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]337 };
338
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]339 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]340 compatible = "ti,omap4-i2c";
341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]344 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]345 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]346 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]347 };
348
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]349 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]350 compatible = "ti,omap4-i2c";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]354 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]355 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]356 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]357 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]358
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]359 mmc1: mmc@48060000 {
360 compatible = "ti,omap4-hsmmc";
361 ti,hwmods = "mmc1";
362 ti,dual-volt;
363 ti,needs-special-reset;
364 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]365 dmas = <&edma_xbar 24 0 0
366 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]367 dma-names = "tx", "rx";
368 interrupts = <64>;
369 interrupt-parent = <&intc>;
370 reg = <0x48060000 0x1000>;
371 status = "disabled";
372 };
373
374 mmc2: mmc@481d8000 {
375 compatible = "ti,omap4-hsmmc";
376 ti,hwmods = "mmc2";
377 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]378 dmas = <&edma 2 0
379 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]380 dma-names = "tx", "rx";
381 interrupts = <28>;
382 interrupt-parent = <&intc>;
383 reg = <0x481d8000 0x1000>;
384 status = "disabled";
385 };
386
387 mmc3: mmc@47810000 {
388 compatible = "ti,omap4-hsmmc";
389 ti,hwmods = "mmc3";
390 ti,needs-special-reset;
391 interrupts = <29>;
392 interrupt-parent = <&intc>;
393 reg = <0x47810000 0x1000>;
394 status = "disabled";
395 };
396
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]397 hwspinlock: spinlock@480ca000 {
398 compatible = "ti,omap4-hwspinlock";
399 reg = <0x480ca000 0x1000>;
400 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]401 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]402 };
403
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]404 wdt2: wdt@44e35000 {
405 compatible = "ti,omap3-wdt";
406 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]407 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]408 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]409 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]410
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]411 dcan0: can@481cc000 {
412 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]413 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]414 reg = <0x481cc000 0x2000>;
415 clocks = <&dcan0_fck>;
416 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]417 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]418 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]419 status = "disabled";
420 };
421
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]422 dcan1: can@481d0000 {
423 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]424 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]425 reg = <0x481d0000 0x2000>;
426 clocks = <&dcan1_fck>;
427 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]428 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]429 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]430 status = "disabled";
431 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]432
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]433 mailbox: mailbox@480C8000 {
434 compatible = "ti,omap4-mailbox";
435 reg = <0x480C8000 0x200>;
436 interrupts = <77>;
437 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]438 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]439 ti,mbox-num-users = <4>;
440 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]441 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]442 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]443 ti,mbox-tx = <0 0 0>;
444 ti,mbox-rx = <0 0 3>;
445 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]446 };
447
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]448 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]449 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]450 reg = <0x44e31000 0x400>;
451 interrupts = <67>;
452 ti,hwmods = "timer1";
453 ti,timer-alwon;
454 };
455
456 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]457 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]458 reg = <0x48040000 0x400>;
459 interrupts = <68>;
460 ti,hwmods = "timer2";
461 };
462
463 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]464 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]465 reg = <0x48042000 0x400>;
466 interrupts = <69>;
467 ti,hwmods = "timer3";
468 };
469
470 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]471 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]472 reg = <0x48044000 0x400>;
473 interrupts = <92>;
474 ti,hwmods = "timer4";
475 ti,timer-pwm;
476 };
477
478 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]479 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]480 reg = <0x48046000 0x400>;
481 interrupts = <93>;
482 ti,hwmods = "timer5";
483 ti,timer-pwm;
484 };
485
486 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]487 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]488 reg = <0x48048000 0x400>;
489 interrupts = <94>;
490 ti,hwmods = "timer6";
491 ti,timer-pwm;
492 };
493
494 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]495 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]496 reg = <0x4804a000 0x400>;
497 interrupts = <95>;
498 ti,hwmods = "timer7";
499 ti,timer-pwm;
500 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]501
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]502 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]503 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]504 reg = <0x44e3e000 0x1000>;
505 interrupts = <75
506 76>;
507 ti,hwmods = "rtc";
508 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]509
510 spi0: spi@48030000 {
511 compatible = "ti,omap4-mcspi";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]515 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]516 ti,spi-num-cs = <2>;
517 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]518 dmas = <&edma 16 0
519 &edma 17 0
520 &edma 18 0
521 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]522 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]523 status = "disabled";
524 };
525
526 spi1: spi@481a0000 {
527 compatible = "ti,omap4-mcspi";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]531 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]532 ti,spi-num-cs = <2>;
533 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]534 dmas = <&edma 42 0
535 &edma 43 0
536 &edma 44 0
537 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]538 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]539 status = "disabled";
540 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]541
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]542 usb: usb@47400000 {
543 compatible = "ti,am33xx-usb";
544 reg = <0x47400000 0x1000>;
545 ranges;
546 #address-cells = <1>;
547 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]548 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]549 status = "disabled";
550
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]551 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]552 compatible = "ti,am335x-usb-ctrl-module";
553 reg = <0x44e10620 0x10
554 0x44e10648 0x4>;
555 reg-names = "phy_ctrl", "wakeup";
556 status = "disabled";
557 };
558
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]559 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]560 compatible = "ti,am335x-usb-phy";
561 reg = <0x47401300 0x100>;
562 reg-names = "phy";
563 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]564 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]565 };
566
567 usb0: usb@47401000 {
568 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]569 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]570 reg = <0x47401400 0x400
571 0x47401000 0x200>;
572 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]573
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]574 interrupts = <18>;
575 interrupt-names = "mc";
576 dr_mode = "otg";
577 mentor,multipoint = <1>;
578 mentor,num-eps = <16>;
579 mentor,ram-bits = <12>;
580 mentor,power = <500>;
581 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]582
583 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
584 &cppi41dma 2 0 &cppi41dma 3 0
585 &cppi41dma 4 0 &cppi41dma 5 0
586 &cppi41dma 6 0 &cppi41dma 7 0
587 &cppi41dma 8 0 &cppi41dma 9 0
588 &cppi41dma 10 0 &cppi41dma 11 0
589 &cppi41dma 12 0 &cppi41dma 13 0
590 &cppi41dma 14 0 &cppi41dma 0 1
591 &cppi41dma 1 1 &cppi41dma 2 1
592 &cppi41dma 3 1 &cppi41dma 4 1
593 &cppi41dma 5 1 &cppi41dma 6 1
594 &cppi41dma 7 1 &cppi41dma 8 1
595 &cppi41dma 9 1 &cppi41dma 10 1
596 &cppi41dma 11 1 &cppi41dma 12 1
597 &cppi41dma 13 1 &cppi41dma 14 1>;
598 dma-names =
599 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
600 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
601 "rx14", "rx15",
602 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
603 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
604 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]605 };
606
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]607 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]608 compatible = "ti,am335x-usb-phy";
609 reg = <0x47401b00 0x100>;
610 reg-names = "phy";
611 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]612 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]613 };
614
615 usb1: usb@47401800 {
616 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]617 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]618 reg = <0x47401c00 0x400
619 0x47401800 0x200>;
620 reg-names = "mc", "control";
621 interrupts = <19>;
622 interrupt-names = "mc";
623 dr_mode = "otg";
624 mentor,multipoint = <1>;
625 mentor,num-eps = <16>;
626 mentor,ram-bits = <12>;
627 mentor,power = <500>;
628 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]629
630 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
631 &cppi41dma 17 0 &cppi41dma 18 0
632 &cppi41dma 19 0 &cppi41dma 20 0
633 &cppi41dma 21 0 &cppi41dma 22 0
634 &cppi41dma 23 0 &cppi41dma 24 0
635 &cppi41dma 25 0 &cppi41dma 26 0
636 &cppi41dma 27 0 &cppi41dma 28 0
637 &cppi41dma 29 0 &cppi41dma 15 1
638 &cppi41dma 16 1 &cppi41dma 17 1
639 &cppi41dma 18 1 &cppi41dma 19 1
640 &cppi41dma 20 1 &cppi41dma 21 1
641 &cppi41dma 22 1 &cppi41dma 23 1
642 &cppi41dma 24 1 &cppi41dma 25 1
643 &cppi41dma 26 1 &cppi41dma 27 1
644 &cppi41dma 28 1 &cppi41dma 29 1>;
645 dma-names =
646 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
647 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
648 "rx14", "rx15",
649 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
650 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
651 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]652 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]653
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]654 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]655 compatible = "ti,am3359-cppi41";
656 reg = <0x47400000 0x1000
657 0x47402000 0x1000
658 0x47403000 0x1000
659 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]660 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]661 interrupts = <17>;
662 interrupt-names = "glue";
663 #dma-cells = <2>;
664 #dma-channels = <30>;
665 #dma-requests = <256>;
666 status = "disabled";
667 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]668 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]669
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]670 epwmss0: epwmss@48300000 {
671 compatible = "ti,am33xx-pwmss";
672 reg = <0x48300000 0x10>;
673 ti,hwmods = "epwmss0";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 status = "disabled";
677 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
678 0x48300180 0x48300180 0x80 /* EQEP */
679 0x48300200 0x48300200 0x80>; /* EHRPWM */
680
681 ecap0: ecap@48300100 {
682 compatible = "ti,am33xx-ecap";
683 #pwm-cells = <3>;
684 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]685 interrupts = <31>;
686 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]687 ti,hwmods = "ecap0";
688 status = "disabled";
689 };
690
691 ehrpwm0: ehrpwm@48300200 {
692 compatible = "ti,am33xx-ehrpwm";
693 #pwm-cells = <3>;
694 reg = <0x48300200 0x80>;
695 ti,hwmods = "ehrpwm0";
696 status = "disabled";
697 };
698 };
699
700 epwmss1: epwmss@48302000 {
701 compatible = "ti,am33xx-pwmss";
702 reg = <0x48302000 0x10>;
703 ti,hwmods = "epwmss1";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 status = "disabled";
707 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
708 0x48302180 0x48302180 0x80 /* EQEP */
709 0x48302200 0x48302200 0x80>; /* EHRPWM */
710
711 ecap1: ecap@48302100 {
712 compatible = "ti,am33xx-ecap";
713 #pwm-cells = <3>;
714 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]715 interrupts = <47>;
716 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]717 ti,hwmods = "ecap1";
718 status = "disabled";
719 };
720
721 ehrpwm1: ehrpwm@48302200 {
722 compatible = "ti,am33xx-ehrpwm";
723 #pwm-cells = <3>;
724 reg = <0x48302200 0x80>;
725 ti,hwmods = "ehrpwm1";
726 status = "disabled";
727 };
728 };
729
730 epwmss2: epwmss@48304000 {
731 compatible = "ti,am33xx-pwmss";
732 reg = <0x48304000 0x10>;
733 ti,hwmods = "epwmss2";
734 #address-cells = <1>;
735 #size-cells = <1>;
736 status = "disabled";
737 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
738 0x48304180 0x48304180 0x80 /* EQEP */
739 0x48304200 0x48304200 0x80>; /* EHRPWM */
740
741 ecap2: ecap@48304100 {
742 compatible = "ti,am33xx-ecap";
743 #pwm-cells = <3>;
744 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]745 interrupts = <61>;
746 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]747 ti,hwmods = "ecap2";
748 status = "disabled";
749 };
750
751 ehrpwm2: ehrpwm@48304200 {
752 compatible = "ti,am33xx-ehrpwm";
753 #pwm-cells = <3>;
754 reg = <0x48304200 0x80>;
755 ti,hwmods = "ehrpwm2";
756 status = "disabled";
757 };
758 };
759
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]760 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]761 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]762 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]763 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
764 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]765 cpdma_channels = <8>;
766 ale_entries = <1024>;
767 bd_ram_size = <0x2000>;
768 no_bd_ram = <0>;
769 rx_descs = <64>;
770 mac_control = <0x20>;
771 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]772 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]773 cpts_clock_mult = <0x80000000>;
774 cpts_clock_shift = <29>;
775 reg = <0x4a100000 0x800
776 0x4a101200 0x100>;
777 #address-cells = <1>;
778 #size-cells = <1>;
779 interrupt-parent = <&intc>;
780 /*
781 * c0_rx_thresh_pend
782 * c0_rx_pend
783 * c0_tx_pend
784 * c0_misc_pend
785 */
786 interrupts = <40 41 42 43>;
787 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]788 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]789 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]790
791 davinci_mdio: mdio@4a101000 {
792 compatible = "ti,davinci_mdio";
793 #address-cells = <1>;
794 #size-cells = <0>;
795 ti,hwmods = "davinci_mdio";
796 bus_freq = <1000000>;
797 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]798 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]799 };
800
801 cpsw_emac0: slave@4a100200 {
802 /* Filled in by U-Boot */
803 mac-address = [ 00 00 00 00 00 00 ];
804 };
805
806 cpsw_emac1: slave@4a100300 {
807 /* Filled in by U-Boot */
808 mac-address = [ 00 00 00 00 00 00 ];
809 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]810
811 phy_sel: cpsw-phy-sel@44e10650 {
812 compatible = "ti,am3352-cpsw-phy-sel";
813 reg= <0x44e10650 0x4>;
814 reg-names = "gmii-sel";
815 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]816 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]817
818 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]819 compatible = "mmio-sram";
820 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]821 };
822
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]823 elm: elm@48080000 {
824 compatible = "ti,am3352-elm";
825 reg = <0x48080000 0x2000>;
826 interrupts = <4>;
827 ti,hwmods = "elm";
828 status = "disabled";
829 };
830
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]831 lcdc: lcdc@4830e000 {
832 compatible = "ti,am33xx-tilcdc";
833 reg = <0x4830e000 0x1000>;
834 interrupt-parent = <&intc>;
835 interrupts = <36>;
836 ti,hwmods = "lcdc";
837 status = "disabled";
838 };
839
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]840 tscadc: tscadc@44e0d000 {
841 compatible = "ti,am3359-tscadc";
842 reg = <0x44e0d000 0x1000>;
843 interrupt-parent = <&intc>;
844 interrupts = <16>;
845 ti,hwmods = "adc_tsc";
846 status = "disabled";
847
848 tsc {
849 compatible = "ti,am3359-tsc";
850 };
851 am335x_adc: adc {
852 #io-channel-cells = <1>;
853 compatible = "ti,am3359-adc";
854 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]855 };
856
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]857 gpmc: gpmc@50000000 {
858 compatible = "ti,am3352-gpmc";
859 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]860 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]861 reg = <0x50000000 0x2000>;
862 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame^]863 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]864 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]865 gpmc,num-cs = <7>;
866 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]867 #address-cells = <2>;
868 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]869 interrupt-controller;
870 #interrupt-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]871 status = "disabled";
872 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]873
874 sham: sham@53100000 {
875 compatible = "ti,omap4-sham";
876 ti,hwmods = "sham";
877 reg = <0x53100000 0x200>;
878 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]879 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]880 dma-names = "rx";
881 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]882
883 aes: aes@53500000 {
884 compatible = "ti,omap4-aes";
885 ti,hwmods = "aes";
886 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]887 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]888 dmas = <&edma 6 0>,
889 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]890 dma-names = "tx", "rx";
891 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]892
893 mcasp0: mcasp@48038000 {
894 compatible = "ti,am33xx-mcasp-audio";
895 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]896 reg = <0x48038000 0x2000>,
897 <0x46000000 0x400000>;
898 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]899 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]900 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]901 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]902 dmas = <&edma 8 2>,
903 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]904 dma-names = "tx", "rx";
905 };
906
907 mcasp1: mcasp@4803C000 {
908 compatible = "ti,am33xx-mcasp-audio";
909 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]910 reg = <0x4803C000 0x2000>,
911 <0x46400000 0x400000>;
912 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]913 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]914 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]915 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]916 dmas = <&edma 10 2>,
917 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]918 dma-names = "tx", "rx";
919 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]920
921 rng: rng@48310000 {
922 compatible = "ti,omap4-rng";
923 ti,hwmods = "rng";
924 reg = <0x48310000 0x2000>;
925 interrupts = <111>;
926 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]927 };
928};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]929
930/include/ "am33xx-clocks.dtsi"