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gerrit-public.fairphone.software / kernel / msm-4.9 / 0011ca13b6c1cf8c86398d95e18fd0df42ca2bf3 / . / arch / arm64 / boot / dts / qcom / sdm670.dtsi
blob: 50ea44a8b558bb55e48d85f29c100142e6da42ac [file] [log] [blame]
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]1/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "skeleton64.dtsi"
14#include <dt-bindings/interrupt-controller/arm-gic.h>
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]15#include <dt-bindings/clock/qcom,gcc-sdm845.h>
16#include <dt-bindings/clock/qcom,camcc-sdm845.h>
17#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
18#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
19#include <dt-bindings/clock/qcom,videocc-sdm845.h>
20#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
21#include <dt-bindings/clock/qcom,rpmh.h>
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]22#include <dt-bindings/soc/qcom,tcs-mbox.h>
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]23#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]24#include <dt-bindings/clock/qcom,aop-qmp.h>
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]25
Santosh Mardi903c95d2017-09-25 10:36:29 +0530[diff] [blame]26#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
27
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]28/ {
29 model = "Qualcomm Technologies, Inc. SDM670";
30 compatible = "qcom,sdm670";
31 qcom,msm-id = <336 0x0>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]32 interrupt-parent = <&pdc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]33
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]34 aliases {
35 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]36 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]37 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
Mukesh Kumar Savaliya7b272542017-07-10 19:35:29 +0530[diff] [blame]38 serial0 = &qupv3_se12_2uart;
39 spi0 = &qupv3_se8_spi;
40 i2c0 = &qupv3_se10_i2c;
41 i2c1 = &qupv3_se3_i2c;
42 hsuart0 = &qupv3_se6_4uart;
43 };
44
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]45 chosen {
Pavankumar Kondeti2c218d72017-10-03 19:31:31 +0530[diff] [blame]46 bootargs = "rcupdate.rcu_expedited=1 core_ctl_disable_cpumask=6-7";
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]47 };
48
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 CPU0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]59 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]60 cpu-release-addr = <0x0 0x90000000>;
61 next-level-cache = <&L2_0>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]62 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]63 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]64 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]65 L2_0: l2-cache {
66 compatible = "arm,arch-cache";
67 cache-size = <0x20000>;
68 cache-level = <2>;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "arm,arch-cache";
72 cache-size = <0x100000>;
73 cache-level = <3>;
74 };
75 };
76 L1_I_0: l1-icache {
77 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]78 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]79 };
80 L1_D_0: l1-dcache {
81 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]82 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]83 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]84 L1_TLB_0: l1-tlb {
85 qcom,dump-size = <0x3000>;
86 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]87 };
88
89 CPU1: cpu@100 {
90 device_type = "cpu";
91 compatible = "arm,armv8";
92 reg = <0x0 0x100>;
93 enable-method = "psci";
94 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]95 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]96 cpu-release-addr = <0x0 0x90000000>;
97 next-level-cache = <&L2_100>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]98 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]99 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]100 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]101 L2_100: l2-cache {
102 compatible = "arm,arch-cache";
103 cache-size = <0x20000>;
104 cache-level = <2>;
105 next-level-cache = <&L3_0>;
106 };
107 L1_I_100: l1-icache {
108 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]109 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]110 };
111 L1_D_100: l1-dcache {
112 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]113 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]114 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]115 L1_TLB_100: l1-tlb {
116 qcom,dump-size = <0x3000>;
117 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]118 };
119
120 CPU2: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x200>;
124 enable-method = "psci";
125 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]126 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]127 cpu-release-addr = <0x0 0x90000000>;
128 next-level-cache = <&L2_200>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]129 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]130 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]131 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]132 L2_200: l2-cache {
133 compatible = "arm,arch-cache";
134 cache-size = <0x20000>;
135 cache-level = <2>;
136 next-level-cache = <&L3_0>;
137 };
138 L1_I_200: l1-icache {
139 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]140 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]141 };
142 L1_D_200: l1-dcache {
143 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]144 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]145 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]146 L1_TLB_200: l1-tlb {
147 qcom,dump-size = <0x3000>;
148 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x0 0x300>;
155 enable-method = "psci";
156 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]157 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]158 cpu-release-addr = <0x0 0x90000000>;
159 next-level-cache = <&L2_300>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]160 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]161 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]162 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]163 L2_300: l2-cache {
164 compatible = "arm,arch-cache";
165 cache-size = <0x20000>;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 L1_I_300: l1-icache {
170 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]171 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]172 };
173 L1_D_300: l1-dcache {
174 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]175 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]176 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]177 L1_TLB_300: l1-tlb {
178 qcom,dump-size = <0x3000>;
179 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]180 };
181
182 CPU4: cpu@400 {
183 device_type = "cpu";
184 compatible = "arm,armv8";
185 reg = <0x0 0x400>;
186 enable-method = "psci";
187 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]188 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]189 cpu-release-addr = <0x0 0x90000000>;
190 next-level-cache = <&L2_400>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]191 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]192 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]193 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]194 L2_400: l2-cache {
195 compatible = "arm,arch-cache";
196 cache-size = <0x20000>;
197 cache-level = <2>;
198 next-level-cache = <&L3_0>;
199 };
200 L1_I_400: l1-icache {
201 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]202 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]203 };
204 L1_D_400: l1-dcache {
205 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]206 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]207 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]208 L1_TLB_400: l1-tlb {
209 qcom,dump-size = <0x3000>;
210 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]211 };
212
213 CPU5: cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x0 0x500>;
217 enable-method = "psci";
218 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]219 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]220 cpu-release-addr = <0x0 0x90000000>;
221 next-level-cache = <&L2_500>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]222 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]223 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]224 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]225 L2_500: l2-cache {
226 compatible = "arm,arch-cache";
227 cache-size = <0x20000>;
228 cache-level = <2>;
229 next-level-cache = <&L3_0>;
230 };
231 L1_I_500: l1-icache {
232 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]233 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]234 };
235 L1_D_500: l1-dcache {
236 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]237 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]238 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]239 L1_TLB_500: l1-tlb {
240 qcom,dump-size = <0x3000>;
241 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]242 };
243
244 CPU6: cpu@600 {
245 device_type = "cpu";
246 compatible = "arm,armv8";
247 reg = <0x0 0x600>;
248 enable-method = "psci";
249 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]250 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]251 cpu-release-addr = <0x0 0x90000000>;
252 next-level-cache = <&L2_600>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]253 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]254 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]255 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]256 L2_600: l2-cache {
257 compatible = "arm,arch-cache";
258 cache-size = <0x40000>;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
261 };
262 L1_I_600: l1-icache {
263 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]264 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]265 };
266 L1_D_600: l1-dcache {
267 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]268 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]269 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]270 L1_TLB_600: l1-tlb {
271 qcom,dump-size = <0x3c000>;
272 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]273 };
274
275 CPU7: cpu@700 {
276 device_type = "cpu";
277 compatible = "arm,armv8";
278 reg = <0x0 0x700>;
279 enable-method = "psci";
280 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]281 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]282 cpu-release-addr = <0x0 0x90000000>;
283 next-level-cache = <&L2_700>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]284 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]285 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]286 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]287 L2_700: l2-cache {
288 compatible = "arm,arch-cache";
289 cache-size = <0x40000>;
290 cache-level = <2>;
291 next-level-cache = <&L3_0>;
292 };
293 L1_I_700: l1-icache {
294 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]295 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]296 };
297 L1_D_700: l1-dcache {
298 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]299 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]300 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]301 L1_TLB_700: l1-tlb {
302 qcom,dump-size = <0x3c000>;
303 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]304 };
305
306 cpu-map {
307 cluster0 {
308 core0 {
309 cpu = <&CPU0>;
310 };
311
312 core1 {
313 cpu = <&CPU1>;
314 };
315
316 core2 {
317 cpu = <&CPU2>;
318 };
319
320 core3 {
321 cpu = <&CPU3>;
322 };
323
324 core4 {
325 cpu = <&CPU4>;
326 };
327
328 core5 {
329 cpu = <&CPU5>;
330 };
331 };
332 cluster1 {
333 core0 {
334 cpu = <&CPU6>;
335 };
336
337 core1 {
338 cpu = <&CPU7>;
339 };
340 };
341 };
342 };
343
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]344 energy_costs: energy-costs {
345 compatible = "sched-energy";
346
347 CPU_COST_0: core-cost0 {
348 busy-cost-data = <
349 300000 14
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]350 576000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]351 748800 31
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]352 998400 46
353 1209600 57
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]354 1324800 84
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]355 1516800 96
356 1612800 114
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]357 1708800 139
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]358 >;
359 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]360 12 10 8 6 4
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]361 >;
362 };
363 CPU_COST_1: core-cost1 {
364 busy-cost-data = <
365 300000 256
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]366 652800 307
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]367 825600 332
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]368 979200 382
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]369 1132800 408
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]370 1363200 448
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]371 1536000 586
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]372 1747200 641
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]373 1843200 659
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]374 1996800 696
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]375 2016000 865
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]376 2054400 876
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]377 2169600 900
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]378 2208000 924
Pavankumar Kondeti0011ca12018-12-04 10:06:40 +0530[diff] [blame^]379 2304000 940
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]380 2361600 948
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]381 2400000 1170
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]382 2457600 1200
383 2515200 1300
384 2611200 1400
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]385 >;
386 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]387 100 80 60 40 20
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]388 >;
389 };
390 CLUSTER_COST_0: cluster-cost0 {
391 busy-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]392 300000 6
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]393 576000 7
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]394 748800 8
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]395 998400 9
396 1209600 10
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]397 1324800 13
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]398 1516800 15
399 1612800 16
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]400 1708800 19
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]401 >;
402 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]403 5 4 3 2 1
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]404 >;
405 };
406 CLUSTER_COST_1: cluster-cost1 {
407 busy-cost-data = <
408 300000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]409 652800 30
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]410 825600 33
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]411 979200 38
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]412 1132800 40
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]413 1363200 44
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]414 1536000 58
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]415 1747200 64
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]416 1843200 65
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]417 1996800 69
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]418 2016000 85
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]419 2054400 87
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]420 2169600 90
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]421 2208000 92
Pavankumar Kondeti0011ca12018-12-04 10:06:40 +0530[diff] [blame^]422 2304000 93
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]423 2361600 94
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]424 2400000 117
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]425 2457600 120
426 2515200 130
427 2611200 140
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]428 >;
429 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]430 5 4 3 2 1
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]431 >;
432 };
433 };
434
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]435 psci {
436 compatible = "arm,psci-1.0";
437 method = "smc";
438 };
439
440 soc: soc { };
441
Imran Khanb1066fa2017-08-01 17:20:22 +0530[diff] [blame]442 vendor: vendor {
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges = <0 0 0 0xffffffff>;
446 compatible = "simple-bus";
447 };
448
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]449 firmware: firmware {
450 android {
451 compatible = "android,firmware";
452
monisingfb2cb762017-12-19 14:40:49 +0530[diff] [blame]453 vbmeta {
454 compatible = "android,vbmeta";
455 parts = "vbmeta,boot,system,vendor,dtbo";
456 };
457
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]458 fstab {
459 compatible = "android,fstab";
460 vendor {
461 compatible = "android,vendor";
462 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
463 type = "ext4";
464 mnt_flags = "ro,barrier=1,discard";
AnilKumar Chimata0d646ab2017-10-25 22:09:03 +0530[diff] [blame]465 fsmgr_flags = "wait,slotselect,avb";
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]466 };
467 };
468 };
469 };
470
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]471 reserved-memory {
472 #address-cells = <2>;
473 #size-cells = <2>;
474 ranges;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]475
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]476 hyp_region: hyp_region@85700000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]477 compatible = "removed-dma-pool";
478 no-map;
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]479 reg = <0 0x85700000 0 0x600000>;
480 };
481
482 xbl_region: xbl_region@85e00000 {
483 compatible = "removed-dma-pool";
484 no-map;
485 reg = <0 0x85e00000 0 0x100000>;
486 };
487
488 removed_region: removed_region@85fc0000 {
489 compatible = "removed-dma-pool";
490 no-map;
491 reg = <0 0x85fc0000 0 0x2f40000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]492 };
493
494 pil_camera_mem: camera_region@8ab00000 {
495 compatible = "removed-dma-pool";
496 no-map;
497 reg = <0 0x8ab00000 0 0x500000>;
498 };
499
500 pil_modem_mem: modem_region@8b000000 {
501 compatible = "removed-dma-pool";
502 no-map;
503 reg = <0 0x8b000000 0 0x7e00000>;
504 };
505
506 pil_video_mem: pil_video_region@92e00000 {
507 compatible = "removed-dma-pool";
508 no-map;
509 reg = <0 0x92e00000 0 0x500000>;
510 };
511
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]512 wlan_msa_mem: wlan_msa_region@93300000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]513 compatible = "removed-dma-pool";
514 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]515 reg = <0 0x93300000 0 0x100000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]516 };
517
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]518 pil_cdsp_mem: cdsp_regions@93400000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]519 compatible = "removed-dma-pool";
520 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]521 reg = <0 0x93400000 0 0x800000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]522 };
523
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]524 pil_mba_mem: pil_mba_region@0x93c00000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]525 compatible = "removed-dma-pool";
526 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]527 reg = <0 0x93c00000 0 0x200000>;
528 };
529
530 pil_adsp_mem: pil_adsp_region@93e00000 {
531 compatible = "removed-dma-pool";
532 no-map;
533 reg = <0 0x93e00000 0 0x1e00000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]534 };
535
Prakash Gupta7c571ef2018-01-19 17:57:47 +0530[diff] [blame]536 pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
537 compatible = "removed-dma-pool";
538 no-map;
539 reg = <0 0x95c00000 0 0x10000>;
540 };
541
542 pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
543 compatible = "removed-dma-pool";
544 no-map;
545 reg = <0 0x95c10000 0 0x5000>;
546 };
547
548 pil_gpu_mem: gpu_region@0x95c15000 {
549 compatible = "removed-dma-pool";
550 no-map;
551 reg = <0 0x95c15000 0 0x2000>;
552 };
553
554 qseecom_mem: qseecom_region@0x9e400000 {
555 compatible = "shared-dma-pool";
556 no-map;
557 reg = <0 0x9e400000 0 0x1400000>;
558 };
559
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]560 adsp_mem: adsp_region {
561 compatible = "shared-dma-pool";
562 alloc-ranges = <0 0x00000000 0 0xffffffff>;
563 reusable;
564 alignment = <0 0x400000>;
Tharun Kumar Meruguf0bb40e2018-06-25 16:02:04 +0530[diff] [blame]565 size = <0 0x800000>;
566 };
567
568 sdsp_mem: sdsp_region {
569 compatible = "shared-dma-pool";
570 alloc-ranges = <0 0x00000000 0 0xffffffff>;
571 reusable;
572 alignment = <0 0x400000>;
573 size = <0 0x400000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]574 };
575
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]576 qseecom_ta_mem: qseecom_ta_region {
577 compatible = "shared-dma-pool";
578 alloc-ranges = <0 0x00000000 0 0xffffffff>;
579 reusable;
580 alignment = <0 0x400000>;
581 size = <0 0x1000000>;
582 };
583
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]584 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
585 compatible = "shared-dma-pool";
586 alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
587 reusable;
588 alignment = <0 0x400000>;
589 size = <0 0x800000>;
590 };
591
592 secure_display_memory: secure_display_region {
593 compatible = "shared-dma-pool";
594 alloc-ranges = <0 0x00000000 0 0xffffffff>;
595 reusable;
596 alignment = <0 0x400000>;
597 size = <0 0x5c00000>;
598 };
599
Jayant Shekhare3191272018-01-30 16:49:08 +0530[diff] [blame]600 cont_splash_memory: cont_splash_region@9c000000 {
Sandeep Pandaf5ed08d2018-11-08 23:16:46 +0530[diff] [blame]601 reg = <0x0 0x9c000000 0x0 0x2300000>;
Jayant Shekharb59d1692017-11-10 14:21:40 +0530[diff] [blame]602 label = "cont_splash_region";
603 };
604
Sandeep Pandaf5ed08d2018-11-08 23:16:46 +0530[diff] [blame]605 dfps_data_memory: dfps_data_region@9e300000 {
606 reg = <0x0 0x9e300000 0x0 0x0100000>;
607 label = "dfps_data_region";
608 };
609
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]610 dump_mem: mem_dump_region {
611 compatible = "shared-dma-pool";
612 reusable;
613 size = <0 0x2400000>;
614 };
615
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]616 /* global autoconfigured region for contiguous allocations */
617 linux,cma {
618 compatible = "shared-dma-pool";
619 alloc-ranges = <0 0x00000000 0 0xffffffff>;
620 reusable;
621 alignment = <0 0x400000>;
622 size = <0 0x2000000>;
623 linux,cma-default;
624 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]625 };
626};
627
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]628#include "sdm670-ion.dtsi"
629
Dhoat Harpal92d63dea2017-06-06 21:20:26 +0530[diff] [blame]630#include "sdm670-smp2p.dtsi"
631
c_mtharuce962e42017-12-05 22:41:17 +0530[diff] [blame]632#include "msm-rdbg.dtsi"
633
Mukesh Kumar Savaliya065ca482017-06-06 14:44:45 +0530[diff] [blame]634#include "sdm670-qupv3.dtsi"
635
Saranya Chiduraf49fee12017-06-19 10:52:37 +0530[diff] [blame]636#include "sdm670-coresight.dtsi"
Manikanta Kanamarlapudid4abc602017-08-28 19:23:41 +0530[diff] [blame]637
638#include "sdm670-vidc.dtsi"
639
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]640#include "sdm670-sde-pll.dtsi"
641
642#include "sdm670-sde.dtsi"
643
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]644&soc {
645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges = <0 0 0 0xffffffff>;
648 compatible = "simple-bus";
649
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]650 jtag_mm0: jtagmm@7040000 {
651 compatible = "qcom,jtagv8-mm";
652 reg = <0x7040000 0x1000>;
653 reg-names = "etm-base";
654
655 clocks = <&clock_aop QDSS_CLK>;
656 clock-names = "core_clk";
657
658 qcom,coresight-jtagmm-cpu = <&CPU0>;
659 };
660
661 jtag_mm1: jtagmm@7140000 {
662 compatible = "qcom,jtagv8-mm";
663 reg = <0x7140000 0x1000>;
664 reg-names = "etm-base";
665
666 clocks = <&clock_aop QDSS_CLK>;
667 clock-names = "core_clk";
668
Mao Jinlong7da84d72018-11-13 21:03:30 +0800[diff] [blame]669 qcom,coresight-jtagmm-cpu = <&CPU1>;
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]670 };
671
672 jtag_mm2: jtagmm@7240000 {
673 compatible = "qcom,jtagv8-mm";
674 reg = <0x7240000 0x1000>;
675 reg-names = "etm-base";
676
677 clocks = <&clock_aop QDSS_CLK>;
678 clock-names = "core_clk";
679
680 qcom,coresight-jtagmm-cpu = <&CPU2>;
681 };
682
683 jtag_mm3: jtagmm@7340000 {
684 compatible = "qcom,jtagv8-mm";
685 reg = <0x7340000 0x1000>;
686 reg-names = "etm-base";
687
688 clocks = <&clock_aop QDSS_CLK>;
689 clock-names = "core_clk";
690
691 qcom,coresight-jtagmm-cpu = <&CPU3>;
692 };
693
694 jtag_mm4: jtagmm@7440000 {
695 compatible = "qcom,jtagv8-mm";
696 reg = <0x7440000 0x1000>;
697 reg-names = "etm-base";
698
699 clocks = <&clock_aop QDSS_CLK>;
700 clock-names = "core_clk";
701
702 qcom,coresight-jtagmm-cpu = <&CPU4>;
703 };
704
705 jtag_mm5: jtagmm@7540000 {
706 compatible = "qcom,jtagv8-mm";
707 reg = <0x7540000 0x1000>;
708 reg-names = "etm-base";
709
710 clocks = <&clock_aop QDSS_CLK>;
711 clock-names = "core_clk";
712
713 qcom,coresight-jtagmm-cpu = <&CPU5>;
714 };
715
716 jtag_mm6: jtagmm@7640000 {
717 compatible = "qcom,jtagv8-mm";
718 reg = <0x7640000 0x1000>;
719 reg-names = "etm-base";
720
721 clocks = <&clock_aop QDSS_CLK>;
722 clock-names = "core_clk";
723
724 qcom,coresight-jtagmm-cpu = <&CPU6>;
725 };
726
727 jtag_mm7: jtagmm@7740000 {
728 compatible = "qcom,jtagv8-mm";
729 reg = <0x7740000 0x1000>;
730 reg-names = "etm-base";
731
732 clocks = <&clock_aop QDSS_CLK>;
733 clock-names = "core_clk";
734
735 qcom,coresight-jtagmm-cpu = <&CPU7>;
736 };
737
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]738 intc: interrupt-controller@17a00000 {
739 compatible = "arm,gic-v3";
740 #interrupt-cells = <3>;
741 interrupt-controller;
742 #redistributor-regions = <1>;
743 redistributor-stride = <0x0 0x20000>;
744 reg = <0x17a00000 0x10000>, /* GICD */
745 <0x17a60000 0x100000>; /* GICR * 8 */
746 interrupts = <1 9 4>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]747 interrupt-parent = <&intc>;
Gaurav Kohli34f87562018-05-11 12:26:16 +0530[diff] [blame]748 ignored-save-restore-irqs = <38>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]749 };
750
Raghavendra Kakarla04f032162017-12-08 19:11:54 +0530[diff] [blame]751 pdc: interrupt-controller@b220000{
752 compatible = "qcom,pdc-sdm670";
753 reg = <0xb220000 0x400>;
754 #interrupt-cells = <3>;
755 interrupt-parent = <&intc>;
756 interrupt-controller;
757 };
758
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]759 timer {
760 compatible = "arm,armv8-timer";
761 interrupts = <1 1 0xf08>,
762 <1 2 0xf08>,
763 <1 3 0xf08>,
764 <1 0 0xf08>;
765 clock-frequency = <19200000>;
766 };
767
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]768 qcom,memshare {
769 compatible = "qcom,memshare";
770
771 qcom,client_1 {
772 compatible = "qcom,memshare-peripheral";
773 qcom,peripheral-size = <0x0>;
774 qcom,client-id = <0>;
775 qcom,allocate-boot-time;
776 label = "modem";
777 };
778
779 qcom,client_2 {
780 compatible = "qcom,memshare-peripheral";
781 qcom,peripheral-size = <0x0>;
782 qcom,client-id = <2>;
783 label = "modem";
784 };
785
786 mem_client_3_size: qcom,client_3 {
787 compatible = "qcom,memshare-peripheral";
788 qcom,peripheral-size = <0x500000>;
789 qcom,client-id = <1>;
Manoj Prabhu B991f9222018-01-03 19:13:56 +0530[diff] [blame]790 qcom,allocate-boot-time;
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]791 label = "modem";
792 };
793 };
794
Lakshmi Sunkarabbd69892017-06-09 13:17:10 +0530[diff] [blame]795 qcom,sps {
796 compatible = "qcom,msm_sps_4k";
797 qcom,pipe-attr-ee;
798 };
799
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]800 qcom_cedev: qcedev@1de0000 {
801 compatible = "qcom,qcedev";
802 reg = <0x1de0000 0x20000>,
803 <0x1dc4000 0x24000>;
804 reg-names = "crypto-base","crypto-bam-base";
805 interrupts = <0 272 0>;
806 qcom,bam-pipe-pair = <3>;
807 qcom,ce-hw-instance = <0>;
808 qcom,ce-device = <0>;
809 qcom,ce-hw-shared;
810 qcom,bam-ee = <0>;
811 qcom,msm-bus,name = "qcedev-noc";
812 qcom,msm-bus,num-cases = <2>;
813 qcom,msm-bus,num-paths = <1>;
814 qcom,msm-bus,vectors-KBps =
815 <125 512 0 0>,
816 <125 512 393600 393600>;
817 clock-names = "core_clk_src", "core_clk",
818 "iface_clk", "bus_clk";
819 clocks = <&clock_gcc GCC_CE1_CLK>,
820 <&clock_gcc GCC_CE1_CLK>,
821 <&clock_gcc GCC_CE1_AHB_CLK>,
822 <&clock_gcc GCC_CE1_AXI_CLK>;
823 qcom,ce-opp-freq = <171430000>;
824 qcom,request-bw-before-clk;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]825 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]826 iommus = <&apps_smmu 0x706 0x1>,
827 <&apps_smmu 0x716 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]828 };
829
Tatenda Chipeperekwa8a77c8a2018-01-30 14:50:11 -0800[diff] [blame]830 qcom_msmhdcp: qcom,msm_hdcp {
831 compatible = "qcom,msm-hdcp";
832 };
833
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]834 qcom_crypto: qcrypto@1de0000 {
835 compatible = "qcom,qcrypto";
836 reg = <0x1de0000 0x20000>,
837 <0x1dc4000 0x24000>;
838 reg-names = "crypto-base","crypto-bam-base";
839 interrupts = <0 272 0>;
840 qcom,bam-pipe-pair = <2>;
841 qcom,ce-hw-instance = <0>;
842 qcom,ce-device = <0>;
843 qcom,bam-ee = <0>;
844 qcom,ce-hw-shared;
845 qcom,clk-mgmt-sus-res;
846 qcom,msm-bus,name = "qcrypto-noc";
847 qcom,msm-bus,num-cases = <2>;
848 qcom,msm-bus,num-paths = <1>;
849 qcom,msm-bus,vectors-KBps =
850 <125 512 0 0>,
851 <125 512 393600 393600>;
852 clock-names = "core_clk_src", "core_clk",
853 "iface_clk", "bus_clk";
854 clocks = <&clock_gcc GCC_CE1_CLK>,
855 <&clock_gcc GCC_CE1_CLK>,
856 <&clock_gcc GCC_CE1_AHB_CLK>,
857 <&clock_gcc GCC_CE1_AXI_CLK>;
858 qcom,ce-opp-freq = <171430000>;
859 qcom,request-bw-before-clk;
860 qcom,use-sw-aes-cbc-ecb-ctr-algo;
861 qcom,use-sw-aes-xts-algo;
862 qcom,use-sw-aes-ccm-algo;
863 qcom,use-sw-aead-algo;
864 qcom,use-sw-ahash-algo;
865 qcom,use-sw-hmac-algo;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]866 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]867 iommus = <&apps_smmu 0x704 0x1>,
868 <&apps_smmu 0x714 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]869 };
870
Abir Ghoshb849ab22017-09-19 13:03:11 +0530[diff] [blame]871 qcom,qbt1000 {
872 compatible = "qcom,qbt1000";
873 clock-names = "core", "iface";
874 clock-frequency = <25000000>;
875 qcom,ipc-gpio = <&tlmm 121 0>;
876 qcom,finger-detect-gpio = <&tlmm 122 0>;
877 };
878
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]879 qcom_seecom: qseecom@86d00000 {
880 compatible = "qcom,qseecom";
881 reg = <0x86d00000 0x2200000>;
882 reg-names = "secapp-region";
883 qcom,hlos-num-ce-hw-instances = <1>;
884 qcom,hlos-ce-hw-instance = <0>;
885 qcom,qsee-ce-hw-instance = <0>;
886 qcom,disk-encrypt-pipe-pair = <2>;
887 qcom,support-fde;
888 qcom,no-clock-support;
Neeraj Soni7c4254c2017-11-15 11:13:14 +0530[diff] [blame]889 qcom,fde-key-size;
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]890 qcom,appsbl-qseecom-support;
891 qcom,msm-bus,name = "qseecom-noc";
892 qcom,msm-bus,num-cases = <4>;
893 qcom,msm-bus,num-paths = <1>;
894 qcom,msm-bus,vectors-KBps =
895 <125 512 0 0>,
896 <125 512 200000 400000>,
897 <125 512 300000 800000>,
898 <125 512 400000 1000000>;
899 clock-names = "core_clk_src", "core_clk",
900 "iface_clk", "bus_clk";
901 clocks = <&clock_gcc GCC_CE1_CLK>,
902 <&clock_gcc GCC_CE1_CLK>,
903 <&clock_gcc GCC_CE1_AHB_CLK>,
904 <&clock_gcc GCC_CE1_AXI_CLK>;
905 qcom,ce-opp-freq = <171430000>;
906 qcom,qsee-reentrancy-support = <2>;
907 };
908
mohamed sunfeer732f7572017-09-19 19:51:11 +0530[diff] [blame]909 qcom_tzlog: tz-log@146bf720 {
910 compatible = "qcom,tz-log";
911 reg = <0x146bf720 0x3000>;
912 qcom,hyplog-enabled;
913 hyplog-address-offset = <0x410>;
914 hyplog-size-offset = <0x414>;
915 };
916
mohamed sunfeer2228b242017-09-19 19:10:08 +0530[diff] [blame]917 qcom_rng: qrng@793000{
918 compatible = "qcom,msm-rng";
919 reg = <0x793000 0x1000>;
920 qcom,msm-rng-iface-clk;
921 qcom,no-qrng-config;
922 qcom,msm-bus,name = "msm-rng-noc";
923 qcom,msm-bus,num-cases = <2>;
924 qcom,msm-bus,num-paths = <1>;
925 qcom,msm-bus,vectors-KBps =
926 <1 618 0 0>, /* No vote */
927 <1 618 0 800>; /* 100 KHz */
928 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
929 clock-names = "iface_clk";
930 };
931
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]932 thermal_zones: thermal-zones {};
Rama Krishna Phani Aa3c0e782017-07-17 20:09:15 +0530[diff] [blame]933
934 tsens0: tsens@c222000 {
935 compatible = "qcom,tsens24xx";
936 reg = <0xc222000 0x4>,
937 <0xc263000 0x1ff>;
938 reg-names = "tsens_srot_physical",
939 "tsens_tm_physical";
940 interrupts = <0 506 0>, <0 508 0>;
941 interrupt-names = "tsens-upper-lower", "tsens-critical";
942 #thermal-sensor-cells = <1>;
943 };
944
945 tsens1: tsens@c223000 {
946 compatible = "qcom,tsens24xx";
947 reg = <0xc223000 0x4>,
948 <0xc265000 0x1ff>;
949 reg-names = "tsens_srot_physical",
950 "tsens_tm_physical";
951 interrupts = <0 507 0>, <0 509 0>;
952 interrupt-names = "tsens-upper-lower", "tsens-critical";
953 #thermal-sensor-cells = <1>;
954 };
955
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]956 timer@0x17c90000{
957 #address-cells = <1>;
958 #size-cells = <1>;
959 ranges;
960 compatible = "arm,armv7-timer-mem";
961 reg = <0x17c90000 0x1000>;
962 clock-frequency = <19200000>;
963
964 frame@0x17ca0000 {
965 frame-number = <0>;
966 interrupts = <0 7 0x4>,
967 <0 6 0x4>;
968 reg = <0x17ca0000 0x1000>,
969 <0x17cb0000 0x1000>;
970 };
971
972 frame@17cc0000 {
973 frame-number = <1>;
974 interrupts = <0 8 0x4>;
975 reg = <0x17cc0000 0x1000>;
976 status = "disabled";
977 };
978
979 frame@17cd0000 {
980 frame-number = <2>;
981 interrupts = <0 9 0x4>;
982 reg = <0x17cd0000 0x1000>;
983 status = "disabled";
984 };
985
986 frame@17ce0000 {
987 frame-number = <3>;
988 interrupts = <0 10 0x4>;
989 reg = <0x17ce0000 0x1000>;
990 status = "disabled";
991 };
992
993 frame@17cf0000 {
994 frame-number = <4>;
995 interrupts = <0 11 0x4>;
996 reg = <0x17cf0000 0x1000>;
997 status = "disabled";
998 };
999
1000 frame@17d00000 {
1001 frame-number = <5>;
1002 interrupts = <0 12 0x4>;
1003 reg = <0x17d00000 0x1000>;
1004 status = "disabled";
1005 };
1006
1007 frame@17d10000 {
1008 frame-number = <6>;
1009 interrupts = <0 13 0x4>;
1010 reg = <0x17d10000 0x1000>;
1011 status = "disabled";
1012 };
1013 };
1014
1015 restart@10ac000 {
1016 compatible = "qcom,pshold";
1017 reg = <0xC264000 0x4>,
1018 <0x1fd3000 0x4>;
1019 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1020 };
1021
Maulik Shah6bf7d5d2017-07-27 09:48:42 +0530[diff] [blame]1022 aop-msg-client {
1023 compatible = "qcom,debugfs-qmp-client";
1024 mboxes = <&qmp_aop 0>;
1025 mbox-names = "aop";
1026 };
1027
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1028 clock_rpmh: qcom,rpmhclk {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1029 compatible = "qcom,rpmh-clk-sdm670";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1030 #clock-cells = <1>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1031 mboxes = <&apps_rsc 0>;
1032 mbox-names = "apps";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1033 };
1034
1035 clock_gcc: qcom,gcc@100000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1036 compatible = "qcom,gcc-sdm670", "syscon";
1037 reg = <0x100000 0x1f0000>;
1038 reg-names = "cc_base";
1039 vdd_cx-supply = <&pm660l_s3_level>;
1040 vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1041 #clock-cells = <1>;
1042 #reset-cells = <1>;
1043 };
1044
1045 clock_videocc: qcom,videocc@ab00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1046 compatible = "qcom,video_cc-sdm670", "syscon";
1047 reg = <0xab00000 0x10000>;
1048 reg-names = "cc_base";
1049 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1050 #clock-cells = <1>;
1051 #reset-cells = <1>;
1052 };
1053
1054 clock_camcc: qcom,camcc@ad00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1055 compatible = "qcom,cam_cc-sdm670", "syscon";
1056 reg = <0xad00000 0x10000>;
1057 reg-names = "cc_base";
1058 vdd_cx-supply = <&pm660l_s3_level>;
1059 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1060 #clock-cells = <1>;
1061 #reset-cells = <1>;
Alok Pandey499587b2018-02-08 22:14:59 +0530[diff] [blame]1062 qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;
1063 qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;
1064 qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;
1065 qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;
1066 qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;
1067 qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;
1068 qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;
1069 qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;
1070 qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;
1071 qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;
1072 qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;
1073 qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;
1074 qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;
1075 qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1076 };
1077
1078 clock_dispcc: qcom,dispcc@af00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1079 compatible = "qcom,dispcc-sdm670", "syscon";
1080 reg = <0xaf00000 0x10000>;
1081 reg-names = "cc_base";
1082 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1083 #clock-cells = <1>;
1084 #reset-cells = <1>;
1085 };
1086
1087 clock_gpucc: qcom,gpucc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1088 compatible = "qcom,gpucc-sdm670", "syscon";
1089 reg = <0x5090000 0x9000>;
1090 reg-names = "cc_base";
1091 vdd_cx-supply = <&pm660l_s3_level>;
1092 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1093 qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1094 #clock-cells = <1>;
1095 #reset-cells = <1>;
1096 };
1097
1098 clock_gfx: qcom,gfxcc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1099 compatible = "qcom,gfxcc-sdm670";
1100 reg = <0x5090000 0x9000>;
1101 reg-names = "cc_base";
1102 vdd_gfx-supply = <&pm660l_s2_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1103 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1104 #clock-cells = <1>;
1105 #reset-cells = <1>;
1106 };
1107
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1108 cpucc_debug: syscon@17970018 {
1109 compatible = "syscon";
1110 reg = <0x17970018 0x4>;
1111 };
1112
1113 clock_debug: qcom,cc-debug {
1114 compatible = "qcom,debugcc-sdm845";
Shefali Jain582eb3b2018-04-24 11:46:58 +0530[diff] [blame]1115 qcom,cc-count = <6>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1116 qcom,gcc = <&clock_gcc>;
1117 qcom,videocc = <&clock_videocc>;
1118 qcom,camcc = <&clock_camcc>;
1119 qcom,dispcc = <&clock_dispcc>;
1120 qcom,gpucc = <&clock_gpucc>;
1121 qcom,cpucc = <&cpucc_debug>;
1122 clock-names = "xo_clk_src";
1123 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1124 #clock-cells = <1>;
1125 };
1126
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1127 clock_cpucc: qcom,cpucc@0x17d41000 {
1128 compatible = "qcom,clk-cpu-osm-sdm670";
1129 reg = <0x17d41000 0x1400>,
1130 <0x17d43000 0x1400>,
David Collins1e048402017-11-29 15:43:09 -0800[diff] [blame]1131 <0x17d45800 0x1400>;
1132 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda02617bd2017-11-10 16:03:43 -0800[diff] [blame]1133 vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
1134 vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1135
Odelu Kukatla86c179e2017-12-12 19:10:23 +0530[diff] [blame]1136 qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]1137 l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1138
1139 clock-names = "xo_ao";
1140 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1141 #clock-cells = <1>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1142 };
1143
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1144 clock_aop: qcom,aopclk {
Odelu Kukatla80f617f2017-09-15 19:30:25 +0530[diff] [blame]1145 compatible = "qcom,aop-qmp-clk-v1";
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1146 #clock-cells = <1>;
1147 mboxes = <&qmp_aop 0>;
1148 mbox-names = "qdss_clk";
1149 };
1150
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1151 slim_aud: slim@62dc0000 {
1152 cell-index = <1>;
1153 compatible = "qcom,slim-ngd";
1154 reg = <0x62dc0000 0x2c000>,
1155 <0x62d84000 0x2a000>;
1156 reg-names = "slimbus_physical", "slimbus_bam_physical";
1157 interrupts = <0 163 0>, <0 164 0>;
1158 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
1159 qcom,apps-ch-pipes = <0x780000>;
1160 qcom,ea-pc = <0x290>;
1161 status = "disabled";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1162 qcom,iommu-s1-bypass;
1163
1164 iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1165 compatible = "qcom,iommu-slim-ctrl-cb";
1166 iommus = <&apps_smmu 0x1826 0x0>,
1167 <&apps_smmu 0x182d 0x0>,
1168 <&apps_smmu 0x182e 0x1>,
1169 <&apps_smmu 0x1830 0x1>;
1170 };
1171
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1172 };
1173
1174 slim_qca: slim@62e40000 {
1175 cell-index = <3>;
1176 compatible = "qcom,slim-ngd";
1177 reg = <0x62e40000 0x2c000>,
1178 <0x62e04000 0x20000>;
1179 reg-names = "slimbus_physical", "slimbus_bam_physical";
1180 interrupts = <0 291 0>, <0 292 0>;
1181 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1182 status = "ok";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1183 qcom,iommu-s1-bypass;
1184
1185 iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1186 compatible = "qcom,iommu-slim-ctrl-cb";
1187 iommus = <&apps_smmu 0x1833 0x0>;
1188 };
1189
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1190 /* Slimbus Slave DT for WCN3990 */
1191 btfmslim_codec: wcn3990 {
1192 compatible = "qcom,btfmslim_slave";
1193 elemental-addr = [00 01 20 02 17 02];
1194 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
1195 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
1196 };
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1197 };
1198
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1199 wdog: qcom,wdt@17980000{
1200 compatible = "qcom,msm-watchdog";
1201 reg = <0x17980000 0x1000>;
1202 reg-names = "wdt-base";
Lingutla Chandrasekhar9fb9ba92017-10-08 21:59:19 +0530[diff] [blame]1203 interrupts = <0 0 0>, <0 1 0>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1204 qcom,bark-time = <11000>;
Neeraj Upadhyaydbc184d2017-12-07 16:05:39 +0530[diff] [blame]1205 qcom,pet-time = <9360>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1206 qcom,ipi-ping;
1207 qcom,wakeup-enable;
1208 };
1209
1210 qcom,msm-rtb {
1211 compatible = "qcom,msm-rtb";
1212 qcom,rtb-size = <0x100000>;
1213 };
1214
Lingutla Chandrasekhar4d78d722017-11-10 16:03:44 +0530[diff] [blame]1215 qcom,mpm2-sleep-counter@c221000 {
1216 compatible = "qcom,mpm2-sleep-counter";
1217 reg = <0x0c221000 0x1000>;
1218 clock-frequency = <32768>;
1219 };
1220
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1221 qcom,msm-imem@146bf000 {
1222 compatible = "qcom,msm-imem";
1223 reg = <0x146bf000 0x1000>;
1224 ranges = <0x0 0x146bf000 0x1000>;
1225 #address-cells = <1>;
1226 #size-cells = <1>;
1227
1228 mem_dump_table@10 {
1229 compatible = "qcom,msm-imem-mem_dump_table";
1230 reg = <0x10 8>;
1231 };
1232
Lingutla Chandrasekharfa5c13f2017-09-25 11:01:58 +0530[diff] [blame]1233 dload_type@1c {
1234 compatible = "qcom,msm-imem-dload-type";
1235 reg = <0x1c 0x4>;
1236 };
1237
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1238 restart_reason@65c {
1239 compatible = "qcom,msm-imem-restart_reason";
1240 reg = <0x65c 4>;
1241 };
1242
1243 pil@94c {
1244 compatible = "qcom,msm-imem-pil";
1245 reg = <0x94c 200>;
1246 };
1247
1248 kaslr_offset@6d0 {
1249 compatible = "qcom,msm-imem-kaslr_offset";
1250 reg = <0x6d0 12>;
1251 };
Lingutla Chandrasekhar3c51f0b2017-09-12 14:21:21 +0530[diff] [blame]1252
1253 boot_stats@6b0 {
1254 compatible = "qcom,msm-imem-boot_stats";
1255 reg = <0x6b0 0x20>;
1256 };
1257
1258 diag_dload@c8 {
1259 compatible = "qcom,msm-imem-diag-dload";
1260 reg = <0xc8 0xc8>;
1261 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1262 };
1263
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1264 gpi_dma0: qcom,gpi-dma@0x800000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1265 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1266 compatible = "qcom,gpi-dma";
1267 reg = <0x800000 0x60000>;
1268 reg-names = "gpi-top";
1269 interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
1270 <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
1271 <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
1272 <0 256 0>;
1273 qcom,max-num-gpii = <13>;
1274 qcom,gpii-mask = <0xfa>;
1275 qcom,ev-factor = <2>;
1276 iommus = <&apps_smmu 0x0016 0x0>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1277 qcom,smmu-cfg = <0x1>;
1278 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1279 status = "ok";
1280 };
1281
1282 gpi_dma1: qcom,gpi-dma@0xa00000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1283 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1284 compatible = "qcom,gpi-dma";
1285 reg = <0xa00000 0x60000>;
1286 reg-names = "gpi-top";
1287 interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,
1288 <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,
1289 <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>,
1290 <0 299 0>;
1291 qcom,max-num-gpii = <13>;
1292 qcom,gpii-mask = <0xfa>;
1293 qcom,ev-factor = <2>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1294 qcom,smmu-cfg = <0x1>;
1295 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1296 iommus = <&apps_smmu 0x06d6 0x0>;
1297 status = "ok";
1298 };
1299
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1300 cpuss_dump {
1301 compatible = "qcom,cpuss-dump";
1302 qcom,l1_i_cache0 {
1303 qcom,dump-node = <&L1_I_0>;
1304 qcom,dump-id = <0x60>;
1305 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1306 qcom,l1_i_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1307 qcom,dump-node = <&L1_I_100>;
1308 qcom,dump-id = <0x61>;
1309 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1310 qcom,l1_i_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1311 qcom,dump-node = <&L1_I_200>;
1312 qcom,dump-id = <0x62>;
1313 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1314 qcom,l1_i_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1315 qcom,dump-node = <&L1_I_300>;
1316 qcom,dump-id = <0x63>;
1317 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1318 qcom,l1_i_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1319 qcom,dump-node = <&L1_I_400>;
1320 qcom,dump-id = <0x64>;
1321 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1322 qcom,l1_i_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1323 qcom,dump-node = <&L1_I_500>;
1324 qcom,dump-id = <0x65>;
1325 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1326 qcom,l1_i_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1327 qcom,dump-node = <&L1_I_600>;
1328 qcom,dump-id = <0x66>;
1329 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1330 qcom,l1_i_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1331 qcom,dump-node = <&L1_I_700>;
1332 qcom,dump-id = <0x67>;
1333 };
1334 qcom,l1_d_cache0 {
1335 qcom,dump-node = <&L1_D_0>;
1336 qcom,dump-id = <0x80>;
1337 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1338 qcom,l1_d_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1339 qcom,dump-node = <&L1_D_100>;
1340 qcom,dump-id = <0x81>;
1341 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1342 qcom,l1_d_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1343 qcom,dump-node = <&L1_D_200>;
1344 qcom,dump-id = <0x82>;
1345 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1346 qcom,l1_d_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1347 qcom,dump-node = <&L1_D_300>;
1348 qcom,dump-id = <0x83>;
1349 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1350 qcom,l1_d_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1351 qcom,dump-node = <&L1_D_400>;
1352 qcom,dump-id = <0x84>;
1353 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1354 qcom,l1_d_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1355 qcom,dump-node = <&L1_D_500>;
1356 qcom,dump-id = <0x85>;
1357 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1358 qcom,l1_d_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1359 qcom,dump-node = <&L1_D_600>;
1360 qcom,dump-id = <0x86>;
1361 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1362 qcom,l1_d_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1363 qcom,dump-node = <&L1_D_700>;
1364 qcom,dump-id = <0x87>;
1365 };
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1366 qcom,llcc1_d_cache {
1367 qcom,dump-node = <&LLCC_1>;
1368 qcom,dump-id = <0x140>;
1369 };
1370 qcom,llcc2_d_cache {
1371 qcom,dump-node = <&LLCC_2>;
1372 qcom,dump-id = <0x141>;
1373 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1374 qcom,l1_tlb_dump0 {
1375 qcom,dump-node = <&L1_TLB_0>;
1376 qcom,dump-id = <0x20>;
1377 };
1378 qcom,l1_tlb_dump100 {
1379 qcom,dump-node = <&L1_TLB_100>;
1380 qcom,dump-id = <0x21>;
1381 };
1382 qcom,l1_tlb_dump200 {
1383 qcom,dump-node = <&L1_TLB_200>;
1384 qcom,dump-id = <0x22>;
1385 };
1386 qcom,l1_tlb_dump300 {
1387 qcom,dump-node = <&L1_TLB_300>;
1388 qcom,dump-id = <0x23>;
1389 };
1390 qcom,l1_tlb_dump400 {
1391 qcom,dump-node = <&L1_TLB_400>;
1392 qcom,dump-id = <0x24>;
1393 };
1394 qcom,l1_tlb_dump500 {
1395 qcom,dump-node = <&L1_TLB_500>;
1396 qcom,dump-id = <0x25>;
1397 };
1398 qcom,l1_tlb_dump600 {
1399 qcom,dump-node = <&L1_TLB_600>;
1400 qcom,dump-id = <0x26>;
1401 };
1402 qcom,l1_tlb_dump700 {
1403 qcom,dump-node = <&L1_TLB_700>;
1404 qcom,dump-id = <0x27>;
1405 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1406 };
1407
Vishwanath Raju Kb6e9cb22018-05-02 11:56:34 +0530[diff] [blame]1408 mem_dump: mem_dump {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1409 compatible = "qcom,mem-dump";
1410 memory-region = <&dump_mem>;
1411
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1412 rpmh {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1413 qcom,dump-size = <0x2000000>;
1414 qcom,dump-id = <0xec>;
1415 };
1416
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1417 rpm_sw {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1418 qcom,dump-size = <0x28000>;
1419 qcom,dump-id = <0xea>;
1420 };
1421
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1422 pmic {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1423 qcom,dump-size = <0x10000>;
1424 qcom,dump-id = <0xe4>;
1425 };
1426
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1427 tmc_etf {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1428 qcom,dump-size = <0x10000>;
1429 qcom,dump-id = <0xf0>;
1430 };
1431
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1432 tmc_etfswao {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1433 qcom,dump-size = <0x8400>;
1434 qcom,dump-id = <0xf1>;
1435 };
1436
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1437 tmc_etr_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1438 qcom,dump-size = <0x1000>;
1439 qcom,dump-id = <0x100>;
1440 };
1441
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1442 tmc_etf_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1443 qcom,dump-size = <0x1000>;
1444 qcom,dump-id = <0x101>;
1445 };
1446
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1447 etfswao_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1448 qcom,dump-size = <0x1000>;
1449 qcom,dump-id = <0x102>;
1450 };
1451
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1452 misc_data {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1453 qcom,dump-size = <0x1000>;
1454 qcom,dump-id = <0xe8>;
1455 };
1456
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1457 power_regs {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1458 qcom,dump-size = <0x100000>;
1459 qcom,dump-id = <0xed>;
1460 };
1461 };
1462
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1463 kryo3xx-erp {
1464 compatible = "arm,arm64-kryo3xx-cpu-erp";
1465 interrupts = <1 6 4>,
1466 <1 7 4>,
1467 <0 34 4>,
1468 <0 35 4>;
1469
1470 interrupt-names = "l1-l2-faultirq",
1471 "l1-l2-errirq",
1472 "l3-scu-errirq",
1473 "l3-scu-faultirq";
1474 };
1475
Dhoat Harpala24cb2c2017-06-06 20:39:54 +0530[diff] [blame]1476 qcom,ipc-spinlock@1f40000 {
1477 compatible = "qcom,ipc-spinlock-sfpb";
1478 reg = <0x1f40000 0x8000>;
1479 qcom,num-locks = <8>;
1480 };
1481
Dhoat Harpaldd9bfaf2017-06-06 20:43:16 +0530[diff] [blame]1482 qcom,smem@86000000 {
1483 compatible = "qcom,smem";
1484 reg = <0x86000000 0x200000>,
1485 <0x17911008 0x4>,
1486 <0x778000 0x7000>,
1487 <0x1fd4000 0x8>;
1488 reg-names = "smem", "irq-reg-base", "aux-mem1",
1489 "smem_targ_info_reg";
1490 qcom,mpu-enabled;
1491 };
1492
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1493 qmp_aop: qcom,qmp-aop@c300000 {
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1494 compatible = "qcom,qmp-mbox";
1495 label = "aop";
1496 reg = <0xc300000 0x100000>,
1497 <0x1799000c 0x4>;
1498 reg-names = "msgram", "irq-reg-base";
1499 qcom,irq-mask = <0x1>;
1500 interrupts = <0 389 1>;
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1501 priority = <0>;
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1502 mbox-desc-offset = <0x0>;
1503 #mbox-cells = <1>;
1504 };
1505
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1506 qcom,glink-smem-native-xprt-modem@86000000 {
1507 compatible = "qcom,glink-smem-native-xprt";
1508 reg = <0x86000000 0x200000>,
1509 <0x1799000c 0x4>;
1510 reg-names = "smem", "irq-reg-base";
1511 qcom,irq-mask = <0x1000>;
1512 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1513 label = "mpss";
1514 };
1515
1516 qcom,glink-smem-native-xprt-adsp@86000000 {
1517 compatible = "qcom,glink-smem-native-xprt";
1518 reg = <0x86000000 0x200000>,
1519 <0x1799000c 0x4>;
1520 reg-names = "smem", "irq-reg-base";
Dhoat Harpal3adebbe2017-07-06 15:59:13 +0530[diff] [blame]1521 qcom,irq-mask = <0x1000000>;
1522 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1523 label = "lpass";
1524 qcom,qos-config = <&glink_qos_adsp>;
1525 qcom,ramp-time = <0xaf>;
1526 };
1527
1528 glink_qos_adsp: qcom,glink-qos-config-adsp {
1529 compatible = "qcom,glink-qos-config";
1530 qcom,flow-info = <0x3c 0x0>,
1531 <0x3c 0x0>,
1532 <0x3c 0x0>,
1533 <0x3c 0x0>;
1534 qcom,mtu-size = <0x800>;
1535 qcom,tput-stats-cycle = <0xa>;
1536 };
1537
1538 glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1539 compatible = "qcom,glink-spi-xprt";
1540 label = "wdsp";
1541 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1542 qcom,qos-config = <&glink_qos_wdsp>;
1543 qcom,ramp-time = <0x10>,
1544 <0x20>,
1545 <0x30>,
1546 <0x40>;
1547 };
1548
1549 glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1550 compatible = "qcom,glink-fifo-config";
1551 qcom,out-read-idx-reg = <0x12000>;
1552 qcom,out-write-idx-reg = <0x12004>;
1553 qcom,in-read-idx-reg = <0x1200C>;
1554 qcom,in-write-idx-reg = <0x12010>;
1555 };
1556
1557 glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1558 compatible = "qcom,glink-qos-config";
1559 qcom,flow-info = <0x80 0x0>,
1560 <0x70 0x1>,
1561 <0x60 0x2>,
1562 <0x50 0x3>;
1563 qcom,mtu-size = <0x800>;
1564 qcom,tput-stats-cycle = <0xa>;
1565 };
1566
1567 qcom,glink-smem-native-xprt-cdsp@86000000 {
1568 compatible = "qcom,glink-smem-native-xprt";
1569 reg = <0x86000000 0x200000>,
1570 <0x1799000c 0x4>;
1571 reg-names = "smem", "irq-reg-base";
1572 qcom,irq-mask = <0x10>;
1573 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1574 label = "cdsp";
1575 };
1576
Dhoat Harpal9cb73cc2017-06-06 20:58:14 +0530[diff] [blame]1577 glink_mpss: qcom,glink-ssr-modem {
1578 compatible = "qcom,glink_ssr";
1579 label = "modem";
1580 qcom,edge = "mpss";
1581 qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>;
1582 qcom,xprt = "smem";
1583 };
1584
1585 glink_lpass: qcom,glink-ssr-adsp {
1586 compatible = "qcom,glink_ssr";
1587 label = "adsp";
1588 qcom,edge = "lpass";
1589 qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>;
1590 qcom,xprt = "smem";
1591 };
1592
1593 glink_cdsp: qcom,glink-ssr-cdsp {
1594 compatible = "qcom,glink_ssr";
1595 label = "cdsp";
1596 qcom,edge = "cdsp";
1597 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>;
1598 qcom,xprt = "smem";
1599 };
1600
Dhoat Harpal22dafa92017-06-06 21:03:34 +0530[diff] [blame]1601 qcom,ipc_router {
1602 compatible = "qcom,ipc_router";
1603 qcom,node-id = <1>;
1604 };
1605
1606 qcom,ipc_router_modem_xprt {
1607 compatible = "qcom,ipc_router_glink_xprt";
1608 qcom,ch-name = "IPCRTR";
1609 qcom,xprt-remote = "mpss";
1610 qcom,glink-xprt = "smem";
1611 qcom,xprt-linkid = <1>;
1612 qcom,xprt-version = <1>;
1613 qcom,fragmented-data;
1614 };
1615
1616 qcom,ipc_router_q6_xprt {
1617 compatible = "qcom,ipc_router_glink_xprt";
1618 qcom,ch-name = "IPCRTR";
1619 qcom,xprt-remote = "lpass";
1620 qcom,glink-xprt = "smem";
1621 qcom,xprt-linkid = <1>;
1622 qcom,xprt-version = <1>;
1623 qcom,fragmented-data;
1624 };
1625
1626 qcom,ipc_router_cdsp_xprt {
1627 compatible = "qcom,ipc_router_glink_xprt";
1628 qcom,ch-name = "IPCRTR";
1629 qcom,xprt-remote = "cdsp";
1630 qcom,glink-xprt = "smem";
1631 qcom,xprt-linkid = <1>;
1632 qcom,xprt-version = <1>;
1633 qcom,fragmented-data;
1634 };
1635
Dhoat Harpal11d34482017-06-06 21:00:14 +0530[diff] [blame]1636 qcom,glink_pkt {
1637 compatible = "qcom,glinkpkt";
1638
1639 qcom,glinkpkt-at-mdm0 {
1640 qcom,glinkpkt-transport = "smem";
1641 qcom,glinkpkt-edge = "mpss";
1642 qcom,glinkpkt-ch-name = "DS";
1643 qcom,glinkpkt-dev-name = "at_mdm0";
1644 };
1645
1646 qcom,glinkpkt-loopback_cntl {
1647 qcom,glinkpkt-transport = "lloop";
1648 qcom,glinkpkt-edge = "local";
1649 qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1650 qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1651 };
1652
1653 qcom,glinkpkt-loopback_data {
1654 qcom,glinkpkt-transport = "lloop";
1655 qcom,glinkpkt-edge = "local";
1656 qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1657 qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1658 };
1659
1660 qcom,glinkpkt-apr-apps2 {
1661 qcom,glinkpkt-transport = "smem";
1662 qcom,glinkpkt-edge = "adsp";
1663 qcom,glinkpkt-ch-name = "apr_apps2";
1664 qcom,glinkpkt-dev-name = "apr_apps2";
1665 };
1666
1667 qcom,glinkpkt-data40-cntl {
1668 qcom,glinkpkt-transport = "smem";
1669 qcom,glinkpkt-edge = "mpss";
1670 qcom,glinkpkt-ch-name = "DATA40_CNTL";
1671 qcom,glinkpkt-dev-name = "smdcntl8";
1672 };
1673
1674 qcom,glinkpkt-data1 {
1675 qcom,glinkpkt-transport = "smem";
1676 qcom,glinkpkt-edge = "mpss";
1677 qcom,glinkpkt-ch-name = "DATA1";
1678 qcom,glinkpkt-dev-name = "smd7";
1679 };
1680
1681 qcom,glinkpkt-data4 {
1682 qcom,glinkpkt-transport = "smem";
1683 qcom,glinkpkt-edge = "mpss";
1684 qcom,glinkpkt-ch-name = "DATA4";
1685 qcom,glinkpkt-dev-name = "smd8";
1686 };
1687
1688 qcom,glinkpkt-data11 {
1689 qcom,glinkpkt-transport = "smem";
1690 qcom,glinkpkt-edge = "mpss";
1691 qcom,glinkpkt-ch-name = "DATA11";
1692 qcom,glinkpkt-dev-name = "smd11";
1693 };
1694 };
1695
Gaurav Kohlid1131902018-02-21 13:21:25 +0530[diff] [blame]1696 qcom,chd_silver {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1697 compatible = "qcom,core-hang-detect";
1698 label = "silver";
1699 qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
1700 0x17e30058 0x17e40058 0x17e50058>;
1701 qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
1702 0x17e30060 0x17e40060 0x17e50060>;
1703 };
1704
1705 qcom,chd_gold {
1706 compatible = "qcom,core-hang-detect";
1707 label = "gold";
1708 qcom,threshold-arr = <0x17e60058 0x17e70058>;
1709 qcom,config-arr = <0x17e60060 0x17e70060>;
1710 };
1711
1712 qcom,ghd {
1713 compatible = "qcom,gladiator-hang-detect-v2";
1714 qcom,threshold-arr = <0x1799041c 0x17990420>;
1715 qcom,config-reg = <0x17990434>;
1716 };
1717
1718 qcom,msm-gladiator-v3@17900000 {
1719 compatible = "qcom,msm-gladiator-v3";
1720 reg = <0x17900000 0xd080>;
1721 reg-names = "gladiator_base";
1722 interrupts = <0 17 0>;
1723 };
1724
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1725 eud: qcom,msm-eud@88e0000 {
1726 compatible = "qcom,msm-eud";
1727 interrupt-names = "eud_irq";
1728 interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
1729 reg = <0x88e0000 0x2000>;
1730 reg-names = "eud_base";
Lingutla Chandrasekhar5422daf2017-10-26 11:27:32 +0530[diff] [blame]1731 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1732 clock-names = "cfg_ahb_clk";
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1733 };
1734
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1735 qcom,llcc@1100000 {
1736 compatible = "qcom,llcc-core", "syscon", "simple-mfd";
1737 reg = <0x1100000 0x250000>;
1738 reg-names = "llcc_base";
1739 qcom,llcc-banks-off = <0x0 0x80000 >;
1740 qcom,llcc-broadcast-off = <0x200000>;
1741
1742 llcc: qcom,sdm670-llcc {
1743 compatible = "qcom,sdm670-llcc";
1744 #cache-cells = <1>;
1745 max-slices = <32>;
1746 qcom,dump-size = <0x80000>;
1747 };
1748
Sankaran Nampoothiri0c5dac02017-11-06 11:53:52 +0530[diff] [blame]1749 qcom,llcc-perfmon {
1750 compatible = "qcom,llcc-perfmon";
1751 };
1752
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1753 qcom,llcc-erp {
1754 compatible = "qcom,llcc-erp";
1755 interrupt-names = "ecc_irq";
1756 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1757 };
1758
1759 qcom,llcc-amon {
1760 compatible = "qcom,llcc-amon";
1761 };
1762
1763 LLCC_1: llcc_1_dcache {
1764 qcom,dump-size = <0xd8000>;
1765 };
1766
1767 LLCC_2: llcc_2_dcache {
1768 qcom,dump-size = <0xd8000>;
1769 };
1770 };
1771
Maulik Shah210773d2017-06-15 09:49:12 +0530[diff] [blame]1772 cmd_db: qcom,cmd-db@c3f000c {
1773 compatible = "qcom,cmd-db";
1774 reg = <0xc3f000c 0x8>;
1775 };
1776
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]1777 apps_rsc: mailbox@179e0000 {
1778 compatible = "qcom,tcs-drv";
1779 label = "apps_rsc";
1780 reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
1781 interrupts = <0 5 0>;
1782 #mbox-cells = <1>;
1783 qcom,drv-id = <2>;
1784 qcom,tcs-config = <ACTIVE_TCS 2>,
1785 <SLEEP_TCS 3>,
1786 <WAKE_TCS 3>,
1787 <CONTROL_TCS 1>;
1788 };
1789
Maulik Shahda3941f2017-06-15 09:41:38 +0530[diff] [blame]1790 disp_rsc: mailbox@af20000 {
1791 compatible = "qcom,tcs-drv";
1792 label = "display_rsc";
1793 reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
1794 interrupts = <0 129 0>;
1795 #mbox-cells = <1>;
1796 qcom,drv-id = <0>;
1797 qcom,tcs-config = <SLEEP_TCS 1>,
1798 <WAKE_TCS 1>,
1799 <ACTIVE_TCS 0>,
1800 <CONTROL_TCS 1>;
1801 };
1802
Maulik Shah0dd203f2017-06-15 09:44:59 +0530[diff] [blame]1803 system_pm {
1804 compatible = "qcom,system-pm";
1805 mboxes = <&apps_rsc 0>;
1806 };
1807
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1808 dcc: dcc_v2@10a2000 {
Mao Jinlong1d656f92018-04-09 16:09:44 +0800[diff] [blame]1809 compatible = "qcom,dcc-v2";
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1810 reg = <0x10a2000 0x1000>,
1811 <0x10ae000 0x2000>;
1812 reg-names = "dcc-base", "dcc-ram-base";
Saranya Chidurac0a161c2017-08-28 13:06:10 +0530[diff] [blame]1813
1814 dcc-ram-offset = <0x6000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1815 };
1816
Tirupathi Reddy9ae4c892017-06-09 12:30:31 +0530[diff] [blame]1817 spmi_bus: qcom,spmi@c440000 {
1818 compatible = "qcom,spmi-pmic-arb";
1819 reg = <0xc440000 0x1100>,
1820 <0xc600000 0x2000000>,
1821 <0xe600000 0x100000>,
1822 <0xe700000 0xa0000>,
1823 <0xc40a000 0x26000>;
1824 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1825 interrupt-names = "periph_irq";
1826 interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
1827 qcom,ee = <0>;
1828 qcom,channel = <0>;
1829 #address-cells = <2>;
1830 #size-cells = <0>;
1831 interrupt-controller;
1832 #interrupt-cells = <4>;
1833 cell-index = <0>;
1834 };
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1835
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1836 ufs_ice: ufsice@1d90000 {
1837 compatible = "qcom,ice";
1838 reg = <0x1d90000 0x8000>;
1839 qcom,enable-ice-clk;
1840 clock-names = "ufs_core_clk", "bus_clk",
1841 "iface_clk", "ice_core_clk";
1842 clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
1843 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1844 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1845 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1846 qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
1847 vdd-hba-supply = <&ufs_phy_gdsc>;
1848 qcom,msm-bus,name = "ufs_ice_noc";
1849 qcom,msm-bus,num-cases = <2>;
1850 qcom,msm-bus,num-paths = <1>;
1851 qcom,msm-bus,vectors-KBps =
1852 <1 650 0 0>, /* No vote */
1853 <1 650 1000 0>; /* Max. bandwidth */
1854 qcom,bus-vector-names = "MIN",
1855 "MAX";
1856 qcom,instance-type = "ufs";
1857 };
1858
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1859 ufsphy_mem: ufsphy_mem@1d87000 {
1860 reg = <0x1d87000 0xe00>; /* PHY regs */
1861 reg-names = "phy_mem";
1862 #phy-cells = <0>;
1863
1864 lanes-per-direction = <1>;
1865
1866 clock-names = "ref_clk_src",
1867 "ref_clk",
1868 "ref_aux_clk";
1869 clocks = <&clock_rpmh RPMH_CXO_CLK>,
1870 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1871 <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
1872
1873 status = "disabled";
1874 };
1875
1876 ufshc_mem: ufshc@1d84000 {
1877 compatible = "qcom,ufshc";
1878 reg = <0x1d84000 0x3000>;
1879 interrupts = <0 265 0>;
1880 phys = <&ufsphy_mem>;
1881 phy-names = "ufsphy";
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1882 ufs-qcom-crypto = <&ufs_ice>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1883
1884 lanes-per-direction = <1>;
Sayali Lokhande1e49f022018-09-07 12:24:43 +0530[diff] [blame]1885 spm-level = <5>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1886 dev-ref-clk-freq = <0>; /* 19.2 MHz */
1887
1888 clock-names =
1889 "core_clk",
1890 "bus_aggr_clk",
1891 "iface_clk",
1892 "core_clk_unipro",
1893 "core_clk_ice",
1894 "ref_clk",
1895 "tx_lane0_sync_clk",
1896 "rx_lane0_sync_clk";
1897 clocks =
1898 <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]1899 <&clock_gcc UFS_PHY_AXI_UFS_VOTE_CLK>,
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1900 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1901 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
1902 <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
1903 <&clock_rpmh RPMH_CXO_CLK>,
1904 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1905 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1906 freq-table-hz =
1907 <50000000 200000000>,
1908 <0 0>,
1909 <0 0>,
1910 <37500000 150000000>,
1911 <75000000 300000000>,
1912 <0 0>,
1913 <0 0>,
1914 <0 0>;
1915
Sayali Lokhandeaa3db742017-10-09 15:13:01 +0530[diff] [blame]1916 non-removable;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1917 qcom,msm-bus,name = "ufshc_mem";
1918 qcom,msm-bus,num-cases = <12>;
1919 qcom,msm-bus,num-paths = <2>;
1920 qcom,msm-bus,vectors-KBps =
1921 /*
1922 * During HS G3 UFS runs at nominal voltage corner, vote
1923 * higher bandwidth to push other buses in the data path
1924 * to run at nominal to achieve max throughput.
1925 * 4GBps pushes BIMC to run at nominal.
1926 * 200MBps pushes CNOC to run at nominal.
1927 * Vote for half of this bandwidth for HS G3 1-lane.
1928 * For max bandwidth, vote high enough to push the buses
1929 * to run in turbo voltage corner.
1930 */
1931 <123 512 0 0>, <1 757 0 0>, /* No vote */
1932 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
1933 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
1934 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
1935 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
1936 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
1937 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
1938 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
1939 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
1940 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
1941 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
1942 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
1943
1944 qcom,bus-vector-names = "MIN",
1945 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1946 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1947 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1948 "MAX";
1949
1950 /* PM QoS */
1951 qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]1952 qcom,pm-qos-cpu-group-latency-us = <67 67>;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1953 qcom,pm-qos-default-cpu = <0>;
1954
Sayali Lokhandebd53f6a2018-04-05 16:32:08 +0530[diff] [blame]1955 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
1956 pinctrl-0 = <&ufs_dev_reset_assert>;
1957 pinctrl-1 = <&ufs_dev_reset_deassert>;
1958
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1959 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
1960 reset-names = "core_reset";
1961
1962 status = "disabled";
1963 };
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1964
1965 qcom,lpass@62400000 {
1966 compatible = "qcom,pil-tz-generic";
1967 reg = <0x62400000 0x00100>;
1968 interrupts = <0 162 1>;
1969
1970 vdd_cx-supply = <&pm660l_l9_level>;
1971 qcom,proxy-reg-names = "vdd_cx";
1972 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
1973
1974 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1975 clock-names = "xo";
1976 qcom,proxy-clock-names = "xo";
1977
1978 qcom,pas-id = <1>;
1979 qcom,proxy-timeout-ms = <10000>;
1980 qcom,smem-id = <423>;
1981 qcom,sysmon-id = <1>;
1982 qcom,ssctl-instance-id = <0x14>;
1983 qcom,firmware-name = "adsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1984 qcom,signal-aop;
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1985 memory-region = <&pil_adsp_mem>;
1986
1987 /* GPIO inputs from lpass */
1988 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
1989 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
1990 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
1991 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
1992
1993 /* GPIO output to lpass */
1994 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1995
1996 mboxes = <&qmp_aop 0>;
1997 mbox-names = "adsp-pil";
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1998 status = "ok";
1999 };
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2000
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]2001 qcom,rmtfs_sharedmem@0 {
2002 compatible = "qcom,sharedmem-uio";
2003 reg = <0x0 0x200000>;
2004 reg-names = "rmtfs";
2005 qcom,client-id = <0x00000001>;
Sahitya Tummala57f7b572017-10-23 10:29:03 +0530[diff] [blame]2006 qcom,guard-memory;
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]2007 };
2008
Mohammed Javidf97a10e2017-10-08 13:11:26 +0530[diff] [blame]2009 qcom,msm_gsi {
2010 compatible = "qcom,msm_gsi";
2011 };
2012
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2013 qcom,rmnet-ipa {
2014 compatible = "qcom,rmnet-ipa3";
2015 qcom,rmnet-ipa-ssr;
2016 qcom,ipa-loaduC;
2017 qcom,ipa-advertise-sg-support;
2018 qcom,ipa-napi-enable;
2019 };
2020
2021 ipa_hw: qcom,ipa@01e00000 {
2022 compatible = "qcom,ipa";
2023 reg = <0x1e00000 0x34000>,
2024 <0x1e04000 0x2c000>;
2025 reg-names = "ipa-base", "gsi-base";
2026 interrupts =
2027 <0 311 0>,
2028 <0 432 0>;
2029 interrupt-names = "ipa-irq", "gsi-irq";
2030 qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
Mohammed Javiddcefa282018-04-10 17:22:30 +0530[diff] [blame]2031 qcom,ipa-hw-mode = <0>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2032 qcom,ee = <0>;
2033 qcom,use-ipa-tethering-bridge;
2034 qcom,modem-cfg-emb-pipe-flt;
2035 qcom,ipa-wdi2;
2036 qcom,use-64-bit-dma-mask;
2037 qcom,arm-smmu;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2038 qcom,bandwidth-vote-for-ipa;
2039 qcom,msm-bus,name = "ipa";
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2040 qcom,msm-bus,num-cases = <5>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2041 qcom,msm-bus,num-paths = <4>;
2042 qcom,msm-bus,vectors-KBps =
2043 /* No vote */
2044 <90 512 0 0>,
2045 <90 585 0 0>,
2046 <1 676 0 0>,
2047 <143 777 0 0>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2048 /* SVS2 */
2049 <90 512 80000 600000>,
2050 <90 585 80000 350000>,
2051 <1 676 40000 40000>, /*gcc_config_noc_clk_src */
2052 <143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2053 /* SVS */
2054 <90 512 80000 640000>,
2055 <90 585 80000 640000>,
2056 <1 676 80000 80000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2057 <143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2058 /* NOMINAL */
2059 <90 512 206000 960000>,
2060 <90 585 206000 960000>,
2061 <1 676 206000 160000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2062 <143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2063 /* TURBO */
2064 <90 512 206000 3600000>,
2065 <90 585 206000 3600000>,
2066 <1 676 206000 300000>,
Mohammed Javid6c065482017-09-19 19:19:27 +0530[diff] [blame]2067 <143 777 0 355>; /* IB defined for IPA clk in MHz*/
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2068 qcom,bus-vector-names =
2069 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2070
2071 /* IPA RAM mmap */
2072 qcom,ipa-ram-mmap = <
2073 0x280 /* ofst_start; */
2074 0x0 /* nat_ofst; */
2075 0x0 /* nat_size; */
2076 0x288 /* v4_flt_hash_ofst; */
2077 0x78 /* v4_flt_hash_size; */
2078 0x4000 /* v4_flt_hash_size_ddr; */
2079 0x308 /* v4_flt_nhash_ofst; */
2080 0x78 /* v4_flt_nhash_size; */
2081 0x4000 /* v4_flt_nhash_size_ddr; */
2082 0x388 /* v6_flt_hash_ofst; */
2083 0x78 /* v6_flt_hash_size; */
2084 0x4000 /* v6_flt_hash_size_ddr; */
2085 0x408 /* v6_flt_nhash_ofst; */
2086 0x78 /* v6_flt_nhash_size; */
2087 0x4000 /* v6_flt_nhash_size_ddr; */
2088 0xf /* v4_rt_num_index; */
2089 0x0 /* v4_modem_rt_index_lo; */
2090 0x7 /* v4_modem_rt_index_hi; */
2091 0x8 /* v4_apps_rt_index_lo; */
2092 0xe /* v4_apps_rt_index_hi; */
2093 0x488 /* v4_rt_hash_ofst; */
2094 0x78 /* v4_rt_hash_size; */
2095 0x4000 /* v4_rt_hash_size_ddr; */
2096 0x508 /* v4_rt_nhash_ofst; */
2097 0x78 /* v4_rt_nhash_size; */
2098 0x4000 /* v4_rt_nhash_size_ddr; */
2099 0xf /* v6_rt_num_index; */
2100 0x0 /* v6_modem_rt_index_lo; */
2101 0x7 /* v6_modem_rt_index_hi; */
2102 0x8 /* v6_apps_rt_index_lo; */
2103 0xe /* v6_apps_rt_index_hi; */
2104 0x588 /* v6_rt_hash_ofst; */
2105 0x78 /* v6_rt_hash_size; */
2106 0x4000 /* v6_rt_hash_size_ddr; */
2107 0x608 /* v6_rt_nhash_ofst; */
2108 0x78 /* v6_rt_nhash_size; */
2109 0x4000 /* v6_rt_nhash_size_ddr; */
2110 0x688 /* modem_hdr_ofst; */
2111 0x140 /* modem_hdr_size; */
2112 0x7c8 /* apps_hdr_ofst; */
2113 0x0 /* apps_hdr_size; */
2114 0x800 /* apps_hdr_size_ddr; */
2115 0x7d0 /* modem_hdr_proc_ctx_ofst; */
2116 0x200 /* modem_hdr_proc_ctx_size; */
2117 0x9d0 /* apps_hdr_proc_ctx_ofst; */
2118 0x200 /* apps_hdr_proc_ctx_size; */
2119 0x0 /* apps_hdr_proc_ctx_size_ddr; */
2120 0x0 /* modem_comp_decomp_ofst; diff */
2121 0x0 /* modem_comp_decomp_size; diff */
2122 0xbd8 /* modem_ofst; */
2123 0x1024 /* modem_size; */
2124 0x2000 /* apps_v4_flt_hash_ofst; */
2125 0x0 /* apps_v4_flt_hash_size; */
2126 0x2000 /* apps_v4_flt_nhash_ofst; */
2127 0x0 /* apps_v4_flt_nhash_size; */
2128 0x2000 /* apps_v6_flt_hash_ofst; */
2129 0x0 /* apps_v6_flt_hash_size; */
2130 0x2000 /* apps_v6_flt_nhash_ofst; */
2131 0x0 /* apps_v6_flt_nhash_size; */
2132 0x80 /* uc_info_ofst; */
2133 0x200 /* uc_info_size; */
2134 0x2000 /* end_ofst; */
2135 0x2000 /* apps_v4_rt_hash_ofst; */
2136 0x0 /* apps_v4_rt_hash_size; */
2137 0x2000 /* apps_v4_rt_nhash_ofst; */
2138 0x0 /* apps_v4_rt_nhash_size; */
2139 0x2000 /* apps_v6_rt_hash_ofst; */
2140 0x0 /* apps_v6_rt_hash_size; */
2141 0x2000 /* apps_v6_rt_nhash_ofst; */
2142 0x0 /* apps_v6_rt_nhash_size; */
2143 0x1c00 /* uc_event_ring_ofst; */
2144 0x400 /* uc_event_ring_size; */
2145 >;
2146
2147 /* smp2p gpio information */
2148 qcom,smp2pgpio_map_ipa_1_out {
2149 compatible = "qcom,smp2pgpio-map-ipa-1-out";
2150 gpios = <&smp2pgpio_ipa_1_out 0 0>;
2151 };
2152
2153 qcom,smp2pgpio_map_ipa_1_in {
2154 compatible = "qcom,smp2pgpio-map-ipa-1-in";
2155 gpios = <&smp2pgpio_ipa_1_in 0 0>;
2156 };
2157
2158 ipa_smmu_ap: ipa_smmu_ap {
2159 compatible = "qcom,ipa-smmu-ap-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2160 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2161 iommus = <&apps_smmu 0x720 0x0>;
2162 qcom,iova-mapping = <0x20000000 0x40000000>;
2163 };
2164
2165 ipa_smmu_wlan: ipa_smmu_wlan {
2166 compatible = "qcom,ipa-smmu-wlan-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2167 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2168 iommus = <&apps_smmu 0x721 0x0>;
2169 };
2170
2171 ipa_smmu_uc: ipa_smmu_uc {
2172 compatible = "qcom,ipa-smmu-uc-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2173 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2174 iommus = <&apps_smmu 0x722 0x0>;
2175 qcom,iova-mapping = <0x40000000 0x20000000>;
2176 };
2177 };
2178
2179 qcom,ipa_fws {
2180 compatible = "qcom,pil-tz-generic";
2181 qcom,pas-id = <0xf>;
2182 qcom,firmware-name = "ipa_fws";
Mohammed Javid42445cb2018-02-01 18:22:17 +0530[diff] [blame]2183 qcom,pil-force-shutdown;
Mohammed Javide0dd2a32018-01-25 14:18:56 +0530[diff] [blame]2184 memory-region = <&pil_ipa_fw_mem>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2185 };
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2186
2187 pil_modem: qcom,mss@4080000 {
2188 compatible = "qcom,pil-q6v55-mss";
2189 reg = <0x4080000 0x100>,
2190 <0x1f63000 0x008>,
2191 <0x1f65000 0x008>,
2192 <0x1f64000 0x008>,
2193 <0x4180000 0x020>,
2194 <0xc2b0000 0x004>,
2195 <0xb2e0100 0x004>,
2196 <0x4180044 0x004>;
2197 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2198 "halt_nc", "rmb_base", "restart_reg",
2199 "pdc_sync", "alt_reset";
2200
2201 clocks = <&clock_rpmh RPMH_CXO_CLK>,
2202 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2203 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2204 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2205 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2206 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2207 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
2208 <&clock_gcc GCC_PRNG_AHB_CLK>;
2209 clock-names = "xo", "iface_clk", "bus_clk",
2210 "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2211 "mnoc_axi_clk", "prng_clk";
2212 qcom,proxy-clock-names = "xo", "prng_clk";
2213 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2214 "gpll0_mss_clk", "snoc_axi_clk",
2215 "mnoc_axi_clk";
2216
2217 interrupts = <0 266 1>;
2218 vdd_cx-supply = <&pm660l_s3_level>;
2219 vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
2220 vdd_mx-supply = <&pm660l_s1_level>;
2221 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Jitendra Sharma2e981ef2017-10-30 12:16:23 +0530[diff] [blame]2222 vdd_mss-supply = <&pm660_s5_level>;
2223 vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2224 qcom,firmware-name = "modem";
2225 qcom,pil-self-auth;
2226 qcom,sysmon-id = <0>;
Avaneesh Kumar Dwivedi8d336612017-11-09 16:48:25 +0530[diff] [blame]2227 qcom,minidump-id = <3>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2228 qcom,ssctl-instance-id = <0x12>;
2229 qcom,override-acc;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2230 qcom,signal-aop;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2231 qcom,qdsp6v65-1-0;
Jitendra Sharma93dd7fc2017-10-14 17:38:55 +0530[diff] [blame]2232 qcom,mss_pdc_offset = <9>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2233 status = "ok";
2234 memory-region = <&pil_modem_mem>;
2235 qcom,mem-protect-id = <0xF>;
Shadab Naseem60b870a2018-05-11 14:31:03 +0530[diff] [blame]2236 qcom,complete-ramdump;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2237
2238 /* GPIO inputs from mss */
2239 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2240 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2241 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2242 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2243 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2244
2245 /* GPIO output to mss */
2246 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2247
2248 mboxes = <&qmp_aop 0>;
2249 mbox-names = "mss-pil";
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2250 qcom,mba-mem@0 {
2251 compatible = "qcom,pil-mba-mem";
2252 memory-region = <&pil_mba_mem>;
2253 };
2254 };
Gaurav Kohli985a99d2017-07-25 18:46:45 +0530[diff] [blame]2255
2256 qcom,venus@aae0000 {
2257 compatible = "qcom,pil-tz-generic";
2258 reg = <0xaae0000 0x4000>;
2259
2260 vdd-supply = <&venus_gdsc>;
2261 qcom,proxy-reg-names = "vdd";
2262
2263 clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2264 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
2265 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2266 clock-names = "core_clk", "iface_clk", "bus_clk";
2267 qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
2268
2269 qcom,pas-id = <9>;
2270 qcom,msm-bus,name = "pil-venus";
2271 qcom,msm-bus,num-cases = <2>;
2272 qcom,msm-bus,num-paths = <1>;
2273 qcom,msm-bus,vectors-KBps =
2274 <63 512 0 0>,
2275 <63 512 0 304000>;
2276 qcom,proxy-timeout-ms = <100>;
2277 qcom,firmware-name = "venus";
2278 memory-region = <&pil_video_mem>;
2279 status = "ok";
2280 };
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2281
2282 qcom,turing@8300000 {
2283 compatible = "qcom,pil-tz-generic";
2284 reg = <0x8300000 0x100000>;
2285 interrupts = <0 578 1>;
2286
2287 vdd_cx-supply = <&pm660l_s3_level>;
2288 qcom,proxy-reg-names = "vdd_cx";
2289 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2290
2291 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2292 clock-names = "xo";
2293 qcom,proxy-clock-names = "xo";
2294
2295 qcom,pas-id = <18>;
2296 qcom,proxy-timeout-ms = <10000>;
2297 qcom,smem-id = <601>;
2298 qcom,sysmon-id = <7>;
2299 qcom,ssctl-instance-id = <0x17>;
2300 qcom,firmware-name = "cdsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2301 qcom,signal-aop;
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2302 memory-region = <&pil_cdsp_mem>;
2303
2304 /* GPIO inputs from turing */
2305 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2306 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2307 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2308 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2309
2310 /* GPIO output to turing*/
2311 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2312
2313 mboxes = <&qmp_aop 0>;
2314 mbox-names = "cdsp-pil";
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2315 status = "ok";
2316 };
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2317
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2318 sdcc1_ice: sdcc1ice@7c8000 {
2319 compatible = "qcom,ice";
2320 reg = <0x7c8000 0x8000>;
2321 qcom,enable-ice-clk;
2322 clock-names = "ice_core_clk_src", "ice_core_clk",
2323 "bus_clk", "iface_clk";
2324 clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
2325 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2326 <&clock_gcc GCC_SDCC1_APPS_CLK>,
2327 <&clock_gcc GCC_SDCC1_AHB_CLK>;
2328 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
2329 qcom,msm-bus,name = "sdcc_ice_noc";
2330 qcom,msm-bus,num-cases = <2>;
2331 qcom,msm-bus,num-paths = <1>;
2332 qcom,msm-bus,vectors-KBps =
2333 <150 512 0 0>, /* No vote */
2334 <150 512 1000 0>; /* Max. bandwidth */
2335 qcom,bus-vector-names = "MIN",
2336 "MAX";
2337 qcom,instance-type = "sdcc";
2338 };
2339
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2340 sdhc_1: sdhci@7c4000 {
2341 compatible = "qcom,sdhci-msm-v5";
2342 reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
2343 reg-names = "hc_mem", "cmdq_mem";
2344
2345 interrupts = <0 641 0>, <0 644 0>;
2346 interrupt-names = "hc_irq", "pwr_irq";
2347
2348 qcom,bus-width = <8>;
2349 qcom,large-address-bus;
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2350 sdhc-msm-crypto = <&sdcc1_ice>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2351
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2352 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2353 192000000 384000000>;
Vijay Viswanath01db23a2017-11-09 15:46:22 +0530[diff] [blame]2354 qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
2355 100000000 200000000 200000000>;
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2356 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2357
2358 qcom,devfreq,freq-table = <50000000 200000000>;
2359
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2360 qcom,msm-bus,name = "sdhc1";
2361 qcom,msm-bus,num-cases = <9>;
2362 qcom,msm-bus,num-paths = <2>;
2363 qcom,msm-bus,vectors-KBps =
2364 /* No vote */
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2365 <150 512 0 0>, <1 782 0 0>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2366 /* 400 KB/s*/
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2367 <150 512 1046 1600>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2368 <1 782 1600 1600>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2369 /* 20 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2370 <150 512 52286 80000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2371 <1 782 80000 80000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2372 /* 25 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2373 <150 512 65360 100000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2374 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2375 /* 50 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2376 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2377 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2378 /* 100 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2379 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2380 <1 782 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2381 /* 200 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2382 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2383 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2384 /* 400 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2385 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2386 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2387 /* Max. bandwidth */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2388 <150 512 1338562 4096000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2389 <1 782 1338562 4096000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2390 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2391 100000000 200000000 400000000 4294967295>;
2392
2393 /* PM QoS */
2394 qcom,pm-qos-irq-type = "affine_irq";
Vijay Viswanathcac6f862018-03-20 11:40:54 +0530[diff] [blame]2395 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2396 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2397 qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
2398 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2399
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2400 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2401 <&clock_gcc GCC_SDCC1_APPS_CLK>,
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2402 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]2403 <&clock_gcc UFS_PHY_AXI_EMMC_VOTE_CLK>;
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2404 clock-names = "iface_clk", "core_clk", "ice_core_clk",
2405 "bus_aggr_clk";
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2406
2407 qcom,ice-clk-rates = <300000000 75000000>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2408
Vijay Viswanathd4dcf5f2017-10-17 15:42:00 +0530[diff] [blame]2409 qcom,ddr-config = <0xC3040873>;
2410
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2411 qcom,nonremovable;
Asutosh Das3d37f972018-01-12 15:48:25 +0530[diff] [blame]2412 nvmem-cells = <&minor_rev>;
2413 nvmem-cell-names = "minor_rev";
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2414
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2415 status = "disabled";
2416 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2417
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2418 sdhc_2: sdhci@8804000 {
2419 compatible = "qcom,sdhci-msm-v5";
2420 reg = <0x8804000 0x1000>;
2421 reg-names = "hc_mem";
2422
2423 interrupts = <0 204 0>, <0 222 0>;
2424 interrupt-names = "hc_irq", "pwr_irq";
2425
2426 qcom,bus-width = <4>;
2427 qcom,large-address-bus;
2428
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2429 qcom,clk-rates = <400000 20000000 25000000
2430 50000000 100000000 201500000>;
2431 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2432 "SDR104";
2433
2434 qcom,devfreq,freq-table = <50000000 201500000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2435
2436 qcom,msm-bus,name = "sdhc2";
2437 qcom,msm-bus,num-cases = <8>;
2438 qcom,msm-bus,num-paths = <2>;
2439 qcom,msm-bus,vectors-KBps =
2440 /* No vote */
2441 <81 512 0 0>, <1 608 0 0>,
2442 /* 400 KB/s*/
2443 <81 512 1046 1600>,
2444 <1 608 1600 1600>,
2445 /* 20 MB/s */
2446 <81 512 52286 80000>,
2447 <1 608 80000 80000>,
2448 /* 25 MB/s */
2449 <81 512 65360 100000>,
2450 <1 608 100000 100000>,
2451 /* 50 MB/s */
2452 <81 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2453 <1 608 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2454 /* 100 MB/s */
2455 <81 512 261438 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2456 <1 608 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2457 /* 200 MB/s */
2458 <81 512 261438 400000>,
2459 <1 608 300000 300000>,
2460 /* Max. bandwidth */
2461 <81 512 1338562 4096000>,
2462 <1 608 1338562 4096000>;
2463 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2464 100000000 200000000 4294967295>;
2465
2466 /* PM QoS */
2467 qcom,pm-qos-irq-type = "affine_irq";
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2468 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2469 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2470 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2471
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2472 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
2473 <&clock_gcc GCC_SDCC2_APPS_CLK>;
2474 clock-names = "iface_clk", "core_clk";
2475
2476 status = "disabled";
2477 };
2478
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2479 qcom,msm-cdsp-loader {
2480 compatible = "qcom,cdsp-loader";
2481 qcom,proc-img-to-load = "cdsp";
2482 };
2483
2484 qcom,msm-adsprpc-mem {
2485 compatible = "qcom,msm-adsprpc-mem-region";
2486 memory-region = <&adsp_mem>;
Tharun Kumar Merugu8bb71292018-01-17 15:55:05 +0530[diff] [blame]2487 restrict-access;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2488 };
2489
2490 qcom,msm_fastrpc {
2491 compatible = "qcom,msm-fastrpc-compute";
Tharun Kumar Merugubbebad12017-12-21 16:33:03 +0530[diff] [blame]2492 qcom,adsp-remoteheap-vmid = <22 37>;
Tharun Kumar Merugu1cb19c62018-01-18 12:20:16 +0530[diff] [blame]2493 qcom,fastrpc-adsp-audio-pdr;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2494 qcom,fastrpc-adsp-sensors-pdr;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2495
2496 qcom,msm_fastrpc_compute_cb1 {
2497 compatible = "qcom,msm-fastrpc-compute-cb";
2498 label = "cdsprpc-smd";
2499 iommus = <&apps_smmu 0x1421 0x30>;
2500 dma-coherent;
2501 };
2502 qcom,msm_fastrpc_compute_cb2 {
2503 compatible = "qcom,msm-fastrpc-compute-cb";
2504 label = "cdsprpc-smd";
2505 iommus = <&apps_smmu 0x1422 0x30>;
2506 dma-coherent;
2507 };
2508 qcom,msm_fastrpc_compute_cb3 {
2509 compatible = "qcom,msm-fastrpc-compute-cb";
2510 label = "cdsprpc-smd";
2511 iommus = <&apps_smmu 0x1423 0x30>;
2512 dma-coherent;
2513 };
2514 qcom,msm_fastrpc_compute_cb4 {
2515 compatible = "qcom,msm-fastrpc-compute-cb";
2516 label = "cdsprpc-smd";
2517 iommus = <&apps_smmu 0x1424 0x30>;
2518 dma-coherent;
2519 };
2520 qcom,msm_fastrpc_compute_cb5 {
2521 compatible = "qcom,msm-fastrpc-compute-cb";
2522 label = "cdsprpc-smd";
2523 iommus = <&apps_smmu 0x1425 0x30>;
2524 dma-coherent;
2525 };
2526 qcom,msm_fastrpc_compute_cb6 {
2527 compatible = "qcom,msm-fastrpc-compute-cb";
2528 label = "cdsprpc-smd";
2529 iommus = <&apps_smmu 0x1426 0x30>;
2530 dma-coherent;
2531 };
2532 qcom,msm_fastrpc_compute_cb7 {
2533 compatible = "qcom,msm-fastrpc-compute-cb";
2534 label = "cdsprpc-smd";
2535 qcom,secure-context-bank;
2536 iommus = <&apps_smmu 0x1429 0x30>;
2537 dma-coherent;
2538 };
2539 qcom,msm_fastrpc_compute_cb8 {
2540 compatible = "qcom,msm-fastrpc-compute-cb";
2541 label = "cdsprpc-smd";
2542 qcom,secure-context-bank;
2543 iommus = <&apps_smmu 0x142A 0x30>;
2544 dma-coherent;
2545 };
2546 qcom,msm_fastrpc_compute_cb9 {
2547 compatible = "qcom,msm-fastrpc-compute-cb";
2548 label = "adsprpc-smd";
2549 iommus = <&apps_smmu 0x1803 0x0>;
2550 dma-coherent;
2551 };
2552 qcom,msm_fastrpc_compute_cb10 {
2553 compatible = "qcom,msm-fastrpc-compute-cb";
2554 label = "adsprpc-smd";
2555 iommus = <&apps_smmu 0x1804 0x0>;
2556 dma-coherent;
2557 };
2558 qcom,msm_fastrpc_compute_cb11 {
2559 compatible = "qcom,msm-fastrpc-compute-cb";
2560 label = "adsprpc-smd";
2561 iommus = <&apps_smmu 0x1805 0x0>;
2562 dma-coherent;
2563 };
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2564 qcom,msm_fastrpc_compute_cb12 {
2565 compatible = "qcom,msm-fastrpc-compute-cb";
2566 label = "adsprpc-smd";
2567 iommus = <&apps_smmu 0x1806 0x0>;
2568 dma-coherent;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2569 shared-cb;
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2570 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2571 };
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2572
Rupesh Tatiyaf2072952017-10-08 19:57:12 +0530[diff] [blame]2573 bluetooth: bt_wcn3990 {
2574 compatible = "qca,wcn3990";
2575 qca,bt-vdd-core-supply = <&pm660_l9>;
2576 qca,bt-vdd-pa-supply = <&pm660_l6>;
2577 qca,bt-vdd-ldo-supply = <&pm660_l19>;
2578
2579 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
2580 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
2581 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
2582
2583 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
2584 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
2585 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
2586 };
2587
Sarada Prasanna Garnayakd5ccc902018-02-22 15:54:50 +0530[diff] [blame]2588 icnss: qcom,icnss@18800000 {
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2589 compatible = "qcom,icnss";
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2590 reg = <0x18800000 0x800000>,
2591 <0xa0000000 0x10000000>,
2592 <0xb0000000 0x10000>;
2593 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
2594 iommus = <&apps_smmu 0x0040 0x1>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2595 interrupts = <0 414 0 /* CE0 */ >,
2596 <0 415 0 /* CE1 */ >,
2597 <0 416 0 /* CE2 */ >,
2598 <0 417 0 /* CE3 */ >,
2599 <0 418 0 /* CE4 */ >,
2600 <0 419 0 /* CE5 */ >,
2601 <0 420 0 /* CE6 */ >,
2602 <0 421 0 /* CE7 */ >,
2603 <0 422 0 /* CE8 */ >,
2604 <0 423 0 /* CE9 */ >,
2605 <0 424 0 /* CE10 */ >,
2606 <0 425 0 /* CE11 */ >;
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2607 vdd-0.8-cx-mx-supply = <&pm660_l5>;
2608 vdd-1.8-xo-supply = <&pm660_l9>;
2609 vdd-1.3-rfa-supply = <&pm660_l6>;
2610 vdd-3.3-ch0-supply = <&pm660_l19>;
Hardik Kantilal Patel25c05b42017-12-08 11:10:27 +0530[diff] [blame]2611 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2612 qcom,wlan-msa-memory = <0x100000>;
Anurag Chouhana4f55db2017-11-22 16:35:27 +0530[diff] [blame]2613 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
Hardik Kantilal Patel1697bd12018-03-05 14:46:29 +0530[diff] [blame]2614 qcom,gpio-force-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
2615 qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2616 qcom,smmu-s1-bypass;
2617 };
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2618
2619 cpubw: qcom,cpubw {
2620 compatible = "qcom,devbw";
2621 governor = "performance";
2622 qcom,src-dst-ports =
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2623 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2624 qcom,active-only;
2625 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2626 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2627 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2628 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2629 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2630 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2631 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2632 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2633 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2634 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2635 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2636 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2637 };
2638
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2639 bwmon: qcom,cpu-bwmon {
2640 compatible = "qcom,bimc-bwmon4";
2641 reg = <0x1436400 0x300>, <0x1436300 0x200>;
2642 reg-names = "base", "global_base";
2643 interrupts = <0 581 4>;
2644 qcom,mport = <0>;
Santosh Mardida0b0f82017-10-13 23:30:22 +0530[diff] [blame]2645 qcom,count-unit = <0x10000>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2646 qcom,hw-timer-hz = <19200000>;
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2647 qcom,target-dev = <&cpubw>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2648 };
2649
2650 memlat_cpu0: qcom,memlat-cpu0 {
2651 compatible = "qcom,devbw";
2652 governor = "powersave";
2653 qcom,src-dst-ports = <1 512>;
2654 qcom,active-only;
2655 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2656 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2657 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2658 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2659 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2660 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2661 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2662 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2663 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2664 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2665 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2666 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2667 };
2668
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2669 memlat_cpu6: qcom,memlat-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2670 compatible = "qcom,devbw";
2671 governor = "powersave";
2672 qcom,src-dst-ports = <1 512>;
2673 qcom,active-only;
2674 status = "ok";
2675 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2676 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2677 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2678 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2679 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2680 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2681 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2682 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2683 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2684 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2685 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2686 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2687 };
2688
Odelu Kukatlafe8d3302017-11-17 10:54:32 +0530[diff] [blame]2689 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
2690 compatible = "qcom,devbw";
2691 governor = "powersave";
2692 qcom,src-dst-ports = <139 627>;
2693 qcom,active-only;
2694 status = "ok";
2695 qcom,bw-tbl =
2696 < 1 >;
2697 };
2698
Odelu Kukatla95e7aea2018-02-27 15:46:39 +0530[diff] [blame]2699 bus_proxy_client: qcom,bus_proxy_client {
2700 compatible = "qcom,bus-proxy-client";
2701 qcom,msm-bus,name = "bus-proxy-client";
2702 qcom,msm-bus,num-cases = <2>;
2703 qcom,msm-bus,num-paths = <2>;
2704 qcom,msm-bus,vectors-KBps =
2705 <22 512 0 0>, <23 512 0 0>,
2706 <22 512 0 5000000>, <23 512 0 5000000>;
2707 qcom,msm-bus,active-only;
2708 status = "ok";
2709 };
2710
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2711 devfreq_memlat_0: qcom,cpu0-memlat-mon {
2712 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2713 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2714 qcom,target-dev = <&memlat_cpu0>;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2715 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2716 qcom,core-dev-table =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2717 < 748800 MHZ_TO_MBPS( 300, 4) >,
2718 < 998400 MHZ_TO_MBPS( 451, 4) >,
2719 < 1209600 MHZ_TO_MBPS( 547, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2720 < 1516800 MHZ_TO_MBPS( 768, 4) >,
2721 < 1708000 MHZ_TO_MBPS(1017, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2722 };
2723
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2724 devfreq_memlat_6: qcom,cpu6-memlat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2725 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2726 qcom,cpulist = <&CPU6 &CPU7>;
2727 qcom,target-dev = <&memlat_cpu6>;
2728 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2729 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2730 < 825600 MHZ_TO_MBPS( 300, 4) >,
2731 < 1132800 MHZ_TO_MBPS( 547, 4) >,
2732 < 1363200 MHZ_TO_MBPS(1017, 4) >,
2733 < 1996800 MHZ_TO_MBPS(1555, 4) >,
2734 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2735 };
2736
2737 l3_cpu0: qcom,l3-cpu0 {
2738 compatible = "devfreq-simple-dev";
2739 clock-names = "devfreq_clk";
2740 clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
2741 governor = "performance";
2742 };
2743
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2744 l3_cpu6: qcom,l3-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2745 compatible = "devfreq-simple-dev";
2746 clock-names = "devfreq_clk";
2747 clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
2748 governor = "performance";
2749 };
2750
2751 devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
2752 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2753 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2754 qcom,target-dev = <&l3_cpu0>;
2755 qcom,cachemiss-ev = <0x17>;
2756 qcom,core-dev-table =
Santosh Mardi10d45032017-11-02 17:25:54 +0530[diff] [blame]2757 < 576000 300000000 >,
Santosh Mardi831cc872018-01-11 14:52:32 +0530[diff] [blame]2758 < 998400 556800000 >,
2759 < 1209660 844800000 >,
2760 < 1516800 940800000 >,
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2761 < 1612800 1382400000 >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2762 < 1708000 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2763 };
2764
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2765 devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2766 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2767 qcom,cpulist = <&CPU6 &CPU7>;
2768 qcom,target-dev = <&l3_cpu6>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2769 qcom,cachemiss-ev = <0x17>;
2770 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2771 < 1132800 556800000 >,
2772 < 1363200 806400000 >,
2773 < 1747200 940800000 >,
2774 < 1996800 1190400000 >,
2775 < 2457600 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2776 };
2777
2778 mincpubw: qcom,mincpubw {
2779 compatible = "qcom,devbw";
2780 governor = "powersave";
2781 qcom,src-dst-ports = <1 512>;
2782 qcom,active-only;
2783 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2784 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2785 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2786 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2787 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2788 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2789 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2790 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2791 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2792 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2793 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2794 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2795 };
2796
2797 devfreq-cpufreq {
2798 mincpubw-cpufreq {
2799 target-dev = <&mincpubw>;
2800 cpu-to-dev-map-0 =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2801 < 748800 MHZ_TO_MBPS( 300, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2802 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2803 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2804 < 1708000 MHZ_TO_MBPS( 768, 4) >;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2805 cpu-to-dev-map-6 =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2806 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2807 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2808 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2809 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2810 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2811 };
2812 };
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2813
Jonathan Avilac7a6fd52017-10-12 15:24:05 -0700[diff] [blame]2814 mincpu0bw: qcom,mincpu0bw {
2815 compatible = "qcom,devbw";
2816 governor = "powersave";
2817 qcom,src-dst-ports = <1 512>;
2818 qcom,active-only;
2819 qcom,bw-tbl =
2820 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2821 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2822 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2823 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2824 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2825 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2826 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2827 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2828 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2829 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2830 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2831 };
2832
2833 mincpu6bw: qcom,mincpu6bw {
2834 compatible = "qcom,devbw";
2835 governor = "powersave";
2836 qcom,src-dst-ports = <1 512>;
2837 qcom,active-only;
2838 qcom,bw-tbl =
2839 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2840 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2841 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2842 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2843 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2844 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2845 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2846 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2847 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2848 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2849 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2850 };
2851
2852 devfreq_compute0: qcom,devfreq-compute0 {
2853 compatible = "qcom,arm-cpu-mon";
2854 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
2855 qcom,target-dev = <&mincpu0bw>;
2856 qcom,core-dev-table =
2857 < 748800 MHZ_TO_MBPS( 300, 4) >,
2858 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2859 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2860 < 1708000 MHZ_TO_MBPS( 768, 4) >;
2861 };
2862
2863 devfreq_compute6: qcom,devfreq-compute6 {
2864 compatible = "qcom,arm-cpu-mon";
2865 qcom,cpulist = <&CPU6 &CPU7>;
2866 qcom,target-dev = <&mincpu6bw>;
2867 qcom,core-dev-table =
2868 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2869 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2870 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2871 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2872 < 2457600 MHZ_TO_MBPS(1804, 4) >;
2873 };
2874
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]2875 l3_cdsp: qcom,l3-cdsp {
2876 compatible = "devfreq-simple-dev";
2877 clock-names = "devfreq_clk";
2878 clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;
2879 governor = "powersave";
2880 };
2881
Raghavendra Rao Ananta28dd4502017-10-18 10:28:31 -0700[diff] [blame]2882 cpu_pmu: cpu-pmu {
2883 compatible = "arm,armv8-pmuv3";
2884 qcom,irq-is-percpu;
2885 interrupts = <1 5 4>;
2886 };
2887
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2888 gpu_gx_domain_addr: syscon@0x5091508 {
2889 compatible = "syscon";
2890 reg = <0x5091508 0x4>;
2891 };
2892
2893 gpu_gx_sw_reset: syscon@0x5091008 {
2894 compatible = "syscon";
2895 reg = <0x5091008 0x4>;
2896 };
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2897
2898 qfprom: qfprom@0x780000 {
2899 compatible = "qcom,qfprom";
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2900 reg = <0x00784000 0x1000>;
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2901 #address-cells = <1>;
2902 #size-cells = <1>;
2903 ranges;
2904
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2905 minor_rev: minor_rev@0x78414c {
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2906 reg = <0x14c 0x4>;
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2907 bits = <0 30>; /* Access 30 bits from bit offset 0 */
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2908 };
2909 };
2910
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2911};
2912
Ashay Jaiswal81940302017-09-20 15:17:58 +0530[diff] [blame]2913#include "pm660.dtsi"
2914#include "pm660l.dtsi"
2915#include "sdm670-regulator.dtsi"
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2916#include "sdm670-pinctrl.dtsi"
Vijayanand Jittad48c4082017-06-07 15:07:51 +0530[diff] [blame]2917#include "msm-arm-smmu-sdm670.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2918#include "msm-gdsc-sdm845.dtsi"
Maulik Shahd313ea82017-06-14 13:10:52 +0530[diff] [blame]2919#include "sdm670-pm.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2920
2921&usb30_prim_gdsc {
2922 status = "ok";
2923};
2924
2925&ufs_phy_gdsc {
2926 status = "ok";
2927};
2928
2929&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
2930 status = "ok";
2931};
2932
2933&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
2934 status = "ok";
2935};
2936
2937&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
2938 status = "ok";
2939};
2940
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2941&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
2942 status = "ok";
2943};
2944
2945&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
2946 status = "ok";
2947};
2948
2949&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
2950 status = "ok";
2951};
2952
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2953&bps_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2954 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2955 status = "ok";
2956};
2957
2958&ife_0_gdsc {
2959 status = "ok";
2960};
2961
2962&ife_1_gdsc {
2963 status = "ok";
2964};
2965
2966&ipe_0_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2967 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2968 status = "ok";
2969};
2970
2971&ipe_1_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2972 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2973 status = "ok";
2974};
2975
2976&titan_top_gdsc {
2977 status = "ok";
2978};
2979
2980&mdss_core_gdsc {
2981 status = "ok";
Sandeep Pandaae888352017-11-15 13:15:31 +0530[diff] [blame]2982 proxy-supply = <&mdss_core_gdsc>;
2983 qcom,proxy-consumer-enable;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2984};
2985
2986&gpu_cx_gdsc {
Odelu Kukatla4abca302018-06-19 12:46:47 +0530[diff] [blame]2987 parent-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2988 status = "ok";
2989};
2990
2991&gpu_gx_gdsc {
2992 clock-names = "core_root_clk";
2993 clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
2994 qcom,force-enable-root-clk;
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2995 parent-supply = <&pm660l_s2_level>;
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2996 domain-addr = <&gpu_gx_domain_addr>;
2997 sw-reset = <&gpu_gx_sw_reset>;
2998 qcom,reset-aon-logic;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2999 status = "ok";
3000};
3001
3002&vcodec0_gdsc {
3003 qcom,support-hw-trigger;
3004 status = "ok";
3005};
3006
3007&vcodec1_gdsc {
3008 qcom,support-hw-trigger;
3009 status = "ok";
3010};
3011
3012&venus_gdsc {
3013 status = "ok";
3014};
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]3015
Sandeep Panda229db242017-10-03 11:32:29 +0530[diff] [blame]3016&mdss_dsi0 {
3017 qcom,core-supply-entries {
3018 #address-cells = <1>;
3019 #size-cells = <0>;
3020
3021 qcom,core-supply-entry@0 {
3022 reg = <0>;
3023 qcom,supply-name = "refgen";
3024 qcom,supply-min-voltage = <0>;
3025 qcom,supply-max-voltage = <0>;
3026 qcom,supply-enable-load = <0>;
3027 qcom,supply-disable-load = <0>;
3028 };
3029 };
3030};
3031
3032&mdss_dsi1 {
3033 qcom,core-supply-entries {
3034 #address-cells = <1>;
3035 #size-cells = <0>;
3036
3037 qcom,core-supply-entry@0 {
3038 reg = <0>;
3039 qcom,supply-name = "refgen";
3040 qcom,supply-min-voltage = <0>;
3041 qcom,supply-max-voltage = <0>;
3042 qcom,supply-enable-load = <0>;
3043 qcom,supply-disable-load = <0>;
3044 };
3045 };
3046};
3047
Padmanabhan Komanduru07137332017-10-20 12:53:23 +0530[diff] [blame]3048&sde_dp {
3049 qcom,core-supply-entries {
3050 #address-cells = <1>;
3051 #size-cells = <0>;
3052
3053 qcom,core-supply-entry@0 {
3054 reg = <0>;
3055 qcom,supply-name = "refgen";
3056 qcom,supply-min-voltage = <0>;
3057 qcom,supply-max-voltage = <0>;
3058 qcom,supply-enable-load = <0>;
3059 qcom,supply-disable-load = <0>;
3060 };
3061 };
3062};
3063
Rohit Kumar14051282017-07-12 11:18:48 +0530[diff] [blame]3064#include "sdm670-audio.dtsi"
Pratham Pratap9e420a32017-09-05 11:26:57 +0530[diff] [blame]3065#include "sdm670-usb.dtsi"
Rajesh Kemisettiba56c482017-08-31 18:12:35 +0530[diff] [blame]3066#include "sdm670-gpu.dtsi"
Suresh Vankadara402d0ca2017-10-26 22:54:54 +0530[diff] [blame]3067#include "sdm670-camera.dtsi"
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]3068#include "sdm670-thermal.dtsi"
Odelu Kukatlaf197e382017-07-04 19:47:35 +0530[diff] [blame]3069#include "sdm670-bus.dtsi"
Tirupathi Reddyf805ac72017-10-12 14:22:17 +0530[diff] [blame]3070
3071&pm660_div_clk {
3072 status = "ok";
3073};
Tirupathi Reddy53b92a62017-10-26 13:57:42 +0530[diff] [blame]3074
3075&qupv3_se10_i2c {
3076 nx30p6093: nx30p6093@36 {
3077 status = "disabled";
3078 compatible = "nxp,nx30p6093";
3079 reg = <0x36>;
3080 interrupt-parent = <&tlmm>;
3081 interrupts = <5 IRQ_TYPE_NONE>;
3082 nxp,long-wakeup-sec = <28800>; /* 8 hours */
3083 nxp,short-wakeup-ms = <180000>; /* 3 mins */
3084 pinctrl-names = "default";
3085 pinctrl-0 = <&nx30p6093_intr_default>;
3086 };
3087};