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gerrit-public.fairphone.software / kernel / msm-4.9 / 138e4e16f0e1d7dee8e6d0534147e15c0a3d94d5 / . / drivers / gpu / drm / radeon / r600.c
blob: 608926180e0c74fdb187cb2643563faedb54084c [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Tejun Heo5a0e3ad2010-03-24 17:04:11 +0900[diff] [blame]28#include <linux/slab.h>
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -0400[diff] [blame]32#include <linux/module.h>
David Howells760285e2012-10-02 18:01:07 +0100[diff] [blame]33#include <drm/drmP.h>
34#include <drm/radeon_drm.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +0000[diff] [blame]36#include "radeon_asic.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]37#include "radeon_mode.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]38#include "r600d.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]39#include "atom.h"
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]40#include "avivod.h"
Alex Deucher138e4e12013-01-11 15:33:13 -0500[diff] [blame^]41#include "radeon_ucode.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]42
43/* Firmware Names */
44MODULE_FIRMWARE("radeon/R600_pfp.bin");
45MODULE_FIRMWARE("radeon/R600_me.bin");
46MODULE_FIRMWARE("radeon/RV610_pfp.bin");
47MODULE_FIRMWARE("radeon/RV610_me.bin");
48MODULE_FIRMWARE("radeon/RV630_pfp.bin");
49MODULE_FIRMWARE("radeon/RV630_me.bin");
50MODULE_FIRMWARE("radeon/RV620_pfp.bin");
51MODULE_FIRMWARE("radeon/RV620_me.bin");
52MODULE_FIRMWARE("radeon/RV635_pfp.bin");
53MODULE_FIRMWARE("radeon/RV635_me.bin");
54MODULE_FIRMWARE("radeon/RV670_pfp.bin");
55MODULE_FIRMWARE("radeon/RV670_me.bin");
56MODULE_FIRMWARE("radeon/RS780_pfp.bin");
57MODULE_FIRMWARE("radeon/RS780_me.bin");
58MODULE_FIRMWARE("radeon/RV770_pfp.bin");
59MODULE_FIRMWARE("radeon/RV770_me.bin");
60MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61MODULE_FIRMWARE("radeon/RV730_me.bin");
62MODULE_FIRMWARE("radeon/RV710_pfp.bin");
63MODULE_FIRMWARE("radeon/RV710_me.bin");
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]64MODULE_FIRMWARE("radeon/R600_rlc.bin");
65MODULE_FIRMWARE("radeon/R700_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]66MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
67MODULE_FIRMWARE("radeon/CEDAR_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]68MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]69MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
70MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]71MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]72MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
73MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]74MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
Dave Airliea7433742010-04-09 15:31:09 +1000[diff] [blame]75MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]76MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]77MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
Alex Deucher439bd6c2010-11-22 17:56:31 -0500[diff] [blame]78MODULE_FIRMWARE("radeon/PALM_pfp.bin");
79MODULE_FIRMWARE("radeon/PALM_me.bin");
80MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
Alex Deucherd5c5a722011-05-31 15:42:48 -0400[diff] [blame]81MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
82MODULE_FIRMWARE("radeon/SUMO_me.bin");
83MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
84MODULE_FIRMWARE("radeon/SUMO2_me.bin");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]85
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]86static const u32 crtc_offsets[2] =
87{
88 0,
89 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
90};
91
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]92int r600_debugfs_mc_info_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]93
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]94/* r600,rv610,rv630,rv620,rv635,rv670 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]95int r600_mc_wait_for_idle(struct radeon_device *rdev);
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]96static void r600_gpu_init(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]97void r600_fini(struct radeon_device *rdev);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]98void r600_irq_disable(struct radeon_device *rdev);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]99static void r600_pcie_gen2_enable(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]100
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]101/**
102 * r600_get_xclk - get the xclk
103 *
104 * @rdev: radeon_device pointer
105 *
106 * Returns the reference clock used by the gfx engine
107 * (r6xx, IGPs, APUs).
108 */
109u32 r600_get_xclk(struct radeon_device *rdev)
110{
111 return rdev->clock.spll.reference_freq;
112}
113
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]114/* get temperature in millidegrees */
Alex Deucher20d391d2011-02-01 16:12:34 -0500[diff] [blame]115int rv6xx_get_temp(struct radeon_device *rdev)
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]116{
117 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
118 ASIC_T_SHIFT;
Alex Deucher20d391d2011-02-01 16:12:34 -0500[diff] [blame]119 int actual_temp = temp & 0xff;
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]120
Alex Deucher20d391d2011-02-01 16:12:34 -0500[diff] [blame]121 if (temp & 0x100)
122 actual_temp -= 256;
123
124 return actual_temp * 1000;
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]125}
126
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]127void r600_pm_get_dynpm_state(struct radeon_device *rdev)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]128{
129 int i;
130
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]131 rdev->pm.dynpm_can_upclock = true;
132 rdev->pm.dynpm_can_downclock = true;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]133
134 /* power state array is low to high, default is first */
135 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
136 int min_power_state_index = 0;
137
138 if (rdev->pm.num_power_states > 2)
139 min_power_state_index = 1;
140
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]141 switch (rdev->pm.dynpm_planned_action) {
142 case DYNPM_ACTION_MINIMUM:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]143 rdev->pm.requested_power_state_index = min_power_state_index;
144 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]145 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]146 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]147 case DYNPM_ACTION_DOWNCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]148 if (rdev->pm.current_power_state_index == min_power_state_index) {
149 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]150 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]151 } else {
152 if (rdev->pm.active_crtc_count > 1) {
153 for (i = 0; i < rdev->pm.num_power_states; i++) {
Alex Deucherd7311172010-05-03 01:13:14 -0400[diff] [blame]154 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]155 continue;
156 else if (i >= rdev->pm.current_power_state_index) {
157 rdev->pm.requested_power_state_index =
158 rdev->pm.current_power_state_index;
159 break;
160 } else {
161 rdev->pm.requested_power_state_index = i;
162 break;
163 }
164 }
Alex Deucher773c3fa2010-06-25 16:21:27 -0400[diff] [blame]165 } else {
166 if (rdev->pm.current_power_state_index == 0)
167 rdev->pm.requested_power_state_index =
168 rdev->pm.num_power_states - 1;
169 else
170 rdev->pm.requested_power_state_index =
171 rdev->pm.current_power_state_index - 1;
172 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]173 }
174 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherd7311172010-05-03 01:13:14 -0400[diff] [blame]175 /* don't use the power state if crtcs are active and no display flag is set */
176 if ((rdev->pm.active_crtc_count > 0) &&
177 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].flags &
179 RADEON_PM_MODE_NO_DISPLAY)) {
180 rdev->pm.requested_power_state_index++;
181 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]182 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]183 case DYNPM_ACTION_UPCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]184 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
185 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]186 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]187 } else {
188 if (rdev->pm.active_crtc_count > 1) {
189 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
Alex Deucherd7311172010-05-03 01:13:14 -0400[diff] [blame]190 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]191 continue;
192 else if (i <= rdev->pm.current_power_state_index) {
193 rdev->pm.requested_power_state_index =
194 rdev->pm.current_power_state_index;
195 break;
196 } else {
197 rdev->pm.requested_power_state_index = i;
198 break;
199 }
200 }
201 } else
202 rdev->pm.requested_power_state_index =
203 rdev->pm.current_power_state_index + 1;
204 }
205 rdev->pm.requested_clock_mode_index = 0;
206 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]207 case DYNPM_ACTION_DEFAULT:
Alex Deucher58e21df2010-03-22 13:31:08 -0400[diff] [blame]208 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
209 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]210 rdev->pm.dynpm_can_upclock = false;
Alex Deucher58e21df2010-03-22 13:31:08 -0400[diff] [blame]211 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]212 case DYNPM_ACTION_NONE:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]213 default:
214 DRM_ERROR("Requested mode for not defined action\n");
215 return;
216 }
217 } else {
218 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
219 /* for now just select the first power state and switch between clock modes */
220 /* power state array is low to high, default is first (0) */
221 if (rdev->pm.active_crtc_count > 1) {
222 rdev->pm.requested_power_state_index = -1;
223 /* start at 1 as we don't want the default mode */
224 for (i = 1; i < rdev->pm.num_power_states; i++) {
Alex Deucherd7311172010-05-03 01:13:14 -0400[diff] [blame]225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]226 continue;
227 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
228 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
229 rdev->pm.requested_power_state_index = i;
230 break;
231 }
232 }
233 /* if nothing selected, grab the default state. */
234 if (rdev->pm.requested_power_state_index == -1)
235 rdev->pm.requested_power_state_index = 0;
236 } else
237 rdev->pm.requested_power_state_index = 1;
238
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]239 switch (rdev->pm.dynpm_planned_action) {
240 case DYNPM_ACTION_MINIMUM:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]241 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]242 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]243 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]244 case DYNPM_ACTION_DOWNCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]245 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
246 if (rdev->pm.current_clock_mode_index == 0) {
247 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]248 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]249 } else
250 rdev->pm.requested_clock_mode_index =
251 rdev->pm.current_clock_mode_index - 1;
252 } else {
253 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]254 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]255 }
Alex Deucherd7311172010-05-03 01:13:14 -0400[diff] [blame]256 /* don't use the power state if crtcs are active and no display flag is set */
257 if ((rdev->pm.active_crtc_count > 0) &&
258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
259 clock_info[rdev->pm.requested_clock_mode_index].flags &
260 RADEON_PM_MODE_NO_DISPLAY)) {
261 rdev->pm.requested_clock_mode_index++;
262 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]263 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]264 case DYNPM_ACTION_UPCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]265 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
266 if (rdev->pm.current_clock_mode_index ==
267 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
268 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]269 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]270 } else
271 rdev->pm.requested_clock_mode_index =
272 rdev->pm.current_clock_mode_index + 1;
273 } else {
274 rdev->pm.requested_clock_mode_index =
275 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]276 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]277 }
278 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]279 case DYNPM_ACTION_DEFAULT:
Alex Deucher58e21df2010-03-22 13:31:08 -0400[diff] [blame]280 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
281 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]282 rdev->pm.dynpm_can_upclock = false;
Alex Deucher58e21df2010-03-22 13:31:08 -0400[diff] [blame]283 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]284 case DYNPM_ACTION_NONE:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]285 default:
286 DRM_ERROR("Requested mode for not defined action\n");
287 return;
288 }
289 }
290
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000[diff] [blame]291 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
Alex Deucherce8a3eb2010-05-07 16:58:27 -0400[diff] [blame]292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].sclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
295 clock_info[rdev->pm.requested_clock_mode_index].mclk,
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 pcie_lanes);
Alex Deuchera48b9b42010-04-22 14:03:55 -0400[diff] [blame]298}
299
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]300void rs780_pm_init_profile(struct radeon_device *rdev)
301{
302 if (rdev->pm.num_power_states == 2) {
303 /* default */
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
308 /* low sh */
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]313 /* mid sh */
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]318 /* high sh */
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
323 /* low mh */
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]328 /* mid mh */
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]333 /* high mh */
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
338 } else if (rdev->pm.num_power_states == 3) {
339 /* default */
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
342 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
344 /* low sh */
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]349 /* mid sh */
350 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]354 /* high sh */
355 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
357 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
359 /* low mh */
360 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]364 /* mid mh */
365 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
367 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]369 /* high mh */
370 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
372 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
373 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
374 } else {
375 /* default */
376 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
378 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
380 /* low sh */
381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]385 /* mid sh */
386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]390 /* high sh */
391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
393 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
395 /* low mh */
396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]400 /* mid mh */
401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
403 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]405 /* high mh */
406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
408 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
409 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
410 }
411}
412
413void r600_pm_init_profile(struct radeon_device *rdev)
414{
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]415 int idx;
416
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]417 if (rdev->family == CHIP_R600) {
418 /* XXX */
419 /* default */
420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
422 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]423 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]424 /* low sh */
425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]428 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]429 /* mid sh */
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
433 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]434 /* high sh */
435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
436 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]438 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]439 /* low mh */
440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
441 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]443 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]444 /* mid mh */
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
446 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
448 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]449 /* high mh */
450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]453 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]454 } else {
455 if (rdev->pm.num_power_states < 4) {
456 /* default */
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
460 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
461 /* low sh */
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
463 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
464 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]465 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
466 /* mid sh */
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
468 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
469 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
470 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]471 /* high sh */
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
473 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
476 /* low mh */
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
478 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]479 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]480 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
481 /* low mh */
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
485 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]486 /* high mh */
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
488 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
490 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
491 } else {
492 /* default */
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
494 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
495 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
497 /* low sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]498 if (rdev->flags & RADEON_IS_MOBILITY)
499 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
500 else
501 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
504 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]506 /* mid sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]507 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
509 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
510 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]511 /* high sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
514 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]515 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
516 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
517 /* low mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]518 if (rdev->flags & RADEON_IS_MOBILITY)
519 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
520 else
521 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
523 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
525 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400[diff] [blame]526 /* mid mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]527 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
528 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
529 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
530 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
Alex Deucher4bff5172010-05-17 19:41:26 -0400[diff] [blame]531 /* high mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400[diff] [blame]532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
533 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
534 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]535 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
537 }
538 }
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]539}
540
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]541void r600_pm_misc(struct radeon_device *rdev)
542{
Rafał Miłeckia081a9d2010-06-07 18:20:25 -0400[diff] [blame]543 int req_ps_idx = rdev->pm.requested_power_state_index;
544 int req_cm_idx = rdev->pm.requested_clock_mode_index;
545 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
546 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
Alex Deucher7ac9aa52010-05-27 19:25:54 -0400[diff] [blame]547
Alex Deucher4d601732010-06-07 18:15:18 -0400[diff] [blame]548 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
Alex Deuchera377e182011-06-20 13:00:31 -0400[diff] [blame]549 /* 0xff01 is a flag rather then an actual voltage */
550 if (voltage->voltage == 0xff01)
551 return;
Alex Deucher4d601732010-06-07 18:15:18 -0400[diff] [blame]552 if (voltage->voltage != rdev->pm.current_vddc) {
Alex Deucher8a83ec52011-04-12 14:49:23 -0400[diff] [blame]553 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
Alex Deucher4d601732010-06-07 18:15:18 -0400[diff] [blame]554 rdev->pm.current_vddc = voltage->voltage;
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000[diff] [blame]555 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
Alex Deucher4d601732010-06-07 18:15:18 -0400[diff] [blame]556 }
557 }
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]558}
559
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]560bool r600_gui_idle(struct radeon_device *rdev)
561{
562 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
563 return false;
564 else
565 return true;
566}
567
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]568/* hpd for digital panel detect/disconnect */
569bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
570{
571 bool connected = false;
572
573 if (ASIC_IS_DCE3(rdev)) {
574 switch (hpd) {
575 case RADEON_HPD_1:
576 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_2:
580 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 case RADEON_HPD_3:
584 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
585 connected = true;
586 break;
587 case RADEON_HPD_4:
588 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
589 connected = true;
590 break;
591 /* DCE 3.2 */
592 case RADEON_HPD_5:
593 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
594 connected = true;
595 break;
596 case RADEON_HPD_6:
597 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
598 connected = true;
599 break;
600 default:
601 break;
602 }
603 } else {
604 switch (hpd) {
605 case RADEON_HPD_1:
606 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 case RADEON_HPD_2:
610 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
611 connected = true;
612 break;
613 case RADEON_HPD_3:
614 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
615 connected = true;
616 break;
617 default:
618 break;
619 }
620 }
621 return connected;
622}
623
624void r600_hpd_set_polarity(struct radeon_device *rdev,
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]625 enum radeon_hpd_id hpd)
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]626{
627 u32 tmp;
628 bool connected = r600_hpd_sense(rdev, hpd);
629
630 if (ASIC_IS_DCE3(rdev)) {
631 switch (hpd) {
632 case RADEON_HPD_1:
633 tmp = RREG32(DC_HPD1_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD1_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_2:
641 tmp = RREG32(DC_HPD2_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD2_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_3:
649 tmp = RREG32(DC_HPD3_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD3_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_4:
657 tmp = RREG32(DC_HPD4_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD4_INT_CONTROL, tmp);
663 break;
664 case RADEON_HPD_5:
665 tmp = RREG32(DC_HPD5_INT_CONTROL);
666 if (connected)
667 tmp &= ~DC_HPDx_INT_POLARITY;
668 else
669 tmp |= DC_HPDx_INT_POLARITY;
670 WREG32(DC_HPD5_INT_CONTROL, tmp);
671 break;
672 /* DCE 3.2 */
673 case RADEON_HPD_6:
674 tmp = RREG32(DC_HPD6_INT_CONTROL);
675 if (connected)
676 tmp &= ~DC_HPDx_INT_POLARITY;
677 else
678 tmp |= DC_HPDx_INT_POLARITY;
679 WREG32(DC_HPD6_INT_CONTROL, tmp);
680 break;
681 default:
682 break;
683 }
684 } else {
685 switch (hpd) {
686 case RADEON_HPD_1:
687 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_2:
695 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
701 break;
702 case RADEON_HPD_3:
703 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
704 if (connected)
705 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
706 else
707 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
708 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
709 break;
710 default:
711 break;
712 }
713 }
714}
715
716void r600_hpd_init(struct radeon_device *rdev)
717{
718 struct drm_device *dev = rdev->ddev;
719 struct drm_connector *connector;
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]720 unsigned enable = 0;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]721
Alex Deucher64912e92011-11-03 11:21:39 -0400[diff] [blame]722 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
723 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]724
Jerome Glisse455c89b2012-05-04 11:06:22 -0400[diff] [blame]725 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
726 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
727 /* don't try to enable hpd on eDP or LVDS avoid breaking the
728 * aux dp channel on imac and help (but not completely fix)
729 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
730 */
731 continue;
732 }
Alex Deucher64912e92011-11-03 11:21:39 -0400[diff] [blame]733 if (ASIC_IS_DCE3(rdev)) {
734 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
735 if (ASIC_IS_DCE32(rdev))
736 tmp |= DC_HPDx_EN;
737
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]738 switch (radeon_connector->hpd.hpd) {
739 case RADEON_HPD_1:
740 WREG32(DC_HPD1_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]741 break;
742 case RADEON_HPD_2:
743 WREG32(DC_HPD2_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]744 break;
745 case RADEON_HPD_3:
746 WREG32(DC_HPD3_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]747 break;
748 case RADEON_HPD_4:
749 WREG32(DC_HPD4_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]750 break;
751 /* DCE 3.2 */
752 case RADEON_HPD_5:
753 WREG32(DC_HPD5_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]754 break;
755 case RADEON_HPD_6:
756 WREG32(DC_HPD6_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]757 break;
758 default:
759 break;
760 }
Alex Deucher64912e92011-11-03 11:21:39 -0400[diff] [blame]761 } else {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]762 switch (radeon_connector->hpd.hpd) {
763 case RADEON_HPD_1:
764 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]765 break;
766 case RADEON_HPD_2:
767 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]768 break;
769 case RADEON_HPD_3:
770 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]771 break;
772 default:
773 break;
774 }
775 }
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]776 enable |= 1 << radeon_connector->hpd.hpd;
Alex Deucher64912e92011-11-03 11:21:39 -0400[diff] [blame]777 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]778 }
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]779 radeon_irq_kms_enable_hpd(rdev, enable);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]780}
781
782void r600_hpd_fini(struct radeon_device *rdev)
783{
784 struct drm_device *dev = rdev->ddev;
785 struct drm_connector *connector;
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]786 unsigned disable = 0;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]787
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]788 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
789 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
790 if (ASIC_IS_DCE3(rdev)) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]791 switch (radeon_connector->hpd.hpd) {
792 case RADEON_HPD_1:
793 WREG32(DC_HPD1_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]794 break;
795 case RADEON_HPD_2:
796 WREG32(DC_HPD2_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]797 break;
798 case RADEON_HPD_3:
799 WREG32(DC_HPD3_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]800 break;
801 case RADEON_HPD_4:
802 WREG32(DC_HPD4_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]803 break;
804 /* DCE 3.2 */
805 case RADEON_HPD_5:
806 WREG32(DC_HPD5_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]807 break;
808 case RADEON_HPD_6:
809 WREG32(DC_HPD6_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]810 break;
811 default:
812 break;
813 }
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]814 } else {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]815 switch (radeon_connector->hpd.hpd) {
816 case RADEON_HPD_1:
817 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]818 break;
819 case RADEON_HPD_2:
820 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]821 break;
822 case RADEON_HPD_3:
823 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]824 break;
825 default:
826 break;
827 }
828 }
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]829 disable |= 1 << radeon_connector->hpd.hpd;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]830 }
Christian Koenigfb982572012-05-17 01:33:30 +0200[diff] [blame]831 radeon_irq_kms_disable_hpd(rdev, disable);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]832}
833
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]834/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]835 * R600 PCIE GART
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]836 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]837void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]838{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]839 unsigned i;
840 u32 tmp;
841
Dave Airlie2e98f102010-02-15 15:54:45 +1000[diff] [blame]842 /* flush hdp cache so updates hit vram */
Alex Deucherf3886f82010-12-08 10:05:34 -0500[diff] [blame]843 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
844 !(rdev->flags & RADEON_IS_AGP)) {
Jerome Glissec9a1be92011-11-03 11:16:49 -0400[diff] [blame]845 void __iomem *ptr = (void *)rdev->gart.ptr;
Alex Deucher812d0462010-07-26 18:51:53 -0400[diff] [blame]846 u32 tmp;
847
848 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
849 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
Alex Deucherf3886f82010-12-08 10:05:34 -0500[diff] [blame]850 * This seems to cause problems on some AGP cards. Just use the old
851 * method for them.
Alex Deucher812d0462010-07-26 18:51:53 -0400[diff] [blame]852 */
853 WREG32(HDP_DEBUG1, 0);
854 tmp = readl((void __iomem *)ptr);
855 } else
856 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
Dave Airlie2e98f102010-02-15 15:54:45 +1000[diff] [blame]857
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]858 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
859 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
860 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
861 for (i = 0; i < rdev->usec_timeout; i++) {
862 /* read MC_STATUS */
863 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
864 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
865 if (tmp == 2) {
866 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
867 return;
868 }
869 if (tmp) {
870 return;
871 }
872 udelay(1);
873 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]874}
875
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]876int r600_pcie_gart_init(struct radeon_device *rdev)
877{
878 int r;
879
Jerome Glissec9a1be92011-11-03 11:16:49 -0400[diff] [blame]880 if (rdev->gart.robj) {
Joe Perchesfce7d612010-10-30 21:08:30 +0000[diff] [blame]881 WARN(1, "R600 PCIE GART already initialized\n");
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]882 return 0;
883 }
884 /* Initialize common gart structure */
885 r = radeon_gart_init(rdev);
886 if (r)
887 return r;
888 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
889 return radeon_gart_table_vram_alloc(rdev);
890}
891
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]892static int r600_pcie_gart_enable(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]893{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]894 u32 tmp;
895 int r, i;
896
Jerome Glissec9a1be92011-11-03 11:16:49 -0400[diff] [blame]897 if (rdev->gart.robj == NULL) {
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]898 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899 return -EINVAL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]900 }
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]901 r = radeon_gart_table_vram_pin(rdev);
902 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]903 return r;
Dave Airlie82568562010-02-05 16:00:07 +1000[diff] [blame]904 radeon_gart_restore(rdev);
Dave Airliebc1a6312009-09-15 11:07:52 +1000[diff] [blame]905
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]906 /* Setup L2 cache */
907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
908 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
909 EFFECTIVE_L2_QUEUE_SIZE(7));
910 WREG32(VM_L2_CNTL2, 0);
911 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
912 /* Setup TLB control */
913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
914 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
915 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
916 ENABLE_WAIT_L2_QUERY;
917 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
920 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
922 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
923 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
926 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
930 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
931 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]932 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]933 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
934 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
935 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
936 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
937 (u32)(rdev->dummy_page.addr >> 12));
938 for (i = 1; i < 7; i++)
939 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
940
941 r600_pcie_gart_tlb_flush(rdev);
Tormod Voldenfcf4de52011-08-31 21:54:07 +0000[diff] [blame]942 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
943 (unsigned)(rdev->mc.gtt_size >> 20),
944 (unsigned long long)rdev->gart.table_addr);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]945 rdev->gart.ready = true;
946 return 0;
947}
948
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]949static void r600_pcie_gart_disable(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]950{
951 u32 tmp;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400[diff] [blame]952 int i;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]953
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]954 /* Disable all tables */
955 for (i = 0; i < 7; i++)
956 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
957
958 /* Disable L2 cache */
959 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
960 EFFECTIVE_L2_QUEUE_SIZE(7));
961 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
962 /* Setup L1 TLB control */
963 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
964 ENABLE_WAIT_L2_QUERY;
965 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400[diff] [blame]979 radeon_gart_table_vram_unpin(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]980}
981
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]982static void r600_pcie_gart_fini(struct radeon_device *rdev)
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]983{
Jerome Glissef9274562010-03-17 14:44:29 +0000[diff] [blame]984 radeon_gart_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]985 r600_pcie_gart_disable(rdev);
986 radeon_gart_table_vram_free(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]987}
988
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]989static void r600_agp_enable(struct radeon_device *rdev)
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]990{
991 u32 tmp;
992 int i;
993
994 /* Setup L2 cache */
995 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
996 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
997 EFFECTIVE_L2_QUEUE_SIZE(7));
998 WREG32(VM_L2_CNTL2, 0);
999 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000 /* Setup TLB control */
1001 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1002 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1003 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1004 ENABLE_WAIT_L2_QUERY;
1005 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1018 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1019 for (i = 0; i < 7; i++)
1020 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1021}
1022
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1023int r600_mc_wait_for_idle(struct radeon_device *rdev)
1024{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1025 unsigned i;
1026 u32 tmp;
1027
1028 for (i = 0; i < rdev->usec_timeout; i++) {
1029 /* read MC_STATUS */
1030 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1031 if (!tmp)
1032 return 0;
1033 udelay(1);
1034 }
1035 return -1;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1036}
1037
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]1038uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1039{
1040 uint32_t r;
1041
1042 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1043 r = RREG32(R_0028FC_MC_DATA);
1044 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1045 return r;
1046}
1047
1048void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1049{
1050 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1051 S_0028F8_MC_IND_WR_EN(1));
1052 WREG32(R_0028FC_MC_DATA, v);
1053 WREG32(R_0028F8_MC_INDEX, 0x7F);
1054}
1055
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1056static void r600_mc_program(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1057{
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1058 struct rv515_mc_save save;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1059 u32 tmp;
1060 int i, j;
1061
1062 /* Initialize HDP */
1063 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1064 WREG32((0x2c14 + j), 0x00000000);
1065 WREG32((0x2c18 + j), 0x00000000);
1066 WREG32((0x2c1c + j), 0x00000000);
1067 WREG32((0x2c20 + j), 0x00000000);
1068 WREG32((0x2c24 + j), 0x00000000);
1069 }
1070 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1071
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1072 rv515_mc_stop(rdev, &save);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1073 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1074 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1075 }
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1076 /* Lockout access through VGA aperture (doesn't exist before R600) */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1077 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1078 /* Update configuration */
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]1079 if (rdev->flags & RADEON_IS_AGP) {
1080 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1081 /* VRAM before AGP */
1082 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1083 rdev->mc.vram_start >> 12);
1084 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1085 rdev->mc.gtt_end >> 12);
1086 } else {
1087 /* VRAM after AGP */
1088 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1089 rdev->mc.gtt_start >> 12);
1090 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1091 rdev->mc.vram_end >> 12);
1092 }
1093 } else {
1094 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1095 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1096 }
Alex Deucher16cdf042011-10-28 10:30:02 -0400[diff] [blame]1097 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]1098 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1099 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1100 WREG32(MC_VM_FB_LOCATION, tmp);
1101 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1102 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
Jerome Glisse46fcd2b2010-06-03 19:34:48 +0200[diff] [blame]1103 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1104 if (rdev->flags & RADEON_IS_AGP) {
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]1105 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1106 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1107 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1108 } else {
1109 WREG32(MC_VM_AGP_BASE, 0);
1110 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1111 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1112 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1113 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1114 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1115 }
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1116 rv515_mc_resume(rdev, &save);
Dave Airlie698443d2009-09-18 14:16:38 +1000[diff] [blame]1117 /* we need to own VRAM, so turn off the VGA renderer here
1118 * to stop it overwriting our objects */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]1119 rv515_vga_render_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1120}
1121
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1122/**
1123 * r600_vram_gtt_location - try to find VRAM & GTT location
1124 * @rdev: radeon device structure holding all necessary informations
1125 * @mc: memory controller structure holding memory informations
1126 *
1127 * Function will place try to place VRAM at same place as in CPU (PCI)
1128 * address space as some GPU seems to have issue when we reprogram at
1129 * different address space.
1130 *
1131 * If there is not enough space to fit the unvisible VRAM after the
1132 * aperture then we limit the VRAM size to the aperture.
1133 *
1134 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1135 * them to be in one from GPU point of view so that we can program GPU to
1136 * catch access outside them (weird GPU policy see ??).
1137 *
1138 * This function will never fails, worst case are limiting VRAM or GTT.
1139 *
1140 * Note: GTT start, end, size should be initialized before calling this
1141 * function on AGP platform.
1142 */
Alex Deucher0ef0c1f2010-11-22 17:56:26 -0500[diff] [blame]1143static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1144{
1145 u64 size_bf, size_af;
1146
1147 if (mc->mc_vram_size > 0xE0000000) {
1148 /* leave room for at least 512M GTT */
1149 dev_warn(rdev->dev, "limiting VRAM\n");
1150 mc->real_vram_size = 0xE0000000;
1151 mc->mc_vram_size = 0xE0000000;
1152 }
1153 if (rdev->flags & RADEON_IS_AGP) {
1154 size_bf = mc->gtt_start;
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400[diff] [blame]1155 size_af = mc->mc_mask - mc->gtt_end;
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1156 if (size_bf > size_af) {
1157 if (mc->mc_vram_size > size_bf) {
1158 dev_warn(rdev->dev, "limiting VRAM\n");
1159 mc->real_vram_size = size_bf;
1160 mc->mc_vram_size = size_bf;
1161 }
1162 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1163 } else {
1164 if (mc->mc_vram_size > size_af) {
1165 dev_warn(rdev->dev, "limiting VRAM\n");
1166 mc->real_vram_size = size_af;
1167 mc->mc_vram_size = size_af;
1168 }
Jerome Glissedfc6ae52012-04-17 16:51:38 -0400[diff] [blame]1169 mc->vram_start = mc->gtt_end + 1;
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1170 }
1171 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1172 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1173 mc->mc_vram_size >> 20, mc->vram_start,
1174 mc->vram_end, mc->real_vram_size >> 20);
1175 } else {
1176 u64 base = 0;
Alex Deucher8961d522010-12-03 14:37:22 -0500[diff] [blame]1177 if (rdev->flags & RADEON_IS_IGP) {
1178 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1179 base <<= 24;
1180 }
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1181 radeon_vram_location(rdev, &rdev->mc, base);
Alex Deucher8d369bb2010-07-15 10:51:10 -0400[diff] [blame]1182 rdev->mc.gtt_base_align = 0;
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1183 radeon_gtt_location(rdev, mc);
1184 }
1185}
1186
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]1187static int r600_mc_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1188{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1189 u32 tmp;
Alex Deucher5885b7a2009-10-19 17:23:33 -0400[diff] [blame]1190 int chansize, numchan;
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]1191 uint32_t h_addr, l_addr;
1192 unsigned long long k8_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1193
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1194 /* Get VRAM informations */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1195 rdev->mc.vram_is_ddr = true;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1196 tmp = RREG32(RAMCFG);
1197 if (tmp & CHANSIZE_OVERRIDE) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1198 chansize = 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1199 } else if (tmp & CHANSIZE_MASK) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1200 chansize = 64;
1201 } else {
1202 chansize = 32;
1203 }
Alex Deucher5885b7a2009-10-19 17:23:33 -0400[diff] [blame]1204 tmp = RREG32(CHMAP);
1205 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1206 case 0:
1207 default:
1208 numchan = 1;
1209 break;
1210 case 1:
1211 numchan = 2;
1212 break;
1213 case 2:
1214 numchan = 4;
1215 break;
1216 case 3:
1217 numchan = 8;
1218 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1219 }
Alex Deucher5885b7a2009-10-19 17:23:33 -0400[diff] [blame]1220 rdev->mc.vram_width = numchan * chansize;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1221 /* Could aper size report 0 ? */
Jordan Crouse01d73a62010-05-27 13:40:24 -0600[diff] [blame]1222 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1223 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1224 /* Setup GPU memory space */
1225 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1226 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +0000[diff] [blame]1227 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000[diff] [blame]1228 r600_vram_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -0400[diff] [blame]1229
Alex Deucherf8920342010-06-30 12:02:03 -0400[diff] [blame]1230 if (rdev->flags & RADEON_IS_IGP) {
1231 rs690_pm_info(rdev);
Alex Deucher06b64762010-01-05 11:27:29 -0500[diff] [blame]1232 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]1233
1234 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1235 /* Use K8 direct mapping for fast fb access. */
1236 rdev->fastfb_working = false;
1237 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1238 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1239 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1240#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1241 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1242#endif
1243 {
1244 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1245 * memory is present.
1246 */
1247 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1248 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1249 (unsigned long long)rdev->mc.aper_base, k8_addr);
1250 rdev->mc.aper_base = (resource_size_t)k8_addr;
1251 rdev->fastfb_working = true;
1252 }
1253 }
1254 }
Alex Deucherf8920342010-06-30 12:02:03 -0400[diff] [blame]1255 }
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]1256
Alex Deucherf47299c2010-03-16 20:54:38 -0400[diff] [blame]1257 radeon_update_bandwidth_info(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1258 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1259}
1260
Alex Deucher16cdf042011-10-28 10:30:02 -0400[diff] [blame]1261int r600_vram_scratch_init(struct radeon_device *rdev)
1262{
1263 int r;
1264
1265 if (rdev->vram_scratch.robj == NULL) {
1266 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1267 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400[diff] [blame]1268 NULL, &rdev->vram_scratch.robj);
Alex Deucher16cdf042011-10-28 10:30:02 -0400[diff] [blame]1269 if (r) {
1270 return r;
1271 }
1272 }
1273
1274 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1275 if (unlikely(r != 0))
1276 return r;
1277 r = radeon_bo_pin(rdev->vram_scratch.robj,
1278 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1279 if (r) {
1280 radeon_bo_unreserve(rdev->vram_scratch.robj);
1281 return r;
1282 }
1283 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1284 (void **)&rdev->vram_scratch.ptr);
1285 if (r)
1286 radeon_bo_unpin(rdev->vram_scratch.robj);
1287 radeon_bo_unreserve(rdev->vram_scratch.robj);
1288
1289 return r;
1290}
1291
1292void r600_vram_scratch_fini(struct radeon_device *rdev)
1293{
1294 int r;
1295
1296 if (rdev->vram_scratch.robj == NULL) {
1297 return;
1298 }
1299 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1300 if (likely(r == 0)) {
1301 radeon_bo_kunmap(rdev->vram_scratch.robj);
1302 radeon_bo_unpin(rdev->vram_scratch.robj);
1303 radeon_bo_unreserve(rdev->vram_scratch.robj);
1304 }
1305 radeon_bo_unref(&rdev->vram_scratch.robj);
1306}
1307
Alex Deucher410a3412013-01-18 13:05:39 -0500[diff] [blame]1308void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1309{
1310 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1311
1312 if (hung)
1313 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1314 else
1315 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1316
1317 WREG32(R600_BIOS_3_SCRATCH, tmp);
1318}
1319
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1320static void r600_print_gpu_status_regs(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1321{
Jerome Glisse64c56e82013-01-02 17:30:35 -0500[diff] [blame]1322 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1323 RREG32(R_008010_GRBM_STATUS));
Jerome Glisse64c56e82013-01-02 17:30:35 -0500[diff] [blame]1324 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1325 RREG32(R_008014_GRBM_STATUS2));
Jerome Glisse64c56e82013-01-02 17:30:35 -0500[diff] [blame]1326 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1327 RREG32(R_000E50_SRBM_STATUS));
Jerome Glisse440a7cd2012-06-27 12:25:01 -0400[diff] [blame]1328 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1329 RREG32(CP_STALLED_STAT1));
Jerome Glisse440a7cd2012-06-27 12:25:01 -0400[diff] [blame]1330 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1331 RREG32(CP_STALLED_STAT2));
Jerome Glisse440a7cd2012-06-27 12:25:01 -0400[diff] [blame]1332 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1333 RREG32(CP_BUSY_STAT));
Jerome Glisse440a7cd2012-06-27 12:25:01 -0400[diff] [blame]1334 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1335 RREG32(CP_STAT));
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1336 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1337 RREG32(DMA_STATUS_REG));
1338}
1339
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1340static bool r600_is_display_hung(struct radeon_device *rdev)
1341{
1342 u32 crtc_hung = 0;
1343 u32 crtc_status[2];
1344 u32 i, j, tmp;
1345
1346 for (i = 0; i < rdev->num_crtc; i++) {
1347 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1348 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1349 crtc_hung |= (1 << i);
1350 }
1351 }
1352
1353 for (j = 0; j < 10; j++) {
1354 for (i = 0; i < rdev->num_crtc; i++) {
1355 if (crtc_hung & (1 << i)) {
1356 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1357 if (tmp != crtc_status[i])
1358 crtc_hung &= ~(1 << i);
1359 }
1360 }
1361 if (crtc_hung == 0)
1362 return false;
1363 udelay(100);
1364 }
1365
1366 return true;
1367}
1368
1369static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1370{
1371 u32 reset_mask = 0;
1372 u32 tmp;
1373
1374 /* GRBM_STATUS */
1375 tmp = RREG32(R_008010_GRBM_STATUS);
1376 if (rdev->family >= CHIP_RV770) {
1377 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1378 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1379 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1380 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1381 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1382 reset_mask |= RADEON_RESET_GFX;
1383 } else {
1384 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1385 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1386 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1387 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1388 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1389 reset_mask |= RADEON_RESET_GFX;
1390 }
1391
1392 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1393 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1394 reset_mask |= RADEON_RESET_CP;
1395
1396 if (G_008010_GRBM_EE_BUSY(tmp))
1397 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1398
1399 /* DMA_STATUS_REG */
1400 tmp = RREG32(DMA_STATUS_REG);
1401 if (!(tmp & DMA_IDLE))
1402 reset_mask |= RADEON_RESET_DMA;
1403
1404 /* SRBM_STATUS */
1405 tmp = RREG32(R_000E50_SRBM_STATUS);
1406 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1407 reset_mask |= RADEON_RESET_RLC;
1408
1409 if (G_000E50_IH_BUSY(tmp))
1410 reset_mask |= RADEON_RESET_IH;
1411
1412 if (G_000E50_SEM_BUSY(tmp))
1413 reset_mask |= RADEON_RESET_SEM;
1414
1415 if (G_000E50_GRBM_RQ_PENDING(tmp))
1416 reset_mask |= RADEON_RESET_GRBM;
1417
1418 if (G_000E50_VMC_BUSY(tmp))
1419 reset_mask |= RADEON_RESET_VMC;
1420
1421 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1422 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1423 G_000E50_MCDW_BUSY(tmp))
1424 reset_mask |= RADEON_RESET_MC;
1425
1426 if (r600_is_display_hung(rdev))
1427 reset_mask |= RADEON_RESET_DISPLAY;
1428
Alex Deucherd808fc82013-02-28 10:03:08 -0500[diff] [blame]1429 /* Skip MC reset as it's mostly likely not hung, just busy */
1430 if (reset_mask & RADEON_RESET_MC) {
1431 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1432 reset_mask &= ~RADEON_RESET_MC;
1433 }
1434
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1435 return reset_mask;
1436}
1437
1438static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1439{
1440 struct rv515_mc_save save;
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1441 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1442 u32 tmp;
Alex Deucher19fc42e2013-01-14 11:04:39 -0500[diff] [blame]1443
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1444 if (reset_mask == 0)
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1445 return;
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1446
1447 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1448
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1449 r600_print_gpu_status_regs(rdev);
1450
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1451 /* Disable CP parsing/prefetching */
1452 if (rdev->family >= CHIP_RV770)
1453 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1454 else
1455 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1456
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1457 /* disable the RLC */
1458 WREG32(RLC_CNTL, 0);
1459
1460 if (reset_mask & RADEON_RESET_DMA) {
1461 /* Disable DMA */
1462 tmp = RREG32(DMA_RB_CNTL);
1463 tmp &= ~DMA_RB_ENABLE;
1464 WREG32(DMA_RB_CNTL, tmp);
1465 }
1466
1467 mdelay(50);
1468
Alex Deucherca578022013-01-23 18:56:08 -0500[diff] [blame]1469 rv515_mc_stop(rdev, &save);
1470 if (r600_mc_wait_for_idle(rdev)) {
1471 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1472 }
1473
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1474 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1475 if (rdev->family >= CHIP_RV770)
1476 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1477 S_008020_SOFT_RESET_CB(1) |
1478 S_008020_SOFT_RESET_PA(1) |
1479 S_008020_SOFT_RESET_SC(1) |
1480 S_008020_SOFT_RESET_SPI(1) |
1481 S_008020_SOFT_RESET_SX(1) |
1482 S_008020_SOFT_RESET_SH(1) |
1483 S_008020_SOFT_RESET_TC(1) |
1484 S_008020_SOFT_RESET_TA(1) |
1485 S_008020_SOFT_RESET_VC(1) |
1486 S_008020_SOFT_RESET_VGT(1);
1487 else
1488 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1489 S_008020_SOFT_RESET_DB(1) |
1490 S_008020_SOFT_RESET_CB(1) |
1491 S_008020_SOFT_RESET_PA(1) |
1492 S_008020_SOFT_RESET_SC(1) |
1493 S_008020_SOFT_RESET_SMX(1) |
1494 S_008020_SOFT_RESET_SPI(1) |
1495 S_008020_SOFT_RESET_SX(1) |
1496 S_008020_SOFT_RESET_SH(1) |
1497 S_008020_SOFT_RESET_TC(1) |
1498 S_008020_SOFT_RESET_TA(1) |
1499 S_008020_SOFT_RESET_VC(1) |
1500 S_008020_SOFT_RESET_VGT(1);
1501 }
1502
1503 if (reset_mask & RADEON_RESET_CP) {
1504 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1505 S_008020_SOFT_RESET_VGT(1);
1506
1507 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1508 }
1509
1510 if (reset_mask & RADEON_RESET_DMA) {
1511 if (rdev->family >= CHIP_RV770)
1512 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1513 else
1514 srbm_soft_reset |= SOFT_RESET_DMA;
1515 }
1516
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1517 if (reset_mask & RADEON_RESET_RLC)
1518 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1519
1520 if (reset_mask & RADEON_RESET_SEM)
1521 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1522
1523 if (reset_mask & RADEON_RESET_IH)
1524 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1525
1526 if (reset_mask & RADEON_RESET_GRBM)
1527 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1528
Alex Deucher24178ec2013-01-24 15:00:17 -0500[diff] [blame]1529 if (!(rdev->flags & RADEON_IS_IGP)) {
1530 if (reset_mask & RADEON_RESET_MC)
1531 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1532 }
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1533
1534 if (reset_mask & RADEON_RESET_VMC)
1535 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1536
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1537 if (grbm_soft_reset) {
1538 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1539 tmp |= grbm_soft_reset;
1540 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1541 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1542 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1543
1544 udelay(50);
1545
1546 tmp &= ~grbm_soft_reset;
1547 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1548 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1549 }
1550
1551 if (srbm_soft_reset) {
1552 tmp = RREG32(SRBM_SOFT_RESET);
1553 tmp |= srbm_soft_reset;
1554 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1555 WREG32(SRBM_SOFT_RESET, tmp);
1556 tmp = RREG32(SRBM_SOFT_RESET);
1557
1558 udelay(50);
1559
1560 tmp &= ~srbm_soft_reset;
1561 WREG32(SRBM_SOFT_RESET, tmp);
1562 tmp = RREG32(SRBM_SOFT_RESET);
1563 }
Alex Deucher71e3d152013-01-03 12:20:35 -0500[diff] [blame]1564
1565 /* Wait a little for things to settle down */
1566 mdelay(1);
1567
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]1568 rv515_mc_resume(rdev, &save);
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1569 udelay(50);
Alex Deucher410a3412013-01-18 13:05:39 -0500[diff] [blame]1570
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1571 r600_print_gpu_status_regs(rdev);
Alex Deucherd3cb7812013-01-18 13:53:37 -0500[diff] [blame]1572}
1573
1574int r600_asic_reset(struct radeon_device *rdev)
1575{
Alex Deucherf13f7732013-01-18 18:12:22 -0500[diff] [blame]1576 u32 reset_mask;
1577
1578 reset_mask = r600_gpu_check_soft_reset(rdev);
1579
1580 if (reset_mask)
1581 r600_set_bios_scratch_engine_hung(rdev, true);
1582
1583 r600_gpu_soft_reset(rdev, reset_mask);
1584
1585 reset_mask = r600_gpu_check_soft_reset(rdev);
1586
1587 if (!reset_mask)
1588 r600_set_bios_scratch_engine_hung(rdev, false);
1589
1590 return 0;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1591}
1592
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1593/**
1594 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1595 *
1596 * @rdev: radeon_device pointer
1597 * @ring: radeon_ring structure holding ring information
1598 *
1599 * Check if the GFX engine is locked up.
1600 * Returns true if the engine appears to be locked up, false if not.
1601 */
1602bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]1603{
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1604 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]1605
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1606 if (!(reset_mask & (RADEON_RESET_GFX |
1607 RADEON_RESET_COMPUTE |
1608 RADEON_RESET_CP))) {
Christian König069211e2012-05-02 15:11:20 +0200[diff] [blame]1609 radeon_ring_lockup_update(ring);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]1610 return false;
1611 }
1612 /* force CP activities */
Christian König7b9ef162012-05-02 15:11:23 +0200[diff] [blame]1613 radeon_ring_force_activity(rdev, ring);
Christian König069211e2012-05-02 15:11:20 +0200[diff] [blame]1614 return radeon_ring_test_lockup(rdev, ring);
Jerome Glisse225758d2010-03-09 14:45:10 +0000[diff] [blame]1615}
1616
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]1617/**
1618 * r600_dma_is_lockup - Check if the DMA engine is locked up
1619 *
1620 * @rdev: radeon_device pointer
1621 * @ring: radeon_ring structure holding ring information
1622 *
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1623 * Check if the async DMA engine is locked up.
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]1624 * Returns true if the engine appears to be locked up, false if not.
1625 */
1626bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1627{
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1628 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]1629
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]1630 if (!(reset_mask & RADEON_RESET_DMA)) {
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]1631 radeon_ring_lockup_update(ring);
1632 return false;
1633 }
1634 /* force ring activities */
1635 radeon_ring_force_activity(rdev, ring);
1636 return radeon_ring_test_lockup(rdev, ring);
1637}
1638
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1639u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1640 u32 tiling_pipe_num,
1641 u32 max_rb_num,
1642 u32 total_max_rb_num,
1643 u32 disabled_rb_mask)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1644{
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1645 u32 rendering_pipe_num, rb_num_width, req_rb_num;
Mikko Tiihonenf689e3a2013-01-30 14:10:04 -0500[diff] [blame]1646 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1647 u32 data = 0, mask = 1 << (max_rb_num - 1);
1648 unsigned i, j;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1649
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1650 /* mask out the RBs that don't exist on that asic */
Mikko Tiihonenf689e3a2013-01-30 14:10:04 -0500[diff] [blame]1651 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1652 /* make sure at least one RB is available */
1653 if ((tmp & 0xff) != 0xff)
1654 disabled_rb_mask = tmp;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1655
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1656 rendering_pipe_num = 1 << tiling_pipe_num;
1657 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1658 BUG_ON(rendering_pipe_num < req_rb_num);
1659
1660 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1661 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1662
1663 if (rdev->family <= CHIP_RV740) {
1664 /* r6xx/r7xx */
1665 rb_num_width = 2;
1666 } else {
1667 /* eg+ */
1668 rb_num_width = 4;
1669 }
1670
1671 for (i = 0; i < max_rb_num; i++) {
1672 if (!(mask & disabled_rb_mask)) {
1673 for (j = 0; j < pipe_rb_ratio; j++) {
1674 data <<= rb_num_width;
1675 data |= max_rb_num - i - 1;
1676 }
1677 if (pipe_rb_remain) {
1678 data <<= rb_num_width;
1679 data |= max_rb_num - i - 1;
1680 pipe_rb_remain--;
1681 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1682 }
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1683 mask >>= 1;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1684 }
1685
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1686 return data;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1687}
1688
1689int r600_count_pipe_bits(uint32_t val)
1690{
Akinobu Mitaef8cf3a2012-11-09 12:10:41 +0000[diff] [blame]1691 return hweight32(val);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1692}
1693
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]1694static void r600_gpu_init(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1695{
1696 u32 tiling_config;
1697 u32 ramcfg;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1698 u32 cc_rb_backend_disable;
1699 u32 cc_gc_shader_pipe_config;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1700 u32 tmp;
1701 int i, j;
1702 u32 sq_config;
1703 u32 sq_gpr_resource_mgmt_1 = 0;
1704 u32 sq_gpr_resource_mgmt_2 = 0;
1705 u32 sq_thread_resource_mgmt = 0;
1706 u32 sq_stack_resource_mgmt_1 = 0;
1707 u32 sq_stack_resource_mgmt_2 = 0;
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1708 u32 disabled_rb_mask;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1709
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1710 rdev->config.r600.tiling_group_size = 256;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1711 switch (rdev->family) {
1712 case CHIP_R600:
1713 rdev->config.r600.max_pipes = 4;
1714 rdev->config.r600.max_tile_pipes = 8;
1715 rdev->config.r600.max_simds = 4;
1716 rdev->config.r600.max_backends = 4;
1717 rdev->config.r600.max_gprs = 256;
1718 rdev->config.r600.max_threads = 192;
1719 rdev->config.r600.max_stack_entries = 256;
1720 rdev->config.r600.max_hw_contexts = 8;
1721 rdev->config.r600.max_gs_threads = 16;
1722 rdev->config.r600.sx_max_export_size = 128;
1723 rdev->config.r600.sx_max_export_pos_size = 16;
1724 rdev->config.r600.sx_max_export_smx_size = 128;
1725 rdev->config.r600.sq_num_cf_insts = 2;
1726 break;
1727 case CHIP_RV630:
1728 case CHIP_RV635:
1729 rdev->config.r600.max_pipes = 2;
1730 rdev->config.r600.max_tile_pipes = 2;
1731 rdev->config.r600.max_simds = 3;
1732 rdev->config.r600.max_backends = 1;
1733 rdev->config.r600.max_gprs = 128;
1734 rdev->config.r600.max_threads = 192;
1735 rdev->config.r600.max_stack_entries = 128;
1736 rdev->config.r600.max_hw_contexts = 8;
1737 rdev->config.r600.max_gs_threads = 4;
1738 rdev->config.r600.sx_max_export_size = 128;
1739 rdev->config.r600.sx_max_export_pos_size = 16;
1740 rdev->config.r600.sx_max_export_smx_size = 128;
1741 rdev->config.r600.sq_num_cf_insts = 2;
1742 break;
1743 case CHIP_RV610:
1744 case CHIP_RV620:
1745 case CHIP_RS780:
1746 case CHIP_RS880:
1747 rdev->config.r600.max_pipes = 1;
1748 rdev->config.r600.max_tile_pipes = 1;
1749 rdev->config.r600.max_simds = 2;
1750 rdev->config.r600.max_backends = 1;
1751 rdev->config.r600.max_gprs = 128;
1752 rdev->config.r600.max_threads = 192;
1753 rdev->config.r600.max_stack_entries = 128;
1754 rdev->config.r600.max_hw_contexts = 4;
1755 rdev->config.r600.max_gs_threads = 4;
1756 rdev->config.r600.sx_max_export_size = 128;
1757 rdev->config.r600.sx_max_export_pos_size = 16;
1758 rdev->config.r600.sx_max_export_smx_size = 128;
1759 rdev->config.r600.sq_num_cf_insts = 1;
1760 break;
1761 case CHIP_RV670:
1762 rdev->config.r600.max_pipes = 4;
1763 rdev->config.r600.max_tile_pipes = 4;
1764 rdev->config.r600.max_simds = 4;
1765 rdev->config.r600.max_backends = 4;
1766 rdev->config.r600.max_gprs = 192;
1767 rdev->config.r600.max_threads = 192;
1768 rdev->config.r600.max_stack_entries = 256;
1769 rdev->config.r600.max_hw_contexts = 8;
1770 rdev->config.r600.max_gs_threads = 16;
1771 rdev->config.r600.sx_max_export_size = 128;
1772 rdev->config.r600.sx_max_export_pos_size = 16;
1773 rdev->config.r600.sx_max_export_smx_size = 128;
1774 rdev->config.r600.sq_num_cf_insts = 2;
1775 break;
1776 default:
1777 break;
1778 }
1779
1780 /* Initialize HDP */
1781 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1782 WREG32((0x2c14 + j), 0x00000000);
1783 WREG32((0x2c18 + j), 0x00000000);
1784 WREG32((0x2c1c + j), 0x00000000);
1785 WREG32((0x2c20 + j), 0x00000000);
1786 WREG32((0x2c24 + j), 0x00000000);
1787 }
1788
1789 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1790
1791 /* Setup tiling */
1792 tiling_config = 0;
1793 ramcfg = RREG32(RAMCFG);
1794 switch (rdev->config.r600.max_tile_pipes) {
1795 case 1:
1796 tiling_config |= PIPE_TILING(0);
1797 break;
1798 case 2:
1799 tiling_config |= PIPE_TILING(1);
1800 break;
1801 case 4:
1802 tiling_config |= PIPE_TILING(2);
1803 break;
1804 case 8:
1805 tiling_config |= PIPE_TILING(3);
1806 break;
1807 default:
1808 break;
1809 }
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1810 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
Jerome Glisse961fb592010-02-10 22:30:05 +0000[diff] [blame]1811 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1812 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Alex Deucher881fe6c2010-10-18 23:54:56 -0400[diff] [blame]1813 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1814
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1815 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1816 if (tmp > 3) {
1817 tiling_config |= ROW_TILING(3);
1818 tiling_config |= SAMPLE_SPLIT(3);
1819 } else {
1820 tiling_config |= ROW_TILING(tmp);
1821 tiling_config |= SAMPLE_SPLIT(tmp);
1822 }
1823 tiling_config |= BANK_SWAPS(1);
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1824
1825 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1826 tmp = R6XX_MAX_BACKENDS -
1827 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1828 if (tmp < rdev->config.r600.max_backends) {
1829 rdev->config.r600.max_backends = tmp;
1830 }
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1831
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1832 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1833 tmp = R6XX_MAX_PIPES -
1834 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1835 if (tmp < rdev->config.r600.max_pipes) {
1836 rdev->config.r600.max_pipes = tmp;
1837 }
1838 tmp = R6XX_MAX_SIMDS -
1839 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1840 if (tmp < rdev->config.r600.max_simds) {
1841 rdev->config.r600.max_simds = tmp;
1842 }
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1843
Alex Deucher416a2bd2012-05-31 19:00:25 -0400[diff] [blame]1844 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1845 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1846 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1847 R6XX_MAX_BACKENDS, disabled_rb_mask);
1848 tiling_config |= tmp << 16;
1849 rdev->config.r600.backend_map = tmp;
1850
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400[diff] [blame]1851 rdev->config.r600.tile_config = tiling_config;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1852 WREG32(GB_TILING_CONFIG, tiling_config);
1853 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1854 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]1855 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1856
Alex Deucherd03f5d52010-02-19 16:22:31 -0500[diff] [blame]1857 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1858 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1859 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1860
1861 /* Setup some CP states */
1862 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1863 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1864
1865 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1866 SYNC_WALKER | SYNC_ALIGNER));
1867 /* Setup various GPU states */
1868 if (rdev->family == CHIP_RV670)
1869 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1870
1871 tmp = RREG32(SX_DEBUG_1);
1872 tmp |= SMX_EVENT_RELEASE;
1873 if ((rdev->family > CHIP_R600))
1874 tmp |= ENABLE_NEW_SMX_ADDRESS;
1875 WREG32(SX_DEBUG_1, tmp);
1876
1877 if (((rdev->family) == CHIP_R600) ||
1878 ((rdev->family) == CHIP_RV630) ||
1879 ((rdev->family) == CHIP_RV610) ||
1880 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]1881 ((rdev->family) == CHIP_RS780) ||
1882 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1883 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1884 } else {
1885 WREG32(DB_DEBUG, 0);
1886 }
1887 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1888 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1889
1890 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1891 WREG32(VGT_NUM_INSTANCES, 0);
1892
1893 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1894 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1895
1896 tmp = RREG32(SQ_MS_FIFO_SIZES);
1897 if (((rdev->family) == CHIP_RV610) ||
1898 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]1899 ((rdev->family) == CHIP_RS780) ||
1900 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1901 tmp = (CACHE_FIFO_SIZE(0xa) |
1902 FETCH_FIFO_HIWATER(0xa) |
1903 DONE_FIFO_HIWATER(0xe0) |
1904 ALU_UPDATE_FIFO_HIWATER(0x8));
1905 } else if (((rdev->family) == CHIP_R600) ||
1906 ((rdev->family) == CHIP_RV630)) {
1907 tmp &= ~DONE_FIFO_HIWATER(0xff);
1908 tmp |= DONE_FIFO_HIWATER(0x4);
1909 }
1910 WREG32(SQ_MS_FIFO_SIZES, tmp);
1911
1912 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1913 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1914 */
1915 sq_config = RREG32(SQ_CONFIG);
1916 sq_config &= ~(PS_PRIO(3) |
1917 VS_PRIO(3) |
1918 GS_PRIO(3) |
1919 ES_PRIO(3));
1920 sq_config |= (DX9_CONSTS |
1921 VC_ENABLE |
1922 PS_PRIO(0) |
1923 VS_PRIO(1) |
1924 GS_PRIO(2) |
1925 ES_PRIO(3));
1926
1927 if ((rdev->family) == CHIP_R600) {
1928 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1929 NUM_VS_GPRS(124) |
1930 NUM_CLAUSE_TEMP_GPRS(4));
1931 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1932 NUM_ES_GPRS(0));
1933 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1934 NUM_VS_THREADS(48) |
1935 NUM_GS_THREADS(4) |
1936 NUM_ES_THREADS(4));
1937 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1938 NUM_VS_STACK_ENTRIES(128));
1939 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1940 NUM_ES_STACK_ENTRIES(0));
1941 } else if (((rdev->family) == CHIP_RV610) ||
1942 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]1943 ((rdev->family) == CHIP_RS780) ||
1944 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]1945 /* no vertex cache */
1946 sq_config &= ~VC_ENABLE;
1947
1948 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1949 NUM_VS_GPRS(44) |
1950 NUM_CLAUSE_TEMP_GPRS(2));
1951 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1952 NUM_ES_GPRS(17));
1953 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1954 NUM_VS_THREADS(78) |
1955 NUM_GS_THREADS(4) |
1956 NUM_ES_THREADS(31));
1957 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1958 NUM_VS_STACK_ENTRIES(40));
1959 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1960 NUM_ES_STACK_ENTRIES(16));
1961 } else if (((rdev->family) == CHIP_RV630) ||
1962 ((rdev->family) == CHIP_RV635)) {
1963 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1964 NUM_VS_GPRS(44) |
1965 NUM_CLAUSE_TEMP_GPRS(2));
1966 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1967 NUM_ES_GPRS(18));
1968 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1969 NUM_VS_THREADS(78) |
1970 NUM_GS_THREADS(4) |
1971 NUM_ES_THREADS(31));
1972 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1973 NUM_VS_STACK_ENTRIES(40));
1974 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1975 NUM_ES_STACK_ENTRIES(16));
1976 } else if ((rdev->family) == CHIP_RV670) {
1977 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1978 NUM_VS_GPRS(44) |
1979 NUM_CLAUSE_TEMP_GPRS(2));
1980 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1981 NUM_ES_GPRS(17));
1982 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1983 NUM_VS_THREADS(78) |
1984 NUM_GS_THREADS(4) |
1985 NUM_ES_THREADS(31));
1986 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1987 NUM_VS_STACK_ENTRIES(64));
1988 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1989 NUM_ES_STACK_ENTRIES(64));
1990 }
1991
1992 WREG32(SQ_CONFIG, sq_config);
1993 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1994 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1995 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1996 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1997 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1998
1999 if (((rdev->family) == CHIP_RV610) ||
2000 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]2001 ((rdev->family) == CHIP_RS780) ||
2002 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2003 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2004 } else {
2005 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2006 }
2007
2008 /* More default values. 2D/3D driver should adjust as needed */
2009 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2010 S1_X(0x4) | S1_Y(0xc)));
2011 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2012 S1_X(0x2) | S1_Y(0x2) |
2013 S2_X(0xa) | S2_Y(0x6) |
2014 S3_X(0x6) | S3_Y(0xa)));
2015 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2016 S1_X(0x4) | S1_Y(0xc) |
2017 S2_X(0x1) | S2_Y(0x6) |
2018 S3_X(0xa) | S3_Y(0xe)));
2019 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2020 S5_X(0x0) | S5_Y(0x0) |
2021 S6_X(0xb) | S6_Y(0x4) |
2022 S7_X(0x7) | S7_Y(0x8)));
2023
2024 WREG32(VGT_STRMOUT_EN, 0);
2025 tmp = rdev->config.r600.max_pipes * 16;
2026 switch (rdev->family) {
2027 case CHIP_RV610:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2028 case CHIP_RV620:
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]2029 case CHIP_RS780:
2030 case CHIP_RS880:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2031 tmp += 32;
2032 break;
2033 case CHIP_RV670:
2034 tmp += 128;
2035 break;
2036 default:
2037 break;
2038 }
2039 if (tmp > 256) {
2040 tmp = 256;
2041 }
2042 WREG32(VGT_ES_PER_GS, 128);
2043 WREG32(VGT_GS_PER_ES, tmp);
2044 WREG32(VGT_GS_PER_VS, 2);
2045 WREG32(VGT_GS_VERTEX_REUSE, 16);
2046
2047 /* more default values. 2D/3D driver should adjust as needed */
2048 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2049 WREG32(VGT_STRMOUT_EN, 0);
2050 WREG32(SX_MISC, 0);
2051 WREG32(PA_SC_MODE_CNTL, 0);
2052 WREG32(PA_SC_AA_CONFIG, 0);
2053 WREG32(PA_SC_LINE_STIPPLE, 0);
2054 WREG32(SPI_INPUT_Z, 0);
2055 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2056 WREG32(CB_COLOR7_FRAG, 0);
2057
2058 /* Clear render buffer base addresses */
2059 WREG32(CB_COLOR0_BASE, 0);
2060 WREG32(CB_COLOR1_BASE, 0);
2061 WREG32(CB_COLOR2_BASE, 0);
2062 WREG32(CB_COLOR3_BASE, 0);
2063 WREG32(CB_COLOR4_BASE, 0);
2064 WREG32(CB_COLOR5_BASE, 0);
2065 WREG32(CB_COLOR6_BASE, 0);
2066 WREG32(CB_COLOR7_BASE, 0);
2067 WREG32(CB_COLOR7_FRAG, 0);
2068
2069 switch (rdev->family) {
2070 case CHIP_RV610:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2071 case CHIP_RV620:
Alex Deucheree59f2b2009-11-05 13:11:46 -0500[diff] [blame]2072 case CHIP_RS780:
2073 case CHIP_RS880:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2074 tmp = TC_L2_SIZE(8);
2075 break;
2076 case CHIP_RV630:
2077 case CHIP_RV635:
2078 tmp = TC_L2_SIZE(4);
2079 break;
2080 case CHIP_R600:
2081 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2082 break;
2083 default:
2084 tmp = TC_L2_SIZE(0);
2085 break;
2086 }
2087 WREG32(TC_CNTL, tmp);
2088
2089 tmp = RREG32(HDP_HOST_PATH_CNTL);
2090 WREG32(HDP_HOST_PATH_CNTL, tmp);
2091
2092 tmp = RREG32(ARB_POP);
2093 tmp |= ENABLE_TC128;
2094 WREG32(ARB_POP, tmp);
2095
2096 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2097 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2098 NUM_CLIP_SEQ(3)));
2099 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
Alex Deucherb866d132012-06-14 22:06:36 +0200[diff] [blame]2100 WREG32(VC_ENHANCE, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2101}
2102
2103
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]2104/*
2105 * Indirect registers accessor
2106 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2107u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]2108{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2109 u32 r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]2110
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2111 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2112 (void)RREG32(PCIE_PORT_INDEX);
2113 r = RREG32(PCIE_PORT_DATA);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]2114 return r;
2115}
2116
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2117void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]2118{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2119 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2120 (void)RREG32(PCIE_PORT_INDEX);
2121 WREG32(PCIE_PORT_DATA, (v));
2122 (void)RREG32(PCIE_PORT_DATA);
2123}
2124
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2125/*
2126 * CP & Ring
2127 */
2128void r600_cp_stop(struct radeon_device *rdev)
2129{
Dave Airlie53595332011-03-14 09:47:24 +1000[diff] [blame]2130 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2131 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2132 WREG32(SCRATCH_UMSK, 0);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2133 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2134}
2135
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2136int r600_init_microcode(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2137{
2138 struct platform_device *pdev;
2139 const char *chip_name;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2140 const char *rlc_chip_name;
2141 size_t pfp_req_size, me_req_size, rlc_req_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2142 char fw_name[30];
2143 int err;
2144
2145 DRM_DEBUG("\n");
2146
2147 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
2148 err = IS_ERR(pdev);
2149 if (err) {
2150 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
2151 return -EINVAL;
2152 }
2153
2154 switch (rdev->family) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2155 case CHIP_R600:
2156 chip_name = "R600";
2157 rlc_chip_name = "R600";
2158 break;
2159 case CHIP_RV610:
2160 chip_name = "RV610";
2161 rlc_chip_name = "R600";
2162 break;
2163 case CHIP_RV630:
2164 chip_name = "RV630";
2165 rlc_chip_name = "R600";
2166 break;
2167 case CHIP_RV620:
2168 chip_name = "RV620";
2169 rlc_chip_name = "R600";
2170 break;
2171 case CHIP_RV635:
2172 chip_name = "RV635";
2173 rlc_chip_name = "R600";
2174 break;
2175 case CHIP_RV670:
2176 chip_name = "RV670";
2177 rlc_chip_name = "R600";
2178 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2179 case CHIP_RS780:
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2180 case CHIP_RS880:
2181 chip_name = "RS780";
2182 rlc_chip_name = "R600";
2183 break;
2184 case CHIP_RV770:
2185 chip_name = "RV770";
2186 rlc_chip_name = "R700";
2187 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2188 case CHIP_RV730:
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2189 case CHIP_RV740:
2190 chip_name = "RV730";
2191 rlc_chip_name = "R700";
2192 break;
2193 case CHIP_RV710:
2194 chip_name = "RV710";
2195 rlc_chip_name = "R700";
2196 break;
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2197 case CHIP_CEDAR:
2198 chip_name = "CEDAR";
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]2199 rlc_chip_name = "CEDAR";
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2200 break;
2201 case CHIP_REDWOOD:
2202 chip_name = "REDWOOD";
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]2203 rlc_chip_name = "REDWOOD";
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2204 break;
2205 case CHIP_JUNIPER:
2206 chip_name = "JUNIPER";
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]2207 rlc_chip_name = "JUNIPER";
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2208 break;
2209 case CHIP_CYPRESS:
2210 case CHIP_HEMLOCK:
2211 chip_name = "CYPRESS";
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]2212 rlc_chip_name = "CYPRESS";
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2213 break;
Alex Deucher439bd6c2010-11-22 17:56:31 -0500[diff] [blame]2214 case CHIP_PALM:
2215 chip_name = "PALM";
2216 rlc_chip_name = "SUMO";
2217 break;
Alex Deucherd5c5a722011-05-31 15:42:48 -0400[diff] [blame]2218 case CHIP_SUMO:
2219 chip_name = "SUMO";
2220 rlc_chip_name = "SUMO";
2221 break;
2222 case CHIP_SUMO2:
2223 chip_name = "SUMO2";
2224 rlc_chip_name = "SUMO";
2225 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2226 default: BUG();
2227 }
2228
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2229 if (rdev->family >= CHIP_CEDAR) {
2230 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2231 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]2232 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2233 } else if (rdev->family >= CHIP_RV770) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2234 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2235 me_req_size = R700_PM4_UCODE_SIZE * 4;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2236 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2237 } else {
Alex Deucher138e4e12013-01-11 15:33:13 -0500[diff] [blame^]2238 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2239 me_req_size = R600_PM4_UCODE_SIZE * 12;
2240 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2241 }
2242
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2243 DRM_INFO("Loading %s Microcode\n", chip_name);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2244
2245 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2246 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2247 if (err)
2248 goto out;
2249 if (rdev->pfp_fw->size != pfp_req_size) {
2250 printk(KERN_ERR
2251 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2252 rdev->pfp_fw->size, fw_name);
2253 err = -EINVAL;
2254 goto out;
2255 }
2256
2257 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2258 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2259 if (err)
2260 goto out;
2261 if (rdev->me_fw->size != me_req_size) {
2262 printk(KERN_ERR
2263 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2264 rdev->me_fw->size, fw_name);
2265 err = -EINVAL;
2266 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2267
2268 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2269 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2270 if (err)
2271 goto out;
2272 if (rdev->rlc_fw->size != rlc_req_size) {
2273 printk(KERN_ERR
2274 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2275 rdev->rlc_fw->size, fw_name);
2276 err = -EINVAL;
2277 }
2278
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2279out:
2280 platform_device_unregister(pdev);
2281
2282 if (err) {
2283 if (err != -EINVAL)
2284 printk(KERN_ERR
2285 "r600_cp: Failed to load firmware \"%s\"\n",
2286 fw_name);
2287 release_firmware(rdev->pfp_fw);
2288 rdev->pfp_fw = NULL;
2289 release_firmware(rdev->me_fw);
2290 rdev->me_fw = NULL;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]2291 release_firmware(rdev->rlc_fw);
2292 rdev->rlc_fw = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2293 }
2294 return err;
2295}
2296
2297static int r600_cp_load_microcode(struct radeon_device *rdev)
2298{
2299 const __be32 *fw_data;
2300 int i;
2301
2302 if (!rdev->me_fw || !rdev->pfp_fw)
2303 return -EINVAL;
2304
2305 r600_cp_stop(rdev);
2306
Cédric Cano4eace7f2011-02-11 19:45:38 -0500[diff] [blame]2307 WREG32(CP_RB_CNTL,
2308#ifdef __BIG_ENDIAN
2309 BUF_SWAP_32BIT |
2310#endif
2311 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2312
2313 /* Reset cp */
2314 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2315 RREG32(GRBM_SOFT_RESET);
2316 mdelay(15);
2317 WREG32(GRBM_SOFT_RESET, 0);
2318
2319 WREG32(CP_ME_RAM_WADDR, 0);
2320
2321 fw_data = (const __be32 *)rdev->me_fw->data;
2322 WREG32(CP_ME_RAM_WADDR, 0);
Alex Deucher138e4e12013-01-11 15:33:13 -0500[diff] [blame^]2323 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2324 WREG32(CP_ME_RAM_DATA,
2325 be32_to_cpup(fw_data++));
2326
2327 fw_data = (const __be32 *)rdev->pfp_fw->data;
2328 WREG32(CP_PFP_UCODE_ADDR, 0);
Alex Deucher138e4e12013-01-11 15:33:13 -0500[diff] [blame^]2329 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2330 WREG32(CP_PFP_UCODE_DATA,
2331 be32_to_cpup(fw_data++));
2332
2333 WREG32(CP_PFP_UCODE_ADDR, 0);
2334 WREG32(CP_ME_RAM_WADDR, 0);
2335 WREG32(CP_ME_RAM_RADDR, 0);
2336 return 0;
2337}
2338
2339int r600_cp_start(struct radeon_device *rdev)
2340{
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2341 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2342 int r;
2343 uint32_t cp_me;
2344
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2345 r = radeon_ring_lock(rdev, ring, 7);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2346 if (r) {
2347 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2348 return r;
2349 }
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2350 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2351 radeon_ring_write(ring, 0x1);
Alex Deucher7e7b41d2010-09-02 21:32:32 -0400[diff] [blame]2352 if (rdev->family >= CHIP_RV770) {
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2353 radeon_ring_write(ring, 0x0);
2354 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]2355 } else {
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2356 radeon_ring_write(ring, 0x3);
2357 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2358 }
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2359 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2360 radeon_ring_write(ring, 0);
2361 radeon_ring_write(ring, 0);
2362 radeon_ring_unlock_commit(rdev, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2363
2364 cp_me = 0xff;
2365 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2366 return 0;
2367}
2368
2369int r600_cp_resume(struct radeon_device *rdev)
2370{
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2371 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2372 u32 tmp;
2373 u32 rb_bufsz;
2374 int r;
2375
2376 /* Reset cp */
2377 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2378 RREG32(GRBM_SOFT_RESET);
2379 mdelay(15);
2380 WREG32(GRBM_SOFT_RESET, 0);
2381
2382 /* Set ring buffer size */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2383 rb_bufsz = drm_order(ring->ring_size / 8);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2384 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2385#ifdef __BIG_ENDIAN
Alex Deucherd6f28932009-11-02 16:01:27 -0500[diff] [blame]2386 tmp |= BUF_SWAP_32BIT;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2387#endif
Alex Deucherd6f28932009-11-02 16:01:27 -0500[diff] [blame]2388 WREG32(CP_RB_CNTL, tmp);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]2389 WREG32(CP_SEM_WAIT_TIMER, 0x0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2390
2391 /* Set the write pointer delay */
2392 WREG32(CP_RB_WPTR_DELAY, 0);
2393
2394 /* Initialize the ring buffer's read and write pointers */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2395 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2396 WREG32(CP_RB_RPTR_WR, 0);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2397 ring->wptr = 0;
2398 WREG32(CP_RB_WPTR, ring->wptr);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2399
2400 /* set the wb address whether it's enabled or not */
Cédric Cano4eace7f2011-02-11 19:45:38 -0500[diff] [blame]2401 WREG32(CP_RB_RPTR_ADDR,
Cédric Cano4eace7f2011-02-11 19:45:38 -0500[diff] [blame]2402 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2403 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2404 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2405
2406 if (rdev->wb.enabled)
2407 WREG32(SCRATCH_UMSK, 0xff);
2408 else {
2409 tmp |= RB_NO_UPDATE;
2410 WREG32(SCRATCH_UMSK, 0);
2411 }
2412
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2413 mdelay(1);
2414 WREG32(CP_RB_CNTL, tmp);
2415
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2416 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2417 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2418
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2419 ring->rptr = RREG32(CP_RB_RPTR);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2420
2421 r600_cp_start(rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2422 ring->ready = true;
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]2423 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2424 if (r) {
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2425 ring->ready = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2426 return r;
2427 }
2428 return 0;
2429}
2430
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2431void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2432{
2433 u32 rb_bufsz;
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]2434 int r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2435
2436 /* Align ring size */
2437 rb_bufsz = drm_order(ring_size / 8);
2438 ring_size = (1 << (rb_bufsz + 1)) * 4;
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2439 ring->ring_size = ring_size;
2440 ring->align_mask = 16 - 1;
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]2441
Alex Deucher89d35802012-07-17 14:02:31 -0400[diff] [blame]2442 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2443 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2444 if (r) {
2445 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2446 ring->rptr_save_reg = 0;
2447 }
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]2448 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2449}
2450
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]2451void r600_cp_fini(struct radeon_device *rdev)
2452{
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]2453 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]2454 r600_cp_stop(rdev);
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]2455 radeon_ring_fini(rdev, ring);
2456 radeon_scratch_free(rdev, ring->rptr_save_reg);
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]2457}
2458
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2459/*
2460 * DMA
2461 * Starting with R600, the GPU has an asynchronous
2462 * DMA engine. The programming model is very similar
2463 * to the 3D engine (ring buffer, IBs, etc.), but the
2464 * DMA controller has it's own packet format that is
2465 * different form the PM4 format used by the 3D engine.
2466 * It supports copying data, writing embedded data,
2467 * solid fills, and a number of other things. It also
2468 * has support for tiling/detiling of buffers.
2469 */
2470/**
2471 * r600_dma_stop - stop the async dma engine
2472 *
2473 * @rdev: radeon_device pointer
2474 *
2475 * Stop the async dma engine (r6xx-evergreen).
2476 */
2477void r600_dma_stop(struct radeon_device *rdev)
2478{
2479 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2480
2481 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2482
2483 rb_cntl &= ~DMA_RB_ENABLE;
2484 WREG32(DMA_RB_CNTL, rb_cntl);
2485
2486 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2487}
2488
2489/**
2490 * r600_dma_resume - setup and start the async dma engine
2491 *
2492 * @rdev: radeon_device pointer
2493 *
2494 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2495 * Returns 0 for success, error for failure.
2496 */
2497int r600_dma_resume(struct radeon_device *rdev)
2498{
2499 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
Michel Dänzerb3dfcb22013-01-24 19:02:01 +0100[diff] [blame]2500 u32 rb_cntl, dma_cntl, ib_cntl;
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2501 u32 rb_bufsz;
2502 int r;
2503
2504 /* Reset dma */
2505 if (rdev->family >= CHIP_RV770)
2506 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2507 else
2508 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2509 RREG32(SRBM_SOFT_RESET);
2510 udelay(50);
2511 WREG32(SRBM_SOFT_RESET, 0);
2512
2513 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2514 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2515
2516 /* Set ring buffer size in dwords */
2517 rb_bufsz = drm_order(ring->ring_size / 4);
2518 rb_cntl = rb_bufsz << 1;
2519#ifdef __BIG_ENDIAN
2520 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2521#endif
2522 WREG32(DMA_RB_CNTL, rb_cntl);
2523
2524 /* Initialize the ring buffer's read and write pointers */
2525 WREG32(DMA_RB_RPTR, 0);
2526 WREG32(DMA_RB_WPTR, 0);
2527
2528 /* set the wb address whether it's enabled or not */
2529 WREG32(DMA_RB_RPTR_ADDR_HI,
2530 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2531 WREG32(DMA_RB_RPTR_ADDR_LO,
2532 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2533
2534 if (rdev->wb.enabled)
2535 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2536
2537 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2538
2539 /* enable DMA IBs */
Michel Dänzerb3dfcb22013-01-24 19:02:01 +0100[diff] [blame]2540 ib_cntl = DMA_IB_ENABLE;
2541#ifdef __BIG_ENDIAN
2542 ib_cntl |= DMA_IB_SWAP_ENABLE;
2543#endif
2544 WREG32(DMA_IB_CNTL, ib_cntl);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2545
2546 dma_cntl = RREG32(DMA_CNTL);
2547 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2548 WREG32(DMA_CNTL, dma_cntl);
2549
2550 if (rdev->family >= CHIP_RV770)
2551 WREG32(DMA_MODE, 1);
2552
2553 ring->wptr = 0;
2554 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2555
2556 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2557
2558 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2559
2560 ring->ready = true;
2561
2562 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2563 if (r) {
2564 ring->ready = false;
2565 return r;
2566 }
2567
2568 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2569
2570 return 0;
2571}
2572
2573/**
2574 * r600_dma_fini - tear down the async dma engine
2575 *
2576 * @rdev: radeon_device pointer
2577 *
2578 * Stop the async dma engine and free the ring (r6xx-evergreen).
2579 */
2580void r600_dma_fini(struct radeon_device *rdev)
2581{
2582 r600_dma_stop(rdev);
2583 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2584}
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2585
2586/*
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2587 * UVD
2588 */
2589int r600_uvd_rbc_start(struct radeon_device *rdev)
2590{
2591 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2592 uint64_t rptr_addr;
2593 uint32_t rb_bufsz, tmp;
2594 int r;
2595
2596 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
2597
2598 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
2599 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2600 return -EINVAL;
2601 }
2602
2603 /* force RBC into idle state */
2604 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2605
2606 /* Set the write pointer delay */
2607 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2608
2609 /* set the wb address */
2610 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
2611
2612 /* programm the 4GB memory segment for rptr and ring buffer */
2613 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
2614 (0x7 << 16) | (0x1 << 31));
2615
2616 /* Initialize the ring buffer's read and write pointers */
2617 WREG32(UVD_RBC_RB_RPTR, 0x0);
2618
2619 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2620 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2621
2622 /* set the ring address */
2623 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2624
2625 /* Set ring buffer size */
2626 rb_bufsz = drm_order(ring->ring_size);
2627 rb_bufsz = (0x1 << 8) | rb_bufsz;
2628 WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
2629
2630 ring->ready = true;
2631 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2632 if (r) {
2633 ring->ready = false;
2634 return r;
2635 }
2636
2637 r = radeon_ring_lock(rdev, ring, 10);
2638 if (r) {
2639 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2640 return r;
2641 }
2642
2643 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2644 radeon_ring_write(ring, tmp);
2645 radeon_ring_write(ring, 0xFFFFF);
2646
2647 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2648 radeon_ring_write(ring, tmp);
2649 radeon_ring_write(ring, 0xFFFFF);
2650
2651 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2652 radeon_ring_write(ring, tmp);
2653 radeon_ring_write(ring, 0xFFFFF);
2654
2655 /* Clear timeout status bits */
2656 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2657 radeon_ring_write(ring, 0x8);
2658
2659 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
Christian König03708b052013-04-23 11:01:31 +0200[diff] [blame]2660 radeon_ring_write(ring, 3);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2661
2662 radeon_ring_unlock_commit(rdev, ring);
2663
2664 return 0;
2665}
2666
2667void r600_uvd_rbc_stop(struct radeon_device *rdev)
2668{
2669 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2670
2671 /* force RBC into idle state */
2672 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2673 ring->ready = false;
2674}
2675
2676int r600_uvd_init(struct radeon_device *rdev)
2677{
2678 int i, j, r;
Alex Deucher9b1be4d2013-06-07 10:04:54 -0400[diff] [blame]2679 /* disable byte swapping */
2680 u32 lmi_swap_cntl = 0;
2681 u32 mp_swap_cntl = 0;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2682
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2683 /* raise clocks while booting up the VCPU */
2684 radeon_set_uvd_clocks(rdev, 53300, 40000);
2685
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2686 /* disable clock gating */
2687 WREG32(UVD_CGC_GATE, 0);
2688
2689 /* disable interupt */
2690 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2691
2692 /* put LMI, VCPU, RBC etc... into reset */
2693 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2694 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2695 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2696 mdelay(5);
2697
2698 /* take UVD block out of reset */
2699 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2700 mdelay(5);
2701
2702 /* initialize UVD memory controller */
2703 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2704 (1 << 21) | (1 << 9) | (1 << 20));
2705
Alex Deucher9b1be4d2013-06-07 10:04:54 -0400[diff] [blame]2706#ifdef __BIG_ENDIAN
2707 /* swap (8 in 32) RB and IB */
2708 lmi_swap_cntl = 0xa;
2709 mp_swap_cntl = 0;
2710#endif
2711 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
2712 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2713
2714 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2715 WREG32(UVD_MPC_SET_MUXA1, 0x0);
2716 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2717 WREG32(UVD_MPC_SET_MUXB1, 0x0);
2718 WREG32(UVD_MPC_SET_ALU, 0);
2719 WREG32(UVD_MPC_SET_MUX, 0x88);
2720
2721 /* Stall UMC */
2722 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2723 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2724
2725 /* take all subblocks out of reset, except VCPU */
2726 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2727 mdelay(5);
2728
2729 /* enable VCPU clock */
2730 WREG32(UVD_VCPU_CNTL, 1 << 9);
2731
2732 /* enable UMC */
2733 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2734
2735 /* boot up the VCPU */
2736 WREG32(UVD_SOFT_RESET, 0);
2737 mdelay(10);
2738
2739 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2740
2741 for (i = 0; i < 10; ++i) {
2742 uint32_t status;
2743 for (j = 0; j < 100; ++j) {
2744 status = RREG32(UVD_STATUS);
2745 if (status & 2)
2746 break;
2747 mdelay(10);
2748 }
2749 r = 0;
2750 if (status & 2)
2751 break;
2752
2753 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2754 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2755 mdelay(10);
2756 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2757 mdelay(10);
2758 r = -1;
2759 }
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2760
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2761 if (r) {
2762 DRM_ERROR("UVD not responding, giving up!!!\n");
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2763 radeon_set_uvd_clocks(rdev, 0, 0);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2764 return r;
2765 }
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2766
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2767 /* enable interupt */
2768 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2769
2770 r = r600_uvd_rbc_start(rdev);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2771 if (!r)
2772 DRM_INFO("UVD initialized successfully.\n");
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2773
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]2774 /* lower clocks again */
2775 radeon_set_uvd_clocks(rdev, 0, 0);
2776
2777 return r;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2778}
2779
2780/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2781 * GPU scratch registers helpers function.
2782 */
2783void r600_scratch_init(struct radeon_device *rdev)
2784{
2785 int i;
2786
2787 rdev->scratch.num_reg = 7;
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2788 rdev->scratch.reg_base = SCRATCH_REG0;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2789 for (i = 0; i < rdev->scratch.num_reg; i++) {
2790 rdev->scratch.free[i] = true;
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]2791 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2792 }
2793}
2794
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2795int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2796{
2797 uint32_t scratch;
2798 uint32_t tmp = 0;
Alex Deucher8b25ed32012-07-17 14:02:30 -0400[diff] [blame]2799 unsigned i;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2800 int r;
2801
2802 r = radeon_scratch_get(rdev, &scratch);
2803 if (r) {
2804 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2805 return r;
2806 }
2807 WREG32(scratch, 0xCAFEDEAD);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2808 r = radeon_ring_lock(rdev, ring, 3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2809 if (r) {
Alex Deucher8b25ed32012-07-17 14:02:30 -0400[diff] [blame]2810 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2811 radeon_scratch_free(rdev, scratch);
2812 return r;
2813 }
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2814 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2815 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2816 radeon_ring_write(ring, 0xDEADBEEF);
2817 radeon_ring_unlock_commit(rdev, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2818 for (i = 0; i < rdev->usec_timeout; i++) {
2819 tmp = RREG32(scratch);
2820 if (tmp == 0xDEADBEEF)
2821 break;
2822 DRM_UDELAY(1);
2823 }
2824 if (i < rdev->usec_timeout) {
Alex Deucher8b25ed32012-07-17 14:02:30 -0400[diff] [blame]2825 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2826 } else {
Christian Königbf852792011-10-13 13:19:22 +0200[diff] [blame]2827 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
Alex Deucher8b25ed32012-07-17 14:02:30 -0400[diff] [blame]2828 ring->idx, scratch, tmp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2829 r = -EINVAL;
2830 }
2831 radeon_scratch_free(rdev, scratch);
2832 return r;
2833}
2834
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2835/**
2836 * r600_dma_ring_test - simple async dma engine test
2837 *
2838 * @rdev: radeon_device pointer
2839 * @ring: radeon_ring structure holding ring information
2840 *
2841 * Test the DMA engine by writing using it to write an
2842 * value to memory. (r6xx-SI).
2843 * Returns 0 for success, error for failure.
2844 */
2845int r600_dma_ring_test(struct radeon_device *rdev,
2846 struct radeon_ring *ring)
2847{
2848 unsigned i;
2849 int r;
2850 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2851 u32 tmp;
2852
2853 if (!ptr) {
2854 DRM_ERROR("invalid vram scratch pointer\n");
2855 return -EINVAL;
2856 }
2857
2858 tmp = 0xCAFEDEAD;
2859 writel(tmp, ptr);
2860
2861 r = radeon_ring_lock(rdev, ring, 4);
2862 if (r) {
2863 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2864 return r;
2865 }
2866 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2867 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2868 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2869 radeon_ring_write(ring, 0xDEADBEEF);
2870 radeon_ring_unlock_commit(rdev, ring);
2871
2872 for (i = 0; i < rdev->usec_timeout; i++) {
2873 tmp = readl(ptr);
2874 if (tmp == 0xDEADBEEF)
2875 break;
2876 DRM_UDELAY(1);
2877 }
2878
2879 if (i < rdev->usec_timeout) {
2880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2881 } else {
2882 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2883 ring->idx, tmp);
2884 r = -EINVAL;
2885 }
2886 return r;
2887}
2888
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2889int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2890{
2891 uint32_t tmp = 0;
2892 unsigned i;
2893 int r;
2894
2895 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
2896 r = radeon_ring_lock(rdev, ring, 3);
2897 if (r) {
2898 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2899 ring->idx, r);
2900 return r;
2901 }
2902 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2903 radeon_ring_write(ring, 0xDEADBEEF);
2904 radeon_ring_unlock_commit(rdev, ring);
2905 for (i = 0; i < rdev->usec_timeout; i++) {
2906 tmp = RREG32(UVD_CONTEXT_ID);
2907 if (tmp == 0xDEADBEEF)
2908 break;
2909 DRM_UDELAY(1);
2910 }
2911
2912 if (i < rdev->usec_timeout) {
2913 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2914 ring->idx, i);
2915 } else {
2916 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2917 ring->idx, tmp);
2918 r = -EINVAL;
2919 }
2920 return r;
2921}
2922
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]2923/*
2924 * CP fences/semaphores
2925 */
2926
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2927void r600_fence_ring_emit(struct radeon_device *rdev,
2928 struct radeon_fence *fence)
2929{
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2930 struct radeon_ring *ring = &rdev->ring[fence->ring];
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]2931
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2932 if (rdev->wb.use_event) {
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000[diff] [blame]2933 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
Jerome Glisse77b1bad2011-10-26 11:41:22 -0400[diff] [blame]2934 /* flush read cache over gart */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2935 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2936 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2937 PACKET3_VC_ACTION_ENA |
2938 PACKET3_SH_ACTION_ENA);
2939 radeon_ring_write(ring, 0xFFFFFFFF);
2940 radeon_ring_write(ring, 0);
2941 radeon_ring_write(ring, 10); /* poll interval */
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2942 /* EVENT_WRITE_EOP - flush caches, send int */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2943 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2944 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2945 radeon_ring_write(ring, addr & 0xffffffff);
2946 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2947 radeon_ring_write(ring, fence->seq);
2948 radeon_ring_write(ring, 0);
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2949 } else {
Jerome Glisse77b1bad2011-10-26 11:41:22 -0400[diff] [blame]2950 /* flush read cache over gart */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2951 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2952 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2953 PACKET3_VC_ACTION_ENA |
2954 PACKET3_SH_ACTION_ENA);
2955 radeon_ring_write(ring, 0xFFFFFFFF);
2956 radeon_ring_write(ring, 0);
2957 radeon_ring_write(ring, 10); /* poll interval */
2958 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2959 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2960 /* wait for 3D idle clean */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2961 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2962 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2963 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2964 /* Emit fence sequence & fire IRQ */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2965 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2966 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2967 radeon_ring_write(ring, fence->seq);
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2968 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2969 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2970 radeon_ring_write(ring, RB_INT_STAT);
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]2971 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]2972}
2973
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]2974void r600_uvd_fence_emit(struct radeon_device *rdev,
2975 struct radeon_fence *fence)
2976{
2977 struct radeon_ring *ring = &rdev->ring[fence->ring];
2978 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
2979
2980 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2981 radeon_ring_write(ring, fence->seq);
2982 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2983 radeon_ring_write(ring, addr & 0xffffffff);
2984 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2985 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2986 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2987 radeon_ring_write(ring, 0);
2988
2989 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2990 radeon_ring_write(ring, 0);
2991 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2992 radeon_ring_write(ring, 0);
2993 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2994 radeon_ring_write(ring, 2);
2995 return;
2996}
2997
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]2998void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]2999 struct radeon_ring *ring,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]3000 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]3001 bool emit_wait)
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]3002{
3003 uint64_t addr = semaphore->gpu_addr;
3004 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3005
Christian König0be70432012-03-07 11:28:57 +0100[diff] [blame]3006 if (rdev->family < CHIP_CAYMAN)
3007 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
3008
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]3009 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3010 radeon_ring_write(ring, addr & 0xffffffff);
3011 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]3012}
3013
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3014/*
3015 * DMA fences/semaphores
3016 */
3017
3018/**
3019 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
3020 *
3021 * @rdev: radeon_device pointer
3022 * @fence: radeon fence object
3023 *
3024 * Add a DMA fence packet to the ring to write
3025 * the fence seq number and DMA trap packet to generate
3026 * an interrupt if needed (r6xx-r7xx).
3027 */
3028void r600_dma_fence_ring_emit(struct radeon_device *rdev,
3029 struct radeon_fence *fence)
3030{
3031 struct radeon_ring *ring = &rdev->ring[fence->ring];
3032 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
Jerome Glisse86a18812012-12-12 16:43:15 -0500[diff] [blame]3033
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3034 /* write the fence */
3035 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3036 radeon_ring_write(ring, addr & 0xfffffffc);
3037 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
Jerome Glisse86a18812012-12-12 16:43:15 -0500[diff] [blame]3038 radeon_ring_write(ring, lower_32_bits(fence->seq));
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3039 /* generate an interrupt */
3040 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3041}
3042
3043/**
3044 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3045 *
3046 * @rdev: radeon_device pointer
3047 * @ring: radeon_ring structure holding ring information
3048 * @semaphore: radeon semaphore object
3049 * @emit_wait: wait or signal semaphore
3050 *
3051 * Add a DMA semaphore packet to the ring wait on or signal
3052 * other rings (r6xx-SI).
3053 */
3054void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
3055 struct radeon_ring *ring,
3056 struct radeon_semaphore *semaphore,
3057 bool emit_wait)
3058{
3059 u64 addr = semaphore->gpu_addr;
3060 u32 s = emit_wait ? 0 : 1;
3061
3062 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
3063 radeon_ring_write(ring, addr & 0xfffffffc);
3064 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3065}
3066
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3067void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3068 struct radeon_ring *ring,
3069 struct radeon_semaphore *semaphore,
3070 bool emit_wait)
3071{
3072 uint64_t addr = semaphore->gpu_addr;
3073
3074 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3075 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3076
3077 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3078 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3079
3080 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3081 radeon_ring_write(ring, emit_wait ? 1 : 0);
3082}
3083
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3084int r600_copy_blit(struct radeon_device *rdev,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]3085 uint64_t src_offset,
3086 uint64_t dst_offset,
3087 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]3088 struct radeon_fence **fence)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3089{
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]3090 struct radeon_semaphore *sem = NULL;
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]3091 struct radeon_sa_bo *vb = NULL;
Jerome Glisseff82f052010-01-22 15:19:00 +0100[diff] [blame]3092 int r;
3093
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]3094 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
Jerome Glisseff82f052010-01-22 15:19:00 +0100[diff] [blame]3095 if (r) {
Jerome Glisseff82f052010-01-22 15:19:00 +0100[diff] [blame]3096 return r;
3097 }
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]3098 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]3099 r600_blit_done_copy(rdev, fence, vb, sem);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3100 return 0;
3101}
3102
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3103/**
3104 * r600_copy_dma - copy pages using the DMA engine
3105 *
3106 * @rdev: radeon_device pointer
3107 * @src_offset: src GPU address
3108 * @dst_offset: dst GPU address
3109 * @num_gpu_pages: number of GPU pages to xfer
3110 * @fence: radeon fence object
3111 *
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]3112 * Copy GPU paging using the DMA engine (r6xx).
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3113 * Used by the radeon ttm implementation to move pages if
3114 * registered as the asic copy callback.
3115 */
3116int r600_copy_dma(struct radeon_device *rdev,
3117 uint64_t src_offset, uint64_t dst_offset,
3118 unsigned num_gpu_pages,
3119 struct radeon_fence **fence)
3120{
3121 struct radeon_semaphore *sem = NULL;
3122 int ring_index = rdev->asic->copy.dma_ring_index;
3123 struct radeon_ring *ring = &rdev->ring[ring_index];
3124 u32 size_in_dw, cur_size_in_dw;
3125 int i, num_loops;
3126 int r = 0;
3127
3128 r = radeon_semaphore_create(rdev, &sem);
3129 if (r) {
3130 DRM_ERROR("radeon: moving bo (%d).\n", r);
3131 return r;
3132 }
3133
3134 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]3135 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
3136 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3137 if (r) {
3138 DRM_ERROR("radeon: moving bo (%d).\n", r);
3139 radeon_semaphore_free(rdev, &sem, NULL);
3140 return r;
3141 }
3142
3143 if (radeon_fence_need_sync(*fence, ring->idx)) {
3144 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3145 ring->idx);
3146 radeon_fence_note_sync(*fence, ring->idx);
3147 } else {
3148 radeon_semaphore_free(rdev, &sem, NULL);
3149 }
3150
3151 for (i = 0; i < num_loops; i++) {
3152 cur_size_in_dw = size_in_dw;
Alex Deucher909d9eb2013-01-02 18:30:21 -0500[diff] [blame]3153 if (cur_size_in_dw > 0xFFFE)
3154 cur_size_in_dw = 0xFFFE;
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3155 size_in_dw -= cur_size_in_dw;
3156 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3157 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3158 radeon_ring_write(ring, src_offset & 0xfffffffc);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]3159 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
3160 (upper_32_bits(src_offset) & 0xff)));
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3161 src_offset += cur_size_in_dw * 4;
3162 dst_offset += cur_size_in_dw * 4;
3163 }
3164
3165 r = radeon_fence_emit(rdev, fence, ring->idx);
3166 if (r) {
3167 radeon_ring_unlock_undo(rdev, ring);
3168 return r;
3169 }
3170
3171 radeon_ring_unlock_commit(rdev, ring);
3172 radeon_semaphore_free(rdev, &sem, *fence);
3173
3174 return r;
3175}
3176
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3177int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3178 uint32_t tiling_flags, uint32_t pitch,
3179 uint32_t offset, uint32_t obj_size)
3180{
3181 /* FIXME: implement */
3182 return 0;
3183}
3184
3185void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3186{
3187 /* FIXME: implement */
3188}
3189
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400[diff] [blame]3190static int r600_startup(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3191{
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3192 struct radeon_ring *ring;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3193 int r;
3194
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]3195 /* enable pcie gen2 link */
3196 r600_pcie_gen2_enable(rdev);
3197
Alex Deucher779720a2009-12-09 19:31:44 -0500[diff] [blame]3198 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3199 r = r600_init_microcode(rdev);
3200 if (r) {
3201 DRM_ERROR("Failed to load firmware!\n");
3202 return r;
3203 }
3204 }
3205
Alex Deucher16cdf042011-10-28 10:30:02 -0400[diff] [blame]3206 r = r600_vram_scratch_init(rdev);
3207 if (r)
3208 return r;
3209
Jerome Glissea3c19452009-10-01 18:02:13 +0200[diff] [blame]3210 r600_mc_program(rdev);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]3211 if (rdev->flags & RADEON_IS_AGP) {
3212 r600_agp_enable(rdev);
3213 } else {
3214 r = r600_pcie_gart_enable(rdev);
3215 if (r)
3216 return r;
3217 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3218 r600_gpu_init(rdev);
Jerome Glissec38c7b62010-02-04 17:27:27 +0100[diff] [blame]3219 r = r600_blit_init(rdev);
3220 if (r) {
3221 r600_blit_fini(rdev);
Alex Deucher27cd7762012-02-23 17:53:42 -0500[diff] [blame]3222 rdev->asic->copy.copy = NULL;
Jerome Glissec38c7b62010-02-04 17:27:27 +0100[diff] [blame]3223 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3224 }
Alex Deucherb70d6bb2010-08-06 21:36:58 -0400[diff] [blame]3225
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3226 /* allocate wb buffer */
3227 r = radeon_wb_init(rdev);
3228 if (r)
3229 return r;
3230
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000[diff] [blame]3231 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3232 if (r) {
3233 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3234 return r;
3235 }
3236
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3237 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3238 if (r) {
3239 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3240 return r;
3241 }
3242
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3243 /* Enable IRQ */
Adis Hamziće49f3952013-06-02 16:47:54 +0200[diff] [blame]3244 if (!rdev->irq.installed) {
3245 r = radeon_irq_kms_init(rdev);
3246 if (r)
3247 return r;
3248 }
3249
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3250 r = r600_irq_init(rdev);
3251 if (r) {
3252 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3253 radeon_irq_kms_fini(rdev);
3254 return r;
3255 }
3256 r600_irq_set(rdev);
3257
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3258 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]3259 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
Alex Deucher78c55602011-11-17 14:25:56 -0500[diff] [blame]3260 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3261 0, 0xfffff, RADEON_CP_PACKET2);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3262 if (r)
3263 return r;
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3264
3265 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3266 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3267 DMA_RB_RPTR, DMA_RB_WPTR,
3268 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3269 if (r)
3270 return r;
3271
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3272 r = r600_cp_load_microcode(rdev);
3273 if (r)
3274 return r;
3275 r = r600_cp_resume(rdev);
3276 if (r)
3277 return r;
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3278
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3279 r = r600_dma_resume(rdev);
3280 if (r)
3281 return r;
3282
Christian König2898c342012-07-05 11:55:34 +0200[diff] [blame]3283 r = radeon_ib_pool_init(rdev);
3284 if (r) {
3285 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500[diff] [blame]3286 return r;
Christian König2898c342012-07-05 11:55:34 +0200[diff] [blame]3287 }
Jerome Glisseb15ba512011-11-15 11:48:34 -0500[diff] [blame]3288
Alex Deucherd4e30ef2012-06-04 17:18:51 -0400[diff] [blame]3289 r = r600_audio_init(rdev);
3290 if (r) {
3291 DRM_ERROR("radeon: audio init failed\n");
3292 return r;
3293 }
3294
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3295 return 0;
3296}
3297
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]3298void r600_vga_set_state(struct radeon_device *rdev, bool state)
3299{
3300 uint32_t temp;
3301
3302 temp = RREG32(CONFIG_CNTL);
3303 if (state == false) {
3304 temp &= ~(1<<0);
3305 temp |= (1<<1);
3306 } else {
3307 temp &= ~(1<<1);
3308 }
3309 WREG32(CONFIG_CNTL, temp);
3310}
3311
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3312int r600_resume(struct radeon_device *rdev)
3313{
3314 int r;
3315
Jerome Glisse1a029b72009-10-06 19:04:30 +0200[diff] [blame]3316 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3317 * posting will perform necessary task to bring back GPU into good
3318 * shape.
3319 */
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3320 /* post card */
Jerome Glissee7d40b92009-10-01 18:02:15 +0200[diff] [blame]3321 atom_asic_init(rdev->mode_info.atom_context);
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3322
Jerome Glisseb15ba512011-11-15 11:48:34 -0500[diff] [blame]3323 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3324 r = r600_startup(rdev);
3325 if (r) {
3326 DRM_ERROR("r600 startup failed on resume\n");
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500[diff] [blame]3327 rdev->accel_working = false;
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3328 return r;
3329 }
3330
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3331 return r;
3332}
3333
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3334int r600_suspend(struct radeon_device *rdev)
3335{
Rafał Miłecki38fd2c62010-01-28 18:16:30 +0100[diff] [blame]3336 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3337 r600_cp_stop(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3338 r600_dma_stop(rdev);
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]3339 r600_irq_suspend(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3340 radeon_wb_disable(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]3341 r600_pcie_gart_disable(rdev);
Alex Deucher6ddddfe2011-10-14 10:51:22 -0400[diff] [blame]3342
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3343 return 0;
3344}
3345
3346/* Plan is to move initialization in that function and use
3347 * helper function so that radeon_device_init pretty much
3348 * do nothing more than calling asic specific function. This
3349 * should also allow to remove a bunch of callback function
3350 * like vram_info.
3351 */
3352int r600_init(struct radeon_device *rdev)
3353{
3354 int r;
3355
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3356 if (r600_debugfs_mc_info_init(rdev)) {
3357 DRM_ERROR("Failed to register debugfs file for mc !\n");
3358 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3359 /* Read BIOS */
3360 if (!radeon_get_bios(rdev)) {
3361 if (ASIC_IS_AVIVO(rdev))
3362 return -EINVAL;
3363 }
3364 /* Must be an ATOMBIOS */
Jerome Glissee7d40b92009-10-01 18:02:15 +0200[diff] [blame]3365 if (!rdev->is_atom_bios) {
3366 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3367 return -EINVAL;
Jerome Glissee7d40b92009-10-01 18:02:15 +0200[diff] [blame]3368 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3369 r = radeon_atombios_init(rdev);
3370 if (r)
3371 return r;
3372 /* Post card if necessary */
Alex Deucherfd909c32011-01-11 18:08:59 -0500[diff] [blame]3373 if (!radeon_card_posted(rdev)) {
Dave Airlie72542d72009-12-01 14:06:31 +1000[diff] [blame]3374 if (!rdev->bios) {
3375 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3376 return -EINVAL;
3377 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3378 DRM_INFO("GPU not posted. posting now...\n");
3379 atom_asic_init(rdev->mode_info.atom_context);
3380 }
3381 /* Initialize scratch registers */
3382 r600_scratch_init(rdev);
3383 /* Initialize surface registers */
3384 radeon_surface_init(rdev);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]3385 /* Initialize clocks */
Michel Dänzer5e6dde72009-09-17 09:42:28 +0200[diff] [blame]3386 radeon_get_clock_info(rdev->ddev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3387 /* Fence driver */
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000[diff] [blame]3388 r = radeon_fence_driver_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3389 if (r)
3390 return r;
Jerome Glisse700a0cc2010-01-13 15:16:38 +0100[diff] [blame]3391 if (rdev->flags & RADEON_IS_AGP) {
3392 r = radeon_agp_init(rdev);
3393 if (r)
3394 radeon_agp_disable(rdev);
3395 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3396 r = r600_mc_init(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +0200[diff] [blame]3397 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3398 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3399 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3400 r = radeon_bo_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3401 if (r)
3402 return r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3403
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]3404 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3405 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3406
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3407 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3408 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3409
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3410 rdev->ih.ring_obj = NULL;
3411 r600_ih_ring_init(rdev, 64 * 1024);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3412
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]3413 r = r600_pcie_gart_init(rdev);
3414 if (r)
3415 return r;
3416
Alex Deucher779720a2009-12-09 19:31:44 -0500[diff] [blame]3417 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +1000[diff] [blame]3418 r = r600_startup(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3419 if (r) {
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]3420 dev_err(rdev->dev, "disabling GPU acceleration\n");
3421 r600_cp_fini(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3422 r600_dma_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]3423 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3424 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200[diff] [blame]3425 radeon_ib_pool_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]3426 radeon_irq_kms_fini(rdev);
Jerome Glisse75c81292009-10-01 18:02:14 +0200[diff] [blame]3427 r600_pcie_gart_fini(rdev);
Jerome Glisse733289c2009-09-16 15:24:21 +0200[diff] [blame]3428 rdev->accel_working = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3429 }
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200[diff] [blame]3430
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3431 return 0;
3432}
3433
3434void r600_fini(struct radeon_device *rdev)
3435{
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200[diff] [blame]3436 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3437 r600_blit_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]3438 r600_cp_fini(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3439 r600_dma_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3440 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3441 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200[diff] [blame]3442 radeon_ib_pool_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3443 radeon_irq_kms_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200[diff] [blame]3444 r600_pcie_gart_fini(rdev);
Alex Deucher16cdf042011-10-28 10:30:02 -0400[diff] [blame]3445 r600_vram_scratch_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100[diff] [blame]3446 radeon_agp_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3447 radeon_gem_fini(rdev);
3448 radeon_fence_driver_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3449 radeon_bo_fini(rdev);
Jerome Glissee7d40b92009-10-01 18:02:15 +0200[diff] [blame]3450 radeon_atombios_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3451 kfree(rdev->bios);
3452 rdev->bios = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3453}
3454
3455
3456/*
3457 * CS stuff
3458 */
3459void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3460{
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]3461 struct radeon_ring *ring = &rdev->ring[ib->ring];
Alex Deucher89d35802012-07-17 14:02:31 -0400[diff] [blame]3462 u32 next_rptr;
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]3463
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]3464 if (ring->rptr_save_reg) {
Alex Deucher89d35802012-07-17 14:02:31 -0400[diff] [blame]3465 next_rptr = ring->wptr + 3 + 4;
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]3466 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3467 radeon_ring_write(ring, ((ring->rptr_save_reg -
3468 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3469 radeon_ring_write(ring, next_rptr);
Alex Deucher89d35802012-07-17 14:02:31 -0400[diff] [blame]3470 } else if (rdev->wb.enabled) {
3471 next_rptr = ring->wptr + 5 + 4;
3472 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3473 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3474 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3475 radeon_ring_write(ring, next_rptr);
3476 radeon_ring_write(ring, 0);
Christian König45df6802012-07-06 16:22:55 +0200[diff] [blame]3477 }
3478
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]3479 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3480 radeon_ring_write(ring,
Cédric Cano4eace7f2011-02-11 19:45:38 -0500[diff] [blame]3481#ifdef __BIG_ENDIAN
3482 (2 << 0) |
3483#endif
3484 (ib->gpu_addr & 0xFFFFFFFC));
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]3485 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3486 radeon_ring_write(ring, ib->length_dw);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3487}
3488
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3489void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3490{
3491 struct radeon_ring *ring = &rdev->ring[ib->ring];
3492
3493 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3494 radeon_ring_write(ring, ib->gpu_addr);
3495 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3496 radeon_ring_write(ring, ib->length_dw);
3497}
3498
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]3499int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3500{
Jerome Glissef2e39222012-05-09 15:35:02 +0200[diff] [blame]3501 struct radeon_ib ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3502 uint32_t scratch;
3503 uint32_t tmp = 0;
3504 unsigned i;
3505 int r;
3506
3507 r = radeon_scratch_get(rdev, &scratch);
3508 if (r) {
3509 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3510 return r;
3511 }
3512 WREG32(scratch, 0xCAFEDEAD);
Christian König4bf3dd92012-08-06 18:57:44 +0200[diff] [blame]3513 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3514 if (r) {
3515 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +0200[diff] [blame]3516 goto free_scratch;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3517 }
Jerome Glissef2e39222012-05-09 15:35:02 +0200[diff] [blame]3518 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3519 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3520 ib.ptr[2] = 0xDEADBEEF;
3521 ib.length_dw = 3;
Christian König4ef72562012-07-13 13:06:00 +0200[diff] [blame]3522 r = radeon_ib_schedule(rdev, &ib, NULL);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3523 if (r) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3524 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +0200[diff] [blame]3525 goto free_ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3526 }
Jerome Glissef2e39222012-05-09 15:35:02 +0200[diff] [blame]3527 r = radeon_fence_wait(ib.fence, false);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3528 if (r) {
3529 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +0200[diff] [blame]3530 goto free_ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3531 }
3532 for (i = 0; i < rdev->usec_timeout; i++) {
3533 tmp = RREG32(scratch);
3534 if (tmp == 0xDEADBEEF)
3535 break;
3536 DRM_UDELAY(1);
3537 }
3538 if (i < rdev->usec_timeout) {
Jerome Glissef2e39222012-05-09 15:35:02 +0200[diff] [blame]3539 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3540 } else {
Daniel J Blueman4417d7f2010-09-22 17:57:19 +0100[diff] [blame]3541 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3542 scratch, tmp);
3543 r = -EINVAL;
3544 }
Michel Dänzeraf026c52012-09-20 10:31:10 +0200[diff] [blame]3545free_ib:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3546 radeon_ib_free(rdev, &ib);
Michel Dänzeraf026c52012-09-20 10:31:10 +0200[diff] [blame]3547free_scratch:
3548 radeon_scratch_free(rdev, scratch);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3549 return r;
3550}
3551
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3552/**
3553 * r600_dma_ib_test - test an IB on the DMA engine
3554 *
3555 * @rdev: radeon_device pointer
3556 * @ring: radeon_ring structure holding ring information
3557 *
3558 * Test a simple IB in the DMA ring (r6xx-SI).
3559 * Returns 0 on success, error on failure.
3560 */
3561int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3562{
3563 struct radeon_ib ib;
3564 unsigned i;
3565 int r;
3566 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3567 u32 tmp = 0;
3568
3569 if (!ptr) {
3570 DRM_ERROR("invalid vram scratch pointer\n");
3571 return -EINVAL;
3572 }
3573
3574 tmp = 0xCAFEDEAD;
3575 writel(tmp, ptr);
3576
3577 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3578 if (r) {
3579 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3580 return r;
3581 }
3582
3583 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3584 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3585 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3586 ib.ptr[3] = 0xDEADBEEF;
3587 ib.length_dw = 4;
3588
3589 r = radeon_ib_schedule(rdev, &ib, NULL);
3590 if (r) {
3591 radeon_ib_free(rdev, &ib);
3592 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3593 return r;
3594 }
3595 r = radeon_fence_wait(ib.fence, false);
3596 if (r) {
3597 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3598 return r;
3599 }
3600 for (i = 0; i < rdev->usec_timeout; i++) {
3601 tmp = readl(ptr);
3602 if (tmp == 0xDEADBEEF)
3603 break;
3604 DRM_UDELAY(1);
3605 }
3606 if (i < rdev->usec_timeout) {
3607 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3608 } else {
3609 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3610 r = -EINVAL;
3611 }
3612 radeon_ib_free(rdev, &ib);
3613 return r;
3614}
3615
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3616int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3617{
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3618 struct radeon_fence *fence = NULL;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3619 int r;
3620
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3621 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3622 if (r) {
3623 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3624 return r;
3625 }
3626
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3627 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3628 if (r) {
3629 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3630 goto error;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3631 }
3632
3633 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3634 if (r) {
3635 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3636 goto error;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3637 }
3638
3639 r = radeon_fence_wait(fence, false);
3640 if (r) {
3641 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3642 goto error;
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3643 }
3644 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3645error:
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3646 radeon_fence_unref(&fence);
Christian Königb05e9e42013-04-19 16:14:19 +0200[diff] [blame]3647 radeon_set_uvd_clocks(rdev, 0, 0);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]3648 return r;
3649}
3650
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3651/**
3652 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3653 *
3654 * @rdev: radeon_device pointer
3655 * @ib: IB object to schedule
3656 *
3657 * Schedule an IB in the DMA ring (r6xx-r7xx).
3658 */
3659void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3660{
3661 struct radeon_ring *ring = &rdev->ring[ib->ring];
3662
3663 if (rdev->wb.enabled) {
3664 u32 next_rptr = ring->wptr + 4;
3665 while ((next_rptr & 7) != 5)
3666 next_rptr++;
3667 next_rptr += 3;
3668 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3669 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3670 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3671 radeon_ring_write(ring, next_rptr);
3672 }
3673
3674 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3675 * Pad as necessary with NOPs.
3676 */
3677 while ((ring->wptr & 7) != 5)
3678 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3679 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3680 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3681 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3682
3683}
3684
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3685/*
3686 * Interrupts
3687 *
3688 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3689 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3690 * writing to the ring and the GPU consuming, the GPU writes to the ring
3691 * and host consumes. As the host irq handler processes interrupts, it
3692 * increments the rptr. When the rptr catches up with the wptr, all the
3693 * current interrupts have been processed.
3694 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3695
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3696void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3697{
3698 u32 rb_bufsz;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]3699
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3700 /* Align ring size */
3701 rb_bufsz = drm_order(ring_size / 4);
3702 ring_size = (1 << rb_bufsz) * 4;
3703 rdev->ih.ring_size = ring_size;
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]3704 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3705 rdev->ih.rptr = 0;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3706}
3707
Alex Deucher25a857f2012-03-20 17:18:22 -0400[diff] [blame]3708int r600_ih_ring_alloc(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3709{
3710 int r;
3711
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3712 /* Allocate ring buffer */
3713 if (rdev->ih.ring_obj == NULL) {
Daniel Vetter441921d2011-02-18 17:59:16 +0100[diff] [blame]3714 r = radeon_bo_create(rdev, rdev->ih.ring_size,
Alex Deucher268b2512010-11-17 19:00:26 -0500[diff] [blame]3715 PAGE_SIZE, true,
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3716 RADEON_GEM_DOMAIN_GTT,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400[diff] [blame]3717 NULL, &rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3718 if (r) {
3719 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3720 return r;
3721 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3722 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3723 if (unlikely(r != 0))
3724 return r;
3725 r = radeon_bo_pin(rdev->ih.ring_obj,
3726 RADEON_GEM_DOMAIN_GTT,
3727 &rdev->ih.gpu_addr);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3728 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3729 radeon_bo_unreserve(rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3730 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3731 return r;
3732 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3733 r = radeon_bo_kmap(rdev->ih.ring_obj,
3734 (void **)&rdev->ih.ring);
3735 radeon_bo_unreserve(rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3736 if (r) {
3737 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3738 return r;
3739 }
3740 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3741 return 0;
3742}
3743
Alex Deucher25a857f2012-03-20 17:18:22 -0400[diff] [blame]3744void r600_ih_ring_fini(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3745{
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3746 int r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3747 if (rdev->ih.ring_obj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100[diff] [blame]3748 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3749 if (likely(r == 0)) {
3750 radeon_bo_kunmap(rdev->ih.ring_obj);
3751 radeon_bo_unpin(rdev->ih.ring_obj);
3752 radeon_bo_unreserve(rdev->ih.ring_obj);
3753 }
3754 radeon_bo_unref(&rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3755 rdev->ih.ring = NULL;
3756 rdev->ih.ring_obj = NULL;
3757 }
3758}
3759
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]3760void r600_rlc_stop(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3761{
3762
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]3763 if ((rdev->family >= CHIP_RV770) &&
3764 (rdev->family <= CHIP_RV740)) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3765 /* r7xx asics need to soft reset RLC before halting */
3766 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3767 RREG32(SRBM_SOFT_RESET);
Arnd Bergmann4de833c2012-04-05 12:58:22 -0600[diff] [blame]3768 mdelay(15);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3769 WREG32(SRBM_SOFT_RESET, 0);
3770 RREG32(SRBM_SOFT_RESET);
3771 }
3772
3773 WREG32(RLC_CNTL, 0);
3774}
3775
3776static void r600_rlc_start(struct radeon_device *rdev)
3777{
3778 WREG32(RLC_CNTL, RLC_ENABLE);
3779}
3780
3781static int r600_rlc_init(struct radeon_device *rdev)
3782{
3783 u32 i;
3784 const __be32 *fw_data;
3785
3786 if (!rdev->rlc_fw)
3787 return -EINVAL;
3788
3789 r600_rlc_stop(rdev);
3790
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3791 WREG32(RLC_HB_CNTL, 0);
Alex Deucherc420c742012-03-20 17:18:39 -0400[diff] [blame]3792
3793 if (rdev->family == CHIP_ARUBA) {
3794 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3795 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3796 }
3797 if (rdev->family <= CHIP_CAYMAN) {
3798 WREG32(RLC_HB_BASE, 0);
3799 WREG32(RLC_HB_RPTR, 0);
3800 WREG32(RLC_HB_WPTR, 0);
3801 }
Alex Deucher12727802011-03-02 20:07:32 -0500[diff] [blame]3802 if (rdev->family <= CHIP_CAICOS) {
3803 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3804 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3805 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3806 WREG32(RLC_MC_CNTL, 0);
3807 WREG32(RLC_UCODE_CNTL, 0);
3808
3809 fw_data = (const __be32 *)rdev->rlc_fw->data;
Alex Deucherc420c742012-03-20 17:18:39 -0400[diff] [blame]3810 if (rdev->family >= CHIP_ARUBA) {
3811 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3812 WREG32(RLC_UCODE_ADDR, i);
3813 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3814 }
3815 } else if (rdev->family >= CHIP_CAYMAN) {
Alex Deucher12727802011-03-02 20:07:32 -0500[diff] [blame]3816 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3817 WREG32(RLC_UCODE_ADDR, i);
3818 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3819 }
3820 } else if (rdev->family >= CHIP_CEDAR) {
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]3821 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3822 WREG32(RLC_UCODE_ADDR, i);
3823 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3824 }
3825 } else if (rdev->family >= CHIP_RV770) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3826 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3827 WREG32(RLC_UCODE_ADDR, i);
3828 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3829 }
3830 } else {
Alex Deucher138e4e12013-01-11 15:33:13 -0500[diff] [blame^]3831 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3832 WREG32(RLC_UCODE_ADDR, i);
3833 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3834 }
3835 }
3836 WREG32(RLC_UCODE_ADDR, 0);
3837
3838 r600_rlc_start(rdev);
3839
3840 return 0;
3841}
3842
3843static void r600_enable_interrupts(struct radeon_device *rdev)
3844{
3845 u32 ih_cntl = RREG32(IH_CNTL);
3846 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3847
3848 ih_cntl |= ENABLE_INTR;
3849 ih_rb_cntl |= IH_RB_ENABLE;
3850 WREG32(IH_CNTL, ih_cntl);
3851 WREG32(IH_RB_CNTL, ih_rb_cntl);
3852 rdev->ih.enabled = true;
3853}
3854
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]3855void r600_disable_interrupts(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3856{
3857 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3858 u32 ih_cntl = RREG32(IH_CNTL);
3859
3860 ih_rb_cntl &= ~IH_RB_ENABLE;
3861 ih_cntl &= ~ENABLE_INTR;
3862 WREG32(IH_RB_CNTL, ih_rb_cntl);
3863 WREG32(IH_CNTL, ih_cntl);
3864 /* set rptr, wptr to 0 */
3865 WREG32(IH_RB_RPTR, 0);
3866 WREG32(IH_RB_WPTR, 0);
3867 rdev->ih.enabled = false;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3868 rdev->ih.rptr = 0;
3869}
3870
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3871static void r600_disable_interrupt_state(struct radeon_device *rdev)
3872{
3873 u32 tmp;
3874
Alex Deucher3555e532010-10-08 12:09:12 -0400[diff] [blame]3875 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]3876 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3877 WREG32(DMA_CNTL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3878 WREG32(GRBM_INT_CNTL, 0);
3879 WREG32(DxMODE_INT_MASK, 0);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]3880 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3881 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3882 if (ASIC_IS_DCE3(rdev)) {
3883 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3884 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3885 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3886 WREG32(DC_HPD1_INT_CONTROL, tmp);
3887 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3888 WREG32(DC_HPD2_INT_CONTROL, tmp);
3889 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3890 WREG32(DC_HPD3_INT_CONTROL, tmp);
3891 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3892 WREG32(DC_HPD4_INT_CONTROL, tmp);
3893 if (ASIC_IS_DCE32(rdev)) {
3894 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -0400[diff] [blame]3895 WREG32(DC_HPD5_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3896 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -0400[diff] [blame]3897 WREG32(DC_HPD6_INT_CONTROL, tmp);
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]3898 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3899 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3900 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3901 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]3902 } else {
3903 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3904 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3905 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3906 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3907 }
3908 } else {
3909 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3910 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3911 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -0400[diff] [blame]3912 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3913 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -0400[diff] [blame]3914 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3915 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -0400[diff] [blame]3916 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]3917 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3918 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3919 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3920 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]3921 }
3922}
3923
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3924int r600_irq_init(struct radeon_device *rdev)
3925{
3926 int ret = 0;
3927 int rb_bufsz;
3928 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3929
3930 /* allocate ring */
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]3931 ret = r600_ih_ring_alloc(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3932 if (ret)
3933 return ret;
3934
3935 /* disable irqs */
3936 r600_disable_interrupts(rdev);
3937
3938 /* init rlc */
3939 ret = r600_rlc_init(rdev);
3940 if (ret) {
3941 r600_ih_ring_fini(rdev);
3942 return ret;
3943 }
3944
3945 /* setup interrupt control */
3946 /* set dummy read address to ring address */
3947 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3948 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3949 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3950 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3951 */
3952 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3953 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3954 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3955 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3956
3957 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3958 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3959
3960 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3961 IH_WPTR_OVERFLOW_CLEAR |
3962 (rb_bufsz << 1));
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]3963
3964 if (rdev->wb.enabled)
3965 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3966
3967 /* set the writeback address whether it's enabled or not */
3968 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3969 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3970
3971 WREG32(IH_RB_CNTL, ih_rb_cntl);
3972
3973 /* set rptr, wptr to 0 */
3974 WREG32(IH_RB_RPTR, 0);
3975 WREG32(IH_RB_WPTR, 0);
3976
3977 /* Default settings for IH_CNTL (disabled at first) */
3978 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3979 /* RPTR_REARM only works if msi's are enabled */
3980 if (rdev->msi_enabled)
3981 ih_cntl |= RPTR_REARM;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3982 WREG32(IH_CNTL, ih_cntl);
3983
3984 /* force the active interrupt state to all disabled */
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]3985 if (rdev->family >= CHIP_CEDAR)
3986 evergreen_disable_interrupt_state(rdev);
3987 else
3988 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3989
Dave Airlie20998102012-04-03 11:53:05 +0100[diff] [blame]3990 /* at this point everything should be setup correctly to enable master */
3991 pci_set_master(rdev->pdev);
3992
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]3993 /* enable irqs */
3994 r600_enable_interrupts(rdev);
3995
3996 return ret;
3997}
3998
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]3999void r600_irq_suspend(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4000{
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]4001 r600_irq_disable(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4002 r600_rlc_stop(rdev);
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]4003}
4004
4005void r600_irq_fini(struct radeon_device *rdev)
4006{
4007 r600_irq_suspend(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4008 r600_ih_ring_fini(rdev);
4009}
4010
4011int r600_irq_set(struct radeon_device *rdev)
4012{
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4013 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
4014 u32 mode_int = 0;
4015 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
Alex Deucher2031f772010-04-22 12:52:11 -0400[diff] [blame]4016 u32 grbm_int_cntl = 0;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4017 u32 hdmi0, hdmi1;
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4018 u32 d1grph = 0, d2grph = 0;
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]4019 u32 dma_cntl;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4020
Jerome Glisse003e69f2010-01-07 15:39:14 +0100[diff] [blame]4021 if (!rdev->irq.installed) {
Joe Perchesfce7d612010-10-30 21:08:30 +0000[diff] [blame]4022 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
Jerome Glisse003e69f2010-01-07 15:39:14 +0100[diff] [blame]4023 return -EINVAL;
4024 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4025 /* don't enable anything if the ih is disabled */
Jerome Glisse79c2bbc2010-01-15 14:44:38 +0100[diff] [blame]4026 if (!rdev->ih.enabled) {
4027 r600_disable_interrupts(rdev);
4028 /* force the active interrupt state to all disabled */
4029 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4030 return 0;
Jerome Glisse79c2bbc2010-01-15 14:44:38 +0100[diff] [blame]4031 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4032
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4033 if (ASIC_IS_DCE3(rdev)) {
4034 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4035 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4036 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4037 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4038 if (ASIC_IS_DCE32(rdev)) {
4039 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4040 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4041 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4042 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4043 } else {
4044 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4045 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4046 }
4047 } else {
4048 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4049 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4050 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4051 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4052 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4053 }
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]4054 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4055
Christian Koenig736fc372012-05-17 19:52:00 +0200[diff] [blame]4056 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4057 DRM_DEBUG("r600_irq_set: sw int\n");
4058 cp_int_cntl |= RB_INT_ENABLE;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400[diff] [blame]4059 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4060 }
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]4061
4062 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4063 DRM_DEBUG("r600_irq_set: sw int dma\n");
4064 dma_cntl |= TRAP_ENABLE;
4065 }
4066
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4067 if (rdev->irq.crtc_vblank_int[0] ||
Christian Koenig736fc372012-05-17 19:52:00 +0200[diff] [blame]4068 atomic_read(&rdev->irq.pflip[0])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4069 DRM_DEBUG("r600_irq_set: vblank 0\n");
4070 mode_int |= D1MODE_VBLANK_INT_MASK;
4071 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4072 if (rdev->irq.crtc_vblank_int[1] ||
Christian Koenig736fc372012-05-17 19:52:00 +0200[diff] [blame]4073 atomic_read(&rdev->irq.pflip[1])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4074 DRM_DEBUG("r600_irq_set: vblank 1\n");
4075 mode_int |= D2MODE_VBLANK_INT_MASK;
4076 }
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4077 if (rdev->irq.hpd[0]) {
4078 DRM_DEBUG("r600_irq_set: hpd 1\n");
4079 hpd1 |= DC_HPDx_INT_EN;
4080 }
4081 if (rdev->irq.hpd[1]) {
4082 DRM_DEBUG("r600_irq_set: hpd 2\n");
4083 hpd2 |= DC_HPDx_INT_EN;
4084 }
4085 if (rdev->irq.hpd[2]) {
4086 DRM_DEBUG("r600_irq_set: hpd 3\n");
4087 hpd3 |= DC_HPDx_INT_EN;
4088 }
4089 if (rdev->irq.hpd[3]) {
4090 DRM_DEBUG("r600_irq_set: hpd 4\n");
4091 hpd4 |= DC_HPDx_INT_EN;
4092 }
4093 if (rdev->irq.hpd[4]) {
4094 DRM_DEBUG("r600_irq_set: hpd 5\n");
4095 hpd5 |= DC_HPDx_INT_EN;
4096 }
4097 if (rdev->irq.hpd[5]) {
4098 DRM_DEBUG("r600_irq_set: hpd 6\n");
4099 hpd6 |= DC_HPDx_INT_EN;
4100 }
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4101 if (rdev->irq.afmt[0]) {
4102 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4103 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4104 }
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4105 if (rdev->irq.afmt[1]) {
4106 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4107 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4108 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4109
4110 WREG32(CP_INT_CNTL, cp_int_cntl);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]4111 WREG32(DMA_CNTL, dma_cntl);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4112 WREG32(DxMODE_INT_MASK, mode_int);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4113 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
4114 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
Alex Deucher2031f772010-04-22 12:52:11 -0400[diff] [blame]4115 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4116 if (ASIC_IS_DCE3(rdev)) {
4117 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4118 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4119 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4120 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4121 if (ASIC_IS_DCE32(rdev)) {
4122 WREG32(DC_HPD5_INT_CONTROL, hpd5);
4123 WREG32(DC_HPD6_INT_CONTROL, hpd6);
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4124 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
4125 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4126 } else {
4127 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4128 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4129 }
4130 } else {
4131 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
4132 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
4133 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4134 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4135 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4136 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4137
4138 return 0;
4139}
4140
Andi Kleence580fa2011-10-13 16:08:47 -0700[diff] [blame]4141static void r600_irq_ack(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4142{
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4143 u32 tmp;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4144
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4145 if (ASIC_IS_DCE3(rdev)) {
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4146 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
4147 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
4148 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4149 if (ASIC_IS_DCE32(rdev)) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4150 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
4151 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4152 } else {
4153 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4154 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
4155 }
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4156 } else {
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4157 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4158 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4159 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4160 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4161 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4162 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4163 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
4164 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4165
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4166 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4167 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4168 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4169 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4170 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4171 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4172 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4173 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4174 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4175 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4176 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4177 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4178 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4179 if (ASIC_IS_DCE3(rdev)) {
4180 tmp = RREG32(DC_HPD1_INT_CONTROL);
4181 tmp |= DC_HPDx_INT_ACK;
4182 WREG32(DC_HPD1_INT_CONTROL, tmp);
4183 } else {
4184 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
4185 tmp |= DC_HPDx_INT_ACK;
4186 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
4187 }
4188 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4189 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4190 if (ASIC_IS_DCE3(rdev)) {
4191 tmp = RREG32(DC_HPD2_INT_CONTROL);
4192 tmp |= DC_HPDx_INT_ACK;
4193 WREG32(DC_HPD2_INT_CONTROL, tmp);
4194 } else {
4195 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
4196 tmp |= DC_HPDx_INT_ACK;
4197 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
4198 }
4199 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4200 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4201 if (ASIC_IS_DCE3(rdev)) {
4202 tmp = RREG32(DC_HPD3_INT_CONTROL);
4203 tmp |= DC_HPDx_INT_ACK;
4204 WREG32(DC_HPD3_INT_CONTROL, tmp);
4205 } else {
4206 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
4207 tmp |= DC_HPDx_INT_ACK;
4208 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
4209 }
4210 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4211 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4212 tmp = RREG32(DC_HPD4_INT_CONTROL);
4213 tmp |= DC_HPDx_INT_ACK;
4214 WREG32(DC_HPD4_INT_CONTROL, tmp);
4215 }
4216 if (ASIC_IS_DCE32(rdev)) {
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4217 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4218 tmp = RREG32(DC_HPD5_INT_CONTROL);
4219 tmp |= DC_HPDx_INT_ACK;
4220 WREG32(DC_HPD5_INT_CONTROL, tmp);
4221 }
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4222 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4223 tmp = RREG32(DC_HPD5_INT_CONTROL);
4224 tmp |= DC_HPDx_INT_ACK;
4225 WREG32(DC_HPD6_INT_CONTROL, tmp);
4226 }
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4227 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4228 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4229 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4230 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4231 }
4232 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4233 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4234 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200[diff] [blame]4235 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4236 }
4237 } else {
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4238 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4239 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4240 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4241 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4242 }
4243 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4244 if (ASIC_IS_DCE3(rdev)) {
4245 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4246 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4247 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4248 } else {
4249 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4250 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4251 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4252 }
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4253 }
4254 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4255}
4256
4257void r600_irq_disable(struct radeon_device *rdev)
4258{
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4259 r600_disable_interrupts(rdev);
4260 /* Wait and acknowledge irq */
4261 mdelay(1);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4262 r600_irq_ack(rdev);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4263 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4264}
4265
Andi Kleence580fa2011-10-13 16:08:47 -0700[diff] [blame]4266static u32 r600_get_ih_wptr(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4267{
4268 u32 wptr, tmp;
4269
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]4270 if (rdev->wb.enabled)
Cédric Cano204ae242011-04-19 11:07:13 -0400[diff] [blame]4271 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
Alex Deucher724c80e2010-08-27 18:25:25 -0400[diff] [blame]4272 else
4273 wptr = RREG32(IH_RB_WPTR);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4274
4275 if (wptr & RB_OVERFLOW) {
Jerome Glisse7924e5e2010-01-15 14:44:39 +0100[diff] [blame]4276 /* When a ring buffer overflow happen start parsing interrupt
4277 * from the last not overwritten vector (wptr + 16). Hopefully
4278 * this should allow us to catchup.
4279 */
4280 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4281 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
4282 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4283 tmp = RREG32(IH_RB_CNTL);
4284 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4285 WREG32(IH_RB_CNTL, tmp);
4286 }
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]4287 return (wptr & rdev->ih.ptr_mask);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4288}
4289
4290/* r600 IV Ring
4291 * Each IV ring entry is 128 bits:
4292 * [7:0] - interrupt source id
4293 * [31:8] - reserved
4294 * [59:32] - interrupt source data
4295 * [127:60] - reserved
4296 *
4297 * The basic interrupt vector entries
4298 * are decoded as follows:
4299 * src_id src_data description
4300 * 1 0 D1 Vblank
4301 * 1 1 D1 Vline
4302 * 5 0 D2 Vblank
4303 * 5 1 D2 Vline
4304 * 19 0 FP Hot plug detection A
4305 * 19 1 FP Hot plug detection B
4306 * 19 2 DAC A auto-detection
4307 * 19 3 DAC B auto-detection
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4308 * 21 4 HDMI block A
4309 * 21 5 HDMI block B
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4310 * 176 - CP_INT RB
4311 * 177 - CP_INT IB1
4312 * 178 - CP_INT IB2
4313 * 181 - EOP Interrupt
4314 * 233 - GUI Idle
4315 *
4316 * Note, these are based on r600 and may need to be
4317 * adjusted or added to on newer asics
4318 */
4319
4320int r600_irq_process(struct radeon_device *rdev)
4321{
Dave Airlie682f1a52011-06-18 03:59:51 +0000[diff] [blame]4322 u32 wptr;
4323 u32 rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4324 u32 src_id, src_data;
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4325 u32 ring_index;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4326 bool queue_hotplug = false;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4327 bool queue_hdmi = false;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4328
Dave Airlie682f1a52011-06-18 03:59:51 +0000[diff] [blame]4329 if (!rdev->ih.enabled || rdev->shutdown)
Jerome Glisse79c2bbc2010-01-15 14:44:38 +0100[diff] [blame]4330 return IRQ_NONE;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4331
Benjamin Herrenschmidtf6a56932011-07-13 06:28:22 +0000[diff] [blame]4332 /* No MSIs, need a dummy read to flush PCI DMAs */
4333 if (!rdev->msi_enabled)
4334 RREG32(IH_RB_WPTR);
4335
Dave Airlie682f1a52011-06-18 03:59:51 +0000[diff] [blame]4336 wptr = r600_get_ih_wptr(rdev);
Christian Koenigc20dc362012-05-16 21:45:24 +0200[diff] [blame]4337
4338restart_ih:
4339 /* is somebody else already processing irqs? */
4340 if (atomic_xchg(&rdev->ih.lock, 1))
4341 return IRQ_NONE;
4342
Dave Airlie682f1a52011-06-18 03:59:51 +0000[diff] [blame]4343 rptr = rdev->ih.rptr;
4344 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4345
Benjamin Herrenschmidt964f6642011-07-13 16:28:19 +1000[diff] [blame]4346 /* Order reading of wptr vs. reading of IH ring data */
4347 rmb();
4348
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4349 /* display interrupts */
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4350 r600_irq_ack(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4351
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4352 while (rptr != wptr) {
4353 /* wptr/rptr are in bytes! */
4354 ring_index = rptr / 4;
Cédric Cano4eace7f2011-02-11 19:45:38 -0500[diff] [blame]4355 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4356 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4357
4358 switch (src_id) {
4359 case 1: /* D1 vblank/vline */
4360 switch (src_data) {
4361 case 0: /* D1 vblank */
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4362 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4363 if (rdev->irq.crtc_vblank_int[0]) {
4364 drm_handle_vblank(rdev->ddev, 0);
4365 rdev->pm.vblank_sync = true;
4366 wake_up(&rdev->irq.vblank_queue);
4367 }
Christian Koenig736fc372012-05-17 19:52:00 +0200[diff] [blame]4368 if (atomic_read(&rdev->irq.pflip[0]))
Mario Kleiner3e4ea742010-11-21 10:59:02 -0500[diff] [blame]4369 radeon_crtc_handle_flip(rdev, 0);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4370 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4371 DRM_DEBUG("IH: D1 vblank\n");
4372 }
4373 break;
4374 case 1: /* D1 vline */
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4375 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4376 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4377 DRM_DEBUG("IH: D1 vline\n");
4378 }
4379 break;
4380 default:
Alex Deucherb0425892010-01-11 19:47:38 -0500[diff] [blame]4381 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4382 break;
4383 }
4384 break;
4385 case 5: /* D2 vblank/vline */
4386 switch (src_data) {
4387 case 0: /* D2 vblank */
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4388 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4389 if (rdev->irq.crtc_vblank_int[1]) {
4390 drm_handle_vblank(rdev->ddev, 1);
4391 rdev->pm.vblank_sync = true;
4392 wake_up(&rdev->irq.vblank_queue);
4393 }
Christian Koenig736fc372012-05-17 19:52:00 +0200[diff] [blame]4394 if (atomic_read(&rdev->irq.pflip[1]))
Mario Kleiner3e4ea742010-11-21 10:59:02 -0500[diff] [blame]4395 radeon_crtc_handle_flip(rdev, 1);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4396 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4397 DRM_DEBUG("IH: D2 vblank\n");
4398 }
4399 break;
4400 case 1: /* D1 vline */
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4401 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4402 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4403 DRM_DEBUG("IH: D2 vline\n");
4404 }
4405 break;
4406 default:
Alex Deucherb0425892010-01-11 19:47:38 -0500[diff] [blame]4407 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4408 break;
4409 }
4410 break;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4411 case 19: /* HPD/DAC hotplug */
4412 switch (src_data) {
4413 case 0:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4414 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4415 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4416 queue_hotplug = true;
4417 DRM_DEBUG("IH: HPD1\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4418 }
4419 break;
4420 case 1:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4421 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4422 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4423 queue_hotplug = true;
4424 DRM_DEBUG("IH: HPD2\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4425 }
4426 break;
4427 case 4:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4428 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4429 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4430 queue_hotplug = true;
4431 DRM_DEBUG("IH: HPD3\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4432 }
4433 break;
4434 case 5:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4435 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4436 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4437 queue_hotplug = true;
4438 DRM_DEBUG("IH: HPD4\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4439 }
4440 break;
4441 case 10:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4442 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4443 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4444 queue_hotplug = true;
4445 DRM_DEBUG("IH: HPD5\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4446 }
4447 break;
4448 case 12:
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]4449 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4450 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4451 queue_hotplug = true;
4452 DRM_DEBUG("IH: HPD6\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4453 }
4454 break;
4455 default:
Alex Deucherb0425892010-01-11 19:47:38 -0500[diff] [blame]4456 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500[diff] [blame]4457 break;
4458 }
4459 break;
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4460 case 21: /* hdmi */
4461 switch (src_data) {
4462 case 4:
4463 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4464 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4465 queue_hdmi = true;
4466 DRM_DEBUG("IH: HDMI0\n");
4467 }
4468 break;
4469 case 5:
4470 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4471 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4472 queue_hdmi = true;
4473 DRM_DEBUG("IH: HDMI1\n");
4474 }
4475 break;
4476 default:
4477 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4478 break;
4479 }
Christian Koenigf2594932010-04-10 03:13:16 +0200[diff] [blame]4480 break;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4481 case 176: /* CP_INT in ring buffer */
4482 case 177: /* CP_INT in IB1 */
4483 case 178: /* CP_INT in IB2 */
4484 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
Alex Deucher74652802011-08-25 13:39:48 -0400[diff] [blame]4485 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4486 break;
4487 case 181: /* CP EOP event */
4488 DRM_DEBUG("IH: CP EOP\n");
Alex Deucher74652802011-08-25 13:39:48 -0400[diff] [blame]4489 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4490 break;
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]4491 case 224: /* DMA trap event */
4492 DRM_DEBUG("IH: DMA trap\n");
4493 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4494 break;
Alex Deucher2031f772010-04-22 12:52:11 -0400[diff] [blame]4495 case 233: /* GUI IDLE */
Ilija Hadzic303c8052011-06-07 14:54:48 -0400[diff] [blame]4496 DRM_DEBUG("IH: GUI idle\n");
Alex Deucher2031f772010-04-22 12:52:11 -0400[diff] [blame]4497 break;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4498 default:
Alex Deucherb0425892010-01-11 19:47:38 -0500[diff] [blame]4499 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4500 break;
4501 }
4502
4503 /* wptr/rptr are in bytes! */
Jerome Glisse0c452492010-01-15 14:44:37 +0100[diff] [blame]4504 rptr += 16;
4505 rptr &= rdev->ih.ptr_mask;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4506 }
Alex Deucherd4877cf2009-12-04 16:56:37 -0500[diff] [blame]4507 if (queue_hotplug)
Tejun Heo32c87fc2011-01-03 14:49:32 +0100[diff] [blame]4508 schedule_work(&rdev->hotplug_work);
Alex Deucherf122c612012-03-30 08:59:57 -0400[diff] [blame]4509 if (queue_hdmi)
4510 schedule_work(&rdev->audio_work);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4511 rdev->ih.rptr = rptr;
4512 WREG32(IH_RB_RPTR, rdev->ih.rptr);
Christian Koenigc20dc362012-05-16 21:45:24 +0200[diff] [blame]4513 atomic_set(&rdev->ih.lock, 0);
4514
4515 /* make sure wptr hasn't changed while processing */
4516 wptr = r600_get_ih_wptr(rdev);
4517 if (wptr != rptr)
4518 goto restart_ih;
4519
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500[diff] [blame]4520 return IRQ_HANDLED;
4521}
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]4522
4523/*
4524 * Debugfs info
4525 */
4526#if defined(CONFIG_DEBUG_FS)
4527
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]4528static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4529{
4530 struct drm_info_node *node = (struct drm_info_node *) m->private;
4531 struct drm_device *dev = node->minor->dev;
4532 struct radeon_device *rdev = dev->dev_private;
4533
4534 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4535 DREG32_SYS(m, rdev, VM_L2_STATUS);
4536 return 0;
4537}
4538
4539static struct drm_info_list r600_mc_info_list[] = {
4540 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]4541};
4542#endif
4543
4544int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4545{
4546#if defined(CONFIG_DEBUG_FS)
4547 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4548#else
4549 return 0;
4550#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]4551}
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]4552
4553/**
4554 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4555 * rdev: radeon device structure
4556 * bo: buffer object struct which userspace is waiting for idle
4557 *
4558 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4559 * through ring buffer, this leads to corruption in rendering, see
4560 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4561 * directly perform HDP flush by writing register through MMIO.
4562 */
4563void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4564{
Alex Deucher812d0462010-07-26 18:51:53 -0400[diff] [blame]4565 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
Alex Deucherf3886f82010-12-08 10:05:34 -0500[diff] [blame]4566 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4567 * This seems to cause problems on some AGP cards. Just use the old
4568 * method for them.
Alex Deucher812d0462010-07-26 18:51:53 -0400[diff] [blame]4569 */
Alex Deuchere4884592010-09-27 10:57:10 -0400[diff] [blame]4570 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
Alex Deucherf3886f82010-12-08 10:05:34 -0500[diff] [blame]4571 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
Alex Deucher87cbf8f2010-08-27 13:59:54 -0400[diff] [blame]4572 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
Alex Deucher812d0462010-07-26 18:51:53 -0400[diff] [blame]4573 u32 tmp;
4574
4575 WREG32(HDP_DEBUG1, 0);
4576 tmp = readl((void __iomem *)ptr);
4577 } else
4578 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]4579}
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4580
4581void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4582{
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4583 u32 link_width_cntl, mask;
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4584
4585 if (rdev->flags & RADEON_IS_IGP)
4586 return;
4587
4588 if (!(rdev->flags & RADEON_IS_PCIE))
4589 return;
4590
4591 /* x2 cards have a special sequence */
4592 if (ASIC_IS_X2(rdev))
4593 return;
4594
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4595 radeon_gui_idle(rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4596
4597 switch (lanes) {
4598 case 0:
4599 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4600 break;
4601 case 1:
4602 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4603 break;
4604 case 2:
4605 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4606 break;
4607 case 4:
4608 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4609 break;
4610 case 8:
4611 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4612 break;
4613 case 12:
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4614 /* not actually supported */
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4615 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4616 break;
4617 case 16:
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4618 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4619 break;
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4620 default:
4621 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4622 return;
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4623 }
4624
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4625 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4626 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4627 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4628 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4629 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4630
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4631 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4632}
4633
4634int r600_get_pcie_lanes(struct radeon_device *rdev)
4635{
4636 u32 link_width_cntl;
4637
4638 if (rdev->flags & RADEON_IS_IGP)
4639 return 0;
4640
4641 if (!(rdev->flags & RADEON_IS_PCIE))
4642 return 0;
4643
4644 /* x2 cards have a special sequence */
4645 if (ASIC_IS_X2(rdev))
4646 return 0;
4647
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4648 radeon_gui_idle(rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4649
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4650 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4651
4652 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4653 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4654 return 1;
4655 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4656 return 2;
4657 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4658 return 4;
4659 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4660 return 8;
Alex Deucherd5445a12013-03-18 18:52:13 -0400[diff] [blame]4661 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4662 /* not actually supported */
4663 return 12;
4664 case RADEON_PCIE_LC_LINK_WIDTH_X0:
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]4665 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4666 default:
4667 return 16;
4668 }
4669}
4670
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4671static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4672{
4673 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4674 u16 link_cntl2;
4675
Alex Deucherd42dd572011-01-12 20:05:11 -0500[diff] [blame]4676 if (radeon_pcie_gen2 == 0)
4677 return;
4678
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4679 if (rdev->flags & RADEON_IS_IGP)
4680 return;
4681
4682 if (!(rdev->flags & RADEON_IS_PCIE))
4683 return;
4684
4685 /* x2 cards have a special sequence */
4686 if (ASIC_IS_X2(rdev))
4687 return;
4688
4689 /* only RV6xx+ chips are supported */
4690 if (rdev->family <= CHIP_R600)
4691 return;
4692
Kleber Sacilotto de Souza7e0e4192013-05-03 19:43:13 -0300[diff] [blame]4693 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4694 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
Dave Airlie197bbb32012-06-27 08:35:54 +0100[diff] [blame]4695 return;
4696
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4697 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Alex Deucher3691fee2012-10-08 17:46:27 -0400[diff] [blame]4698 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4699 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4700 return;
4701 }
4702
Dave Airlie197bbb32012-06-27 08:35:54 +0100[diff] [blame]4703 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4704
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4705 /* 55 nm r6xx asics */
4706 if ((rdev->family == CHIP_RV670) ||
4707 (rdev->family == CHIP_RV620) ||
4708 (rdev->family == CHIP_RV635)) {
4709 /* advertise upconfig capability */
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4710 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4711 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4712 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4713 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4714 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4715 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4716 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4717 LC_RECONFIG_ARC_MISSING_ESCAPE);
4718 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4719 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4720 } else {
4721 link_width_cntl |= LC_UPCONFIGURE_DIS;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4722 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4723 }
4724 }
4725
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4726 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4727 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4728 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4729
4730 /* 55 nm r6xx asics */
4731 if ((rdev->family == CHIP_RV670) ||
4732 (rdev->family == CHIP_RV620) ||
4733 (rdev->family == CHIP_RV635)) {
4734 WREG32(MM_CFGREGS_CNTL, 0x8);
4735 link_cntl2 = RREG32(0x4088);
4736 WREG32(MM_CFGREGS_CNTL, 0);
4737 /* not supported yet */
4738 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4739 return;
4740 }
4741
4742 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4743 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4744 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4745 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4746 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4747 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4748
4749 tmp = RREG32(0x541c);
4750 WREG32(0x541c, tmp | 0x8);
4751 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4752 link_cntl2 = RREG16(0x4088);
4753 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4754 link_cntl2 |= 0x2;
4755 WREG16(0x4088, link_cntl2);
4756 WREG32(MM_CFGREGS_CNTL, 0);
4757
4758 if ((rdev->family == CHIP_RV670) ||
4759 (rdev->family == CHIP_RV620) ||
4760 (rdev->family == CHIP_RV635)) {
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4761 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4762 training_cntl &= ~LC_POINT_7_PLUS_EN;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4763 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4764 } else {
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4765 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4766 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4767 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4768 }
4769
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4770 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4771 speed_cntl |= LC_GEN2_EN_STRAP;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4772 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4773
4774 } else {
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4775 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4776 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4777 if (1)
4778 link_width_cntl |= LC_UPCONFIGURE_DIS;
4779 else
4780 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
Alex Deucher492d2b62012-10-25 16:06:59 -0400[diff] [blame]4781 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]4782 }
4783}
Marek Olšák6759a0a2012-08-09 16:34:17 +0200[diff] [blame]4784
4785/**
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]4786 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
Marek Olšák6759a0a2012-08-09 16:34:17 +0200[diff] [blame]4787 *
4788 * @rdev: radeon_device pointer
4789 *
4790 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4791 * Returns the 64 bit clock counter snapshot.
4792 */
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]4793uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
Marek Olšák6759a0a2012-08-09 16:34:17 +0200[diff] [blame]4794{
4795 uint64_t clock;
4796
4797 mutex_lock(&rdev->gpu_clock_mutex);
4798 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4799 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4800 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4801 mutex_unlock(&rdev->gpu_clock_mutex);
4802 return clock;
4803}