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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
Ralf Baechle010b8532006-01-29 18:42:08 +00005 * Copyright (C) 1994 - 2006 Ralf Baechle
Ralf Baechle41943182005-05-05 16:45:59 +00006 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Ralf Baechle70342282013-01-22 12:59:30 +01007 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010017#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/stddef.h>
Paul Gortmaker73bc2562011-07-23 16:30:40 -040019#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechle57599062007-02-18 19:07:31 +000021#include <asm/bugs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/cpu.h>
Maciej W. Rozyckif6843622015-04-03 23:27:26 +010023#include <asm/cpu-features.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020024#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <asm/fpu.h>
26#include <asm/mipsregs.h>
Paul Burton30ee6152014-03-27 10:57:30 +000027#include <asm/mipsmtregs.h>
Paul Burtona5e9a692014-01-27 15:23:10 +000028#include <asm/msa.h>
David Daney654f57b2008-09-23 00:07:16 -070029#include <asm/watch.h>
Paul Gortmaker06372a62011-07-23 16:26:41 -040030#include <asm/elf.h>
Markos Chandras4f12b912014-07-18 10:51:32 +010031#include <asm/pgtable-bits.h>
Chris Dearmana074f0e2009-07-10 01:51:27 -070032#include <asm/spram.h>
David Daney949e51b2010-10-14 11:32:33 -070033#include <asm/uaccess.h>
34
Paul Burtone14f1db2015-07-27 12:58:23 -070035/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
Maciej W. Rozyckif6843622015-04-03 23:27:26 +010038/*
Maciej W. Rozycki7aecd5c2015-04-03 23:27:54 +010039 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
73/*
Maciej W. Rozycki9b266162015-04-03 23:27:48 +010074 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
Maciej W. Rozycki90b712d2015-06-02 17:50:59 +010080 fcsr = c->fpu_csr31;
Maciej W. Rozycki9b266162015-04-03 23:27:48 +010081 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
Maciej W. Rozycki9b266162015-04-03 23:27:48 +010086 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
101/*
Maciej W. Rozyckif6843622015-04-03 23:27:26 +0100102 * Set the FIR feature flags for the FPU emulator.
103 */
104static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
105{
106 u32 value;
107
108 value = 0;
109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_D | MIPS_FPIR_S;
113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
116 c->fpu_id = value;
117}
118
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100119/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
120static unsigned int mips_nofpu_msk31;
121
Maciej W. Rozycki7aecd5c2015-04-03 23:27:54 +0100122/*
123 * Set options for FPU hardware.
124 */
125static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
126{
127 c->fpu_id = cpu_get_fpu_id();
128 mips_nofpu_msk31 = c->fpu_msk31;
129
130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
133 if (c->fpu_id & MIPS_FPIR_3D)
134 c->ases |= MIPS_ASE_MIPS3D;
135 if (c->fpu_id & MIPS_FPIR_FREP)
136 c->options |= MIPS_CPU_FRE;
137 }
138
139 cpu_set_fpu_fcsr_mask(c);
140}
141
142/*
143 * Set options for the FPU emulator.
144 */
145static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
146{
147 c->options &= ~MIPS_CPU_FPU;
148 c->fpu_msk31 = mips_nofpu_msk31;
149
150 cpu_set_nofpu_id(c);
151}
152
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000153static int mips_fpu_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -0700154
155static int __init fpu_disable(char *s)
156{
Maciej W. Rozycki7aecd5c2015-04-03 23:27:54 +0100157 cpu_set_nofpu_opts(&boot_cpu_data);
Kevin Cernekee0103d232010-05-02 14:43:52 -0700158 mips_fpu_disabled = 1;
159
160 return 1;
161}
162
163__setup("nofpu", fpu_disable);
164
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000165int mips_dsp_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -0700166
167static int __init dsp_disable(char *s)
168{
Steven J. Hillee80f7c72012-08-03 10:26:04 -0500169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -0700170 mips_dsp_disabled = 1;
171
172 return 1;
173}
174
175__setup("nodsp", dsp_disable);
176
Markos Chandras3d528b32014-07-14 12:46:13 +0100177static int mips_htw_disabled;
178
179static int __init htw_disable(char *s)
180{
181 mips_htw_disabled = 1;
182 cpu_data[0].options &= ~MIPS_CPU_HTW;
183 write_c0_pwctl(read_c0_pwctl() &
184 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
185
186 return 1;
187}
188
189__setup("nohtw", htw_disable);
190
Markos Chandras97f4ad22014-08-29 09:37:26 +0100191static int mips_ftlb_disabled;
192static int mips_has_ftlb_configured;
193
Markos Chandras912708c2015-07-09 10:40:51 +0100194static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
Markos Chandras97f4ad22014-08-29 09:37:26 +0100195
196static int __init ftlb_disable(char *s)
197{
198 unsigned int config4, mmuextdef;
199
200 /*
201 * If the core hasn't done any FTLB configuration, there is nothing
202 * for us to do here.
203 */
204 if (!mips_has_ftlb_configured)
205 return 1;
206
207 /* Disable it in the boot cpu */
Markos Chandras912708c2015-07-09 10:40:51 +0100208 if (set_ftlb_enable(&cpu_data[0], 0)) {
209 pr_warn("Can't turn FTLB off\n");
210 return 1;
211 }
Markos Chandras97f4ad22014-08-29 09:37:26 +0100212
213 back_to_back_c0_hazard();
214
215 config4 = read_c0_config4();
216
217 /* Check that FTLB has been disabled */
218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
221 /* This should never happen */
222 pr_warn("FTLB could not be disabled!\n");
223 return 1;
224 }
225
226 mips_ftlb_disabled = 1;
227 mips_has_ftlb_configured = 0;
228
229 /*
230 * noftlb is mainly used for debug purposes so print
231 * an informative message instead of using pr_debug()
232 */
233 pr_info("FTLB has been disabled\n");
234
235 /*
236 * Some of these bits are duplicated in the decode_config4.
237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
238 * once FTLB has been disabled so undo what decode_config4 did.
239 */
240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
241 cpu_data[0].tlbsizeftlbsets;
242 cpu_data[0].tlbsizeftlbsets = 0;
243 cpu_data[0].tlbsizeftlbways = 0;
244
245 return 1;
246}
247
248__setup("noftlb", ftlb_disable);
249
250
Marc St-Jean9267a302007-06-14 15:55:31 -0600251static inline void check_errata(void)
252{
253 struct cpuinfo_mips *c = &current_cpu_data;
254
Ralf Baechle69f24d12013-09-17 10:25:47 +0200255 switch (current_cpu_type()) {
Marc St-Jean9267a302007-06-14 15:55:31 -0600256 case CPU_34K:
257 /*
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
Ralf Baechleb633648c52014-05-23 16:29:44 +0200259 * This code only handles VPE0, any SMP/RTOS code
Marc St-Jean9267a302007-06-14 15:55:31 -0600260 * making use of VPE1 will be responsable for that VPE.
261 */
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
264 break;
265 default:
266 break;
267 }
268}
269
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270void __init check_bugs32(void)
271{
Marc St-Jean9267a302007-06-14 15:55:31 -0600272 check_errata();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273}
274
275/*
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
279 */
280static inline int cpu_has_confreg(void)
281{
282#ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
286
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
290 write_c0_conf(cfg);
291 return size1 != size2;
292#else
293 return 0;
294#endif
295}
296
Robert Millanc094c992011-04-18 11:37:55 -0700297static inline void set_elf_platform(int cpu, const char *plat)
298{
299 if (cpu == 0)
300 __elf_platform = plat;
301}
302
Guenter Roeck91dfc422010-02-02 08:52:20 -0800303static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
304{
305#ifdef __NEED_VMBITS_PROBE
David Daney5b7efa82010-02-08 12:27:00 -0800306 write_c0_entryhi(0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800307 back_to_back_c0_hazard();
David Daney5b7efa82010-02-08 12:27:00 -0800308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800309#endif
310}
311
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000312static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
Steven J. Hilla96102b2012-12-07 04:31:36 +0000313{
314 switch (isa) {
315 case MIPS_CPU_ISA_M64R2:
316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
317 case MIPS_CPU_ISA_M64R1:
318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
319 case MIPS_CPU_ISA_V:
320 c->isa_level |= MIPS_CPU_ISA_V;
321 case MIPS_CPU_ISA_IV:
322 c->isa_level |= MIPS_CPU_ISA_IV;
323 case MIPS_CPU_ISA_III:
Ralf Baechle1990e542013-06-26 17:06:34 +0200324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000325 break;
326
Leonid Yegoshin8b8aa632014-11-13 13:51:51 +0000327 /* R6 incompatible with everything else */
328 case MIPS_CPU_ISA_M64R6:
329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
330 case MIPS_CPU_ISA_M32R6:
331 c->isa_level |= MIPS_CPU_ISA_M32R6;
332 /* Break here so we don't add incompatible ISAs */
333 break;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000334 case MIPS_CPU_ISA_M32R2:
335 c->isa_level |= MIPS_CPU_ISA_M32R2;
336 case MIPS_CPU_ISA_M32R1:
337 c->isa_level |= MIPS_CPU_ISA_M32R1;
338 case MIPS_CPU_ISA_II:
339 c->isa_level |= MIPS_CPU_ISA_II;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000340 break;
341 }
342}
343
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000344static char unknown_isa[] = KERN_ERR \
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100345 "Unsupported ISA type, c0.config0: %d.";
346
Markos Chandrascf0a8aa2014-11-10 12:25:34 +0000347static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
348{
349
350 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
351
352 /*
353 * 0 = All TLBWR instructions go to FTLB
354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
355 * FTLB and 1 goes to the VTLB.
356 * 2 = 7:1: As above with 7:1 ratio.
357 * 3 = 3:1: As above with 3:1 ratio.
358 *
359 * Use the linear midpoint as the probability threshold.
360 */
361 if (probability >= 12)
362 return 1;
363 else if (probability >= 6)
364 return 2;
365 else
366 /*
367 * So FTLB is less than 4 times bigger than VTLB.
368 * A 3:1 ratio can still be useful though.
369 */
370 return 3;
371}
372
Markos Chandras912708c2015-07-09 10:40:51 +0100373static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000374{
Markos Chandras20a7f7e2015-07-09 10:40:53 +0100375 unsigned int config;
James Hogand83b0e82014-01-22 16:19:40 +0000376
377 /* It's implementation dependent how the FTLB can be enabled */
378 switch (c->cputype) {
379 case CPU_PROAPTIV:
380 case CPU_P5600:
381 /* proAptiv & related cores use Config6 to enable the FTLB */
Markos Chandras20a7f7e2015-07-09 10:40:53 +0100382 config = read_c0_config6();
Markos Chandrascf0a8aa2014-11-10 12:25:34 +0000383 /* Clear the old probability value */
Markos Chandras20a7f7e2015-07-09 10:40:53 +0100384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000385 if (enable)
386 /* Enable FTLB */
Markos Chandras20a7f7e2015-07-09 10:40:53 +0100387 write_c0_config6(config |
Markos Chandrascf0a8aa2014-11-10 12:25:34 +0000388 (calculate_ftlb_probability(c)
389 << MIPS_CONF6_FTLBP_SHIFT)
390 | MIPS_CONF6_FTLBEN);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000391 else
392 /* Disable FTLB */
Markos Chandras20a7f7e2015-07-09 10:40:53 +0100393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
394 break;
395 case CPU_I6400:
396 /* I6400 & related cores use Config7 to configure FTLB */
397 config = read_c0_config7();
398 /* Clear the old probability value */
399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
400 write_c0_config7(config | (calculate_ftlb_probability(c)
401 << MIPS_CONF7_FTLBP_SHIFT));
James Hogand83b0e82014-01-22 16:19:40 +0000402 break;
Markos Chandras912708c2015-07-09 10:40:51 +0100403 default:
404 return 1;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000405 }
Markos Chandras912708c2015-07-09 10:40:51 +0100406
407 return 0;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000408}
409
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100410static inline unsigned int decode_config0(struct cpuinfo_mips *c)
411{
412 unsigned int config0;
James Hogan2f6f3132015-09-17 17:49:20 +0100413 int isa, mt;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100414
415 config0 = read_c0_config();
416
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000417 /*
418 * Look for Standard TLB or Dual VTLB and FTLB
419 */
James Hogan2f6f3132015-09-17 17:49:20 +0100420 mt = config0 & MIPS_CONF_MT;
421 if (mt == MIPS_CONF_MT_TLB)
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100422 c->options |= MIPS_CPU_TLB;
James Hogan2f6f3132015-09-17 17:49:20 +0100423 else if (mt == MIPS_CONF_MT_FTLB)
424 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000425
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100426 isa = (config0 & MIPS_CONF_AT) >> 13;
427 switch (isa) {
428 case 0:
429 switch ((config0 & MIPS_CONF_AR) >> 10) {
430 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000431 set_isa(c, MIPS_CPU_ISA_M32R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100432 break;
433 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000434 set_isa(c, MIPS_CPU_ISA_M32R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100435 break;
Leonid Yegoshin8b8aa632014-11-13 13:51:51 +0000436 case 2:
437 set_isa(c, MIPS_CPU_ISA_M32R6);
438 break;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100439 default:
440 goto unknown;
441 }
442 break;
443 case 2:
444 switch ((config0 & MIPS_CONF_AR) >> 10) {
445 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000446 set_isa(c, MIPS_CPU_ISA_M64R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100447 break;
448 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000449 set_isa(c, MIPS_CPU_ISA_M64R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100450 break;
Leonid Yegoshin8b8aa632014-11-13 13:51:51 +0000451 case 2:
452 set_isa(c, MIPS_CPU_ISA_M64R6);
453 break;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100454 default:
455 goto unknown;
456 }
457 break;
458 default:
459 goto unknown;
460 }
461
462 return config0 & MIPS_CONF_M;
463
464unknown:
465 panic(unknown_isa, config0);
466}
467
468static inline unsigned int decode_config1(struct cpuinfo_mips *c)
469{
470 unsigned int config1;
471
472 config1 = read_c0_config1();
473
474 if (config1 & MIPS_CONF1_MD)
475 c->ases |= MIPS_ASE_MDMX;
476 if (config1 & MIPS_CONF1_WR)
477 c->options |= MIPS_CPU_WATCH;
478 if (config1 & MIPS_CONF1_CA)
479 c->ases |= MIPS_ASE_MIPS16;
480 if (config1 & MIPS_CONF1_EP)
481 c->options |= MIPS_CPU_EJTAG;
482 if (config1 & MIPS_CONF1_FP) {
483 c->options |= MIPS_CPU_FPU;
484 c->options |= MIPS_CPU_32FPR;
485 }
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000486 if (cpu_has_tlb) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100487 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000488 c->tlbsizevtlb = c->tlbsize;
489 c->tlbsizeftlbsets = 0;
490 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100491
492 return config1 & MIPS_CONF_M;
493}
494
495static inline unsigned int decode_config2(struct cpuinfo_mips *c)
496{
497 unsigned int config2;
498
499 config2 = read_c0_config2();
500
501 if (config2 & MIPS_CONF2_SL)
502 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
503
504 return config2 & MIPS_CONF_M;
505}
506
507static inline unsigned int decode_config3(struct cpuinfo_mips *c)
508{
509 unsigned int config3;
510
511 config3 = read_c0_config3();
512
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500513 if (config3 & MIPS_CONF3_SM) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100514 c->ases |= MIPS_ASE_SMARTMIPS;
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500515 c->options |= MIPS_CPU_RIXI;
516 }
517 if (config3 & MIPS_CONF3_RXI)
518 c->options |= MIPS_CPU_RIXI;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100519 if (config3 & MIPS_CONF3_DSP)
520 c->ases |= MIPS_ASE_DSP;
Steven J. Hillee80f7c72012-08-03 10:26:04 -0500521 if (config3 & MIPS_CONF3_DSP2P)
522 c->ases |= MIPS_ASE_DSP2P;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100523 if (config3 & MIPS_CONF3_VINT)
524 c->options |= MIPS_CPU_VINT;
525 if (config3 & MIPS_CONF3_VEIC)
526 c->options |= MIPS_CPU_VEIC;
527 if (config3 & MIPS_CONF3_MT)
528 c->ases |= MIPS_ASE_MIPSMT;
529 if (config3 & MIPS_CONF3_ULRI)
530 c->options |= MIPS_CPU_ULRI;
Steven J. Hillf8fa4812012-12-07 03:51:35 +0000531 if (config3 & MIPS_CONF3_ISA)
532 c->options |= MIPS_CPU_MICROMIPS;
David Daney1e7decd2013-02-16 23:42:43 +0100533 if (config3 & MIPS_CONF3_VZ)
534 c->ases |= MIPS_ASE_VZ;
Steven J. Hill4a0156f2013-11-14 16:12:24 +0000535 if (config3 & MIPS_CONF3_SC)
536 c->options |= MIPS_CPU_SEGMENTS;
Paul Burtona5e9a692014-01-27 15:23:10 +0000537 if (config3 & MIPS_CONF3_MSA)
538 c->ases |= MIPS_ASE_MSA;
Markos Chandras3d528b32014-07-14 12:46:13 +0100539 /* Only tested on 32-bit cores */
Markos Chandrased4cbc82015-01-26 13:04:33 +0000540 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
541 c->htw_seq = 0;
Markos Chandras3d528b32014-07-14 12:46:13 +0100542 c->options |= MIPS_CPU_HTW;
Markos Chandrased4cbc82015-01-26 13:04:33 +0000543 }
James Hogan9b3274b2015-02-02 11:45:08 +0000544 if (config3 & MIPS_CONF3_CDMM)
545 c->options |= MIPS_CPU_CDMM;
James Hoganaaa7be42015-07-15 16:17:44 +0100546 if (config3 & MIPS_CONF3_SP)
547 c->options |= MIPS_CPU_SP;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100548
549 return config3 & MIPS_CONF_M;
550}
551
552static inline unsigned int decode_config4(struct cpuinfo_mips *c)
553{
554 unsigned int config4;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000555 unsigned int newcf4;
556 unsigned int mmuextdef;
557 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100558
559 config4 = read_c0_config4();
560
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000561 if (cpu_has_tlb) {
562 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
563 c->options |= MIPS_CPU_TLBINV;
Markos Chandrase87569c2015-07-09 10:40:52 +0100564 /*
565 * This is a bit ugly. R6 has dropped that field from
566 * config4 and the only valid configuration is VTLB+FTLB so
567 * set a good value for mmuextdef for that case.
568 */
569 if (cpu_has_mips_r6)
570 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
571 else
572 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
573
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000574 switch (mmuextdef) {
575 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
576 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
577 c->tlbsizevtlb = c->tlbsize;
578 break;
579 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
580 c->tlbsizevtlb +=
581 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
582 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
583 c->tlbsize = c->tlbsizevtlb;
584 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
585 /* fall through */
586 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
Markos Chandras97f4ad22014-08-29 09:37:26 +0100587 if (mips_ftlb_disabled)
588 break;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000589 newcf4 = (config4 & ~ftlb_page) |
590 (page_size_ftlb(mmuextdef) <<
591 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
592 write_c0_config4(newcf4);
593 back_to_back_c0_hazard();
594 config4 = read_c0_config4();
595 if (config4 != newcf4) {
596 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
597 PAGE_SIZE, config4);
598 /* Switch FTLB off */
599 set_ftlb_enable(c, 0);
600 break;
601 }
602 c->tlbsizeftlbsets = 1 <<
603 ((config4 & MIPS_CONF4_FTLBSETS) >>
604 MIPS_CONF4_FTLBSETS_SHIFT);
605 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
606 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
607 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
Markos Chandras97f4ad22014-08-29 09:37:26 +0100608 mips_has_ftlb_configured = 1;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000609 break;
610 }
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000611 }
612
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100613 c->kscratch_mask = (config4 >> 16) & 0xff;
614
615 return config4 & MIPS_CONF_M;
616}
617
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200618static inline unsigned int decode_config5(struct cpuinfo_mips *c)
619{
620 unsigned int config5;
621
622 config5 = read_c0_config5();
Paul Burtond175ed22014-09-11 08:30:19 +0100623 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200624 write_c0_config5(config5);
625
Markos Chandras49016742014-01-09 16:04:51 +0000626 if (config5 & MIPS_CONF5_EVA)
627 c->options |= MIPS_CPU_EVA;
Paul Burton1f6c52f2014-07-14 10:32:14 +0100628 if (config5 & MIPS_CONF5_MRP)
629 c->options |= MIPS_CPU_MAAR;
Markos Chandras5aed9da2014-12-02 09:46:19 +0000630 if (config5 & MIPS_CONF5_LLB)
631 c->options |= MIPS_CPU_RW_LLB;
Steven J. Hillc5b36782015-02-26 18:16:38 -0600632#ifdef CONFIG_XPA
633 if (config5 & MIPS_CONF5_MVH)
634 c->options |= MIPS_CPU_XPA;
635#endif
Markos Chandras49016742014-01-09 16:04:51 +0000636
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200637 return config5 & MIPS_CONF_M;
638}
639
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000640static void decode_configs(struct cpuinfo_mips *c)
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100641{
642 int ok;
643
644 /* MIPS32 or MIPS64 compliant CPU. */
645 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
646 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
647
648 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
649
Markos Chandras97f4ad22014-08-29 09:37:26 +0100650 /* Enable FTLB if present and not disabled */
651 set_ftlb_enable(c, !mips_ftlb_disabled);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000652
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100653 ok = decode_config0(c); /* Read Config registers. */
Ralf Baechle70342282013-01-22 12:59:30 +0100654 BUG_ON(!ok); /* Arch spec violation! */
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100655 if (ok)
656 ok = decode_config1(c);
657 if (ok)
658 ok = decode_config2(c);
659 if (ok)
660 ok = decode_config3(c);
661 if (ok)
662 ok = decode_config4(c);
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200663 if (ok)
664 ok = decode_config5(c);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100665
666 mips_probe_watch_registers(c);
667
Leonid Yegoshin6575b1d2014-07-15 14:09:57 +0100668 if (cpu_has_rixi) {
669 /* Enable the RIXI exceptions */
Steven J. Hilla5770df2015-02-19 10:18:52 -0600670 set_c0_pagegrain(PG_IEC);
Leonid Yegoshin6575b1d2014-07-15 14:09:57 +0100671 back_to_back_c0_hazard();
672 /* Verify the IEC bit is set */
673 if (read_c0_pagegrain() & PG_IEC)
674 c->options |= MIPS_CPU_RIXIEX;
675 }
676
Paul Burton0ee958e2014-01-15 10:31:53 +0000677#ifndef CONFIG_MIPS_CPS
Leonid Yegoshin8b8aa632014-11-13 13:51:51 +0000678 if (cpu_has_mips_r2_r6) {
David Daney45b585c2014-05-28 23:52:10 +0200679 c->core = get_ebase_cpunum();
Paul Burton30ee6152014-03-27 10:57:30 +0000680 if (cpu_has_mipsmt)
681 c->core >>= fls(core_nvpes()) - 1;
682 }
Paul Burton0ee958e2014-01-15 10:31:53 +0000683#endif
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100684}
685
Ralf Baechle02cf2112005-10-01 13:06:32 +0100686#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 | MIPS_CPU_COUNTER)
688
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000689static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100691 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 case PRID_IMP_R2000:
693 c->cputype = CPU_R2000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000694 __cpu_name[cpu] = "R2000";
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100695 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100696 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500697 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 if (__cpu_has_fpu())
699 c->options |= MIPS_CPU_FPU;
700 c->tlbsize = 64;
701 break;
702 case PRID_IMP_R3000:
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100703 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000704 if (cpu_has_confreg()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 c->cputype = CPU_R3081E;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000706 __cpu_name[cpu] = "R3081";
707 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708 c->cputype = CPU_R3000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000709 __cpu_name[cpu] = "R3000A";
710 }
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000711 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 c->cputype = CPU_R3000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000713 __cpu_name[cpu] = "R3000";
714 }
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100715 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100716 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500717 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 if (__cpu_has_fpu())
719 c->options |= MIPS_CPU_FPU;
720 c->tlbsize = 64;
721 break;
722 case PRID_IMP_R4000:
723 if (read_c0_config() & CONF_SC) {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100724 if ((c->processor_id & PRID_REV_MASK) >=
725 PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 c->cputype = CPU_R4400PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000727 __cpu_name[cpu] = "R4400PC";
728 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 c->cputype = CPU_R4000PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000730 __cpu_name[cpu] = "R4000PC";
731 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100733 int cca = read_c0_config() & CONF_CM_CMASK;
734 int mc;
735
736 /*
737 * SC and MC versions can't be reliably told apart,
738 * but only the latter support coherent caching
739 * modes so assume the firmware has set the KSEG0
740 * coherency attribute reasonably (if uncached, we
741 * assume SC).
742 */
743 switch (cca) {
744 case CONF_CM_CACHABLE_CE:
745 case CONF_CM_CACHABLE_COW:
746 case CONF_CM_CACHABLE_CUW:
747 mc = 1;
748 break;
749 default:
750 mc = 0;
751 break;
752 }
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100753 if ((c->processor_id & PRID_REV_MASK) >=
754 PRID_REV_R4400) {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100755 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
756 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000757 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100758 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
759 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000760 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 }
762
Steven J. Hilla96102b2012-12-07 04:31:36 +0000763 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100764 c->fpu_msk31 |= FPU_CSR_CONDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500766 MIPS_CPU_WATCH | MIPS_CPU_VCE |
767 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 c->tlbsize = 48;
769 break;
770 case PRID_IMP_VR41XX:
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900771 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100772 c->fpu_msk31 |= FPU_CSR_CONDX;
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900773 c->options = R4K_OPTS;
774 c->tlbsize = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 switch (c->processor_id & 0xf0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 case PRID_REV_VR4111:
777 c->cputype = CPU_VR4111;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000778 __cpu_name[cpu] = "NEC VR4111";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 case PRID_REV_VR4121:
781 c->cputype = CPU_VR4121;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000782 __cpu_name[cpu] = "NEC VR4121";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 break;
784 case PRID_REV_VR4122:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000785 if ((c->processor_id & 0xf) < 0x3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 c->cputype = CPU_VR4122;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000787 __cpu_name[cpu] = "NEC VR4122";
788 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 c->cputype = CPU_VR4181A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000790 __cpu_name[cpu] = "NEC VR4181A";
791 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 break;
793 case PRID_REV_VR4130:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000794 if ((c->processor_id & 0xf) < 0x4) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 c->cputype = CPU_VR4131;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000796 __cpu_name[cpu] = "NEC VR4131";
797 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 c->cputype = CPU_VR4133;
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900799 c->options |= MIPS_CPU_LLSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000800 __cpu_name[cpu] = "NEC VR4133";
801 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 break;
803 default:
804 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
805 c->cputype = CPU_VR41XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000806 __cpu_name[cpu] = "NEC Vr41xx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 break;
808 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 break;
810 case PRID_IMP_R4300:
811 c->cputype = CPU_R4300;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000812 __cpu_name[cpu] = "R4300";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000813 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100814 c->fpu_msk31 |= FPU_CSR_CONDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500816 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 c->tlbsize = 32;
818 break;
819 case PRID_IMP_R4600:
820 c->cputype = CPU_R4600;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000821 __cpu_name[cpu] = "R4600";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000822 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100823 c->fpu_msk31 |= FPU_CSR_CONDX;
Thiemo Seufer075e7502005-07-27 21:48:12 +0000824 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
825 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 c->tlbsize = 48;
827 break;
828 #if 0
Steven J. Hill03751e72012-05-10 23:21:18 -0500829 case PRID_IMP_R4650:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 /*
831 * This processor doesn't have an MMU, so it's not
832 * "real easy" to run Linux on it. It is left purely
833 * for documentation. Commented out because it shares
834 * it's c0_prid id number with the TX3900.
835 */
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000836 c->cputype = CPU_R4650;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000837 __cpu_name[cpu] = "R4650";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000838 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100839 c->fpu_msk31 |= FPU_CSR_CONDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
Steven J. Hill03751e72012-05-10 23:21:18 -0500841 c->tlbsize = 48;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 break;
843 #endif
844 case PRID_IMP_TX39:
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100845 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100846 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
848 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
849 c->cputype = CPU_TX3927;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000850 __cpu_name[cpu] = "TX3927";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 c->tlbsize = 64;
852 } else {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100853 switch (c->processor_id & PRID_REV_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 case PRID_REV_TX3912:
855 c->cputype = CPU_TX3912;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000856 __cpu_name[cpu] = "TX3912";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 c->tlbsize = 32;
858 break;
859 case PRID_REV_TX3922:
860 c->cputype = CPU_TX3922;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000861 __cpu_name[cpu] = "TX3922";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 c->tlbsize = 64;
863 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 }
865 }
866 break;
867 case PRID_IMP_R4700:
868 c->cputype = CPU_R4700;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000869 __cpu_name[cpu] = "R4700";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000870 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100871 c->fpu_msk31 |= FPU_CSR_CONDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500873 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 c->tlbsize = 48;
875 break;
876 case PRID_IMP_TX49:
877 c->cputype = CPU_TX49XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000878 __cpu_name[cpu] = "R49XX";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000879 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100880 c->fpu_msk31 |= FPU_CSR_CONDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 c->options = R4K_OPTS | MIPS_CPU_LLSC;
882 if (!(c->processor_id & 0x08))
883 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
884 c->tlbsize = 48;
885 break;
886 case PRID_IMP_R5000:
887 c->cputype = CPU_R5000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000888 __cpu_name[cpu] = "R5000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000889 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500891 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 c->tlbsize = 48;
893 break;
894 case PRID_IMP_R5432:
895 c->cputype = CPU_R5432;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000896 __cpu_name[cpu] = "R5432";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000897 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500899 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 c->tlbsize = 48;
901 break;
902 case PRID_IMP_R5500:
903 c->cputype = CPU_R5500;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000904 __cpu_name[cpu] = "R5500";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000905 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500907 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908 c->tlbsize = 48;
909 break;
910 case PRID_IMP_NEVADA:
911 c->cputype = CPU_NEVADA;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000912 __cpu_name[cpu] = "Nevada";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000913 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500915 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 c->tlbsize = 48;
917 break;
918 case PRID_IMP_R6000:
919 c->cputype = CPU_R6000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000920 __cpu_name[cpu] = "R6000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000921 set_isa(c, MIPS_CPU_ISA_II);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100922 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500924 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 c->tlbsize = 32;
926 break;
927 case PRID_IMP_R6000A:
928 c->cputype = CPU_R6000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000929 __cpu_name[cpu] = "R6000A";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000930 set_isa(c, MIPS_CPU_ISA_II);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +0100931 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500933 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 c->tlbsize = 32;
935 break;
936 case PRID_IMP_RM7000:
937 c->cputype = CPU_RM7000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000938 __cpu_name[cpu] = "RM7000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000939 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500941 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 /*
Ralf Baechle70342282013-01-22 12:59:30 +0100943 * Undocumented RM7000: Bit 29 in the info register of
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 * the RM7000 v2.0 indicates if the TLB has 48 or 64
945 * entries.
946 *
Ralf Baechle70342282013-01-22 12:59:30 +0100947 * 29 1 => 64 entry JTLB
948 * 0 => 48 entry JTLB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949 */
950 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
951 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952 case PRID_IMP_R8000:
953 c->cputype = CPU_R8000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000954 __cpu_name[cpu] = "RM8000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000955 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500957 MIPS_CPU_FPU | MIPS_CPU_32FPR |
958 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
960 break;
961 case PRID_IMP_R10000:
962 c->cputype = CPU_R10000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000963 __cpu_name[cpu] = "R10000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000964 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000965 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500966 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500968 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969 c->tlbsize = 64;
970 break;
971 case PRID_IMP_R12000:
972 c->cputype = CPU_R12000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000973 __cpu_name[cpu] = "R12000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000974 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000975 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500976 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Joshua Kinard8d5ded12015-06-02 18:21:33 -0400978 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979 c->tlbsize = 64;
980 break;
Kumba44d921b2006-05-16 22:23:59 -0400981 case PRID_IMP_R14000:
Joshua Kinard30577392015-01-21 07:59:45 -0500982 if (((c->processor_id >> 4) & 0x0f) > 2) {
983 c->cputype = CPU_R16000;
984 __cpu_name[cpu] = "R16000";
985 } else {
986 c->cputype = CPU_R14000;
987 __cpu_name[cpu] = "R14000";
988 }
Steven J. Hilla96102b2012-12-07 04:31:36 +0000989 set_isa(c, MIPS_CPU_ISA_IV);
Kumba44d921b2006-05-16 22:23:59 -0400990 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500991 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Kumba44d921b2006-05-16 22:23:59 -0400992 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Joshua Kinard8d5ded12015-06-02 18:21:33 -0400993 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
Kumba44d921b2006-05-16 22:23:59 -0400994 c->tlbsize = 64;
995 break;
Huacai Chen26859192014-02-16 16:01:18 +0800996 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
Robert Millan5aac1e82011-04-16 11:29:29 -0700997 switch (c->processor_id & PRID_REV_MASK) {
998 case PRID_REV_LOONGSON2E:
Huacai Chenc579d312014-03-21 18:44:00 +0800999 c->cputype = CPU_LOONGSON2;
1000 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -07001001 set_elf_platform(cpu, "loongson2e");
Huacai Chen7352c8b2014-11-04 14:13:23 +08001002 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +01001003 c->fpu_msk31 |= FPU_CSR_CONDX;
Robert Millan5aac1e82011-04-16 11:29:29 -07001004 break;
1005 case PRID_REV_LOONGSON2F:
Huacai Chenc579d312014-03-21 18:44:00 +08001006 c->cputype = CPU_LOONGSON2;
1007 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -07001008 set_elf_platform(cpu, "loongson2f");
Huacai Chen7352c8b2014-11-04 14:13:23 +08001009 set_isa(c, MIPS_CPU_ISA_III);
Maciej W. Rozycki9b266162015-04-03 23:27:48 +01001010 c->fpu_msk31 |= FPU_CSR_CONDX;
Robert Millan5aac1e82011-04-16 11:29:29 -07001011 break;
Huacai Chenc579d312014-03-21 18:44:00 +08001012 case PRID_REV_LOONGSON3A:
1013 c->cputype = CPU_LOONGSON3;
1014 __cpu_name[cpu] = "ICT Loongson-3";
1015 set_elf_platform(cpu, "loongson3a");
Huacai Chen7352c8b2014-11-04 14:13:23 +08001016 set_isa(c, MIPS_CPU_ISA_M64R1);
Huacai Chenc579d312014-03-21 18:44:00 +08001017 break;
Huacai Chene7841be2014-06-26 11:41:30 +08001018 case PRID_REV_LOONGSON3B_R1:
1019 case PRID_REV_LOONGSON3B_R2:
1020 c->cputype = CPU_LOONGSON3;
1021 __cpu_name[cpu] = "ICT Loongson-3";
1022 set_elf_platform(cpu, "loongson3b");
Huacai Chen7352c8b2014-11-04 14:13:23 +08001023 set_isa(c, MIPS_CPU_ISA_M64R1);
Huacai Chene7841be2014-06-26 11:41:30 +08001024 break;
Robert Millan5aac1e82011-04-16 11:29:29 -07001025 }
1026
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001027 c->options = R4K_OPTS |
1028 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1029 MIPS_CPU_32FPR;
1030 c->tlbsize = 64;
Huacai Chencc94ea32014-11-04 14:13:22 +08001031 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001032 break;
Huacai Chen26859192014-02-16 16:01:18 +08001033 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001034 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001036 c->cputype = CPU_LOONGSON1;
Ralf Baechleb4672d32005-12-08 14:04:24 +00001037
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001038 switch (c->processor_id & PRID_REV_MASK) {
1039 case PRID_REV_LOONGSON1B:
1040 __cpu_name[cpu] = "Loongson 1B";
Ralf Baechleb4672d32005-12-08 14:04:24 +00001041 break;
Ralf Baechleb4672d32005-12-08 14:04:24 +00001042 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001043
Ralf Baechle41943182005-05-05 16:45:59 +00001044 break;
Ralf Baechle41943182005-05-05 16:45:59 +00001045 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046}
1047
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001048static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049{
Markos Chandras4f12b912014-07-18 10:51:32 +01001050 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001051 switch (c->processor_id & PRID_IMP_MASK) {
Leonid Yegoshinb2498af2014-11-24 12:59:44 +00001052 case PRID_IMP_QEMU_GENERIC:
1053 c->writecombine = _CACHE_UNCACHED;
1054 c->cputype = CPU_QEMU_GENERIC;
1055 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1056 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 case PRID_IMP_4KC:
1058 c->cputype = CPU_4KC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001059 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001060 __cpu_name[cpu] = "MIPS 4Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 break;
1062 case PRID_IMP_4KEC:
Ralf Baechle2b07bd02005-04-08 20:36:05 +00001063 case PRID_IMP_4KECR2:
1064 c->cputype = CPU_4KEC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001065 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001066 __cpu_name[cpu] = "MIPS 4KEc";
Ralf Baechle2b07bd02005-04-08 20:36:05 +00001067 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 case PRID_IMP_4KSC:
Ralf Baechle8afcb5d2005-10-04 15:01:26 +01001069 case PRID_IMP_4KSD:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 c->cputype = CPU_4KSC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001071 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001072 __cpu_name[cpu] = "MIPS 4KSc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073 break;
1074 case PRID_IMP_5KC:
1075 c->cputype = CPU_5KC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001076 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001077 __cpu_name[cpu] = "MIPS 5Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 break;
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001079 case PRID_IMP_5KE:
1080 c->cputype = CPU_5KE;
Markos Chandras4f12b912014-07-18 10:51:32 +01001081 c->writecombine = _CACHE_UNCACHED;
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001082 __cpu_name[cpu] = "MIPS 5KE";
1083 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 case PRID_IMP_20KC:
1085 c->cputype = CPU_20KC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001086 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001087 __cpu_name[cpu] = "MIPS 20Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 break;
1089 case PRID_IMP_24K:
1090 c->cputype = CPU_24K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001091 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001092 __cpu_name[cpu] = "MIPS 24Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 break;
John Crispin42f3cae2013-01-11 22:44:10 +01001094 case PRID_IMP_24KE:
1095 c->cputype = CPU_24K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001096 c->writecombine = _CACHE_UNCACHED;
John Crispin42f3cae2013-01-11 22:44:10 +01001097 __cpu_name[cpu] = "MIPS 24KEc";
1098 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 case PRID_IMP_25KF:
1100 c->cputype = CPU_25KF;
Markos Chandras4f12b912014-07-18 10:51:32 +01001101 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001102 __cpu_name[cpu] = "MIPS 25Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 break;
Ralf Baechlebbc7f222005-07-12 16:12:05 +00001104 case PRID_IMP_34K:
1105 c->cputype = CPU_34K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001106 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001107 __cpu_name[cpu] = "MIPS 34Kc";
Ralf Baechlebbc7f222005-07-12 16:12:05 +00001108 break;
Chris Dearmanc6209532006-05-02 14:08:46 +01001109 case PRID_IMP_74K:
1110 c->cputype = CPU_74K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001111 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001112 __cpu_name[cpu] = "MIPS 74Kc";
Chris Dearmanc6209532006-05-02 14:08:46 +01001113 break;
Steven J. Hill113c62d2012-07-06 23:56:00 +02001114 case PRID_IMP_M14KC:
1115 c->cputype = CPU_M14KC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001116 c->writecombine = _CACHE_UNCACHED;
Steven J. Hill113c62d2012-07-06 23:56:00 +02001117 __cpu_name[cpu] = "MIPS M14Kc";
1118 break;
Steven J. Hillf8fa4812012-12-07 03:51:35 +00001119 case PRID_IMP_M14KEC:
1120 c->cputype = CPU_M14KEC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001121 c->writecombine = _CACHE_UNCACHED;
Steven J. Hillf8fa4812012-12-07 03:51:35 +00001122 __cpu_name[cpu] = "MIPS M14KEc";
1123 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +01001124 case PRID_IMP_1004K:
1125 c->cputype = CPU_1004K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001126 c->writecombine = _CACHE_UNCACHED;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001127 __cpu_name[cpu] = "MIPS 1004Kc";
Ralf Baechle39b8d522008-04-28 17:14:26 +01001128 break;
Steven J. Hill006a8512012-06-26 04:11:03 +00001129 case PRID_IMP_1074K:
Steven J. Hill442e14a2014-01-17 15:03:50 -06001130 c->cputype = CPU_1074K;
Markos Chandras4f12b912014-07-18 10:51:32 +01001131 c->writecombine = _CACHE_UNCACHED;
Steven J. Hill006a8512012-06-26 04:11:03 +00001132 __cpu_name[cpu] = "MIPS 1074Kc";
1133 break;
Leonid Yegoshinb5f065e2013-11-20 10:46:02 +00001134 case PRID_IMP_INTERAPTIV_UP:
1135 c->cputype = CPU_INTERAPTIV;
1136 __cpu_name[cpu] = "MIPS interAptiv";
1137 break;
1138 case PRID_IMP_INTERAPTIV_MP:
1139 c->cputype = CPU_INTERAPTIV;
1140 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1141 break;
Leonid Yegoshinb0d4d302013-11-14 16:12:28 +00001142 case PRID_IMP_PROAPTIV_UP:
1143 c->cputype = CPU_PROAPTIV;
1144 __cpu_name[cpu] = "MIPS proAptiv";
1145 break;
1146 case PRID_IMP_PROAPTIV_MP:
1147 c->cputype = CPU_PROAPTIV;
1148 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1149 break;
James Hogan829dcc02014-01-22 16:19:39 +00001150 case PRID_IMP_P5600:
1151 c->cputype = CPU_P5600;
1152 __cpu_name[cpu] = "MIPS P5600";
1153 break;
Markos Chandrase57f9a22015-07-09 10:40:37 +01001154 case PRID_IMP_I6400:
1155 c->cputype = CPU_I6400;
1156 __cpu_name[cpu] = "MIPS I6400";
1157 break;
Leonid Yegoshin9943ed92014-03-04 13:34:44 +00001158 case PRID_IMP_M5150:
1159 c->cputype = CPU_M5150;
1160 __cpu_name[cpu] = "MIPS M5150";
1161 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162 }
Chris Dearman0b6d4972007-09-13 12:32:02 +01001163
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001164 decode_configs(c);
1165
Chris Dearman0b6d4972007-09-13 12:32:02 +01001166 spram_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167}
1168
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001169static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170{
Ralf Baechle41943182005-05-05 16:45:59 +00001171 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001172 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 case PRID_IMP_AU1_REV1:
1174 case PRID_IMP_AU1_REV2:
Manuel Lauss270717a2009-03-25 17:49:28 +01001175 c->cputype = CPU_ALCHEMY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 switch ((c->processor_id >> 24) & 0xff) {
1177 case 0:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001178 __cpu_name[cpu] = "Au1000";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 break;
1180 case 1:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001181 __cpu_name[cpu] = "Au1500";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182 break;
1183 case 2:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001184 __cpu_name[cpu] = "Au1100";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185 break;
1186 case 3:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001187 __cpu_name[cpu] = "Au1550";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 break;
Pete Popove3ad1c22005-03-01 06:33:16 +00001189 case 4:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001190 __cpu_name[cpu] = "Au1200";
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001191 if ((c->processor_id & PRID_REV_MASK) == 2)
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001192 __cpu_name[cpu] = "Au1250";
Manuel Lauss237cfee2007-12-06 09:07:55 +01001193 break;
1194 case 5:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001195 __cpu_name[cpu] = "Au1210";
Pete Popove3ad1c22005-03-01 06:33:16 +00001196 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 default:
Manuel Lauss270717a2009-03-25 17:49:28 +01001198 __cpu_name[cpu] = "Au1xxx";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199 break;
1200 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 break;
1202 }
1203}
1204
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001205static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206{
Ralf Baechle41943182005-05-05 16:45:59 +00001207 decode_configs(c);
Ralf Baechle02cf2112005-10-01 13:06:32 +01001208
Markos Chandras4f12b912014-07-18 10:51:32 +01001209 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001210 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 case PRID_IMP_SB1:
1212 c->cputype = CPU_SB1;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001213 __cpu_name[cpu] = "SiByte SB1";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 /* FPU in pass1 is known to have issues. */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001215 if ((c->processor_id & PRID_REV_MASK) < 0x02)
Ralf Baechle010b8532006-01-29 18:42:08 +00001216 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 break;
Andrew Isaacson93ce2f522005-10-19 23:56:20 -07001218 case PRID_IMP_SB1A:
1219 c->cputype = CPU_SB1A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001220 __cpu_name[cpu] = "SiByte SB1A";
Andrew Isaacson93ce2f522005-10-19 23:56:20 -07001221 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 }
1223}
1224
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001225static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226{
Ralf Baechle41943182005-05-05 16:45:59 +00001227 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001228 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229 case PRID_IMP_SR71000:
1230 c->cputype = CPU_SR71000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001231 __cpu_name[cpu] = "Sandcraft SR71000";
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232 c->scache.ways = 8;
1233 c->tlbsize = 64;
1234 break;
1235 }
1236}
1237
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001238static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
Pete Popovbdf21b12005-07-14 17:47:57 +00001239{
1240 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001241 switch (c->processor_id & PRID_IMP_MASK) {
Pete Popovbdf21b12005-07-14 17:47:57 +00001242 case PRID_IMP_PR4450:
1243 c->cputype = CPU_PR4450;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001244 __cpu_name[cpu] = "Philips PR4450";
Steven J. Hilla96102b2012-12-07 04:31:36 +00001245 set_isa(c, MIPS_CPU_ISA_M32R1);
Pete Popovbdf21b12005-07-14 17:47:57 +00001246 break;
Pete Popovbdf21b12005-07-14 17:47:57 +00001247 }
1248}
1249
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001250static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001251{
1252 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001253 switch (c->processor_id & PRID_IMP_MASK) {
Kevin Cernekee190fca32010-11-23 10:26:45 -08001254 case PRID_IMP_BMIPS32_REV4:
1255 case PRID_IMP_BMIPS32_REV8:
Kevin Cernekee602977b2010-10-16 14:22:30 -07001256 c->cputype = CPU_BMIPS32;
1257 __cpu_name[cpu] = "Broadcom BMIPS32";
Kevin Cernekee06785df2011-04-16 11:29:28 -07001258 set_elf_platform(cpu, "bmips32");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001259 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -07001260 case PRID_IMP_BMIPS3300:
1261 case PRID_IMP_BMIPS3300_ALT:
1262 case PRID_IMP_BMIPS3300_BUG:
1263 c->cputype = CPU_BMIPS3300;
1264 __cpu_name[cpu] = "Broadcom BMIPS3300";
Kevin Cernekee06785df2011-04-16 11:29:28 -07001265 set_elf_platform(cpu, "bmips3300");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001266 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -07001267 case PRID_IMP_BMIPS43XX: {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001268 int rev = c->processor_id & PRID_REV_MASK;
Kevin Cernekee602977b2010-10-16 14:22:30 -07001269
1270 if (rev >= PRID_REV_BMIPS4380_LO &&
1271 rev <= PRID_REV_BMIPS4380_HI) {
1272 c->cputype = CPU_BMIPS4380;
1273 __cpu_name[cpu] = "Broadcom BMIPS4380";
Kevin Cernekee06785df2011-04-16 11:29:28 -07001274 set_elf_platform(cpu, "bmips4380");
Kevin Cernekee602977b2010-10-16 14:22:30 -07001275 } else {
1276 c->cputype = CPU_BMIPS4350;
1277 __cpu_name[cpu] = "Broadcom BMIPS4350";
Kevin Cernekee06785df2011-04-16 11:29:28 -07001278 set_elf_platform(cpu, "bmips4350");
Maxime Bizon0de663e2009-08-18 13:23:37 +01001279 }
1280 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001281 }
Kevin Cernekee602977b2010-10-16 14:22:30 -07001282 case PRID_IMP_BMIPS5000:
Kevin Cernekee68e6a782014-10-20 21:28:01 -07001283 case PRID_IMP_BMIPS5200:
Kevin Cernekee602977b2010-10-16 14:22:30 -07001284 c->cputype = CPU_BMIPS5000;
1285 __cpu_name[cpu] = "Broadcom BMIPS5000";
Kevin Cernekee06785df2011-04-16 11:29:28 -07001286 set_elf_platform(cpu, "bmips5000");
Kevin Cernekee602977b2010-10-16 14:22:30 -07001287 c->options |= MIPS_CPU_ULRI;
1288 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -07001289 }
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001290}
1291
David Daney0dd47812008-12-11 15:33:26 -08001292static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1293{
1294 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001295 switch (c->processor_id & PRID_IMP_MASK) {
David Daney0dd47812008-12-11 15:33:26 -08001296 case PRID_IMP_CAVIUM_CN38XX:
1297 case PRID_IMP_CAVIUM_CN31XX:
1298 case PRID_IMP_CAVIUM_CN30XX:
David Daney6f329462010-02-10 15:12:48 -08001299 c->cputype = CPU_CAVIUM_OCTEON;
1300 __cpu_name[cpu] = "Cavium Octeon";
1301 goto platform;
David Daney0dd47812008-12-11 15:33:26 -08001302 case PRID_IMP_CAVIUM_CN58XX:
1303 case PRID_IMP_CAVIUM_CN56XX:
1304 case PRID_IMP_CAVIUM_CN50XX:
1305 case PRID_IMP_CAVIUM_CN52XX:
David Daney6f329462010-02-10 15:12:48 -08001306 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1307 __cpu_name[cpu] = "Cavium Octeon+";
1308platform:
Robert Millanc094c992011-04-18 11:37:55 -07001309 set_elf_platform(cpu, "octeon");
David Daney0dd47812008-12-11 15:33:26 -08001310 break;
David Daneya1431b62011-09-24 02:29:54 +02001311 case PRID_IMP_CAVIUM_CN61XX:
David Daney0e56b382010-10-07 16:03:45 -07001312 case PRID_IMP_CAVIUM_CN63XX:
David Daneya1431b62011-09-24 02:29:54 +02001313 case PRID_IMP_CAVIUM_CN66XX:
1314 case PRID_IMP_CAVIUM_CN68XX:
David Daneyaf04bb82013-07-29 15:07:01 -07001315 case PRID_IMP_CAVIUM_CNF71XX:
David Daney0e56b382010-10-07 16:03:45 -07001316 c->cputype = CPU_CAVIUM_OCTEON2;
1317 __cpu_name[cpu] = "Cavium Octeon II";
Robert Millanc094c992011-04-18 11:37:55 -07001318 set_elf_platform(cpu, "octeon2");
David Daney0e56b382010-10-07 16:03:45 -07001319 break;
David Daneyaf04bb82013-07-29 15:07:01 -07001320 case PRID_IMP_CAVIUM_CN70XX:
1321 case PRID_IMP_CAVIUM_CN78XX:
1322 c->cputype = CPU_CAVIUM_OCTEON3;
1323 __cpu_name[cpu] = "Cavium Octeon III";
1324 set_elf_platform(cpu, "octeon3");
1325 break;
David Daney0dd47812008-12-11 15:33:26 -08001326 default:
1327 printk(KERN_INFO "Unknown Octeon chip!\n");
1328 c->cputype = CPU_UNKNOWN;
1329 break;
1330 }
1331}
1332
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001333static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1334{
1335 decode_configs(c);
1336 /* JZRISC does not implement the CP0 counter. */
1337 c->options &= ~MIPS_CPU_COUNTER;
Maciej W. Rozycki06947aa2014-04-06 21:31:29 +01001338 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001339 switch (c->processor_id & PRID_IMP_MASK) {
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001340 case PRID_IMP_JZRISC:
1341 c->cputype = CPU_JZRISC;
Markos Chandras4f12b912014-07-18 10:51:32 +01001342 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001343 __cpu_name[cpu] = "Ingenic JZRISC";
1344 break;
1345 default:
1346 panic("Unknown Ingenic Processor ID!");
1347 break;
1348 }
1349}
1350
Jayachandran Ca7117c62011-05-11 12:04:58 +05301351static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1352{
1353 decode_configs(c);
1354
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001355 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
Manuel Lauss809f36c2011-11-01 20:03:30 +01001356 c->cputype = CPU_ALCHEMY;
1357 __cpu_name[cpu] = "Au1300";
1358 /* following stuff is not for Alchemy */
1359 return;
1360 }
1361
Ralf Baechle70342282013-01-22 12:59:30 +01001362 c->options = (MIPS_CPU_TLB |
1363 MIPS_CPU_4KEX |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301364 MIPS_CPU_COUNTER |
Ralf Baechle70342282013-01-22 12:59:30 +01001365 MIPS_CPU_DIVEC |
1366 MIPS_CPU_WATCH |
1367 MIPS_CPU_EJTAG |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301368 MIPS_CPU_LLSC);
1369
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001370 switch (c->processor_id & PRID_IMP_MASK) {
Jayachandran C4ca86a22013-08-11 14:43:54 +05301371 case PRID_IMP_NETLOGIC_XLP2XX:
Jayachandran C8907c552013-12-21 16:52:20 +05301372 case PRID_IMP_NETLOGIC_XLP9XX:
Yonghong Song1c983982014-04-29 20:07:53 +05301373 case PRID_IMP_NETLOGIC_XLP5XX:
Jayachandran C4ca86a22013-08-11 14:43:54 +05301374 c->cputype = CPU_XLP;
1375 __cpu_name[cpu] = "Broadcom XLPII";
1376 break;
1377
Jayachandran C2aa54b22011-11-16 00:21:29 +00001378 case PRID_IMP_NETLOGIC_XLP8XX:
1379 case PRID_IMP_NETLOGIC_XLP3XX:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001380 c->cputype = CPU_XLP;
1381 __cpu_name[cpu] = "Netlogic XLP";
1382 break;
1383
Jayachandran Ca7117c62011-05-11 12:04:58 +05301384 case PRID_IMP_NETLOGIC_XLR732:
1385 case PRID_IMP_NETLOGIC_XLR716:
1386 case PRID_IMP_NETLOGIC_XLR532:
1387 case PRID_IMP_NETLOGIC_XLR308:
1388 case PRID_IMP_NETLOGIC_XLR532C:
1389 case PRID_IMP_NETLOGIC_XLR516C:
1390 case PRID_IMP_NETLOGIC_XLR508C:
1391 case PRID_IMP_NETLOGIC_XLR308C:
1392 c->cputype = CPU_XLR;
1393 __cpu_name[cpu] = "Netlogic XLR";
1394 break;
1395
1396 case PRID_IMP_NETLOGIC_XLS608:
1397 case PRID_IMP_NETLOGIC_XLS408:
1398 case PRID_IMP_NETLOGIC_XLS404:
1399 case PRID_IMP_NETLOGIC_XLS208:
1400 case PRID_IMP_NETLOGIC_XLS204:
1401 case PRID_IMP_NETLOGIC_XLS108:
1402 case PRID_IMP_NETLOGIC_XLS104:
1403 case PRID_IMP_NETLOGIC_XLS616B:
1404 case PRID_IMP_NETLOGIC_XLS608B:
1405 case PRID_IMP_NETLOGIC_XLS416B:
1406 case PRID_IMP_NETLOGIC_XLS412B:
1407 case PRID_IMP_NETLOGIC_XLS408B:
1408 case PRID_IMP_NETLOGIC_XLS404B:
1409 c->cputype = CPU_XLR;
1410 __cpu_name[cpu] = "Netlogic XLS";
1411 break;
1412
1413 default:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001414 pr_info("Unknown Netlogic chip id [%02x]!\n",
Jayachandran Ca7117c62011-05-11 12:04:58 +05301415 c->processor_id);
1416 c->cputype = CPU_XLR;
1417 break;
1418 }
1419
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001420 if (c->cputype == CPU_XLP) {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001421 set_isa(c, MIPS_CPU_ISA_M64R2);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001422 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1423 /* This will be updated again after all threads are woken up */
1424 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1425 } else {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001426 set_isa(c, MIPS_CPU_ISA_M64R1);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001427 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1428 }
Jayachandran C7777b932013-06-11 14:41:35 +00001429 c->kscratch_mask = 0xf;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301430}
1431
David Daney949e51b2010-10-14 11:32:33 -07001432#ifdef CONFIG_64BIT
1433/* For use by uaccess.h */
1434u64 __ua_limit;
1435EXPORT_SYMBOL(__ua_limit);
1436#endif
1437
Ralf Baechle9966db252007-10-11 23:46:17 +01001438const char *__cpu_name[NR_CPUS];
David Daney874fd3b2010-01-28 16:52:12 -08001439const char *__elf_platform;
Ralf Baechle9966db252007-10-11 23:46:17 +01001440
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001441void cpu_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001442{
1443 struct cpuinfo_mips *c = &current_cpu_data;
Ralf Baechle9966db252007-10-11 23:46:17 +01001444 unsigned int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445
Ralf Baechle70342282013-01-22 12:59:30 +01001446 c->processor_id = PRID_IMP_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 c->fpu_id = FPIR_IMP_NONE;
1448 c->cputype = CPU_UNKNOWN;
Markos Chandras4f12b912014-07-18 10:51:32 +01001449 c->writecombine = _CACHE_UNCACHED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450
Maciej W. Rozycki9b266162015-04-03 23:27:48 +01001451 c->fpu_csr31 = FPU_CSR_RN;
1452 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1453
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 c->processor_id = read_c0_prid();
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001455 switch (c->processor_id & PRID_COMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001456 case PRID_COMP_LEGACY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001457 cpu_probe_legacy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458 break;
1459 case PRID_COMP_MIPS:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001460 cpu_probe_mips(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461 break;
1462 case PRID_COMP_ALCHEMY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001463 cpu_probe_alchemy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464 break;
1465 case PRID_COMP_SIBYTE:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001466 cpu_probe_sibyte(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001468 case PRID_COMP_BROADCOM:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001469 cpu_probe_broadcom(c, cpu);
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001470 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471 case PRID_COMP_SANDCRAFT:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001472 cpu_probe_sandcraft(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473 break;
Daniel Lairda92b0582008-03-06 09:07:18 +00001474 case PRID_COMP_NXP:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001475 cpu_probe_nxp(c, cpu);
Ralf Baechlea3dddd52006-03-11 08:18:41 +00001476 break;
David Daney0dd47812008-12-11 15:33:26 -08001477 case PRID_COMP_CAVIUM:
1478 cpu_probe_cavium(c, cpu);
1479 break;
Paul Burton252617a2015-05-24 16:11:14 +01001480 case PRID_COMP_INGENIC_D0:
1481 case PRID_COMP_INGENIC_D1:
1482 case PRID_COMP_INGENIC_E1:
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001483 cpu_probe_ingenic(c, cpu);
1484 break;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301485 case PRID_COMP_NETLOGIC:
1486 cpu_probe_netlogic(c, cpu);
1487 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 }
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001489
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001490 BUG_ON(!__cpu_name[cpu]);
1491 BUG_ON(c->cputype == CPU_UNKNOWN);
1492
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001493 /*
1494 * Platform code can force the cpu type to optimize code
1495 * generation. In that case be sure the cpu type is correctly
1496 * manually setup otherwise it could trigger some nasty bugs.
1497 */
1498 BUG_ON(current_cpu_type() != c->cputype);
1499
Kevin Cernekee0103d232010-05-02 14:43:52 -07001500 if (mips_fpu_disabled)
1501 c->options &= ~MIPS_CPU_FPU;
1502
1503 if (mips_dsp_disabled)
Steven J. Hillee80f7c72012-08-03 10:26:04 -05001504 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -07001505
Markos Chandras3d528b32014-07-14 12:46:13 +01001506 if (mips_htw_disabled) {
1507 c->options &= ~MIPS_CPU_HTW;
1508 write_c0_pwctl(read_c0_pwctl() &
1509 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1510 }
1511
Maciej W. Rozycki7aecd5c2015-04-03 23:27:54 +01001512 if (c->options & MIPS_CPU_FPU)
1513 cpu_set_fpu_opts(c);
1514 else
1515 cpu_set_nofpu_opts(c);
Ralf Baechle9966db252007-10-11 23:46:17 +01001516
Joshua Kinard8d5ded12015-06-02 18:21:33 -04001517 if (cpu_has_bp_ghist)
1518 write_c0_r10k_diag(read_c0_r10k_diag() |
1519 R10K_DIAG_E_GHIST);
1520
Leonid Yegoshin8b8aa632014-11-13 13:51:51 +00001521 if (cpu_has_mips_r2_r6) {
Ralf Baechlef6771db2007-11-08 18:02:29 +00001522 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
Al Cooperda4b62c2012-07-13 16:44:51 -04001523 /* R2 has Performance Counter Interrupt indicator */
1524 c->options |= MIPS_CPU_PCI;
1525 }
Ralf Baechlef6771db2007-11-08 18:02:29 +00001526 else
1527 c->srsets = 1;
Guenter Roeck91dfc422010-02-02 08:52:20 -08001528
Paul Burton4c063032015-07-27 12:58:24 -07001529 if (cpu_has_mips_r6)
1530 elf_hwcap |= HWCAP_MIPS_R6;
1531
Paul Burtona8ad1362014-01-28 14:28:43 +00001532 if (cpu_has_msa) {
Paul Burtona5e9a692014-01-27 15:23:10 +00001533 c->msa_id = cpu_get_msa_id();
Paul Burtona8ad1362014-01-28 14:28:43 +00001534 WARN(c->msa_id & MSA_IR_WRPF,
1535 "Vector register partitioning unimplemented!");
Paul Burton3cc9fa72015-07-27 12:58:25 -07001536 elf_hwcap |= HWCAP_MIPS_MSA;
Paul Burtona8ad1362014-01-28 14:28:43 +00001537 }
Paul Burtona5e9a692014-01-27 15:23:10 +00001538
Guenter Roeck91dfc422010-02-02 08:52:20 -08001539 cpu_probe_vmbits(c);
David Daney949e51b2010-10-14 11:32:33 -07001540
1541#ifdef CONFIG_64BIT
1542 if (cpu == 0)
1543 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1544#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545}
1546
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001547void cpu_report(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548{
1549 struct cpuinfo_mips *c = &current_cpu_data;
1550
Leonid Yegoshind9f897c2013-10-07 10:43:32 +01001551 pr_info("CPU%d revision is: %08x (%s)\n",
1552 smp_processor_id(), c->processor_id, cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 if (c->options & MIPS_CPU_FPU)
Ralf Baechle9966db252007-10-11 23:46:17 +01001554 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
Paul Burtona5e9a692014-01-27 15:23:10 +00001555 if (cpu_has_msa)
1556 pr_info("MSA revision is: %08x\n", c->msa_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557}