Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 37 | /* |
| 38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 39 | * over cache flushing. |
| 40 | */ |
| 41 | struct pipe_control { |
| 42 | struct drm_i915_gem_object *obj; |
| 43 | volatile u32 *cpu_page; |
| 44 | u32 gtt_offset; |
| 45 | }; |
| 46 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 47 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 48 | { |
| 49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
| 50 | if (space < 0) |
| 51 | space += ring->size; |
| 52 | return space; |
| 53 | } |
| 54 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 55 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 57 | u32 invalidate_domains, |
| 58 | u32 flush_domains) |
| 59 | { |
| 60 | u32 cmd; |
| 61 | int ret; |
| 62 | |
| 63 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 65 | cmd |= MI_NO_WRITE_FLUSH; |
| 66 | |
| 67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 68 | cmd |= MI_READ_FLUSH; |
| 69 | |
| 70 | ret = intel_ring_begin(ring, 2); |
| 71 | if (ret) |
| 72 | return ret; |
| 73 | |
| 74 | intel_ring_emit(ring, cmd); |
| 75 | intel_ring_emit(ring, MI_NOOP); |
| 76 | intel_ring_advance(ring); |
| 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | static int |
| 82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 83 | u32 invalidate_domains, |
| 84 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 85 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 86 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 87 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 88 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 89 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 90 | /* |
| 91 | * read/write caches: |
| 92 | * |
| 93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 95 | * also flushed at 2d versus 3d pipeline switches. |
| 96 | * |
| 97 | * read-only caches: |
| 98 | * |
| 99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 100 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 101 | * |
| 102 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 103 | * |
| 104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 105 | * invalidated when MI_EXE_FLUSH is set. |
| 106 | * |
| 107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 108 | * invalidated with every MI_FLUSH. |
| 109 | * |
| 110 | * TLBs: |
| 111 | * |
| 112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 115 | * are flushed at any MI_FLUSH. |
| 116 | */ |
| 117 | |
| 118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 120 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 122 | cmd |= MI_EXE_FLUSH; |
| 123 | |
| 124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 125 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 126 | cmd |= MI_INVALIDATE_ISP; |
| 127 | |
| 128 | ret = intel_ring_begin(ring, 2); |
| 129 | if (ret) |
| 130 | return ret; |
| 131 | |
| 132 | intel_ring_emit(ring, cmd); |
| 133 | intel_ring_emit(ring, MI_NOOP); |
| 134 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 135 | |
| 136 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 137 | } |
| 138 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 139 | /** |
| 140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 141 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 143 | * |
| 144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 145 | * produced by non-pipelined state commands), software needs to first |
| 146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 147 | * 0. |
| 148 | * |
| 149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 151 | * |
| 152 | * And the workaround for these two requires this workaround first: |
| 153 | * |
| 154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 155 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 156 | * flushes. |
| 157 | * |
| 158 | * And this last workaround is tricky because of the requirements on |
| 159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 160 | * volume 2 part 1: |
| 161 | * |
| 162 | * "1 of the following must also be set: |
| 163 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 164 | * - Depth Cache Flush Enable ([0] of DW1) |
| 165 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 166 | * - Depth Stall ([13] of DW1) |
| 167 | * - Post-Sync Operation ([13] of DW1) |
| 168 | * - Notify Enable ([8] of DW1)" |
| 169 | * |
| 170 | * The cache flushes require the workaround flush that triggered this |
| 171 | * one, so we can't use it. Depth stall would trigger the same. |
| 172 | * Post-sync nonzero is what triggered this second workaround, so we |
| 173 | * can't use that one either. Notify enable is IRQs, which aren't |
| 174 | * really our business. That leaves only stall at scoreboard. |
| 175 | */ |
| 176 | static int |
| 177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 178 | { |
| 179 | struct pipe_control *pc = ring->private; |
| 180 | u32 scratch_addr = pc->gtt_offset + 128; |
| 181 | int ret; |
| 182 | |
| 183 | |
| 184 | ret = intel_ring_begin(ring, 6); |
| 185 | if (ret) |
| 186 | return ret; |
| 187 | |
| 188 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 189 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 190 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 192 | intel_ring_emit(ring, 0); /* low dword */ |
| 193 | intel_ring_emit(ring, 0); /* high dword */ |
| 194 | intel_ring_emit(ring, MI_NOOP); |
| 195 | intel_ring_advance(ring); |
| 196 | |
| 197 | ret = intel_ring_begin(ring, 6); |
| 198 | if (ret) |
| 199 | return ret; |
| 200 | |
| 201 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 202 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 204 | intel_ring_emit(ring, 0); |
| 205 | intel_ring_emit(ring, 0); |
| 206 | intel_ring_emit(ring, MI_NOOP); |
| 207 | intel_ring_advance(ring); |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static int |
| 213 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 214 | u32 invalidate_domains, u32 flush_domains) |
| 215 | { |
| 216 | u32 flags = 0; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 217 | int ret; |
| 218 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 219 | /* Just flush everything. Experiments have shown that reducing the |
| 220 | * number of bits based on the write domains has little performance |
| 221 | * impact. |
| 222 | */ |
| 223 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
Ben Widawsky | cc0f639 | 2012-06-04 14:42:49 -0700 | [diff] [blame] | 224 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 225 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 226 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 227 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 228 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 229 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 230 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 231 | /* |
| 232 | * Ensure that any following seqno writes only happen when the render |
| 233 | * cache is indeed flushed (but only if the caller actually wants that). |
| 234 | */ |
| 235 | if (flush_domains) |
| 236 | flags |= PIPE_CONTROL_CS_STALL; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 237 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame^] | 238 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 239 | if (ret) |
| 240 | return ret; |
| 241 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame^] | 242 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 243 | intel_ring_emit(ring, flags); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame^] | 244 | intel_ring_emit(ring, 0); |
| 245 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 246 | intel_ring_advance(ring); |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame^] | 251 | static int |
| 252 | gen6_render_ring_flush__wa(struct intel_ring_buffer *ring, |
| 253 | u32 invalidate_domains, u32 flush_domains) |
| 254 | { |
| 255 | int ret; |
| 256 | |
| 257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 258 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 259 | if (ret) |
| 260 | return ret; |
| 261 | |
| 262 | return gen6_render_ring_flush(ring, invalidate_domains, flush_domains); |
| 263 | } |
| 264 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 265 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 266 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 267 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 268 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 269 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 270 | } |
| 271 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 272 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 273 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 274 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 275 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 276 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 277 | |
| 278 | return I915_READ(acthd_reg); |
| 279 | } |
| 280 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 281 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 282 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 283 | struct drm_device *dev = ring->dev; |
| 284 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 285 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 286 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 287 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 288 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 289 | if (HAS_FORCE_WAKE(dev)) |
| 290 | gen6_gt_force_wake_get(dev_priv); |
| 291 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 292 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 293 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 294 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 295 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 296 | |
| 297 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 298 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 299 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 300 | |
| 301 | /* G45 ring initialization fails to reset head to zero */ |
| 302 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 303 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 304 | "ctl %08x head %08x tail %08x start %08x\n", |
| 305 | ring->name, |
| 306 | I915_READ_CTL(ring), |
| 307 | I915_READ_HEAD(ring), |
| 308 | I915_READ_TAIL(ring), |
| 309 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 310 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 311 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 312 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 313 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 314 | DRM_ERROR("failed to set %s head to zero " |
| 315 | "ctl %08x head %08x tail %08x start %08x\n", |
| 316 | ring->name, |
| 317 | I915_READ_CTL(ring), |
| 318 | I915_READ_HEAD(ring), |
| 319 | I915_READ_TAIL(ring), |
| 320 | I915_READ_START(ring)); |
| 321 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 322 | } |
| 323 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 324 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 325 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 326 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 327 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 328 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 329 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
| 330 | I915_READ_START(ring) == obj->gtt_offset && |
| 331 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 332 | DRM_ERROR("%s initialization failed " |
| 333 | "ctl %08x head %08x tail %08x start %08x\n", |
| 334 | ring->name, |
| 335 | I915_READ_CTL(ring), |
| 336 | I915_READ_HEAD(ring), |
| 337 | I915_READ_TAIL(ring), |
| 338 | I915_READ_START(ring)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 339 | ret = -EIO; |
| 340 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 341 | } |
| 342 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 343 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 344 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 345 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 346 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 347 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 348 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 349 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 350 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 351 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 352 | out: |
| 353 | if (HAS_FORCE_WAKE(dev)) |
| 354 | gen6_gt_force_wake_put(dev_priv); |
| 355 | |
| 356 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 357 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 358 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 359 | static int |
| 360 | init_pipe_control(struct intel_ring_buffer *ring) |
| 361 | { |
| 362 | struct pipe_control *pc; |
| 363 | struct drm_i915_gem_object *obj; |
| 364 | int ret; |
| 365 | |
| 366 | if (ring->private) |
| 367 | return 0; |
| 368 | |
| 369 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 370 | if (!pc) |
| 371 | return -ENOMEM; |
| 372 | |
| 373 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 374 | if (obj == NULL) { |
| 375 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 376 | ret = -ENOMEM; |
| 377 | goto err; |
| 378 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 379 | |
| 380 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 381 | |
| 382 | ret = i915_gem_object_pin(obj, 4096, true); |
| 383 | if (ret) |
| 384 | goto err_unref; |
| 385 | |
| 386 | pc->gtt_offset = obj->gtt_offset; |
| 387 | pc->cpu_page = kmap(obj->pages[0]); |
| 388 | if (pc->cpu_page == NULL) |
| 389 | goto err_unpin; |
| 390 | |
| 391 | pc->obj = obj; |
| 392 | ring->private = pc; |
| 393 | return 0; |
| 394 | |
| 395 | err_unpin: |
| 396 | i915_gem_object_unpin(obj); |
| 397 | err_unref: |
| 398 | drm_gem_object_unreference(&obj->base); |
| 399 | err: |
| 400 | kfree(pc); |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | static void |
| 405 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 406 | { |
| 407 | struct pipe_control *pc = ring->private; |
| 408 | struct drm_i915_gem_object *obj; |
| 409 | |
| 410 | if (!ring->private) |
| 411 | return; |
| 412 | |
| 413 | obj = pc->obj; |
| 414 | kunmap(obj->pages[0]); |
| 415 | i915_gem_object_unpin(obj); |
| 416 | drm_gem_object_unreference(&obj->base); |
| 417 | |
| 418 | kfree(pc); |
| 419 | ring->private = NULL; |
| 420 | } |
| 421 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 422 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 423 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 424 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 425 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 426 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 427 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 428 | if (INTEL_INFO(dev)->gen > 3) { |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 429 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Jesse Barnes | b095cd0 | 2011-08-12 15:28:32 -0700 | [diff] [blame] | 430 | if (IS_GEN7(dev)) |
| 431 | I915_WRITE(GFX_MODE_GEN7, |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 432 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 433 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 434 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 435 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 436 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 437 | ret = init_pipe_control(ring); |
| 438 | if (ret) |
| 439 | return ret; |
| 440 | } |
| 441 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 442 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 443 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 444 | * "If this bit is set, STCunit will have LRA as replacement |
| 445 | * policy. [...] This bit must be reset. LRA replacement |
| 446 | * policy is not supported." |
| 447 | */ |
| 448 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 449 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 12b0286 | 2012-06-04 14:42:50 -0700 | [diff] [blame] | 450 | |
| 451 | /* This is not explicitly set for GEN6, so read the register. |
| 452 | * see intel_ring_mi_set_context() for why we care. |
| 453 | * TODO: consider explicitly setting the bit for GEN5 |
| 454 | */ |
| 455 | ring->itlb_before_ctx_switch = |
| 456 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 457 | } |
| 458 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 459 | if (INTEL_INFO(dev)->gen >= 6) |
| 460 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 461 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 462 | if (HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 463 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 464 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 465 | return ret; |
| 466 | } |
| 467 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 468 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 469 | { |
| 470 | if (!ring->private) |
| 471 | return; |
| 472 | |
| 473 | cleanup_pipe_control(ring); |
| 474 | } |
| 475 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 476 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 477 | update_mboxes(struct intel_ring_buffer *ring, |
| 478 | u32 seqno, |
| 479 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 480 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 481 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
| 482 | MI_SEMAPHORE_GLOBAL_GTT | |
| 483 | MI_SEMAPHORE_REGISTER | |
| 484 | MI_SEMAPHORE_UPDATE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 485 | intel_ring_emit(ring, seqno); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 486 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 487 | } |
| 488 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 489 | /** |
| 490 | * gen6_add_request - Update the semaphore mailbox registers |
| 491 | * |
| 492 | * @ring - ring that is adding a request |
| 493 | * @seqno - return seqno stuck into the ring |
| 494 | * |
| 495 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 496 | * This acts like a signal in the canonical semaphore. |
| 497 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 498 | static int |
| 499 | gen6_add_request(struct intel_ring_buffer *ring, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 500 | u32 *seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 501 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 502 | u32 mbox1_reg; |
| 503 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 504 | int ret; |
| 505 | |
| 506 | ret = intel_ring_begin(ring, 10); |
| 507 | if (ret) |
| 508 | return ret; |
| 509 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 510 | mbox1_reg = ring->signal_mbox[0]; |
| 511 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 512 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 513 | *seqno = i915_gem_next_request_seqno(ring); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 514 | |
| 515 | update_mboxes(ring, *seqno, mbox1_reg); |
| 516 | update_mboxes(ring, *seqno, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 517 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 518 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 519 | intel_ring_emit(ring, *seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 520 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 521 | intel_ring_advance(ring); |
| 522 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 523 | return 0; |
| 524 | } |
| 525 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 526 | /** |
| 527 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 528 | * |
| 529 | * @waiter - ring that is waiting |
| 530 | * @signaller - ring which has, or will signal |
| 531 | * @seqno - seqno which the waiter will block on |
| 532 | */ |
| 533 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 534 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 535 | struct intel_ring_buffer *signaller, |
| 536 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 537 | { |
| 538 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 539 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 540 | MI_SEMAPHORE_COMPARE | |
| 541 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 542 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 543 | /* Throughout all of the GEM code, seqno passed implies our current |
| 544 | * seqno is >= the last seqno executed. However for hardware the |
| 545 | * comparison is strictly greater than. |
| 546 | */ |
| 547 | seqno -= 1; |
| 548 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 549 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 550 | MI_SEMAPHORE_SYNC_INVALID); |
| 551 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 552 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 553 | if (ret) |
| 554 | return ret; |
| 555 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 556 | intel_ring_emit(waiter, |
| 557 | dw1 | signaller->semaphore_register[waiter->id]); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 558 | intel_ring_emit(waiter, seqno); |
| 559 | intel_ring_emit(waiter, 0); |
| 560 | intel_ring_emit(waiter, MI_NOOP); |
| 561 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 562 | |
| 563 | return 0; |
| 564 | } |
| 565 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 566 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 567 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 568 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 569 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 570 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 571 | intel_ring_emit(ring__, 0); \ |
| 572 | intel_ring_emit(ring__, 0); \ |
| 573 | } while (0) |
| 574 | |
| 575 | static int |
| 576 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 577 | u32 *result) |
| 578 | { |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 579 | u32 seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 580 | struct pipe_control *pc = ring->private; |
| 581 | u32 scratch_addr = pc->gtt_offset + 128; |
| 582 | int ret; |
| 583 | |
| 584 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 585 | * incoherent with writes to memory, i.e. completely fubar, |
| 586 | * so we need to use PIPE_NOTIFY instead. |
| 587 | * |
| 588 | * However, we also need to workaround the qword write |
| 589 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 590 | * memory before requesting an interrupt. |
| 591 | */ |
| 592 | ret = intel_ring_begin(ring, 32); |
| 593 | if (ret) |
| 594 | return ret; |
| 595 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 596 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 597 | PIPE_CONTROL_WRITE_FLUSH | |
| 598 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 599 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 600 | intel_ring_emit(ring, seqno); |
| 601 | intel_ring_emit(ring, 0); |
| 602 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 603 | scratch_addr += 128; /* write to separate cachelines */ |
| 604 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 605 | scratch_addr += 128; |
| 606 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 607 | scratch_addr += 128; |
| 608 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 609 | scratch_addr += 128; |
| 610 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 611 | scratch_addr += 128; |
| 612 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 613 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 614 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 615 | PIPE_CONTROL_WRITE_FLUSH | |
| 616 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 617 | PIPE_CONTROL_NOTIFY); |
| 618 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 619 | intel_ring_emit(ring, seqno); |
| 620 | intel_ring_emit(ring, 0); |
| 621 | intel_ring_advance(ring); |
| 622 | |
| 623 | *result = seqno; |
| 624 | return 0; |
| 625 | } |
| 626 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 627 | static u32 |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 628 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) |
| 629 | { |
| 630 | struct drm_device *dev = ring->dev; |
| 631 | |
| 632 | /* Workaround to force correct ordering between irq and seqno writes on |
| 633 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 634 | * ACTHD) before reading the status page. */ |
Daniel Vetter | 1c7eaac | 2012-03-27 09:31:24 +0200 | [diff] [blame] | 635 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 636 | intel_ring_get_active_head(ring); |
| 637 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 638 | } |
| 639 | |
| 640 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 641 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 642 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 643 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 644 | } |
| 645 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 646 | static u32 |
| 647 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 648 | { |
| 649 | struct pipe_control *pc = ring->private; |
| 650 | return pc->cpu_page[0]; |
| 651 | } |
| 652 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 653 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 654 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 655 | { |
| 656 | struct drm_device *dev = ring->dev; |
| 657 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 658 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 659 | |
| 660 | if (!dev->irq_enabled) |
| 661 | return false; |
| 662 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 663 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 664 | if (ring->irq_refcount++ == 0) { |
| 665 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 666 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 667 | POSTING_READ(GTIMR); |
| 668 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 669 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 670 | |
| 671 | return true; |
| 672 | } |
| 673 | |
| 674 | static void |
| 675 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 676 | { |
| 677 | struct drm_device *dev = ring->dev; |
| 678 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 679 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 680 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 681 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 682 | if (--ring->irq_refcount == 0) { |
| 683 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 684 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 685 | POSTING_READ(GTIMR); |
| 686 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 687 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 691 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 692 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 693 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 694 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 695 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 696 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 697 | if (!dev->irq_enabled) |
| 698 | return false; |
| 699 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 700 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 701 | if (ring->irq_refcount++ == 0) { |
| 702 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 703 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 704 | POSTING_READ(IMR); |
| 705 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 706 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 707 | |
| 708 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 709 | } |
| 710 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 711 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 712 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 713 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 714 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 715 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 716 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 717 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 718 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 719 | if (--ring->irq_refcount == 0) { |
| 720 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 721 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 722 | POSTING_READ(IMR); |
| 723 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 724 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 725 | } |
| 726 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 727 | static bool |
| 728 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 729 | { |
| 730 | struct drm_device *dev = ring->dev; |
| 731 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 732 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 733 | |
| 734 | if (!dev->irq_enabled) |
| 735 | return false; |
| 736 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 737 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 738 | if (ring->irq_refcount++ == 0) { |
| 739 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 740 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 741 | POSTING_READ16(IMR); |
| 742 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 743 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 744 | |
| 745 | return true; |
| 746 | } |
| 747 | |
| 748 | static void |
| 749 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 750 | { |
| 751 | struct drm_device *dev = ring->dev; |
| 752 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 753 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 754 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 755 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 756 | if (--ring->irq_refcount == 0) { |
| 757 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 758 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 759 | POSTING_READ16(IMR); |
| 760 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 761 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 762 | } |
| 763 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 764 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 765 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 766 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 767 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 768 | u32 mmio = 0; |
| 769 | |
| 770 | /* The ring status page addresses are no longer next to the rest of |
| 771 | * the ring registers as of gen7. |
| 772 | */ |
| 773 | if (IS_GEN7(dev)) { |
| 774 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 775 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 776 | mmio = RENDER_HWS_PGA_GEN7; |
| 777 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 778 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 779 | mmio = BLT_HWS_PGA_GEN7; |
| 780 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 781 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 782 | mmio = BSD_HWS_PGA_GEN7; |
| 783 | break; |
| 784 | } |
| 785 | } else if (IS_GEN6(ring->dev)) { |
| 786 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 787 | } else { |
| 788 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 789 | } |
| 790 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 791 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 792 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 793 | } |
| 794 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 795 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 796 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 797 | u32 invalidate_domains, |
| 798 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 799 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 800 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 801 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 802 | ret = intel_ring_begin(ring, 2); |
| 803 | if (ret) |
| 804 | return ret; |
| 805 | |
| 806 | intel_ring_emit(ring, MI_FLUSH); |
| 807 | intel_ring_emit(ring, MI_NOOP); |
| 808 | intel_ring_advance(ring); |
| 809 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 810 | } |
| 811 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 812 | static int |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 813 | i9xx_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 814 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 815 | { |
| 816 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 817 | int ret; |
| 818 | |
| 819 | ret = intel_ring_begin(ring, 4); |
| 820 | if (ret) |
| 821 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 822 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 823 | seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 824 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 825 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 826 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 827 | intel_ring_emit(ring, seqno); |
| 828 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 829 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 830 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 831 | *result = seqno; |
| 832 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 833 | } |
| 834 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 835 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 836 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 837 | { |
| 838 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 839 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 840 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 841 | |
| 842 | if (!dev->irq_enabled) |
| 843 | return false; |
| 844 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 845 | /* It looks like we need to prevent the gt from suspending while waiting |
| 846 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 847 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 848 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 849 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 850 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 851 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 852 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 853 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
| 854 | GEN6_RENDER_L3_PARITY_ERROR)); |
| 855 | else |
| 856 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 857 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 858 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 859 | POSTING_READ(GTIMR); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 860 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 861 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 862 | |
| 863 | return true; |
| 864 | } |
| 865 | |
| 866 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 867 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 868 | { |
| 869 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 870 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 871 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 872 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 873 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 874 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 875 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 876 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 877 | else |
| 878 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 879 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 880 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 881 | POSTING_READ(GTIMR); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 882 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 883 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 884 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 885 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 886 | } |
| 887 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 888 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 889 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 890 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 891 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 892 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 893 | ret = intel_ring_begin(ring, 2); |
| 894 | if (ret) |
| 895 | return ret; |
| 896 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 897 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 898 | MI_BATCH_BUFFER_START | |
| 899 | MI_BATCH_GTT | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 900 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 901 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 902 | intel_ring_advance(ring); |
| 903 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 904 | return 0; |
| 905 | } |
| 906 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 907 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 908 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 909 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 910 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 911 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 912 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 913 | ret = intel_ring_begin(ring, 4); |
| 914 | if (ret) |
| 915 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 916 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 917 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 918 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 919 | intel_ring_emit(ring, offset + len - 8); |
| 920 | intel_ring_emit(ring, 0); |
| 921 | intel_ring_advance(ring); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 922 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 923 | return 0; |
| 924 | } |
| 925 | |
| 926 | static int |
| 927 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 928 | u32 offset, u32 len) |
| 929 | { |
| 930 | int ret; |
| 931 | |
| 932 | ret = intel_ring_begin(ring, 2); |
| 933 | if (ret) |
| 934 | return ret; |
| 935 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 936 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 937 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 938 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 939 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 940 | return 0; |
| 941 | } |
| 942 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 943 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 944 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 945 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 946 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 947 | obj = ring->status_page.obj; |
| 948 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 949 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 950 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 951 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 952 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 953 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 954 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 955 | } |
| 956 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 957 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 958 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 959 | struct drm_device *dev = ring->dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 960 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 961 | int ret; |
| 962 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 963 | obj = i915_gem_alloc_object(dev, 4096); |
| 964 | if (obj == NULL) { |
| 965 | DRM_ERROR("Failed to allocate status page\n"); |
| 966 | ret = -ENOMEM; |
| 967 | goto err; |
| 968 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 969 | |
| 970 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 971 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 972 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 973 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 974 | goto err_unref; |
| 975 | } |
| 976 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 977 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 978 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 979 | if (ring->status_page.page_addr == NULL) { |
Ben Widawsky | 2e6c21e | 2012-07-12 23:16:12 -0700 | [diff] [blame] | 980 | ret = -ENOMEM; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 981 | goto err_unpin; |
| 982 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 983 | ring->status_page.obj = obj; |
| 984 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 985 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 986 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 987 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 988 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 989 | |
| 990 | return 0; |
| 991 | |
| 992 | err_unpin: |
| 993 | i915_gem_object_unpin(obj); |
| 994 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 995 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 996 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 997 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 998 | } |
| 999 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1000 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1001 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1002 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1003 | struct drm_i915_gem_object *obj; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1004 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1005 | int ret; |
| 1006 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1007 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1008 | INIT_LIST_HEAD(&ring->active_list); |
| 1009 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1010 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1011 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1012 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1013 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1014 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1015 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1016 | if (ret) |
| 1017 | return ret; |
| 1018 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1019 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1020 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1021 | if (obj == NULL) { |
| 1022 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1023 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1024 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1025 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1026 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1027 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1028 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1029 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1030 | if (ret) |
| 1031 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1032 | |
Chris Wilson | 3eef891 | 2012-06-04 17:05:40 +0100 | [diff] [blame] | 1033 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1034 | if (ret) |
| 1035 | goto err_unpin; |
| 1036 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1037 | ring->virtual_start = |
| 1038 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, |
| 1039 | ring->size); |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1040 | if (ring->virtual_start == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1041 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1042 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1043 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1044 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1045 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1046 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1047 | if (ret) |
| 1048 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1049 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1050 | /* Workaround an erratum on the i830 which causes a hang if |
| 1051 | * the TAIL pointer points to within the last 2 cachelines |
| 1052 | * of the buffer. |
| 1053 | */ |
| 1054 | ring->effective_size = ring->size; |
Chris Wilson | 27c1cbd | 2012-04-09 13:59:46 +0100 | [diff] [blame] | 1055 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1056 | ring->effective_size -= 128; |
| 1057 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1058 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1059 | |
| 1060 | err_unmap: |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1061 | iounmap(ring->virtual_start); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1062 | err_unpin: |
| 1063 | i915_gem_object_unpin(obj); |
| 1064 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1065 | drm_gem_object_unreference(&obj->base); |
| 1066 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1067 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1068 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1069 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1070 | } |
| 1071 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1072 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1073 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1074 | struct drm_i915_private *dev_priv; |
| 1075 | int ret; |
| 1076 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1077 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1078 | return; |
| 1079 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1080 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1081 | dev_priv = ring->dev->dev_private; |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 1082 | ret = intel_wait_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1083 | if (ret) |
| 1084 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1085 | ring->name, ret); |
| 1086 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1087 | I915_WRITE_CTL(ring, 0); |
| 1088 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1089 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1090 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1091 | i915_gem_object_unpin(ring->obj); |
| 1092 | drm_gem_object_unreference(&ring->obj->base); |
| 1093 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1094 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1095 | if (ring->cleanup) |
| 1096 | ring->cleanup(ring); |
| 1097 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1098 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1099 | } |
| 1100 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1101 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1102 | { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1103 | uint32_t __iomem *virt; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1104 | int rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1105 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1106 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1107 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1108 | if (ret) |
| 1109 | return ret; |
| 1110 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1111 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1112 | virt = ring->virtual_start + ring->tail; |
| 1113 | rem /= 4; |
| 1114 | while (rem--) |
| 1115 | iowrite32(MI_NOOP, virt++); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1116 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1117 | ring->tail = 0; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1118 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1119 | |
| 1120 | return 0; |
| 1121 | } |
| 1122 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1123 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1124 | { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1125 | int ret; |
| 1126 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1127 | ret = i915_wait_seqno(ring, seqno); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1128 | if (!ret) |
| 1129 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1130 | |
| 1131 | return ret; |
| 1132 | } |
| 1133 | |
| 1134 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1135 | { |
| 1136 | struct drm_i915_gem_request *request; |
| 1137 | u32 seqno = 0; |
| 1138 | int ret; |
| 1139 | |
| 1140 | i915_gem_retire_requests_ring(ring); |
| 1141 | |
| 1142 | if (ring->last_retired_head != -1) { |
| 1143 | ring->head = ring->last_retired_head; |
| 1144 | ring->last_retired_head = -1; |
| 1145 | ring->space = ring_space(ring); |
| 1146 | if (ring->space >= n) |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | list_for_each_entry(request, &ring->request_list, list) { |
| 1151 | int space; |
| 1152 | |
| 1153 | if (request->tail == -1) |
| 1154 | continue; |
| 1155 | |
| 1156 | space = request->tail - (ring->tail + 8); |
| 1157 | if (space < 0) |
| 1158 | space += ring->size; |
| 1159 | if (space >= n) { |
| 1160 | seqno = request->seqno; |
| 1161 | break; |
| 1162 | } |
| 1163 | |
| 1164 | /* Consume this request in case we need more space than |
| 1165 | * is available and so need to prevent a race between |
| 1166 | * updating last_retired_head and direct reads of |
| 1167 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1168 | */ |
| 1169 | request->tail = -1; |
| 1170 | } |
| 1171 | |
| 1172 | if (seqno == 0) |
| 1173 | return -ENOSPC; |
| 1174 | |
| 1175 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1176 | if (ret) |
| 1177 | return ret; |
| 1178 | |
| 1179 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1180 | return -ENOSPC; |
| 1181 | |
| 1182 | ring->head = ring->last_retired_head; |
| 1183 | ring->last_retired_head = -1; |
| 1184 | ring->space = ring_space(ring); |
| 1185 | if (WARN_ON(ring->space < n)) |
| 1186 | return -ENOSPC; |
| 1187 | |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1191 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1192 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1193 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1194 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1195 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1196 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1197 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1198 | ret = intel_ring_wait_request(ring, n); |
| 1199 | if (ret != -ENOSPC) |
| 1200 | return ret; |
| 1201 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1202 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1203 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1204 | * leaving it early runs the risk of corrupting GEM state (due |
| 1205 | * to running on almost untested codepaths). But on resume |
| 1206 | * timers don't work yet, so prevent a complete hang in that |
| 1207 | * case by choosing an insanely large timeout. */ |
| 1208 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1209 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1210 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1211 | ring->head = I915_READ_HEAD(ring); |
| 1212 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1213 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1214 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | if (dev->primary->master) { |
| 1219 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1220 | if (master_priv->sarea_priv) |
| 1221 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1222 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1223 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1224 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1225 | |
| 1226 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
| 1227 | if (ret) |
| 1228 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1229 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1230 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1231 | return -EBUSY; |
| 1232 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1233 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1234 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1235 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1236 | { |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1237 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 1238 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1239 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1240 | |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1241 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
| 1242 | if (ret) |
| 1243 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1244 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1245 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1246 | ret = intel_wrap_ring_buffer(ring); |
| 1247 | if (unlikely(ret)) |
| 1248 | return ret; |
| 1249 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1250 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1251 | if (unlikely(ring->space < n)) { |
| 1252 | ret = intel_wait_ring_buffer(ring, n); |
| 1253 | if (unlikely(ret)) |
| 1254 | return ret; |
| 1255 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1256 | |
| 1257 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1258 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1259 | } |
| 1260 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1261 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1262 | { |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1263 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1264 | |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1265 | ring->tail &= ring->size - 1; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1266 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
| 1267 | return; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1268 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1269 | } |
| 1270 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1271 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1272 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1273 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1274 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1275 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1276 | |
| 1277 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1278 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1279 | /* Disable notification that the ring is IDLE. The GT |
| 1280 | * will then assume that it is busy and bring it out of rc6. |
| 1281 | */ |
| 1282 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1283 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1284 | |
| 1285 | /* Clear the context id. Here be magic! */ |
| 1286 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1287 | |
| 1288 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1289 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1290 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1291 | 50)) |
| 1292 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1293 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1294 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1295 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1296 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1297 | |
| 1298 | /* Let the ring send IDLE messages to the GT again, |
| 1299 | * and so let it sleep to conserve power when idle. |
| 1300 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1301 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1302 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1303 | } |
| 1304 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1305 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1306 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1307 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1308 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1309 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1310 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1311 | ret = intel_ring_begin(ring, 4); |
| 1312 | if (ret) |
| 1313 | return ret; |
| 1314 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1315 | cmd = MI_FLUSH_DW; |
| 1316 | if (invalidate & I915_GEM_GPU_DOMAINS) |
| 1317 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 1318 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1319 | intel_ring_emit(ring, 0); |
| 1320 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1321 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1322 | intel_ring_advance(ring); |
| 1323 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1324 | } |
| 1325 | |
| 1326 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1327 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1328 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1329 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1330 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1331 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1332 | ret = intel_ring_begin(ring, 2); |
| 1333 | if (ret) |
| 1334 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1335 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1336 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
| 1337 | /* bit0-7 is the length on GEN6+ */ |
| 1338 | intel_ring_emit(ring, offset); |
| 1339 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1340 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1341 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1342 | } |
| 1343 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1344 | /* Blitter support (SandyBridge+) */ |
| 1345 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1346 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1347 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1348 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1349 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1350 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1351 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1352 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1353 | if (ret) |
| 1354 | return ret; |
| 1355 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1356 | cmd = MI_FLUSH_DW; |
| 1357 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
| 1358 | cmd |= MI_INVALIDATE_TLB; |
| 1359 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1360 | intel_ring_emit(ring, 0); |
| 1361 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1362 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1363 | intel_ring_advance(ring); |
| 1364 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1365 | } |
| 1366 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1367 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1368 | { |
| 1369 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1370 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1371 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1372 | ring->name = "render ring"; |
| 1373 | ring->id = RCS; |
| 1374 | ring->mmio_base = RENDER_RING_BASE; |
| 1375 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1376 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1377 | ring->add_request = gen6_add_request; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 1378 | ring->flush = gen6_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame^] | 1379 | if (INTEL_INFO(dev)->gen == 6) |
| 1380 | ring->flush = gen6_render_ring_flush__wa; |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1381 | ring->irq_get = gen6_ring_get_irq; |
| 1382 | ring->irq_put = gen6_ring_put_irq; |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 1383 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1384 | ring->get_seqno = gen6_ring_get_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1385 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1386 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
| 1387 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; |
| 1388 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; |
| 1389 | ring->signal_mbox[0] = GEN6_VRSYNC; |
| 1390 | ring->signal_mbox[1] = GEN6_BRSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1391 | } else if (IS_GEN5(dev)) { |
| 1392 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1393 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1394 | ring->get_seqno = pc_render_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1395 | ring->irq_get = gen5_ring_get_irq; |
| 1396 | ring->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1397 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1398 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1399 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1400 | if (INTEL_INFO(dev)->gen < 4) |
| 1401 | ring->flush = gen2_render_ring_flush; |
| 1402 | else |
| 1403 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1404 | ring->get_seqno = ring_get_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1405 | if (IS_GEN2(dev)) { |
| 1406 | ring->irq_get = i8xx_ring_get_irq; |
| 1407 | ring->irq_put = i8xx_ring_put_irq; |
| 1408 | } else { |
| 1409 | ring->irq_get = i9xx_ring_get_irq; |
| 1410 | ring->irq_put = i9xx_ring_put_irq; |
| 1411 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1412 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1413 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1414 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1415 | if (INTEL_INFO(dev)->gen >= 6) |
| 1416 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1417 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1418 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1419 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1420 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1421 | else |
| 1422 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1423 | ring->init = init_render_ring; |
| 1424 | ring->cleanup = render_ring_cleanup; |
| 1425 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1426 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1427 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1428 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1429 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1430 | } |
| 1431 | |
| 1432 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1433 | } |
| 1434 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1435 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1436 | { |
| 1437 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1438 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1439 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1440 | ring->name = "render ring"; |
| 1441 | ring->id = RCS; |
| 1442 | ring->mmio_base = RENDER_RING_BASE; |
| 1443 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1444 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 1445 | /* non-kms not supported on gen6+ */ |
| 1446 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1447 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1448 | |
| 1449 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 1450 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 1451 | * the special gen5 functions. */ |
| 1452 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1453 | if (INTEL_INFO(dev)->gen < 4) |
| 1454 | ring->flush = gen2_render_ring_flush; |
| 1455 | else |
| 1456 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1457 | ring->get_seqno = ring_get_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1458 | if (IS_GEN2(dev)) { |
| 1459 | ring->irq_get = i8xx_ring_get_irq; |
| 1460 | ring->irq_put = i8xx_ring_put_irq; |
| 1461 | } else { |
| 1462 | ring->irq_get = i9xx_ring_get_irq; |
| 1463 | ring->irq_put = i9xx_ring_put_irq; |
| 1464 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1465 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1466 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1467 | if (INTEL_INFO(dev)->gen >= 4) |
| 1468 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1469 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1470 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1471 | else |
| 1472 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1473 | ring->init = init_render_ring; |
| 1474 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1475 | |
Keith Packard | f323470 | 2011-07-22 10:44:39 -0700 | [diff] [blame] | 1476 | if (!I915_NEED_GFX_HWS(dev)) |
| 1477 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1478 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1479 | ring->dev = dev; |
| 1480 | INIT_LIST_HEAD(&ring->active_list); |
| 1481 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1482 | |
| 1483 | ring->size = size; |
| 1484 | ring->effective_size = ring->size; |
| 1485 | if (IS_I830(ring->dev)) |
| 1486 | ring->effective_size -= 128; |
| 1487 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1488 | ring->virtual_start = ioremap_wc(start, size); |
| 1489 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1490 | DRM_ERROR("can not ioremap virtual address for" |
| 1491 | " ring buffer\n"); |
| 1492 | return -ENOMEM; |
| 1493 | } |
| 1494 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1495 | return 0; |
| 1496 | } |
| 1497 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1498 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1499 | { |
| 1500 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1501 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1502 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1503 | ring->name = "bsd ring"; |
| 1504 | ring->id = VCS; |
| 1505 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1506 | ring->write_tail = ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1507 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1508 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1509 | /* gen6 bsd needs a special wa for tail updates */ |
| 1510 | if (IS_GEN6(dev)) |
| 1511 | ring->write_tail = gen6_bsd_ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1512 | ring->flush = gen6_ring_flush; |
| 1513 | ring->add_request = gen6_add_request; |
| 1514 | ring->get_seqno = gen6_ring_get_seqno; |
| 1515 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; |
| 1516 | ring->irq_get = gen6_ring_get_irq; |
| 1517 | ring->irq_put = gen6_ring_put_irq; |
| 1518 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1519 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1520 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
| 1521 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; |
| 1522 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; |
| 1523 | ring->signal_mbox[0] = GEN6_RVSYNC; |
| 1524 | ring->signal_mbox[1] = GEN6_BVSYNC; |
| 1525 | } else { |
| 1526 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1527 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1528 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1529 | ring->get_seqno = ring_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1530 | if (IS_GEN5(dev)) { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1531 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1532 | ring->irq_get = gen5_ring_get_irq; |
| 1533 | ring->irq_put = gen5_ring_put_irq; |
| 1534 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1535 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1536 | ring->irq_get = i9xx_ring_get_irq; |
| 1537 | ring->irq_put = i9xx_ring_put_irq; |
| 1538 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1539 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1540 | } |
| 1541 | ring->init = init_ring_common; |
| 1542 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1543 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1544 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1545 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1546 | |
| 1547 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1548 | { |
| 1549 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1550 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1551 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1552 | ring->name = "blitter ring"; |
| 1553 | ring->id = BCS; |
| 1554 | |
| 1555 | ring->mmio_base = BLT_RING_BASE; |
| 1556 | ring->write_tail = ring_write_tail; |
| 1557 | ring->flush = blt_ring_flush; |
| 1558 | ring->add_request = gen6_add_request; |
| 1559 | ring->get_seqno = gen6_ring_get_seqno; |
| 1560 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; |
| 1561 | ring->irq_get = gen6_ring_get_irq; |
| 1562 | ring->irq_put = gen6_ring_put_irq; |
| 1563 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1564 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1565 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
| 1566 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; |
| 1567 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; |
| 1568 | ring->signal_mbox[0] = GEN6_RBSYNC; |
| 1569 | ring->signal_mbox[1] = GEN6_VBSYNC; |
| 1570 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1571 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1572 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1573 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1574 | |
| 1575 | int |
| 1576 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 1577 | { |
| 1578 | int ret; |
| 1579 | |
| 1580 | if (!ring->gpu_caches_dirty) |
| 1581 | return 0; |
| 1582 | |
| 1583 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1584 | if (ret) |
| 1585 | return ret; |
| 1586 | |
| 1587 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1588 | |
| 1589 | ring->gpu_caches_dirty = false; |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | int |
| 1594 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 1595 | { |
| 1596 | uint32_t flush_domains; |
| 1597 | int ret; |
| 1598 | |
| 1599 | flush_domains = 0; |
| 1600 | if (ring->gpu_caches_dirty) |
| 1601 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 1602 | |
| 1603 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1604 | if (ret) |
| 1605 | return ret; |
| 1606 | |
| 1607 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1608 | |
| 1609 | ring->gpu_caches_dirty = false; |
| 1610 | return 0; |
| 1611 | } |