Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 30 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "i915_drm.h" |
| 34 | #include "i915_drv.h" |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/console.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 38 | #include <linux/module.h> |
Zhao Yakui | 354ff96 | 2009-07-08 14:13:12 +0800 | [diff] [blame] | 39 | #include "drm_crtc_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 40 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 41 | static int i915_modeset __read_mostly = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 43 | MODULE_PARM_DESC(modeset, |
| 44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
| 45 | "1=on, -1=force vga console preference [default])"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 46 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
| 53 | "Override lid status (0=autodetect [default], 1=lid open, " |
| 54 | "-1=lid closed)"); |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 55 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 56 | unsigned int i915_powersave __read_mostly = 1; |
Chris Wilson | 0aa9927 | 2010-11-02 09:20:50 +0000 | [diff] [blame] | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 58 | MODULE_PARM_DESC(powersave, |
| 59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 60 | |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 61 | int i915_semaphores __read_mostly = -1; |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 63 | MODULE_PARM_DESC(semaphores, |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 65 | |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 66 | int i915_enable_rc6 __read_mostly = -1; |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 69 | "Enable power-saving render C-state 6 (default: -1 (use per-chip default)"); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 70 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 71 | int i915_enable_fbc __read_mostly = -1; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 72 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 73 | MODULE_PARM_DESC(i915_enable_fbc, |
| 74 | "Enable frame buffer compression for power savings " |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 75 | "(default: -1 (use per-chip default))"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 76 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 77 | unsigned int i915_lvds_downclock __read_mostly = 0; |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 78 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 79 | MODULE_PARM_DESC(lvds_downclock, |
| 80 | "Use panel (LVDS/eDP) downclocking for power savings " |
| 81 | "(default: false)"); |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 82 | |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 83 | int i915_lvds_channel_mode __read_mostly; |
| 84 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); |
| 85 | MODULE_PARM_DESC(lvds_channel_mode, |
| 86 | "Specify LVDS channel mode " |
| 87 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
| 88 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 89 | int i915_panel_use_ssc __read_mostly = -1; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 90 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 91 | MODULE_PARM_DESC(lvds_use_ssc, |
| 92 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
Keith Packard | 72bbe58 | 2011-09-26 16:09:45 -0700 | [diff] [blame] | 93 | "(default: auto from VBT)"); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 94 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 95 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 96 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 97 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
Mathias Fröhlich | c10e408 | 2012-03-01 06:44:35 +0100 | [diff] [blame] | 98 | "Override/Ignore selection of SDVO panel mode in the VBT " |
| 99 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 100 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 101 | static bool i915_try_reset __read_mostly = true; |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 102 | module_param_named(reset, i915_try_reset, bool, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 103 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 104 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 105 | bool i915_enable_hangcheck __read_mostly = true; |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 106 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 107 | MODULE_PARM_DESC(enable_hangcheck, |
| 108 | "Periodically check GPU activity for detecting hangs. " |
| 109 | "WARNING: Disabling this can cause system wide hangs. " |
| 110 | "(default: true)"); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 111 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 112 | bool i915_enable_ppgtt __read_mostly = 1; |
| 113 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600); |
| 114 | MODULE_PARM_DESC(i915_enable_ppgtt, |
| 115 | "Enable PPGTT (default: true)"); |
| 116 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 117 | static struct drm_driver driver; |
Zhenyu Wang | 1f7a6e3 | 2010-02-23 14:05:24 +0800 | [diff] [blame] | 118 | extern int intel_agp_enabled; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 119 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 120 | #define INTEL_VGA_DEVICE(id, info) { \ |
Daniel Vetter | 80a2901 | 2011-10-11 10:59:05 +0200 | [diff] [blame] | 121 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 122 | .class_mask = 0xff0000, \ |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 123 | .vendor = 0x8086, \ |
| 124 | .device = id, \ |
| 125 | .subvendor = PCI_ANY_ID, \ |
| 126 | .subdevice = PCI_ANY_ID, \ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 127 | .driver_data = (unsigned long) info } |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 128 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 129 | static const struct intel_device_info intel_i830_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 130 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 131 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 132 | }; |
| 133 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 134 | static const struct intel_device_info intel_845g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 135 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 136 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 137 | }; |
| 138 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 139 | static const struct intel_device_info intel_i85x_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 140 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 141 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 142 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 143 | }; |
| 144 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 145 | static const struct intel_device_info intel_i865g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 146 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 147 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 148 | }; |
| 149 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 150 | static const struct intel_device_info intel_i915g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 151 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 152 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 153 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 154 | static const struct intel_device_info intel_i915gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 155 | .gen = 3, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 156 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 157 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 158 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 159 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 160 | static const struct intel_device_info intel_i945g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 161 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 162 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 163 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 164 | static const struct intel_device_info intel_i945gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 165 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 166 | .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 167 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 168 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 169 | }; |
| 170 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 171 | static const struct intel_device_info intel_i965g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 172 | .gen = 4, .is_broadwater = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 173 | .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 174 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 175 | }; |
| 176 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 177 | static const struct intel_device_info intel_i965gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 178 | .gen = 4, .is_crestline = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 179 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 180 | .has_overlay = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 181 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 182 | }; |
| 183 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 184 | static const struct intel_device_info intel_g33_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 185 | .gen = 3, .is_g33 = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 186 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 187 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 188 | }; |
| 189 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 190 | static const struct intel_device_info intel_g45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 191 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 192 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 193 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 194 | }; |
| 195 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 196 | static const struct intel_device_info intel_gm45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 197 | .gen = 4, .is_g4x = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 198 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 199 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 200 | .supports_tv = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 201 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 202 | }; |
| 203 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 204 | static const struct intel_device_info intel_pineview_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 205 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 206 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 207 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 208 | }; |
| 209 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 210 | static const struct intel_device_info intel_ironlake_d_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 211 | .gen = 5, |
Eugeni Dodonov | 5a117db | 2012-01-05 09:34:29 -0200 | [diff] [blame] | 212 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 213 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 214 | }; |
| 215 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 216 | static const struct intel_device_info intel_ironlake_m_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 217 | .gen = 5, .is_mobile = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 219 | .has_fbc = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 220 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 221 | }; |
| 222 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 223 | static const struct intel_device_info intel_sandybridge_d_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 224 | .gen = 6, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 225 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 226 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 227 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 228 | .has_llc = 1, |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 229 | }; |
| 230 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 231 | static const struct intel_device_info intel_sandybridge_m_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 232 | .gen = 6, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 233 | .need_gfx_hws = 1, .has_hotplug = 1, |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 234 | .has_fbc = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 235 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 236 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 237 | .has_llc = 1, |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 238 | }; |
| 239 | |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 240 | static const struct intel_device_info intel_ivybridge_d_info = { |
| 241 | .is_ivybridge = 1, .gen = 7, |
| 242 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 243 | .has_bsd_ring = 1, |
| 244 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 245 | .has_llc = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | static const struct intel_device_info intel_ivybridge_m_info = { |
| 249 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
| 250 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 251 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
| 252 | .has_bsd_ring = 1, |
| 253 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 254 | .has_llc = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 255 | }; |
| 256 | |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame^] | 257 | static const struct intel_device_info intel_valleyview_m_info = { |
| 258 | .gen = 7, .is_mobile = 1, |
| 259 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 260 | .has_fbc = 0, |
| 261 | .has_bsd_ring = 1, |
| 262 | .has_blt_ring = 1, |
| 263 | .is_valleyview = 1, |
| 264 | }; |
| 265 | |
| 266 | static const struct intel_device_info intel_valleyview_d_info = { |
| 267 | .gen = 7, |
| 268 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 269 | .has_fbc = 0, |
| 270 | .has_bsd_ring = 1, |
| 271 | .has_blt_ring = 1, |
| 272 | .is_valleyview = 1, |
| 273 | }; |
| 274 | |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 275 | static const struct pci_device_id pciidlist[] = { /* aka */ |
| 276 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ |
| 277 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ |
| 278 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 279 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 280 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
| 281 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
| 282 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
| 283 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
| 284 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
| 285 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
| 286 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
| 287 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
| 288 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
| 289 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
| 290 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
| 291 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
| 292 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
| 293 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
| 294 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
| 295 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
| 296 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
| 297 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
| 298 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
| 299 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
| 300 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
| 301 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
Chris Wilson | 41a5142 | 2010-09-17 08:22:30 +0100 | [diff] [blame] | 302 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 303 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
| 304 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
| 305 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
| 306 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 307 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 308 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
| 309 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 310 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 311 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
Zhenyu Wang | 4fefe43 | 2010-08-19 09:46:16 +0800 | [diff] [blame] | 312 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 313 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 314 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
| 315 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
| 316 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
| 317 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
| 318 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 319 | {0, 0, 0} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | }; |
| 321 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 322 | #if defined(CONFIG_DRM_I915_KMS) |
| 323 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 324 | #endif |
| 325 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 326 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 327 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 328 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 329 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 330 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 331 | void intel_detect_pch(struct drm_device *dev) |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 332 | { |
| 333 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 334 | struct pci_dev *pch; |
| 335 | |
| 336 | /* |
| 337 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 338 | * make graphics device passthrough work easy for VMM, that only |
| 339 | * need to expose ISA bridge to let driver know the real hardware |
| 340 | * underneath. This is a requirement from virtualization team. |
| 341 | */ |
| 342 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 343 | if (pch) { |
| 344 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
| 345 | int id; |
| 346 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
| 347 | |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 348 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 349 | dev_priv->pch_type = PCH_IBX; |
| 350 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
| 351 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 352 | dev_priv->pch_type = PCH_CPT; |
| 353 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 354 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 355 | /* PantherPoint is CPT compatible */ |
| 356 | dev_priv->pch_type = PCH_CPT; |
| 357 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 358 | } |
| 359 | } |
| 360 | pci_dev_put(pch); |
| 361 | } |
| 362 | } |
| 363 | |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 364 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
Chris Wilson | eb43f4a | 2010-12-08 17:32:24 +0000 | [diff] [blame] | 365 | { |
| 366 | int count; |
| 367 | |
| 368 | count = 0; |
| 369 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 370 | udelay(10); |
| 371 | |
| 372 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
| 373 | POSTING_READ(FORCEWAKE); |
| 374 | |
| 375 | count = 0; |
| 376 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) |
| 377 | udelay(10); |
| 378 | } |
| 379 | |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 380 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
| 381 | { |
| 382 | int count; |
| 383 | |
| 384 | count = 0; |
| 385 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) |
| 386 | udelay(10); |
| 387 | |
| 388 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); |
| 389 | POSTING_READ(FORCEWAKE_MT); |
| 390 | |
| 391 | count = 0; |
| 392 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) |
| 393 | udelay(10); |
| 394 | } |
| 395 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 396 | /* |
| 397 | * Generally this is called implicitly by the register read function. However, |
| 398 | * if some sequence requires the GT to not power down then this function should |
| 399 | * be called at the beginning of the sequence followed by a call to |
| 400 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 401 | */ |
| 402 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 403 | { |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 404 | unsigned long irqflags; |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 405 | |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 406 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
| 407 | if (dev_priv->forcewake_count++ == 0) |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 408 | dev_priv->display.force_wake_get(dev_priv); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 409 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 410 | } |
| 411 | |
Ben Widawsky | ee64cbd | 2012-02-09 10:15:19 +0100 | [diff] [blame] | 412 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 413 | { |
| 414 | u32 gtfifodbg; |
| 415 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); |
| 416 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
| 417 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
| 418 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
| 419 | } |
| 420 | |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 421 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
Chris Wilson | eb43f4a | 2010-12-08 17:32:24 +0000 | [diff] [blame] | 422 | { |
| 423 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
Ben Widawsky | ee64cbd | 2012-02-09 10:15:19 +0100 | [diff] [blame] | 424 | /* The below doubles as a POSTING_READ */ |
| 425 | gen6_gt_check_fifodbg(dev_priv); |
Chris Wilson | eb43f4a | 2010-12-08 17:32:24 +0000 | [diff] [blame] | 426 | } |
| 427 | |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 428 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
| 429 | { |
| 430 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); |
Ben Widawsky | ee64cbd | 2012-02-09 10:15:19 +0100 | [diff] [blame] | 431 | /* The below doubles as a POSTING_READ */ |
| 432 | gen6_gt_check_fifodbg(dev_priv); |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 433 | } |
| 434 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 435 | /* |
| 436 | * see gen6_gt_force_wake_get() |
| 437 | */ |
| 438 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 439 | { |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 440 | unsigned long irqflags; |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 441 | |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 442 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
| 443 | if (--dev_priv->forcewake_count == 0) |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 444 | dev_priv->display.force_wake_put(dev_priv); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 445 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 448 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
Chris Wilson | 9135583 | 2011-03-04 19:22:40 +0000 | [diff] [blame] | 449 | { |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 450 | int ret = 0; |
| 451 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 452 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
Chris Wilson | 95736720 | 2011-05-12 22:17:09 +0100 | [diff] [blame] | 453 | int loop = 500; |
| 454 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 455 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 456 | udelay(10); |
| 457 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 458 | } |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 459 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 460 | ++ret; |
Chris Wilson | 95736720 | 2011-05-12 22:17:09 +0100 | [diff] [blame] | 461 | dev_priv->gt_fifo_count = fifo; |
Chris Wilson | 9135583 | 2011-03-04 19:22:40 +0000 | [diff] [blame] | 462 | } |
Chris Wilson | 95736720 | 2011-05-12 22:17:09 +0100 | [diff] [blame] | 463 | dev_priv->gt_fifo_count--; |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 464 | |
| 465 | return ret; |
Chris Wilson | 9135583 | 2011-03-04 19:22:40 +0000 | [diff] [blame] | 466 | } |
| 467 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 468 | static int i915_drm_freeze(struct drm_device *dev) |
| 469 | { |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 470 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 471 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 472 | drm_kms_helper_poll_disable(dev); |
| 473 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 474 | pci_save_state(dev->pdev); |
| 475 | |
| 476 | /* If KMS is active, we do the leavevt stuff here */ |
| 477 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 478 | int error = i915_gem_idle(dev); |
| 479 | if (error) { |
| 480 | dev_err(&dev->pdev->dev, |
| 481 | "GEM idle failed, resume might fail\n"); |
| 482 | return error; |
| 483 | } |
| 484 | drm_irq_uninstall(dev); |
| 485 | } |
| 486 | |
| 487 | i915_save_state(dev); |
| 488 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 489 | intel_opregion_fini(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 490 | |
| 491 | /* Modeset on resume, not lid events */ |
| 492 | dev_priv->modeset_on_lid = 0; |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 493 | |
| 494 | return 0; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 495 | } |
| 496 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 497 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 498 | { |
| 499 | int error; |
| 500 | |
| 501 | if (!dev || !dev->dev_private) { |
| 502 | DRM_ERROR("dev: %p\n", dev); |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 503 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 504 | return -ENODEV; |
| 505 | } |
| 506 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 507 | if (state.event == PM_EVENT_PRETHAW) |
| 508 | return 0; |
| 509 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 510 | |
| 511 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 512 | return 0; |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 513 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 514 | error = i915_drm_freeze(dev); |
| 515 | if (error) |
| 516 | return error; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 517 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 518 | if (state.event == PM_EVENT_SUSPEND) { |
| 519 | /* Shut down the device */ |
| 520 | pci_disable_device(dev->pdev); |
| 521 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 522 | } |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 523 | |
| 524 | return 0; |
| 525 | } |
| 526 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 527 | static int i915_drm_thaw(struct drm_device *dev) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 528 | { |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 530 | int error = 0; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 531 | |
Chris Wilson | d1c3b17 | 2010-12-08 14:26:19 +0000 | [diff] [blame] | 532 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 533 | mutex_lock(&dev->struct_mutex); |
| 534 | i915_gem_restore_gtt_mappings(dev); |
| 535 | mutex_unlock(&dev->struct_mutex); |
| 536 | } |
| 537 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 538 | i915_restore_state(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 539 | intel_opregion_setup(dev); |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 540 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 541 | /* KMS EnterVT equivalent */ |
| 542 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 543 | mutex_lock(&dev->struct_mutex); |
| 544 | dev_priv->mm.suspended = 0; |
| 545 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 546 | error = i915_gem_init_hw(dev); |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 547 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 548 | |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 549 | if (HAS_PCH_SPLIT(dev)) |
| 550 | ironlake_init_pch_refclk(dev); |
| 551 | |
Chris Wilson | 500f714 | 2011-01-24 15:14:41 +0000 | [diff] [blame] | 552 | drm_mode_config_reset(dev); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 553 | drm_irq_install(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 554 | |
Zhao Yakui | 354ff96 | 2009-07-08 14:13:12 +0800 | [diff] [blame] | 555 | /* Resume the modeset for every activated CRTC */ |
| 556 | drm_helper_resume_force_mode(dev); |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 557 | |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 558 | if (IS_IRONLAKE_M(dev)) |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 559 | ironlake_enable_rc6(dev); |
| 560 | } |
Jesse Barnes | 1daed3f | 2011-01-05 12:01:25 -0800 | [diff] [blame] | 561 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 562 | intel_opregion_init(dev); |
| 563 | |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 564 | dev_priv->modeset_on_lid = 0; |
Jesse Barnes | 06891e2 | 2009-09-14 10:58:48 -0700 | [diff] [blame] | 565 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 566 | return error; |
| 567 | } |
| 568 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 569 | int i915_resume(struct drm_device *dev) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 570 | { |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 571 | int ret; |
| 572 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 573 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 574 | return 0; |
| 575 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 576 | if (pci_enable_device(dev->pdev)) |
| 577 | return -EIO; |
| 578 | |
| 579 | pci_set_master(dev->pdev); |
| 580 | |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 581 | ret = i915_drm_thaw(dev); |
| 582 | if (ret) |
| 583 | return ret; |
| 584 | |
| 585 | drm_kms_helper_poll_enable(dev); |
| 586 | return 0; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 587 | } |
| 588 | |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 589 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
| 590 | { |
| 591 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 592 | |
| 593 | if (IS_I85X(dev)) |
| 594 | return -ENODEV; |
| 595 | |
| 596 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
| 597 | POSTING_READ(D_STATE); |
| 598 | |
| 599 | if (IS_I830(dev) || IS_845G(dev)) { |
| 600 | I915_WRITE(DEBUG_RESET_I830, |
| 601 | DEBUG_RESET_DISPLAY | |
| 602 | DEBUG_RESET_RENDER | |
| 603 | DEBUG_RESET_FULL); |
| 604 | POSTING_READ(DEBUG_RESET_I830); |
| 605 | msleep(1); |
| 606 | |
| 607 | I915_WRITE(DEBUG_RESET_I830, 0); |
| 608 | POSTING_READ(DEBUG_RESET_I830); |
| 609 | } |
| 610 | |
| 611 | msleep(1); |
| 612 | |
| 613 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
| 614 | POSTING_READ(D_STATE); |
| 615 | |
| 616 | return 0; |
| 617 | } |
| 618 | |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 619 | static int i965_reset_complete(struct drm_device *dev) |
| 620 | { |
| 621 | u8 gdrst; |
Kenneth Graunke | eeccdca | 2010-09-11 01:24:50 -0700 | [diff] [blame] | 622 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 623 | return gdrst & 0x1; |
| 624 | } |
| 625 | |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 626 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
| 627 | { |
| 628 | u8 gdrst; |
| 629 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 630 | /* |
| 631 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 632 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 633 | * triggers the reset; when done, the hardware will clear it. |
| 634 | */ |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 635 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 636 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); |
| 637 | |
| 638 | return wait_for(i965_reset_complete(dev), 500); |
| 639 | } |
| 640 | |
| 641 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) |
| 642 | { |
| 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 644 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 645 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); |
| 646 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | } |
| 648 | |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 649 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
| 650 | { |
| 651 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 652 | int ret; |
| 653 | unsigned long irqflags; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 654 | |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 655 | /* Hold gt_lock across reset to prevent any register access |
| 656 | * with forcewake not set correctly |
| 657 | */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 658 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 659 | |
| 660 | /* Reset the chip */ |
| 661 | |
| 662 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 663 | * for fifo space for the write or forcewake the chip for |
| 664 | * the read |
| 665 | */ |
| 666 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); |
| 667 | |
| 668 | /* Spin waiting for the device to ack the reset request */ |
| 669 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
| 670 | |
| 671 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 672 | if (dev_priv->forcewake_count) |
| 673 | dev_priv->display.force_wake_get(dev_priv); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 674 | else |
| 675 | dev_priv->display.force_wake_put(dev_priv); |
| 676 | |
| 677 | /* Restore fifo count */ |
| 678 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 679 | |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 680 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
| 681 | return ret; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 682 | } |
| 683 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 684 | /** |
Eugeni Dodonov | f3953dc | 2011-11-28 16:15:17 -0200 | [diff] [blame] | 685 | * i915_reset - reset chip after a hang |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 686 | * @dev: drm device to reset |
| 687 | * @flags: reset domains |
| 688 | * |
| 689 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
| 690 | * reset or otherwise an error code. |
| 691 | * |
| 692 | * Procedure is fairly simple: |
| 693 | * - reset the chip using the reset reg |
| 694 | * - re-init context state |
| 695 | * - re-init hardware status page |
| 696 | * - re-init ring buffer |
| 697 | * - re-init interrupt state |
| 698 | * - re-init display |
| 699 | */ |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 700 | int i915_reset(struct drm_device *dev, u8 flags) |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 701 | { |
| 702 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 703 | /* |
| 704 | * We really should only reset the display subsystem if we actually |
| 705 | * need to |
| 706 | */ |
| 707 | bool need_display = true; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 708 | int ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 709 | |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 710 | if (!i915_try_reset) |
| 711 | return 0; |
| 712 | |
Chris Wilson | 340479a | 2010-12-04 18:17:15 +0000 | [diff] [blame] | 713 | if (!mutex_trylock(&dev->struct_mutex)) |
| 714 | return -EBUSY; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 715 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 716 | i915_gem_reset(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 717 | |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 718 | ret = -ENODEV; |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 719 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
| 720 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
| 721 | } else switch (INTEL_INFO(dev)->gen) { |
Kenneth Graunke | 1083694 | 2011-07-07 15:33:26 -0700 | [diff] [blame] | 722 | case 7: |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 723 | case 6: |
| 724 | ret = gen6_do_reset(dev, flags); |
| 725 | break; |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 726 | case 5: |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 727 | ret = ironlake_do_reset(dev, flags); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 728 | break; |
| 729 | case 4: |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 730 | ret = i965_do_reset(dev, flags); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 731 | break; |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 732 | case 2: |
| 733 | ret = i8xx_do_reset(dev, flags); |
| 734 | break; |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 735 | } |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 736 | dev_priv->last_gpu_reset = get_seconds(); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 737 | if (ret) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 738 | DRM_ERROR("Failed to reset chip.\n"); |
Daniel J Blueman | f953c93 | 2010-05-17 14:23:52 +0100 | [diff] [blame] | 739 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 740 | return ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 741 | } |
| 742 | |
| 743 | /* Ok, now get things going again... */ |
| 744 | |
| 745 | /* |
| 746 | * Everything depends on having the GTT running, so we need to start |
| 747 | * there. Fortunately we don't need to do this unless we reset the |
| 748 | * chip at a PCI level. |
| 749 | * |
| 750 | * Next we need to restore the context, but we don't use those |
| 751 | * yet either... |
| 752 | * |
| 753 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
| 754 | * was running at the time of the reset (i.e. we weren't VT |
| 755 | * switched away). |
| 756 | */ |
| 757 | if (drm_core_check_feature(dev, DRIVER_MODESET) || |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 758 | !dev_priv->mm.suspended) { |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 759 | dev_priv->mm.suspended = 0; |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 760 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 761 | i915_gem_init_swizzling(dev); |
| 762 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 763 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 764 | if (HAS_BSD(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 765 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 766 | if (HAS_BLT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 767 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 768 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 769 | i915_gem_init_ppgtt(dev); |
| 770 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 771 | mutex_unlock(&dev->struct_mutex); |
| 772 | drm_irq_uninstall(dev); |
Chris Wilson | 500f714 | 2011-01-24 15:14:41 +0000 | [diff] [blame] | 773 | drm_mode_config_reset(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 774 | drm_irq_install(dev); |
| 775 | mutex_lock(&dev->struct_mutex); |
| 776 | } |
| 777 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 778 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 9fd9814 | 2010-09-18 08:08:06 +0100 | [diff] [blame] | 779 | |
| 780 | /* |
| 781 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
| 782 | * need to retrain the display link and cannot just restore the register |
| 783 | * values. |
| 784 | */ |
| 785 | if (need_display) { |
| 786 | mutex_lock(&dev->mode_config.mutex); |
| 787 | drm_helper_resume_force_mode(dev); |
| 788 | mutex_unlock(&dev->mode_config.mutex); |
| 789 | } |
| 790 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 795 | static int __devinit |
| 796 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 797 | { |
Chris Wilson | 5fe49d8 | 2011-02-01 19:43:02 +0000 | [diff] [blame] | 798 | /* Only bind to function 0 of the device. Early generations |
| 799 | * used function 1 as a placeholder for multi-head. This causes |
| 800 | * us confusion instead, especially on the systems where both |
| 801 | * functions have the same PCI-ID! |
| 802 | */ |
| 803 | if (PCI_FUNC(pdev->devfn)) |
| 804 | return -ENODEV; |
| 805 | |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 806 | return drm_get_pci_dev(pdev, ent, &driver); |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | static void |
| 810 | i915_pci_remove(struct pci_dev *pdev) |
| 811 | { |
| 812 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 813 | |
| 814 | drm_put_dev(dev); |
| 815 | } |
| 816 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 817 | static int i915_pm_suspend(struct device *dev) |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 818 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 819 | struct pci_dev *pdev = to_pci_dev(dev); |
| 820 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 821 | int error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 822 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 823 | if (!drm_dev || !drm_dev->dev_private) { |
| 824 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 825 | return -ENODEV; |
| 826 | } |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 827 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 828 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 829 | return 0; |
| 830 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 831 | error = i915_drm_freeze(drm_dev); |
| 832 | if (error) |
| 833 | return error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 834 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 835 | pci_disable_device(pdev); |
| 836 | pci_set_power_state(pdev, PCI_D3hot); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 837 | |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 838 | return 0; |
| 839 | } |
| 840 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 841 | static int i915_pm_resume(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 842 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 843 | struct pci_dev *pdev = to_pci_dev(dev); |
| 844 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 845 | |
| 846 | return i915_resume(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 847 | } |
| 848 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 849 | static int i915_pm_freeze(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 850 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 851 | struct pci_dev *pdev = to_pci_dev(dev); |
| 852 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 853 | |
| 854 | if (!drm_dev || !drm_dev->dev_private) { |
| 855 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 856 | return -ENODEV; |
| 857 | } |
| 858 | |
| 859 | return i915_drm_freeze(drm_dev); |
| 860 | } |
| 861 | |
| 862 | static int i915_pm_thaw(struct device *dev) |
| 863 | { |
| 864 | struct pci_dev *pdev = to_pci_dev(dev); |
| 865 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 866 | |
| 867 | return i915_drm_thaw(drm_dev); |
| 868 | } |
| 869 | |
| 870 | static int i915_pm_poweroff(struct device *dev) |
| 871 | { |
| 872 | struct pci_dev *pdev = to_pci_dev(dev); |
| 873 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 874 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 875 | return i915_drm_freeze(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 876 | } |
| 877 | |
Chris Wilson | b4b78d1 | 2010-06-06 15:40:20 +0100 | [diff] [blame] | 878 | static const struct dev_pm_ops i915_pm_ops = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 879 | .suspend = i915_pm_suspend, |
| 880 | .resume = i915_pm_resume, |
| 881 | .freeze = i915_pm_freeze, |
| 882 | .thaw = i915_pm_thaw, |
| 883 | .poweroff = i915_pm_poweroff, |
| 884 | .restore = i915_pm_resume, |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 885 | }; |
| 886 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 887 | static struct vm_operations_struct i915_gem_vm_ops = { |
| 888 | .fault = i915_gem_fault, |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 889 | .open = drm_gem_vm_open, |
| 890 | .close = drm_gem_vm_close, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 891 | }; |
| 892 | |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 893 | static const struct file_operations i915_driver_fops = { |
| 894 | .owner = THIS_MODULE, |
| 895 | .open = drm_open, |
| 896 | .release = drm_release, |
| 897 | .unlocked_ioctl = drm_ioctl, |
| 898 | .mmap = drm_gem_mmap, |
| 899 | .poll = drm_poll, |
| 900 | .fasync = drm_fasync, |
| 901 | .read = drm_read, |
| 902 | #ifdef CONFIG_COMPAT |
| 903 | .compat_ioctl = i915_compat_ioctl, |
| 904 | #endif |
| 905 | .llseek = noop_llseek, |
| 906 | }; |
| 907 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 908 | static struct drm_driver driver = { |
Michael Witten | 0c54781 | 2011-08-25 17:55:54 +0000 | [diff] [blame] | 909 | /* Don't use MTRRs here; the Xserver or userspace app should |
| 910 | * deal with them for Intel hardware. |
Dave Airlie | 792d2b9 | 2005-11-11 23:30:27 +1100 | [diff] [blame] | 911 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 912 | .driver_features = |
| 913 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ |
| 914 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 915 | .load = i915_driver_load, |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 916 | .unload = i915_driver_unload, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 917 | .open = i915_driver_open, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 918 | .lastclose = i915_driver_lastclose, |
| 919 | .preclose = i915_driver_preclose, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 920 | .postclose = i915_driver_postclose, |
Rafael J. Wysocki | d8e2920 | 2010-01-09 00:45:33 +0100 | [diff] [blame] | 921 | |
| 922 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
| 923 | .suspend = i915_suspend, |
| 924 | .resume = i915_resume, |
| 925 | |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 926 | .device_is_agp = i915_driver_device_is_agp, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | .reclaim_buffers = drm_core_reclaim_buffers, |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 928 | .master_create = i915_master_create, |
| 929 | .master_destroy = i915_master_destroy, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 930 | #if defined(CONFIG_DEBUG_FS) |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 931 | .debugfs_init = i915_debugfs_init, |
| 932 | .debugfs_cleanup = i915_debugfs_cleanup, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 933 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 934 | .gem_init_object = i915_gem_init_object, |
| 935 | .gem_free_object = i915_gem_free_object, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 936 | .gem_vm_ops = &i915_gem_vm_ops, |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 937 | .dumb_create = i915_gem_dumb_create, |
| 938 | .dumb_map_offset = i915_gem_mmap_gtt, |
| 939 | .dumb_destroy = i915_gem_dumb_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 940 | .ioctls = i915_ioctls, |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 941 | .fops = &i915_driver_fops, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 942 | .name = DRIVER_NAME, |
| 943 | .desc = DRIVER_DESC, |
| 944 | .date = DRIVER_DATE, |
| 945 | .major = DRIVER_MAJOR, |
| 946 | .minor = DRIVER_MINOR, |
| 947 | .patchlevel = DRIVER_PATCHLEVEL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | }; |
| 949 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 950 | static struct pci_driver i915_pci_driver = { |
| 951 | .name = DRIVER_NAME, |
| 952 | .id_table = pciidlist, |
| 953 | .probe = i915_pci_probe, |
| 954 | .remove = i915_pci_remove, |
| 955 | .driver.pm = &i915_pm_ops, |
| 956 | }; |
| 957 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | static int __init i915_init(void) |
| 959 | { |
Zhenyu Wang | 1f7a6e3 | 2010-02-23 14:05:24 +0800 | [diff] [blame] | 960 | if (!intel_agp_enabled) { |
| 961 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
| 962 | return -ENODEV; |
| 963 | } |
| 964 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | driver.num_ioctls = i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 966 | |
| 967 | /* |
| 968 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless |
| 969 | * explicitly disabled with the module pararmeter. |
| 970 | * |
| 971 | * Otherwise, just follow the parameter (defaulting to off). |
| 972 | * |
| 973 | * Allow optional vga_text_mode_force boot option to override |
| 974 | * the default behavior. |
| 975 | */ |
| 976 | #if defined(CONFIG_DRM_I915_KMS) |
| 977 | if (i915_modeset != 0) |
| 978 | driver.driver_features |= DRIVER_MODESET; |
| 979 | #endif |
| 980 | if (i915_modeset == 1) |
| 981 | driver.driver_features |= DRIVER_MODESET; |
| 982 | |
| 983 | #ifdef CONFIG_VGA_CONSOLE |
| 984 | if (vgacon_text_force() && i915_modeset == -1) |
| 985 | driver.driver_features &= ~DRIVER_MODESET; |
| 986 | #endif |
| 987 | |
Chris Wilson | 3885c6b | 2011-01-23 10:45:14 +0000 | [diff] [blame] | 988 | if (!(driver.driver_features & DRIVER_MODESET)) |
| 989 | driver.get_vblank_timestamp = NULL; |
| 990 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 991 | return drm_pci_init(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 992 | } |
| 993 | |
| 994 | static void __exit i915_exit(void) |
| 995 | { |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 996 | drm_pci_exit(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | module_init(i915_init); |
| 1000 | module_exit(i915_exit); |
| 1001 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1002 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 1003 | MODULE_DESCRIPTION(DRIVER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | MODULE_LICENSE("GPL and additional rights"); |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1005 | |
Jesse Barnes | b7d8409 | 2012-03-22 14:38:43 -0700 | [diff] [blame] | 1006 | /* We give fast paths for the really cool registers */ |
| 1007 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| 1008 | (((dev_priv)->info->gen >= 6) && \ |
| 1009 | ((reg) < 0x40000) && \ |
| 1010 | ((reg) != FORCEWAKE)) |
| 1011 | |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1012 | #define __i915_read(x, y) \ |
| 1013 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| 1014 | u##x val = 0; \ |
| 1015 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1016 | unsigned long irqflags; \ |
| 1017 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
| 1018 | if (dev_priv->forcewake_count == 0) \ |
| 1019 | dev_priv->display.force_wake_get(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1020 | val = read##y(dev_priv->regs + reg); \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1021 | if (dev_priv->forcewake_count == 0) \ |
| 1022 | dev_priv->display.force_wake_put(dev_priv); \ |
| 1023 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1024 | } else { \ |
| 1025 | val = read##y(dev_priv->regs + reg); \ |
| 1026 | } \ |
| 1027 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| 1028 | return val; \ |
| 1029 | } |
| 1030 | |
| 1031 | __i915_read(8, b) |
| 1032 | __i915_read(16, w) |
| 1033 | __i915_read(32, l) |
| 1034 | __i915_read(64, q) |
| 1035 | #undef __i915_read |
| 1036 | |
| 1037 | #define __i915_write(x, y) \ |
| 1038 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1039 | u32 __fifo_ret = 0; \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1040 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| 1041 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1042 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1043 | } \ |
| 1044 | write##y(val, dev_priv->regs + reg); \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1045 | if (unlikely(__fifo_ret)) { \ |
| 1046 | gen6_gt_check_fifodbg(dev_priv); \ |
| 1047 | } \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1048 | } |
| 1049 | __i915_write(8, b) |
| 1050 | __i915_write(16, w) |
| 1051 | __i915_write(32, l) |
| 1052 | __i915_write(64, q) |
| 1053 | #undef __i915_write |