Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 31 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drmP.h> |
| 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_edid.h> |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "i915_drv.h" |
| 38 | #include "intel_sdvo_regs.h" |
| 39 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
Chris Wilson | a0b1c7a | 2011-09-30 22:56:41 +0100 | [diff] [blame] | 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 44 | |
| 45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 46 | SDVO_TV_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 47 | |
| 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 52 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 53 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 54 | |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 55 | static const char *tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 56 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 57 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 58 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 59 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 60 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 61 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 62 | "SECAM_60" |
| 63 | }; |
| 64 | |
| 65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 66 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 67 | struct intel_sdvo { |
| 68 | struct intel_encoder base; |
| 69 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 70 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 71 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 72 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 73 | struct i2c_adapter ddc; |
| 74 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 75 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 76 | uint32_t sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 77 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 78 | /* Active outputs controlled by this SDVO output */ |
| 79 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 80 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 81 | /* |
| 82 | * Capabilities of the SDVO device returned by |
| 83 | * i830_sdvo_get_capabilities() |
| 84 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 85 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 86 | |
| 87 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 88 | int pixel_clock_min, pixel_clock_max; |
| 89 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 90 | /* |
| 91 | * For multiple function SDVO device, |
| 92 | * this is for current attached outputs. |
| 93 | */ |
| 94 | uint16_t attached_output; |
| 95 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 96 | /* |
| 97 | * Hotplug activation bits for this device |
| 98 | */ |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 99 | uint16_t hotplug_active; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 100 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 101 | /** |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 102 | * This is used to select the color range of RBG outputs in HDMI mode. |
| 103 | * It is only valid when using TMDS encoding and 8 bit per color mode. |
| 104 | */ |
| 105 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 106 | bool color_range_auto; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 107 | |
| 108 | /** |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 109 | * This is set if we're going to treat the device as TV-out. |
| 110 | * |
| 111 | * While we have these nice friendly flags for output types that ought |
| 112 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 113 | * shows up as RGB1 (VGA). |
| 114 | */ |
| 115 | bool is_tv; |
| 116 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 117 | /* On different gens SDVOB is at different places. */ |
| 118 | bool is_sdvob; |
| 119 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 120 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 121 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 122 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 123 | /** |
| 124 | * This is set if we treat the device as HDMI, instead of DVI. |
| 125 | */ |
| 126 | bool is_hdmi; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 127 | bool has_hdmi_monitor; |
| 128 | bool has_hdmi_audio; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 129 | bool rgb_quant_range_selectable; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 130 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 131 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 132 | * This is set if we detect output of sdvo device as LVDS and |
| 133 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 134 | */ |
| 135 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 136 | |
| 137 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 138 | * This is sdvo fixed pannel mode pointer |
| 139 | */ |
| 140 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 141 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 142 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 143 | uint8_t ddc_bus; |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd |
| 147 | */ |
| 148 | uint8_t dtd_sdvo_flags; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 152 | struct intel_connector base; |
| 153 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 154 | /* Mark the type of connector */ |
| 155 | uint16_t output_flag; |
| 156 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 157 | enum hdmi_force_audio force_audio; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 158 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 159 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 160 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 161 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 162 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 163 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 164 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 165 | struct drm_property *left; |
| 166 | struct drm_property *right; |
| 167 | struct drm_property *top; |
| 168 | struct drm_property *bottom; |
| 169 | struct drm_property *hpos; |
| 170 | struct drm_property *vpos; |
| 171 | struct drm_property *contrast; |
| 172 | struct drm_property *saturation; |
| 173 | struct drm_property *hue; |
| 174 | struct drm_property *sharpness; |
| 175 | struct drm_property *flicker_filter; |
| 176 | struct drm_property *flicker_filter_adaptive; |
| 177 | struct drm_property *flicker_filter_2d; |
| 178 | struct drm_property *tv_chroma_filter; |
| 179 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 180 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 181 | |
| 182 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 183 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 184 | |
| 185 | /* Add variable to record current setting for the above property */ |
| 186 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 187 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 188 | /* this is to get the range of margin.*/ |
| 189 | u32 max_hscan, max_vscan; |
| 190 | u32 max_hpos, cur_hpos; |
| 191 | u32 max_vpos, cur_vpos; |
| 192 | u32 cur_brightness, max_brightness; |
| 193 | u32 cur_contrast, max_contrast; |
| 194 | u32 cur_saturation, max_saturation; |
| 195 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 196 | u32 cur_sharpness, max_sharpness; |
| 197 | u32 cur_flicker_filter, max_flicker_filter; |
| 198 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 199 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 200 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 201 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 202 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 203 | }; |
| 204 | |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 205 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 206 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 207 | return container_of(encoder, struct intel_sdvo, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 208 | } |
| 209 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 210 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 211 | { |
| 212 | return container_of(intel_attached_encoder(connector), |
| 213 | struct intel_sdvo, base); |
| 214 | } |
| 215 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 216 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 217 | { |
| 218 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 219 | } |
| 220 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 221 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 222 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 223 | static bool |
| 224 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 225 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 226 | int type); |
| 227 | static bool |
| 228 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 229 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 230 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 231 | /** |
| 232 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 233 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 234 | * comments in the BIOS). |
| 235 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 236 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 237 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 238 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 239 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 240 | u32 bval = val, cval = val; |
| 241 | int i; |
| 242 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 243 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 244 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 245 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 246 | return; |
| 247 | } |
| 248 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 249 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 250 | cval = I915_READ(SDVOC); |
| 251 | } else { |
| 252 | bval = I915_READ(SDVOB); |
| 253 | } |
| 254 | /* |
| 255 | * Write the registers twice for luck. Sometimes, |
| 256 | * writing them only once doesn't appear to 'stick'. |
| 257 | * The BIOS does this too. Yay, magic |
| 258 | */ |
| 259 | for (i = 0; i < 2; i++) |
| 260 | { |
| 261 | I915_WRITE(SDVOB, bval); |
| 262 | I915_READ(SDVOB); |
| 263 | I915_WRITE(SDVOC, cval); |
| 264 | I915_READ(SDVOC); |
| 265 | } |
| 266 | } |
| 267 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 268 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 269 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 270 | struct i2c_msg msgs[] = { |
| 271 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 272 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 273 | .flags = 0, |
| 274 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 275 | .buf = &addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 276 | }, |
| 277 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 278 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 279 | .flags = I2C_M_RD, |
| 280 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 281 | .buf = ch, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 282 | } |
| 283 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 284 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 285 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 286 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 287 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 288 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 289 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 290 | return false; |
| 291 | } |
| 292 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 293 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 294 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 295 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 296 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 297 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 298 | } sdvo_cmd_names[] = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 342 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 343 | /* Add the op code for SDVO enhancements */ |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 388 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 389 | /* HDMI op code */ |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 410 | }; |
| 411 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 412 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 413 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 414 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 415 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 416 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 417 | int i; |
| 418 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 419 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 420 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 421 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 422 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 423 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 424 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 425 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 426 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 427 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 428 | break; |
| 429 | } |
| 430 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 431 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 432 | DRM_LOG_KMS("(%02X)", cmd); |
| 433 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 434 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 435 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 436 | static const char *cmd_status_names[] = { |
| 437 | "Power on", |
| 438 | "Success", |
| 439 | "Not supported", |
| 440 | "Invalid arg", |
| 441 | "Pending", |
| 442 | "Target not specified", |
| 443 | "Scaling not supported" |
| 444 | }; |
| 445 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 446 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 447 | const void *args, int args_len) |
| 448 | { |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 449 | u8 *buf, status; |
| 450 | struct i2c_msg *msgs; |
| 451 | int i, ret = true; |
| 452 | |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 453 | /* Would be simpler to allocate both in one go ? */ |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 454 | buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL); |
| 455 | if (!buf) |
| 456 | return false; |
| 457 | |
| 458 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 459 | if (!msgs) { |
| 460 | kfree(buf); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 461 | return false; |
Alan Cox | 0274df3 | 2012-07-25 13:51:04 +0100 | [diff] [blame] | 462 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 463 | |
| 464 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 465 | |
| 466 | for (i = 0; i < args_len; i++) { |
| 467 | msgs[i].addr = intel_sdvo->slave_addr; |
| 468 | msgs[i].flags = 0; |
| 469 | msgs[i].len = 2; |
| 470 | msgs[i].buf = buf + 2 *i; |
| 471 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
| 472 | buf[2*i + 1] = ((u8*)args)[i]; |
| 473 | } |
| 474 | msgs[i].addr = intel_sdvo->slave_addr; |
| 475 | msgs[i].flags = 0; |
| 476 | msgs[i].len = 2; |
| 477 | msgs[i].buf = buf + 2*i; |
| 478 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
| 479 | buf[2*i + 1] = cmd; |
| 480 | |
| 481 | /* the following two are to read the response */ |
| 482 | status = SDVO_I2C_CMD_STATUS; |
| 483 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 484 | msgs[i+1].flags = 0; |
| 485 | msgs[i+1].len = 1; |
| 486 | msgs[i+1].buf = &status; |
| 487 | |
| 488 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 489 | msgs[i+2].flags = I2C_M_RD; |
| 490 | msgs[i+2].len = 1; |
| 491 | msgs[i+2].buf = &status; |
| 492 | |
| 493 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 494 | if (ret < 0) { |
| 495 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 496 | ret = false; |
| 497 | goto out; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 498 | } |
| 499 | if (ret != i+3) { |
| 500 | /* failure in I2C transfer */ |
| 501 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 502 | ret = false; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 503 | } |
| 504 | |
Ben Widawsky | 3bf3f45 | 2012-04-16 14:07:41 -0700 | [diff] [blame] | 505 | out: |
| 506 | kfree(msgs); |
| 507 | kfree(buf); |
| 508 | return ret; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 509 | } |
| 510 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 511 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 512 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 513 | { |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 514 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 515 | u8 status; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 516 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 517 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 518 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
| 519 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 520 | /* |
| 521 | * The documentation states that all commands will be |
| 522 | * processed within 15µs, and that we need only poll |
| 523 | * the status byte a maximum of 3 times in order for the |
| 524 | * command to be complete. |
| 525 | * |
| 526 | * Check 5 times in case the hardware failed to read the docs. |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 527 | * |
| 528 | * Also beware that the first response by many devices is to |
| 529 | * reply PENDING and stall for time. TVs are notorious for |
| 530 | * requiring longer than specified to complete their replies. |
| 531 | * Originally (in the DDX long ago), the delay was only ever 15ms |
| 532 | * with an additional delay of 30ms applied for TVs added later after |
| 533 | * many experiments. To accommodate both sets of delays, we do a |
| 534 | * sequence of slow checks if the device is falling behind and fails |
| 535 | * to reply within 5*15µs. |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 536 | */ |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 537 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 538 | SDVO_I2C_CMD_STATUS, |
| 539 | &status)) |
| 540 | goto log_fail; |
| 541 | |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 542 | while (status == SDVO_CMD_STATUS_PENDING && --retry) { |
| 543 | if (retry < 10) |
| 544 | msleep(15); |
| 545 | else |
| 546 | udelay(15); |
| 547 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 548 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 549 | SDVO_I2C_CMD_STATUS, |
| 550 | &status)) |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 551 | goto log_fail; |
| 552 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 553 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 554 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 555 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 556 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 557 | DRM_LOG_KMS("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 558 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 559 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 560 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 561 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 562 | /* Read the command response */ |
| 563 | for (i = 0; i < response_len; i++) { |
| 564 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 565 | SDVO_I2C_RETURN_0 + i, |
| 566 | &((u8 *)response)[i])) |
| 567 | goto log_fail; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 568 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 569 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 570 | DRM_LOG_KMS("\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 571 | return true; |
| 572 | |
| 573 | log_fail: |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 574 | DRM_LOG_KMS("... failed\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 575 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 576 | } |
| 577 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 578 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 579 | { |
| 580 | if (mode->clock >= 100000) |
| 581 | return 1; |
| 582 | else if (mode->clock >= 50000) |
| 583 | return 2; |
| 584 | else |
| 585 | return 4; |
| 586 | } |
| 587 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 588 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 589 | u8 ddc_bus) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 591 | /* This must be the immediately preceding write before the i2c xfer */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 592 | return intel_sdvo_write_cmd(intel_sdvo, |
| 593 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
| 594 | &ddc_bus, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 595 | } |
| 596 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 597 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 598 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 599 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 600 | return false; |
| 601 | |
| 602 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | static bool |
| 606 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 607 | { |
| 608 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 609 | return false; |
| 610 | |
| 611 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 612 | } |
| 613 | |
| 614 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 615 | { |
| 616 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 617 | return intel_sdvo_set_value(intel_sdvo, |
| 618 | SDVO_CMD_SET_TARGET_INPUT, |
| 619 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | /** |
| 623 | * Return whether each input is trained. |
| 624 | * |
| 625 | * This function is making an assumption about the layout of the response, |
| 626 | * which should be checked against the docs. |
| 627 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 628 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 629 | { |
| 630 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 631 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 632 | BUILD_BUG_ON(sizeof(response) != 1); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 633 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 634 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 635 | return false; |
| 636 | |
| 637 | *input_1 = response.input0_trained; |
| 638 | *input_2 = response.input1_trained; |
| 639 | return true; |
| 640 | } |
| 641 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 642 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 643 | u16 outputs) |
| 644 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 645 | return intel_sdvo_set_value(intel_sdvo, |
| 646 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 647 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 648 | } |
| 649 | |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 650 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
| 651 | u16 *outputs) |
| 652 | { |
| 653 | return intel_sdvo_get_value(intel_sdvo, |
| 654 | SDVO_CMD_GET_ACTIVE_OUTPUTS, |
| 655 | outputs, sizeof(*outputs)); |
| 656 | } |
| 657 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 658 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | int mode) |
| 660 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 661 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 662 | |
| 663 | switch (mode) { |
| 664 | case DRM_MODE_DPMS_ON: |
| 665 | state = SDVO_ENCODER_STATE_ON; |
| 666 | break; |
| 667 | case DRM_MODE_DPMS_STANDBY: |
| 668 | state = SDVO_ENCODER_STATE_STANDBY; |
| 669 | break; |
| 670 | case DRM_MODE_DPMS_SUSPEND: |
| 671 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 672 | break; |
| 673 | case DRM_MODE_DPMS_OFF: |
| 674 | state = SDVO_ENCODER_STATE_OFF; |
| 675 | break; |
| 676 | } |
| 677 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 678 | return intel_sdvo_set_value(intel_sdvo, |
| 679 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 680 | } |
| 681 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 682 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 683 | int *clock_min, |
| 684 | int *clock_max) |
| 685 | { |
| 686 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 687 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 688 | BUILD_BUG_ON(sizeof(clocks) != 4); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 689 | if (!intel_sdvo_get_value(intel_sdvo, |
| 690 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 691 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 692 | return false; |
| 693 | |
| 694 | /* Convert the values from units of 10 kHz to kHz. */ |
| 695 | *clock_min = clocks.min * 10; |
| 696 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 697 | return true; |
| 698 | } |
| 699 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 700 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 701 | u16 outputs) |
| 702 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 703 | return intel_sdvo_set_value(intel_sdvo, |
| 704 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 705 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 706 | } |
| 707 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 708 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 709 | struct intel_sdvo_dtd *dtd) |
| 710 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 711 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 712 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | } |
| 714 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 715 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 716 | struct intel_sdvo_dtd *dtd) |
| 717 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 718 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 719 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 720 | } |
| 721 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 722 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 723 | struct intel_sdvo_dtd *dtd) |
| 724 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 725 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 726 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 727 | } |
| 728 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 729 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 730 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 731 | uint16_t clock, |
| 732 | uint16_t width, |
| 733 | uint16_t height) |
| 734 | { |
| 735 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 736 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 737 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 738 | args.clock = clock; |
| 739 | args.width = width; |
| 740 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 741 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 742 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 743 | if (intel_sdvo->is_lvds && |
| 744 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 745 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 746 | args.scaled = 1; |
| 747 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 748 | return intel_sdvo_set_value(intel_sdvo, |
| 749 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 750 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 751 | } |
| 752 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 753 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 754 | struct intel_sdvo_dtd *dtd) |
| 755 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 756 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
| 757 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 758 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 759 | &dtd->part1, sizeof(dtd->part1)) && |
| 760 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 761 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 762 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 763 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 764 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 765 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 766 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 767 | } |
| 768 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 769 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 770 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 771 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 772 | uint16_t width, height; |
| 773 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 774 | uint16_t h_sync_offset, v_sync_offset; |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 775 | int mode_clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 776 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 777 | width = mode->hdisplay; |
| 778 | height = mode->vdisplay; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 779 | |
| 780 | /* do some mode translations */ |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 781 | h_blank_len = mode->htotal - mode->hdisplay; |
| 782 | h_sync_len = mode->hsync_end - mode->hsync_start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 783 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 784 | v_blank_len = mode->vtotal - mode->vdisplay; |
| 785 | v_sync_len = mode->vsync_end - mode->vsync_start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 786 | |
Daniel Vetter | c6ebd4c | 2012-04-24 18:27:57 +0200 | [diff] [blame] | 787 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
| 788 | v_sync_offset = mode->vsync_start - mode->vdisplay; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 789 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 790 | mode_clock = mode->clock; |
| 791 | mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1; |
| 792 | mode_clock /= 10; |
| 793 | dtd->part1.clock = mode_clock; |
| 794 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 795 | dtd->part1.h_active = width & 0xff; |
| 796 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 797 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 798 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 799 | dtd->part1.v_active = height & 0xff; |
| 800 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 801 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 802 | ((v_blank_len >> 8) & 0xf); |
| 803 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 804 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 805 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 806 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 807 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 808 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 809 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 810 | ((v_sync_len & 0x30) >> 4); |
| 811 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 812 | dtd->part2.dtd_flags = 0x18; |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 813 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 814 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 815 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 816 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 817 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 818 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 819 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 820 | dtd->part2.sdvo_flags = 0; |
| 821 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 822 | dtd->part2.reserved = 0; |
| 823 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 824 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 825 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 826 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 827 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 828 | mode->hdisplay = dtd->part1.h_active; |
| 829 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 830 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 831 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 832 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 833 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 834 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 835 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 836 | |
| 837 | mode->vdisplay = dtd->part1.v_active; |
| 838 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 839 | mode->vsync_start = mode->vdisplay; |
| 840 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 841 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 842 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 843 | mode->vsync_end = mode->vsync_start + |
| 844 | (dtd->part2.v_sync_off_width & 0xf); |
| 845 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 846 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 847 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 848 | |
| 849 | mode->clock = dtd->part1.clock * 10; |
| 850 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 851 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 852 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
| 853 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 854 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 855 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
Daniel Vetter | 59d92bf | 2012-05-12 22:22:58 +0200 | [diff] [blame] | 856 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 857 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 858 | } |
| 859 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 860 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 861 | { |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 862 | struct intel_sdvo_encode encode; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 863 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 864 | BUILD_BUG_ON(sizeof(encode) != 2); |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 865 | return intel_sdvo_get_value(intel_sdvo, |
| 866 | SDVO_CMD_GET_SUPP_ENCODE, |
| 867 | &encode, sizeof(encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 868 | } |
| 869 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 870 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 871 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 872 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 873 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 874 | } |
| 875 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 876 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 877 | uint8_t mode) |
| 878 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 879 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 883 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 884 | { |
| 885 | int i, j; |
| 886 | uint8_t set_buf_index[2]; |
| 887 | uint8_t av_split; |
| 888 | uint8_t buf_size; |
| 889 | uint8_t buf[48]; |
| 890 | uint8_t *pos; |
| 891 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 892 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 893 | |
| 894 | for (i = 0; i <= av_split; i++) { |
| 895 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 896 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 897 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 898 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 899 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 900 | |
| 901 | pos = buf; |
| 902 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 903 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 904 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 905 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 906 | pos += 8; |
| 907 | } |
| 908 | } |
| 909 | } |
| 910 | #endif |
| 911 | |
Daniel Vetter | b6e0e54 | 2012-10-21 12:52:39 +0200 | [diff] [blame] | 912 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
| 913 | unsigned if_index, uint8_t tx_rate, |
| 914 | uint8_t *data, unsigned length) |
| 915 | { |
| 916 | uint8_t set_buf_index[2] = { if_index, 0 }; |
| 917 | uint8_t hbuf_size, tmp[8]; |
| 918 | int i; |
| 919 | |
| 920 | if (!intel_sdvo_set_value(intel_sdvo, |
| 921 | SDVO_CMD_SET_HBUF_INDEX, |
| 922 | set_buf_index, 2)) |
| 923 | return false; |
| 924 | |
| 925 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, |
| 926 | &hbuf_size, 1)) |
| 927 | return false; |
| 928 | |
| 929 | /* Buffer size is 0 based, hooray! */ |
| 930 | hbuf_size++; |
| 931 | |
| 932 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", |
| 933 | if_index, length, hbuf_size); |
| 934 | |
| 935 | for (i = 0; i < hbuf_size; i += 8) { |
| 936 | memset(tmp, 0, 8); |
| 937 | if (i < length) |
| 938 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); |
| 939 | |
| 940 | if (!intel_sdvo_set_value(intel_sdvo, |
| 941 | SDVO_CMD_SET_HBUF_DATA, |
| 942 | tmp, 8)) |
| 943 | return false; |
| 944 | } |
| 945 | |
| 946 | return intel_sdvo_set_value(intel_sdvo, |
| 947 | SDVO_CMD_SET_HBUF_TXRATE, |
| 948 | &tx_rate, 1); |
| 949 | } |
| 950 | |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 951 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
| 952 | const struct drm_display_mode *adjusted_mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 953 | { |
| 954 | struct dip_infoframe avi_if = { |
| 955 | .type = DIP_TYPE_AVI, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 956 | .ver = DIP_VERSION_AVI, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 957 | .len = DIP_LEN_AVI, |
| 958 | }; |
Daniel Vetter | 81014b9 | 2012-05-12 20:22:00 +0200 | [diff] [blame] | 959 | uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 960 | |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 961 | if (intel_sdvo->rgb_quant_range_selectable) { |
| 962 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) |
| 963 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
| 964 | else |
| 965 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; |
| 966 | } |
| 967 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 968 | intel_dip_infoframe_csum(&avi_if); |
| 969 | |
Daniel Vetter | 81014b9 | 2012-05-12 20:22:00 +0200 | [diff] [blame] | 970 | /* sdvo spec says that the ecc is handled by the hw, and it looks like |
| 971 | * we must not send the ecc field, either. */ |
| 972 | memcpy(sdvo_data, &avi_if, 3); |
| 973 | sdvo_data[3] = avi_if.checksum; |
| 974 | memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); |
| 975 | |
Daniel Vetter | b6e0e54 | 2012-10-21 12:52:39 +0200 | [diff] [blame] | 976 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
| 977 | SDVO_HBUF_TX_VSYNC, |
| 978 | sdvo_data, sizeof(sdvo_data)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 979 | } |
| 980 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 981 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 982 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 983 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 984 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 985 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 986 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 987 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 988 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 989 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 990 | BUILD_BUG_ON(sizeof(format) != 6); |
| 991 | return intel_sdvo_set_value(intel_sdvo, |
| 992 | SDVO_CMD_SET_TV_FORMAT, |
| 993 | &format, sizeof(format)); |
| 994 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 995 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 996 | static bool |
| 997 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 998 | const struct drm_display_mode *mode) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 999 | { |
| 1000 | struct intel_sdvo_dtd output_dtd; |
| 1001 | |
| 1002 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1003 | intel_sdvo->attached_output)) |
| 1004 | return false; |
| 1005 | |
| 1006 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 1007 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1008 | return false; |
| 1009 | |
| 1010 | return true; |
| 1011 | } |
| 1012 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1013 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
| 1014 | * Unfortunately we have to set up the full output mode to do that. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1015 | static bool |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1016 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1017 | const struct drm_display_mode *mode, |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1018 | struct drm_display_mode *adjusted_mode) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1019 | { |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1020 | struct intel_sdvo_dtd input_dtd; |
| 1021 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1022 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 1023 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1024 | return false; |
| 1025 | |
| 1026 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 1027 | mode->clock / 10, |
| 1028 | mode->hdisplay, |
| 1029 | mode->vdisplay)) |
| 1030 | return false; |
| 1031 | |
| 1032 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1033 | &input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1034 | return false; |
| 1035 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1036 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 1037 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1038 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1039 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1040 | } |
| 1041 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1042 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1043 | const struct drm_display_mode *mode, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1044 | struct drm_display_mode *adjusted_mode) |
| 1045 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1046 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1047 | int multiplier; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1048 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1049 | /* We need to construct preferred input timings based on our |
| 1050 | * output timings. To do that, we have to set the output |
| 1051 | * timings, even though this isn't really the right place in |
| 1052 | * the sequence to do it. Oh well. |
| 1053 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1054 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1055 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1056 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1057 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1058 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1059 | mode, |
| 1060 | adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1061 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1062 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1063 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1064 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1065 | |
Daniel Vetter | c9a2969 | 2012-04-10 13:55:47 +0200 | [diff] [blame] | 1066 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1067 | mode, |
| 1068 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1069 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1070 | |
| 1071 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1072 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1073 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1074 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 1075 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1076 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1077 | if (intel_sdvo->color_range_auto) { |
| 1078 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
| 1079 | if (intel_sdvo->has_hdmi_monitor && |
| 1080 | drm_mode_cea_vic(adjusted_mode) > 1) |
| 1081 | intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235; |
| 1082 | else |
| 1083 | intel_sdvo->color_range = 0; |
| 1084 | } |
| 1085 | |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1086 | if (intel_sdvo->color_range) |
| 1087 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; |
| 1088 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1089 | return true; |
| 1090 | } |
| 1091 | |
| 1092 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 1093 | struct drm_display_mode *mode, |
| 1094 | struct drm_display_mode *adjusted_mode) |
| 1095 | { |
| 1096 | struct drm_device *dev = encoder->dev; |
| 1097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1098 | struct drm_crtc *crtc = encoder->crtc; |
| 1099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1100 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1101 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1102 | struct intel_sdvo_in_out_map in_out; |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1103 | struct intel_sdvo_dtd input_dtd, output_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1104 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 1105 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1106 | |
| 1107 | if (!mode) |
| 1108 | return; |
| 1109 | |
| 1110 | /* First, set the input mapping for the first input to our controlled |
| 1111 | * output. This is only correct if we're a single-input device, in |
| 1112 | * which case the first input is the output from the appropriate SDVO |
| 1113 | * channel on the motherboard. In a two-input device, the first input |
| 1114 | * will be SDVOB and the second SDVOC. |
| 1115 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1116 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1117 | in_out.in1 = 0; |
| 1118 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1119 | intel_sdvo_set_value(intel_sdvo, |
| 1120 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1121 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1122 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1123 | /* Set the output timings to the screen */ |
| 1124 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1125 | intel_sdvo->attached_output)) |
| 1126 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1127 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1128 | /* lvds has a special fixed output timing. */ |
| 1129 | if (intel_sdvo->is_lvds) |
| 1130 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
| 1131 | intel_sdvo->sdvo_lvds_fixed_mode); |
| 1132 | else |
| 1133 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
Daniel Vetter | c8d4bb5 | 2012-04-10 13:55:48 +0200 | [diff] [blame] | 1134 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1135 | DRM_INFO("Setting output timings on %s failed\n", |
| 1136 | SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1137 | |
| 1138 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1139 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1140 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1141 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1142 | if (intel_sdvo->has_hdmi_monitor) { |
| 1143 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 1144 | intel_sdvo_set_colorimetry(intel_sdvo, |
| 1145 | SDVO_COLORIMETRY_RGB256); |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1146 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1147 | } else |
| 1148 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1149 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1150 | if (intel_sdvo->is_tv && |
| 1151 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1152 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1153 | |
Daniel Vetter | 6651819 | 2012-04-01 19:16:18 +0200 | [diff] [blame] | 1154 | /* We have tried to get input timing in mode_fixup, and filled into |
| 1155 | * adjusted_mode. |
| 1156 | */ |
| 1157 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Egbert Eich | e751823 | 2012-10-13 14:29:31 +0200 | [diff] [blame] | 1158 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
| 1159 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; |
Daniel Vetter | c8d4bb5 | 2012-04-10 13:55:48 +0200 | [diff] [blame] | 1160 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
| 1161 | DRM_INFO("Setting input timings on %s failed\n", |
| 1162 | SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1163 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1164 | switch (pixel_multiplier) { |
| 1165 | default: |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1166 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1167 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1168 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1169 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1170 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1171 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1172 | |
| 1173 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1174 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | ba68e08 | 2012-01-06 19:45:34 -0200 | [diff] [blame] | 1175 | /* The real mode polarity is set by the SDVO commands, using |
| 1176 | * struct intel_sdvo_dtd. */ |
| 1177 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1178 | if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1179 | sdvox |= intel_sdvo->color_range; |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1180 | if (INTEL_INFO(dev)->gen < 5) |
| 1181 | sdvox |= SDVO_BORDER_ENABLE; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1182 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1183 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1184 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1185 | case SDVOB: |
| 1186 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1187 | break; |
| 1188 | case SDVOC: |
| 1189 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1190 | break; |
| 1191 | } |
| 1192 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1193 | } |
Paulo Zanoni | 3573c41 | 2011-10-14 18:16:22 -0300 | [diff] [blame] | 1194 | |
| 1195 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) |
| 1196 | sdvox |= TRANSCODER_CPT(intel_crtc->pipe); |
| 1197 | else |
| 1198 | sdvox |= TRANSCODER(intel_crtc->pipe); |
| 1199 | |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1200 | if (intel_sdvo->has_hdmi_audio) |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1201 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1202 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1203 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1204 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1205 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1206 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1207 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1208 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1209 | } |
| 1210 | |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1211 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
| 1212 | INTEL_INFO(dev)->gen < 5) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1213 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1214 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1215 | } |
| 1216 | |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1217 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1218 | { |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1219 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1220 | to_intel_sdvo_connector(&connector->base); |
| 1221 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); |
| 1222 | u16 active_outputs; |
| 1223 | |
| 1224 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
| 1225 | |
| 1226 | if (active_outputs & intel_sdvo_connector->output_flag) |
| 1227 | return true; |
| 1228 | else |
| 1229 | return false; |
| 1230 | } |
| 1231 | |
| 1232 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, |
| 1233 | enum pipe *pipe) |
| 1234 | { |
| 1235 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1236 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 1237 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
| 1238 | u32 tmp; |
| 1239 | |
| 1240 | tmp = I915_READ(intel_sdvo->sdvo_reg); |
| 1241 | |
| 1242 | if (!(tmp & SDVO_ENABLE)) |
| 1243 | return false; |
| 1244 | |
| 1245 | if (HAS_PCH_CPT(dev)) |
| 1246 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 1247 | else |
| 1248 | *pipe = PORT_TO_PIPE(tmp); |
| 1249 | |
| 1250 | return true; |
| 1251 | } |
| 1252 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1253 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
| 1254 | { |
| 1255 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 1256 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1257 | u32 temp; |
| 1258 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1259 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
| 1260 | if (0) |
| 1261 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1262 | DRM_MODE_DPMS_OFF); |
| 1263 | |
| 1264 | temp = I915_READ(intel_sdvo->sdvo_reg); |
| 1265 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1266 | /* HW workaround for IBX, we need to move the port to |
| 1267 | * transcoder A before disabling it. */ |
| 1268 | if (HAS_PCH_IBX(encoder->base.dev)) { |
| 1269 | struct drm_crtc *crtc = encoder->base.crtc; |
| 1270 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
| 1271 | |
| 1272 | if (temp & SDVO_PIPE_B_SELECT) { |
| 1273 | temp &= ~SDVO_PIPE_B_SELECT; |
| 1274 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
| 1275 | POSTING_READ(intel_sdvo->sdvo_reg); |
| 1276 | |
| 1277 | /* Again we need to write this twice. */ |
| 1278 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
| 1279 | POSTING_READ(intel_sdvo->sdvo_reg); |
| 1280 | |
| 1281 | /* Transcoder selection bits only update |
| 1282 | * effectively on vblank. */ |
| 1283 | if (crtc) |
| 1284 | intel_wait_for_vblank(encoder->base.dev, pipe); |
| 1285 | else |
| 1286 | msleep(50); |
| 1287 | } |
| 1288 | } |
| 1289 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1290 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
| 1291 | } |
| 1292 | } |
| 1293 | |
| 1294 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
| 1295 | { |
| 1296 | struct drm_device *dev = encoder->base.dev; |
| 1297 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1298 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
| 1299 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 1300 | u32 temp; |
| 1301 | bool input1, input2; |
| 1302 | int i; |
| 1303 | u8 status; |
| 1304 | |
| 1305 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1306 | if ((temp & SDVO_ENABLE) == 0) { |
| 1307 | /* HW workaround for IBX, we need to move the port |
| 1308 | * to transcoder A before disabling it. */ |
| 1309 | if (HAS_PCH_IBX(dev)) { |
| 1310 | struct drm_crtc *crtc = encoder->base.crtc; |
| 1311 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
| 1312 | |
| 1313 | /* Restore the transcoder select bit. */ |
| 1314 | if (pipe == PIPE_B) |
| 1315 | temp |= SDVO_PIPE_B_SELECT; |
| 1316 | } |
| 1317 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1318 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Chris Wilson | 776ca7c | 2012-11-21 10:44:23 +0000 | [diff] [blame] | 1319 | } |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 1320 | for (i = 0; i < 2; i++) |
| 1321 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 1322 | |
| 1323 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
| 1324 | /* Warn if the device reported failure to sync. |
| 1325 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1326 | * a given it the status is a success, we succeeded. |
| 1327 | */ |
| 1328 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
| 1329 | DRM_DEBUG_KMS("First %s output reported failure to " |
| 1330 | "sync\n", SDVO_NAME(intel_sdvo)); |
| 1331 | } |
| 1332 | |
| 1333 | if (0) |
| 1334 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1335 | DRM_MODE_DPMS_ON); |
| 1336 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
| 1337 | } |
| 1338 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 1339 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1340 | { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 1341 | struct drm_crtc *crtc; |
| 1342 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1343 | |
| 1344 | /* dvo supports only 2 dpms states. */ |
| 1345 | if (mode != DRM_MODE_DPMS_ON) |
| 1346 | mode = DRM_MODE_DPMS_OFF; |
| 1347 | |
| 1348 | if (mode == connector->dpms) |
| 1349 | return; |
| 1350 | |
| 1351 | connector->dpms = mode; |
| 1352 | |
| 1353 | /* Only need to change hw state when actually enabled */ |
| 1354 | crtc = intel_sdvo->base.base.crtc; |
| 1355 | if (!crtc) { |
| 1356 | intel_sdvo->base.connectors_active = false; |
| 1357 | return; |
| 1358 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1359 | |
| 1360 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1361 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1362 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1363 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1364 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 1365 | intel_sdvo->base.connectors_active = false; |
| 1366 | |
| 1367 | intel_crtc_update_dpms(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1368 | } else { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 1369 | intel_sdvo->base.connectors_active = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1370 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 1371 | intel_crtc_update_dpms(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1372 | |
| 1373 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1374 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1375 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1376 | } |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 1377 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 1378 | intel_modeset_check_state(connector->dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1379 | } |
| 1380 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1381 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1382 | struct drm_display_mode *mode) |
| 1383 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1384 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1385 | |
| 1386 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1387 | return MODE_NO_DBLESCAN; |
| 1388 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1389 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1390 | return MODE_CLOCK_LOW; |
| 1391 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1392 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1393 | return MODE_CLOCK_HIGH; |
| 1394 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1395 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1396 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1397 | return MODE_PANEL; |
| 1398 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1399 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1400 | return MODE_PANEL; |
| 1401 | } |
| 1402 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1403 | return MODE_OK; |
| 1404 | } |
| 1405 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1406 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1407 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 1408 | BUILD_BUG_ON(sizeof(*caps) != 8); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1409 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1410 | SDVO_CMD_GET_DEVICE_CAPS, |
| 1411 | caps, sizeof(*caps))) |
| 1412 | return false; |
| 1413 | |
| 1414 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
| 1415 | " vendor_id: %d\n" |
| 1416 | " device_id: %d\n" |
| 1417 | " device_rev_id: %d\n" |
| 1418 | " sdvo_version_major: %d\n" |
| 1419 | " sdvo_version_minor: %d\n" |
| 1420 | " sdvo_inputs_mask: %d\n" |
| 1421 | " smooth_scaling: %d\n" |
| 1422 | " sharp_scaling: %d\n" |
| 1423 | " up_scaling: %d\n" |
| 1424 | " down_scaling: %d\n" |
| 1425 | " stall_support: %d\n" |
| 1426 | " output_flags: %d\n", |
| 1427 | caps->vendor_id, |
| 1428 | caps->device_id, |
| 1429 | caps->device_rev_id, |
| 1430 | caps->sdvo_version_major, |
| 1431 | caps->sdvo_version_minor, |
| 1432 | caps->sdvo_inputs_mask, |
| 1433 | caps->smooth_scaling, |
| 1434 | caps->sharp_scaling, |
| 1435 | caps->up_scaling, |
| 1436 | caps->down_scaling, |
| 1437 | caps->stall_support, |
| 1438 | caps->output_flags); |
| 1439 | |
| 1440 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1441 | } |
| 1442 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1443 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1444 | { |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1445 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1446 | uint16_t hotplug; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1447 | |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1448 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
| 1449 | * on the line. */ |
| 1450 | if (IS_I945G(dev) || IS_I945GM(dev)) |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1451 | return 0; |
Daniel Vetter | 768b107 | 2012-05-04 11:29:56 +0200 | [diff] [blame] | 1452 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1453 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1454 | &hotplug, sizeof(hotplug))) |
| 1455 | return 0; |
| 1456 | |
| 1457 | return hotplug; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1458 | } |
| 1459 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1460 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1461 | { |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1462 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1463 | |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 1464 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
| 1465 | &intel_sdvo->hotplug_active, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1466 | } |
| 1467 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1468 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1469 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1470 | { |
Chris Wilson | bc65212 | 2011-01-25 13:28:29 +0000 | [diff] [blame] | 1471 | /* Is there more than one type of output? */ |
Adam Jackson | 2294488 | 2011-06-16 16:36:24 -0400 | [diff] [blame] | 1472 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1473 | } |
| 1474 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1475 | static struct edid * |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1476 | intel_sdvo_get_edid(struct drm_connector *connector) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1477 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1478 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
| 1479 | return drm_get_edid(connector, &sdvo->ddc); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1480 | } |
| 1481 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1482 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1483 | static struct edid * |
| 1484 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1485 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1486 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1487 | |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1488 | return drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 1489 | intel_gmbus_get_adapter(dev_priv, |
| 1490 | dev_priv->crt_ddc_pin)); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1491 | } |
| 1492 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1493 | static enum drm_connector_status |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1494 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1495 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1496 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1497 | enum drm_connector_status status; |
| 1498 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1499 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1500 | edid = intel_sdvo_get_edid(connector); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1501 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1502 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1503 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1504 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1505 | /* |
| 1506 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1507 | * the EDID. It is used for SDVO SPD ROM. |
| 1508 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1509 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1510 | intel_sdvo->ddc_bus = ddc; |
| 1511 | edid = intel_sdvo_get_edid(connector); |
| 1512 | if (edid) |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1513 | break; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1514 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1515 | /* |
| 1516 | * If we found the EDID on the other bus, |
| 1517 | * assume that is the correct DDC bus. |
| 1518 | */ |
| 1519 | if (edid == NULL) |
| 1520 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1521 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1522 | |
| 1523 | /* |
| 1524 | * When there is no edid and no monitor is connected with VGA |
| 1525 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1526 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1527 | if (edid == NULL) |
| 1528 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1529 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1530 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1531 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1532 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1533 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1534 | status = connector_status_connected; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1535 | if (intel_sdvo->is_hdmi) { |
| 1536 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
| 1537 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1538 | intel_sdvo->rgb_quant_range_selectable = |
| 1539 | drm_rgb_quant_range_selectable(edid); |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1540 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1541 | } else |
| 1542 | status = connector_status_disconnected; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1543 | kfree(edid); |
| 1544 | } |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1545 | |
| 1546 | if (status == connector_status_connected) { |
| 1547 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 1548 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
| 1549 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1550 | } |
| 1551 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1552 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1553 | } |
| 1554 | |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1555 | static bool |
| 1556 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
| 1557 | struct edid *edid) |
| 1558 | { |
| 1559 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
| 1560 | bool connector_is_digital = !!IS_DIGITAL(sdvo); |
| 1561 | |
| 1562 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", |
| 1563 | connector_is_digital, monitor_is_digital); |
| 1564 | return connector_is_digital == monitor_is_digital; |
| 1565 | } |
| 1566 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1567 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1568 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1569 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1570 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1571 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1572 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1573 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1574 | |
Chris Wilson | fc37381 | 2012-11-23 11:57:56 +0000 | [diff] [blame] | 1575 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1576 | SDVO_CMD_GET_ATTACHED_DISPLAYS, |
| 1577 | &response, 2)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1578 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1579 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1580 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
| 1581 | response & 0xff, response >> 8, |
| 1582 | intel_sdvo_connector->output_flag); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1583 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1584 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1585 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1586 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1587 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1588 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1589 | intel_sdvo->has_hdmi_monitor = false; |
| 1590 | intel_sdvo->has_hdmi_audio = false; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 1591 | intel_sdvo->rgb_quant_range_selectable = false; |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1592 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1593 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1594 | ret = connector_status_disconnected; |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1595 | else if (IS_TMDS(intel_sdvo_connector)) |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1596 | ret = intel_sdvo_tmds_sink_detect(connector); |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1597 | else { |
| 1598 | struct edid *edid; |
| 1599 | |
| 1600 | /* if we have an edid check it matches the connection */ |
| 1601 | edid = intel_sdvo_get_edid(connector); |
| 1602 | if (edid == NULL) |
| 1603 | edid = intel_sdvo_get_analog_edid(connector); |
| 1604 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1605 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
| 1606 | edid)) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1607 | ret = connector_status_connected; |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1608 | else |
| 1609 | ret = connector_status_disconnected; |
| 1610 | |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1611 | kfree(edid); |
| 1612 | } else |
| 1613 | ret = connector_status_connected; |
| 1614 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1615 | |
| 1616 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1617 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1618 | intel_sdvo->is_tv = false; |
| 1619 | intel_sdvo->is_lvds = false; |
| 1620 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1621 | |
| 1622 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1623 | intel_sdvo->is_tv = true; |
| 1624 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1625 | } |
| 1626 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1627 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1628 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1629 | |
| 1630 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1631 | } |
| 1632 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1633 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1634 | { |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1635 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1636 | |
| 1637 | /* set the bus switch and get the modes */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1638 | edid = intel_sdvo_get_edid(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1639 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1640 | /* |
| 1641 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1642 | * link between analog and digital outputs. So, if the regular SDVO |
| 1643 | * DDC fails, check to see if the analog output is disconnected, in |
| 1644 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1645 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1646 | if (edid == NULL) |
| 1647 | edid = intel_sdvo_get_analog_edid(connector); |
| 1648 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1649 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame] | 1650 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
| 1651 | edid)) { |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1652 | drm_mode_connector_update_edid_property(connector, edid); |
| 1653 | drm_add_edid_modes(connector, edid); |
| 1654 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1655 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1656 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1657 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1658 | } |
| 1659 | |
| 1660 | /* |
| 1661 | * Set of SDVO TV modes. |
| 1662 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1663 | * XXX: all 60Hz refresh? |
| 1664 | */ |
Chris Wilson | b1f559e | 2011-01-26 09:49:47 +0000 | [diff] [blame] | 1665 | static const struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1666 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1667 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1668 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1669 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1670 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1671 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1672 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1673 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1674 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1675 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1676 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1677 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1678 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1679 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1680 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1681 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1682 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1683 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1684 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1685 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1686 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1687 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1688 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1689 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1690 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1691 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1692 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1693 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1694 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1695 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1696 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1697 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1698 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1699 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1700 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1701 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1702 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1703 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1704 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1705 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1706 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1707 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1708 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1709 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1710 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1711 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1712 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1713 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1714 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1715 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1716 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1717 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1718 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1719 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1720 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1721 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1722 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1723 | }; |
| 1724 | |
| 1725 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1726 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1727 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1728 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1729 | uint32_t reply = 0, format_map = 0; |
| 1730 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1731 | |
| 1732 | /* Read the list of supported input resolutions for the selected TV |
| 1733 | * format. |
| 1734 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1735 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1736 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1737 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1738 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1739 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1740 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1741 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1742 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1743 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1744 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1745 | &tv_res, sizeof(tv_res))) |
| 1746 | return; |
| 1747 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1748 | return; |
| 1749 | |
| 1750 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1751 | if (reply & (1 << i)) { |
| 1752 | struct drm_display_mode *nmode; |
| 1753 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1754 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1755 | if (nmode) |
| 1756 | drm_mode_probed_add(connector, nmode); |
| 1757 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1758 | } |
| 1759 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1760 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1761 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1762 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1763 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1764 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1765 | |
| 1766 | /* |
| 1767 | * Attempt to get the mode list from DDC. |
| 1768 | * Assume that the preferred modes are |
| 1769 | * arranged in priority order. |
| 1770 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1771 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1772 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1773 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1774 | |
| 1775 | /* Fetch modes from VBT */ |
| 1776 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1777 | newmode = drm_mode_duplicate(connector->dev, |
| 1778 | dev_priv->sdvo_lvds_vbt_mode); |
| 1779 | if (newmode != NULL) { |
| 1780 | /* Guarantee the mode is preferred */ |
| 1781 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1782 | DRM_MODE_TYPE_DRIVER); |
| 1783 | drm_mode_probed_add(connector, newmode); |
| 1784 | } |
| 1785 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1786 | |
| 1787 | end: |
| 1788 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1789 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1790 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1791 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1792 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1793 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1794 | break; |
| 1795 | } |
| 1796 | } |
| 1797 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1798 | } |
| 1799 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1800 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1801 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1802 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1803 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1804 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1805 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1806 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1807 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1808 | else |
| 1809 | intel_sdvo_get_ddc_modes(connector); |
| 1810 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1811 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1812 | } |
| 1813 | |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 1814 | static void |
| 1815 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1816 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1817 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1818 | struct drm_device *dev = connector->dev; |
| 1819 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1820 | if (intel_sdvo_connector->left) |
| 1821 | drm_property_destroy(dev, intel_sdvo_connector->left); |
| 1822 | if (intel_sdvo_connector->right) |
| 1823 | drm_property_destroy(dev, intel_sdvo_connector->right); |
| 1824 | if (intel_sdvo_connector->top) |
| 1825 | drm_property_destroy(dev, intel_sdvo_connector->top); |
| 1826 | if (intel_sdvo_connector->bottom) |
| 1827 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
| 1828 | if (intel_sdvo_connector->hpos) |
| 1829 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
| 1830 | if (intel_sdvo_connector->vpos) |
| 1831 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
| 1832 | if (intel_sdvo_connector->saturation) |
| 1833 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
| 1834 | if (intel_sdvo_connector->contrast) |
| 1835 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
| 1836 | if (intel_sdvo_connector->hue) |
| 1837 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
| 1838 | if (intel_sdvo_connector->sharpness) |
| 1839 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
| 1840 | if (intel_sdvo_connector->flicker_filter) |
| 1841 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
| 1842 | if (intel_sdvo_connector->flicker_filter_2d) |
| 1843 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
| 1844 | if (intel_sdvo_connector->flicker_filter_adaptive) |
| 1845 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
| 1846 | if (intel_sdvo_connector->tv_luma_filter) |
| 1847 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
| 1848 | if (intel_sdvo_connector->tv_chroma_filter) |
| 1849 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1850 | if (intel_sdvo_connector->dot_crawl) |
| 1851 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1852 | if (intel_sdvo_connector->brightness) |
| 1853 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1854 | } |
| 1855 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1856 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1857 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1858 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1859 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1860 | if (intel_sdvo_connector->tv_format) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1861 | drm_property_destroy(connector->dev, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1862 | intel_sdvo_connector->tv_format); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1863 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1864 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1865 | drm_sysfs_connector_remove(connector); |
| 1866 | drm_connector_cleanup(connector); |
Jani Nikula | 4b745b1 | 2012-11-12 18:31:36 +0200 | [diff] [blame] | 1867 | kfree(intel_sdvo_connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1868 | } |
| 1869 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1870 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
| 1871 | { |
| 1872 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1873 | struct edid *edid; |
| 1874 | bool has_audio = false; |
| 1875 | |
| 1876 | if (!intel_sdvo->is_hdmi) |
| 1877 | return false; |
| 1878 | |
| 1879 | edid = intel_sdvo_get_edid(connector); |
| 1880 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) |
| 1881 | has_audio = drm_detect_monitor_audio(edid); |
Jani Nikula | 38ab8a2 | 2012-08-15 12:32:36 +0300 | [diff] [blame] | 1882 | kfree(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1883 | |
| 1884 | return has_audio; |
| 1885 | } |
| 1886 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1887 | static int |
| 1888 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1889 | struct drm_property *property, |
| 1890 | uint64_t val) |
| 1891 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1892 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1893 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1894 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1895 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1896 | uint8_t cmd; |
| 1897 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1898 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 1899 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1900 | if (ret) |
| 1901 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1902 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1903 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1904 | int i = val; |
| 1905 | bool has_audio; |
| 1906 | |
| 1907 | if (i == intel_sdvo_connector->force_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1908 | return 0; |
| 1909 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1910 | intel_sdvo_connector->force_audio = i; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1911 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 1912 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1913 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
| 1914 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 1915 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1916 | |
| 1917 | if (has_audio == intel_sdvo->has_hdmi_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1918 | return 0; |
| 1919 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1920 | intel_sdvo->has_hdmi_audio = has_audio; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1921 | goto done; |
| 1922 | } |
| 1923 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1924 | if (property == dev_priv->broadcast_rgb_property) { |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1925 | switch (val) { |
| 1926 | case INTEL_BROADCAST_RGB_AUTO: |
| 1927 | intel_sdvo->color_range_auto = true; |
| 1928 | break; |
| 1929 | case INTEL_BROADCAST_RGB_FULL: |
| 1930 | intel_sdvo->color_range_auto = false; |
| 1931 | intel_sdvo->color_range = 0; |
| 1932 | break; |
| 1933 | case INTEL_BROADCAST_RGB_LIMITED: |
| 1934 | intel_sdvo->color_range_auto = false; |
| 1935 | intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235; |
| 1936 | break; |
| 1937 | default: |
| 1938 | return -EINVAL; |
| 1939 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1940 | goto done; |
| 1941 | } |
| 1942 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1943 | #define CHECK_PROPERTY(name, NAME) \ |
| 1944 | if (intel_sdvo_connector->name == property) { \ |
| 1945 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 1946 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 1947 | cmd = SDVO_CMD_SET_##NAME; \ |
| 1948 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 1949 | goto set_value; \ |
| 1950 | } |
| 1951 | |
| 1952 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1953 | if (val >= TV_FORMAT_NUM) |
| 1954 | return -EINVAL; |
| 1955 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1956 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1957 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1958 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1959 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1960 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1961 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1962 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1963 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1964 | if (intel_sdvo_connector->left == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 1965 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1966 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1967 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1968 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1969 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1970 | intel_sdvo_connector->left_margin = temp_value; |
| 1971 | intel_sdvo_connector->right_margin = temp_value; |
| 1972 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1973 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1974 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1975 | goto set_value; |
| 1976 | } else if (intel_sdvo_connector->right == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 1977 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1978 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1979 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1980 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1981 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1982 | intel_sdvo_connector->left_margin = temp_value; |
| 1983 | intel_sdvo_connector->right_margin = temp_value; |
| 1984 | temp_value = intel_sdvo_connector->max_hscan - |
| 1985 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1986 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1987 | goto set_value; |
| 1988 | } else if (intel_sdvo_connector->top == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 1989 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1990 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1991 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1992 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1993 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1994 | intel_sdvo_connector->top_margin = temp_value; |
| 1995 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1996 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1997 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1998 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1999 | goto set_value; |
| 2000 | } else if (intel_sdvo_connector->bottom == property) { |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2001 | drm_object_property_set_value(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2002 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2003 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2004 | return 0; |
| 2005 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2006 | intel_sdvo_connector->top_margin = temp_value; |
| 2007 | intel_sdvo_connector->bottom_margin = temp_value; |
| 2008 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2009 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2010 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2011 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2012 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2013 | CHECK_PROPERTY(hpos, HPOS) |
| 2014 | CHECK_PROPERTY(vpos, VPOS) |
| 2015 | CHECK_PROPERTY(saturation, SATURATION) |
| 2016 | CHECK_PROPERTY(contrast, CONTRAST) |
| 2017 | CHECK_PROPERTY(hue, HUE) |
| 2018 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 2019 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 2020 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 2021 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 2022 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 2023 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 2024 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2025 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2026 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2027 | |
| 2028 | return -EINVAL; /* unknown property */ |
| 2029 | |
| 2030 | set_value: |
| 2031 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 2032 | return -EIO; |
| 2033 | |
| 2034 | |
| 2035 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 2036 | if (intel_sdvo->base.base.crtc) |
| 2037 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2038 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2039 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2040 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2041 | } |
| 2042 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2043 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2044 | .mode_fixup = intel_sdvo_mode_fixup, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2045 | .mode_set = intel_sdvo_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame] | 2046 | .disable = intel_encoder_noop, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2047 | }; |
| 2048 | |
| 2049 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 2050 | .dpms = intel_sdvo_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2051 | .detect = intel_sdvo_detect, |
| 2052 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2053 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2054 | .destroy = intel_sdvo_destroy, |
| 2055 | }; |
| 2056 | |
| 2057 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 2058 | .get_modes = intel_sdvo_get_modes, |
| 2059 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2060 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2061 | }; |
| 2062 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 2063 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2064 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 2065 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2066 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2067 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2068 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2069 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2070 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2071 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2072 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2073 | } |
| 2074 | |
| 2075 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 2076 | .destroy = intel_sdvo_enc_destroy, |
| 2077 | }; |
| 2078 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 2079 | static void |
| 2080 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 2081 | { |
| 2082 | uint16_t mask = 0; |
| 2083 | unsigned int num_bits; |
| 2084 | |
| 2085 | /* Make a mask of outputs less than or equal to our own priority in the |
| 2086 | * list. |
| 2087 | */ |
| 2088 | switch (sdvo->controlled_output) { |
| 2089 | case SDVO_OUTPUT_LVDS1: |
| 2090 | mask |= SDVO_OUTPUT_LVDS1; |
| 2091 | case SDVO_OUTPUT_LVDS0: |
| 2092 | mask |= SDVO_OUTPUT_LVDS0; |
| 2093 | case SDVO_OUTPUT_TMDS1: |
| 2094 | mask |= SDVO_OUTPUT_TMDS1; |
| 2095 | case SDVO_OUTPUT_TMDS0: |
| 2096 | mask |= SDVO_OUTPUT_TMDS0; |
| 2097 | case SDVO_OUTPUT_RGB1: |
| 2098 | mask |= SDVO_OUTPUT_RGB1; |
| 2099 | case SDVO_OUTPUT_RGB0: |
| 2100 | mask |= SDVO_OUTPUT_RGB0; |
| 2101 | break; |
| 2102 | } |
| 2103 | |
| 2104 | /* Count bits to find what number we are in the priority list. */ |
| 2105 | mask &= sdvo->caps.output_flags; |
| 2106 | num_bits = hweight16(mask); |
| 2107 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 2108 | if (num_bits > 3) |
| 2109 | num_bits = 3; |
| 2110 | |
| 2111 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 2112 | sdvo->ddc_bus = 1 << num_bits; |
| 2113 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2114 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2115 | /** |
| 2116 | * Choose the appropriate DDC bus for control bus switch command for this |
| 2117 | * SDVO output based on the controlled output. |
| 2118 | * |
| 2119 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 2120 | * outputs, then LVDS outputs. |
| 2121 | */ |
| 2122 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2123 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2124 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2125 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2126 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2127 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2128 | if (sdvo->is_sdvob) |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2129 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 2130 | else |
| 2131 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2132 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 2133 | if (mapping->initialized) |
| 2134 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 2135 | else |
| 2136 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2137 | } |
| 2138 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2139 | static void |
| 2140 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
| 2141 | struct intel_sdvo *sdvo, u32 reg) |
| 2142 | { |
| 2143 | struct sdvo_device_mapping *mapping; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 2144 | u8 pin; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2145 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2146 | if (sdvo->is_sdvob) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2147 | mapping = &dev_priv->sdvo_mappings[0]; |
| 2148 | else |
| 2149 | mapping = &dev_priv->sdvo_mappings[1]; |
| 2150 | |
Jani Nikula | 6cb1612 | 2012-10-22 16:12:17 +0300 | [diff] [blame] | 2151 | if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2152 | pin = mapping->i2c_pin; |
Jani Nikula | 6cb1612 | 2012-10-22 16:12:17 +0300 | [diff] [blame] | 2153 | else |
| 2154 | pin = GMBUS_PORT_DPB; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2155 | |
Jani Nikula | 6cb1612 | 2012-10-22 16:12:17 +0300 | [diff] [blame] | 2156 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
| 2157 | |
| 2158 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow |
| 2159 | * our code totally fails once we start using gmbus. Hence fall back to |
| 2160 | * bit banging for now. */ |
| 2161 | intel_gmbus_force_bit(sdvo->i2c, true); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2162 | } |
| 2163 | |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 2164 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
| 2165 | static void |
| 2166 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) |
| 2167 | { |
| 2168 | intel_gmbus_force_bit(sdvo->i2c, false); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2169 | } |
| 2170 | |
| 2171 | static bool |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2172 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2173 | { |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 2174 | return intel_sdvo_check_supp_encode(intel_sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2175 | } |
| 2176 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2177 | static u8 |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2178 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2179 | { |
| 2180 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2181 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2182 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2183 | if (sdvo->is_sdvob) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2184 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2185 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2186 | } else { |
| 2187 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2188 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2189 | } |
| 2190 | |
| 2191 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2192 | if (my_mapping->slave_addr) |
| 2193 | return my_mapping->slave_addr; |
| 2194 | |
| 2195 | /* If the BIOS only described a different SDVO device, use the |
| 2196 | * address that it isn't using. |
| 2197 | */ |
| 2198 | if (other_mapping->slave_addr) { |
| 2199 | if (other_mapping->slave_addr == 0x70) |
| 2200 | return 0x72; |
| 2201 | else |
| 2202 | return 0x70; |
| 2203 | } |
| 2204 | |
| 2205 | /* No SDVO device info is found for another DVO port, |
| 2206 | * so use mapping assumption we had before BIOS parsing. |
| 2207 | */ |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2208 | if (sdvo->is_sdvob) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2209 | return 0x70; |
| 2210 | else |
| 2211 | return 0x72; |
| 2212 | } |
| 2213 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2214 | static void |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2215 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 2216 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2217 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2218 | drm_connector_init(encoder->base.base.dev, |
| 2219 | &connector->base.base, |
| 2220 | &intel_sdvo_connector_funcs, |
| 2221 | connector->base.base.connector_type); |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2222 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2223 | drm_connector_helper_add(&connector->base.base, |
| 2224 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2225 | |
Peter Ross | 8f4839e | 2012-01-28 14:49:25 +0100 | [diff] [blame] | 2226 | connector->base.base.interlace_allowed = 1; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2227 | connector->base.base.doublescan_allowed = 0; |
| 2228 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 2229 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2230 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2231 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 2232 | drm_sysfs_connector_add(&connector->base.base); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2233 | } |
| 2234 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2235 | static void |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2236 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
| 2237 | struct intel_sdvo_connector *connector) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2238 | { |
| 2239 | struct drm_device *dev = connector->base.base.dev; |
| 2240 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2241 | intel_attach_force_audio_property(&connector->base.base); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2242 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2243 | intel_attach_broadcast_rgb_property(&connector->base.base); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2244 | intel_sdvo->color_range_auto = true; |
| 2245 | } |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2246 | } |
| 2247 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2248 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2249 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2250 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2251 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2252 | struct drm_connector *connector; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2253 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2254 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2255 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2256 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2257 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2258 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2259 | return false; |
| 2260 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2261 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2262 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2263 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2264 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2265 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2266 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2267 | } |
| 2268 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2269 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2270 | connector = &intel_connector->base; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2271 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
| 2272 | intel_sdvo_connector->output_flag) { |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2273 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2274 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2275 | /* Some SDVO devices have one-shot hotplug interrupts. |
| 2276 | * Ensure that they get re-enabled when an interrupt happens. |
| 2277 | */ |
| 2278 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; |
| 2279 | intel_sdvo_enable_hotplug(intel_encoder); |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2280 | } else { |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2281 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2282 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2283 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2284 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2285 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2286 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2287 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2288 | intel_sdvo->is_hdmi = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2289 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2290 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2291 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | f797d22 | 2010-12-23 09:43:48 +0000 | [diff] [blame] | 2292 | if (intel_sdvo->is_hdmi) |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2293 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2294 | |
| 2295 | return true; |
| 2296 | } |
| 2297 | |
| 2298 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2299 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2300 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2301 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2302 | struct drm_connector *connector; |
| 2303 | struct intel_connector *intel_connector; |
| 2304 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2305 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2306 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2307 | if (!intel_sdvo_connector) |
| 2308 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2309 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2310 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2311 | connector = &intel_connector->base; |
| 2312 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2313 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2314 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2315 | intel_sdvo->controlled_output |= type; |
| 2316 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2317 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2318 | intel_sdvo->is_tv = true; |
| 2319 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2320 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2321 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2322 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2323 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2324 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2325 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2326 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2327 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2328 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2329 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2330 | |
| 2331 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2332 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2333 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2334 | } |
| 2335 | |
| 2336 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2337 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2338 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2339 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2340 | struct drm_connector *connector; |
| 2341 | struct intel_connector *intel_connector; |
| 2342 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2343 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2344 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2345 | if (!intel_sdvo_connector) |
| 2346 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2347 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2348 | intel_connector = &intel_sdvo_connector->base; |
| 2349 | connector = &intel_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2350 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 2351 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2352 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2353 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2354 | if (device == 0) { |
| 2355 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2356 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2357 | } else if (device == 1) { |
| 2358 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2359 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2360 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2361 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2362 | intel_sdvo_connector_init(intel_sdvo_connector, |
| 2363 | intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2364 | return true; |
| 2365 | } |
| 2366 | |
| 2367 | static bool |
| 2368 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2369 | { |
| 2370 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2371 | struct drm_connector *connector; |
| 2372 | struct intel_connector *intel_connector; |
| 2373 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2374 | |
| 2375 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2376 | if (!intel_sdvo_connector) |
| 2377 | return false; |
| 2378 | |
| 2379 | intel_connector = &intel_sdvo_connector->base; |
| 2380 | connector = &intel_connector->base; |
| 2381 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2382 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2383 | |
| 2384 | if (device == 0) { |
| 2385 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2386 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2387 | } else if (device == 1) { |
| 2388 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2389 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2390 | } |
| 2391 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2392 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2393 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2394 | goto err; |
| 2395 | |
| 2396 | return true; |
| 2397 | |
| 2398 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2399 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2400 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2401 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2402 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2403 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2404 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2405 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2406 | intel_sdvo->is_tv = false; |
| 2407 | intel_sdvo->base.needs_tv_clock = false; |
| 2408 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2409 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2410 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2411 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2412 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2413 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2414 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2415 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2416 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2417 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2418 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2419 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2420 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2421 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2422 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2423 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2424 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2425 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2426 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2427 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2428 | |
Chris Wilson | a0b1c7a | 2011-09-30 22:56:41 +0100 | [diff] [blame] | 2429 | if (flags & SDVO_OUTPUT_YPRPB0) |
| 2430 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) |
| 2431 | return false; |
| 2432 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2433 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2434 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2435 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2436 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2437 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2438 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2439 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2440 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2441 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2442 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2443 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2444 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2445 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2446 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2447 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2448 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2449 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2450 | unsigned char bytes[2]; |
| 2451 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2452 | intel_sdvo->controlled_output = 0; |
| 2453 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2454 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2455 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2456 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2457 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2458 | } |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2459 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2460 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2461 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2462 | } |
| 2463 | |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2464 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
| 2465 | { |
| 2466 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 2467 | struct drm_connector *connector, *tmp; |
| 2468 | |
| 2469 | list_for_each_entry_safe(connector, tmp, |
| 2470 | &dev->mode_config.connector_list, head) { |
| 2471 | if (intel_attached_encoder(connector) == &intel_sdvo->base) |
| 2472 | intel_sdvo_destroy(connector); |
| 2473 | } |
| 2474 | } |
| 2475 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2476 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2477 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2478 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2479 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2480 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2481 | struct intel_sdvo_tv_format format; |
| 2482 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2483 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2484 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2485 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2486 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2487 | BUILD_BUG_ON(sizeof(format) != 6); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2488 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2489 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2490 | &format, sizeof(format))) |
| 2491 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2492 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2493 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2494 | |
| 2495 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2496 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2497 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2498 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2499 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2500 | if (format_map & (1 << i)) |
| 2501 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2502 | |
| 2503 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2504 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2505 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2506 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2507 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2508 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2509 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2510 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2511 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2512 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2513 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2514 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2515 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2516 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2517 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2518 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2519 | |
| 2520 | } |
| 2521 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2522 | #define ENHANCEMENT(name, NAME) do { \ |
| 2523 | if (enhancements.name) { \ |
| 2524 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2525 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2526 | return false; \ |
| 2527 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2528 | intel_sdvo_connector->cur_##name = response; \ |
| 2529 | intel_sdvo_connector->name = \ |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2530 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2531 | if (!intel_sdvo_connector->name) return false; \ |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2532 | drm_object_attach_property(&connector->base, \ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2533 | intel_sdvo_connector->name, \ |
| 2534 | intel_sdvo_connector->cur_##name); \ |
| 2535 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2536 | data_value[0], data_value[1], response); \ |
| 2537 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2538 | } while (0) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2539 | |
| 2540 | static bool |
| 2541 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2542 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2543 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2544 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2545 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2546 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2547 | uint16_t response, data_value[2]; |
| 2548 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2549 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2550 | if (enhancements.overscan_h) { |
| 2551 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2552 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2553 | &data_value, 4)) |
| 2554 | return false; |
| 2555 | |
| 2556 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2557 | SDVO_CMD_GET_OVERSCAN_H, |
| 2558 | &response, 2)) |
| 2559 | return false; |
| 2560 | |
| 2561 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2562 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2563 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2564 | intel_sdvo_connector->left = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2565 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2566 | if (!intel_sdvo_connector->left) |
| 2567 | return false; |
| 2568 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2569 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2570 | intel_sdvo_connector->left, |
| 2571 | intel_sdvo_connector->left_margin); |
| 2572 | |
| 2573 | intel_sdvo_connector->right = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2574 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2575 | if (!intel_sdvo_connector->right) |
| 2576 | return false; |
| 2577 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2578 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2579 | intel_sdvo_connector->right, |
| 2580 | intel_sdvo_connector->right_margin); |
| 2581 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2582 | "default %d, current %d\n", |
| 2583 | data_value[0], data_value[1], response); |
| 2584 | } |
| 2585 | |
| 2586 | if (enhancements.overscan_v) { |
| 2587 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2588 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2589 | &data_value, 4)) |
| 2590 | return false; |
| 2591 | |
| 2592 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2593 | SDVO_CMD_GET_OVERSCAN_V, |
| 2594 | &response, 2)) |
| 2595 | return false; |
| 2596 | |
| 2597 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2598 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2599 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2600 | intel_sdvo_connector->top = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2601 | drm_property_create_range(dev, 0, |
| 2602 | "top_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2603 | if (!intel_sdvo_connector->top) |
| 2604 | return false; |
| 2605 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2606 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2607 | intel_sdvo_connector->top, |
| 2608 | intel_sdvo_connector->top_margin); |
| 2609 | |
| 2610 | intel_sdvo_connector->bottom = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2611 | drm_property_create_range(dev, 0, |
| 2612 | "bottom_margin", 0, data_value[0]); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2613 | if (!intel_sdvo_connector->bottom) |
| 2614 | return false; |
| 2615 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2616 | drm_object_attach_property(&connector->base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2617 | intel_sdvo_connector->bottom, |
| 2618 | intel_sdvo_connector->bottom_margin); |
| 2619 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2620 | "default %d, current %d\n", |
| 2621 | data_value[0], data_value[1], response); |
| 2622 | } |
| 2623 | |
| 2624 | ENHANCEMENT(hpos, HPOS); |
| 2625 | ENHANCEMENT(vpos, VPOS); |
| 2626 | ENHANCEMENT(saturation, SATURATION); |
| 2627 | ENHANCEMENT(contrast, CONTRAST); |
| 2628 | ENHANCEMENT(hue, HUE); |
| 2629 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2630 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2631 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2632 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2633 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2634 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2635 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2636 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2637 | if (enhancements.dot_crawl) { |
| 2638 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2639 | return false; |
| 2640 | |
| 2641 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2642 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2643 | intel_sdvo_connector->dot_crawl = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 2644 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2645 | if (!intel_sdvo_connector->dot_crawl) |
| 2646 | return false; |
| 2647 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2648 | drm_object_attach_property(&connector->base, |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2649 | intel_sdvo_connector->dot_crawl, |
| 2650 | intel_sdvo_connector->cur_dot_crawl); |
| 2651 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2652 | } |
| 2653 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2654 | return true; |
| 2655 | } |
| 2656 | |
| 2657 | static bool |
| 2658 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2659 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2660 | struct intel_sdvo_enhancements_reply enhancements) |
| 2661 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2662 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2663 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2664 | uint16_t response, data_value[2]; |
| 2665 | |
| 2666 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2667 | |
| 2668 | return true; |
| 2669 | } |
| 2670 | #undef ENHANCEMENT |
| 2671 | |
| 2672 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2673 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2674 | { |
| 2675 | union { |
| 2676 | struct intel_sdvo_enhancements_reply reply; |
| 2677 | uint16_t response; |
| 2678 | } enhancements; |
| 2679 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2680 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
| 2681 | |
Chris Wilson | cf9a2f3 | 2010-09-23 16:17:33 +0100 | [diff] [blame] | 2682 | enhancements.response = 0; |
| 2683 | intel_sdvo_get_value(intel_sdvo, |
| 2684 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
| 2685 | &enhancements, sizeof(enhancements)); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2686 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2687 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2688 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2689 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2690 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2691 | if (IS_TV(intel_sdvo_connector)) |
| 2692 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2693 | else if (IS_LVDS(intel_sdvo_connector)) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2694 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2695 | else |
| 2696 | return true; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2697 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2698 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2699 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 2700 | struct i2c_msg *msgs, |
| 2701 | int num) |
| 2702 | { |
| 2703 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2704 | |
| 2705 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 2706 | return -EIO; |
| 2707 | |
| 2708 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 2709 | } |
| 2710 | |
| 2711 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 2712 | { |
| 2713 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2714 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 2715 | } |
| 2716 | |
| 2717 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 2718 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 2719 | .functionality = intel_sdvo_ddc_proxy_func |
| 2720 | }; |
| 2721 | |
| 2722 | static bool |
| 2723 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 2724 | struct drm_device *dev) |
| 2725 | { |
| 2726 | sdvo->ddc.owner = THIS_MODULE; |
| 2727 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 2728 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
| 2729 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
| 2730 | sdvo->ddc.algo_data = sdvo; |
| 2731 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 2732 | |
| 2733 | return i2c_add_adapter(&sdvo->ddc) == 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2734 | } |
| 2735 | |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2736 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2737 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2738 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2739 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2740 | struct intel_sdvo *intel_sdvo; |
Chris Wilson | 084b612 | 2012-05-11 18:01:33 +0100 | [diff] [blame] | 2741 | u32 hotplug_mask; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2742 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2743 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2744 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2745 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2746 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2747 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2748 | intel_sdvo->sdvo_reg = sdvo_reg; |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2749 | intel_sdvo->is_sdvob = is_sdvob; |
| 2750 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2751 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 2752 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
| 2753 | goto err_i2c_bus; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2754 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2755 | /* encoder type will be decided later */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2756 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2757 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2758 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2759 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2760 | /* Read the regs to test if we can talk to the device */ |
| 2761 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2762 | u8 byte; |
| 2763 | |
| 2764 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2765 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
| 2766 | SDVO_NAME(intel_sdvo)); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2767 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2768 | } |
| 2769 | } |
| 2770 | |
Chris Wilson | 084b612 | 2012-05-11 18:01:33 +0100 | [diff] [blame] | 2771 | hotplug_mask = 0; |
| 2772 | if (IS_G4X(dev)) { |
| 2773 | hotplug_mask = intel_sdvo->is_sdvob ? |
| 2774 | SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X; |
| 2775 | } else if (IS_GEN4(dev)) { |
| 2776 | hotplug_mask = intel_sdvo->is_sdvob ? |
| 2777 | SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965; |
| 2778 | } else { |
| 2779 | hotplug_mask = intel_sdvo->is_sdvob ? |
| 2780 | SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; |
| 2781 | } |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2782 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2783 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2784 | |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 2785 | intel_encoder->disable = intel_disable_sdvo; |
| 2786 | intel_encoder->enable = intel_enable_sdvo; |
Daniel Vetter | 4ac41f4 | 2012-07-02 14:54:00 +0200 | [diff] [blame] | 2787 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
Daniel Vetter | ce22c32 | 2012-07-01 15:31:04 +0200 | [diff] [blame] | 2788 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2789 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2790 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2791 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2792 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2793 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2794 | intel_sdvo->caps.output_flags) != true) { |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 2795 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
| 2796 | SDVO_NAME(intel_sdvo)); |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2797 | /* Output_setup can leave behind connectors! */ |
| 2798 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2799 | } |
| 2800 | |
Daniel Vetter | e506d6f | 2012-11-13 17:24:43 +0100 | [diff] [blame] | 2801 | /* |
| 2802 | * Cloning SDVO with anything is often impossible, since the SDVO |
| 2803 | * encoder can request a special input timing mode. And even if that's |
| 2804 | * not the case we have evidence that cloning a plain unscaled mode with |
| 2805 | * VGA doesn't really work. Furthermore the cloning flags are way too |
| 2806 | * simplistic anyway to express such constraints, so just give up on |
| 2807 | * cloning for SDVO encoders. |
| 2808 | */ |
| 2809 | intel_sdvo->base.cloneable = false; |
| 2810 | |
Jani Nikula | fcbc50d | 2012-08-29 14:08:42 +0300 | [diff] [blame] | 2811 | /* Only enable the hotplug irq if we need it, to work around noisy |
| 2812 | * hotplug lines. |
| 2813 | */ |
Jani Nikula | 5fa7ac9 | 2012-08-29 16:43:58 +0300 | [diff] [blame] | 2814 | if (intel_sdvo->hotplug_active) |
Jani Nikula | fcbc50d | 2012-08-29 14:08:42 +0300 | [diff] [blame] | 2815 | dev_priv->hotplug_supported_mask |= hotplug_mask; |
| 2816 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2817 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2818 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2819 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2820 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2821 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2822 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2823 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2824 | &intel_sdvo->pixel_clock_min, |
| 2825 | &intel_sdvo->pixel_clock_max)) |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2826 | goto err_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2827 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2828 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2829 | "clock range %dMHz - %dMHz, " |
| 2830 | "input 1: %c, input 2: %c, " |
| 2831 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2832 | SDVO_NAME(intel_sdvo), |
| 2833 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2834 | intel_sdvo->caps.device_rev_id, |
| 2835 | intel_sdvo->pixel_clock_min / 1000, |
| 2836 | intel_sdvo->pixel_clock_max / 1000, |
| 2837 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2838 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2839 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2840 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2841 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2842 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2843 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2844 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2845 | |
Jani Nikula | d0ddfbd | 2012-11-12 18:31:35 +0200 | [diff] [blame] | 2846 | err_output: |
| 2847 | intel_sdvo_output_cleanup(intel_sdvo); |
| 2848 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2849 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2850 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2851 | i2c_del_adapter(&intel_sdvo->ddc); |
Jani Nikula | fbfcc4f | 2012-10-22 16:12:18 +0300 | [diff] [blame] | 2852 | err_i2c_bus: |
| 2853 | intel_sdvo_unselect_i2c_bus(intel_sdvo); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2854 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2855 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2856 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2857 | } |