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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050045#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48#define DRV_NAME "ahci"
Jeff Garzikcd70c262007-07-08 02:29:42 -040049#define DRV_VERSION "2.3"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51
52enum {
53 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090054 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020057 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090058 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090059 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090060 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090063 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090071 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090072 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090076 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090077 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 board_ahci = 0,
Tejun Heo648a88b2006-11-09 15:08:40 +090080 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
Conke Hu55a61602007-03-27 18:33:05 +080083 board_ahci_sb600 = 4,
Jeff Garzikcd70c262007-07-08 02:29:42 -040084 board_ahci_mv = 5,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92
93 /* HOST_CTL bits */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97
98 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +090099 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo22b49982006-01-23 21:38:44 +0900100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
Tejun Heo78cd52d2006-05-15 20:58:29 +0900143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900146 PORT_IRQ_PHYRDY |
Tejun Heo78cd52d2006-05-15 20:58:29 +0900147 PORT_IRQ_UNK_FIS,
148 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_TF_ERR |
150 PORT_IRQ_HBUS_DATA_ERR,
151 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
152 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
153 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154
155 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500156 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
158 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
159 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900160 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
162 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
163 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164
Tejun Heo0be0aa92006-07-26 15:59:26 +0900165 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
167 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
168 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400169
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200170 /* ap->flags bits */
Tejun Heo4aeb0e32006-11-01 17:58:33 +0900171 AHCI_FLAG_NO_NCQ = (1 << 24),
172 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
Tejun Heo648a88b2006-11-09 15:08:40 +0900173 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
Conke Hu55a61602007-03-27 18:33:05 +0800174 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
Tejun Heoc7a42152007-05-18 16:23:19 +0200175 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400176 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
177 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900178
179 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
180 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Tejun Heo3cadbcc2007-05-15 03:28:15 +0900181 ATA_FLAG_SKIP_D2H_BSY |
182 ATA_FLAG_ACPI_SATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183};
184
185struct ahci_cmd_hdr {
186 u32 opts;
187 u32 status;
188 u32 tbl_addr;
189 u32 tbl_addr_hi;
190 u32 reserved[4];
191};
192
193struct ahci_sg {
194 u32 addr;
195 u32 addr_hi;
196 u32 reserved;
197 u32 flags_size;
198};
199
200struct ahci_host_priv {
Tejun Heod447df12007-03-18 22:15:33 +0900201 u32 cap; /* cap to use */
202 u32 port_map; /* port map to use */
203 u32 saved_cap; /* saved initial cap */
204 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205};
206
207struct ahci_port_priv {
208 struct ahci_cmd_hdr *cmd_slot;
209 dma_addr_t cmd_slot_dma;
210 void *cmd_tbl;
211 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 void *rx_fis;
213 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900214 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900215 unsigned int ncq_saw_d2h:1;
216 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900217 unsigned int ncq_saw_sdb:1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218};
219
Tejun Heoda3dbb12007-07-16 14:29:40 +0900220static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
221static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900223static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225static int ahci_port_start(struct ata_port *ap);
226static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
228static void ahci_qc_prep(struct ata_queued_cmd *qc);
229static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900230static void ahci_freeze(struct ata_port *ap);
231static void ahci_thaw(struct ata_port *ap);
232static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900233static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900234static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400235static int ahci_port_resume(struct ata_port *ap);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400236static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
237static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
238 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900239#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900240static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900241static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
242static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900243#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244
Jeff Garzik193515d2005-11-07 00:59:37 -0500245static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 .module = THIS_MODULE,
247 .name = DRV_NAME,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900250 .change_queue_depth = ata_scsi_change_queue_depth,
251 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 .this_id = ATA_SHT_THIS_ID,
253 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = AHCI_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = AHCI_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900260 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262};
263
Jeff Garzik057ace52005-10-22 14:27:05 -0400264static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 .port_disable = ata_port_disable,
266
267 .check_status = ahci_check_status,
268 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 .dev_select = ata_noop_dev_select,
270
271 .tf_read = ahci_tf_read,
272
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 .qc_prep = ahci_qc_prep,
274 .qc_issue = ahci_qc_issue,
275
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 .irq_clear = ahci_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900277 .irq_on = ata_dummy_irq_on,
278 .irq_ack = ata_dummy_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
280 .scr_read = ahci_scr_read,
281 .scr_write = ahci_scr_write,
282
Tejun Heo78cd52d2006-05-15 20:58:29 +0900283 .freeze = ahci_freeze,
284 .thaw = ahci_thaw,
285
286 .error_handler = ahci_error_handler,
287 .post_internal_cmd = ahci_post_internal_cmd,
288
Tejun Heo438ac6d2007-03-02 17:31:26 +0900289#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900290 .port_suspend = ahci_port_suspend,
291 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900292#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900293
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 .port_start = ahci_port_start,
295 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296};
297
Tejun Heoad616ff2006-11-01 18:00:24 +0900298static const struct ata_port_operations ahci_vt8251_ops = {
299 .port_disable = ata_port_disable,
300
301 .check_status = ahci_check_status,
302 .check_altstatus = ahci_check_status,
303 .dev_select = ata_noop_dev_select,
304
305 .tf_read = ahci_tf_read,
306
307 .qc_prep = ahci_qc_prep,
308 .qc_issue = ahci_qc_issue,
309
Tejun Heoad616ff2006-11-01 18:00:24 +0900310 .irq_clear = ahci_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900311 .irq_on = ata_dummy_irq_on,
312 .irq_ack = ata_dummy_irq_ack,
Tejun Heoad616ff2006-11-01 18:00:24 +0900313
314 .scr_read = ahci_scr_read,
315 .scr_write = ahci_scr_write,
316
317 .freeze = ahci_freeze,
318 .thaw = ahci_thaw,
319
320 .error_handler = ahci_vt8251_error_handler,
321 .post_internal_cmd = ahci_post_internal_cmd,
322
Tejun Heo438ac6d2007-03-02 17:31:26 +0900323#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900324 .port_suspend = ahci_port_suspend,
325 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900326#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900327
328 .port_start = ahci_port_start,
329 .port_stop = ahci_port_stop,
330};
331
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100332static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 /* board_ahci */
334 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900335 .flags = AHCI_FLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400336 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400337 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 .port_ops = &ahci_ops,
339 },
Tejun Heo648a88b2006-11-09 15:08:40 +0900340 /* board_ahci_pi */
341 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900342 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
Tejun Heo648a88b2006-11-09 15:08:40 +0900343 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400344 .udma_mask = ATA_UDMA6,
Tejun Heo648a88b2006-11-09 15:08:40 +0900345 .port_ops = &ahci_ops,
346 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200347 /* board_ahci_vt8251 */
348 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900349 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
350 AHCI_FLAG_NO_NCQ,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200351 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400352 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900353 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200354 },
Tejun Heo41669552006-11-29 11:33:14 +0900355 /* board_ahci_ign_iferr */
356 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900357 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
Tejun Heo41669552006-11-29 11:33:14 +0900358 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400359 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900360 .port_ops = &ahci_ops,
361 },
Conke Hu55a61602007-03-27 18:33:05 +0800362 /* board_ahci_sb600 */
363 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900364 .flags = AHCI_FLAG_COMMON |
Tejun Heoc7a42152007-05-18 16:23:19 +0200365 AHCI_FLAG_IGN_SERR_INTERNAL |
366 AHCI_FLAG_32BIT_ONLY,
Conke Hu55a61602007-03-27 18:33:05 +0800367 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400368 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800369 .port_ops = &ahci_ops,
370 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400371 /* board_ahci_mv */
372 {
373 .sht = &ahci_sht,
374 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
375 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
376 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI |
377 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
378 AHCI_FLAG_MV_PATA,
379 .pio_mask = 0x1f, /* pio0-4 */
380 .udma_mask = ATA_UDMA6,
381 .port_ops = &ahci_ops,
382 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383};
384
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500385static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400386 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400387 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
388 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
389 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
390 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
391 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900392 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400393 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
395 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
396 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo648a88b2006-11-09 15:08:40 +0900397 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
399 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
400 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
401 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
402 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
406 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
407 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
409 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
Jason Gaston8af12cd2007-03-02 17:39:46 -0800410 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
Tejun Heo648a88b2006-11-09 15:08:40 +0900411 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
412 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400414
Tejun Heoe34bb372007-02-26 20:24:03 +0900415 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
416 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400418
419 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800420 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
henry suc69c0892007-09-20 16:07:33 -0400421 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
422 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
423 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
424 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
426 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400427
428 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400429 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900430 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400431
432 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400433 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500437 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
441 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500445 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800453 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400477
Jeff Garzik95916ed2006-07-29 04:10:14 -0400478 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400479 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
480 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
481 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400482
Jeff Garzikcd70c262007-07-08 02:29:42 -0400483 /* Marvell */
484 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
485
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500486 /* Generic, PCI class code for AHCI */
487 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500488 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500489
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 { } /* terminate list */
491};
492
493
494static struct pci_driver ahci_pci_driver = {
495 .name = DRV_NAME,
496 .id_table = ahci_pci_tbl,
497 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900498 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900499#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900500 .suspend = ahci_pci_device_suspend,
501 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900502#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503};
504
505
Tejun Heo98fa4b62006-11-02 12:17:23 +0900506static inline int ahci_nr_ports(u32 cap)
507{
508 return (cap & 0x1f) + 1;
509}
510
Jeff Garzikdab632e2007-05-28 08:33:01 -0400511static inline void __iomem *__ahci_port_base(struct ata_host *host,
512 unsigned int port_no)
513{
514 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
515
516 return mmio + 0x100 + (port_no * 0x80);
517}
518
Tejun Heo4447d352007-04-17 23:44:08 +0900519static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400521 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522}
523
Tejun Heod447df12007-03-18 22:15:33 +0900524/**
525 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900526 * @pdev: target PCI device
527 * @pi: associated ATA port info
528 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900529 *
530 * Some registers containing configuration info might be setup by
531 * BIOS and might be cleared on reset. This function saves the
532 * initial values of those registers into @hpriv such that they
533 * can be restored after controller reset.
534 *
535 * If inconsistent, config values are fixed up by this function.
536 *
537 * LOCKING:
538 * None.
539 */
Tejun Heo4447d352007-04-17 23:44:08 +0900540static void ahci_save_initial_config(struct pci_dev *pdev,
541 const struct ata_port_info *pi,
542 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900543{
Tejun Heo4447d352007-04-17 23:44:08 +0900544 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900545 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900546 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900547
548 /* Values prefixed with saved_ are written back to host after
549 * reset. Values without are used for driver operation.
550 */
551 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
552 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
553
Tejun Heo274c1fd2007-07-16 14:29:40 +0900554 /* some chips have errata preventing 64bit use */
Tejun Heoc7a42152007-05-18 16:23:19 +0200555 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
556 dev_printk(KERN_INFO, &pdev->dev,
557 "controller can't do 64bit DMA, forcing 32bit\n");
558 cap &= ~HOST_CAP_64;
559 }
560
Tejun Heo274c1fd2007-07-16 14:29:40 +0900561 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
562 dev_printk(KERN_INFO, &pdev->dev,
563 "controller can't do NCQ, turning off CAP_NCQ\n");
564 cap &= ~HOST_CAP_NCQ;
565 }
566
Tejun Heod447df12007-03-18 22:15:33 +0900567 /* fixup zero port_map */
568 if (!port_map) {
Tejun Heoa3d2cc52007-06-19 18:52:56 +0900569 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo4447d352007-04-17 23:44:08 +0900570 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heod447df12007-03-18 22:15:33 +0900571 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
572
573 /* write the fixed up value to the PI register */
574 hpriv->saved_port_map = port_map;
575 }
576
Jeff Garzikcd70c262007-07-08 02:29:42 -0400577 /*
578 * Temporary Marvell 6145 hack: PATA port presence
579 * is asserted through the standard AHCI port
580 * presence register, as bit 4 (counting from 0)
581 */
582 if (pi->flags & AHCI_FLAG_MV_PATA) {
583 dev_printk(KERN_ERR, &pdev->dev,
584 "MV_AHCI HACK: port_map %x -> %x\n",
585 hpriv->port_map,
586 hpriv->port_map & 0xf);
587
588 port_map &= 0xf;
589 }
590
Tejun Heo17199b12007-03-18 22:26:53 +0900591 /* cross check port_map and cap.n_ports */
Tejun Heo4447d352007-04-17 23:44:08 +0900592 if (pi->flags & AHCI_FLAG_HONOR_PI) {
Tejun Heo17199b12007-03-18 22:26:53 +0900593 u32 tmp_port_map = port_map;
594 int n_ports = ahci_nr_ports(cap);
595
596 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
597 if (tmp_port_map & (1 << i)) {
598 n_ports--;
599 tmp_port_map &= ~(1 << i);
600 }
601 }
602
603 /* Whine if inconsistent. No need to update cap.
604 * port_map is used to determine number of ports.
605 */
606 if (n_ports || tmp_port_map)
Tejun Heo4447d352007-04-17 23:44:08 +0900607 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo17199b12007-03-18 22:26:53 +0900608 "nr_ports (%u) and implemented port map "
609 "(0x%x) don't match\n",
610 ahci_nr_ports(cap), port_map);
611 } else {
612 /* fabricate port_map from cap.nr_ports */
613 port_map = (1 << ahci_nr_ports(cap)) - 1;
614 }
615
Tejun Heod447df12007-03-18 22:15:33 +0900616 /* record values to use during operation */
617 hpriv->cap = cap;
618 hpriv->port_map = port_map;
619}
620
621/**
622 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900623 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900624 *
625 * Restore initial config stored by ahci_save_initial_config().
626 *
627 * LOCKING:
628 * None.
629 */
Tejun Heo4447d352007-04-17 23:44:08 +0900630static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900631{
Tejun Heo4447d352007-04-17 23:44:08 +0900632 struct ahci_host_priv *hpriv = host->private_data;
633 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
634
Tejun Heod447df12007-03-18 22:15:33 +0900635 writel(hpriv->saved_cap, mmio + HOST_CAP);
636 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
637 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
638}
639
Tejun Heo203ef6c2007-07-16 14:29:40 +0900640static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900642 static const int offset[] = {
643 [SCR_STATUS] = PORT_SCR_STAT,
644 [SCR_CONTROL] = PORT_SCR_CTL,
645 [SCR_ERROR] = PORT_SCR_ERR,
646 [SCR_ACTIVE] = PORT_SCR_ACT,
647 [SCR_NOTIFICATION] = PORT_SCR_NTF,
648 };
649 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Tejun Heo203ef6c2007-07-16 14:29:40 +0900651 if (sc_reg < ARRAY_SIZE(offset) &&
652 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
653 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900654 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655}
656
Tejun Heo203ef6c2007-07-16 14:29:40 +0900657static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900659 void __iomem *port_mmio = ahci_port_base(ap);
660 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
Tejun Heo203ef6c2007-07-16 14:29:40 +0900662 if (offset) {
663 *val = readl(port_mmio + offset);
664 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900666 return -EINVAL;
667}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668
Tejun Heo203ef6c2007-07-16 14:29:40 +0900669static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
670{
671 void __iomem *port_mmio = ahci_port_base(ap);
672 int offset = ahci_scr_offset(ap, sc_reg);
673
674 if (offset) {
675 writel(val, port_mmio + offset);
676 return 0;
677 }
678 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679}
680
Tejun Heo4447d352007-04-17 23:44:08 +0900681static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900682{
Tejun Heo4447d352007-04-17 23:44:08 +0900683 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900684 u32 tmp;
685
Tejun Heod8fcd112006-07-26 15:59:25 +0900686 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900687 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900688 tmp |= PORT_CMD_START;
689 writel(tmp, port_mmio + PORT_CMD);
690 readl(port_mmio + PORT_CMD); /* flush */
691}
692
Tejun Heo4447d352007-04-17 23:44:08 +0900693static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900694{
Tejun Heo4447d352007-04-17 23:44:08 +0900695 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900696 u32 tmp;
697
698 tmp = readl(port_mmio + PORT_CMD);
699
Tejun Heod8fcd112006-07-26 15:59:25 +0900700 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900701 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
702 return 0;
703
Tejun Heod8fcd112006-07-26 15:59:25 +0900704 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900705 tmp &= ~PORT_CMD_START;
706 writel(tmp, port_mmio + PORT_CMD);
707
Tejun Heod8fcd112006-07-26 15:59:25 +0900708 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900709 tmp = ata_wait_register(port_mmio + PORT_CMD,
710 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900711 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900712 return -EIO;
713
714 return 0;
715}
716
Tejun Heo4447d352007-04-17 23:44:08 +0900717static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900718{
Tejun Heo4447d352007-04-17 23:44:08 +0900719 void __iomem *port_mmio = ahci_port_base(ap);
720 struct ahci_host_priv *hpriv = ap->host->private_data;
721 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900722 u32 tmp;
723
724 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900725 if (hpriv->cap & HOST_CAP_64)
726 writel((pp->cmd_slot_dma >> 16) >> 16,
727 port_mmio + PORT_LST_ADDR_HI);
728 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900729
Tejun Heo4447d352007-04-17 23:44:08 +0900730 if (hpriv->cap & HOST_CAP_64)
731 writel((pp->rx_fis_dma >> 16) >> 16,
732 port_mmio + PORT_FIS_ADDR_HI);
733 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900734
735 /* enable FIS reception */
736 tmp = readl(port_mmio + PORT_CMD);
737 tmp |= PORT_CMD_FIS_RX;
738 writel(tmp, port_mmio + PORT_CMD);
739
740 /* flush */
741 readl(port_mmio + PORT_CMD);
742}
743
Tejun Heo4447d352007-04-17 23:44:08 +0900744static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900745{
Tejun Heo4447d352007-04-17 23:44:08 +0900746 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900747 u32 tmp;
748
749 /* disable FIS reception */
750 tmp = readl(port_mmio + PORT_CMD);
751 tmp &= ~PORT_CMD_FIS_RX;
752 writel(tmp, port_mmio + PORT_CMD);
753
754 /* wait for completion, spec says 500ms, give it 1000 */
755 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
756 PORT_CMD_FIS_ON, 10, 1000);
757 if (tmp & PORT_CMD_FIS_ON)
758 return -EBUSY;
759
760 return 0;
761}
762
Tejun Heo4447d352007-04-17 23:44:08 +0900763static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900764{
Tejun Heo4447d352007-04-17 23:44:08 +0900765 struct ahci_host_priv *hpriv = ap->host->private_data;
766 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900767 u32 cmd;
768
769 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
770
771 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900772 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900773 cmd |= PORT_CMD_SPIN_UP;
774 writel(cmd, port_mmio + PORT_CMD);
775 }
776
777 /* wake up link */
778 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
779}
780
Tejun Heo438ac6d2007-03-02 17:31:26 +0900781#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +0900782static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900783{
Tejun Heo4447d352007-04-17 23:44:08 +0900784 struct ahci_host_priv *hpriv = ap->host->private_data;
785 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900786 u32 cmd, scontrol;
787
Tejun Heo4447d352007-04-17 23:44:08 +0900788 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +0900789 return;
790
791 /* put device into listen mode, first set PxSCTL.DET to 0 */
792 scontrol = readl(port_mmio + PORT_SCR_CTL);
793 scontrol &= ~0xf;
794 writel(scontrol, port_mmio + PORT_SCR_CTL);
795
796 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900797 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +0900798 cmd &= ~PORT_CMD_SPIN_UP;
799 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900800}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900801#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +0900802
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400803static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900804{
Tejun Heo0be0aa92006-07-26 15:59:26 +0900805 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900806 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900807
808 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900809 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900810}
811
Tejun Heo4447d352007-04-17 23:44:08 +0900812static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900813{
814 int rc;
815
816 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900817 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900818 if (rc) {
819 *emsg = "failed to stop engine";
820 return rc;
821 }
822
823 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900824 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900825 if (rc) {
826 *emsg = "failed stop FIS RX";
827 return rc;
828 }
829
Tejun Heo0be0aa92006-07-26 15:59:26 +0900830 return 0;
831}
832
Tejun Heo4447d352007-04-17 23:44:08 +0900833static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900834{
Tejun Heo4447d352007-04-17 23:44:08 +0900835 struct pci_dev *pdev = to_pci_dev(host->dev);
836 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900837 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +0900838
839 /* global controller reset */
840 tmp = readl(mmio + HOST_CTL);
841 if ((tmp & HOST_RESET) == 0) {
842 writel(tmp | HOST_RESET, mmio + HOST_CTL);
843 readl(mmio + HOST_CTL); /* flush */
844 }
845
846 /* reset must complete within 1 second, or
847 * the hardware should be considered fried.
848 */
849 ssleep(1);
850
851 tmp = readl(mmio + HOST_CTL);
852 if (tmp & HOST_RESET) {
Tejun Heo4447d352007-04-17 23:44:08 +0900853 dev_printk(KERN_ERR, host->dev,
Tejun Heod91542c2006-07-26 15:59:26 +0900854 "controller reset failed (0x%x)\n", tmp);
855 return -EIO;
856 }
857
Tejun Heo98fa4b62006-11-02 12:17:23 +0900858 /* turn on AHCI mode */
Tejun Heod91542c2006-07-26 15:59:26 +0900859 writel(HOST_AHCI_EN, mmio + HOST_CTL);
860 (void) readl(mmio + HOST_CTL); /* flush */
Tejun Heo98fa4b62006-11-02 12:17:23 +0900861
Tejun Heod447df12007-03-18 22:15:33 +0900862 /* some registers might be cleared on reset. restore initial values */
Tejun Heo4447d352007-04-17 23:44:08 +0900863 ahci_restore_initial_config(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900864
865 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
866 u16 tmp16;
867
868 /* configure PCS */
869 pci_read_config_word(pdev, 0x92, &tmp16);
870 tmp16 |= 0xf;
871 pci_write_config_word(pdev, 0x92, tmp16);
872 }
873
874 return 0;
875}
876
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400877static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
878 int port_no, void __iomem *mmio,
879 void __iomem *port_mmio)
880{
881 const char *emsg = NULL;
882 int rc;
883 u32 tmp;
884
885 /* make sure port is not active */
886 rc = ahci_deinit_port(ap, &emsg);
887 if (rc)
888 dev_printk(KERN_WARNING, &pdev->dev,
889 "%s (%d)\n", emsg, rc);
890
891 /* clear SError */
892 tmp = readl(port_mmio + PORT_SCR_ERR);
893 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
894 writel(tmp, port_mmio + PORT_SCR_ERR);
895
896 /* clear port IRQ */
897 tmp = readl(port_mmio + PORT_IRQ_STAT);
898 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
899 if (tmp)
900 writel(tmp, port_mmio + PORT_IRQ_STAT);
901
902 writel(1 << port_no, mmio + HOST_IRQ_STAT);
903}
904
Tejun Heo4447d352007-04-17 23:44:08 +0900905static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900906{
Tejun Heo4447d352007-04-17 23:44:08 +0900907 struct pci_dev *pdev = to_pci_dev(host->dev);
908 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400909 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400910 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +0900911 u32 tmp;
912
Jeff Garzikcd70c262007-07-08 02:29:42 -0400913 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
914 port_mmio = __ahci_port_base(host, 4);
915
916 writel(0, port_mmio + PORT_IRQ_MASK);
917
918 /* clear port IRQ */
919 tmp = readl(port_mmio + PORT_IRQ_STAT);
920 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
921 if (tmp)
922 writel(tmp, port_mmio + PORT_IRQ_STAT);
923 }
924
Tejun Heo4447d352007-04-17 23:44:08 +0900925 for (i = 0; i < host->n_ports; i++) {
926 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +0900927
Jeff Garzikcd70c262007-07-08 02:29:42 -0400928 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +0900929 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +0900930 continue;
Tejun Heod91542c2006-07-26 15:59:26 +0900931
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400932 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +0900933 }
934
935 tmp = readl(mmio + HOST_CTL);
936 VPRINTK("HOST_CTL 0x%x\n", tmp);
937 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
938 tmp = readl(mmio + HOST_CTL);
939 VPRINTK("HOST_CTL 0x%x\n", tmp);
940}
941
Tejun Heo422b7592005-12-19 22:37:17 +0900942static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943{
Tejun Heo4447d352007-04-17 23:44:08 +0900944 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +0900946 u32 tmp;
947
948 tmp = readl(port_mmio + PORT_SIG);
949 tf.lbah = (tmp >> 24) & 0xff;
950 tf.lbam = (tmp >> 16) & 0xff;
951 tf.lbal = (tmp >> 8) & 0xff;
952 tf.nsect = (tmp) & 0xff;
953
954 return ata_dev_classify(&tf);
955}
956
Tejun Heo12fad3f2006-05-15 21:03:55 +0900957static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
958 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +0900959{
Tejun Heo12fad3f2006-05-15 21:03:55 +0900960 dma_addr_t cmd_tbl_dma;
961
962 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
963
964 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
965 pp->cmd_slot[tag].status = 0;
966 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
967 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +0900968}
969
Tejun Heod2e75df2007-07-16 14:29:39 +0900970static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200971{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900972 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -0400973 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200974 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +0900975 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200976
Tejun Heod2e75df2007-07-16 14:29:39 +0900977 /* do we need to kick the port? */
978 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
979 if (!busy && !force_restart)
980 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200981
Tejun Heod2e75df2007-07-16 14:29:39 +0900982 /* stop engine */
983 rc = ahci_stop_engine(ap);
984 if (rc)
985 goto out_restart;
986
987 /* need to do CLO? */
988 if (!busy) {
989 rc = 0;
990 goto out_restart;
991 }
992
993 if (!(hpriv->cap & HOST_CAP_CLO)) {
994 rc = -EOPNOTSUPP;
995 goto out_restart;
996 }
997
998 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200999 tmp = readl(port_mmio + PORT_CMD);
1000 tmp |= PORT_CMD_CLO;
1001 writel(tmp, port_mmio + PORT_CMD);
1002
Tejun Heod2e75df2007-07-16 14:29:39 +09001003 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001004 tmp = ata_wait_register(port_mmio + PORT_CMD,
1005 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1006 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001007 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001008
Tejun Heod2e75df2007-07-16 14:29:39 +09001009 /* restart engine */
1010 out_restart:
1011 ahci_start_engine(ap);
1012 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001013}
1014
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001015static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1016 struct ata_taskfile *tf, int is_cmd, u16 flags,
1017 unsigned long timeout_msec)
1018{
1019 const u32 cmd_fis_len = 5; /* five dwords */
1020 struct ahci_port_priv *pp = ap->private_data;
1021 void __iomem *port_mmio = ahci_port_base(ap);
1022 u8 *fis = pp->cmd_tbl;
1023 u32 tmp;
1024
1025 /* prep the command */
1026 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1027 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1028
1029 /* issue & wait */
1030 writel(1, port_mmio + PORT_CMD_ISSUE);
1031
1032 if (timeout_msec) {
1033 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1034 1, timeout_msec);
1035 if (tmp & 0x1) {
1036 ahci_kick_engine(ap, 1);
1037 return -EBUSY;
1038 }
1039 } else
1040 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1041
1042 return 0;
1043}
1044
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001045static int ahci_do_softreset(struct ata_port *ap, unsigned int *class,
1046 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001047{
Tejun Heo4658f792006-03-22 21:07:03 +09001048 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001049 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001050 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001051 int rc;
1052
1053 DPRINTK("ENTER\n");
1054
Tejun Heo81952c52006-05-15 20:57:47 +09001055 if (ata_port_offline(ap)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001056 DPRINTK("PHY reports no device\n");
1057 *class = ATA_DEV_NONE;
1058 return 0;
1059 }
1060
Tejun Heo4658f792006-03-22 21:07:03 +09001061 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001062 rc = ahci_kick_engine(ap, 1);
1063 if (rc)
1064 ata_port_printk(ap, KERN_WARNING,
1065 "failed to reset engine (errno=%d)", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001066
Tejun Heo3373efd2006-05-15 20:57:53 +09001067 ata_tf_init(ap->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001068
1069 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001070 msecs = 0;
1071 now = jiffies;
1072 if (time_after(now, deadline))
1073 msecs = jiffies_to_msecs(deadline - now);
1074
Tejun Heo4658f792006-03-22 21:07:03 +09001075 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001076 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001077 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001078 rc = -EIO;
1079 reason = "1st FIS failed";
1080 goto fail;
1081 }
1082
1083 /* spec says at least 5us, but be generous and sleep for 1ms */
1084 msleep(1);
1085
1086 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001087 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001088 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001089
1090 /* spec mandates ">= 2ms" before checking status.
1091 * We wait 150ms, because that was the magic delay used for
1092 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1093 * between when the ATA command register is written, and then
1094 * status is checked. Because waiting for "a while" before
1095 * checking status is fine, post SRST, we perform this magic
1096 * delay here as well.
1097 */
1098 msleep(150);
1099
Tejun Heo9b893912007-02-02 16:50:52 +09001100 rc = ata_wait_ready(ap, deadline);
1101 /* link occupied, -ENODEV too is an error */
1102 if (rc) {
1103 reason = "device not ready";
1104 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001105 }
Tejun Heo9b893912007-02-02 16:50:52 +09001106 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001107
1108 DPRINTK("EXIT, class=%u\n", *class);
1109 return 0;
1110
Tejun Heo4658f792006-03-22 21:07:03 +09001111 fail:
Tejun Heof15a1da2006-05-15 20:57:56 +09001112 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001113 return rc;
1114}
1115
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001116static int ahci_softreset(struct ata_port *ap, unsigned int *class,
1117 unsigned long deadline)
1118{
1119 return ahci_do_softreset(ap, class, 0, deadline);
1120}
1121
Tejun Heod4b2bab2007-02-02 16:50:52 +09001122static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1123 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001124{
Tejun Heo42969712006-05-31 18:28:18 +09001125 struct ahci_port_priv *pp = ap->private_data;
1126 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1127 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001128 int rc;
1129
1130 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131
Tejun Heo4447d352007-04-17 23:44:08 +09001132 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001133
1134 /* clear D2H reception area to properly wait for D2H FIS */
1135 ata_tf_init(ap->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001136 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001137 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001138
Tejun Heod4b2bab2007-02-02 16:50:52 +09001139 rc = sata_std_hardreset(ap, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001140
Tejun Heo4447d352007-04-17 23:44:08 +09001141 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Tejun Heo81952c52006-05-15 20:57:47 +09001143 if (rc == 0 && ata_port_online(ap))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001144 *class = ahci_dev_classify(ap);
1145 if (*class == ATA_DEV_UNKNOWN)
1146 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147
Tejun Heo4bd00f62006-02-11 16:26:02 +09001148 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1149 return rc;
1150}
1151
Tejun Heod4b2bab2007-02-02 16:50:52 +09001152static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1153 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001154{
Tejun Heoda3dbb12007-07-16 14:29:40 +09001155 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001156 int rc;
1157
1158 DPRINTK("ENTER\n");
1159
Tejun Heo4447d352007-04-17 23:44:08 +09001160 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001161
Tejun Heod4b2bab2007-02-02 16:50:52 +09001162 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1163 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001164
1165 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001166 ahci_scr_read(ap, SCR_ERROR, &serror);
1167 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001168
Tejun Heo4447d352007-04-17 23:44:08 +09001169 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001170
1171 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1172
1173 /* vt8251 doesn't clear BSY on signature FIS reception,
1174 * request follow-up softreset.
1175 */
1176 return rc ?: -EAGAIN;
1177}
1178
Tejun Heo4bd00f62006-02-11 16:26:02 +09001179static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1180{
Tejun Heo4447d352007-04-17 23:44:08 +09001181 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001182 u32 new_tmp, tmp;
1183
1184 ata_std_postreset(ap, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001185
1186 /* Make sure port's ATAPI bit is set appropriately */
1187 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001188 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001189 new_tmp |= PORT_CMD_ATAPI;
1190 else
1191 new_tmp &= ~PORT_CMD_ATAPI;
1192 if (new_tmp != tmp) {
1193 writel(new_tmp, port_mmio + PORT_CMD);
1194 readl(port_mmio + PORT_CMD); /* flush */
1195 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196}
1197
1198static u8 ahci_check_status(struct ata_port *ap)
1199{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001200 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201
1202 return readl(mmio + PORT_TFDATA) & 0xFF;
1203}
1204
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1206{
1207 struct ahci_port_priv *pp = ap->private_data;
1208 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1209
1210 ata_tf_from_fis(d2h_fis, tf);
1211}
1212
Tejun Heo12fad3f2006-05-15 21:03:55 +09001213static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001215 struct scatterlist *sg;
1216 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001217 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218
1219 VPRINTK("ENTER\n");
1220
1221 /*
1222 * Next, the S/G list.
1223 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001224 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001225 ata_for_each_sg(sg, qc) {
1226 dma_addr_t addr = sg_dma_address(sg);
1227 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001229 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1230 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1231 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -05001232
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001233 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001234 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001236
1237 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238}
1239
1240static void ahci_qc_prep(struct ata_queued_cmd *qc)
1241{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001242 struct ata_port *ap = qc->ap;
1243 struct ahci_port_priv *pp = ap->private_data;
Tejun Heocc9278e2006-02-10 17:25:47 +09001244 int is_atapi = is_atapi_taskfile(&qc->tf);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001245 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 u32 opts;
1247 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001248 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249
1250 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 * Fill in command table information. First, the header,
1252 * a SATA Register - Host to Device command FIS.
1253 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001254 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1255
Tejun Heo99771262007-07-16 14:29:38 +09001256 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001257 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001258 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1259 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001260 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261
Tejun Heocc9278e2006-02-10 17:25:47 +09001262 n_elem = 0;
1263 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001264 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265
Tejun Heocc9278e2006-02-10 17:25:47 +09001266 /*
1267 * Fill in command slot information.
1268 */
1269 opts = cmd_fis_len | n_elem << 16;
1270 if (qc->tf.flags & ATA_TFLAG_WRITE)
1271 opts |= AHCI_CMD_WRITE;
1272 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001273 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001274
Tejun Heo12fad3f2006-05-15 21:03:55 +09001275 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276}
1277
Tejun Heo78cd52d2006-05-15 20:58:29 +09001278static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279{
Tejun Heo78cd52d2006-05-15 20:58:29 +09001280 struct ahci_port_priv *pp = ap->private_data;
1281 struct ata_eh_info *ehi = &ap->eh_info;
1282 unsigned int err_mask = 0, action = 0;
1283 struct ata_queued_cmd *qc;
1284 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285
Tejun Heo78cd52d2006-05-15 20:58:29 +09001286 ata_ehi_clear_desc(ehi);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001287
Tejun Heo78cd52d2006-05-15 20:58:29 +09001288 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001289 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001290 ahci_scr_write(ap, SCR_ERROR, serror);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291
Tejun Heo78cd52d2006-05-15 20:58:29 +09001292 /* analyze @irq_stat */
1293 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294
Tejun Heo41669552006-11-29 11:33:14 +09001295 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1296 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1297 irq_stat &= ~PORT_IRQ_IF_ERR;
1298
Conke Hu55a61602007-03-27 18:33:05 +08001299 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001300 err_mask |= AC_ERR_DEV;
Conke Hu55a61602007-03-27 18:33:05 +08001301 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1302 serror &= ~SERR_INTERNAL;
1303 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001304
1305 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1306 err_mask |= AC_ERR_HOST_BUS;
1307 action |= ATA_EH_SOFTRESET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308 }
1309
Tejun Heo78cd52d2006-05-15 20:58:29 +09001310 if (irq_stat & PORT_IRQ_IF_ERR) {
1311 err_mask |= AC_ERR_ATA_BUS;
1312 action |= ATA_EH_SOFTRESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001313 ata_ehi_push_desc(ehi, "interface fatal error");
Tejun Heo78cd52d2006-05-15 20:58:29 +09001314 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315
Tejun Heo78cd52d2006-05-15 20:58:29 +09001316 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
Tejun Heo42969712006-05-31 18:28:18 +09001317 ata_ehi_hotplugged(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +09001318 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
Tejun Heo78cd52d2006-05-15 20:58:29 +09001319 "connection status changed" : "PHY RDY changed");
1320 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321
Tejun Heo78cd52d2006-05-15 20:58:29 +09001322 if (irq_stat & PORT_IRQ_UNK_FIS) {
1323 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324
Tejun Heo78cd52d2006-05-15 20:58:29 +09001325 err_mask |= AC_ERR_HSM;
1326 action |= ATA_EH_SOFTRESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001327 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
Tejun Heo78cd52d2006-05-15 20:58:29 +09001328 unk[0], unk[1], unk[2], unk[3]);
1329 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001330
Tejun Heo78cd52d2006-05-15 20:58:29 +09001331 /* okay, let's hand over to EH */
1332 ehi->serror |= serror;
1333 ehi->action |= action;
1334
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 qc = ata_qc_from_tag(ap, ap->active_tag);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001336 if (qc)
1337 qc->err_mask |= err_mask;
1338 else
1339 ehi->err_mask |= err_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340
Tejun Heo78cd52d2006-05-15 20:58:29 +09001341 if (irq_stat & PORT_IRQ_FREEZE)
1342 ata_port_freeze(ap);
1343 else
1344 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345}
1346
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001347static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348{
Tejun Heo4447d352007-04-17 23:44:08 +09001349 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001350 struct ata_eh_info *ehi = &ap->eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001351 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001352 u32 status, qc_active;
Tejun Heo0291f952007-01-25 19:16:28 +09001353 int rc, known_irq = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
1355 status = readl(port_mmio + PORT_IRQ_STAT);
1356 writel(status, port_mmio + PORT_IRQ_STAT);
1357
Tejun Heo78cd52d2006-05-15 20:58:29 +09001358 if (unlikely(status & PORT_IRQ_ERROR)) {
1359 ahci_error_intr(ap, status);
1360 return;
1361 }
1362
Tejun Heo12fad3f2006-05-15 21:03:55 +09001363 if (ap->sactive)
1364 qc_active = readl(port_mmio + PORT_SCR_ACT);
1365 else
1366 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1367
1368 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1369 if (rc > 0)
1370 return;
1371 if (rc < 0) {
1372 ehi->err_mask |= AC_ERR_HSM;
1373 ehi->action |= ATA_EH_SOFTRESET;
1374 ata_port_freeze(ap);
1375 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 }
1377
Tejun Heo2a3917a2006-05-15 20:58:30 +09001378 /* hmmm... a spurious interupt */
1379
Tejun Heo0291f952007-01-25 19:16:28 +09001380 /* if !NCQ, ignore. No modern ATA device has broken HSM
1381 * implementation for non-NCQ commands.
1382 */
1383 if (!ap->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001384 return;
1385
Tejun Heo0291f952007-01-25 19:16:28 +09001386 if (status & PORT_IRQ_D2H_REG_FIS) {
1387 if (!pp->ncq_saw_d2h)
1388 ata_port_printk(ap, KERN_INFO,
1389 "D2H reg with I during NCQ, "
1390 "this message won't be printed again\n");
1391 pp->ncq_saw_d2h = 1;
1392 known_irq = 1;
1393 }
Tejun Heo2a3917a2006-05-15 20:58:30 +09001394
Tejun Heo0291f952007-01-25 19:16:28 +09001395 if (status & PORT_IRQ_DMAS_FIS) {
1396 if (!pp->ncq_saw_dmas)
1397 ata_port_printk(ap, KERN_INFO,
1398 "DMAS FIS during NCQ, "
1399 "this message won't be printed again\n");
1400 pp->ncq_saw_dmas = 1;
1401 known_irq = 1;
1402 }
1403
Tejun Heoa2bbd0c2007-02-21 16:34:25 +09001404 if (status & PORT_IRQ_SDB_FIS) {
Al Viro04d4f7a2007-02-09 16:39:30 +00001405 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
Tejun Heo0291f952007-01-25 19:16:28 +09001406
Tejun Heoafb2d552007-02-27 13:24:19 +09001407 if (le32_to_cpu(f[1])) {
1408 /* SDB FIS containing spurious completions
1409 * might be dangerous, whine and fail commands
1410 * with HSM violation. EH will turn off NCQ
1411 * after several such failures.
1412 */
1413 ata_ehi_push_desc(ehi,
1414 "spurious completions during NCQ "
1415 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1416 readl(port_mmio + PORT_CMD_ISSUE),
1417 readl(port_mmio + PORT_SCR_ACT),
1418 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1419 ehi->err_mask |= AC_ERR_HSM;
1420 ehi->action |= ATA_EH_SOFTRESET;
1421 ata_port_freeze(ap);
1422 } else {
1423 if (!pp->ncq_saw_sdb)
1424 ata_port_printk(ap, KERN_INFO,
1425 "spurious SDB FIS %08x:%08x during NCQ, "
1426 "this message won't be printed again\n",
1427 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1428 pp->ncq_saw_sdb = 1;
1429 }
Tejun Heo0291f952007-01-25 19:16:28 +09001430 known_irq = 1;
1431 }
1432
1433 if (!known_irq)
Tejun Heo78cd52d2006-05-15 20:58:29 +09001434 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
Tejun Heo0291f952007-01-25 19:16:28 +09001435 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
Tejun Heo12fad3f2006-05-15 21:03:55 +09001436 status, ap->active_tag, ap->sactive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437}
1438
1439static void ahci_irq_clear(struct ata_port *ap)
1440{
1441 /* TODO */
1442}
1443
David Howells7d12e782006-10-05 14:55:46 +01001444static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445{
Jeff Garzikcca39742006-08-24 03:19:22 -04001446 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 struct ahci_host_priv *hpriv;
1448 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001449 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450 u32 irq_stat, irq_ack = 0;
1451
1452 VPRINTK("ENTER\n");
1453
Jeff Garzikcca39742006-08-24 03:19:22 -04001454 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001455 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001456
1457 /* sigh. 0xffffffff is a valid return from h/w */
1458 irq_stat = readl(mmio + HOST_IRQ_STAT);
1459 irq_stat &= hpriv->port_map;
1460 if (!irq_stat)
1461 return IRQ_NONE;
1462
Jeff Garzikcca39742006-08-24 03:19:22 -04001463 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
Jeff Garzikcca39742006-08-24 03:19:22 -04001465 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467
Jeff Garzik67846b32005-10-05 02:58:32 -04001468 if (!(irq_stat & (1 << i)))
1469 continue;
1470
Jeff Garzikcca39742006-08-24 03:19:22 -04001471 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001472 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001473 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001474 VPRINTK("port %u\n", i);
1475 } else {
1476 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001477 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001478 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001479 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001481
1482 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483 }
1484
1485 if (irq_ack) {
1486 writel(irq_ack, mmio + HOST_IRQ_STAT);
1487 handled = 1;
1488 }
1489
Jeff Garzikcca39742006-08-24 03:19:22 -04001490 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
1492 VPRINTK("EXIT\n");
1493
1494 return IRQ_RETVAL(handled);
1495}
1496
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001497static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498{
1499 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001500 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501
Tejun Heo12fad3f2006-05-15 21:03:55 +09001502 if (qc->tf.protocol == ATA_PROT_NCQ)
1503 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1504 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1506
1507 return 0;
1508}
1509
Tejun Heo78cd52d2006-05-15 20:58:29 +09001510static void ahci_freeze(struct ata_port *ap)
1511{
Tejun Heo4447d352007-04-17 23:44:08 +09001512 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001513
1514 /* turn IRQ off */
1515 writel(0, port_mmio + PORT_IRQ_MASK);
1516}
1517
1518static void ahci_thaw(struct ata_port *ap)
1519{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001520 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001521 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001522 u32 tmp;
1523
1524 /* clear IRQ */
1525 tmp = readl(port_mmio + PORT_IRQ_STAT);
1526 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001527 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001528
1529 /* turn IRQ back on */
1530 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1531}
1532
1533static void ahci_error_handler(struct ata_port *ap)
1534{
Tejun Heob51e9e52006-06-29 01:29:30 +09001535 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001536 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001537 ahci_stop_engine(ap);
1538 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001539 }
1540
1541 /* perform recovery */
Tejun Heo4aeb0e32006-11-01 17:58:33 +09001542 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
Tejun Heof5914a42006-05-31 18:27:48 +09001543 ahci_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001544}
1545
Tejun Heoad616ff2006-11-01 18:00:24 +09001546static void ahci_vt8251_error_handler(struct ata_port *ap)
1547{
Tejun Heoad616ff2006-11-01 18:00:24 +09001548 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1549 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001550 ahci_stop_engine(ap);
1551 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001552 }
1553
1554 /* perform recovery */
1555 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1556 ahci_postreset);
1557}
1558
Tejun Heo78cd52d2006-05-15 20:58:29 +09001559static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1560{
1561 struct ata_port *ap = qc->ap;
1562
Tejun Heod2e75df2007-07-16 14:29:39 +09001563 /* make DMA engine forget about the failed command */
1564 if (qc->flags & ATA_QCFLAG_FAILED)
1565 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001566}
1567
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001568static int ahci_port_resume(struct ata_port *ap)
1569{
1570 ahci_power_up(ap);
1571 ahci_start_port(ap);
1572
1573 return 0;
1574}
1575
Tejun Heo438ac6d2007-03-02 17:31:26 +09001576#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001577static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1578{
Tejun Heoc1332872006-07-26 15:59:26 +09001579 const char *emsg = NULL;
1580 int rc;
1581
Tejun Heo4447d352007-04-17 23:44:08 +09001582 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001583 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001584 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001585 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001586 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001587 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001588 }
1589
1590 return rc;
1591}
1592
Tejun Heoc1332872006-07-26 15:59:26 +09001593static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1594{
Jeff Garzikcca39742006-08-24 03:19:22 -04001595 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001596 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001597 u32 ctl;
1598
1599 if (mesg.event == PM_EVENT_SUSPEND) {
1600 /* AHCI spec rev1.1 section 8.3.3:
1601 * Software must disable interrupts prior to requesting a
1602 * transition of the HBA to D3 state.
1603 */
1604 ctl = readl(mmio + HOST_CTL);
1605 ctl &= ~HOST_IRQ_EN;
1606 writel(ctl, mmio + HOST_CTL);
1607 readl(mmio + HOST_CTL); /* flush */
1608 }
1609
1610 return ata_pci_device_suspend(pdev, mesg);
1611}
1612
1613static int ahci_pci_device_resume(struct pci_dev *pdev)
1614{
Jeff Garzikcca39742006-08-24 03:19:22 -04001615 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001616 int rc;
1617
Tejun Heo553c4aa2006-12-26 19:39:50 +09001618 rc = ata_pci_device_do_resume(pdev);
1619 if (rc)
1620 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09001621
1622 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09001623 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001624 if (rc)
1625 return rc;
1626
Tejun Heo4447d352007-04-17 23:44:08 +09001627 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001628 }
1629
Jeff Garzikcca39742006-08-24 03:19:22 -04001630 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001631
1632 return 0;
1633}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001634#endif
Tejun Heoc1332872006-07-26 15:59:26 +09001635
Tejun Heo254950c2006-07-26 15:59:25 +09001636static int ahci_port_start(struct ata_port *ap)
1637{
Jeff Garzikcca39742006-08-24 03:19:22 -04001638 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09001639 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09001640 void *mem;
1641 dma_addr_t mem_dma;
1642 int rc;
1643
Tejun Heo24dc5f32007-01-20 16:00:28 +09001644 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09001645 if (!pp)
1646 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001647
1648 rc = ata_pad_alloc(ap, dev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001649 if (rc)
Tejun Heo254950c2006-07-26 15:59:25 +09001650 return rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001651
Tejun Heo24dc5f32007-01-20 16:00:28 +09001652 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1653 GFP_KERNEL);
1654 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09001655 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001656 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1657
1658 /*
1659 * First item in chunk of DMA memory: 32-slot command table,
1660 * 32 bytes each in size
1661 */
1662 pp->cmd_slot = mem;
1663 pp->cmd_slot_dma = mem_dma;
1664
1665 mem += AHCI_CMD_SLOT_SZ;
1666 mem_dma += AHCI_CMD_SLOT_SZ;
1667
1668 /*
1669 * Second item: Received-FIS area
1670 */
1671 pp->rx_fis = mem;
1672 pp->rx_fis_dma = mem_dma;
1673
1674 mem += AHCI_RX_FIS_SZ;
1675 mem_dma += AHCI_RX_FIS_SZ;
1676
1677 /*
1678 * Third item: data area for storing a single command
1679 * and its scatter-gather table
1680 */
1681 pp->cmd_tbl = mem;
1682 pp->cmd_tbl_dma = mem_dma;
1683
1684 ap->private_data = pp;
1685
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001686 /* engage engines, captain */
1687 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09001688}
1689
1690static void ahci_port_stop(struct ata_port *ap)
1691{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001692 const char *emsg = NULL;
1693 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001694
Tejun Heo0be0aa92006-07-26 15:59:26 +09001695 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09001696 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001697 if (rc)
1698 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09001699}
1700
Tejun Heo4447d352007-04-17 23:44:08 +09001701static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705 if (using_dac &&
1706 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1707 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1708 if (rc) {
1709 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1710 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001711 dev_printk(KERN_ERR, &pdev->dev,
1712 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713 return rc;
1714 }
1715 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 } else {
1717 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1718 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001719 dev_printk(KERN_ERR, &pdev->dev,
1720 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 return rc;
1722 }
1723 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1724 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001725 dev_printk(KERN_ERR, &pdev->dev,
1726 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727 return rc;
1728 }
1729 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730 return 0;
1731}
1732
Tejun Heo4447d352007-04-17 23:44:08 +09001733static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734{
Tejun Heo4447d352007-04-17 23:44:08 +09001735 struct ahci_host_priv *hpriv = host->private_data;
1736 struct pci_dev *pdev = to_pci_dev(host->dev);
1737 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738 u32 vers, cap, impl, speed;
1739 const char *speed_s;
1740 u16 cc;
1741 const char *scc_s;
1742
1743 vers = readl(mmio + HOST_VERSION);
1744 cap = hpriv->cap;
1745 impl = hpriv->port_map;
1746
1747 speed = (cap >> 20) & 0xf;
1748 if (speed == 1)
1749 speed_s = "1.5";
1750 else if (speed == 2)
1751 speed_s = "3";
1752 else
1753 speed_s = "?";
1754
1755 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05001756 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001757 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05001758 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05001760 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761 scc_s = "RAID";
1762 else
1763 scc_s = "unknown";
1764
Jeff Garzika9524a72005-10-30 14:39:11 -05001765 dev_printk(KERN_INFO, &pdev->dev,
1766 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1768 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
1770 (vers >> 24) & 0xff,
1771 (vers >> 16) & 0xff,
1772 (vers >> 8) & 0xff,
1773 vers & 0xff,
1774
1775 ((cap >> 8) & 0x1f) + 1,
1776 (cap & 0x1f) + 1,
1777 speed_s,
1778 impl,
1779 scc_s);
1780
Jeff Garzika9524a72005-10-30 14:39:11 -05001781 dev_printk(KERN_INFO, &pdev->dev,
1782 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09001783 "%s%s%s%s%s%s%s"
1784 "%s%s%s%s%s%s%s\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786
1787 cap & (1 << 31) ? "64bit " : "",
1788 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09001789 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790 cap & (1 << 28) ? "ilck " : "",
1791 cap & (1 << 27) ? "stag " : "",
1792 cap & (1 << 26) ? "pm " : "",
1793 cap & (1 << 25) ? "led " : "",
1794
1795 cap & (1 << 24) ? "clo " : "",
1796 cap & (1 << 19) ? "nz " : "",
1797 cap & (1 << 18) ? "only " : "",
1798 cap & (1 << 17) ? "pmp " : "",
1799 cap & (1 << 15) ? "pio " : "",
1800 cap & (1 << 14) ? "slum " : "",
1801 cap & (1 << 13) ? "part " : ""
1802 );
1803}
1804
Tejun Heo24dc5f32007-01-20 16:00:28 +09001805static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806{
1807 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09001808 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1809 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001810 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001812 struct ata_host *host;
1813 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
1815 VPRINTK("ENTER\n");
1816
Tejun Heo12fad3f2006-05-15 21:03:55 +09001817 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1818
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001820 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821
Tejun Heo4447d352007-04-17 23:44:08 +09001822 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001823 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001824 if (rc)
1825 return rc;
1826
Tejun Heo0d5ff562007-02-01 15:06:36 +09001827 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1828 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001829 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001830 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001831 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832
Jeff Garzikcd70c262007-07-08 02:29:42 -04001833 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
Jeff Garzik907f4672005-05-12 15:03:42 -04001834 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835
Tejun Heo24dc5f32007-01-20 16:00:28 +09001836 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1837 if (!hpriv)
1838 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839
Tejun Heo4447d352007-04-17 23:44:08 +09001840 /* save initial config */
1841 ahci_save_initial_config(pdev, &pi, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842
Tejun Heo4447d352007-04-17 23:44:08 +09001843 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09001844 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09001845 pi.flags |= ATA_FLAG_NCQ;
1846
1847 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1848 if (!host)
1849 return -ENOMEM;
1850 host->iomap = pcim_iomap_table(pdev);
1851 host->private_data = hpriv;
1852
1853 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001854 struct ata_port *ap = host->ports[i];
1855 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001856
Jeff Garzikdab632e2007-05-28 08:33:01 -04001857 /* standard SATA port setup */
Tejun Heo203ef6c2007-07-16 14:29:40 +09001858 if (hpriv->port_map & (1 << i))
Tejun Heo4447d352007-04-17 23:44:08 +09001859 ap->ioaddr.cmd_addr = port_mmio;
Jeff Garzikdab632e2007-05-28 08:33:01 -04001860
1861 /* disabled/not-implemented port */
1862 else
1863 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001864 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865
1866 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001867 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001869 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870
Tejun Heo4447d352007-04-17 23:44:08 +09001871 rc = ahci_reset_controller(host);
1872 if (rc)
1873 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001874
Tejun Heo4447d352007-04-17 23:44:08 +09001875 ahci_init_controller(host);
1876 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877
Tejun Heo4447d352007-04-17 23:44:08 +09001878 pci_set_master(pdev);
1879 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1880 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001881}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
1883static int __init ahci_init(void)
1884{
Pavel Roskinb7887192006-08-10 18:13:18 +09001885 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886}
1887
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888static void __exit ahci_exit(void)
1889{
1890 pci_unregister_driver(&ahci_pci_driver);
1891}
1892
1893
1894MODULE_AUTHOR("Jeff Garzik");
1895MODULE_DESCRIPTION("AHCI SATA low-level driver");
1896MODULE_LICENSE("GPL");
1897MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001898MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899
1900module_init(ahci_init);
1901module_exit(ahci_exit);