blob: 9b765107e15cf8a17cc4803dfabb1c9ada64b337 [file] [log] [blame]
Alan Jenkins9e1b9b82009-11-07 21:03:54 +00001config SYMBOL_PREFIX
2 string
3 default "_"
4
Bryan Wu1394f032007-05-06 14:50:22 -07005config MMU
Mike Frysingerbac7d892009-06-07 03:46:06 -04006 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -07007
8config FPU
Mike Frysingerbac7d892009-06-07 03:46:06 -04009 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070010
11config RWSEM_GENERIC_SPINLOCK
Mike Frysingerbac7d892009-06-07 03:46:06 -040012 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070013
14config RWSEM_XCHGADD_ALGORITHM
Mike Frysingerbac7d892009-06-07 03:46:06 -040015 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070016
17config BLACKFIN
Mike Frysingerbac7d892009-06-07 03:46:06 -040018 def_bool y
Mike Frysinger652afdc2010-01-25 22:12:32 +000019 select HAVE_ARCH_KGDB
Mike Frysingere8f263d2010-01-26 07:33:53 +000020 select HAVE_ARCH_TRACEHOOK
Mike Frysingerf5074422010-07-21 09:13:02 -040021 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
Mike Frysinger1ee76d72009-06-10 04:45:29 -040023 select HAVE_FUNCTION_GRAPH_TRACER
Mike Frysinger1c873be2009-06-09 07:25:09 -040024 select HAVE_FUNCTION_TRACER
Mike Frysingeraebfef02010-01-22 07:35:20 -050025 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
Sam Ravnborgec7748b2008-02-09 10:46:40 +010026 select HAVE_IDE
Mike Frysinger7db79172011-05-06 11:47:52 -040027 select HAVE_IRQ_WORK
Barry Songd86bfb12010-01-07 04:11:17 +000028 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
Mike Frysinger67df6cc2010-07-19 05:37:54 +000031 select HAVE_KERNEL_LZO if RAMKERNEL
Mathieu Desnoyers42d4b832008-02-02 15:10:34 -050032 select HAVE_OPROFILE
Mike Frysinger7db79172011-05-06 11:47:52 -040033 select HAVE_PERF_EVENTS
Mark Brown7563bbf2012-04-15 10:52:54 +010034 select ARCH_HAVE_CUSTOM_GPIO_H
Michael Hennericha4f0b32c2008-11-18 17:48:22 +080035 select ARCH_WANT_OPTIONAL_GPIOLIB
Thomas Gleixner7b028862011-01-19 20:29:58 +010036 select HAVE_GENERIC_HARDIRQS
Mike Frysingerbee18be2011-03-21 02:39:10 -040037 select GENERIC_ATOMIC64
Thomas Gleixner7b028862011-01-19 20:29:58 +010038 select GENERIC_IRQ_PROBE
39 select IRQ_PER_CPU if SMP
Cong Wangd314d742012-03-23 15:01:51 -070040 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
Thomas Gleixner6bba2682012-04-20 13:05:53 +000041 select GENERIC_SMP_IDLE_THREAD
Anna-Maria Gleixnerdfbaec02012-05-18 16:45:45 +000042 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
Bryan Wu1394f032007-05-06 14:50:22 -070043
Mike Frysingerddf9dda2009-06-13 07:42:58 -040044config GENERIC_CSUM
45 def_bool y
46
Mike Frysinger70f12562009-06-07 17:18:25 -040047config GENERIC_BUG
48 def_bool y
49 depends on BUG
50
Aubrey Lie3defff2007-05-21 18:09:11 +080051config ZONE_DMA
Mike Frysingerbac7d892009-06-07 03:46:06 -040052 def_bool y
Aubrey Lie3defff2007-05-21 18:09:11 +080053
Michael Hennerichb2d15832007-07-24 15:46:36 +080054config GENERIC_GPIO
Mike Frysingerbac7d892009-06-07 03:46:06 -040055 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070056
57config FORCE_MAX_ZONEORDER
58 int
59 default "14"
60
61config GENERIC_CALIBRATE_DELAY
Mike Frysingerbac7d892009-06-07 03:46:06 -040062 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070063
Mike Frysinger6fa68e72009-06-08 18:45:01 -040064config LOCKDEP_SUPPORT
65 def_bool y
66
Mike Frysingerc7b412f2009-06-08 18:44:45 -040067config STACKTRACE_SUPPORT
68 def_bool y
69
Mike Frysinger8f860012009-06-08 12:49:48 -040070config TRACE_IRQFLAGS_SUPPORT
71 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070072
Bryan Wu1394f032007-05-06 14:50:22 -070073source "init/Kconfig"
Matt Helsleydc52ddc2008-10-18 20:27:21 -070074
Bryan Wu1394f032007-05-06 14:50:22 -070075source "kernel/Kconfig.preempt"
76
Matt Helsleydc52ddc2008-10-18 20:27:21 -070077source "kernel/Kconfig.freezer"
78
Bryan Wu1394f032007-05-06 14:50:22 -070079menu "Blackfin Processor Options"
80
81comment "Processor and Board Settings"
82
83choice
84 prompt "CPU"
85 default BF533
86
Bryan Wu2f6f4bc2008-11-18 17:48:21 +080087config BF512
88 bool "BF512"
89 help
90 BF512 Processor Support.
91
92config BF514
93 bool "BF514"
94 help
95 BF514 Processor Support.
96
97config BF516
98 bool "BF516"
99 help
100 BF516 Processor Support.
101
102config BF518
103 bool "BF518"
104 help
105 BF518 Processor Support.
106
Michael Hennerich59003142007-10-21 16:54:27 +0800107config BF522
108 bool "BF522"
109 help
110 BF522 Processor Support.
111
Mike Frysinger1545a112007-12-24 16:54:48 +0800112config BF523
113 bool "BF523"
114 help
115 BF523 Processor Support.
116
117config BF524
118 bool "BF524"
119 help
120 BF524 Processor Support.
121
Michael Hennerich59003142007-10-21 16:54:27 +0800122config BF525
123 bool "BF525"
124 help
125 BF525 Processor Support.
126
Mike Frysinger1545a112007-12-24 16:54:48 +0800127config BF526
128 bool "BF526"
129 help
130 BF526 Processor Support.
131
Michael Hennerich59003142007-10-21 16:54:27 +0800132config BF527
133 bool "BF527"
134 help
135 BF527 Processor Support.
136
Bryan Wu1394f032007-05-06 14:50:22 -0700137config BF531
138 bool "BF531"
139 help
140 BF531 Processor Support.
141
142config BF532
143 bool "BF532"
144 help
145 BF532 Processor Support.
146
147config BF533
148 bool "BF533"
149 help
150 BF533 Processor Support.
151
152config BF534
153 bool "BF534"
154 help
155 BF534 Processor Support.
156
157config BF536
158 bool "BF536"
159 help
160 BF536 Processor Support.
161
162config BF537
163 bool "BF537"
164 help
165 BF537 Processor Support.
166
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800167config BF538
168 bool "BF538"
169 help
170 BF538 Processor Support.
171
172config BF539
173 bool "BF539"
174 help
175 BF539 Processor Support.
176
Mike Frysinger5df326a2009-11-16 23:49:41 +0000177config BF542_std
Roy Huang24a07a12007-07-12 22:41:45 +0800178 bool "BF542"
179 help
180 BF542 Processor Support.
181
Mike Frysinger2f89c062009-02-04 16:49:45 +0800182config BF542M
183 bool "BF542m"
184 help
185 BF542 Processor Support.
186
Mike Frysinger5df326a2009-11-16 23:49:41 +0000187config BF544_std
Roy Huang24a07a12007-07-12 22:41:45 +0800188 bool "BF544"
189 help
190 BF544 Processor Support.
191
Mike Frysinger2f89c062009-02-04 16:49:45 +0800192config BF544M
193 bool "BF544m"
194 help
195 BF544 Processor Support.
196
Mike Frysinger5df326a2009-11-16 23:49:41 +0000197config BF547_std
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800198 bool "BF547"
199 help
200 BF547 Processor Support.
201
Mike Frysinger2f89c062009-02-04 16:49:45 +0800202config BF547M
203 bool "BF547m"
204 help
205 BF547 Processor Support.
206
Mike Frysinger5df326a2009-11-16 23:49:41 +0000207config BF548_std
Roy Huang24a07a12007-07-12 22:41:45 +0800208 bool "BF548"
209 help
210 BF548 Processor Support.
211
Mike Frysinger2f89c062009-02-04 16:49:45 +0800212config BF548M
213 bool "BF548m"
214 help
215 BF548 Processor Support.
216
Mike Frysinger5df326a2009-11-16 23:49:41 +0000217config BF549_std
Roy Huang24a07a12007-07-12 22:41:45 +0800218 bool "BF549"
219 help
220 BF549 Processor Support.
221
Mike Frysinger2f89c062009-02-04 16:49:45 +0800222config BF549M
223 bool "BF549m"
224 help
225 BF549 Processor Support.
226
Bryan Wu1394f032007-05-06 14:50:22 -0700227config BF561
228 bool "BF561"
229 help
Mike Frysingercd88b4d2008-10-09 12:03:22 +0800230 BF561 Processor Support.
Bryan Wu1394f032007-05-06 14:50:22 -0700231
Bob Liub5affb02012-05-16 17:37:24 +0800232config BF609
233 bool "BF609"
234 select CLKDEV_LOOKUP
235 help
236 BF609 Processor Support.
237
Bryan Wu1394f032007-05-06 14:50:22 -0700238endchoice
239
Graf Yang46fa5ee2009-01-07 23:14:39 +0800240config SMP
241 depends on BF561
Yi Li0d152c22009-12-28 10:21:49 +0000242 select TICKSOURCE_CORETMR
Graf Yang46fa5ee2009-01-07 23:14:39 +0800243 bool "Symmetric multi-processing support"
244 ---help---
245 This enables support for systems with more than one CPU,
246 like the dual core BF561. If you have a system with only one
247 CPU, say N. If you have a system with more than one CPU, say Y.
248
249 If you don't know what to do here, say N.
250
251config NR_CPUS
252 int
253 depends on SMP
254 default 2 if BF561
255
Graf Yang0b39db22009-12-28 11:13:51 +0000256config HOTPLUG_CPU
257 bool "Support for hot-pluggable CPUs"
258 depends on SMP && HOTPLUG
259 default y
260
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800261config BF_REV_MIN
262 int
Bob Liub5affb02012-05-16 17:37:24 +0800263 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800264 default 2 if (BF537 || BF536 || BF534)
Mike Frysinger2f89c062009-02-04 16:49:45 +0800265 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800266 default 4 if (BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800267
268config BF_REV_MAX
269 int
Bob Liub5affb02012-05-16 17:37:24 +0800270 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
Mike Frysinger2f89c062009-02-04 16:49:45 +0800271 default 3 if (BF537 || BF536 || BF534 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800272 default 5 if (BF561 || BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800273 default 6 if (BF533 || BF532 || BF531)
274
Bryan Wu1394f032007-05-06 14:50:22 -0700275choice
276 prompt "Silicon Rev"
Bob Liub5affb02012-05-16 17:37:24 +0800277 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
Mike Frysingerf8b55652009-04-13 21:58:34 +0000278 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
Mike Frysinger2f89c062009-02-04 16:49:45 +0800279 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
Roy Huang24a07a12007-07-12 22:41:45 +0800280
281config BF_REV_0_0
282 bool "0.0"
Bob Liub5affb02012-05-16 17:37:24 +0800283 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
Michael Hennerich59003142007-10-21 16:54:27 +0800284
285config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800286 bool "0.1"
Mike Frysinger3d15f302009-06-15 16:21:44 +0000287 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700288
289config BF_REV_0_2
290 bool "0.2"
Mike Frysinger8060bb62010-08-16 16:18:12 +0000291 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700292
293config BF_REV_0_3
294 bool "0.3"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800295 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
Bryan Wu1394f032007-05-06 14:50:22 -0700296
297config BF_REV_0_4
298 bool "0.4"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700300
301config BF_REV_0_5
302 bool "0.5"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800303 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700304
Mike Frysinger49f72532008-10-09 12:06:27 +0800305config BF_REV_0_6
306 bool "0.6"
307 depends on (BF533 || BF532 || BF531)
308
Jie Zhangde3025f2007-06-25 18:04:12 +0800309config BF_REV_ANY
310 bool "any"
311
312config BF_REV_NONE
313 bool "none"
314
Bryan Wu1394f032007-05-06 14:50:22 -0700315endchoice
316
Roy Huang24a07a12007-07-12 22:41:45 +0800317config BF53x
318 bool
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
320 default y
321
Bryan Wu1394f032007-05-06 14:50:22 -0700322config MEM_MT48LC64M4A2FB_7E
323 bool
324 depends on (BFIN533_STAMP)
325 default y
326
327config MEM_MT48LC16M16A2TG_75
328 bool
329 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Harald Krapfenbauer60584342009-09-10 15:12:08 +0000330 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
331 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
332 || BFIN527_BLUETECHNIX_CM)
Bryan Wu1394f032007-05-06 14:50:22 -0700333 default y
334
335config MEM_MT48LC32M8A2_75
336 bool
Mike Frysinger084f9eb2010-05-20 04:26:54 +0000337 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
Bryan Wu1394f032007-05-06 14:50:22 -0700338 default y
339
340config MEM_MT48LC8M32B2B5_7
341 bool
342 depends on (BFIN561_BLUETECHNIX_CM)
343 default y
344
Michael Hennerich59003142007-10-21 16:54:27 +0800345config MEM_MT48LC32M16A2TG_75
346 bool
Michael Hennerich8effc4a2010-06-15 09:51:05 +0000347 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
Michael Hennerich59003142007-10-21 16:54:27 +0800348 default y
349
Graf Yangee48efb2009-06-18 04:32:04 +0000350config MEM_MT48H32M16LFCJ_75
351 bool
352 depends on (BFIN526_EZBRD)
353 default y
354
Bob Liuf82f16d2012-07-23 10:47:48 +0800355config MEM_MT47H64M16
356 bool
357 depends on (BFIN609_EZKIT)
358 default y
359
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800360source "arch/blackfin/mach-bf518/Kconfig"
Michael Hennerich59003142007-10-21 16:54:27 +0800361source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700362source "arch/blackfin/mach-bf533/Kconfig"
363source "arch/blackfin/mach-bf561/Kconfig"
364source "arch/blackfin/mach-bf537/Kconfig"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800365source "arch/blackfin/mach-bf538/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800366source "arch/blackfin/mach-bf548/Kconfig"
Bob Liub5affb02012-05-16 17:37:24 +0800367source "arch/blackfin/mach-bf609/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700368
369menu "Board customizations"
370
371config CMDLINE_BOOL
372 bool "Default bootloader kernel arguments"
373
374config CMDLINE
375 string "Initial kernel command string"
376 depends on CMDLINE_BOOL
377 default "console=ttyBF0,57600"
378 help
379 If you don't have a boot loader capable of passing a command line string
380 to the kernel, you may specify one here. As a minimum, you should specify
381 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
382
Mike Frysinger5f004c22008-04-25 02:11:24 +0800383config BOOT_LOAD
384 hex "Kernel load address for booting"
385 default "0x1000"
386 range 0x1000 0x20000000
387 help
388 This option allows you to set the load address of the kernel.
389 This can be useful if you are on a board which has a small amount
390 of memory or you wish to reserve some memory at the beginning of
391 the address space.
392
393 Note that you need to keep this value above 4k (0x1000) as this
394 memory region is used to capture NULL pointer references as well
395 as some core kernel functions.
396
Bob Liub5affb02012-05-16 17:37:24 +0800397config PHY_RAM_BASE_ADDRESS
398 hex "Physical RAM Base"
399 default 0x0
400 help
401 set BF609 FPGA physical SRAM base address
402
Michael Hennerich8cc71172008-10-13 14:45:06 +0800403config ROM_BASE
404 hex "Kernel ROM Base"
Mike Frysinger86249912008-11-18 17:48:22 +0800405 depends on ROMKERNEL
Barry Songd86bfb12010-01-07 04:11:17 +0000406 default "0x20040040"
Bob Liu30036682012-05-30 15:30:27 +0800407 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
Michael Hennerich8cc71172008-10-13 14:45:06 +0800408 range 0x20000000 0x30000000 if (BF54x || BF561)
Bob Liu30036682012-05-30 15:30:27 +0800409 range 0xB0000000 0xC0000000 if (BF60x)
Michael Hennerich8cc71172008-10-13 14:45:06 +0800410 help
Barry Songd86bfb12010-01-07 04:11:17 +0000411 Make sure your ROM base does not include any file-header
412 information that is prepended to the kernel.
413
414 For example, the bootable U-Boot format (created with
415 mkimage) has a 64 byte header (0x40). So while the image
416 you write to flash might start at say 0x20080000, you have
417 to add 0x40 to get the kernel's ROM base as it will come
418 after the header.
Michael Hennerich8cc71172008-10-13 14:45:06 +0800419
Robin Getzf16295e2007-08-03 18:07:17 +0800420comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700421
422config CLKIN_HZ
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800423 int "Frequency of the crystal on the board in Hz"
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800424 default "10000000" if BFIN532_IP0X
Mike Frysingerd0cb9b42009-06-11 21:52:35 +0000425 default "11059200" if BFIN533_STAMP
426 default "24576000" if PNAV10
427 default "25000000" # most people use this
428 default "27000000" if BFIN533_EZKIT
429 default "30000000" if BFIN561_EZKIT
Michael Hennerich8effc4a2010-06-15 09:51:05 +0000430 default "24000000" if BFIN527_AD7160EVAL
Bryan Wu1394f032007-05-06 14:50:22 -0700431 help
432 The frequency of CLKIN crystal oscillator on the board in Hz.
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800433 Warning: This value should match the crystal on the board. Otherwise,
434 peripherals won't work properly.
Bryan Wu1394f032007-05-06 14:50:22 -0700435
Robin Getzf16295e2007-08-03 18:07:17 +0800436config BFIN_KERNEL_CLOCK
437 bool "Re-program Clocks while Kernel boots?"
438 default n
439 help
440 This option decides if kernel clocks are re-programed from the
441 bootloader settings. If the clocks are not set, the SDRAM settings
442 are also not changed, and the Bootloader does 100% of the hardware
443 configuration.
444
445config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800446 bool "Bypass PLL"
Bob Liu7c141c12012-05-17 17:15:40 +0800447 depends on BFIN_KERNEL_CLOCK && (!BF60x)
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800448 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800449
450config CLKIN_HALF
451 bool "Half Clock In"
452 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
453 default n
454 help
455 If this is set the clock will be divided by 2, before it goes to the PLL.
456
457config VCO_MULT
458 int "VCO Multiplier"
459 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
460 range 1 64
461 default "22" if BFIN533_EZKIT
462 default "45" if BFIN533_STAMP
Michael Hennerich6924dfb2009-12-07 13:41:28 +0000463 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800464 default "22" if BFIN533_BLUETECHNIX_CM
Harald Krapfenbauer60584342009-09-10 15:12:08 +0000465 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
Bob Liu7c141c12012-05-17 17:15:40 +0800466 default "20" if (BFIN561_EZKIT || BF609)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800467 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
Michael Hennerich8effc4a2010-06-15 09:51:05 +0000468 default "25" if BFIN527_AD7160EVAL
Robin Getzf16295e2007-08-03 18:07:17 +0800469 help
470 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
471 PLL Frequency = (Crystal Frequency) * (this setting)
472
473choice
474 prompt "Core Clock Divider"
475 depends on BFIN_KERNEL_CLOCK
476 default CCLK_DIV_1
477 help
478 This sets the frequency of the core. It can be 1, 2, 4 or 8
479 Core Frequency = (PLL frequency) / (this setting)
480
481config CCLK_DIV_1
482 bool "1"
483
484config CCLK_DIV_2
485 bool "2"
486
487config CCLK_DIV_4
488 bool "4"
489
490config CCLK_DIV_8
491 bool "8"
492endchoice
493
494config SCLK_DIV
495 int "System Clock Divider"
496 depends on BFIN_KERNEL_CLOCK
497 range 1 15
Bob Liu7c141c12012-05-17 17:15:40 +0800498 default 4
Robin Getzf16295e2007-08-03 18:07:17 +0800499 help
Bob Liu7c141c12012-05-17 17:15:40 +0800500 This sets the frequency of the system clock (including SDRAM or DDR) on
501 !BF60x else it set the clock for system buses and provides the
502 source from which SCLK0 and SCLK1 are derived.
Robin Getzf16295e2007-08-03 18:07:17 +0800503 This can be between 1 and 15
504 System Clock = (PLL frequency) / (this setting)
505
Bob Liu7c141c12012-05-17 17:15:40 +0800506config SCLK0_DIV
507 int "System Clock0 Divider"
508 depends on BFIN_KERNEL_CLOCK && BF60x
509 range 1 15
510 default 1
511 help
512 This sets the frequency of the system clock0 for PVP and all other
513 peripherals not clocked by SCLK1.
514 This can be between 1 and 15
515 System Clock0 = (System Clock) / (this setting)
516
517config SCLK1_DIV
518 int "System Clock1 Divider"
519 depends on BFIN_KERNEL_CLOCK && BF60x
520 range 1 15
521 default 1
522 help
523 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
524 This can be between 1 and 15
525 System Clock1 = (System Clock) / (this setting)
526
527config DCLK_DIV
528 int "DDR Clock Divider"
529 depends on BFIN_KERNEL_CLOCK && BF60x
530 range 1 15
531 default 2
532 help
533 This sets the frequency of the DDR memory.
534 This can be between 1 and 15
535 DDR Clock = (PLL frequency) / (this setting)
536
Mike Frysinger5f004c22008-04-25 02:11:24 +0800537choice
538 prompt "DDR SDRAM Chip Type"
539 depends on BFIN_KERNEL_CLOCK
540 depends on BF54x
541 default MEM_MT46V32M16_5B
542
543config MEM_MT46V32M16_6T
544 bool "MT46V32M16_6T"
545
546config MEM_MT46V32M16_5B
547 bool "MT46V32M16_5B"
548endchoice
549
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800550choice
551 prompt "DDR/SDRAM Timing"
Bob Liu7c141c12012-05-17 17:15:40 +0800552 depends on BFIN_KERNEL_CLOCK && !BF60x
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800553 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
554 help
555 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
556 The calculated SDRAM timing parameters may not be 100%
557 accurate - This option is therefore marked experimental.
558
559config BFIN_KERNEL_CLOCK_MEMINIT_CALC
560 bool "Calculate Timings (EXPERIMENTAL)"
561 depends on EXPERIMENTAL
562
563config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
564 bool "Provide accurate Timings based on target SCLK"
565 help
566 Please consult the Blackfin Hardware Reference Manuals as well
567 as the memory device datasheet.
568 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
569endchoice
570
571menu "Memory Init Control"
572 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
573
574config MEM_DDRCTL0
575 depends on BF54x
576 hex "DDRCTL0"
577 default 0x0
578
579config MEM_DDRCTL1
580 depends on BF54x
581 hex "DDRCTL1"
582 default 0x0
583
584config MEM_DDRCTL2
585 depends on BF54x
586 hex "DDRCTL2"
587 default 0x0
588
589config MEM_EBIU_DDRQUE
590 depends on BF54x
591 hex "DDRQUE"
592 default 0x0
593
594config MEM_SDRRC
595 depends on !BF54x
596 hex "SDRRC"
597 default 0x0
598
599config MEM_SDGCTL
600 depends on !BF54x
601 hex "SDGCTL"
602 default 0x0
603endmenu
604
Robin Getzf16295e2007-08-03 18:07:17 +0800605#
606# Max & Min Speeds for various Chips
607#
608config MAX_VCO_HZ
609 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800610 default 400000000 if BF512
611 default 400000000 if BF514
612 default 400000000 if BF516
613 default 400000000 if BF518
Mike Frysinger7b062632009-08-11 21:27:09 +0000614 default 400000000 if BF522
615 default 600000000 if BF523
Mike Frysinger1545a112007-12-24 16:54:48 +0800616 default 400000000 if BF524
Robin Getzf16295e2007-08-03 18:07:17 +0800617 default 600000000 if BF525
Mike Frysinger1545a112007-12-24 16:54:48 +0800618 default 400000000 if BF526
Robin Getzf16295e2007-08-03 18:07:17 +0800619 default 600000000 if BF527
620 default 400000000 if BF531
621 default 400000000 if BF532
622 default 750000000 if BF533
623 default 500000000 if BF534
624 default 400000000 if BF536
625 default 600000000 if BF537
Robin Getzf72eecb2007-11-21 16:29:20 +0800626 default 533333333 if BF538
627 default 533333333 if BF539
Robin Getzf16295e2007-08-03 18:07:17 +0800628 default 600000000 if BF542
Robin Getzf72eecb2007-11-21 16:29:20 +0800629 default 533333333 if BF544
Mike Frysinger1545a112007-12-24 16:54:48 +0800630 default 600000000 if BF547
631 default 600000000 if BF548
Robin Getzf72eecb2007-11-21 16:29:20 +0800632 default 533333333 if BF549
Robin Getzf16295e2007-08-03 18:07:17 +0800633 default 600000000 if BF561
Bob Liu7c141c12012-05-17 17:15:40 +0800634 default 800000000 if BF609
Robin Getzf16295e2007-08-03 18:07:17 +0800635
636config MIN_VCO_HZ
637 int
638 default 50000000
639
640config MAX_SCLK_HZ
641 int
Bob Liu7c141c12012-05-17 17:15:40 +0800642 default 200000000 if BF609
Robin Getzf72eecb2007-11-21 16:29:20 +0800643 default 133333333
Robin Getzf16295e2007-08-03 18:07:17 +0800644
645config MIN_SCLK_HZ
646 int
647 default 27000000
648
649comment "Kernel Timer/Scheduler"
650
651source kernel/Kconfig.hz
652
Anna-Maria Gleixnerdfbaec02012-05-18 16:45:45 +0000653config SET_GENERIC_CLOCKEVENTS
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800654 bool "Generic clock events"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800655 default y
Anna-Maria Gleixnerdfbaec02012-05-18 16:45:45 +0000656 select GENERIC_CLOCKEVENTS
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800657
Yi Li0d152c22009-12-28 10:21:49 +0000658menu "Clock event device"
Graf Yang1fa9be72009-05-15 11:01:59 +0000659 depends on GENERIC_CLOCKEVENTS
Graf Yang1fa9be72009-05-15 11:01:59 +0000660config TICKSOURCE_GPTMR0
Yi Li0d152c22009-12-28 10:21:49 +0000661 bool "GPTimer0"
662 depends on !SMP
Graf Yang1fa9be72009-05-15 11:01:59 +0000663 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000664
665config TICKSOURCE_CORETMR
Yi Li0d152c22009-12-28 10:21:49 +0000666 bool "Core timer"
667 default y
668endmenu
Graf Yang1fa9be72009-05-15 11:01:59 +0000669
Yi Li0d152c22009-12-28 10:21:49 +0000670menu "Clock souce"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800671 depends on GENERIC_CLOCKEVENTS
Yi Li0d152c22009-12-28 10:21:49 +0000672config CYCLES_CLOCKSOURCE
673 bool "CYCLES"
674 default y
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800675 depends on !BFIN_SCRATCH_REG_CYCLES
Graf Yang1fa9be72009-05-15 11:01:59 +0000676 depends on !SMP
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800677 help
678 If you say Y here, you will enable support for using the 'cycles'
679 registers as a clock source. Doing so means you will be unable to
680 safely write to the 'cycles' register during runtime. You will
681 still be able to read it (such as for performance monitoring), but
682 writing the registers will most likely crash the kernel.
683
Graf Yang1fa9be72009-05-15 11:01:59 +0000684config GPTMR0_CLOCKSOURCE
Yi Li0d152c22009-12-28 10:21:49 +0000685 bool "GPTimer0"
Mike Frysinger3aca47c2009-06-18 19:40:47 +0000686 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000687 depends on !TICKSOURCE_GPTMR0
Yi Li0d152c22009-12-28 10:21:49 +0000688endmenu
Graf Yang1fa9be72009-05-15 11:01:59 +0000689
Mike Frysinger5f004c22008-04-25 02:11:24 +0800690comment "Misc"
Sonic Zhang971d5bc2008-01-27 16:32:31 +0800691
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800692choice
693 prompt "Blackfin Exception Scratch Register"
694 default BFIN_SCRATCH_REG_RETN
695 help
696 Select the resource to reserve for the Exception handler:
697 - RETN: Non-Maskable Interrupt (NMI)
698 - RETE: Exception Return (JTAG/ICE)
699 - CYCLES: Performance counter
700
701 If you are unsure, please select "RETN".
702
703config BFIN_SCRATCH_REG_RETN
704 bool "RETN"
705 help
706 Use the RETN register in the Blackfin exception handler
707 as a stack scratch register. This means you cannot
708 safely use NMI on the Blackfin while running Linux, but
709 you can debug the system with a JTAG ICE and use the
710 CYCLES performance registers.
711
712 If you are unsure, please select "RETN".
713
714config BFIN_SCRATCH_REG_RETE
715 bool "RETE"
716 help
717 Use the RETE register in the Blackfin exception handler
718 as a stack scratch register. This means you cannot
719 safely use a JTAG ICE while debugging a Blackfin board,
720 but you can safely use the CYCLES performance registers
721 and the NMI.
722
723 If you are unsure, please select "RETN".
724
725config BFIN_SCRATCH_REG_CYCLES
726 bool "CYCLES"
727 help
728 Use the CYCLES register in the Blackfin exception handler
729 as a stack scratch register. This means you cannot
730 safely use the CYCLES performance registers on a Blackfin
731 board at anytime, but you can debug the system with a JTAG
732 ICE and use the NMI.
733
734 If you are unsure, please select "RETN".
735
736endchoice
737
Bryan Wu1394f032007-05-06 14:50:22 -0700738endmenu
739
740
741menu "Blackfin Kernel Optimizations"
742
Bryan Wu1394f032007-05-06 14:50:22 -0700743comment "Memory Optimizations"
744
745config I_ENTRY_L1
746 bool "Locate interrupt entry code in L1 Memory"
747 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500748 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700749 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200750 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
751 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700752
753config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200754 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700755 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500756 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700757 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200758 If enabled, the entire ASM lowlevel exception and interrupt entry code
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800759 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200760 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700761
762config DO_IRQ_L1
763 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
764 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500765 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700766 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200767 If enabled, the frequently called do_irq dispatcher function is linked
768 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700769
770config CORE_TIMER_IRQ_L1
771 bool "Locate frequently called timer_interrupt() function in L1 Memory"
772 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500773 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700774 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200775 If enabled, the frequently called timer_interrupt() function is linked
776 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700777
778config IDLE_L1
779 bool "Locate frequently idle function in L1 Memory"
780 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500781 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700782 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200783 If enabled, the frequently called idle function is linked
784 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700785
786config SCHEDULE_L1
787 bool "Locate kernel schedule function in L1 Memory"
788 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500789 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700790 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200791 If enabled, the frequently called kernel schedule is linked
792 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700793
794config ARITHMETIC_OPS_L1
795 bool "Locate kernel owned arithmetic functions in L1 Memory"
796 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500797 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700798 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200799 If enabled, arithmetic functions are linked
800 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700801
802config ACCESS_OK_L1
803 bool "Locate access_ok function in L1 Memory"
804 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500805 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700806 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200807 If enabled, the access_ok function is linked
808 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700809
810config MEMSET_L1
811 bool "Locate memset function in L1 Memory"
812 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500813 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700814 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200815 If enabled, the memset function is linked
816 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700817
818config MEMCPY_L1
819 bool "Locate memcpy function in L1 Memory"
820 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500821 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700822 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200823 If enabled, the memcpy function is linked
824 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700825
Robin Getz479ba602010-05-03 17:23:20 +0000826config STRCMP_L1
827 bool "locate strcmp function in L1 Memory"
828 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500829 depends on !SMP
Robin Getz479ba602010-05-03 17:23:20 +0000830 help
831 If enabled, the strcmp function is linked
832 into L1 instruction memory (less latency).
833
834config STRNCMP_L1
835 bool "locate strncmp function in L1 Memory"
836 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500837 depends on !SMP
Robin Getz479ba602010-05-03 17:23:20 +0000838 help
839 If enabled, the strncmp function is linked
840 into L1 instruction memory (less latency).
841
842config STRCPY_L1
843 bool "locate strcpy function in L1 Memory"
844 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500845 depends on !SMP
Robin Getz479ba602010-05-03 17:23:20 +0000846 help
847 If enabled, the strcpy function is linked
848 into L1 instruction memory (less latency).
849
850config STRNCPY_L1
851 bool "locate strncpy function in L1 Memory"
852 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500853 depends on !SMP
Robin Getz479ba602010-05-03 17:23:20 +0000854 help
855 If enabled, the strncpy function is linked
856 into L1 instruction memory (less latency).
857
Bryan Wu1394f032007-05-06 14:50:22 -0700858config SYS_BFIN_SPINLOCK_L1
859 bool "Locate sys_bfin_spinlock function in L1 Memory"
860 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500861 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700862 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200863 If enabled, sys_bfin_spinlock function is linked
864 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700865
866config IP_CHECKSUM_L1
867 bool "Locate IP Checksum function in L1 Memory"
868 default n
Mike Frysinger820b1272011-02-02 22:31:42 -0500869 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700870 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200871 If enabled, the IP Checksum function is linked
872 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700873
874config CACHELINE_ALIGNED_L1
875 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800876 default y if !BF54x
877 default n if BF54x
Mike Frysinger95fc2d8f2012-03-28 11:43:02 +0800878 depends on !SMP && !BF531 && !CRC32
Bryan Wu1394f032007-05-06 14:50:22 -0700879 help
Matt LaPlante692105b2009-01-26 11:12:25 +0100880 If enabled, cacheline_aligned data is linked
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200881 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700882
883config SYSCALL_TAB_L1
884 bool "Locate Syscall Table L1 Data Memory"
885 default n
Mike Frysinger820b1272011-02-02 22:31:42 -0500886 depends on !SMP && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700887 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200888 If enabled, the Syscall LUT is linked
889 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700890
891config CPLB_SWITCH_TAB_L1
892 bool "Locate CPLB Switch Tables L1 Data Memory"
893 default n
Mike Frysinger820b1272011-02-02 22:31:42 -0500894 depends on !SMP && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700895 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200896 If enabled, the CPLB Switch Tables are linked
897 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700898
Mike Frysinger820b1272011-02-02 22:31:42 -0500899config ICACHE_FLUSH_L1
900 bool "Locate icache flush funcs in L1 Inst Memory"
Mike Frysinger74181292010-05-27 22:46:46 +0000901 default y
902 help
Mike Frysinger820b1272011-02-02 22:31:42 -0500903 If enabled, the Blackfin icache flushing functions are linked
Mike Frysinger74181292010-05-27 22:46:46 +0000904 into L1 instruction memory.
905
906 Note that this might be required to address anomalies, but
907 these functions are pretty small, so it shouldn't be too bad.
908 If you are using a processor affected by an anomaly, the build
909 system will double check for you and prevent it.
910
Mike Frysinger820b1272011-02-02 22:31:42 -0500911config DCACHE_FLUSH_L1
912 bool "Locate dcache flush funcs in L1 Inst Memory"
913 default y
914 depends on !SMP
915 help
916 If enabled, the Blackfin dcache flushing functions are linked
917 into L1 instruction memory.
918
Graf Yangca87b7a2008-10-08 17:30:01 +0800919config APP_STACK_L1
920 bool "Support locating application stack in L1 Scratch Memory"
921 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500922 depends on !SMP
Graf Yangca87b7a2008-10-08 17:30:01 +0800923 help
924 If enabled the application stack can be located in L1
925 scratch memory (less latency).
926
927 Currently only works with FLAT binaries.
928
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800929config EXCEPTION_L1_SCRATCH
930 bool "Locate exception stack in L1 Scratch Memory"
931 default n
Mike Frysinger820b1272011-02-02 22:31:42 -0500932 depends on !SMP && !APP_STACK_L1
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800933 help
934 Whenever an exception occurs, use the L1 Scratch memory for
935 stack storage. You cannot place the stacks of FLAT binaries
936 in L1 when using this option.
937
938 If you don't use L1 Scratch, then you should say Y here.
939
Robin Getz251383c2008-08-14 15:12:55 +0800940comment "Speed Optimizations"
941config BFIN_INS_LOWOVERHEAD
942 bool "ins[bwl] low overhead, higher interrupt latency"
943 default y
Mike Frysinger820b1272011-02-02 22:31:42 -0500944 depends on !SMP
Robin Getz251383c2008-08-14 15:12:55 +0800945 help
946 Reads on the Blackfin are speculative. In Blackfin terms, this means
947 they can be interrupted at any time (even after they have been issued
948 on to the external bus), and re-issued after the interrupt occurs.
949 For memory - this is not a big deal, since memory does not change if
950 it sees a read.
951
952 If a FIFO is sitting on the end of the read, it will see two reads,
953 when the core only sees one since the FIFO receives both the read
954 which is cancelled (and not delivered to the core) and the one which
955 is re-issued (which is delivered to the core).
956
957 To solve this, interrupts are turned off before reads occur to
958 I/O space. This option controls which the overhead/latency of
959 controlling interrupts during this time
960 "n" turns interrupts off every read
961 (higher overhead, but lower interrupt latency)
962 "y" turns interrupts off every loop
963 (low overhead, but longer interrupt latency)
964
965 default behavior is to leave this set to on (type "Y"). If you are experiencing
966 interrupt latency issues, it is safe and OK to turn this off.
967
Bryan Wu1394f032007-05-06 14:50:22 -0700968endmenu
969
Bryan Wu1394f032007-05-06 14:50:22 -0700970choice
971 prompt "Kernel executes from"
972 help
973 Choose the memory type that the kernel will be running in.
974
975config RAMKERNEL
976 bool "RAM"
977 help
978 The kernel will be resident in RAM when running.
979
980config ROMKERNEL
981 bool "ROM"
982 help
983 The kernel will be resident in FLASH/ROM when running.
984
985endchoice
986
Mike Frysinger56b4f072010-10-16 19:46:21 -0400987# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
988config XIP_KERNEL
989 bool
990 default y
991 depends on ROMKERNEL
992
Bryan Wu1394f032007-05-06 14:50:22 -0700993source "mm/Kconfig"
994
Mike Frysinger780431e2007-10-21 23:37:54 +0800995config BFIN_GPTIMERS
996 tristate "Enable Blackfin General Purpose Timers API"
997 default n
998 help
999 Enable support for the General Purpose Timers API. If you
1000 are unsure, say N.
1001
1002 To compile this driver as a module, choose M here: the module
Pavel Machek4737f092009-06-05 00:44:53 +02001003 will be called gptimers.
Mike Frysinger780431e2007-10-21 23:37:54 +08001004
Mike Frysinger006669e2011-06-15 16:55:39 -04001005config HAVE_PWM
1006 tristate "Enable PWM API support"
1007 depends on BFIN_GPTIMERS
1008 help
1009 Enable support for the Pulse Width Modulation framework (as
1010 found in linux/pwm.h).
1011
1012 To compile this driver as a module, choose M here: the module
1013 will be called pwm.
1014
Bryan Wu1394f032007-05-06 14:50:22 -07001015choice
Mike Frysingerd292b002008-10-28 11:15:36 +08001016 prompt "Uncached DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -07001017 default DMA_UNCACHED_1M
Scott Jiangc8d11a02012-05-18 16:27:22 -04001018config DMA_UNCACHED_32M
1019 bool "Enable 32M DMA region"
1020config DMA_UNCACHED_16M
1021 bool "Enable 16M DMA region"
1022config DMA_UNCACHED_8M
1023 bool "Enable 8M DMA region"
Cliff Cai86ad7932008-05-17 16:36:52 +08001024config DMA_UNCACHED_4M
1025 bool "Enable 4M DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -07001026config DMA_UNCACHED_2M
1027 bool "Enable 2M DMA region"
1028config DMA_UNCACHED_1M
1029 bool "Enable 1M DMA region"
Barry Songc45c0652009-12-02 09:13:36 +00001030config DMA_UNCACHED_512K
1031 bool "Enable 512K DMA region"
1032config DMA_UNCACHED_256K
1033 bool "Enable 256K DMA region"
1034config DMA_UNCACHED_128K
1035 bool "Enable 128K DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -07001036config DMA_UNCACHED_NONE
1037 bool "Disable DMA region"
1038endchoice
1039
1040
1041comment "Cache Support"
Jie Zhang41ba6532009-06-16 09:48:33 +00001042
Robin Getz3bebca22007-10-10 23:55:26 +08001043config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -07001044 bool "Enable ICACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +00001045 default y
Jie Zhang41ba6532009-06-16 09:48:33 +00001046config BFIN_EXTMEM_ICACHEABLE
1047 bool "Enable ICACHE for external memory"
1048 depends on BFIN_ICACHE
1049 default y
1050config BFIN_L2_ICACHEABLE
1051 bool "Enable ICACHE for L2 SRAM"
1052 depends on BFIN_ICACHE
Steven Miaob0ce61d2012-06-01 10:29:42 +08001053 depends on (BF54x || BF561 || BF60x) && !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +00001054 default n
1055
Robin Getz3bebca22007-10-10 23:55:26 +08001056config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -07001057 bool "Enable DCACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +00001058 default y
Robin Getz3bebca22007-10-10 23:55:26 +08001059config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -07001060 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +08001061 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -07001062 default n
Jie Zhang41ba6532009-06-16 09:48:33 +00001063config BFIN_EXTMEM_DCACHEABLE
1064 bool "Enable DCACHE for external memory"
Robin Getz3bebca22007-10-10 23:55:26 +08001065 depends on BFIN_DCACHE
Jie Zhang41ba6532009-06-16 09:48:33 +00001066 default y
Graf Yang5ba76672009-05-07 04:09:15 +00001067choice
Jie Zhang41ba6532009-06-16 09:48:33 +00001068 prompt "External memory DCACHE policy"
1069 depends on BFIN_EXTMEM_DCACHEABLE
1070 default BFIN_EXTMEM_WRITEBACK if !SMP
1071 default BFIN_EXTMEM_WRITETHROUGH if SMP
1072config BFIN_EXTMEM_WRITEBACK
Graf Yang5ba76672009-05-07 04:09:15 +00001073 bool "Write back"
1074 depends on !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +00001075 help
1076 Write Back Policy:
1077 Cached data will be written back to SDRAM only when needed.
1078 This can give a nice increase in performance, but beware of
1079 broken drivers that do not properly invalidate/flush their
1080 cache.
Graf Yang5ba76672009-05-07 04:09:15 +00001081
Jie Zhang41ba6532009-06-16 09:48:33 +00001082 Write Through Policy:
1083 Cached data will always be written back to SDRAM when the
1084 cache is updated. This is a completely safe setting, but
1085 performance is worse than Write Back.
1086
1087 If you are unsure of the options and you want to be safe,
1088 then go with Write Through.
1089
1090config BFIN_EXTMEM_WRITETHROUGH
Graf Yang5ba76672009-05-07 04:09:15 +00001091 bool "Write through"
Jie Zhang41ba6532009-06-16 09:48:33 +00001092 help
1093 Write Back Policy:
1094 Cached data will be written back to SDRAM only when needed.
1095 This can give a nice increase in performance, but beware of
1096 broken drivers that do not properly invalidate/flush their
1097 cache.
Graf Yang5ba76672009-05-07 04:09:15 +00001098
Jie Zhang41ba6532009-06-16 09:48:33 +00001099 Write Through Policy:
1100 Cached data will always be written back to SDRAM when the
1101 cache is updated. This is a completely safe setting, but
1102 performance is worse than Write Back.
1103
1104 If you are unsure of the options and you want to be safe,
1105 then go with Write Through.
Graf Yang5ba76672009-05-07 04:09:15 +00001106
1107endchoice
Sonic Zhangf099f392008-10-09 14:11:57 +08001108
Jie Zhang41ba6532009-06-16 09:48:33 +00001109config BFIN_L2_DCACHEABLE
1110 bool "Enable DCACHE for L2 SRAM"
1111 depends on BFIN_DCACHE
Bob Liub5affb02012-05-16 17:37:24 +08001112 depends on (BF54x || BF561 || BF60x) && !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +00001113 default n
1114choice
1115 prompt "L2 SRAM DCACHE policy"
1116 depends on BFIN_L2_DCACHEABLE
1117 default BFIN_L2_WRITEBACK
1118config BFIN_L2_WRITEBACK
1119 bool "Write back"
Jie Zhang41ba6532009-06-16 09:48:33 +00001120
1121config BFIN_L2_WRITETHROUGH
1122 bool "Write through"
Jie Zhang41ba6532009-06-16 09:48:33 +00001123endchoice
1124
1125
1126comment "Memory Protection Unit"
Bernd Schmidtb97b8a92008-01-27 18:39:16 +08001127config MPU
1128 bool "Enable the memory protection unit (EXPERIMENTAL)"
1129 default n
1130 help
1131 Use the processor's MPU to protect applications from accessing
1132 memory they do not own. This comes at a performance penalty
1133 and is recommended only for debugging.
1134
Matt LaPlante692105b2009-01-26 11:12:25 +01001135comment "Asynchronous Memory Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07001136
Mike Frysingerddf416b2007-10-10 18:06:47 +08001137menu "EBIU_AMGCTL Global Control"
Bob Liub5affb02012-05-16 17:37:24 +08001138 depends on !BF60x
Bryan Wu1394f032007-05-06 14:50:22 -07001139config C_AMCKEN
1140 bool "Enable CLKOUT"
1141 default y
1142
1143config C_CDPRIO
1144 bool "DMA has priority over core for ext. accesses"
1145 default n
1146
1147config C_B0PEN
1148 depends on BF561
1149 bool "Bank 0 16 bit packing enable"
1150 default y
1151
1152config C_B1PEN
1153 depends on BF561
1154 bool "Bank 1 16 bit packing enable"
1155 default y
1156
1157config C_B2PEN
1158 depends on BF561
1159 bool "Bank 2 16 bit packing enable"
1160 default y
1161
1162config C_B3PEN
1163 depends on BF561
1164 bool "Bank 3 16 bit packing enable"
1165 default n
1166
1167choice
Matt LaPlante692105b2009-01-26 11:12:25 +01001168 prompt "Enable Asynchronous Memory Banks"
Bryan Wu1394f032007-05-06 14:50:22 -07001169 default C_AMBEN_ALL
1170
1171config C_AMBEN
1172 bool "Disable All Banks"
1173
1174config C_AMBEN_B0
1175 bool "Enable Bank 0"
1176
1177config C_AMBEN_B0_B1
1178 bool "Enable Bank 0 & 1"
1179
1180config C_AMBEN_B0_B1_B2
1181 bool "Enable Bank 0 & 1 & 2"
1182
1183config C_AMBEN_ALL
1184 bool "Enable All Banks"
1185endchoice
1186endmenu
1187
1188menu "EBIU_AMBCTL Control"
Bob Liub5affb02012-05-16 17:37:24 +08001189 depends on !BF60x
Bryan Wu1394f032007-05-06 14:50:22 -07001190config BANK_0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001191 hex "Bank 0 (AMBCTL0.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001192 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001193 help
1194 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1195 used to control the Asynchronous Memory Bank 0 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001196
1197config BANK_1
Mike Frysingerc8342f82009-03-31 00:18:35 +00001198 hex "Bank 1 (AMBCTL0.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001199 default 0x7BB0
Michael Hennerich197fba52008-05-07 17:03:27 +08001200 default 0x5558 if BF54x
Mike Frysingerc8342f82009-03-31 00:18:35 +00001201 help
1202 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1203 used to control the Asynchronous Memory Bank 1 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001204
1205config BANK_2
Mike Frysingerc8342f82009-03-31 00:18:35 +00001206 hex "Bank 2 (AMBCTL1.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001207 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001208 help
1209 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1210 used to control the Asynchronous Memory Bank 2 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001211
1212config BANK_3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001213 hex "Bank 3 (AMBCTL1.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001214 default 0x99B3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001215 help
1216 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1217 used to control the Asynchronous Memory Bank 3 settings.
1218
Bryan Wu1394f032007-05-06 14:50:22 -07001219endmenu
1220
Sonic Zhange40540b2007-11-21 23:49:52 +08001221config EBIU_MBSCTLVAL
1222 hex "EBIU Bank Select Control Register"
1223 depends on BF54x
1224 default 0
1225
1226config EBIU_MODEVAL
1227 hex "Flash Memory Mode Control Register"
1228 depends on BF54x
1229 default 1
1230
1231config EBIU_FCTLVAL
1232 hex "Flash Memory Bank Control Register"
1233 depends on BF54x
1234 default 6
Bryan Wu1394f032007-05-06 14:50:22 -07001235endmenu
1236
1237#############################################################################
1238menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1239
1240config PCI
1241 bool "PCI support"
Adrian Bunka95ca3b2008-08-27 10:55:05 +08001242 depends on BROKEN
Bryan Wu1394f032007-05-06 14:50:22 -07001243 help
1244 Support for PCI bus.
1245
1246source "drivers/pci/Kconfig"
1247
Bryan Wu1394f032007-05-06 14:50:22 -07001248source "drivers/pcmcia/Kconfig"
1249
1250source "drivers/pci/hotplug/Kconfig"
1251
1252endmenu
1253
1254menu "Executable file formats"
1255
1256source "fs/Kconfig.binfmt"
1257
1258endmenu
1259
1260menu "Power management options"
Graf Yangad461632009-08-07 03:52:54 +00001261
Bryan Wu1394f032007-05-06 14:50:22 -07001262source "kernel/power/Kconfig"
1263
Johannes Bergf4cb5702007-12-08 02:14:00 +01001264config ARCH_SUSPEND_POSSIBLE
1265 def_bool y
Johannes Bergf4cb5702007-12-08 02:14:00 +01001266
Bryan Wu1394f032007-05-06 14:50:22 -07001267choice
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001268 prompt "Standby Power Saving Mode"
Steven Miao0fbd88c2012-05-17 17:29:54 +08001269 depends on PM && !BF60x
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001270 default PM_BFIN_SLEEP_DEEPER
1271config PM_BFIN_SLEEP_DEEPER
1272 bool "Sleep Deeper"
Bryan Wu1394f032007-05-06 14:50:22 -07001273 help
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001274 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1275 power dissipation by disabling the clock to the processor core (CCLK).
1276 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1277 to 0.85 V to provide the greatest power savings, while preserving the
1278 processor state.
1279 The PLL and system clock (SCLK) continue to operate at a very low
1280 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1281 the SDRAM is put into Self Refresh Mode. Typically an external event
1282 such as GPIO interrupt or RTC activity wakes up the processor.
1283 Various Peripherals such as UART, SPORT, PPI may not function as
1284 normal during Sleep Deeper, due to the reduced SCLK frequency.
1285 When in the sleep mode, system DMA access to L1 memory is not supported.
Bryan Wu1394f032007-05-06 14:50:22 -07001286
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001287 If unsure, select "Sleep Deeper".
1288
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001289config PM_BFIN_SLEEP
1290 bool "Sleep"
1291 help
1292 Sleep Mode (High Power Savings) - The sleep mode reduces power
1293 dissipation by disabling the clock to the processor core (CCLK).
1294 The PLL and system clock (SCLK), however, continue to operate in
1295 this mode. Typically an external event or RTC activity will wake
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001296 up the processor. When in the sleep mode, system DMA access to L1
1297 memory is not supported.
1298
1299 If unsure, select "Sleep Deeper".
Bryan Wu1394f032007-05-06 14:50:22 -07001300endchoice
1301
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001302comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1303 depends on PM
1304
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001305config PM_BFIN_WAKE_PH6
1306 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001307 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001308 default n
1309 help
1310 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1311
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001312config PM_BFIN_WAKE_GP
1313 bool "Allow Wake-Up from GPIOs"
1314 depends on PM && BF54x
1315 default n
1316 help
1317 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
Michael Hennerich19986282009-03-05 16:45:55 +08001318 (all processors, except ADSP-BF549). This option sets
1319 the general-purpose wake-up enable (GPWE) control bit to enable
1320 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
Masanari Iida59bf8962012-04-18 00:01:21 +09001321 On ADSP-BF549 this option enables the same functionality on the
Michael Hennerich19986282009-03-05 16:45:55 +08001322 /MRXON pin also PH7.
1323
Steven Miao0fbd88c2012-05-17 17:29:54 +08001324config PM_BFIN_WAKE_PA15
1325 bool "Allow Wake-Up from PA15"
1326 depends on PM && BF60x
1327 default n
1328 help
1329 Enable PA15 Wake-Up
1330
1331config PM_BFIN_WAKE_PA15_POL
1332 int "Wake-up priority"
1333 depends on PM_BFIN_WAKE_PA15
1334 default 0
1335 help
1336 Wake-Up priority 0(low) 1(high)
1337
1338config PM_BFIN_WAKE_PB15
1339 bool "Allow Wake-Up from PB15"
1340 depends on PM && BF60x
1341 default n
1342 help
1343 Enable PB15 Wake-Up
1344
1345config PM_BFIN_WAKE_PB15_POL
1346 int "Wake-up priority"
1347 depends on PM_BFIN_WAKE_PB15
1348 default 0
1349 help
1350 Wake-Up priority 0(low) 1(high)
1351
1352config PM_BFIN_WAKE_PC15
1353 bool "Allow Wake-Up from PC15"
1354 depends on PM && BF60x
1355 default n
1356 help
1357 Enable PC15 Wake-Up
1358
1359config PM_BFIN_WAKE_PC15_POL
1360 int "Wake-up priority"
1361 depends on PM_BFIN_WAKE_PC15
1362 default 0
1363 help
1364 Wake-Up priority 0(low) 1(high)
1365
1366config PM_BFIN_WAKE_PD06
1367 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1368 depends on PM && BF60x
1369 default n
1370 help
1371 Enable PD06(ETH0_PHYINT) Wake-up
1372
1373config PM_BFIN_WAKE_PD06_POL
1374 int "Wake-up priority"
1375 depends on PM_BFIN_WAKE_PD06
1376 default 0
1377 help
1378 Wake-Up priority 0(low) 1(high)
1379
1380config PM_BFIN_WAKE_PE12
1381 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1382 depends on PM && BF60x
1383 default n
1384 help
1385 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1386
1387config PM_BFIN_WAKE_PE12_POL
1388 int "Wake-up priority"
1389 depends on PM_BFIN_WAKE_PE12
1390 default 0
1391 help
1392 Wake-Up priority 0(low) 1(high)
1393
1394config PM_BFIN_WAKE_PG04
1395 bool "Allow Wake-Up from PG04(CAN0_RX)"
1396 depends on PM && BF60x
1397 default n
1398 help
1399 Enable PG04(CAN0_RX) Wake-up
1400
1401config PM_BFIN_WAKE_PG04_POL
1402 int "Wake-up priority"
1403 depends on PM_BFIN_WAKE_PG04
1404 default 0
1405 help
1406 Wake-Up priority 0(low) 1(high)
1407
1408config PM_BFIN_WAKE_PG13
1409 bool "Allow Wake-Up from PG13"
1410 depends on PM && BF60x
1411 default n
1412 help
1413 Enable PG13 Wake-Up
1414
1415config PM_BFIN_WAKE_PG13_POL
1416 int "Wake-up priority"
1417 depends on PM_BFIN_WAKE_PG13
1418 default 0
1419 help
1420 Wake-Up priority 0(low) 1(high)
1421
1422config PM_BFIN_WAKE_USB
1423 bool "Allow Wake-Up from (USB)"
1424 depends on PM && BF60x
1425 default n
1426 help
1427 Enable (USB) Wake-up
1428
1429config PM_BFIN_WAKE_USB_POL
1430 int "Wake-up priority"
1431 depends on PM_BFIN_WAKE_USB
1432 default 0
1433 help
1434 Wake-Up priority 0(low) 1(high)
1435
Bryan Wu1394f032007-05-06 14:50:22 -07001436endmenu
1437
Bryan Wu1394f032007-05-06 14:50:22 -07001438menu "CPU Frequency scaling"
1439
1440source "drivers/cpufreq/Kconfig"
1441
Michael Hennerich5ad2ca52008-11-18 17:48:22 +08001442config BFIN_CPU_FREQ
1443 bool
1444 depends on CPU_FREQ
1445 select CPU_FREQ_TABLE
1446 default y
1447
Michael Hennerich14b03202008-05-07 11:41:26 +08001448config CPU_VOLTAGE
1449 bool "CPU Voltage scaling"
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001450 depends on EXPERIMENTAL
Michael Hennerich14b03202008-05-07 11:41:26 +08001451 depends on CPU_FREQ
1452 default n
1453 help
1454 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1455 This option violates the PLL BYPASS recommendation in the Blackfin Processor
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001456 manuals. There is a theoretical risk that during VDDINT transitions
Michael Hennerich14b03202008-05-07 11:41:26 +08001457 the PLL may unlock.
1458
Bryan Wu1394f032007-05-06 14:50:22 -07001459endmenu
1460
Bryan Wu1394f032007-05-06 14:50:22 -07001461source "net/Kconfig"
1462
1463source "drivers/Kconfig"
1464
Mike Frysinger872d0242009-10-06 04:49:07 +00001465source "drivers/firmware/Kconfig"
1466
Bryan Wu1394f032007-05-06 14:50:22 -07001467source "fs/Kconfig"
1468
Mike Frysinger74ce8322007-11-21 23:50:49 +08001469source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001470
1471source "security/Kconfig"
1472
1473source "crypto/Kconfig"
1474
1475source "lib/Kconfig"