blob: 6abcf326b6492f8deed7fadea5639ca632d446b0 [file] [log] [blame]
Daniel Vetter76aaf222010-11-05 22:23:30 +01001/*
2 * Copyright © 2010 Daniel Vetter
Ben Widawskyc4ac5242014-02-19 22:05:47 -08003 * Copyright © 2011-2014 Intel Corporation
Daniel Vetter76aaf222010-11-05 22:23:30 +01004 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
Daniel Vetter0e46ce22014-01-08 16:10:27 +010026#include <linux/seq_file.h>
David Howells760285e2012-10-02 18:01:07 +010027#include <drm/drmP.h>
28#include <drm/i915_drm.h>
Daniel Vetter76aaf222010-11-05 22:23:30 +010029#include "i915_drv.h"
Yu Zhang5dda8fa2015-02-10 19:05:48 +080030#include "i915_vgpu.h"
Daniel Vetter76aaf222010-11-05 22:23:30 +010031#include "i915_trace.h"
32#include "intel_drv.h"
33
Tvrtko Ursulin45f8f692014-12-10 17:27:59 +000034/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
Joonas Lahtinenec7adb62015-03-16 14:11:13 +020070 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
Tvrtko Ursulin45f8f692014-12-10 17:27:59 +000073 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
Daniel Vetter70b9f6f2015-04-14 17:35:27 +020095static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +000098const struct i915_ggtt_view i915_ggtt_view_normal;
Joonas Lahtinen9abc4642015-03-27 13:09:22 +020099const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +0000102
Daniel Vettercfa7c862014-04-29 11:53:58 +0200103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
Chris Wilson1893a712014-09-19 11:56:27 +0100105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
Chris Wilson1893a712014-09-19 11:56:27 +0100110
Yu Zhang71ba2d62015-02-10 19:05:54 +0800111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
Damien Lespiau70ee45e2014-11-14 15:05:59 +0000114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
Daniel Vettercfa7c862014-04-29 11:53:58 +0200120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
Chris Wilson1893a712014-09-19 11:56:27 +0100125 if (enable_ppgtt == 2 && has_full_ppgtt)
Daniel Vettercfa7c862014-04-29 11:53:58 +0200126 return 2;
127
Daniel Vetter93a25a92014-03-06 09:40:43 +0100128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
Daniel Vettercfa7c862014-04-29 11:53:58 +0200132 return 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100133 }
134#endif
135
Jesse Barnes62942ed2014-06-13 09:28:33 -0700136 /* Early VLV doesn't have this */
Ville Syrjäläca2aed6c2014-06-28 02:03:56 +0300137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
Jesse Barnes62942ed2014-06-13 09:28:33 -0700139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
Michel Thierry2f82bbd2014-12-15 14:58:00 +0000143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100147}
148
Daniel Vetter70b9f6f2015-04-14 17:35:27 +0200149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
Daniel Vetter47552652015-04-14 17:35:24 +0200152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
Daniel Vetter70b9f6f2015-04-14 17:35:27 +0200161
162 return 0;
Daniel Vetter47552652015-04-14 17:35:24 +0200163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
Ben Widawsky6f65e292013-12-06 14:10:56 -0800172
Daniel Vetter2c642b02015-04-14 17:35:26 +0200173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700176{
Michel Thierry07749ef2015-03-16 16:00:54 +0000177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700178 pte |= addr;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300179
180 switch (level) {
181 case I915_CACHE_NONE:
Ben Widawskyfbe5d362013-11-04 19:56:49 -0800182 pte |= PPAT_UNCACHED_INDEX;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700192 return pte;
193}
194
Daniel Vetter2c642b02015-04-14 17:35:26 +0200195static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
196 dma_addr_t addr,
197 enum i915_cache_level level)
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800198{
Michel Thierry07749ef2015-03-16 16:00:54 +0000199 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800200 pde |= addr;
201 if (level != I915_CACHE_NONE)
202 pde |= PPAT_CACHED_PDE_INDEX;
203 else
204 pde |= PPAT_UNCACHED_INDEX;
205 return pde;
206}
207
Michel Thierry07749ef2015-03-16 16:00:54 +0000208static gen6_pte_t snb_pte_encode(dma_addr_t addr,
209 enum i915_cache_level level,
210 bool valid, u32 unused)
Ben Widawsky54d12522012-09-24 16:44:32 -0700211{
Michel Thierry07749ef2015-03-16 16:00:54 +0000212 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky54d12522012-09-24 16:44:32 -0700213 pte |= GEN6_PTE_ADDR_ENCODE(addr);
Ben Widawskye7210c32012-10-19 09:33:22 -0700214
215 switch (level) {
Chris Wilson350ec882013-08-06 13:17:02 +0100216 case I915_CACHE_L3_LLC:
217 case I915_CACHE_LLC:
218 pte |= GEN6_PTE_CACHE_LLC;
219 break;
220 case I915_CACHE_NONE:
221 pte |= GEN6_PTE_UNCACHED;
222 break;
223 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100224 MISSING_CASE(level);
Chris Wilson350ec882013-08-06 13:17:02 +0100225 }
226
227 return pte;
228}
229
Michel Thierry07749ef2015-03-16 16:00:54 +0000230static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
231 enum i915_cache_level level,
232 bool valid, u32 unused)
Chris Wilson350ec882013-08-06 13:17:02 +0100233{
Michel Thierry07749ef2015-03-16 16:00:54 +0000234 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Chris Wilson350ec882013-08-06 13:17:02 +0100235 pte |= GEN6_PTE_ADDR_ENCODE(addr);
236
237 switch (level) {
238 case I915_CACHE_L3_LLC:
239 pte |= GEN7_PTE_CACHE_L3_LLC;
Ben Widawskye7210c32012-10-19 09:33:22 -0700240 break;
241 case I915_CACHE_LLC:
242 pte |= GEN6_PTE_CACHE_LLC;
243 break;
244 case I915_CACHE_NONE:
Kenneth Graunke91197082013-04-22 00:53:51 -0700245 pte |= GEN6_PTE_UNCACHED;
Ben Widawskye7210c32012-10-19 09:33:22 -0700246 break;
247 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100248 MISSING_CASE(level);
Ben Widawskye7210c32012-10-19 09:33:22 -0700249 }
250
Ben Widawsky54d12522012-09-24 16:44:32 -0700251 return pte;
252}
253
Michel Thierry07749ef2015-03-16 16:00:54 +0000254static gen6_pte_t byt_pte_encode(dma_addr_t addr,
255 enum i915_cache_level level,
256 bool valid, u32 flags)
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700257{
Michel Thierry07749ef2015-03-16 16:00:54 +0000258 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700259 pte |= GEN6_PTE_ADDR_ENCODE(addr);
260
Akash Goel24f3a8c2014-06-17 10:59:42 +0530261 if (!(flags & PTE_READ_ONLY))
262 pte |= BYT_PTE_WRITEABLE;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700263
264 if (level != I915_CACHE_NONE)
265 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
266
267 return pte;
268}
269
Michel Thierry07749ef2015-03-16 16:00:54 +0000270static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
271 enum i915_cache_level level,
272 bool valid, u32 unused)
Kenneth Graunke91197082013-04-22 00:53:51 -0700273{
Michel Thierry07749ef2015-03-16 16:00:54 +0000274 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky0d8ff152013-07-04 11:02:03 -0700275 pte |= HSW_PTE_ADDR_ENCODE(addr);
Kenneth Graunke91197082013-04-22 00:53:51 -0700276
277 if (level != I915_CACHE_NONE)
Ben Widawsky87a6b682013-08-04 23:47:29 -0700278 pte |= HSW_WB_LLC_AGE3;
Kenneth Graunke91197082013-04-22 00:53:51 -0700279
280 return pte;
281}
282
Michel Thierry07749ef2015-03-16 16:00:54 +0000283static gen6_pte_t iris_pte_encode(dma_addr_t addr,
284 enum i915_cache_level level,
285 bool valid, u32 unused)
Ben Widawsky4d15c142013-07-04 11:02:06 -0700286{
Michel Thierry07749ef2015-03-16 16:00:54 +0000287 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky4d15c142013-07-04 11:02:06 -0700288 pte |= HSW_PTE_ADDR_ENCODE(addr);
289
Chris Wilson651d7942013-08-08 14:41:10 +0100290 switch (level) {
291 case I915_CACHE_NONE:
292 break;
293 case I915_CACHE_WT:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000294 pte |= HSW_WT_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100295 break;
296 default:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000297 pte |= HSW_WB_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100298 break;
299 }
Ben Widawsky4d15c142013-07-04 11:02:06 -0700300
301 return pte;
302}
303
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300304static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
Ben Widawsky678d96f2015-03-16 16:00:56 +0000305{
306 struct device *device = &dev->pdev->dev;
307
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300308 p->page = alloc_page(GFP_KERNEL);
309 if (!p->page)
Michel Thierry1266cdb2015-03-24 17:06:33 +0000310 return -ENOMEM;
311
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
314
315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
319
Michel Thierry1266cdb2015-03-24 17:06:33 +0000320 return 0;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000321}
322
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300323static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 if (WARN_ON(!p->page))
326 return;
327
328 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
329 __free_page(p->page);
330 memset(p, 0, sizeof(*p));
331}
332
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300333static void *kmap_page_dma(struct i915_page_dma *p)
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300334{
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300335 return kmap_atomic(p->page);
336}
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300337
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300338/* We use the flushing unmap only with ppgtt structures:
339 * page directories, page tables and scratch pages.
340 */
341static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
342{
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300343 /* There are only few exceptions for gen >=6. chv and bxt.
344 * And we are not sure about the latter so play safe for now.
345 */
346 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
347 drm_clflush_virt_range(vaddr, PAGE_SIZE);
348
349 kunmap_atomic(vaddr);
350}
351
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300352#define kmap_px(px) kmap_page_dma(&(px)->base)
353#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
354
355static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
356 const uint64_t val)
357{
358 int i;
359 uint64_t * const vaddr = kmap_page_dma(p);
360
361 for (i = 0; i < 512; i++)
362 vaddr[i] = val;
363
364 kunmap_page_dma(dev, vaddr);
365}
366
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300367static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
368 const uint32_t val32)
369{
370 uint64_t v = val32;
371
372 v = v << 32 | val32;
373
374 fill_page_dma(dev, p, v);
375}
376
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300377static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
Ben Widawsky06fda602015-02-24 16:22:36 +0000378{
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300379 cleanup_page_dma(dev, &pt->base);
Ben Widawsky678d96f2015-03-16 16:00:56 +0000380 kfree(pt->used_ptes);
Ben Widawsky06fda602015-02-24 16:22:36 +0000381 kfree(pt);
382}
383
Michel Thierry5a8e9942015-04-08 12:13:25 +0100384static void gen8_initialize_pt(struct i915_address_space *vm,
Michel Thierrye5815a22015-04-08 12:13:32 +0100385 struct i915_page_table *pt)
Michel Thierry5a8e9942015-04-08 12:13:25 +0100386{
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300387 gen8_pte_t scratch_pte;
Michel Thierry5a8e9942015-04-08 12:13:25 +0100388
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300389 scratch_pte = gen8_pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
Michel Thierry5a8e9942015-04-08 12:13:25 +0100390
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300391 fill_page_dma(vm->dev, &pt->base, scratch_pte);
Michel Thierry5a8e9942015-04-08 12:13:25 +0100392}
393
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300394static struct i915_page_table *alloc_pt(struct drm_device *dev)
Ben Widawsky06fda602015-02-24 16:22:36 +0000395{
Michel Thierryec565b32015-04-08 12:13:23 +0100396 struct i915_page_table *pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000397 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
398 GEN8_PTES : GEN6_PTES;
399 int ret = -ENOMEM;
Ben Widawsky06fda602015-02-24 16:22:36 +0000400
401 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
402 if (!pt)
403 return ERR_PTR(-ENOMEM);
404
Ben Widawsky678d96f2015-03-16 16:00:56 +0000405 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
406 GFP_KERNEL);
407
408 if (!pt->used_ptes)
409 goto fail_bitmap;
410
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300411 ret = setup_page_dma(dev, &pt->base);
Ben Widawsky678d96f2015-03-16 16:00:56 +0000412 if (ret)
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300413 goto fail_page_m;
Ben Widawsky06fda602015-02-24 16:22:36 +0000414
415 return pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000416
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300417fail_page_m:
Ben Widawsky678d96f2015-03-16 16:00:56 +0000418 kfree(pt->used_ptes);
419fail_bitmap:
420 kfree(pt);
421
422 return ERR_PTR(ret);
Ben Widawsky06fda602015-02-24 16:22:36 +0000423}
424
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300425static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
Ben Widawsky06fda602015-02-24 16:22:36 +0000426{
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300427 if (pd->base.page) {
428 cleanup_page_dma(dev, &pd->base);
Michel Thierry33c88192015-04-08 12:13:33 +0100429 kfree(pd->used_pdes);
Ben Widawsky06fda602015-02-24 16:22:36 +0000430 kfree(pd);
431 }
432}
433
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300434static struct i915_page_directory *alloc_pd(struct drm_device *dev)
Ben Widawsky06fda602015-02-24 16:22:36 +0000435{
Michel Thierryec565b32015-04-08 12:13:23 +0100436 struct i915_page_directory *pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100437 int ret = -ENOMEM;
Ben Widawsky06fda602015-02-24 16:22:36 +0000438
439 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
440 if (!pd)
441 return ERR_PTR(-ENOMEM);
442
Michel Thierry33c88192015-04-08 12:13:33 +0100443 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
444 sizeof(*pd->used_pdes), GFP_KERNEL);
445 if (!pd->used_pdes)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300446 goto fail_bitmap;
Michel Thierry33c88192015-04-08 12:13:33 +0100447
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300448 ret = setup_page_dma(dev, &pd->base);
Michel Thierry33c88192015-04-08 12:13:33 +0100449 if (ret)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300450 goto fail_page_m;
Michel Thierrye5815a22015-04-08 12:13:32 +0100451
Ben Widawsky06fda602015-02-24 16:22:36 +0000452 return pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100453
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300454fail_page_m:
Michel Thierry33c88192015-04-08 12:13:33 +0100455 kfree(pd->used_pdes);
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300456fail_bitmap:
Michel Thierry33c88192015-04-08 12:13:33 +0100457 kfree(pd);
458
459 return ERR_PTR(ret);
Ben Widawsky06fda602015-02-24 16:22:36 +0000460}
461
Ben Widawsky94e409c2013-11-04 22:29:36 -0800462/* Broadwell Page Directory Pointer Descriptors */
John Harrisone85b26d2015-05-29 17:43:56 +0100463static int gen8_write_pdp(struct drm_i915_gem_request *req,
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100464 unsigned entry,
465 dma_addr_t addr)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800466{
John Harrisone85b26d2015-05-29 17:43:56 +0100467 struct intel_engine_cs *ring = req->ring;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800468 int ret;
469
470 BUG_ON(entry >= 4);
471
John Harrison5fb9de12015-05-29 17:44:07 +0100472 ret = intel_ring_begin(req, 6);
Ben Widawsky94e409c2013-11-04 22:29:36 -0800473 if (ret)
474 return ret;
475
476 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
477 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100478 intel_ring_emit(ring, upper_32_bits(addr));
Ben Widawsky94e409c2013-11-04 22:29:36 -0800479 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
480 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100481 intel_ring_emit(ring, lower_32_bits(addr));
Ben Widawsky94e409c2013-11-04 22:29:36 -0800482 intel_ring_advance(ring);
483
484 return 0;
485}
486
Ben Widawskyeeb94882013-12-06 14:11:10 -0800487static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +0100488 struct drm_i915_gem_request *req)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800489{
Ben Widawskyeeb94882013-12-06 14:11:10 -0800490 int i, ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800491
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100492 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
Mika Kuoppalad852c7b2015-06-25 18:35:06 +0300493 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
494
John Harrisone85b26d2015-05-29 17:43:56 +0100495 ret = gen8_write_pdp(req, i, pd_daddr);
Ben Widawskyeeb94882013-12-06 14:11:10 -0800496 if (ret)
497 return ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800498 }
Ben Widawskyd595bd42013-11-25 09:54:32 -0800499
Ben Widawskyeeb94882013-12-06 14:11:10 -0800500 return 0;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800501}
502
Ben Widawsky459108b2013-11-02 21:07:23 -0700503static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -0800504 uint64_t start,
505 uint64_t length,
Ben Widawsky459108b2013-11-02 21:07:23 -0700506 bool use_scratch)
507{
508 struct i915_hw_ppgtt *ppgtt =
509 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +0000510 gen8_pte_t *pt_vaddr, scratch_pte;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800511 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
512 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
513 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky782f1492014-02-20 11:50:33 -0800514 unsigned num_entries = length >> PAGE_SHIFT;
Ben Widawsky459108b2013-11-02 21:07:23 -0700515 unsigned last_pte, i;
516
517 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
518 I915_CACHE_LLC, use_scratch);
519
520 while (num_entries) {
Michel Thierryec565b32015-04-08 12:13:23 +0100521 struct i915_page_directory *pd;
522 struct i915_page_table *pt;
Ben Widawsky06fda602015-02-24 16:22:36 +0000523
524 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
525 continue;
526
527 pd = ppgtt->pdp.page_directory[pdpe];
528
529 if (WARN_ON(!pd->page_table[pde]))
530 continue;
531
532 pt = pd->page_table[pde];
533
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300534 if (WARN_ON(!pt->base.page))
Ben Widawsky06fda602015-02-24 16:22:36 +0000535 continue;
536
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800537 last_pte = pte + num_entries;
Michel Thierry07749ef2015-03-16 16:00:54 +0000538 if (last_pte > GEN8_PTES)
539 last_pte = GEN8_PTES;
Ben Widawsky459108b2013-11-02 21:07:23 -0700540
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300541 pt_vaddr = kmap_px(pt);
Ben Widawsky459108b2013-11-02 21:07:23 -0700542
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800543 for (i = pte; i < last_pte; i++) {
Ben Widawsky459108b2013-11-02 21:07:23 -0700544 pt_vaddr[i] = scratch_pte;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800545 num_entries--;
546 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700547
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300548 kunmap_px(ppgtt, pt);
Ben Widawsky459108b2013-11-02 21:07:23 -0700549
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800550 pte = 0;
Michel Thierry07749ef2015-03-16 16:00:54 +0000551 if (++pde == I915_PDES) {
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800552 pdpe++;
553 pde = 0;
554 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700555 }
556}
557
Ben Widawsky9df15b42013-11-02 21:07:24 -0700558static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
559 struct sg_table *pages,
Ben Widawsky782f1492014-02-20 11:50:33 -0800560 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530561 enum i915_cache_level cache_level, u32 unused)
Ben Widawsky9df15b42013-11-02 21:07:24 -0700562{
563 struct i915_hw_ppgtt *ppgtt =
564 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +0000565 gen8_pte_t *pt_vaddr;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800566 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
567 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
568 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700569 struct sg_page_iter sg_iter;
570
Chris Wilson6f1cc992013-12-31 15:50:31 +0000571 pt_vaddr = NULL;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700572
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800573 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
Ben Widawsky76643602015-01-22 17:01:24 +0000574 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800575 break;
576
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000577 if (pt_vaddr == NULL) {
Michel Thierryec565b32015-04-08 12:13:23 +0100578 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
579 struct i915_page_table *pt = pd->page_table[pde];
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300580 pt_vaddr = kmap_px(pt);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000581 }
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800582
583 pt_vaddr[pte] =
Chris Wilson6f1cc992013-12-31 15:50:31 +0000584 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
585 cache_level, true);
Michel Thierry07749ef2015-03-16 16:00:54 +0000586 if (++pte == GEN8_PTES) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300587 kunmap_px(ppgtt, pt_vaddr);
Chris Wilson6f1cc992013-12-31 15:50:31 +0000588 pt_vaddr = NULL;
Michel Thierry07749ef2015-03-16 16:00:54 +0000589 if (++pde == I915_PDES) {
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800590 pdpe++;
591 pde = 0;
592 }
593 pte = 0;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700594 }
595 }
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300596
597 if (pt_vaddr)
598 kunmap_px(ppgtt, pt_vaddr);
Ben Widawsky9df15b42013-11-02 21:07:24 -0700599}
600
Michel Thierry69876be2015-04-08 12:13:27 +0100601static void __gen8_do_map_pt(gen8_pde_t * const pde,
602 struct i915_page_table *pt,
603 struct drm_device *dev)
604{
605 gen8_pde_t entry =
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300606 gen8_pde_encode(dev, pt->base.daddr, I915_CACHE_LLC);
Michel Thierry69876be2015-04-08 12:13:27 +0100607 *pde = entry;
608}
609
610static void gen8_initialize_pd(struct i915_address_space *vm,
611 struct i915_page_directory *pd)
612{
613 struct i915_hw_ppgtt *ppgtt =
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300614 container_of(vm, struct i915_hw_ppgtt, base);
615 gen8_pde_t scratch_pde;
Michel Thierry69876be2015-04-08 12:13:27 +0100616
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300617 scratch_pde = gen8_pde_encode(vm->dev, ppgtt->scratch_pt->base.daddr,
618 I915_CACHE_LLC);
Michel Thierry69876be2015-04-08 12:13:27 +0100619
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300620 fill_page_dma(vm->dev, &pd->base, scratch_pde);
Michel Thierrye5815a22015-04-08 12:13:32 +0100621}
622
Michel Thierryec565b32015-04-08 12:13:23 +0100623static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
Ben Widawskyb45a6712014-02-12 14:28:44 -0800624{
625 int i;
626
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300627 if (!pd->base.page)
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800628 return;
Ben Widawskyb45a6712014-02-12 14:28:44 -0800629
Michel Thierry33c88192015-04-08 12:13:33 +0100630 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
Ben Widawsky06fda602015-02-24 16:22:36 +0000631 if (WARN_ON(!pd->page_table[i]))
632 continue;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800633
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300634 free_pt(dev, pd->page_table[i]);
Ben Widawsky06fda602015-02-24 16:22:36 +0000635 pd->page_table[i] = NULL;
636 }
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000637}
638
Daniel Vetter061dd492015-04-14 17:35:13 +0200639static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800640{
Daniel Vetter061dd492015-04-14 17:35:13 +0200641 struct i915_hw_ppgtt *ppgtt =
642 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800643 int i;
644
Michel Thierry33c88192015-04-08 12:13:33 +0100645 for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
Ben Widawsky06fda602015-02-24 16:22:36 +0000646 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
647 continue;
648
Michel Thierry06dc68d2015-02-24 16:22:37 +0000649 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300650 free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]);
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800651 }
Michel Thierry69876be2015-04-08 12:13:27 +0100652
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300653 free_pd(ppgtt->base.dev, ppgtt->scratch_pd);
654 free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
Ben Widawskyb45a6712014-02-12 14:28:44 -0800655}
656
Michel Thierryd7b26332015-04-08 12:13:34 +0100657/**
658 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
659 * @ppgtt: Master ppgtt structure.
660 * @pd: Page directory for this address range.
661 * @start: Starting virtual address to begin allocations.
662 * @length Size of the allocations.
663 * @new_pts: Bitmap set by function with new allocations. Likely used by the
664 * caller to free on error.
665 *
666 * Allocate the required number of page tables. Extremely similar to
667 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
668 * the page directory boundary (instead of the page directory pointer). That
669 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
670 * possible, and likely that the caller will need to use multiple calls of this
671 * function to achieve the appropriate allocation.
672 *
673 * Return: 0 if success; negative error code otherwise.
674 */
Michel Thierrye5815a22015-04-08 12:13:32 +0100675static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
676 struct i915_page_directory *pd,
Michel Thierry5441f0c2015-04-08 12:13:28 +0100677 uint64_t start,
Michel Thierryd7b26332015-04-08 12:13:34 +0100678 uint64_t length,
679 unsigned long *new_pts)
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000680{
Michel Thierrye5815a22015-04-08 12:13:32 +0100681 struct drm_device *dev = ppgtt->base.dev;
Michel Thierryd7b26332015-04-08 12:13:34 +0100682 struct i915_page_table *pt;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100683 uint64_t temp;
684 uint32_t pde;
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000685
Michel Thierryd7b26332015-04-08 12:13:34 +0100686 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
687 /* Don't reallocate page tables */
688 if (pt) {
689 /* Scratch is never allocated this way */
690 WARN_ON(pt == ppgtt->scratch_pt);
691 continue;
692 }
693
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300694 pt = alloc_pt(dev);
Michel Thierryd7b26332015-04-08 12:13:34 +0100695 if (IS_ERR(pt))
Ben Widawsky06fda602015-02-24 16:22:36 +0000696 goto unwind_out;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100697
Michel Thierryd7b26332015-04-08 12:13:34 +0100698 gen8_initialize_pt(&ppgtt->base, pt);
699 pd->page_table[pde] = pt;
700 set_bit(pde, new_pts);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000701 }
702
703 return 0;
704
705unwind_out:
Michel Thierryd7b26332015-04-08 12:13:34 +0100706 for_each_set_bit(pde, new_pts, I915_PDES)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300707 free_pt(dev, pd->page_table[pde]);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000708
709 return -ENOMEM;
710}
711
Michel Thierryd7b26332015-04-08 12:13:34 +0100712/**
713 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
714 * @ppgtt: Master ppgtt structure.
715 * @pdp: Page directory pointer for this address range.
716 * @start: Starting virtual address to begin allocations.
717 * @length Size of the allocations.
718 * @new_pds Bitmap set by function with new allocations. Likely used by the
719 * caller to free on error.
720 *
721 * Allocate the required number of page directories starting at the pde index of
722 * @start, and ending at the pde index @start + @length. This function will skip
723 * over already allocated page directories within the range, and only allocate
724 * new ones, setting the appropriate pointer within the pdp as well as the
725 * correct position in the bitmap @new_pds.
726 *
727 * The function will only allocate the pages within the range for a give page
728 * directory pointer. In other words, if @start + @length straddles a virtually
729 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
730 * required by the caller, This is not currently possible, and the BUG in the
731 * code will prevent it.
732 *
733 * Return: 0 if success; negative error code otherwise.
734 */
Michel Thierryc488dbb2015-04-08 12:13:31 +0100735static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
736 struct i915_page_directory_pointer *pdp,
Michel Thierry69876be2015-04-08 12:13:27 +0100737 uint64_t start,
Michel Thierryd7b26332015-04-08 12:13:34 +0100738 uint64_t length,
739 unsigned long *new_pds)
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800740{
Michel Thierrye5815a22015-04-08 12:13:32 +0100741 struct drm_device *dev = ppgtt->base.dev;
Michel Thierryd7b26332015-04-08 12:13:34 +0100742 struct i915_page_directory *pd;
Michel Thierry69876be2015-04-08 12:13:27 +0100743 uint64_t temp;
744 uint32_t pdpe;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800745
Michel Thierryd7b26332015-04-08 12:13:34 +0100746 WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
747
Michel Thierryd7b26332015-04-08 12:13:34 +0100748 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
749 if (pd)
750 continue;
Michel Thierry33c88192015-04-08 12:13:33 +0100751
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300752 pd = alloc_pd(dev);
Michel Thierryd7b26332015-04-08 12:13:34 +0100753 if (IS_ERR(pd))
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000754 goto unwind_out;
Michel Thierry69876be2015-04-08 12:13:27 +0100755
Michel Thierryd7b26332015-04-08 12:13:34 +0100756 gen8_initialize_pd(&ppgtt->base, pd);
757 pdp->page_directory[pdpe] = pd;
758 set_bit(pdpe, new_pds);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000759 }
760
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800761 return 0;
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000762
763unwind_out:
Michel Thierryd7b26332015-04-08 12:13:34 +0100764 for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300765 free_pd(dev, pdp->page_directory[pdpe]);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000766
767 return -ENOMEM;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800768}
769
Michel Thierryd7b26332015-04-08 12:13:34 +0100770static void
771free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
772{
773 int i;
774
775 for (i = 0; i < GEN8_LEGACY_PDPES; i++)
776 kfree(new_pts[i]);
777 kfree(new_pts);
778 kfree(new_pds);
779}
780
781/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
782 * of these are based on the number of PDPEs in the system.
783 */
784static
785int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
786 unsigned long ***new_pts)
787{
788 int i;
789 unsigned long *pds;
790 unsigned long **pts;
791
792 pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
793 if (!pds)
794 return -ENOMEM;
795
796 pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
797 if (!pts) {
798 kfree(pds);
799 return -ENOMEM;
800 }
801
802 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
803 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
804 sizeof(unsigned long), GFP_KERNEL);
805 if (!pts[i])
806 goto err_out;
807 }
808
809 *new_pds = pds;
810 *new_pts = pts;
811
812 return 0;
813
814err_out:
815 free_gen8_temp_bitmaps(pds, pts);
816 return -ENOMEM;
817}
818
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +0300819/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
820 * the page table structures, we mark them dirty so that
821 * context switching/execlist queuing code takes extra steps
822 * to ensure that tlbs are flushed.
823 */
824static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
825{
826 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
827}
828
Michel Thierrye5815a22015-04-08 12:13:32 +0100829static int gen8_alloc_va_range(struct i915_address_space *vm,
830 uint64_t start,
831 uint64_t length)
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800832{
Michel Thierrye5815a22015-04-08 12:13:32 +0100833 struct i915_hw_ppgtt *ppgtt =
834 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryd7b26332015-04-08 12:13:34 +0100835 unsigned long *new_page_dirs, **new_page_tables;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100836 struct i915_page_directory *pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100837 const uint64_t orig_start = start;
838 const uint64_t orig_length = length;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100839 uint64_t temp;
840 uint32_t pdpe;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800841 int ret;
842
Michel Thierryd7b26332015-04-08 12:13:34 +0100843 /* Wrap is never okay since we can only represent 48b, and we don't
844 * actually use the other side of the canonical address space.
845 */
846 if (WARN_ON(start + length < start))
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +0300847 return -ENODEV;
848
849 if (WARN_ON(start + length > ppgtt->base.total))
850 return -ENODEV;
Michel Thierryd7b26332015-04-08 12:13:34 +0100851
852 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800853 if (ret)
854 return ret;
855
Michel Thierryd7b26332015-04-08 12:13:34 +0100856 /* Do the allocations first so we can easily bail out */
857 ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
858 new_page_dirs);
859 if (ret) {
860 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
861 return ret;
862 }
863
864 /* For every page directory referenced, allocate page tables */
Michel Thierry5441f0c2015-04-08 12:13:28 +0100865 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
Michel Thierryd7b26332015-04-08 12:13:34 +0100866 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
867 new_page_tables[pdpe]);
Michel Thierry5441f0c2015-04-08 12:13:28 +0100868 if (ret)
869 goto err_out;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100870 }
871
Michel Thierry33c88192015-04-08 12:13:33 +0100872 start = orig_start;
873 length = orig_length;
874
Michel Thierryd7b26332015-04-08 12:13:34 +0100875 /* Allocations have completed successfully, so set the bitmaps, and do
876 * the mappings. */
Michel Thierry33c88192015-04-08 12:13:33 +0100877 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300878 gen8_pde_t *const page_directory = kmap_px(pd);
Michel Thierry33c88192015-04-08 12:13:33 +0100879 struct i915_page_table *pt;
880 uint64_t pd_len = gen8_clamp_pd(start, length);
881 uint64_t pd_start = start;
882 uint32_t pde;
883
Michel Thierryd7b26332015-04-08 12:13:34 +0100884 /* Every pd should be allocated, we just did that above. */
885 WARN_ON(!pd);
886
887 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
888 /* Same reasoning as pd */
889 WARN_ON(!pt);
890 WARN_ON(!pd_len);
891 WARN_ON(!gen8_pte_count(pd_start, pd_len));
892
893 /* Set our used ptes within the page table */
894 bitmap_set(pt->used_ptes,
895 gen8_pte_index(pd_start),
896 gen8_pte_count(pd_start, pd_len));
897
898 /* Our pde is now pointing to the pagetable, pt */
Michel Thierry33c88192015-04-08 12:13:33 +0100899 set_bit(pde, pd->used_pdes);
Michel Thierryd7b26332015-04-08 12:13:34 +0100900
901 /* Map the PDE to the page table */
902 __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
903
904 /* NB: We haven't yet mapped ptes to pages. At this
905 * point we're still relying on insert_entries() */
Michel Thierry33c88192015-04-08 12:13:33 +0100906 }
Michel Thierryd7b26332015-04-08 12:13:34 +0100907
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300908 kunmap_px(ppgtt, page_directory);
Michel Thierryd7b26332015-04-08 12:13:34 +0100909
Michel Thierry33c88192015-04-08 12:13:33 +0100910 set_bit(pdpe, ppgtt->pdp.used_pdpes);
911 }
912
Michel Thierryd7b26332015-04-08 12:13:34 +0100913 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +0300914 mark_tlbs_dirty(ppgtt);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000915 return 0;
916
917err_out:
Michel Thierryd7b26332015-04-08 12:13:34 +0100918 while (pdpe--) {
919 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300920 free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]);
Michel Thierryd7b26332015-04-08 12:13:34 +0100921 }
922
923 for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300924 free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]);
Michel Thierryd7b26332015-04-08 12:13:34 +0100925
926 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +0300927 mark_tlbs_dirty(ppgtt);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800928 return ret;
929}
930
Daniel Vettereb0b44a2015-03-18 14:47:59 +0100931/*
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800932 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
933 * with a net effect resembling a 2-level page table in normal x86 terms. Each
934 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
935 * space.
Ben Widawsky37aca442013-11-04 20:47:32 -0800936 *
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800937 */
Daniel Vetter5c5f6452015-04-14 17:35:14 +0200938static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky37aca442013-11-04 20:47:32 -0800939{
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300940 ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
Michel Thierry69876be2015-04-08 12:13:27 +0100941 if (IS_ERR(ppgtt->scratch_pt))
942 return PTR_ERR(ppgtt->scratch_pt);
943
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300944 ppgtt->scratch_pd = alloc_pd(ppgtt->base.dev);
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100945 if (IS_ERR(ppgtt->scratch_pd))
946 return PTR_ERR(ppgtt->scratch_pd);
947
Michel Thierry69876be2015-04-08 12:13:27 +0100948 gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100949 gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
Michel Thierry69876be2015-04-08 12:13:27 +0100950
Michel Thierryd7b26332015-04-08 12:13:34 +0100951 ppgtt->base.start = 0;
Daniel Vetter5c5f6452015-04-14 17:35:14 +0200952 ppgtt->base.total = 1ULL << 32;
Michel Thierry501fd702015-05-29 14:15:05 +0100953 if (IS_ENABLED(CONFIG_X86_32))
954 /* While we have a proliferation of size_t variables
955 * we cannot represent the full ppgtt size on 32bit,
956 * so limit it to the same size as the GGTT (currently
957 * 2GiB).
958 */
959 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
Michel Thierryd7b26332015-04-08 12:13:34 +0100960 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
Daniel Vetter5c5f6452015-04-14 17:35:14 +0200961 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
Michel Thierryd7b26332015-04-08 12:13:34 +0100962 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
Daniel Vetterc7e16f22015-04-14 17:35:11 +0200963 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
Daniel Vetter777dc5b2015-04-14 17:35:12 +0200964 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
965 ppgtt->base.bind_vma = ppgtt_bind_vma;
Michel Thierryd7b26332015-04-08 12:13:34 +0100966
967 ppgtt->switch_mm = gen8_mm_switch;
968
969 return 0;
970}
971
Ben Widawsky87d60b62013-12-06 14:11:29 -0800972static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
973{
Ben Widawsky87d60b62013-12-06 14:11:29 -0800974 struct i915_address_space *vm = &ppgtt->base;
Michel Thierry09942c62015-04-08 12:13:30 +0100975 struct i915_page_table *unused;
Michel Thierry07749ef2015-03-16 16:00:54 +0000976 gen6_pte_t scratch_pte;
Ben Widawsky87d60b62013-12-06 14:11:29 -0800977 uint32_t pd_entry;
Michel Thierry09942c62015-04-08 12:13:30 +0100978 uint32_t pte, pde, temp;
979 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
Ben Widawsky87d60b62013-12-06 14:11:29 -0800980
Akash Goel24f3a8c2014-06-17 10:59:42 +0530981 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
Ben Widawsky87d60b62013-12-06 14:11:29 -0800982
Michel Thierry09942c62015-04-08 12:13:30 +0100983 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
Ben Widawsky87d60b62013-12-06 14:11:29 -0800984 u32 expected;
Michel Thierry07749ef2015-03-16 16:00:54 +0000985 gen6_pte_t *pt_vaddr;
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300986 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->base.daddr;
Michel Thierry09942c62015-04-08 12:13:30 +0100987 pd_entry = readl(ppgtt->pd_addr + pde);
Ben Widawsky87d60b62013-12-06 14:11:29 -0800988 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
989
990 if (pd_entry != expected)
991 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
992 pde,
993 pd_entry,
994 expected);
995 seq_printf(m, "\tPDE: %x\n", pd_entry);
996
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300997 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
998
Michel Thierry07749ef2015-03-16 16:00:54 +0000999 for (pte = 0; pte < GEN6_PTES; pte+=4) {
Ben Widawsky87d60b62013-12-06 14:11:29 -08001000 unsigned long va =
Michel Thierry07749ef2015-03-16 16:00:54 +00001001 (pde * PAGE_SIZE * GEN6_PTES) +
Ben Widawsky87d60b62013-12-06 14:11:29 -08001002 (pte * PAGE_SIZE);
1003 int i;
1004 bool found = false;
1005 for (i = 0; i < 4; i++)
1006 if (pt_vaddr[pte + i] != scratch_pte)
1007 found = true;
1008 if (!found)
1009 continue;
1010
1011 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1012 for (i = 0; i < 4; i++) {
1013 if (pt_vaddr[pte + i] != scratch_pte)
1014 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1015 else
1016 seq_puts(m, " SCRATCH ");
1017 }
1018 seq_puts(m, "\n");
1019 }
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001020 kunmap_px(ppgtt, pt_vaddr);
Ben Widawsky87d60b62013-12-06 14:11:29 -08001021 }
1022}
1023
Ben Widawsky678d96f2015-03-16 16:00:56 +00001024/* Write pde (index) from the page directory @pd to the page table @pt */
Michel Thierryec565b32015-04-08 12:13:23 +01001025static void gen6_write_pde(struct i915_page_directory *pd,
1026 const int pde, struct i915_page_table *pt)
Ben Widawsky61973492013-04-08 18:43:54 -07001027{
Ben Widawsky678d96f2015-03-16 16:00:56 +00001028 /* Caller needs to make sure the write completes if necessary */
1029 struct i915_hw_ppgtt *ppgtt =
1030 container_of(pd, struct i915_hw_ppgtt, pd);
1031 u32 pd_entry;
Ben Widawsky61973492013-04-08 18:43:54 -07001032
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001033 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->base.daddr);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001034 pd_entry |= GEN6_PDE_VALID;
Ben Widawsky61973492013-04-08 18:43:54 -07001035
Ben Widawsky678d96f2015-03-16 16:00:56 +00001036 writel(pd_entry, ppgtt->pd_addr + pde);
1037}
Ben Widawsky61973492013-04-08 18:43:54 -07001038
Ben Widawsky678d96f2015-03-16 16:00:56 +00001039/* Write all the page tables found in the ppgtt structure to incrementing page
1040 * directories. */
1041static void gen6_write_page_range(struct drm_i915_private *dev_priv,
Michel Thierryec565b32015-04-08 12:13:23 +01001042 struct i915_page_directory *pd,
Ben Widawsky678d96f2015-03-16 16:00:56 +00001043 uint32_t start, uint32_t length)
1044{
Michel Thierryec565b32015-04-08 12:13:23 +01001045 struct i915_page_table *pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001046 uint32_t pde, temp;
1047
1048 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1049 gen6_write_pde(pd, pde, pt);
1050
1051 /* Make sure write is complete before other code can use this page
1052 * table. Also require for WC mapped PTEs */
1053 readl(dev_priv->gtt.gsm);
Ben Widawsky3e302542013-04-23 23:15:32 -07001054}
1055
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001056static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky3e302542013-04-23 23:15:32 -07001057{
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001058 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
Ben Widawsky3e302542013-04-23 23:15:32 -07001059
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001060 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001061}
Ben Widawsky61973492013-04-08 18:43:54 -07001062
Ben Widawsky90252e52013-12-06 14:11:12 -08001063static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001064 struct drm_i915_gem_request *req)
Ben Widawsky90252e52013-12-06 14:11:12 -08001065{
John Harrisone85b26d2015-05-29 17:43:56 +01001066 struct intel_engine_cs *ring = req->ring;
Ben Widawsky90252e52013-12-06 14:11:12 -08001067 int ret;
Ben Widawsky61973492013-04-08 18:43:54 -07001068
Ben Widawsky90252e52013-12-06 14:11:12 -08001069 /* NB: TLBs must be flushed and invalidated before a switch */
John Harrisona84c3ae2015-05-29 17:43:57 +01001070 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky90252e52013-12-06 14:11:12 -08001071 if (ret)
1072 return ret;
1073
John Harrison5fb9de12015-05-29 17:44:07 +01001074 ret = intel_ring_begin(req, 6);
Ben Widawsky90252e52013-12-06 14:11:12 -08001075 if (ret)
1076 return ret;
1077
1078 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1079 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1080 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1081 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1082 intel_ring_emit(ring, get_pd_offset(ppgtt));
1083 intel_ring_emit(ring, MI_NOOP);
1084 intel_ring_advance(ring);
1085
1086 return 0;
1087}
1088
Yu Zhang71ba2d62015-02-10 19:05:54 +08001089static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001090 struct drm_i915_gem_request *req)
Yu Zhang71ba2d62015-02-10 19:05:54 +08001091{
John Harrisone85b26d2015-05-29 17:43:56 +01001092 struct intel_engine_cs *ring = req->ring;
Yu Zhang71ba2d62015-02-10 19:05:54 +08001093 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1094
1095 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1096 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1097 return 0;
1098}
1099
Ben Widawsky48a10382013-12-06 14:11:11 -08001100static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001101 struct drm_i915_gem_request *req)
Ben Widawsky48a10382013-12-06 14:11:11 -08001102{
John Harrisone85b26d2015-05-29 17:43:56 +01001103 struct intel_engine_cs *ring = req->ring;
Ben Widawsky48a10382013-12-06 14:11:11 -08001104 int ret;
1105
Ben Widawsky48a10382013-12-06 14:11:11 -08001106 /* NB: TLBs must be flushed and invalidated before a switch */
John Harrisona84c3ae2015-05-29 17:43:57 +01001107 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky48a10382013-12-06 14:11:11 -08001108 if (ret)
1109 return ret;
1110
John Harrison5fb9de12015-05-29 17:44:07 +01001111 ret = intel_ring_begin(req, 6);
Ben Widawsky48a10382013-12-06 14:11:11 -08001112 if (ret)
1113 return ret;
1114
1115 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1116 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1117 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1118 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1119 intel_ring_emit(ring, get_pd_offset(ppgtt));
1120 intel_ring_emit(ring, MI_NOOP);
1121 intel_ring_advance(ring);
1122
Ben Widawsky90252e52013-12-06 14:11:12 -08001123 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1124 if (ring->id != RCS) {
John Harrisona84c3ae2015-05-29 17:43:57 +01001125 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky90252e52013-12-06 14:11:12 -08001126 if (ret)
1127 return ret;
1128 }
1129
Ben Widawsky48a10382013-12-06 14:11:11 -08001130 return 0;
1131}
1132
Ben Widawskyeeb94882013-12-06 14:11:10 -08001133static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001134 struct drm_i915_gem_request *req)
Ben Widawskyeeb94882013-12-06 14:11:10 -08001135{
John Harrisone85b26d2015-05-29 17:43:56 +01001136 struct intel_engine_cs *ring = req->ring;
Ben Widawskyeeb94882013-12-06 14:11:10 -08001137 struct drm_device *dev = ppgtt->base.dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139
Ben Widawsky48a10382013-12-06 14:11:11 -08001140
Ben Widawskyeeb94882013-12-06 14:11:10 -08001141 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1142 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1143
1144 POSTING_READ(RING_PP_DIR_DCLV(ring));
1145
1146 return 0;
1147}
1148
Daniel Vetter82460d92014-08-06 20:19:53 +02001149static void gen8_ppgtt_enable(struct drm_device *dev)
Ben Widawskyeeb94882013-12-06 14:11:10 -08001150{
Ben Widawskyeeb94882013-12-06 14:11:10 -08001151 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001152 struct intel_engine_cs *ring;
Daniel Vetter82460d92014-08-06 20:19:53 +02001153 int j;
Ben Widawskyeeb94882013-12-06 14:11:10 -08001154
1155 for_each_ring(ring, dev_priv, j) {
1156 I915_WRITE(RING_MODE_GEN7(ring),
1157 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawskyeeb94882013-12-06 14:11:10 -08001158 }
Ben Widawskyeeb94882013-12-06 14:11:10 -08001159}
1160
Daniel Vetter82460d92014-08-06 20:19:53 +02001161static void gen7_ppgtt_enable(struct drm_device *dev)
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001162{
Jani Nikula50227e12014-03-31 14:27:21 +03001163 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001164 struct intel_engine_cs *ring;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001165 uint32_t ecochk, ecobits;
1166 int i;
1167
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001168 ecobits = I915_READ(GAC_ECO_BITS);
1169 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1170
1171 ecochk = I915_READ(GAM_ECOCHK);
1172 if (IS_HASWELL(dev)) {
1173 ecochk |= ECOCHK_PPGTT_WB_HSW;
1174 } else {
1175 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1176 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1177 }
1178 I915_WRITE(GAM_ECOCHK, ecochk);
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001179
Ben Widawsky61973492013-04-08 18:43:54 -07001180 for_each_ring(ring, dev_priv, i) {
Ben Widawskyeeb94882013-12-06 14:11:10 -08001181 /* GFX_MODE is per-ring on gen7+ */
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001182 I915_WRITE(RING_MODE_GEN7(ring),
1183 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -07001184 }
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001185}
1186
Daniel Vetter82460d92014-08-06 20:19:53 +02001187static void gen6_ppgtt_enable(struct drm_device *dev)
Ben Widawsky61973492013-04-08 18:43:54 -07001188{
Jani Nikula50227e12014-03-31 14:27:21 +03001189 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001190 uint32_t ecochk, gab_ctl, ecobits;
Ben Widawsky61973492013-04-08 18:43:54 -07001191
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001192 ecobits = I915_READ(GAC_ECO_BITS);
1193 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1194 ECOBITS_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -07001195
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001196 gab_ctl = I915_READ(GAB_CTL);
1197 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
Ben Widawsky61973492013-04-08 18:43:54 -07001198
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001199 ecochk = I915_READ(GAM_ECOCHK);
1200 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -07001201
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001202 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -07001203}
1204
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001205/* PPGTT support for Sandybdrige/Gen6 and later */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001206static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001207 uint64_t start,
1208 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001209 bool use_scratch)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001210{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001211 struct i915_hw_ppgtt *ppgtt =
1212 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +00001213 gen6_pte_t *pt_vaddr, scratch_pte;
Ben Widawsky782f1492014-02-20 11:50:33 -08001214 unsigned first_entry = start >> PAGE_SHIFT;
1215 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001216 unsigned act_pt = first_entry / GEN6_PTES;
1217 unsigned first_pte = first_entry % GEN6_PTES;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001218 unsigned last_pte, i;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001219
Akash Goel24f3a8c2014-06-17 10:59:42 +05301220 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001221
Daniel Vetter7bddb012012-02-09 17:15:47 +01001222 while (num_entries) {
1223 last_pte = first_pte + num_entries;
Michel Thierry07749ef2015-03-16 16:00:54 +00001224 if (last_pte > GEN6_PTES)
1225 last_pte = GEN6_PTES;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001226
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001227 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001228
1229 for (i = first_pte; i < last_pte; i++)
1230 pt_vaddr[i] = scratch_pte;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001231
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001232 kunmap_px(ppgtt, pt_vaddr);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001233
Daniel Vetter7bddb012012-02-09 17:15:47 +01001234 num_entries -= last_pte - first_pte;
1235 first_pte = 0;
Daniel Vettera15326a2013-03-19 23:48:39 +01001236 act_pt++;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001237 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001238}
1239
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001240static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
Daniel Vetterdef886c2013-01-24 14:44:56 -08001241 struct sg_table *pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08001242 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301243 enum i915_cache_level cache_level, u32 flags)
Daniel Vetterdef886c2013-01-24 14:44:56 -08001244{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001245 struct i915_hw_ppgtt *ppgtt =
1246 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +00001247 gen6_pte_t *pt_vaddr;
Ben Widawsky782f1492014-02-20 11:50:33 -08001248 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001249 unsigned act_pt = first_entry / GEN6_PTES;
1250 unsigned act_pte = first_entry % GEN6_PTES;
Imre Deak6e995e22013-02-18 19:28:04 +02001251 struct sg_page_iter sg_iter;
Daniel Vetterdef886c2013-01-24 14:44:56 -08001252
Chris Wilsoncc797142013-12-31 15:50:30 +00001253 pt_vaddr = NULL;
Imre Deak6e995e22013-02-18 19:28:04 +02001254 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
Chris Wilsoncc797142013-12-31 15:50:30 +00001255 if (pt_vaddr == NULL)
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001256 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
Daniel Vetterdef886c2013-01-24 14:44:56 -08001257
Chris Wilsoncc797142013-12-31 15:50:30 +00001258 pt_vaddr[act_pte] =
1259 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
Akash Goel24f3a8c2014-06-17 10:59:42 +05301260 cache_level, true, flags);
1261
Michel Thierry07749ef2015-03-16 16:00:54 +00001262 if (++act_pte == GEN6_PTES) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001263 kunmap_px(ppgtt, pt_vaddr);
Chris Wilsoncc797142013-12-31 15:50:30 +00001264 pt_vaddr = NULL;
Daniel Vettera15326a2013-03-19 23:48:39 +01001265 act_pt++;
Imre Deak6e995e22013-02-18 19:28:04 +02001266 act_pte = 0;
Daniel Vetterdef886c2013-01-24 14:44:56 -08001267 }
Daniel Vetterdef886c2013-01-24 14:44:56 -08001268 }
Chris Wilsoncc797142013-12-31 15:50:30 +00001269 if (pt_vaddr)
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001270 kunmap_px(ppgtt, pt_vaddr);
Daniel Vetterdef886c2013-01-24 14:44:56 -08001271}
1272
Michel Thierry4933d512015-03-24 15:46:22 +00001273static void gen6_initialize_pt(struct i915_address_space *vm,
Mika Kuoppala73eeea52015-06-25 18:35:10 +03001274 struct i915_page_table *pt)
Michel Thierry4933d512015-03-24 15:46:22 +00001275{
Mika Kuoppala73eeea52015-06-25 18:35:10 +03001276 gen6_pte_t scratch_pte;
Michel Thierry4933d512015-03-24 15:46:22 +00001277
1278 WARN_ON(vm->scratch.addr == 0);
1279
Mika Kuoppala73eeea52015-06-25 18:35:10 +03001280 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
Michel Thierry4933d512015-03-24 15:46:22 +00001281
Mika Kuoppala73eeea52015-06-25 18:35:10 +03001282 fill_page_dma_32(vm->dev, &pt->base, scratch_pte);
Michel Thierry4933d512015-03-24 15:46:22 +00001283}
1284
Ben Widawsky678d96f2015-03-16 16:00:56 +00001285static int gen6_alloc_va_range(struct i915_address_space *vm,
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001286 uint64_t start_in, uint64_t length_in)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001287{
Michel Thierry4933d512015-03-24 15:46:22 +00001288 DECLARE_BITMAP(new_page_tables, I915_PDES);
1289 struct drm_device *dev = vm->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001291 struct i915_hw_ppgtt *ppgtt =
1292 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryec565b32015-04-08 12:13:23 +01001293 struct i915_page_table *pt;
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001294 uint32_t start, length, start_save, length_save;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001295 uint32_t pde, temp;
Michel Thierry4933d512015-03-24 15:46:22 +00001296 int ret;
1297
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001298 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1299 return -ENODEV;
1300
1301 start = start_save = start_in;
1302 length = length_save = length_in;
Michel Thierry4933d512015-03-24 15:46:22 +00001303
1304 bitmap_zero(new_page_tables, I915_PDES);
1305
1306 /* The allocation is done in two stages so that we can bail out with
1307 * minimal amount of pain. The first stage finds new page tables that
1308 * need allocation. The second stage marks use ptes within the page
1309 * tables.
1310 */
1311 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1312 if (pt != ppgtt->scratch_pt) {
1313 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1314 continue;
1315 }
1316
1317 /* We've already allocated a page table */
1318 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1319
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +03001320 pt = alloc_pt(dev);
Michel Thierry4933d512015-03-24 15:46:22 +00001321 if (IS_ERR(pt)) {
1322 ret = PTR_ERR(pt);
1323 goto unwind_out;
1324 }
1325
1326 gen6_initialize_pt(vm, pt);
1327
1328 ppgtt->pd.page_table[pde] = pt;
1329 set_bit(pde, new_page_tables);
Michel Thierry72744cb2015-03-24 15:46:23 +00001330 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
Michel Thierry4933d512015-03-24 15:46:22 +00001331 }
1332
1333 start = start_save;
1334 length = length_save;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001335
1336 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1337 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1338
1339 bitmap_zero(tmp_bitmap, GEN6_PTES);
1340 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1341 gen6_pte_count(start, length));
1342
Michel Thierry4933d512015-03-24 15:46:22 +00001343 if (test_and_clear_bit(pde, new_page_tables))
1344 gen6_write_pde(&ppgtt->pd, pde, pt);
1345
Michel Thierry72744cb2015-03-24 15:46:23 +00001346 trace_i915_page_table_entry_map(vm, pde, pt,
1347 gen6_pte_index(start),
1348 gen6_pte_count(start, length),
1349 GEN6_PTES);
Michel Thierry4933d512015-03-24 15:46:22 +00001350 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
Ben Widawsky678d96f2015-03-16 16:00:56 +00001351 GEN6_PTES);
1352 }
1353
Michel Thierry4933d512015-03-24 15:46:22 +00001354 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1355
1356 /* Make sure write is complete before other code can use this page
1357 * table. Also require for WC mapped PTEs */
1358 readl(dev_priv->gtt.gsm);
1359
Ben Widawsky563222a2015-03-19 12:53:28 +00001360 mark_tlbs_dirty(ppgtt);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001361 return 0;
Michel Thierry4933d512015-03-24 15:46:22 +00001362
1363unwind_out:
1364 for_each_set_bit(pde, new_page_tables, I915_PDES) {
Michel Thierryec565b32015-04-08 12:13:23 +01001365 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
Michel Thierry4933d512015-03-24 15:46:22 +00001366
1367 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001368 free_pt(vm->dev, pt);
Michel Thierry4933d512015-03-24 15:46:22 +00001369 }
1370
1371 mark_tlbs_dirty(ppgtt);
1372 return ret;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001373}
1374
Daniel Vetter061dd492015-04-14 17:35:13 +02001375static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
Ben Widawskya00d8252014-02-19 22:05:48 -08001376{
Daniel Vetter061dd492015-04-14 17:35:13 +02001377 struct i915_hw_ppgtt *ppgtt =
1378 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry09942c62015-04-08 12:13:30 +01001379 struct i915_page_table *pt;
1380 uint32_t pde;
Daniel Vetter3440d262013-01-24 13:49:56 -08001381
Daniel Vetter061dd492015-04-14 17:35:13 +02001382
1383 drm_mm_remove_node(&ppgtt->node);
1384
Michel Thierry09942c62015-04-08 12:13:30 +01001385 gen6_for_all_pdes(pt, ppgtt, pde) {
Michel Thierry4933d512015-03-24 15:46:22 +00001386 if (pt != ppgtt->scratch_pt)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001387 free_pt(ppgtt->base.dev, pt);
Michel Thierry4933d512015-03-24 15:46:22 +00001388 }
1389
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001390 free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
Daniel Vetter3440d262013-01-24 13:49:56 -08001391}
1392
Ben Widawskyb1465202014-02-19 22:05:49 -08001393static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001394{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001395 struct drm_device *dev = ppgtt->base.dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001396 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3cc1992013-12-06 14:11:08 -08001397 bool retried = false;
Ben Widawskyb1465202014-02-19 22:05:49 -08001398 int ret;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001399
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001400 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1401 * allocator works in address space sizes, so it's multiplied by page
1402 * size. We allocate at the top of the GTT to avoid fragmentation.
1403 */
1404 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +03001405 ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
Michel Thierry4933d512015-03-24 15:46:22 +00001406 if (IS_ERR(ppgtt->scratch_pt))
1407 return PTR_ERR(ppgtt->scratch_pt);
1408
1409 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1410
Ben Widawskye3cc1992013-12-06 14:11:08 -08001411alloc:
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001412 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1413 &ppgtt->node, GEN6_PD_SIZE,
1414 GEN6_PD_ALIGN, 0,
1415 0, dev_priv->gtt.base.total,
Ben Widawsky3e8b5ae2014-05-06 22:21:30 -07001416 DRM_MM_TOPDOWN);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001417 if (ret == -ENOSPC && !retried) {
1418 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1419 GEN6_PD_SIZE, GEN6_PD_ALIGN,
Chris Wilsond23db882014-05-23 08:48:08 +02001420 I915_CACHE_NONE,
1421 0, dev_priv->gtt.base.total,
1422 0);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001423 if (ret)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001424 goto err_out;
Ben Widawskye3cc1992013-12-06 14:11:08 -08001425
1426 retried = true;
1427 goto alloc;
1428 }
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001429
Ben Widawskyc8c26622015-01-22 17:01:25 +00001430 if (ret)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001431 goto err_out;
1432
Ben Widawskyc8c26622015-01-22 17:01:25 +00001433
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001434 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1435 DRM_DEBUG("Forced to use aperture for PDEs\n");
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001436
Ben Widawskyc8c26622015-01-22 17:01:25 +00001437 return 0;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001438
1439err_out:
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001440 free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001441 return ret;
Ben Widawskyb1465202014-02-19 22:05:49 -08001442}
1443
Ben Widawskyb1465202014-02-19 22:05:49 -08001444static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1445{
kbuild test robot2f2cf682015-03-27 19:26:35 +08001446 return gen6_ppgtt_allocate_page_directories(ppgtt);
Ben Widawskyb1465202014-02-19 22:05:49 -08001447}
1448
Michel Thierry4933d512015-03-24 15:46:22 +00001449static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1450 uint64_t start, uint64_t length)
1451{
Michel Thierryec565b32015-04-08 12:13:23 +01001452 struct i915_page_table *unused;
Michel Thierry4933d512015-03-24 15:46:22 +00001453 uint32_t pde, temp;
1454
1455 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1456 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1457}
1458
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001459static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
Ben Widawskyb1465202014-02-19 22:05:49 -08001460{
1461 struct drm_device *dev = ppgtt->base.dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 int ret;
1464
1465 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
Ben Widawsky48a10382013-12-06 14:11:11 -08001466 if (IS_GEN6(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001467 ppgtt->switch_mm = gen6_mm_switch;
Ben Widawsky90252e52013-12-06 14:11:12 -08001468 } else if (IS_HASWELL(dev)) {
Ben Widawsky90252e52013-12-06 14:11:12 -08001469 ppgtt->switch_mm = hsw_mm_switch;
Ben Widawsky48a10382013-12-06 14:11:11 -08001470 } else if (IS_GEN7(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001471 ppgtt->switch_mm = gen7_mm_switch;
1472 } else
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001473 BUG();
Ben Widawskyb1465202014-02-19 22:05:49 -08001474
Yu Zhang71ba2d62015-02-10 19:05:54 +08001475 if (intel_vgpu_active(dev))
1476 ppgtt->switch_mm = vgpu_mm_switch;
1477
Ben Widawskyb1465202014-02-19 22:05:49 -08001478 ret = gen6_ppgtt_alloc(ppgtt);
1479 if (ret)
1480 return ret;
1481
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001482 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001483 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1484 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02001485 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1486 ppgtt->base.bind_vma = ppgtt_bind_vma;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001487 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
Ben Widawsky686e1f62013-11-25 09:54:34 -08001488 ppgtt->base.start = 0;
Michel Thierry09942c62015-04-08 12:13:30 +01001489 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
Ben Widawskyb1465202014-02-19 22:05:49 -08001490 ppgtt->debug_dump = gen6_dump_ppgtt;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001491
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001492 ppgtt->pd.base.ggtt_offset =
Michel Thierry07749ef2015-03-16 16:00:54 +00001493 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001494
Ben Widawsky678d96f2015-03-16 16:00:56 +00001495 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001496 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001497
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001498 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001499
Ben Widawsky678d96f2015-03-16 16:00:56 +00001500 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1501
Thierry Reding440fd522015-01-23 09:05:06 +01001502 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001503 ppgtt->node.size >> 20,
1504 ppgtt->node.start / PAGE_SIZE);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001505
Daniel Vetterfa76da32014-08-06 20:19:54 +02001506 DRM_DEBUG("Adding PPGTT at offset %x\n",
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001507 ppgtt->pd.base.ggtt_offset << 10);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001508
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001509 return 0;
Daniel Vetter3440d262013-01-24 13:49:56 -08001510}
1511
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001512static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter3440d262013-01-24 13:49:56 -08001515
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001516 ppgtt->base.dev = dev;
Ben Widawsky8407bb92014-03-08 11:58:16 -08001517 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
Daniel Vetter3440d262013-01-24 13:49:56 -08001518
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001519 if (INTEL_INFO(dev)->gen < 8)
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001520 return gen6_ppgtt_init(ppgtt);
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001521 else
Michel Thierryd7b26332015-04-08 12:13:34 +01001522 return gen8_ppgtt_init(ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001523}
1524int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1525{
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 int ret = 0;
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001528
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001529 ret = __hw_ppgtt_init(dev, ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001530 if (ret == 0) {
Ben Widawskyc7c48df2013-12-06 14:11:15 -08001531 kref_init(&ppgtt->ref);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001532 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1533 ppgtt->base.total);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001534 i915_init_vm(dev_priv, &ppgtt->base);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001535 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001536
1537 return ret;
1538}
1539
Daniel Vetter82460d92014-08-06 20:19:53 +02001540int i915_ppgtt_init_hw(struct drm_device *dev)
1541{
Thomas Daniel671b50132014-08-20 16:24:50 +01001542 /* In the case of execlists, PPGTT is enabled by the context descriptor
1543 * and the PDPs are contained within the context itself. We don't
1544 * need to do anything here. */
1545 if (i915.enable_execlists)
1546 return 0;
1547
Daniel Vetter82460d92014-08-06 20:19:53 +02001548 if (!USES_PPGTT(dev))
1549 return 0;
1550
1551 if (IS_GEN6(dev))
1552 gen6_ppgtt_enable(dev);
1553 else if (IS_GEN7(dev))
1554 gen7_ppgtt_enable(dev);
1555 else if (INTEL_INFO(dev)->gen >= 8)
1556 gen8_ppgtt_enable(dev);
1557 else
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01001558 MISSING_CASE(INTEL_INFO(dev)->gen);
Daniel Vetter82460d92014-08-06 20:19:53 +02001559
John Harrison4ad2fd82015-06-18 13:11:20 +01001560 return 0;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001561}
John Harrison4ad2fd82015-06-18 13:11:20 +01001562
John Harrisonb3dd6b92015-05-29 17:43:40 +01001563int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
John Harrison4ad2fd82015-06-18 13:11:20 +01001564{
John Harrisonb3dd6b92015-05-29 17:43:40 +01001565 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
John Harrison4ad2fd82015-06-18 13:11:20 +01001566 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1567
1568 if (i915.enable_execlists)
1569 return 0;
1570
1571 if (!ppgtt)
1572 return 0;
1573
John Harrisone85b26d2015-05-29 17:43:56 +01001574 return ppgtt->switch_mm(ppgtt, req);
John Harrison4ad2fd82015-06-18 13:11:20 +01001575}
1576
Daniel Vetter4d884702014-08-06 15:04:47 +02001577struct i915_hw_ppgtt *
1578i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1579{
1580 struct i915_hw_ppgtt *ppgtt;
1581 int ret;
1582
1583 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1584 if (!ppgtt)
1585 return ERR_PTR(-ENOMEM);
1586
1587 ret = i915_ppgtt_init(dev, ppgtt);
1588 if (ret) {
1589 kfree(ppgtt);
1590 return ERR_PTR(ret);
1591 }
1592
1593 ppgtt->file_priv = fpriv;
1594
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001595 trace_i915_ppgtt_create(&ppgtt->base);
1596
Daniel Vetter4d884702014-08-06 15:04:47 +02001597 return ppgtt;
1598}
1599
Daniel Vetteree960be2014-08-06 15:04:45 +02001600void i915_ppgtt_release(struct kref *kref)
1601{
1602 struct i915_hw_ppgtt *ppgtt =
1603 container_of(kref, struct i915_hw_ppgtt, ref);
1604
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001605 trace_i915_ppgtt_release(&ppgtt->base);
1606
Daniel Vetteree960be2014-08-06 15:04:45 +02001607 /* vmas should already be unbound */
1608 WARN_ON(!list_empty(&ppgtt->base.active_list));
1609 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1610
Daniel Vetter19dd1202014-08-06 15:04:55 +02001611 list_del(&ppgtt->base.global_link);
1612 drm_mm_takedown(&ppgtt->base.mm);
1613
Daniel Vetteree960be2014-08-06 15:04:45 +02001614 ppgtt->base.cleanup(&ppgtt->base);
1615 kfree(ppgtt);
1616}
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001617
Ben Widawskya81cc002013-01-18 12:30:31 -08001618extern int intel_iommu_gfx_mapped;
1619/* Certain Gen5 chipsets require require idling the GPU before
1620 * unmapping anything from the GTT when VT-d is enabled.
1621 */
Daniel Vetter2c642b02015-04-14 17:35:26 +02001622static bool needs_idle_maps(struct drm_device *dev)
Ben Widawskya81cc002013-01-18 12:30:31 -08001623{
1624#ifdef CONFIG_INTEL_IOMMU
1625 /* Query intel_iommu to see if we need the workaround. Presumably that
1626 * was loaded first.
1627 */
1628 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1629 return true;
1630#endif
1631 return false;
1632}
1633
Ben Widawsky5c042282011-10-17 15:51:55 -07001634static bool do_idling(struct drm_i915_private *dev_priv)
1635{
1636 bool ret = dev_priv->mm.interruptible;
1637
Ben Widawskya81cc002013-01-18 12:30:31 -08001638 if (unlikely(dev_priv->gtt.do_idle_maps)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001639 dev_priv->mm.interruptible = false;
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001640 if (i915_gpu_idle(dev_priv->dev)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001641 DRM_ERROR("Couldn't idle GPU\n");
1642 /* Wait a bit, in hopes it avoids the hang */
1643 udelay(10);
1644 }
1645 }
1646
1647 return ret;
1648}
1649
1650static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1651{
Ben Widawskya81cc002013-01-18 12:30:31 -08001652 if (unlikely(dev_priv->gtt.do_idle_maps))
Ben Widawsky5c042282011-10-17 15:51:55 -07001653 dev_priv->mm.interruptible = interruptible;
1654}
1655
Ben Widawsky828c7902013-10-16 09:21:30 -07001656void i915_check_and_clear_faults(struct drm_device *dev)
1657{
1658 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001659 struct intel_engine_cs *ring;
Ben Widawsky828c7902013-10-16 09:21:30 -07001660 int i;
1661
1662 if (INTEL_INFO(dev)->gen < 6)
1663 return;
1664
1665 for_each_ring(ring, dev_priv, i) {
1666 u32 fault_reg;
1667 fault_reg = I915_READ(RING_FAULT_REG(ring));
1668 if (fault_reg & RING_FAULT_VALID) {
1669 DRM_DEBUG_DRIVER("Unexpected fault\n"
Paulo Zanoni59a5d292014-10-30 15:52:45 -02001670 "\tAddr: 0x%08lx\n"
Ben Widawsky828c7902013-10-16 09:21:30 -07001671 "\tAddress space: %s\n"
1672 "\tSource ID: %d\n"
1673 "\tType: %d\n",
1674 fault_reg & PAGE_MASK,
1675 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1676 RING_FAULT_SRCID(fault_reg),
1677 RING_FAULT_FAULT_TYPE(fault_reg));
1678 I915_WRITE(RING_FAULT_REG(ring),
1679 fault_reg & ~RING_FAULT_VALID);
1680 }
1681 }
1682 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1683}
1684
Chris Wilson91e56492014-09-25 10:13:12 +01001685static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1686{
1687 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1688 intel_gtt_chipset_flush();
1689 } else {
1690 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1691 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1692 }
1693}
1694
Ben Widawsky828c7902013-10-16 09:21:30 -07001695void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1696{
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 /* Don't bother messing with faults pre GEN6 as we have little
1700 * documentation supporting that it's a good idea.
1701 */
1702 if (INTEL_INFO(dev)->gen < 6)
1703 return;
1704
1705 i915_check_and_clear_faults(dev);
1706
1707 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001708 dev_priv->gtt.base.start,
1709 dev_priv->gtt.base.total,
Daniel Vettere568af12014-03-26 20:08:20 +01001710 true);
Chris Wilson91e56492014-09-25 10:13:12 +01001711
1712 i915_ggtt_flush(dev_priv);
Ben Widawsky828c7902013-10-16 09:21:30 -07001713}
1714
Daniel Vetter74163902012-02-15 23:50:21 +01001715int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001716{
Chris Wilson9da3da62012-06-01 15:20:22 +01001717 if (obj->has_dma_mapping)
Daniel Vetter74163902012-02-15 23:50:21 +01001718 return 0;
Chris Wilson9da3da62012-06-01 15:20:22 +01001719
1720 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1721 obj->pages->sgl, obj->pages->nents,
1722 PCI_DMA_BIDIRECTIONAL))
1723 return -ENOSPC;
1724
1725 return 0;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001726}
1727
Daniel Vetter2c642b02015-04-14 17:35:26 +02001728static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001729{
1730#ifdef writeq
1731 writeq(pte, addr);
1732#else
1733 iowrite32((u32)pte, addr);
1734 iowrite32(pte >> 32, addr + 4);
1735#endif
1736}
1737
1738static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1739 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001740 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301741 enum i915_cache_level level, u32 unused)
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001742{
1743 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001744 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001745 gen8_pte_t __iomem *gtt_entries =
1746 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001747 int i = 0;
1748 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001749 dma_addr_t addr = 0; /* shut up gcc */
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001750
1751 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1752 addr = sg_dma_address(sg_iter.sg) +
1753 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1754 gen8_set_pte(&gtt_entries[i],
1755 gen8_pte_encode(addr, level, true));
1756 i++;
1757 }
1758
1759 /*
1760 * XXX: This serves as a posting read to make sure that the PTE has
1761 * actually been updated. There is some concern that even though
1762 * registers and PTEs are within the same BAR that they are potentially
1763 * of NUMA access patterns. Therefore, even with the way we assume
1764 * hardware should work, we must keep this posting read for paranoia.
1765 */
1766 if (i != 0)
1767 WARN_ON(readq(&gtt_entries[i-1])
1768 != gen8_pte_encode(addr, level, true));
1769
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001770 /* This next bit makes the above posting read even more important. We
1771 * want to flush the TLBs only after we're certain all the PTE updates
1772 * have finished.
1773 */
1774 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1775 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001776}
1777
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001778/*
1779 * Binds an object into the global gtt with the specified cache level. The object
1780 * will be accessible to the GPU via commands whose operands reference offsets
1781 * within the global GTT as well as accessible by the GPU through the GMADR
1782 * mapped BAR (dev_priv->mm.gtt->gtt).
1783 */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001784static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001785 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001786 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301787 enum i915_cache_level level, u32 flags)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001788{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001789 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001790 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001791 gen6_pte_t __iomem *gtt_entries =
1792 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Imre Deak6e995e22013-02-18 19:28:04 +02001793 int i = 0;
1794 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001795 dma_addr_t addr = 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001796
Imre Deak6e995e22013-02-18 19:28:04 +02001797 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
Imre Deak2db76d72013-03-26 15:14:18 +02001798 addr = sg_page_iter_dma_address(&sg_iter);
Akash Goel24f3a8c2014-06-17 10:59:42 +05301799 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
Imre Deak6e995e22013-02-18 19:28:04 +02001800 i++;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001801 }
1802
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001803 /* XXX: This serves as a posting read to make sure that the PTE has
1804 * actually been updated. There is some concern that even though
1805 * registers and PTEs are within the same BAR that they are potentially
1806 * of NUMA access patterns. Therefore, even with the way we assume
1807 * hardware should work, we must keep this posting read for paranoia.
1808 */
Pavel Machek57007df2014-07-28 13:20:58 +02001809 if (i != 0) {
1810 unsigned long gtt = readl(&gtt_entries[i-1]);
1811 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1812 }
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001813
1814 /* This next bit makes the above posting read even more important. We
1815 * want to flush the TLBs only after we're certain all the PTE updates
1816 * have finished.
1817 */
1818 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1819 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001820}
1821
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001822static void gen8_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001823 uint64_t start,
1824 uint64_t length,
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001825 bool use_scratch)
1826{
1827 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001828 unsigned first_entry = start >> PAGE_SHIFT;
1829 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001830 gen8_pte_t scratch_pte, __iomem *gtt_base =
1831 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001832 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1833 int i;
1834
1835 if (WARN(num_entries > max_entries,
1836 "First entry = %d; Num entries = %d (max=%d)\n",
1837 first_entry, num_entries, max_entries))
1838 num_entries = max_entries;
1839
1840 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1841 I915_CACHE_LLC,
1842 use_scratch);
1843 for (i = 0; i < num_entries; i++)
1844 gen8_set_pte(&gtt_base[i], scratch_pte);
1845 readl(gtt_base);
1846}
1847
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001848static void gen6_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001849 uint64_t start,
1850 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001851 bool use_scratch)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001852{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001853 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001854 unsigned first_entry = start >> PAGE_SHIFT;
1855 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001856 gen6_pte_t scratch_pte, __iomem *gtt_base =
1857 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawskya54c0c22013-01-24 14:45:00 -08001858 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001859 int i;
1860
1861 if (WARN(num_entries > max_entries,
1862 "First entry = %d; Num entries = %d (max=%d)\n",
1863 first_entry, num_entries, max_entries))
1864 num_entries = max_entries;
1865
Akash Goel24f3a8c2014-06-17 10:59:42 +05301866 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
Ben Widawsky828c7902013-10-16 09:21:30 -07001867
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001868 for (i = 0; i < num_entries; i++)
1869 iowrite32(scratch_pte, &gtt_base[i]);
1870 readl(gtt_base);
1871}
1872
Daniel Vetterd369d2d2015-04-14 17:35:25 +02001873static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1874 struct sg_table *pages,
1875 uint64_t start,
1876 enum i915_cache_level cache_level, u32 unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001877{
1878 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1879 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1880
Daniel Vetterd369d2d2015-04-14 17:35:25 +02001881 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
Daniel Vetter08755462015-04-20 09:04:05 -07001882
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001883}
1884
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001885static void i915_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001886 uint64_t start,
1887 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001888 bool unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001889{
Ben Widawsky782f1492014-02-20 11:50:33 -08001890 unsigned first_entry = start >> PAGE_SHIFT;
1891 unsigned num_entries = length >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001892 intel_gtt_clear_range(first_entry, num_entries);
1893}
1894
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02001895static int ggtt_bind_vma(struct i915_vma *vma,
1896 enum i915_cache_level cache_level,
1897 u32 flags)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001898{
Ben Widawsky6f65e292013-12-06 14:10:56 -08001899 struct drm_device *dev = vma->vm->dev;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001900 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001901 struct drm_i915_gem_object *obj = vma->obj;
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02001902 struct sg_table *pages = obj->pages;
Daniel Vetterf329f5f2015-04-14 17:35:15 +02001903 u32 pte_flags = 0;
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02001904 int ret;
1905
1906 ret = i915_get_ggtt_vma_pages(vma);
1907 if (ret)
1908 return ret;
1909 pages = vma->ggtt_view.pages;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001910
Akash Goel24f3a8c2014-06-17 10:59:42 +05301911 /* Currently applicable only to VLV */
1912 if (obj->gt_ro)
Daniel Vetterf329f5f2015-04-14 17:35:15 +02001913 pte_flags |= PTE_READ_ONLY;
Akash Goel24f3a8c2014-06-17 10:59:42 +05301914
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02001915
Ben Widawsky6f65e292013-12-06 14:10:56 -08001916 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
Daniel Vetter08755462015-04-20 09:04:05 -07001917 vma->vm->insert_entries(vma->vm, pages,
1918 vma->node.start,
1919 cache_level, pte_flags);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001920 }
Daniel Vetter74898d72012-02-15 23:50:22 +01001921
Daniel Vetter08755462015-04-20 09:04:05 -07001922 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08001923 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02001924 appgtt->base.insert_entries(&appgtt->base, pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08001925 vma->node.start,
Daniel Vetterf329f5f2015-04-14 17:35:15 +02001926 cache_level, pte_flags);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001927 }
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02001928
1929 return 0;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001930}
1931
1932static void ggtt_unbind_vma(struct i915_vma *vma)
1933{
1934 struct drm_device *dev = vma->vm->dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct drm_i915_gem_object *obj = vma->obj;
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03001937 const uint64_t size = min_t(uint64_t,
1938 obj->base.size,
1939 vma->node.size);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001940
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001941 if (vma->bound & GLOBAL_BIND) {
Ben Widawsky782f1492014-02-20 11:50:33 -08001942 vma->vm->clear_range(vma->vm,
1943 vma->node.start,
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03001944 size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08001945 true);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001946 }
1947
Daniel Vetter08755462015-04-20 09:04:05 -07001948 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08001949 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03001950
Ben Widawsky6f65e292013-12-06 14:10:56 -08001951 appgtt->base.clear_range(&appgtt->base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001952 vma->node.start,
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03001953 size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08001954 true);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001955 }
Daniel Vetter74163902012-02-15 23:50:21 +01001956}
1957
1958void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1959{
Ben Widawsky5c042282011-10-17 15:51:55 -07001960 struct drm_device *dev = obj->base.dev;
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 bool interruptible;
1963
1964 interruptible = do_idling(dev_priv);
1965
Chris Wilson9da3da62012-06-01 15:20:22 +01001966 if (!obj->has_dma_mapping)
1967 dma_unmap_sg(&dev->pdev->dev,
1968 obj->pages->sgl, obj->pages->nents,
1969 PCI_DMA_BIDIRECTIONAL);
Ben Widawsky5c042282011-10-17 15:51:55 -07001970
1971 undo_idling(dev_priv, interruptible);
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001972}
Daniel Vetter644ec022012-03-26 09:45:40 +02001973
Chris Wilson42d6ab42012-07-26 11:49:32 +01001974static void i915_gtt_color_adjust(struct drm_mm_node *node,
1975 unsigned long color,
Thierry Reding440fd522015-01-23 09:05:06 +01001976 u64 *start,
1977 u64 *end)
Chris Wilson42d6ab42012-07-26 11:49:32 +01001978{
1979 if (node->color != color)
1980 *start += 4096;
1981
1982 if (!list_empty(&node->node_list)) {
1983 node = list_entry(node->node_list.next,
1984 struct drm_mm_node,
1985 node_list);
1986 if (node->allocated && node->color != color)
1987 *end -= 4096;
1988 }
1989}
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001990
Daniel Vetterf548c0e2014-11-19 21:40:13 +01001991static int i915_gem_setup_global_gtt(struct drm_device *dev,
1992 unsigned long start,
1993 unsigned long mappable_end,
1994 unsigned long end)
Daniel Vetter644ec022012-03-26 09:45:40 +02001995{
Ben Widawskye78891c2013-01-25 16:41:04 -08001996 /* Let GEM Manage all of the aperture.
1997 *
1998 * However, leave one page at the end still bound to the scratch page.
1999 * There are a number of places where the hardware apparently prefetches
2000 * past the end of the object, and we've seen multiple hangs with the
2001 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2002 * aperture. One page should be enough to keep any prefetching inside
2003 * of the aperture.
2004 */
Ben Widawsky40d749802013-07-31 16:59:59 -07002005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
Chris Wilsoned2f3452012-11-15 11:32:19 +00002007 struct drm_mm_node *entry;
2008 struct drm_i915_gem_object *obj;
2009 unsigned long hole_start, hole_end;
Daniel Vetterfa76da32014-08-06 20:19:54 +02002010 int ret;
Daniel Vetter644ec022012-03-26 09:45:40 +02002011
Ben Widawsky35451cb2013-01-17 12:45:13 -08002012 BUG_ON(mappable_end > end);
2013
Chris Wilsoned2f3452012-11-15 11:32:19 +00002014 /* Subtract the guard page ... */
Ben Widawsky40d749802013-07-31 16:59:59 -07002015 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
Yu Zhang5dda8fa2015-02-10 19:05:48 +08002016
2017 dev_priv->gtt.base.start = start;
2018 dev_priv->gtt.base.total = end - start;
2019
2020 if (intel_vgpu_active(dev)) {
2021 ret = intel_vgt_balloon(dev);
2022 if (ret)
2023 return ret;
2024 }
2025
Chris Wilson42d6ab42012-07-26 11:49:32 +01002026 if (!HAS_LLC(dev))
Ben Widawsky93bd8642013-07-16 16:50:06 -07002027 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
Daniel Vetter644ec022012-03-26 09:45:40 +02002028
Chris Wilsoned2f3452012-11-15 11:32:19 +00002029 /* Mark any preallocated objects as occupied */
Ben Widawsky35c20a62013-05-31 11:28:48 -07002030 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawsky40d749802013-07-31 16:59:59 -07002031 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
Daniel Vetterfa76da32014-08-06 20:19:54 +02002032
Ben Widawskyedd41a82013-07-05 14:41:05 -07002033 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
Ben Widawskyc6cfb322013-07-05 14:41:06 -07002034 i915_gem_obj_ggtt_offset(obj), obj->base.size);
Chris Wilsoned2f3452012-11-15 11:32:19 +00002035
Ben Widawskyc6cfb322013-07-05 14:41:06 -07002036 WARN_ON(i915_gem_obj_ggtt_bound(obj));
Ben Widawsky40d749802013-07-31 16:59:59 -07002037 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002038 if (ret) {
2039 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2040 return ret;
2041 }
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01002042 vma->bound |= GLOBAL_BIND;
Chris Wilsoned2f3452012-11-15 11:32:19 +00002043 }
2044
Chris Wilsoned2f3452012-11-15 11:32:19 +00002045 /* Clear any non-preallocated blocks */
Ben Widawsky40d749802013-07-31 16:59:59 -07002046 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
Chris Wilsoned2f3452012-11-15 11:32:19 +00002047 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2048 hole_start, hole_end);
Ben Widawsky782f1492014-02-20 11:50:33 -08002049 ggtt_vm->clear_range(ggtt_vm, hole_start,
2050 hole_end - hole_start, true);
Chris Wilsoned2f3452012-11-15 11:32:19 +00002051 }
2052
2053 /* And finally clear the reserved guard page */
Ben Widawsky782f1492014-02-20 11:50:33 -08002054 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002055
Daniel Vetterfa76da32014-08-06 20:19:54 +02002056 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2057 struct i915_hw_ppgtt *ppgtt;
2058
2059 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2060 if (!ppgtt)
2061 return -ENOMEM;
2062
Daniel Vetter5c5f6452015-04-14 17:35:14 +02002063 ret = __hw_ppgtt_init(dev, ppgtt);
Michel Thierry4933d512015-03-24 15:46:22 +00002064 if (ret) {
Daniel Vetter061dd492015-04-14 17:35:13 +02002065 ppgtt->base.cleanup(&ppgtt->base);
Michel Thierry4933d512015-03-24 15:46:22 +00002066 kfree(ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02002067 return ret;
Michel Thierry4933d512015-03-24 15:46:22 +00002068 }
Daniel Vetterfa76da32014-08-06 20:19:54 +02002069
Daniel Vetter5c5f6452015-04-14 17:35:14 +02002070 if (ppgtt->base.allocate_va_range)
2071 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2072 ppgtt->base.total);
2073 if (ret) {
2074 ppgtt->base.cleanup(&ppgtt->base);
2075 kfree(ppgtt);
2076 return ret;
2077 }
2078
2079 ppgtt->base.clear_range(&ppgtt->base,
2080 ppgtt->base.start,
2081 ppgtt->base.total,
2082 true);
2083
Daniel Vetterfa76da32014-08-06 20:19:54 +02002084 dev_priv->mm.aliasing_ppgtt = ppgtt;
2085 }
2086
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002087 return 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002088}
2089
Ben Widawskyd7e50082012-12-18 10:31:25 -08002090void i915_gem_init_global_gtt(struct drm_device *dev)
2091{
2092 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002093 u64 gtt_size, mappable_size;
Ben Widawskyd7e50082012-12-18 10:31:25 -08002094
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002095 gtt_size = dev_priv->gtt.base.total;
Ben Widawsky93d18792013-01-17 12:45:17 -08002096 mappable_size = dev_priv->gtt.mappable_end;
Ben Widawskyd7e50082012-12-18 10:31:25 -08002097
Ben Widawskye78891c2013-01-25 16:41:04 -08002098 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002099}
2100
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002101void i915_global_gtt_cleanup(struct drm_device *dev)
2102{
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct i915_address_space *vm = &dev_priv->gtt.base;
2105
Daniel Vetter70e32542014-08-06 15:04:57 +02002106 if (dev_priv->mm.aliasing_ppgtt) {
2107 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2108
2109 ppgtt->base.cleanup(&ppgtt->base);
2110 }
2111
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002112 if (drm_mm_initialized(&vm->mm)) {
Yu Zhang5dda8fa2015-02-10 19:05:48 +08002113 if (intel_vgpu_active(dev))
2114 intel_vgt_deballoon();
2115
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002116 drm_mm_takedown(&vm->mm);
2117 list_del(&vm->global_link);
2118 }
2119
2120 vm->cleanup(vm);
2121}
Daniel Vetter70e32542014-08-06 15:04:57 +02002122
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002123static int setup_scratch_page(struct drm_device *dev)
2124{
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct page *page;
2127 dma_addr_t dma_addr;
2128
2129 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2130 if (page == NULL)
2131 return -ENOMEM;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002132 set_pages_uc(page, 1);
2133
2134#ifdef CONFIG_INTEL_IOMMU
2135 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2136 PCI_DMA_BIDIRECTIONAL);
Mika Kuoppalaea3f5d22015-05-22 20:04:58 +03002137 if (pci_dma_mapping_error(dev->pdev, dma_addr)) {
2138 __free_page(page);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002139 return -EINVAL;
Mika Kuoppalaea3f5d22015-05-22 20:04:58 +03002140 }
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002141#else
2142 dma_addr = page_to_phys(page);
2143#endif
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002144 dev_priv->gtt.base.scratch.page = page;
2145 dev_priv->gtt.base.scratch.addr = dma_addr;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002146
2147 return 0;
2148}
2149
2150static void teardown_scratch_page(struct drm_device *dev)
2151{
2152 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002153 struct page *page = dev_priv->gtt.base.scratch.page;
2154
2155 set_pages_wb(page, 1);
2156 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002157 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002158 __free_page(page);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002159}
2160
Daniel Vetter2c642b02015-04-14 17:35:26 +02002161static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002162{
2163 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2164 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2165 return snb_gmch_ctl << 20;
2166}
2167
Daniel Vetter2c642b02015-04-14 17:35:26 +02002168static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
Ben Widawsky9459d252013-11-03 16:53:55 -08002169{
2170 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2171 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2172 if (bdw_gmch_ctl)
2173 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
Ben Widawsky562d55d2014-05-27 16:53:08 -07002174
2175#ifdef CONFIG_X86_32
2176 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2177 if (bdw_gmch_ctl > 4)
2178 bdw_gmch_ctl = 4;
2179#endif
2180
Ben Widawsky9459d252013-11-03 16:53:55 -08002181 return bdw_gmch_ctl << 20;
2182}
2183
Daniel Vetter2c642b02015-04-14 17:35:26 +02002184static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002185{
2186 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2187 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2188
2189 if (gmch_ctrl)
2190 return 1 << (20 + gmch_ctrl);
2191
2192 return 0;
2193}
2194
Daniel Vetter2c642b02015-04-14 17:35:26 +02002195static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002196{
2197 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2198 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2199 return snb_gmch_ctl << 25; /* 32 MB units */
2200}
2201
Daniel Vetter2c642b02015-04-14 17:35:26 +02002202static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
Ben Widawsky9459d252013-11-03 16:53:55 -08002203{
2204 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2205 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2206 return bdw_gmch_ctl << 25; /* 32 MB units */
2207}
2208
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002209static size_t chv_get_stolen_size(u16 gmch_ctrl)
2210{
2211 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2212 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2213
2214 /*
2215 * 0x0 to 0x10: 32MB increments starting at 0MB
2216 * 0x11 to 0x16: 4MB increments starting at 8MB
2217 * 0x17 to 0x1d: 4MB increments start at 36MB
2218 */
2219 if (gmch_ctrl < 0x11)
2220 return gmch_ctrl << 25;
2221 else if (gmch_ctrl < 0x17)
2222 return (gmch_ctrl - 0x11 + 2) << 22;
2223 else
2224 return (gmch_ctrl - 0x17 + 9) << 22;
2225}
2226
Damien Lespiau66375012014-01-09 18:02:46 +00002227static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2228{
2229 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2230 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2231
2232 if (gen9_gmch_ctl < 0xf0)
2233 return gen9_gmch_ctl << 25; /* 32 MB units */
2234 else
2235 /* 4MB increments starting at 0xf0 for 4MB */
2236 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2237}
2238
Ben Widawsky63340132013-11-04 19:32:22 -08002239static int ggtt_probe_common(struct drm_device *dev,
2240 size_t gtt_size)
2241{
2242 struct drm_i915_private *dev_priv = dev->dev_private;
Bjorn Helgaas21c34602013-12-21 10:52:52 -07002243 phys_addr_t gtt_phys_addr;
Ben Widawsky63340132013-11-04 19:32:22 -08002244 int ret;
2245
2246 /* For Modern GENs the PTEs and register space are split in the BAR */
Bjorn Helgaas21c34602013-12-21 10:52:52 -07002247 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
Ben Widawsky63340132013-11-04 19:32:22 -08002248 (pci_resource_len(dev->pdev, 0) / 2);
2249
Imre Deak2a073f892015-03-27 13:07:33 +02002250 /*
2251 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2252 * dropped. For WC mappings in general we have 64 byte burst writes
2253 * when the WC buffer is flushed, so we can't use it, but have to
2254 * resort to an uncached mapping. The WC issue is easily caught by the
2255 * readback check when writing GTT PTE entries.
2256 */
2257 if (IS_BROXTON(dev))
2258 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2259 else
2260 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
Ben Widawsky63340132013-11-04 19:32:22 -08002261 if (!dev_priv->gtt.gsm) {
2262 DRM_ERROR("Failed to map the gtt page table\n");
2263 return -ENOMEM;
2264 }
2265
2266 ret = setup_scratch_page(dev);
2267 if (ret) {
2268 DRM_ERROR("Scratch setup failed\n");
2269 /* iounmap will also get called at remove, but meh */
2270 iounmap(dev_priv->gtt.gsm);
2271 }
2272
2273 return ret;
2274}
2275
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002276/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2277 * bits. When using advanced contexts each context stores its own PAT, but
2278 * writing this data shouldn't be harmful even in those cases. */
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002279static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002280{
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002281 uint64_t pat;
2282
2283 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2284 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2285 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2286 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2287 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2288 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2289 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2290 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2291
Rodrigo Vivid6a8b722014-11-05 16:56:36 -08002292 if (!USES_PPGTT(dev_priv->dev))
2293 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2294 * so RTL will always use the value corresponding to
2295 * pat_sel = 000".
2296 * So let's disable cache for GGTT to avoid screen corruptions.
2297 * MOCS still can be used though.
2298 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2299 * before this patch, i.e. the same uncached + snooping access
2300 * like on gen6/7 seems to be in effect.
2301 * - So this just fixes blitter/render access. Again it looks
2302 * like it's not just uncached access, but uncached + snooping.
2303 * So we can still hold onto all our assumptions wrt cpu
2304 * clflushing on LLC machines.
2305 */
2306 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2307
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002308 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2309 * write would work. */
2310 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2311 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2312}
2313
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002314static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2315{
2316 uint64_t pat;
2317
2318 /*
2319 * Map WB on BDW to snooped on CHV.
2320 *
2321 * Only the snoop bit has meaning for CHV, the rest is
2322 * ignored.
2323 *
Ville Syrjäläcf3d2622014-11-14 21:02:44 +02002324 * The hardware will never snoop for certain types of accesses:
2325 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2326 * - PPGTT page tables
2327 * - some other special cycles
2328 *
2329 * As with BDW, we also need to consider the following for GT accesses:
2330 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2331 * so RTL will always use the value corresponding to
2332 * pat_sel = 000".
2333 * Which means we must set the snoop bit in PAT entry 0
2334 * in order to keep the global status page working.
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002335 */
2336 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2337 GEN8_PPAT(1, 0) |
2338 GEN8_PPAT(2, 0) |
2339 GEN8_PPAT(3, 0) |
2340 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2341 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2342 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2343 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2344
2345 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2346 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2347}
2348
Ben Widawsky63340132013-11-04 19:32:22 -08002349static int gen8_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002350 u64 *gtt_total,
Ben Widawsky63340132013-11-04 19:32:22 -08002351 size_t *stolen,
2352 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002353 u64 *mappable_end)
Ben Widawsky63340132013-11-04 19:32:22 -08002354{
2355 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002356 u64 gtt_size;
Ben Widawsky63340132013-11-04 19:32:22 -08002357 u16 snb_gmch_ctl;
2358 int ret;
2359
2360 /* TODO: We're not aware of mappable constraints on gen8 yet */
2361 *mappable_base = pci_resource_start(dev->pdev, 2);
2362 *mappable_end = pci_resource_len(dev->pdev, 2);
2363
2364 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2365 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2366
2367 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2368
Damien Lespiau66375012014-01-09 18:02:46 +00002369 if (INTEL_INFO(dev)->gen >= 9) {
2370 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2371 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2372 } else if (IS_CHERRYVIEW(dev)) {
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002373 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2374 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2375 } else {
2376 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2377 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2378 }
Ben Widawsky63340132013-11-04 19:32:22 -08002379
Michel Thierry07749ef2015-03-16 16:00:54 +00002380 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
Ben Widawsky63340132013-11-04 19:32:22 -08002381
Sumit Singh5a4e33a2015-03-17 11:39:31 +02002382 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002383 chv_setup_private_ppat(dev_priv);
2384 else
2385 bdw_setup_private_ppat(dev_priv);
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002386
Ben Widawsky63340132013-11-04 19:32:22 -08002387 ret = ggtt_probe_common(dev, gtt_size);
2388
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002389 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2390 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002391 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2392 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawsky63340132013-11-04 19:32:22 -08002393
2394 return ret;
2395}
2396
Ben Widawskybaa09f52013-01-24 13:49:57 -08002397static int gen6_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002398 u64 *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002399 size_t *stolen,
2400 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002401 u64 *mappable_end)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002402{
2403 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002404 unsigned int gtt_size;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002405 u16 snb_gmch_ctl;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002406 int ret;
2407
Ben Widawsky41907dd2013-02-08 11:32:47 -08002408 *mappable_base = pci_resource_start(dev->pdev, 2);
2409 *mappable_end = pci_resource_len(dev->pdev, 2);
2410
Ben Widawskybaa09f52013-01-24 13:49:57 -08002411 /* 64/512MB is the current min/max we actually know of, but this is just
2412 * a coarse sanity check.
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002413 */
Ben Widawsky41907dd2013-02-08 11:32:47 -08002414 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002415 DRM_ERROR("Unknown GMADR size (%llx)\n",
Ben Widawskybaa09f52013-01-24 13:49:57 -08002416 dev_priv->gtt.mappable_end);
2417 return -ENXIO;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002418 }
2419
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002420 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2421 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
Ben Widawskybaa09f52013-01-24 13:49:57 -08002422 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002423
Ben Widawskyc4ae25e2013-05-01 11:00:34 -07002424 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002425
Ben Widawsky63340132013-11-04 19:32:22 -08002426 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
Michel Thierry07749ef2015-03-16 16:00:54 +00002427 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002428
Ben Widawsky63340132013-11-04 19:32:22 -08002429 ret = ggtt_probe_common(dev, gtt_size);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002430
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002431 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2432 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002433 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2434 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002435
2436 return ret;
2437}
2438
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002439static void gen6_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002440{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002441
2442 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
Ben Widawsky5ed16782013-11-25 09:54:43 -08002443
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002444 iounmap(gtt->gsm);
2445 teardown_scratch_page(vm->dev);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002446}
2447
2448static int i915_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002449 u64 *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002450 size_t *stolen,
2451 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002452 u64 *mappable_end)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002453{
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 int ret;
2456
Ben Widawskybaa09f52013-01-24 13:49:57 -08002457 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2458 if (!ret) {
2459 DRM_ERROR("failed to set up gmch\n");
2460 return -EIO;
2461 }
2462
Ben Widawsky41907dd2013-02-08 11:32:47 -08002463 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002464
2465 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002466 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002467 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002468 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2469 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002470
Chris Wilsonc0a7f812013-12-30 12:16:15 +00002471 if (unlikely(dev_priv->gtt.do_idle_maps))
2472 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2473
Ben Widawskybaa09f52013-01-24 13:49:57 -08002474 return 0;
2475}
2476
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002477static void i915_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002478{
2479 intel_gmch_remove();
2480}
2481
2482int i915_gem_gtt_init(struct drm_device *dev)
2483{
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 struct i915_gtt *gtt = &dev_priv->gtt;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002486 int ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002487
Ben Widawskybaa09f52013-01-24 13:49:57 -08002488 if (INTEL_INFO(dev)->gen <= 5) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002489 gtt->gtt_probe = i915_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002490 gtt->base.cleanup = i915_gmch_remove;
Ben Widawsky63340132013-11-04 19:32:22 -08002491 } else if (INTEL_INFO(dev)->gen < 8) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002492 gtt->gtt_probe = gen6_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002493 gtt->base.cleanup = gen6_gmch_remove;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002494 if (IS_HASWELL(dev) && dev_priv->ellc_size)
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002495 gtt->base.pte_encode = iris_pte_encode;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002496 else if (IS_HASWELL(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002497 gtt->base.pte_encode = hsw_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002498 else if (IS_VALLEYVIEW(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002499 gtt->base.pte_encode = byt_pte_encode;
Chris Wilson350ec882013-08-06 13:17:02 +01002500 else if (INTEL_INFO(dev)->gen >= 7)
2501 gtt->base.pte_encode = ivb_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002502 else
Chris Wilson350ec882013-08-06 13:17:02 +01002503 gtt->base.pte_encode = snb_pte_encode;
Ben Widawsky63340132013-11-04 19:32:22 -08002504 } else {
2505 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2506 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002507 }
2508
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002509 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002510 &gtt->mappable_base, &gtt->mappable_end);
Ben Widawskya54c0c22013-01-24 14:45:00 -08002511 if (ret)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002512 return ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002513
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002514 gtt->base.dev = dev;
2515
Ben Widawskybaa09f52013-01-24 13:49:57 -08002516 /* GMADR is the PCI mmio aperture into the global GTT. */
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002517 DRM_INFO("Memory usable by graphics device = %lluM\n",
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002518 gtt->base.total >> 20);
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002519 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002520 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
Daniel Vetter5db6c732014-03-31 16:23:04 +02002521#ifdef CONFIG_INTEL_IOMMU
2522 if (intel_iommu_gfx_mapped)
2523 DRM_INFO("VT-d active for gfx access\n");
2524#endif
Daniel Vettercfa7c862014-04-29 11:53:58 +02002525 /*
2526 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2527 * user's requested state against the hardware/driver capabilities. We
2528 * do this now so that we can print out any log messages once rather
2529 * than every time we check intel_enable_ppgtt().
2530 */
2531 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2532 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002533
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002534 return 0;
Daniel Vetter644ec022012-03-26 09:45:40 +02002535}
Ben Widawsky6f65e292013-12-06 14:10:56 -08002536
Daniel Vetterfa423312015-04-14 17:35:23 +02002537void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2538{
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct drm_i915_gem_object *obj;
2541 struct i915_address_space *vm;
2542
2543 i915_check_and_clear_faults(dev);
2544
2545 /* First fill our portion of the GTT with scratch pages */
2546 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2547 dev_priv->gtt.base.start,
2548 dev_priv->gtt.base.total,
2549 true);
2550
2551 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2552 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2553 &dev_priv->gtt.base);
2554 if (!vma)
2555 continue;
2556
2557 i915_gem_clflush_object(obj, obj->pin_display);
2558 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2559 }
2560
2561
2562 if (INTEL_INFO(dev)->gen >= 8) {
2563 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2564 chv_setup_private_ppat(dev_priv);
2565 else
2566 bdw_setup_private_ppat(dev_priv);
2567
2568 return;
2569 }
2570
2571 if (USES_PPGTT(dev)) {
2572 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2573 /* TODO: Perhaps it shouldn't be gen6 specific */
2574
2575 struct i915_hw_ppgtt *ppgtt =
2576 container_of(vm, struct i915_hw_ppgtt,
2577 base);
2578
2579 if (i915_is_ggtt(vm))
2580 ppgtt = dev_priv->mm.aliasing_ppgtt;
2581
2582 gen6_write_page_range(dev_priv, &ppgtt->pd,
2583 0, ppgtt->base.total);
2584 }
2585 }
2586
2587 i915_ggtt_flush(dev_priv);
2588}
2589
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002590static struct i915_vma *
2591__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2592 struct i915_address_space *vm,
2593 const struct i915_ggtt_view *ggtt_view)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002594{
Dan Carpenterdabde5c2015-03-18 11:21:58 +03002595 struct i915_vma *vma;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002596
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002597 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2598 return ERR_PTR(-EINVAL);
Chris Wilsone20d2ab2015-04-07 16:20:58 +01002599
2600 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
Dan Carpenterdabde5c2015-03-18 11:21:58 +03002601 if (vma == NULL)
2602 return ERR_PTR(-ENOMEM);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002603
Ben Widawsky6f65e292013-12-06 14:10:56 -08002604 INIT_LIST_HEAD(&vma->vma_link);
2605 INIT_LIST_HEAD(&vma->mm_list);
2606 INIT_LIST_HEAD(&vma->exec_list);
2607 vma->vm = vm;
2608 vma->obj = obj;
2609
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002610 if (i915_is_ggtt(vm))
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002611 vma->ggtt_view = *ggtt_view;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002612
Tvrtko Ursulinf7635662014-12-03 14:59:24 +00002613 list_add_tail(&vma->vma_link, &obj->vma_list);
2614 if (!i915_is_ggtt(vm))
Michel Thierrye07f0552014-08-19 15:49:41 +01002615 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
Ben Widawsky6f65e292013-12-06 14:10:56 -08002616
2617 return vma;
2618}
2619
2620struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002621i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2622 struct i915_address_space *vm)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002623{
2624 struct i915_vma *vma;
2625
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002626 vma = i915_gem_obj_to_vma(obj, vm);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002627 if (!vma)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002628 vma = __i915_gem_vma_create(obj, vm,
2629 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002630
2631 return vma;
2632}
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002633
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002634struct i915_vma *
2635i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2636 const struct i915_ggtt_view *view)
2637{
2638 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2639 struct i915_vma *vma;
2640
2641 if (WARN_ON(!view))
2642 return ERR_PTR(-EINVAL);
2643
2644 vma = i915_gem_obj_to_ggtt_view(obj, view);
2645
2646 if (IS_ERR(vma))
2647 return vma;
2648
2649 if (!vma)
2650 vma = __i915_gem_vma_create(obj, ggtt, view);
2651
2652 return vma;
2653
2654}
2655
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002656static void
2657rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2658 struct sg_table *st)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002659{
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002660 unsigned int column, row;
2661 unsigned int src_idx;
2662 struct scatterlist *sg = st->sgl;
2663
2664 st->nents = 0;
2665
2666 for (column = 0; column < width; column++) {
2667 src_idx = width * (height - 1) + column;
2668 for (row = 0; row < height; row++) {
2669 st->nents++;
2670 /* We don't need the pages, but need to initialize
2671 * the entries so the sg list can be happily traversed.
2672 * The only thing we need are DMA addresses.
2673 */
2674 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2675 sg_dma_address(sg) = in[src_idx];
2676 sg_dma_len(sg) = PAGE_SIZE;
2677 sg = sg_next(sg);
2678 src_idx -= width;
2679 }
2680 }
2681}
2682
2683static struct sg_table *
2684intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2685 struct drm_i915_gem_object *obj)
2686{
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002687 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002688 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002689 struct sg_page_iter sg_iter;
2690 unsigned long i;
2691 dma_addr_t *page_addr_list;
2692 struct sg_table *st;
Tvrtko Ursulin1d00dad2015-03-25 10:15:26 +00002693 int ret = -ENOMEM;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002694
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002695 /* Allocate a temporary list of source pages for random access. */
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002696 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2697 sizeof(dma_addr_t));
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002698 if (!page_addr_list)
2699 return ERR_PTR(ret);
2700
2701 /* Allocate target SG list. */
2702 st = kmalloc(sizeof(*st), GFP_KERNEL);
2703 if (!st)
2704 goto err_st_alloc;
2705
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002706 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002707 if (ret)
2708 goto err_sg_alloc;
2709
2710 /* Populate source page list from the object. */
2711 i = 0;
2712 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2713 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2714 i++;
2715 }
2716
2717 /* Rotate the pages. */
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002718 rotate_pages(page_addr_list,
2719 rot_info->width_pages, rot_info->height_pages,
2720 st);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002721
2722 DRM_DEBUG_KMS(
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002723 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
Tvrtko Ursulinc9f8fd22015-06-24 09:55:20 +01002724 obj->base.size, rot_info->pitch, rot_info->height,
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002725 rot_info->pixel_format, rot_info->width_pages,
2726 rot_info->height_pages, size_pages);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002727
2728 drm_free_large(page_addr_list);
2729
2730 return st;
2731
2732err_sg_alloc:
2733 kfree(st);
2734err_st_alloc:
2735 drm_free_large(page_addr_list);
2736
2737 DRM_DEBUG_KMS(
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002738 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
Tvrtko Ursulinc9f8fd22015-06-24 09:55:20 +01002739 obj->base.size, ret, rot_info->pitch, rot_info->height,
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002740 rot_info->pixel_format, rot_info->width_pages,
2741 rot_info->height_pages, size_pages);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002742 return ERR_PTR(ret);
2743}
2744
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03002745static struct sg_table *
2746intel_partial_pages(const struct i915_ggtt_view *view,
2747 struct drm_i915_gem_object *obj)
2748{
2749 struct sg_table *st;
2750 struct scatterlist *sg;
2751 struct sg_page_iter obj_sg_iter;
2752 int ret = -ENOMEM;
2753
2754 st = kmalloc(sizeof(*st), GFP_KERNEL);
2755 if (!st)
2756 goto err_st_alloc;
2757
2758 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2759 if (ret)
2760 goto err_sg_alloc;
2761
2762 sg = st->sgl;
2763 st->nents = 0;
2764 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2765 view->params.partial.offset)
2766 {
2767 if (st->nents >= view->params.partial.size)
2768 break;
2769
2770 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2771 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2772 sg_dma_len(sg) = PAGE_SIZE;
2773
2774 sg = sg_next(sg);
2775 st->nents++;
2776 }
2777
2778 return st;
2779
2780err_sg_alloc:
2781 kfree(st);
2782err_st_alloc:
2783 return ERR_PTR(ret);
2784}
2785
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002786static int
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002787i915_get_ggtt_vma_pages(struct i915_vma *vma)
2788{
2789 int ret = 0;
2790
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002791 if (vma->ggtt_view.pages)
2792 return 0;
2793
2794 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2795 vma->ggtt_view.pages = vma->obj->pages;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002796 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2797 vma->ggtt_view.pages =
2798 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03002799 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2800 vma->ggtt_view.pages =
2801 intel_partial_pages(&vma->ggtt_view, vma->obj);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002802 else
2803 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2804 vma->ggtt_view.type);
2805
2806 if (!vma->ggtt_view.pages) {
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002807 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002808 vma->ggtt_view.type);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002809 ret = -EINVAL;
2810 } else if (IS_ERR(vma->ggtt_view.pages)) {
2811 ret = PTR_ERR(vma->ggtt_view.pages);
2812 vma->ggtt_view.pages = NULL;
2813 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2814 vma->ggtt_view.type, ret);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002815 }
2816
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002817 return ret;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002818}
2819
2820/**
2821 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2822 * @vma: VMA to map
2823 * @cache_level: mapping cache level
2824 * @flags: flags like global or local mapping
2825 *
2826 * DMA addresses are taken from the scatter-gather table of this object (or of
2827 * this VMA in case of non-default GGTT views) and PTE entries set up.
2828 * Note that DMA addresses are also the only part of the SG table we care about.
2829 */
2830int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2831 u32 flags)
2832{
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002833 int ret;
2834 u32 bind_flags;
Mika Kuoppala1d335d12015-04-10 15:54:58 +03002835
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002836 if (WARN_ON(flags == 0))
2837 return -EINVAL;
Mika Kuoppala1d335d12015-04-10 15:54:58 +03002838
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002839 bind_flags = 0;
Daniel Vetter08755462015-04-20 09:04:05 -07002840 if (flags & PIN_GLOBAL)
2841 bind_flags |= GLOBAL_BIND;
2842 if (flags & PIN_USER)
2843 bind_flags |= LOCAL_BIND;
2844
2845 if (flags & PIN_UPDATE)
2846 bind_flags |= vma->bound;
2847 else
2848 bind_flags &= ~vma->bound;
2849
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002850 if (bind_flags == 0)
2851 return 0;
2852
2853 if (vma->bound == 0 && vma->vm->allocate_va_range) {
2854 trace_i915_va_alloc(vma->vm,
2855 vma->node.start,
2856 vma->node.size,
2857 VM_TO_TRACE_NAME(vma->vm));
2858
2859 ret = vma->vm->allocate_va_range(vma->vm,
2860 vma->node.start,
2861 vma->node.size);
2862 if (ret)
2863 return ret;
2864 }
2865
2866 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002867 if (ret)
2868 return ret;
Daniel Vetter08755462015-04-20 09:04:05 -07002869
2870 vma->bound |= bind_flags;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002871
2872 return 0;
2873}
Joonas Lahtinen91e67112015-05-06 14:33:58 +03002874
2875/**
2876 * i915_ggtt_view_size - Get the size of a GGTT view.
2877 * @obj: Object the view is of.
2878 * @view: The view in question.
2879 *
2880 * @return The size of the GGTT view in bytes.
2881 */
2882size_t
2883i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2884 const struct i915_ggtt_view *view)
2885{
Tvrtko Ursulin9e759ff2015-06-23 12:57:43 +01002886 if (view->type == I915_GGTT_VIEW_NORMAL) {
Joonas Lahtinen91e67112015-05-06 14:33:58 +03002887 return obj->base.size;
Tvrtko Ursulin9e759ff2015-06-23 12:57:43 +01002888 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
2889 return view->rotation_info.size;
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03002890 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2891 return view->params.partial.size << PAGE_SHIFT;
Joonas Lahtinen91e67112015-05-06 14:33:58 +03002892 } else {
2893 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2894 return obj->base.size;
2895 }
2896}