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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Ken Zhang420dd202013-01-08 14:28:20 -05004 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070053#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Kalyan Thota9284a272012-11-02 20:55:30 +053074#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053075#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
Ken Zhang4e83b932012-12-02 21:15:47 -050076 struct mdp_display_commit)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053077#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
Ken Zhang420dd202013-01-08 14:28:20 -050078#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Deva Ramasubramanian166b0982013-01-25 20:11:41 -080079#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
80 unsigned int)
Terence Hampson3e636aa2013-05-08 19:01:51 -040081#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
Kuogee Hsieha77eca62012-09-13 13:22:04 -070082
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070083#define FB_TYPE_3D_PANEL 0x10101010
84#define MDP_IMGTYPE2_START 0x10000
85#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070086
87enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088 NOTIFY_UPDATE_START,
89 NOTIFY_UPDATE_STOP,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -070090 NOTIFY_UPDATE_POWER_OFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070091};
92
93enum {
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070094 NOTIFY_TYPE_NO_UPDATE,
95 NOTIFY_TYPE_SUSPEND,
96 NOTIFY_TYPE_UPDATE,
97};
98
99enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100 MDP_RGB_565, /* RGB 565 planer */
101 MDP_XRGB_8888, /* RGB 888 padded */
102 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +0530103 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104 MDP_ARGB_8888, /* ARGB 888 */
105 MDP_RGB_888, /* RGB 888 planer */
106 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
107 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
Pawan Kumar42acdef2013-03-21 19:55:49 +0530108 MDP_CBYCRY_H2V1, /* CbYCrY interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700109 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
110 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700111 MDP_Y_CRCB_H1V2,
112 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700113 MDP_RGBA_8888, /* ARGB 888 */
114 MDP_BGRA_8888, /* ABGR 888 */
115 MDP_RGBX_8888, /* RGBX 888 */
116 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
117 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
118 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530119 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700120 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
121 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
122 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700123 MDP_YCRCB_H1V1, /* YCrCb interleave */
124 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700125 MDP_BGR_565, /* BGR 565 planer */
Adrian Salido-Morenod559ef12012-07-12 20:16:14 -0700126 MDP_BGR_888, /* BGR 888 */
Adrian Salido-Moreno330c0bf2012-08-22 14:15:33 -0700127 MDP_Y_CBCR_H2V2_VENUS,
Pawan Kumar79854382013-02-14 15:27:12 +0530128 MDP_BGRX_8888, /* BGRX 8888 */
Shalabh Jainbea586a2013-08-23 12:30:48 -0700129 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */
130 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */
131 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */
132 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */
133 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */
134 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */
135 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */
136 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700137 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800138 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700139 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700140 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700141};
142
143enum {
144 PMEM_IMG,
145 FB_IMG,
146};
147
Liyuan Lid9736632011-11-11 13:47:59 -0800148enum {
149 HSIC_HUE = 0,
150 HSIC_SAT,
151 HSIC_INT,
152 HSIC_CON,
153 NUM_HSIC_PARAM,
154};
155
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700156#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700157#define MDSS_MDP_RIGHT_MIXER 0x100
158
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700159/* mdp_blit_req flag values */
160#define MDP_ROT_NOP 0
161#define MDP_FLIP_LR 0x1
162#define MDP_FLIP_UD 0x2
163#define MDP_ROT_90 0x4
164#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
165#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
166#define MDP_DITHER 0x8
167#define MDP_BLUR 0x10
168#define MDP_BLEND_FG_PREMULT 0x20000
Padmanabhan Komandurudd10bf12012-10-17 20:27:33 +0530169#define MDP_IS_FG 0x40000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700170#define MDP_DEINTERLACE 0x80000000
171#define MDP_SHARPENING 0x40000000
172#define MDP_NO_DMA_BARRIER_START 0x20000000
173#define MDP_NO_DMA_BARRIER_END 0x10000000
174#define MDP_NO_BLIT 0x08000000
175#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
176#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
177 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
178#define MDP_BLIT_SRC_GEM 0x04000000
179#define MDP_BLIT_DST_GEM 0x02000000
180#define MDP_BLIT_NON_CACHED 0x01000000
181#define MDP_OV_PIPE_SHARE 0x00800000
182#define MDP_DEINTERLACE_ODD 0x00400000
183#define MDP_OV_PLAY_NOWAIT 0x00200000
184#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700185#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530186#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800187#define MDP_BORDERFILL_SUPPORTED 0x00010000
188#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Adrian Salido-Moreno9a8485c2013-02-06 14:08:28 -0800189#define MDP_OV_PIPE_FORCE_DMA 0x00004000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800190#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Sree Sesha Aravind Vadrevu35143132013-03-12 02:32:06 -0700191#define MDP_BWC_EN 0x00000400
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700192#define MDP_DECIMATION_EN 0x00000800
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700193#define MDP_TRANSP_NOP 0xffffffff
194#define MDP_ALPHA_NOP 0xff
195
196#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
197#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
198#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
199#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
200#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
201/* Sentinel: Don't use! */
202#define MDP_FB_PAGE_PROTECTION_INVALID (5)
203/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
204#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700205
206struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700207 uint32_t x;
208 uint32_t y;
209 uint32_t w;
210 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700211};
212
213struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700214 uint32_t width;
215 uint32_t height;
216 uint32_t format;
217 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700218 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700219 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700220};
221
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700222/*
223 * {3x3} + {3} ccs matrix
224 */
225
226#define MDP_CCS_RGB2YUV 0
227#define MDP_CCS_YUV2RGB 1
228
229#define MDP_CCS_SIZE 9
230#define MDP_BV_SIZE 3
231
232struct mdp_ccs {
233 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
234 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
235 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
236};
237
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800238struct mdp_csc {
239 int id;
240 uint32_t csc_mv[9];
241 uint32_t csc_pre_bv[3];
242 uint32_t csc_post_bv[3];
243 uint32_t csc_pre_lv[6];
244 uint32_t csc_post_lv[6];
245};
246
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700247/* The version of the mdp_blit_req structure so that
248 * user applications can selectively decide which functionality
249 * to include
250 */
251
252#define MDP_BLIT_REQ_VERSION 2
253
Daniel Walkerda6df072010-04-23 16:04:20 -0700254struct mdp_blit_req {
255 struct mdp_img src;
256 struct mdp_img dst;
257 struct mdp_rect src_rect;
258 struct mdp_rect dst_rect;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700259 uint32_t alpha;
260 uint32_t transp_mask;
261 uint32_t flags;
262 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700263};
264
265struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700266 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700267 struct mdp_blit_req req[];
268};
269
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270#define MSMFB_DATA_VERSION 2
271
272struct msmfb_data {
273 uint32_t offset;
274 int memory_id;
275 int id;
276 uint32_t flags;
277 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800278 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700279};
280
281#define MSMFB_NEW_REQUEST -1
282
283struct msmfb_overlay_data {
284 uint32_t id;
285 struct msmfb_data data;
286 uint32_t version_key;
287 struct msmfb_data plane1_data;
288 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700289 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700290};
291
292struct msmfb_img {
293 uint32_t width;
294 uint32_t height;
295 uint32_t format;
296};
297
Vinay Kalia27020d12011-10-14 17:50:29 -0700298#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
299struct msmfb_writeback_data {
300 struct msmfb_data buf_info;
301 struct msmfb_img img;
302};
303
Ken Zhang77ce0192012-08-10 11:27:19 -0400304#define MDP_PP_OPS_ENABLE 0x1
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700305#define MDP_PP_OPS_READ 0x2
306#define MDP_PP_OPS_WRITE 0x4
Ken Zhang77ce0192012-08-10 11:27:19 -0400307#define MDP_PP_OPS_DISABLE 0x8
Ken Zhang824758e2012-08-15 11:02:21 -0400308#define MDP_PP_IGC_FLAG_ROM0 0x10
309#define MDP_PP_IGC_FLAG_ROM1 0x20
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700310
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700311#define MDSS_PP_DSPP_CFG 0x000
312#define MDSS_PP_SSPP_CFG 0x100
313#define MDSS_PP_LM_CFG 0x200
314#define MDSS_PP_WB_CFG 0x300
Ping Li8231ae42013-01-09 20:39:25 -0500315
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700316#define MDSS_PP_ARG_MASK 0x3C00
317#define MDSS_PP_ARG_NUM 4
Carl Vanderlip793aa582013-03-18 10:18:47 -0700318#define MDSS_PP_ARG_SHIFT 10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700319#define MDSS_PP_LOCATION_MASK 0x0300
320#define MDSS_PP_LOGICAL_MASK 0x00FF
Ping Li8231ae42013-01-09 20:39:25 -0500321
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700322#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
323#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
Ping Li8231ae42013-01-09 20:39:25 -0500324#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
325#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
326
327
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700328struct mdp_qseed_cfg {
329 uint32_t table_num;
330 uint32_t ops;
331 uint32_t len;
332 uint32_t *data;
333};
334
Ping Li87cca832013-01-30 18:27:52 -0500335struct mdp_sharp_cfg {
336 uint32_t flags;
337 uint32_t strength;
338 uint32_t edge_thr;
339 uint32_t smooth_thr;
340 uint32_t noise_thr;
341};
342
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700343struct mdp_qseed_cfg_data {
344 uint32_t block;
345 struct mdp_qseed_cfg qseed_data;
346};
347
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800348#define MDP_OVERLAY_PP_CSC_CFG 0x1
349#define MDP_OVERLAY_PP_QSEED_CFG 0x2
350#define MDP_OVERLAY_PP_PA_CFG 0x4
351#define MDP_OVERLAY_PP_IGC_CFG 0x8
Ping Li87cca832013-01-30 18:27:52 -0500352#define MDP_OVERLAY_PP_SHARP_CFG 0x10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700353#define MDP_OVERLAY_PP_HIST_CFG 0x20
Carl Vanderlip57027132013-03-18 13:53:16 -0700354#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700355
356#define MDP_CSC_FLAG_ENABLE 0x1
357#define MDP_CSC_FLAG_YUV_IN 0x2
358#define MDP_CSC_FLAG_YUV_OUT 0x4
359
360struct mdp_csc_cfg {
361 /* flags for enable CSC, toggling RGB,YUV input/output */
362 uint32_t flags;
363 uint32_t csc_mv[9];
364 uint32_t csc_pre_bv[3];
365 uint32_t csc_post_bv[3];
366 uint32_t csc_pre_lv[6];
367 uint32_t csc_post_lv[6];
368};
369
370struct mdp_csc_cfg_data {
371 uint32_t block;
372 struct mdp_csc_cfg csc_data;
373};
374
Ping Li58229242012-11-30 14:05:43 -0500375struct mdp_pa_cfg {
376 uint32_t flags;
377 uint32_t hue_adj;
378 uint32_t sat_adj;
379 uint32_t val_adj;
380 uint32_t cont_adj;
381};
382
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800383struct mdp_igc_lut_data {
384 uint32_t block;
385 uint32_t len, ops;
386 uint32_t *c0_c1_data;
387 uint32_t *c2_data;
388};
389
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700390struct mdp_histogram_cfg {
391 uint32_t ops;
392 uint32_t block;
393 uint8_t frame_cnt;
394 uint8_t bit_mask;
395 uint16_t num_bins;
396};
397
Carl Vanderlip57027132013-03-18 13:53:16 -0700398struct mdp_hist_lut_data {
399 uint32_t block;
400 uint32_t ops;
401 uint32_t len;
402 uint32_t *data;
403};
404
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700405struct mdp_overlay_pp_params {
406 uint32_t config_ops;
407 struct mdp_csc_cfg csc_cfg;
408 struct mdp_qseed_cfg qseed_cfg[2];
Ping Li58229242012-11-30 14:05:43 -0500409 struct mdp_pa_cfg pa_cfg;
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800410 struct mdp_igc_lut_data igc_cfg;
Ping Li87cca832013-01-30 18:27:52 -0500411 struct mdp_sharp_cfg sharp_cfg;
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700412 struct mdp_histogram_cfg hist_cfg;
Carl Vanderlip57027132013-03-18 13:53:16 -0700413 struct mdp_hist_lut_data hist_lut_cfg;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700414};
415
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530416/**
417 * enum mdss_mdp_blend_op - Different blend operations set by userspace
418 *
419 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
420 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
421 * would appear opaque in case fg plane alpha is
422 * 0xff.
423 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has
424 * alpha pre-multiplication done. If fg plane alpha
425 * is less than 0xff, apply modulation as well. This
426 * operation is intended on layers having alpha
427 * channel.
428 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha
429 * pre-multiplied. Apply pre-multiplication. If fg
430 * plane alpha is less than 0xff, apply modulation as
431 * well.
432 * @BLEND_OP_MAX: Used to track maximum blend operation possible by
433 * mdp.
434 */
435enum mdss_mdp_blend_op {
436 BLEND_OP_NOT_DEFINED = 0,
437 BLEND_OP_OPAQUE,
438 BLEND_OP_PREMULTIPLIED,
439 BLEND_OP_COVERAGE,
440 BLEND_OP_MAX,
441};
442
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700443struct mdp_overlay {
444 struct msmfb_img src;
445 struct mdp_rect src_rect;
446 struct mdp_rect dst_rect;
447 uint32_t z_order; /* stage number */
448 uint32_t is_fg; /* control alpha & transp */
449 uint32_t alpha;
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530450 uint32_t blend_op;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700451 uint32_t transp_mask;
452 uint32_t flags;
453 uint32_t id;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700454 uint32_t user_data[7];
455 uint8_t horz_deci;
456 uint8_t vert_deci;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700457 struct mdp_overlay_pp_params overlay_pp_cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700458};
459
460struct msmfb_overlay_3d {
461 uint32_t is_3d;
462 uint32_t width;
463 uint32_t height;
464};
465
466
467struct msmfb_overlay_blt {
468 uint32_t enable;
469 uint32_t offset;
470 uint32_t width;
471 uint32_t height;
472 uint32_t bpp;
473};
474
475struct mdp_histogram {
476 uint32_t frame_cnt;
477 uint32_t bin_cnt;
478 uint32_t *r;
479 uint32_t *g;
480 uint32_t *b;
481};
482
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700483enum {
484 DISPLAY_MISR_EDP,
485 DISPLAY_MISR_DSI0,
486 DISPLAY_MISR_DSI1,
487 DISPLAY_MISR_HDMI,
488 DISPLAY_MISR_LCDC,
489 DISPLAY_MISR_ATV,
490 DISPLAY_MISR_DSI_CMD,
491 DISPLAY_MISR_MAX
492};
493
494enum {
495 MISR_OP_NONE,
496 MISR_OP_SFM,
497 MISR_OP_MFM,
498 MISR_OP_BM,
499 MISR_OP_MAX
500};
501
502struct mdp_misr {
503 uint32_t block_id;
504 uint32_t frame_count;
505 uint32_t crc_op_mode;
506 uint32_t crc_value[32];
507};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800508
509/*
510
Ken Zhang6a431632012-08-08 16:46:22 -0400511 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800512
513 MDP_BLOCK_RESERVED is provided for backward compatibility and is
514 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
515 instead.
516
Ken Zhang6a431632012-08-08 16:46:22 -0400517 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
518 same for others.
519
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800520*/
521
522enum {
523 MDP_BLOCK_RESERVED = 0,
524 MDP_BLOCK_OVERLAY_0,
525 MDP_BLOCK_OVERLAY_1,
526 MDP_BLOCK_VG_1,
527 MDP_BLOCK_VG_2,
528 MDP_BLOCK_RGB_1,
529 MDP_BLOCK_RGB_2,
530 MDP_BLOCK_DMA_P,
531 MDP_BLOCK_DMA_S,
532 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700533 MDP_BLOCK_OVERLAY_2,
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700534 MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
Ken Zhang6a431632012-08-08 16:46:22 -0400535 MDP_LOGICAL_BLOCK_DISP_1,
536 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800537 MDP_BLOCK_MAX,
538};
539
Carl Vanderlipba093a22011-11-22 13:59:59 -0800540/*
541 * mdp_histogram_start_req is used to provide the parameters for
542 * histogram start request
543 */
544
545struct mdp_histogram_start_req {
546 uint32_t block;
547 uint8_t frame_cnt;
548 uint8_t bit_mask;
Carl Vanderlip16316322012-10-08 16:47:34 -0700549 uint16_t num_bins;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800550};
551
552/*
553 * mdp_histogram_data is used to return the histogram data, once
554 * the histogram is done/stopped/cance
555 */
556
557struct mdp_histogram_data {
558 uint32_t block;
Ken Zhang0f523bd2012-08-23 11:14:03 -0400559 uint32_t bin_cnt;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800560 uint32_t *c0;
561 uint32_t *c1;
562 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800563 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800564};
565
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800566struct mdp_pcc_coeff {
567 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
568};
569
570struct mdp_pcc_cfg_data {
571 uint32_t block;
572 uint32_t ops;
573 struct mdp_pcc_coeff r, g, b;
574};
575
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400576#define MDP_GAMUT_TABLE_NUM 8
577
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800578enum {
579 mdp_lut_igc,
580 mdp_lut_pgc,
581 mdp_lut_hist,
582 mdp_lut_max,
583};
584
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800585struct mdp_ar_gc_lut_data {
586 uint32_t x_start;
587 uint32_t slope;
588 uint32_t offset;
589};
590
591struct mdp_pgc_lut_data {
592 uint32_t block;
593 uint32_t flags;
594 uint8_t num_r_stages;
595 uint8_t num_g_stages;
596 uint8_t num_b_stages;
597 struct mdp_ar_gc_lut_data *r_data;
598 struct mdp_ar_gc_lut_data *g_data;
599 struct mdp_ar_gc_lut_data *b_data;
600};
601
602
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800603struct mdp_lut_cfg_data {
604 uint32_t lut_type;
605 union {
606 struct mdp_igc_lut_data igc_lut_data;
607 struct mdp_pgc_lut_data pgc_lut_data;
608 struct mdp_hist_lut_data hist_lut_data;
609 } data;
610};
611
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700612struct mdp_bl_scale_data {
613 uint32_t min_lvl;
614 uint32_t scale;
615};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700616
Ken Zhang77ce0192012-08-10 11:27:19 -0400617struct mdp_pa_cfg_data {
618 uint32_t block;
Ping Li58229242012-11-30 14:05:43 -0500619 struct mdp_pa_cfg pa_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400620};
621
Ken Zhang7fb85772012-08-18 14:51:33 -0400622struct mdp_dither_cfg_data {
623 uint32_t block;
624 uint32_t flags;
625 uint32_t g_y_depth;
626 uint32_t r_cr_depth;
627 uint32_t b_cb_depth;
628};
629
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400630struct mdp_gamut_cfg_data {
631 uint32_t block;
632 uint32_t flags;
633 uint32_t gamut_first;
634 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
635 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
636 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
637 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
638};
639
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700640struct mdp_calib_config_data {
641 uint32_t ops;
642 uint32_t addr;
643 uint32_t data;
644};
645
Arpita Banerjee676eea22013-06-04 19:43:24 -0700646struct mdp_calib_config_buffer {
647 uint32_t ops;
648 uint32_t size;
649 uint32_t *buffer;
650};
651
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700652struct mdp_calib_dcm_state {
653 uint32_t ops;
654 uint32_t dcm_state;
655};
656
657enum {
658 DCM_UNINIT,
659 DCM_UNBLANK,
660 DCM_ENTER,
661 DCM_EXIT,
662 DCM_BLANK,
663};
664
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700665#define MDSS_MAX_BL_BRIGHTNESS 255
666#define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1)
667
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700668#define MDSS_AD_MODE_AUTO_BL 0x0
669#define MDSS_AD_MODE_AUTO_STR 0x1
670#define MDSS_AD_MODE_TARG_STR 0x3
671#define MDSS_AD_MODE_MAN_STR 0x7
Carl Vanderlip819c5092013-05-19 12:08:33 -0700672#define MDSS_AD_MODE_CALIB 0xF
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700673
674#define MDP_PP_AD_INIT 0x10
675#define MDP_PP_AD_CFG 0x20
676
677struct mdss_ad_init {
678 uint32_t asym_lut[33];
679 uint32_t color_corr_lut[33];
680 uint8_t i_control[2];
681 uint16_t black_lvl;
682 uint16_t white_lvl;
683 uint8_t var;
684 uint8_t limit_ampl;
685 uint8_t i_dither;
686 uint8_t slope_max;
687 uint8_t slope_min;
688 uint8_t dither_ctl;
689 uint8_t format;
690 uint8_t auto_size;
691 uint16_t frame_w;
692 uint16_t frame_h;
693 uint8_t logo_v;
694 uint8_t logo_h;
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700695 uint32_t bl_lin_len;
696 uint32_t *bl_lin;
697 uint32_t *bl_lin_inv;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700698};
699
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700700#define MDSS_AD_BL_CTRL_MODE_EN 1
701#define MDSS_AD_BL_CTRL_MODE_DIS 0
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700702struct mdss_ad_cfg {
703 uint32_t mode;
704 uint32_t al_calib_lut[33];
705 uint16_t backlight_min;
706 uint16_t backlight_max;
707 uint16_t backlight_scale;
708 uint16_t amb_light_min;
709 uint16_t filter[2];
710 uint16_t calib[4];
711 uint8_t strength_limit;
712 uint8_t t_filter_recursion;
Carl Vanderlip956360e2013-04-04 20:57:17 -0700713 uint16_t stab_itr;
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700714 uint32_t bl_ctrl_mode;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700715};
716
717/* ops uses standard MDP_PP_* flags */
718struct mdss_ad_init_cfg {
719 uint32_t ops;
720 union {
721 struct mdss_ad_init init;
722 struct mdss_ad_cfg cfg;
723 } params;
724};
725
726/* mode uses MDSS_AD_MODE_* flags */
727struct mdss_ad_input {
728 uint32_t mode;
729 union {
730 uint32_t amb_light;
731 uint32_t strength;
Carl Vanderlip819c5092013-05-19 12:08:33 -0700732 uint32_t calib_bl;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700733 } in;
Carl Vanderlip16e79532013-04-02 11:12:16 -0700734 uint32_t output;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700735};
736
Carl Vanderlipa088b7c2013-05-17 13:52:53 -0700737#define MDSS_CALIB_MODE_BL 0x1
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700738struct mdss_calib_cfg {
739 uint32_t ops;
740 uint32_t calib_mask;
741};
742
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800743enum {
744 mdp_op_pcc_cfg,
745 mdp_op_csc_cfg,
746 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700747 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700748 mdp_bl_scale_cfg,
Ken Zhang77ce0192012-08-10 11:27:19 -0400749 mdp_op_pa_cfg,
Ken Zhang7fb85772012-08-18 14:51:33 -0400750 mdp_op_dither_cfg,
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400751 mdp_op_gamut_cfg,
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700752 mdp_op_calib_cfg,
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700753 mdp_op_ad_cfg,
754 mdp_op_ad_input,
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700755 mdp_op_calib_mode,
Arpita Banerjee676eea22013-06-04 19:43:24 -0700756 mdp_op_calib_buffer,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700757 mdp_op_calib_dcm_state,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800758 mdp_op_max,
759};
760
Pawan Kumar9807ea12013-02-14 18:12:02 +0530761enum {
762 WB_FORMAT_NV12,
763 WB_FORMAT_RGB_565,
764 WB_FORMAT_RGB_888,
765 WB_FORMAT_xRGB_8888,
766 WB_FORMAT_ARGB_8888,
Pawan Kumaree811932013-07-09 15:45:01 +0530767 WB_FORMAT_BGRA_8888,
768 WB_FORMAT_BGRX_8888,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530769 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
770};
771
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800772struct msmfb_mdp_pp {
773 uint32_t op;
774 union {
775 struct mdp_pcc_cfg_data pcc_cfg_data;
776 struct mdp_csc_cfg_data csc_cfg_data;
777 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700778 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700779 struct mdp_bl_scale_data bl_scale_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400780 struct mdp_pa_cfg_data pa_cfg_data;
Ken Zhang7fb85772012-08-18 14:51:33 -0400781 struct mdp_dither_cfg_data dither_cfg_data;
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400782 struct mdp_gamut_cfg_data gamut_cfg_data;
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700783 struct mdp_calib_config_data calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700784 struct mdss_ad_init_cfg ad_init_cfg;
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700785 struct mdss_calib_cfg mdss_calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700786 struct mdss_ad_input ad_input;
Arpita Banerjee676eea22013-06-04 19:43:24 -0700787 struct mdp_calib_config_buffer calib_buffer;
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700788 struct mdp_calib_dcm_state calib_dcm;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800789 } data;
790};
791
Manoj Raoa8e39d92013-02-16 08:47:21 -0800792#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
Ken Zhang5cf85c02012-08-23 19:32:52 -0700793enum {
794 metadata_op_none,
795 metadata_op_base_blend,
Ken Zhang420dd202013-01-08 14:28:20 -0500796 metadata_op_frame_rate,
Manoj Raoa8e39d92013-02-16 08:47:21 -0800797 metadata_op_vic,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530798 metadata_op_wb_format,
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800799 metadata_op_get_caps,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700800 metadata_op_crc,
Ken Zhang5cf85c02012-08-23 19:32:52 -0700801 metadata_op_max
802};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800803
Ken Zhang5cf85c02012-08-23 19:32:52 -0700804struct mdp_blend_cfg {
805 uint32_t is_premultiplied;
806};
807
Pawan Kumar9807ea12013-02-14 18:12:02 +0530808struct mdp_mixer_cfg {
809 uint32_t writeback_format;
810 uint32_t alpha;
811};
812
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800813struct mdss_hw_caps {
814 uint32_t mdp_rev;
815 uint8_t rgb_pipes;
816 uint8_t vig_pipes;
817 uint8_t dma_pipes;
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700818 uint32_t features;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800819};
820
Ken Zhang5cf85c02012-08-23 19:32:52 -0700821struct msmfb_metadata {
822 uint32_t op;
823 uint32_t flags;
824 union {
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700825 struct mdp_misr misr_request;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700826 struct mdp_blend_cfg blend_cfg;
Pawan Kumar9807ea12013-02-14 18:12:02 +0530827 struct mdp_mixer_cfg mixer_cfg;
Ken Zhang420dd202013-01-08 14:28:20 -0500828 uint32_t panel_frame_rate;
Manoj Raoa8e39d92013-02-16 08:47:21 -0800829 uint32_t video_info_code;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800830 struct mdss_hw_caps caps;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700831 } data;
832};
Ken Zhang5295d802012-11-07 18:33:16 -0500833
Adrian Salido-Moreno1a74a492013-05-11 21:24:43 -0700834#define MDP_MAX_FENCE_FD 32
Ken Zhang5295d802012-11-07 18:33:16 -0500835#define MDP_BUF_SYNC_FLAG_WAIT 1
836
837struct mdp_buf_sync {
838 uint32_t flags;
839 uint32_t acq_fen_fd_cnt;
840 int *acq_fen_fd;
841 int *rel_fen_fd;
842};
843
Terence Hampson3e636aa2013-05-08 19:01:51 -0400844struct mdp_async_blit_req_list {
845 struct mdp_buf_sync sync;
846 uint32_t count;
847 struct mdp_blit_req req[];
848};
849
Ken Zhang4e83b932012-12-02 21:15:47 -0500850#define MDP_DISPLAY_COMMIT_OVERLAY 1
Ken Zhang5e8588d2012-10-01 11:46:42 -0700851struct mdp_buf_fence {
852 uint32_t flags;
853 uint32_t acq_fen_fd_cnt;
854 int acq_fen_fd[MDP_MAX_FENCE_FD];
855 int rel_fen_fd[MDP_MAX_FENCE_FD];
856};
857
Ken Zhang4e83b932012-12-02 21:15:47 -0500858
859struct mdp_display_commit {
860 uint32_t flags;
861 uint32_t wait_for_finish;
862 struct fb_var_screeninfo var;
Ken Zhang5e8588d2012-10-01 11:46:42 -0700863 struct mdp_buf_fence buf_fence;
Ken Zhang4e83b932012-12-02 21:15:47 -0500864};
865
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700866struct mdp_page_protection {
867 uint32_t page_protection;
868};
869
kuogee hsieh405dc302011-07-21 15:06:59 -0700870
871struct mdp_mixer_info {
872 int pndx;
873 int pnum;
874 int ptype;
875 int mixer_num;
876 int z_order;
877};
878
879#define MAX_PIPE_PER_MIXER 4
880
881struct msmfb_mixer_info_req {
882 int mixer_num;
883 int cnt;
884 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
885};
886
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700887enum {
888 DISPLAY_SUBSYSTEM_ID,
889 ROTATOR_SUBSYSTEM_ID,
890};
kuogee hsieh405dc302011-07-21 15:06:59 -0700891
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800892enum {
893 MDP_IOMMU_DOMAIN_CP,
894 MDP_IOMMU_DOMAIN_NS,
895};
896
Deva Ramasubramanian166b0982013-01-25 20:11:41 -0800897enum {
898 MDP_WRITEBACK_MIRROR_OFF,
899 MDP_WRITEBACK_MIRROR_ON,
900 MDP_WRITEBACK_MIRROR_PAUSE,
901 MDP_WRITEBACK_MIRROR_RESUME,
902};
903
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700904#ifdef __KERNEL__
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800905int msm_fb_get_iommu_domain(struct fb_info *info, int domain);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700906/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700907int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
908 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -0700909struct fb_info *msm_fb_get_writeback_fb(void);
910int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800911int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700912int msm_fb_writeback_queue_buffer(struct fb_info *info,
913 struct msmfb_data *data);
914int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
915 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800916int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700917int msm_fb_writeback_terminate(struct fb_info *info);
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800918int msm_fb_writeback_set_secure(struct fb_info *info, int enable);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700919#endif
920
921#endif /*_MSM_MDP_H_*/