sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2010 OpenWorks LLP |
| 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 37 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 41 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 42 | #include "libvex_guest_ppc64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 43 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 44 | #include "main_globals.h" |
| 45 | #include "main_util.h" |
| 46 | #include "host_generic_regs.h" |
| 47 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 48 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 49 | #include "host_x86_defs.h" |
| 50 | #include "host_amd64_defs.h" |
| 51 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 52 | #include "host_arm_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 53 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 54 | #include "guest_generic_bb_to_IR.h" |
| 55 | #include "guest_x86_defs.h" |
| 56 | #include "guest_amd64_defs.h" |
| 57 | #include "guest_arm_defs.h" |
| 58 | #include "guest_ppc_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 59 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame^] | 60 | #include "host_generic_simd128.h" |
| 61 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 62 | |
| 63 | /* This file contains the top level interface to the library. */ |
| 64 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 65 | /* --------- fwds ... --------- */ |
| 66 | |
| 67 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
| 68 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
| 69 | |
| 70 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 71 | /* --------- Initialise the library. --------- */ |
| 72 | |
| 73 | /* Exported to library client. */ |
| 74 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 75 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 76 | { |
| 77 | vcon->iropt_verbosity = 0; |
| 78 | vcon->iropt_level = 2; |
| 79 | vcon->iropt_precise_memory_exns = False; |
| 80 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 81 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 82 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 83 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | |
| 87 | /* Exported to library client. */ |
| 88 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 89 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 90 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 91 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 92 | void (*failure_exit) ( void ), |
| 93 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 94 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 95 | /* debug paranoia level */ |
| 96 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 97 | /* Are we supporting valgrind checking? */ |
| 98 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 99 | /* Control ... */ |
| 100 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 101 | ) |
| 102 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 103 | /* First off, do enough minimal setup so that the following |
| 104 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 105 | vex_failure_exit = failure_exit; |
| 106 | vex_log_bytes = log_bytes; |
| 107 | |
| 108 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 109 | vassert(!vex_initdone); |
| 110 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 111 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 112 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 113 | |
| 114 | vassert(vcon->iropt_verbosity >= 0); |
| 115 | vassert(vcon->iropt_level >= 0); |
| 116 | vassert(vcon->iropt_level <= 2); |
| 117 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 118 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 119 | vassert(vcon->guest_max_insns >= 1); |
| 120 | vassert(vcon->guest_max_insns <= 100); |
| 121 | vassert(vcon->guest_chase_thresh >= 0); |
| 122 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 123 | vassert(vcon->guest_chase_cond == True |
| 124 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 125 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 126 | /* Check that Vex has been built with sizes of basic types as |
| 127 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 128 | a serious configuration error and should be corrected |
| 129 | immediately. If any of these assertions fail you can fully |
| 130 | expect Vex not to work properly, if at all. */ |
| 131 | |
| 132 | vassert(1 == sizeof(UChar)); |
| 133 | vassert(1 == sizeof(Char)); |
| 134 | vassert(2 == sizeof(UShort)); |
| 135 | vassert(2 == sizeof(Short)); |
| 136 | vassert(4 == sizeof(UInt)); |
| 137 | vassert(4 == sizeof(Int)); |
| 138 | vassert(8 == sizeof(ULong)); |
| 139 | vassert(8 == sizeof(Long)); |
| 140 | vassert(4 == sizeof(Float)); |
| 141 | vassert(8 == sizeof(Double)); |
| 142 | vassert(1 == sizeof(Bool)); |
| 143 | vassert(4 == sizeof(Addr32)); |
| 144 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 145 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame^] | 146 | vassert(16 == sizeof(V128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 147 | |
| 148 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 149 | vassert(sizeof(void*) == sizeof(int*)); |
| 150 | vassert(sizeof(void*) == sizeof(HWord)); |
| 151 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 152 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 153 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 154 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 155 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 156 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 157 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 158 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 159 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 160 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | |
| 164 | /* --------- Make a translation. --------- */ |
| 165 | |
| 166 | /* Exported to library client. */ |
| 167 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 168 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 169 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 170 | /* This the bundle of functions we need to do the back-end stuff |
| 171 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 172 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 173 | HReg* available_real_regs; |
| 174 | Int n_available_real_regs; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 175 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 176 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 177 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 178 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 179 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 180 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
| 181 | void (*ppInstr) ( HInstr*, Bool ); |
| 182 | void (*ppReg) ( HReg ); |
| 183 | HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, |
| 184 | VexAbiInfo* ); |
| 185 | Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); |
| 186 | IRExpr* (*specHelper) ( HChar*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 187 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 188 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 189 | DisOneInstrFn disInstrFn; |
| 190 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 191 | VexGuestLayout* guest_layout; |
| 192 | Bool host_is_bigendian = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 193 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 194 | HInstrArray* vcode; |
| 195 | HInstrArray* rcode; |
| 196 | Int i, j, k, out_used, guest_sizeB; |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 197 | Int offB_TISTART, offB_TILEN; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 198 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 199 | IRType guest_word_type; |
| 200 | IRType host_word_type; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 201 | Bool mode64; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 202 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 203 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 204 | available_real_regs = NULL; |
| 205 | n_available_real_regs = 0; |
| 206 | isMove = NULL; |
| 207 | getRegUsage = NULL; |
| 208 | mapRegs = NULL; |
| 209 | genSpill = NULL; |
| 210 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 211 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 212 | ppInstr = NULL; |
| 213 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 214 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 215 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 216 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 217 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 218 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 219 | guest_word_type = Ity_INVALID; |
| 220 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 221 | offB_TISTART = 0; |
| 222 | offB_TILEN = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 223 | mode64 = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 224 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 225 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 226 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 227 | vassert(vex_initdone); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 228 | vexSetAllocModeTEMP_and_clear(); |
| 229 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 230 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 231 | /* First off, check that the guest and host insn sets |
| 232 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 233 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 234 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 235 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 236 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 237 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 238 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 239 | &available_real_regs ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 240 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 241 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 242 | getRegUsage_X86Instr; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 243 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 244 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 245 | genSpill_X86; |
| 246 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 247 | genReload_X86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 248 | directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; |
| 249 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
| 250 | ppReg = (void(*)(HReg)) ppHRegX86; |
| 251 | iselSB = iselSB_X86; |
| 252 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 253 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 254 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 255 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 256 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 257 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 258 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 259 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 260 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 261 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 262 | &available_real_regs ); |
| 263 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 264 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 265 | getRegUsage_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 266 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 267 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 268 | genSpill_AMD64; |
| 269 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 270 | genReload_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 271 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 272 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 273 | iselSB = iselSB_AMD64; |
sewardj | 0528bb5 | 2005-12-15 15:45:20 +0000 | [diff] [blame] | 274 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 275 | host_is_bigendian = False; |
| 276 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 277 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 278 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 279 | break; |
| 280 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 281 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 282 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 283 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 284 | &available_real_regs, mode64 ); |
| 285 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 286 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 287 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 288 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 289 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 290 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 291 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 292 | iselSB = iselSB_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 293 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 294 | host_is_bigendian = True; |
| 295 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 296 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 297 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 298 | break; |
| 299 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 300 | case VexArchPPC64: |
| 301 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 302 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 303 | &available_real_regs, mode64 ); |
| 304 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 305 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 306 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 307 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 308 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 309 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 310 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 311 | iselSB = iselSB_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 312 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 313 | host_is_bigendian = True; |
| 314 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 315 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 316 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 317 | break; |
| 318 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 319 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 320 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 321 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 322 | &available_real_regs ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 323 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; |
| 324 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; |
| 325 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; |
| 326 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; |
| 327 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; |
| 328 | ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; |
| 329 | ppReg = (void(*)(HReg)) ppHRegARM; |
| 330 | iselSB = iselSB_ARM; |
| 331 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 332 | host_is_bigendian = False; |
| 333 | host_word_type = Ity_I32; |
| 334 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
| 335 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
| 336 | break; |
| 337 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 338 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 339 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 340 | } |
| 341 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 342 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 343 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 344 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 345 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 346 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 347 | disInstrFn = disInstr_X86; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 348 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 349 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 350 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 351 | guest_layout = &x86guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 352 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 353 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 354 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 355 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 356 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); |
| 357 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
| 358 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 359 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 360 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 361 | case VexArchAMD64: |
| 362 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 363 | disInstrFn = disInstr_AMD64; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 364 | specHelper = guest_amd64_spechelper; |
| 365 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 366 | guest_word_type = Ity_I64; |
| 367 | guest_layout = &amd64guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 368 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 369 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 370 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 371 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 372 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 373 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
| 374 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 375 | break; |
| 376 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 377 | case VexArchPPC32: |
| 378 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 379 | disInstrFn = disInstr_PPC; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 380 | specHelper = guest_ppc32_spechelper; |
| 381 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 382 | guest_word_type = Ity_I32; |
| 383 | guest_layout = &ppc32Guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 384 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 385 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 386 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 387 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 388 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 389 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
| 390 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 391 | break; |
| 392 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 393 | case VexArchPPC64: |
| 394 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 395 | disInstrFn = disInstr_PPC; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 396 | specHelper = guest_ppc64_spechelper; |
| 397 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 398 | guest_word_type = Ity_I64; |
| 399 | guest_layout = &ppc64Guest_layout; |
| 400 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 401 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 402 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 403 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 404 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
| 405 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 406 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 407 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 408 | break; |
| 409 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 410 | case VexArchARM: |
| 411 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 412 | disInstrFn = disInstr_ARM; |
| 413 | specHelper = guest_arm_spechelper; |
| 414 | guest_sizeB = sizeof(VexGuestARMState); |
| 415 | guest_word_type = Ity_I32; |
| 416 | guest_layout = &armGuest_layout; |
| 417 | offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); |
| 418 | offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); |
| 419 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
| 420 | vassert(0 == sizeof(VexGuestARMState) % 16); |
| 421 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); |
| 422 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); |
| 423 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 424 | break; |
| 425 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 426 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 427 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 428 | } |
| 429 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 430 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 431 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 432 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 433 | we are simulating one flavour of an architecture a different |
| 434 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 435 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 436 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 437 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 438 | vexAllocSanityCheck(); |
| 439 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 440 | if (vex_traceflags & VEX_TRACE_FE) |
| 441 | vex_printf("\n------------------------" |
| 442 | " Front end " |
| 443 | "------------------------\n\n"); |
| 444 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 445 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 446 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 447 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 448 | vta->guest_bytes, |
| 449 | vta->guest_bytes_addr, |
| 450 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 451 | host_is_bigendian, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 452 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 453 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 454 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 455 | guest_word_type, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 456 | vta->do_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 457 | vta->preamble_function, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 458 | offB_TISTART, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 459 | offB_TILEN ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 460 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 461 | vexAllocSanityCheck(); |
| 462 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 463 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 464 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 465 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 466 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 467 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 468 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 469 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 470 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 471 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 472 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 473 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 474 | } |
| 475 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 476 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 477 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 478 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 479 | vex_printf("can't show code due to extents > 1\n"); |
| 480 | } else { |
| 481 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 482 | UChar* p = (UChar*)vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 483 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 484 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 485 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 486 | guest_bytes_read ); |
| 487 | for (i = 0; i < guest_bytes_read; i++) { |
| 488 | UInt b = (UInt)p[i]; |
| 489 | vex_printf(" %02x", b ); |
| 490 | sum = (sum << 1) ^ b; |
| 491 | } |
| 492 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 493 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 497 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 498 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 499 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 500 | vexAllocSanityCheck(); |
| 501 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 502 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 503 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 504 | vta->guest_bytes_addr ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 505 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 506 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 507 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 508 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 509 | vex_printf("\n------------------------" |
| 510 | " After pre-instr IR optimisation " |
| 511 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 512 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 513 | vex_printf("\n"); |
| 514 | } |
| 515 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 516 | vexAllocSanityCheck(); |
| 517 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 518 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 519 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 520 | irsb = vta->instrument1(vta->callback_opaque, |
| 521 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 522 | vta->guest_extents, |
| 523 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 524 | vexAllocSanityCheck(); |
| 525 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 526 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 527 | irsb = vta->instrument2(vta->callback_opaque, |
| 528 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 529 | vta->guest_extents, |
| 530 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 531 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 532 | if (vex_traceflags & VEX_TRACE_INST) { |
| 533 | vex_printf("\n------------------------" |
| 534 | " After instrumentation " |
| 535 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 536 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 537 | vex_printf("\n"); |
| 538 | } |
| 539 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 540 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 541 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 542 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 543 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 544 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 545 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 546 | do_deadcode_BB( irsb ); |
| 547 | irsb = cprop_BB( irsb ); |
| 548 | do_deadcode_BB( irsb ); |
| 549 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 550 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 551 | } |
| 552 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 553 | vexAllocSanityCheck(); |
| 554 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 555 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 556 | vex_printf("\n------------------------" |
| 557 | " After post-instr IR optimisation " |
| 558 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 559 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 560 | vex_printf("\n"); |
| 561 | } |
| 562 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 563 | /* Turn it into virtual-registerised code. Build trees -- this |
| 564 | also throws away any dead bindings. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 565 | ado_treebuild_BB( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 566 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 567 | if (vta->finaltidy) { |
| 568 | irsb = vta->finaltidy(irsb); |
| 569 | } |
| 570 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 571 | vexAllocSanityCheck(); |
| 572 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 573 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 574 | vex_printf("\n------------------------" |
| 575 | " After tree-building " |
| 576 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 577 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 578 | vex_printf("\n"); |
| 579 | } |
| 580 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 581 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 582 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 583 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 584 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 585 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 586 | vex_printf("\n------------------------" |
| 587 | " Instruction selection " |
| 588 | "------------------------\n"); |
| 589 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 590 | vcode = iselSB ( irsb, vta->arch_host, &vta->archinfo_host, |
| 591 | &vta->abiinfo_both ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 592 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 593 | vexAllocSanityCheck(); |
| 594 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 595 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 596 | vex_printf("\n"); |
| 597 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 598 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 599 | for (i = 0; i < vcode->arr_used; i++) { |
| 600 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 601 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 602 | vex_printf("\n"); |
| 603 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 604 | vex_printf("\n"); |
| 605 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 606 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 607 | /* Register allocate. */ |
| 608 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 609 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 610 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 611 | genSpill, genReload, directReload, |
| 612 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 613 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 614 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 615 | vexAllocSanityCheck(); |
| 616 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 617 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 618 | vex_printf("\n------------------------" |
| 619 | " Register-allocated code " |
| 620 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 621 | for (i = 0; i < rcode->arr_used; i++) { |
| 622 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 623 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 624 | vex_printf("\n"); |
| 625 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 626 | vex_printf("\n"); |
| 627 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 628 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 629 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 630 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 631 | /* end HACK */ |
| 632 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 633 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 634 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 635 | vex_printf("\n------------------------" |
| 636 | " Assembly " |
| 637 | "------------------------\n\n"); |
| 638 | } |
| 639 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 640 | out_used = 0; /* tracks along the host_bytes array */ |
| 641 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 642 | if (vex_traceflags & VEX_TRACE_ASM) { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 643 | ppInstr(rcode->arr[i], mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 644 | vex_printf("\n"); |
| 645 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 646 | j = (*emit)( insn_bytes, 32, rcode->arr[i], mode64, vta->dispatch ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 647 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 648 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 649 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 650 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 651 | else |
| 652 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 653 | vex_printf("\n\n"); |
| 654 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 655 | if (out_used + j > vta->host_bytes_size) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 656 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 657 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 658 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 659 | } |
| 660 | for (k = 0; k < j; k++) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 661 | vta->host_bytes[out_used] = insn_bytes[k]; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 662 | out_used++; |
| 663 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 664 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 665 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 666 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 667 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 668 | vexAllocSanityCheck(); |
| 669 | |
| 670 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 671 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 672 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 673 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 674 | } |
| 675 | |
| 676 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 677 | /* --------- Emulation warnings. --------- */ |
| 678 | |
| 679 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 680 | { |
| 681 | switch (ew) { |
| 682 | case EmWarn_NONE: |
| 683 | return "none"; |
| 684 | case EmWarn_X86_x87exns: |
| 685 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 686 | case EmWarn_X86_x87precision: |
| 687 | return "Selection of non-80-bit x87 FP precision"; |
| 688 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 689 | return "Unmasking SSE FP exceptions"; |
| 690 | case EmWarn_X86_fz: |
| 691 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 692 | case EmWarn_X86_daz: |
| 693 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 694 | case EmWarn_X86_acFlag: |
| 695 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 696 | case EmWarn_PPCexns: |
| 697 | return "Unmasking PPC32/64 FP exceptions"; |
| 698 | case EmWarn_PPC64_redir_overflow: |
| 699 | return "PPC64 function redirection stack overflow"; |
| 700 | case EmWarn_PPC64_redir_underflow: |
| 701 | return "PPC64 function redirection stack underflow"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 702 | default: |
| 703 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 704 | } |
| 705 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 706 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 707 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 708 | |
| 709 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 710 | { |
| 711 | switch (arch) { |
| 712 | case VexArch_INVALID: return "INVALID"; |
| 713 | case VexArchX86: return "X86"; |
| 714 | case VexArchAMD64: return "AMD64"; |
| 715 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 716 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 717 | case VexArchPPC64: return "PPC64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 718 | default: return "VexArch???"; |
| 719 | } |
| 720 | } |
| 721 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 722 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 723 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 724 | HChar* str = show_hwcaps(arch,hwcaps); |
| 725 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 726 | } |
| 727 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 728 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 729 | /* Write default settings info *vai. */ |
| 730 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 731 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 732 | vai->hwcaps = 0; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 733 | vai->ppc_cache_line_szB = 0; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 734 | } |
| 735 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 736 | /* Write default settings info *vbi. */ |
| 737 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 738 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 739 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 740 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 741 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 742 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 743 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
| 744 | vbi->guest_ppc_sc_continues_at_LR = False; |
| 745 | vbi->host_ppc_calls_use_fndescrs = False; |
| 746 | vbi->host_ppc32_regalign_int64_args = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 747 | } |
| 748 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 749 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 750 | /* Return a string showing the hwcaps in a nice way. The string will |
| 751 | be NULL for invalid combinations of flags, so these functions also |
| 752 | serve as a way to validate hwcaps values. */ |
| 753 | |
| 754 | static HChar* show_hwcaps_x86 ( UInt hwcaps ) |
| 755 | { |
| 756 | /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */ |
| 757 | if (hwcaps == 0) |
| 758 | return "x86-sse0"; |
| 759 | if (hwcaps == VEX_HWCAPS_X86_SSE1) |
| 760 | return "x86-sse1"; |
| 761 | if (hwcaps == (VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2)) |
| 762 | return "x86-sse1-sse2"; |
| 763 | if (hwcaps == (VEX_HWCAPS_X86_SSE1 |
| 764 | | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3)) |
| 765 | return "x86-sse1-sse2-sse3"; |
| 766 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 767 | return NULL; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 768 | } |
| 769 | |
| 770 | static HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
| 771 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 772 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 773 | don't expect to come across anything which can do SSE3 but can't |
| 774 | do CX16. Still, we can handle that case. */ |
| 775 | const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3; |
| 776 | const UInt CX16 = VEX_HWCAPS_AMD64_CX16; |
| 777 | UInt c = hwcaps; |
| 778 | if (c == 0) return "amd64-sse2"; |
| 779 | if (c == SSE3) return "amd64-sse3"; |
| 780 | if (c == CX16) return "amd64-sse2-cx16"; |
| 781 | if (c == (SSE3|CX16)) return "amd64-sse3-cx16"; |
| 782 | return NULL; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 783 | } |
| 784 | |
| 785 | static HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
| 786 | { |
| 787 | /* Monotonic with complications. Basically V > F > baseline, |
| 788 | but once you have F then you can have FX or GX too. */ |
| 789 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 790 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 791 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 792 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
| 793 | UInt c = hwcaps; |
| 794 | if (c == 0) return "ppc32-int"; |
| 795 | if (c == F) return "ppc32-int-flt"; |
| 796 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 797 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 798 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 799 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 800 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 801 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 802 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
| 803 | return NULL; |
| 804 | } |
| 805 | |
| 806 | static HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
| 807 | { |
| 808 | /* Monotonic with complications. Basically V > baseline(==F), |
| 809 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 810 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 811 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 812 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 813 | UInt c = hwcaps; |
| 814 | if (c == 0) return "ppc64-int-flt"; |
| 815 | if (c == FX) return "ppc64-int-flt-FX"; |
| 816 | if (c == GX) return "ppc64-int-flt-GX"; |
| 817 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 818 | if (c == V) return "ppc64-int-flt-vmx"; |
| 819 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 820 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 821 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
| 822 | return NULL; |
| 823 | } |
| 824 | |
| 825 | static HChar* show_hwcaps_arm ( UInt hwcaps ) |
| 826 | { |
| 827 | if (hwcaps == 0) return "arm-baseline"; |
| 828 | return NULL; |
| 829 | } |
| 830 | |
| 831 | /* ---- */ |
| 832 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
| 833 | { |
| 834 | switch (arch) { |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 835 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 836 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 837 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 838 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 839 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 840 | default: return NULL; |
| 841 | } |
| 842 | } |
| 843 | |
| 844 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 845 | { |
| 846 | return show_hwcaps(arch,hwcaps) != NULL; |
| 847 | } |
| 848 | |
| 849 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 850 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 851 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 852 | /*---------------------------------------------------------------*/ |