blob: 8bad91870ee91f466fc6b99dc48c9ce136cb25e4 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070035#include "fb.h"
Chia-I Wu09142132014-08-11 15:42:55 +080036
Chia-I Wu3c3edc02014-09-09 10:32:59 +080037/**
38 * Free all resources used by a writer. Note that the initial size is not
39 * reset.
40 */
41static void cmd_writer_reset(struct intel_cmd *cmd,
42 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080043{
Chia-I Wu68f319d2014-09-09 09:43:21 +080044 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080045
Chia-I Wu3c3edc02014-09-09 10:32:59 +080046 if (writer->ptr) {
47 intel_bo_unmap(writer->bo);
48 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080049 }
50
Chia-I Wu3c3edc02014-09-09 10:32:59 +080051 if (writer->bo) {
52 intel_bo_unreference(writer->bo);
53 writer->bo = NULL;
54 }
55
Chia-I Wue24c3292014-08-21 14:05:23 +080056 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080057
58 if (writer->items) {
59 icd_free(writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060060 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080061 writer->item_alloc = 0;
62 writer->item_used = 0;
63 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080064}
65
66/**
67 * Discard everything written so far.
68 */
69static void cmd_writer_discard(struct intel_cmd *cmd,
70 enum intel_cmd_writer_type which)
71{
72 struct intel_cmd_writer *writer = &cmd->writers[which];
73
74 intel_bo_truncate_relocs(writer->bo, 0);
75 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080076 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080077}
78
79static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
80 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060081 size_t size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080082{
83 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
84 [INTEL_CMD_WRITER_BATCH] = "batch",
85 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
86 };
87
Chia-I Wu72292b72014-09-09 10:48:33 +080088 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080089}
90
91/**
92 * Allocate and map the buffer for writing.
93 */
94static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
95 enum intel_cmd_writer_type which)
96{
97 struct intel_cmd_writer *writer = &cmd->writers[which];
98 struct intel_bo *bo;
99
100 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
101 if (bo) {
102 if (writer->bo)
103 intel_bo_unreference(writer->bo);
104 writer->bo = bo;
105 } else if (writer->bo) {
106 /* reuse the old bo */
107 cmd_writer_discard(cmd, which);
108 } else {
109 return XGL_ERROR_OUT_OF_GPU_MEMORY;
110 }
111
112 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800113 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800114
115 writer->ptr = intel_bo_map(writer->bo, true);
116 if (!writer->ptr)
117 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800118
119 return XGL_SUCCESS;
120}
121
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800122/**
123 * Unmap the buffer for submission.
124 */
125static void cmd_writer_unmap(struct intel_cmd *cmd,
126 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800127{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800128 struct intel_cmd_writer *writer = &cmd->writers[which];
129
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800130 intel_bo_unmap(writer->bo);
131 writer->ptr = NULL;
132}
133
134/**
135 * Grow a mapped writer to at least \p new_size. Failures are handled
136 * silently.
137 */
138void cmd_writer_grow(struct intel_cmd *cmd,
139 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600140 size_t new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800141{
142 struct intel_cmd_writer *writer = &cmd->writers[which];
143 struct intel_bo *new_bo;
144 void *new_ptr;
145
146 if (new_size < writer->size << 1)
147 new_size = writer->size << 1;
148 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800149 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800150
151 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
152 if (!new_bo) {
153 cmd_writer_discard(cmd, which);
154 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
155 return;
156 }
157
158 /* map and copy the data over */
159 new_ptr = intel_bo_map(new_bo, true);
160 if (!new_ptr) {
161 intel_bo_unreference(new_bo);
162 cmd_writer_discard(cmd, which);
163 cmd->result = XGL_ERROR_UNKNOWN;
164 return;
165 }
166
Chia-I Wu72292b72014-09-09 10:48:33 +0800167 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800168
169 intel_bo_unmap(writer->bo);
170 intel_bo_unreference(writer->bo);
171
172 writer->size = new_size;
173 writer->bo = new_bo;
174 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800175}
176
Chia-I Wu00b51a82014-09-09 12:07:37 +0800177/**
178 * Record an item for later decoding.
179 */
180void cmd_writer_record(struct intel_cmd *cmd,
181 enum intel_cmd_writer_type which,
182 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600183 size_t offset, size_t size)
Chia-I Wu00b51a82014-09-09 12:07:37 +0800184{
185 struct intel_cmd_writer *writer = &cmd->writers[which];
186 struct intel_cmd_item *item;
187
188 if (writer->item_used == writer->item_alloc) {
189 const unsigned new_alloc = (writer->item_alloc) ?
190 writer->item_alloc << 1 : 256;
191 struct intel_cmd_item *items;
192
193 items = icd_alloc(sizeof(writer->items[0]) * new_alloc,
194 0, XGL_SYSTEM_ALLOC_DEBUG);
195 if (!items) {
196 writer->item_used = 0;
197 cmd->result = XGL_ERROR_OUT_OF_MEMORY;
198 return;
199 }
200
201 memcpy(items, writer->items,
202 sizeof(writer->items[0]) * writer->item_alloc);
203
204 icd_free(writer->items);
205
206 writer->items = items;
207 writer->item_alloc = new_alloc;
208 }
209
210 item = &writer->items[writer->item_used++];
211 item->type = type;
212 item->offset = offset;
213 item->size = size;
214}
215
Chia-I Wu5e25c272014-08-21 20:19:12 +0800216static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800217 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600218 size_t offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800219{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800220 struct intel_cmd_writer *writer = &cmd->writers[which];
221
Chia-I Wu72292b72014-09-09 10:48:33 +0800222 assert(offset + sizeof(val) <= writer->used);
223 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800224}
225
Chia-I Wu730e5362014-08-19 12:15:09 +0800226static void cmd_reset(struct intel_cmd *cmd)
227{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600228 uint32_t i;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800229
230 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
231 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800232
Chia-I Wua57761b2014-10-14 14:27:44 +0800233 if (cmd->bind.shader_cache.entries)
234 icd_free(cmd->bind.shader_cache.entries);
235
Chia-I Wuf8385062015-01-04 16:27:24 +0800236 if (cmd->bind.dset.graphics_dynamic_offsets)
237 icd_free(cmd->bind.dset.graphics_dynamic_offsets);
238 if (cmd->bind.dset.compute_dynamic_offsets)
239 icd_free(cmd->bind.dset.compute_dynamic_offsets);
240
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800241 memset(&cmd->bind, 0, sizeof(cmd->bind));
242
Chia-I Wu343b1372014-08-20 16:39:20 +0800243 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800244 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800245}
246
247static void cmd_destroy(struct intel_obj *obj)
248{
249 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
250
251 intel_cmd_destroy(cmd);
252}
253
254XGL_RESULT intel_cmd_create(struct intel_dev *dev,
255 const XGL_CMD_BUFFER_CREATE_INFO *info,
256 struct intel_cmd **cmd_ret)
257{
Chia-I Wu63883292014-08-25 13:50:26 +0800258 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800259 struct intel_cmd *cmd;
260
Chia-I Wu63883292014-08-25 13:50:26 +0800261 switch (info->queueType) {
262 case XGL_QUEUE_TYPE_GRAPHICS:
263 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
264 break;
265 case XGL_QUEUE_TYPE_COMPUTE:
266 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
267 break;
268 case XGL_QUEUE_TYPE_DMA:
269 pipeline_select = -1;
270 break;
271 default:
272 return XGL_ERROR_INVALID_VALUE;
273 break;
274 }
275
Chia-I Wu730e5362014-08-19 12:15:09 +0800276 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
277 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
278 if (!cmd)
279 return XGL_ERROR_OUT_OF_MEMORY;
280
281 cmd->obj.destroy = cmd_destroy;
282
283 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800284 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800285 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800286
Chia-I Wue0cdd832014-08-25 12:38:56 +0800287 /*
288 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
289 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
290 * and end offsets, for each referenced memories.
291 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800292 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
293 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
294 4096, XGL_SYSTEM_ALLOC_INTERNAL);
295 if (!cmd->relocs) {
296 intel_cmd_destroy(cmd);
297 return XGL_ERROR_OUT_OF_MEMORY;
298 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800299
300 *cmd_ret = cmd;
301
302 return XGL_SUCCESS;
303}
304
305void intel_cmd_destroy(struct intel_cmd *cmd)
306{
307 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800308
309 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800310 intel_base_destroy(&cmd->obj.base);
311}
312
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700313XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, const XGL_CMD_BUFFER_BEGIN_INFO* info)
Chia-I Wu730e5362014-08-19 12:15:09 +0800314{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800315 XGL_RESULT ret;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600316 uint32_t i;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700317 XGL_FLAGS flags = 0;
318 XGL_CMD_BUFFER_BEGIN_INFO* next= (XGL_CMD_BUFFER_BEGIN_INFO*) info;
319 XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *ginfo;
Chia-I Wu730e5362014-08-19 12:15:09 +0800320
321 cmd_reset(cmd);
322
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700323 while (next != NULL) {
324 switch (next->sType) {
325 case XGL_STRUCTURE_TYPE_CMD_BUFFER_BEGIN_INFO:
326 flags = next->flags;
327 break;
328 case XGL_STRUCTURE_TYPE_CMD_BUFFER_GRAPHICS_BEGIN_INFO:
329 ginfo = (XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *) next;
330 cmd->bind.render_pass = (struct intel_render_pass *)
331 ginfo->renderPass;
332 break;
333 default:
334 return XGL_ERROR_INVALID_VALUE;
335 break;
336 }
337 next = (XGL_CMD_BUFFER_BEGIN_INFO*) next->pNext;
338 }
339
Chia-I Wu24565ee2014-08-21 20:24:31 +0800340 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800341 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800342 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800343 }
344
Chia-I Wu68f319d2014-09-09 09:43:21 +0800345 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600346 const uint32_t size = cmd->dev->gpu->max_batch_buffer_size / 2;
347 uint32_t divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800348
349 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
350 divider *= 4;
351
Chia-I Wu68f319d2014-09-09 09:43:21 +0800352 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
353 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
Chia-I Wu72292b72014-09-09 10:48:33 +0800354 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800355 }
356
Chia-I Wu68f319d2014-09-09 09:43:21 +0800357 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800358 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800359 if (ret != XGL_SUCCESS) {
360 cmd_reset(cmd);
361 return ret;
362 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800363 }
364
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800365 cmd_batch_begin(cmd);
366
Chia-I Wu24565ee2014-08-21 20:24:31 +0800367 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800368}
369
370XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
371{
372 struct intel_winsys *winsys = cmd->dev->winsys;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600373 uint32_t i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800374
Chia-I Wub8762122014-12-01 22:51:03 +0800375 /* no matching intel_cmd_begin() */
376 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].ptr)
377 return XGL_ERROR_INCOMPLETE_COMMAND_BUFFER;
378
Chia-I Wue24c3292014-08-21 14:05:23 +0800379 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800380
Chia-I Wu343b1372014-08-20 16:39:20 +0800381 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800382 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800383 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800384 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800385 uint64_t presumed_offset;
386 int err;
387
Chia-I Wud7d1e482014-10-18 13:25:10 +0800388 /*
389 * Once a bo is used as a reloc target, libdrm_intel disallows more
390 * relocs to be added to it. That may happen when
391 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
392 * in another pass.
393 */
394 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
395 continue;
396
Chia-I Wu72292b72014-09-09 10:48:33 +0800397 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800398 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800399 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800400 if (err) {
401 cmd->result = XGL_ERROR_UNKNOWN;
402 break;
403 }
404
405 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800406 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800407 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800408 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800409 for (i = 0; i < cmd->reloc_used; i++) {
410 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
411 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
412 uint64_t presumed_offset;
413 int err;
414
415 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
416 continue;
417
418 err = intel_bo_add_reloc(writer->bo, reloc->offset,
419 cmd->writers[reloc->target].bo, reloc->target_offset,
420 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
421 &presumed_offset);
422 if (err) {
423 cmd->result = XGL_ERROR_UNKNOWN;
424 break;
425 }
426
427 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
428 cmd_writer_patch(cmd, reloc->which, reloc->offset,
429 (uint32_t) presumed_offset);
430 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800431
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800432 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
433 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800434
Chia-I Wu04966702014-08-20 15:05:03 +0800435 if (cmd->result != XGL_SUCCESS)
436 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800437
Chia-I Wu68f319d2014-09-09 09:43:21 +0800438 if (intel_winsys_can_submit_bo(winsys,
439 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800440 return XGL_SUCCESS;
441 else
442 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
443}
444
Chia-I Wu96177272015-01-03 15:27:41 +0800445ICD_EXPORT XGL_RESULT XGLAPI xglCreateCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800446 XGL_DEVICE device,
447 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
448 XGL_CMD_BUFFER* pCmdBuffer)
449{
Chia-I Wu730e5362014-08-19 12:15:09 +0800450 struct intel_dev *dev = intel_dev(device);
451
452 return intel_cmd_create(dev, pCreateInfo,
453 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800454}
455
Chia-I Wu96177272015-01-03 15:27:41 +0800456ICD_EXPORT XGL_RESULT XGLAPI xglBeginCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800457 XGL_CMD_BUFFER cmdBuffer,
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700458 const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu09142132014-08-11 15:42:55 +0800459{
Chia-I Wu730e5362014-08-19 12:15:09 +0800460 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
461
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700462 return intel_cmd_begin(cmd, info);
Chia-I Wu09142132014-08-11 15:42:55 +0800463}
464
Chia-I Wu96177272015-01-03 15:27:41 +0800465ICD_EXPORT XGL_RESULT XGLAPI xglEndCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800466 XGL_CMD_BUFFER cmdBuffer)
467{
Chia-I Wu730e5362014-08-19 12:15:09 +0800468 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
469
470 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800471}
472
Chia-I Wu96177272015-01-03 15:27:41 +0800473ICD_EXPORT XGL_RESULT XGLAPI xglResetCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800474 XGL_CMD_BUFFER cmdBuffer)
475{
Chia-I Wu730e5362014-08-19 12:15:09 +0800476 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
477
478 cmd_reset(cmd);
479
480 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800481}
482
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600483ICD_EXPORT void XGLAPI xglCmdInitAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800484 XGL_CMD_BUFFER cmdBuffer,
485 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600486 uint32_t startCounter,
487 uint32_t counterCount,
488 const uint32_t* pData)
Chia-I Wu09142132014-08-11 15:42:55 +0800489{
490}
491
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600492ICD_EXPORT void XGLAPI xglCmdLoadAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800493 XGL_CMD_BUFFER cmdBuffer,
494 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600495 uint32_t startCounter,
496 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800497 XGL_BUFFER srcBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800498 XGL_GPU_SIZE srcOffset)
499{
500}
501
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600502ICD_EXPORT void XGLAPI xglCmdSaveAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800503 XGL_CMD_BUFFER cmdBuffer,
504 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600505 uint32_t startCounter,
506 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800507 XGL_BUFFER destBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800508 XGL_GPU_SIZE destOffset)
509{
510}
511
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600512ICD_EXPORT void XGLAPI xglCmdDbgMarkerBegin(
Chia-I Wu09142132014-08-11 15:42:55 +0800513 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600514 const char* pMarker)
Chia-I Wu09142132014-08-11 15:42:55 +0800515{
516}
517
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600518ICD_EXPORT void XGLAPI xglCmdDbgMarkerEnd(
Chia-I Wu09142132014-08-11 15:42:55 +0800519 XGL_CMD_BUFFER cmdBuffer)
520{
521}