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gerrit-public.fairphone.software / toolchain / llvm-project / 0937723b49904aeef8b7bdaea69193809b750375 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 4930db9563dd103e241e91aff758af5c9cfb39f3 [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame^]82
83 // A vector type of the same width with element type i32. This is used to
84 // create the canonical constant zero node ImmAllZerosV.
85 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
86 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]87}
88
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]89def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
90def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]91def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
92def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]93def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
94def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]95
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]96// "x" in v32i8x_info means RC = VR256X
97def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
98def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
99def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
100def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
101
102def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
103def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
104def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
105def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
106
107class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
108 X86VectorVTInfo i128> {
109 X86VectorVTInfo info512 = i512;
110 X86VectorVTInfo info256 = i256;
111 X86VectorVTInfo info128 = i128;
112}
113
114def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
115 v16i8x_info>;
116def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
117 v8i16x_info>;
118def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
119 v4i32x_info>;
120def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
121 v2i64x_info>;
122
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]123// This multiclass generates the masking variants from the non-masking
124// variant. It only provides the assembly pieces for the masking variants.
125// It assumes custom ISel patterns for masking which can be provided as
126// template arguments.
127multiclass AVX512_masking_custom<bits<8> O, Format F,
128 dag Outs,
129 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
130 string OpcodeStr,
131 string AttSrcAsm, string IntelSrcAsm,
132 list<dag> Pattern,
133 list<dag> MaskingPattern,
134 list<dag> ZeroMaskingPattern,
135 string MaskingConstraint = "",
136 InstrItinClass itin = NoItinerary,
137 bit IsCommutable = 0> {
138 let isCommutable = IsCommutable in
139 def NAME: AVX512<O, F, Outs, Ins,
140 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
141 "$dst, "#IntelSrcAsm#"}",
142 Pattern, itin>;
143
144 // Prefer over VMOV*rrk Pat<>
145 let AddedComplexity = 20 in
146 def NAME#k: AVX512<O, F, Outs, MaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
148 "$dst {${mask}}, "#IntelSrcAsm#"}",
149 MaskingPattern, itin>,
150 EVEX_K {
151 // In case of the 3src subclass this is overridden with a let.
152 string Constraints = MaskingConstraint;
153 }
154 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
155 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
156 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
157 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
158 ZeroMaskingPattern,
159 itin>,
160 EVEX_KZ;
161}
162
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]163
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]164// Common base class of AVX512_masking and AVX512_masking_3src.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]165multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
166 dag Outs,
167 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]168 string OpcodeStr,
169 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]170 dag RHS, dag MaskingRHS,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]171 string MaskingConstraint = "",
172 InstrItinClass itin = NoItinerary,
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]173 bit IsCommutable = 0> :
174 AVX512_masking_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
175 AttSrcAsm, IntelSrcAsm,
176 [(set _.RC:$dst, RHS)],
177 [(set _.RC:$dst, MaskingRHS)],
178 [(set _.RC:$dst,
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame^]179 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]180 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]181
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]182// This multiclass generates the unconditional/non-masking, the masking and
183// the zero-masking variant of the instruction. In the masking case, the
184// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]185multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
186 dag Outs, dag Ins, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]187 string AttSrcAsm, string IntelSrcAsm,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]188 dag RHS, InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]190 AVX512_masking_common<O, F, _, Outs, Ins,
191 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
192 !con((ins _.KRCWM:$mask), Ins),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]193 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]194 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]195 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]196
197// Similar to AVX512_masking but in this case one of the source operands
198// ($src1) is already tied to $dst so we just use that for the preserved
199// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
200// $src1.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]201multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag NonTiedIns, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]203 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]204 dag RHS> :
205 AVX512_masking_common<O, F, _, Outs,
206 !con((ins _.RC:$src1), NonTiedIns),
207 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
208 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]209 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]210 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]211
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]212// Bitcasts between 512-bit vector types. Return the original type since
213// no instruction is needed for the conversion
214let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]215 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]216 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]217 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
218 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
219 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]220 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]221 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
222 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
223 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]224 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]225 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]226 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
227 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]228 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]229 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
230 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]231 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]232 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
233 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]234 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]235 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
236 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
237 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
238 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
239 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
240 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
241 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
242 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
243 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
244 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
245 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246
247 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
248 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
249 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
250 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
251 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
252 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
253 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
254 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
255 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
256 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
257 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
258 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
259 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
260 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
261 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
262 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
263 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
264 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
265 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
266 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
267 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
268 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
269 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
270 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
271 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
272 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
273 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
274 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
275 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
276 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
277
278// Bitcasts between 256-bit vector types. Return the original type since
279// no instruction is needed for the conversion
280 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
281 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
282 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
283 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
284 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
285 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
286 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
287 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
288 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
289 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
290 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
291 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
292 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
293 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
294 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
295 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
296 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
297 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
298 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
299 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
300 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
301 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
302 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
303 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
304 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
305 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
306 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
307 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
308 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
309 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
310}
311
312//
313// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
314//
315
316let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
317 isPseudo = 1, Predicates = [HasAVX512] in {
318def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
319 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
320}
321
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]322let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]323def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
324def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
325def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]326}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]327
328//===----------------------------------------------------------------------===//
329// AVX-512 - VECTOR INSERT
330//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]331
332multiclass vinsert_for_size<int Opcode,
333 X86VectorVTInfo From, X86VectorVTInfo To,
334 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
335 PatFrag vinsert_insert,
336 SDNodeXForm INSERT_get_vinsert_imm> {
337 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
338 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
339 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
340 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
341 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]342 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
343 (From.VT From.RC:$src2),
344 (iPTR imm)))]>,
345 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]346
347 let mayLoad = 1 in
348 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
349 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
350 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
351 "$dst, $src1, $src2, $src3}",
352 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
353 }
354
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]355 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
356 // vinserti32x4
357 def : Pat<(vinsert_insert:$ins
358 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
359 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
360 VR512:$src1, From.RC:$src2,
361 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]362}
363
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]364multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
365 ValueType EltVT64, int Opcode64> {
366 defm NAME # "32x4" : vinsert_for_size<Opcode32,
367 X86VectorVTInfo< 4, EltVT32, VR128X>,
368 X86VectorVTInfo<16, EltVT32, VR512>,
369 X86VectorVTInfo< 2, EltVT64, VR128X>,
370 X86VectorVTInfo< 8, EltVT64, VR512>,
371 vinsert128_insert,
372 INSERT_get_vinsert128_imm>;
373 defm NAME # "64x4" : vinsert_for_size<Opcode64,
374 X86VectorVTInfo< 4, EltVT64, VR256X>,
375 X86VectorVTInfo< 8, EltVT64, VR512>,
376 X86VectorVTInfo< 8, EltVT32, VR256>,
377 X86VectorVTInfo<16, EltVT32, VR512>,
378 vinsert256_insert,
379 INSERT_get_vinsert256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]380}
381
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]382defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
383defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]384
385// vinsertps - insert f32 to XMM
386def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]387 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]388 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]389 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]390 EVEX_4V;
391def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]392 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]393 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]394 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]395 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
396 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
397
398//===----------------------------------------------------------------------===//
399// AVX-512 VECTOR EXTRACT
400//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]401
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]402multiclass vextract_for_size<int Opcode,
403 X86VectorVTInfo From, X86VectorVTInfo To,
404 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
405 PatFrag vextract_extract,
406 SDNodeXForm EXTRACT_get_vextract_imm> {
407 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
408 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
Adam Nemetf7988d72014-09-25 23:48:49 +0000[diff] [blame]409 (ins VR512:$src1, i8imm:$idx),
410 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
411 "$dst, $src1, $idx}",
412 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
413 (iPTR imm)))]>,
414 EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]415 let mayStore = 1 in
416 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
417 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
418 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
419 "$dst, $src1, $src2}",
420 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
421 }
422
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]423 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
424 // vextracti32x4
425 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
426 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
427 VR512:$src1,
428 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
429
430 // A 128/256-bit subvector extract from the first 512-bit vector position is
431 // a subregister copy that needs no instruction.
432 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
433 (To.VT
434 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
435
436 // And for the alternative types.
437 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
438 (AltTo.VT
439 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]440}
441
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]442multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
443 ValueType EltVT64, int Opcode64> {
444 defm NAME # "32x4" : vextract_for_size<Opcode32,
445 X86VectorVTInfo<16, EltVT32, VR512>,
446 X86VectorVTInfo< 4, EltVT32, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
448 X86VectorVTInfo< 2, EltVT64, VR128X>,
449 vextract128_extract,
450 EXTRACT_get_vextract128_imm>;
451 defm NAME # "64x4" : vextract_for_size<Opcode64,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 4, EltVT64, VR256X>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
455 X86VectorVTInfo< 8, EltVT32, VR256>,
456 vextract256_extract,
457 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]458}
459
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]460defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
461defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]462
463// A 128-bit subvector insert to the first 512-bit vector position
464// is a subregister copy that needs no instruction.
465def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
466 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
467 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
468 sub_ymm)>;
469def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
470 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
471 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
472 sub_ymm)>;
473def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
474 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
475 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
476 sub_ymm)>;
477def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
478 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
479 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
480 sub_ymm)>;
481
482def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
483 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
484def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
485 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
486def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
487 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
488def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
489 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
490
491// vextractps - extract 32 bits from XMM
492def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]493 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]494 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]495 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
496 EVEX;
497
498def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]499 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]500 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]501 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]502 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]503
504//===---------------------------------------------------------------------===//
505// AVX-512 BROADCAST
506//---
507multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
508 RegisterClass DestRC,
509 RegisterClass SrcRC, X86MemOperand x86memop> {
510 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]511 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]512 []>, EVEX;
513 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]514 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]515}
516let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]517 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]518 VR128X, f32mem>,
519 EVEX_V512, EVEX_CD8<32, CD8VT1>;
520}
521
522let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]523 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]524 VR128X, f64mem>,
525 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
526}
527
528def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
529 (VBROADCASTSSZrm addr:$src)>;
530def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
531 (VBROADCASTSDZrm addr:$src)>;
532
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]533def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
534 (VBROADCASTSSZrm addr:$src)>;
535def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
536 (VBROADCASTSDZrm addr:$src)>;
537
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]538multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
539 RegisterClass SrcRC, RegisterClass KRC> {
540 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]541 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]542 []>, EVEX, EVEX_V512;
543 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
544 (ins KRC:$mask, SrcRC:$src),
545 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]546 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]547 []>, EVEX, EVEX_V512, EVEX_KZ;
548}
549
550defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
551defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
552 VEX_W;
553
554def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
555 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
556
557def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
558 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
559
560def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
561 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]562def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
563 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]564def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
565 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]566def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
567 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]568
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]569def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
570 (VPBROADCASTDrZrr GR32:$src)>;
571def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
572 (VPBROADCASTQrZrr GR64:$src)>;
573
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]574def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
575 (v16i32 immAllZerosV), (i16 GR16:$mask))),
576 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
577def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
578 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
579 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
580
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]581multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
582 X86MemOperand x86memop, PatFrag ld_frag,
583 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
584 RegisterClass KRC> {
585 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]586 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]587 [(set DstRC:$dst,
588 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
589 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
590 VR128X:$src),
591 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]592 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]593 [(set DstRC:$dst,
594 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
595 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]596 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]597 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]598 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]599 [(set DstRC:$dst,
600 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
601 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
602 x86memop:$src),
603 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]604 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]605 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
606 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]607 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]608}
609
610defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
611 loadi32, VR512, v16i32, v4i32, VK16WM>,
612 EVEX_V512, EVEX_CD8<32, CD8VT1>;
613defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
614 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
615 EVEX_CD8<64, CD8VT1>;
616
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]617multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
618 X86MemOperand x86memop, PatFrag ld_frag,
619 RegisterClass KRC> {
620 let mayLoad = 1 in {
621 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
622 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
623 []>, EVEX;
624 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
625 x86memop:$src),
626 !strconcat(OpcodeStr,
627 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
628 []>, EVEX, EVEX_KZ;
629 }
630}
631
632defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
633 i128mem, loadv2i64, VK16WM>,
634 EVEX_V512, EVEX_CD8<32, CD8VT4>;
635defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
636 i256mem, loadv4i64, VK16WM>, VEX_W,
637 EVEX_V512, EVEX_CD8<64, CD8VT4>;
638
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]639def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
640 (VPBROADCASTDZrr VR128X:$src)>;
641def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
642 (VPBROADCASTQZrr VR128X:$src)>;
643
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]644def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
645 (VBROADCASTSSZrr VR128X:$src)>;
646def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
647 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]648
649def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
650 (VBROADCASTSSZrr VR128X:$src)>;
651def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
652 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]653
654// Provide fallback in case the load node that is used in the patterns above
655// is used by additional users, which prevents the pattern selection.
656def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
657 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
658def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
659 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
660
661
662let Predicates = [HasAVX512] in {
663def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
664 (EXTRACT_SUBREG
665 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
666 addr:$src)), sub_ymm)>;
667}
668//===----------------------------------------------------------------------===//
669// AVX-512 BROADCAST MASK TO VECTOR REGISTER
670//---
671
672multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
673 RegisterClass DstRC, RegisterClass KRC,
674 ValueType OpVT, ValueType SrcVT> {
675def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]676 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]677 []>, EVEX;
678}
679
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]680let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]681defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
682 VK16, v16i32, v16i1>, EVEX_V512;
683defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
684 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]685}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]686
687//===----------------------------------------------------------------------===//
688// AVX-512 - VPERM
689//
690// -- immediate form --
691multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
692 SDNode OpNode, PatFrag mem_frag,
693 X86MemOperand x86memop, ValueType OpVT> {
694 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
695 (ins RC:$src1, i8imm:$src2),
696 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]697 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]698 [(set RC:$dst,
699 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
700 EVEX;
701 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
702 (ins x86memop:$src1, i8imm:$src2),
703 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]704 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]705 [(set RC:$dst,
706 (OpVT (OpNode (mem_frag addr:$src1),
707 (i8 imm:$src2))))]>, EVEX;
708}
709
710defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
711 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
712let ExeDomain = SSEPackedDouble in
713defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
714 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
715
716// -- VPERM - register form --
717multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
718 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
719
720 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
721 (ins RC:$src1, RC:$src2),
722 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]724 [(set RC:$dst,
725 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
726
727 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
728 (ins RC:$src1, x86memop:$src2),
729 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]730 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]731 [(set RC:$dst,
732 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
733 EVEX_4V;
734}
735
736defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
737 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
738defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
739 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
740let ExeDomain = SSEPackedSingle in
741defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
742 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
743let ExeDomain = SSEPackedDouble in
744defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
745 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
746
747// -- VPERM2I - 3 source operands form --
748multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
749 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]750 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]751let Constraints = "$src1 = $dst" in {
752 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
753 (ins RC:$src1, RC:$src2, RC:$src3),
754 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]755 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]756 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]757 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]758 EVEX_4V;
759
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]760 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
761 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
762 !strconcat(OpcodeStr,
763 " \t{$src3, $src2, $dst {${mask}}|"
764 "$dst {${mask}}, $src2, $src3}"),
765 [(set RC:$dst, (OpVT (vselect KRC:$mask,
766 (OpNode RC:$src1, RC:$src2,
767 RC:$src3),
768 RC:$src1)))]>,
769 EVEX_4V, EVEX_K;
770
771 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
772 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
773 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
774 !strconcat(OpcodeStr,
775 " \t{$src3, $src2, $dst {${mask}} {z} |",
776 "$dst {${mask}} {z}, $src2, $src3}"),
777 [(set RC:$dst, (OpVT (vselect KRC:$mask,
778 (OpNode RC:$src1, RC:$src2,
779 RC:$src3),
780 (OpVT (bitconvert
781 (v16i32 immAllZerosV))))))]>,
782 EVEX_4V, EVEX_KZ;
783
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]784 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
785 (ins RC:$src1, RC:$src2, x86memop:$src3),
786 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]787 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]788 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]789 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]790 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]791
792 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
793 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
794 !strconcat(OpcodeStr,
795 " \t{$src3, $src2, $dst {${mask}}|"
796 "$dst {${mask}}, $src2, $src3}"),
797 [(set RC:$dst,
798 (OpVT (vselect KRC:$mask,
799 (OpNode RC:$src1, RC:$src2,
800 (mem_frag addr:$src3)),
801 RC:$src1)))]>,
802 EVEX_4V, EVEX_K;
803
804 let AddedComplexity = 10 in // Prefer over the rrkz variant
805 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
806 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
807 !strconcat(OpcodeStr,
808 " \t{$src3, $src2, $dst {${mask}} {z}|"
809 "$dst {${mask}} {z}, $src2, $src3}"),
810 [(set RC:$dst,
811 (OpVT (vselect KRC:$mask,
812 (OpNode RC:$src1, RC:$src2,
813 (mem_frag addr:$src3)),
814 (OpVT (bitconvert
815 (v16i32 immAllZerosV))))))]>,
816 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]817 }
818}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]819defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
820 i512mem, X86VPermiv3, v16i32, VK16WM>,
821 EVEX_V512, EVEX_CD8<32, CD8VF>;
822defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
823 i512mem, X86VPermiv3, v8i64, VK8WM>,
824 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
825defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
826 i512mem, X86VPermiv3, v16f32, VK16WM>,
827 EVEX_V512, EVEX_CD8<32, CD8VF>;
828defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
829 i512mem, X86VPermiv3, v8f64, VK8WM>,
830 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]831
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]832multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
833 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]834 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
835 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]836 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
837 OpVT, KRC> {
838 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
839 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
840 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]841
842 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
843 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
844 (!cast<Instruction>(NAME#rrk) VR512:$src1,
845 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]846}
847
848defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]849 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
850 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]851defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]852 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
853 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]854defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]855 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
856 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]857defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]858 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]860
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]861//===----------------------------------------------------------------------===//
862// AVX-512 - BLEND using mask
863//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]864multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]865 RegisterClass KRC, RegisterClass RC,
866 X86MemOperand x86memop, PatFrag mem_frag,
867 SDNode OpNode, ValueType vt> {
868 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]869 (ins KRC:$mask, RC:$src1, RC:$src2),
870 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]871 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]872 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]873 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]874 let mayLoad = 1 in
875 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
876 (ins KRC:$mask, RC:$src1, x86memop:$src2),
877 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]878 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]879 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]880}
881
882let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]883defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]884 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]885 memopv16f32, vselect, v16f32>,
886 EVEX_CD8<32, CD8VF>, EVEX_V512;
887let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]888defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]889 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]890 memopv8f64, vselect, v8f64>,
891 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
892
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]893def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
894 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]895 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]896 VR512:$src1, VR512:$src2)>;
897
898def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
899 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]900 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]901 VR512:$src1, VR512:$src2)>;
902
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]903defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]904 VK16WM, VR512, f512mem,
905 memopv16i32, vselect, v16i32>,
906 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]907
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]908defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]909 VK8WM, VR512, f512mem,
910 memopv8i64, vselect, v8i64>,
911 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]912
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]913def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
914 (v16i32 VR512:$src2), (i16 GR16:$mask))),
915 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
916 VR512:$src1, VR512:$src2)>;
917
918def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
919 (v8i64 VR512:$src2), (i8 GR8:$mask))),
920 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
921 VR512:$src1, VR512:$src2)>;
922
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]923let Predicates = [HasAVX512] in {
924def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
925 (v8f32 VR256X:$src2))),
926 (EXTRACT_SUBREG
927 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
928 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
929 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
930
931def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
932 (v8i32 VR256X:$src2))),
933 (EXTRACT_SUBREG
934 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
935 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
936 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
937}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]938//===----------------------------------------------------------------------===//
939// Compare Instructions
940//===----------------------------------------------------------------------===//
941
942// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
943multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
944 Operand CC, SDNode OpNode, ValueType VT,
945 PatFrag ld_frag, string asm, string asm_alt> {
946 def rr : AVX512Ii8<0xC2, MRMSrcReg,
947 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
948 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
949 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
950 def rm : AVX512Ii8<0xC2, MRMSrcMem,
951 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
952 [(set VK1:$dst, (OpNode (VT RC:$src1),
953 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]954 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]955 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
956 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
957 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
958 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
959 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
960 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
961 }
962}
963
964let Predicates = [HasAVX512] in {
965defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
966 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
967 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
968 XS;
969defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
970 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
971 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
972 XD, VEX_W;
973}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]974
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]975multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
976 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]977 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]978 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
980 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]981 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]982 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]983 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]984 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
986 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
987 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]988 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]989 def rrk : AVX512BI<opc, MRMSrcReg,
990 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
991 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
992 "$dst {${mask}}, $src1, $src2}"),
993 [(set _.KRC:$dst, (and _.KRCWM:$mask,
994 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
995 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
996 let mayLoad = 1 in
997 def rmk : AVX512BI<opc, MRMSrcMem,
998 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1000 "$dst {${mask}}, $src1, $src2}"),
1001 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1002 (OpNode (_.VT _.RC:$src1),
1003 (_.VT (bitconvert
1004 (_.LdFrag addr:$src2))))))],
1005 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1006}
1007
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1008multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1009 X86VectorVTInfo _> :
1010 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1011 let mayLoad = 1 in {
1012 def rmb : AVX512BI<opc, MRMSrcMem,
1013 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1014 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1015 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1016 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1017 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1018 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1019 def rmbk : AVX512BI<opc, MRMSrcMem,
1020 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1021 _.ScalarMemOp:$src2),
1022 !strconcat(OpcodeStr,
1023 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1024 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1025 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1026 (OpNode (_.VT _.RC:$src1),
1027 (X86VBroadcast
1028 (_.ScalarLdFrag addr:$src2)))))],
1029 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1030 }
1031}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1032
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1033multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1034 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1035 let Predicates = [prd] in
1036 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1037 EVEX_V512;
1038
1039 let Predicates = [prd, HasVLX] in {
1040 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1041 EVEX_V256;
1042 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1043 EVEX_V128;
1044 }
1045}
1046
1047multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1048 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1049 Predicate prd> {
1050 let Predicates = [prd] in
1051 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1052 EVEX_V512;
1053
1054 let Predicates = [prd, HasVLX] in {
1055 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1056 EVEX_V256;
1057 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1058 EVEX_V128;
1059 }
1060}
1061
1062defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1063 avx512vl_i8_info, HasBWI>,
1064 EVEX_CD8<8, CD8VF>;
1065
1066defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1067 avx512vl_i16_info, HasBWI>,
1068 EVEX_CD8<16, CD8VF>;
1069
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1070defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1071 avx512vl_i32_info, HasAVX512>,
1072 EVEX_CD8<32, CD8VF>;
1073
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1074defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1075 avx512vl_i64_info, HasAVX512>,
1076 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1077
1078defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1079 avx512vl_i8_info, HasBWI>,
1080 EVEX_CD8<8, CD8VF>;
1081
1082defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1083 avx512vl_i16_info, HasBWI>,
1084 EVEX_CD8<16, CD8VF>;
1085
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1086defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1087 avx512vl_i32_info, HasAVX512>,
1088 EVEX_CD8<32, CD8VF>;
1089
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1090defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1091 avx512vl_i64_info, HasAVX512>,
1092 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1093
1094def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1095 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1096 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1097 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1098
1099def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1100 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1101 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1102 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1103
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1104multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1105 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1106 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1107 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1108 !strconcat("vpcmp${cc}", Suffix,
1109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1110 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1111 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1112 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1113 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1114 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1115 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1116 !strconcat("vpcmp${cc}", Suffix,
1117 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1118 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1119 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1120 imm:$cc))],
1121 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1122 def rrik : AVX512AIi8<opc, MRMSrcReg,
1123 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1124 AVXCC:$cc),
1125 !strconcat("vpcmp${cc}", Suffix,
1126 "\t{$src2, $src1, $dst {${mask}}|",
1127 "$dst {${mask}}, $src1, $src2}"),
1128 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1129 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1130 imm:$cc)))],
1131 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1132 let mayLoad = 1 in
1133 def rmik : AVX512AIi8<opc, MRMSrcMem,
1134 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1135 AVXCC:$cc),
1136 !strconcat("vpcmp${cc}", Suffix,
1137 "\t{$src2, $src1, $dst {${mask}}|",
1138 "$dst {${mask}}, $src1, $src2}"),
1139 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1140 (OpNode (_.VT _.RC:$src1),
1141 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1142 imm:$cc)))],
1143 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1144
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1145 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1146 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1147 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1148 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1149 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1150 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1151 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1152 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1153 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1154 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1155 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1156 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1157 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1158 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1159 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1160 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1161 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2, $cc}"),
1163 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1164 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1165 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1166 i8imm:$cc),
1167 !strconcat("vpcmp", Suffix,
1168 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1169 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1170 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1171 }
1172}
1173
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1174multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1175 X86VectorVTInfo _> :
1176 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1177 let mayLoad = 1 in {
1178 def rmib : AVX512AIi8<opc, MRMSrcMem,
1179 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1180 AVXCC:$cc),
1181 !strconcat("vpcmp${cc}", Suffix,
1182 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1183 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1184 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1185 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1186 imm:$cc))],
1187 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1188 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1189 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1190 _.ScalarMemOp:$src2, AVXCC:$cc),
1191 !strconcat("vpcmp${cc}", Suffix,
1192 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1193 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1194 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1195 (OpNode (_.VT _.RC:$src1),
1196 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1197 imm:$cc)))],
1198 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1199 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1200
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1201 // Accept explicit immediate argument form instead of comparison code.
1202 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1203 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1204 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1205 i8imm:$cc),
1206 !strconcat("vpcmp", Suffix,
1207 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1208 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1209 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1210 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1211 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1212 _.ScalarMemOp:$src2, i8imm:$cc),
1213 !strconcat("vpcmp", Suffix,
1214 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1215 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1216 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1217 }
1218}
1219
1220multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1221 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1222 let Predicates = [prd] in
1223 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1224
1225 let Predicates = [prd, HasVLX] in {
1226 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1227 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1228 }
1229}
1230
1231multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1232 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1233 let Predicates = [prd] in
1234 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1235 EVEX_V512;
1236
1237 let Predicates = [prd, HasVLX] in {
1238 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1239 EVEX_V256;
1240 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1241 EVEX_V128;
1242 }
1243}
1244
1245defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1246 HasBWI>, EVEX_CD8<8, CD8VF>;
1247defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1248 HasBWI>, EVEX_CD8<8, CD8VF>;
1249
1250defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1251 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1252defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1253 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1254
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1255defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1256 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1257defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1258 HasAVX512>, EVEX_CD8<32, CD8VF>;
1259
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1260defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1261 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1262defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1263 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1264
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1265// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1266multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1267 X86MemOperand x86memop, ValueType vt,
1268 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1269 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1270 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1271 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1272 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1273 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1274 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1275 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1276 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1277 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1278 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1279 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1280 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1281 !strconcat("vcmp${cc}", suffix,
1282 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1283 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1284 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1285
1286 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1287 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1288 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1289 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1290 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1291 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1292 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1293 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1294 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1295 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1296 }
1297}
1298
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1299defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1300 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1301 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1302defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1303 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1304 EVEX_CD8<64, CD8VF>;
1305
1306def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1307 (COPY_TO_REGCLASS (VCMPPSZrri
1308 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1309 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1310 imm:$cc), VK8)>;
1311def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1312 (COPY_TO_REGCLASS (VPCMPDZrri
1313 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1314 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1315 imm:$cc), VK8)>;
1316def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1317 (COPY_TO_REGCLASS (VPCMPUDZrri
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1319 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1320 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1321
1322def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1323 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1324 FROUND_NO_EXC)),
1325 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1326 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1327
1328def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1329 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1330 FROUND_NO_EXC)),
1331 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1332 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1333
1334def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1335 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1336 FROUND_CURRENT)),
1337 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1338 (I8Imm imm:$cc)), GR16)>;
1339
1340def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1341 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1342 FROUND_CURRENT)),
1343 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1344 (I8Imm imm:$cc)), GR8)>;
1345
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1346// Mask register copy, including
1347// - copy between mask registers
1348// - load/store mask registers
1349// - copy from GPR to mask register and vice versa
1350//
1351multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1352 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1353 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1354 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1355 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1356 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1357 let mayLoad = 1 in
1358 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1359 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1360 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1361 let mayStore = 1 in
1362 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1363 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1364 }
1365}
1366
1367multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1368 string OpcodeStr,
1369 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1370 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1371 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1372 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1373 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1374 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1375 }
1376}
1377
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1378let Predicates = [HasDQI] in
1379 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1380 i8mem>,
1381 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1382 VEX, PD;
1383
1384let Predicates = [HasAVX512] in
1385 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1386 i16mem>,
1387 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1388 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1389
1390let Predicates = [HasBWI] in {
1391 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1392 i32mem>, VEX, PD, VEX_W;
1393 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1394 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1395}
1396
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1397let Predicates = [HasBWI] in {
1398 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1399 i64mem>, VEX, PS, VEX_W;
1400 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1401 VEX, XD, VEX_W;
1402}
1403
1404// GR from/to mask register
1405let Predicates = [HasDQI] in {
1406 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1407 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1408 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1409 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1410}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1411let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1412 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1413 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1414 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1415 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1416}
1417let Predicates = [HasBWI] in {
1418 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1419 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1420}
1421let Predicates = [HasBWI] in {
1422 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1423 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1424}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1425
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1426// Load/store kreg
1427let Predicates = [HasDQI] in {
1428 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1429 (KMOVBmk addr:$dst, VK8:$src)>;
1430}
1431let Predicates = [HasAVX512] in {
1432 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1433 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1434 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1435 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1436 def : Pat<(i1 (load addr:$src)),
1437 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1438 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1439 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1440}
1441let Predicates = [HasBWI] in {
1442 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1443 (KMOVDmk addr:$dst, VK32:$src)>;
1444}
1445let Predicates = [HasBWI] in {
1446 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1447 (KMOVQmk addr:$dst, VK64:$src)>;
1448}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1449
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1450let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1451 def : Pat<(i1 (trunc (i64 GR64:$src))),
1452 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1453 (i32 1))), VK1)>;
1454
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1455 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1456 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1457
1458 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1459 (COPY_TO_REGCLASS
1460 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1461 VK1)>;
1462 def : Pat<(i1 (trunc (i16 GR16:$src))),
1463 (COPY_TO_REGCLASS
1464 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1465 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1466
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1467 def : Pat<(i32 (zext VK1:$src)),
1468 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1469 def : Pat<(i8 (zext VK1:$src)),
1470 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1471 (AND32ri (KMOVWrk
1472 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1473 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1474 (AND64ri8 (SUBREG_TO_REG (i64 0),
1475 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1476 def : Pat<(i16 (zext VK1:$src)),
1477 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1478 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1479 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1480 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1481 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1482 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1483 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1484}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1485let Predicates = [HasBWI] in {
1486 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1487 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1488 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1489 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1490}
1491
1492
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1493// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1494let Predicates = [HasAVX512] in {
1495 // GR from/to 8-bit mask without native support
1496 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1497 (COPY_TO_REGCLASS
1498 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1499 VK8)>;
1500 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1501 (EXTRACT_SUBREG
1502 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1503 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1504
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1505 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1506 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1507 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1508 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1509}
1510let Predicates = [HasBWI] in {
1511 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1512 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1513 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1514 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1515}
1516
1517// Mask unary operation
1518// - KNOT
1519multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1520 RegisterClass KRC, SDPatternOperator OpNode,
1521 Predicate prd> {
1522 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1523 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1524 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1525 [(set KRC:$dst, (OpNode KRC:$src))]>;
1526}
1527
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1528multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1529 SDPatternOperator OpNode> {
1530 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1531 HasDQI>, VEX, PD;
1532 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1533 HasAVX512>, VEX, PS;
1534 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1535 HasBWI>, VEX, PD, VEX_W;
1536 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1537 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1538}
1539
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1540defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1541
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1542multiclass avx512_mask_unop_int<string IntName, string InstName> {
1543 let Predicates = [HasAVX512] in
1544 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1545 (i16 GR16:$src)),
1546 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1547 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1548}
1549defm : avx512_mask_unop_int<"knot", "KNOT">;
1550
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1551let Predicates = [HasDQI] in
1552def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1553let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1554def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1555let Predicates = [HasBWI] in
1556def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1557let Predicates = [HasBWI] in
1558def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1559
1560// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1561let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1562def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1563 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1564
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1565def : Pat<(not VK8:$src),
1566 (COPY_TO_REGCLASS
1567 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1568}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1569
1570// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1571// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1572multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1573 RegisterClass KRC, SDPatternOperator OpNode,
1574 Predicate prd> {
1575 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1576 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1577 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1578 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1579 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1580}
1581
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1582multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1583 SDPatternOperator OpNode> {
1584 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1585 HasDQI>, VEX_4V, VEX_L, PD;
1586 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1587 HasAVX512>, VEX_4V, VEX_L, PS;
1588 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1589 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1590 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1591 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1592}
1593
1594def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1595def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1596
1597let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1598 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1599 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1600 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1601 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1602}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1603let isCommutable = 0 in
1604 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1605
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1606def : Pat<(xor VK1:$src1, VK1:$src2),
1607 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1608 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1609
1610def : Pat<(or VK1:$src1, VK1:$src2),
1611 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1612 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1613
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1614def : Pat<(and VK1:$src1, VK1:$src2),
1615 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1616 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1617
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1618multiclass avx512_mask_binop_int<string IntName, string InstName> {
1619 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1620 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1621 (i16 GR16:$src1), (i16 GR16:$src2)),
1622 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1623 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1624 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1625}
1626
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1627defm : avx512_mask_binop_int<"kand", "KAND">;
1628defm : avx512_mask_binop_int<"kandn", "KANDN">;
1629defm : avx512_mask_binop_int<"kor", "KOR">;
1630defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1631defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1632
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1633// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1634multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1635 let Predicates = [HasAVX512] in
1636 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1637 (COPY_TO_REGCLASS
1638 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1639 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1640}
1641
1642defm : avx512_binop_pat<and, KANDWrr>;
1643defm : avx512_binop_pat<andn, KANDNWrr>;
1644defm : avx512_binop_pat<or, KORWrr>;
1645defm : avx512_binop_pat<xnor, KXNORWrr>;
1646defm : avx512_binop_pat<xor, KXORWrr>;
1647
1648// Mask unpacking
1649multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1650 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1651 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1652 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1653 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1654 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1655}
1656
1657multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1658 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1659 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1660}
1661
1662defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1663def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1664 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1665 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1666
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1667
1668multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1669 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1670 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1671 (i16 GR16:$src1), (i16 GR16:$src2)),
1672 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1673 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1674 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1675}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1676defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1677
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1678// Mask bit testing
1679multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1680 SDNode OpNode> {
1681 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1682 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1683 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1684 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1685}
1686
1687multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1688 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1689 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1690}
1691
1692defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1693
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1694def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1695 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1696 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1697
1698// Mask shift
1699multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1700 SDNode OpNode> {
1701 let Predicates = [HasAVX512] in
1702 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1703 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1704 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1705 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1706}
1707
1708multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1709 SDNode OpNode> {
1710 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1711 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1712}
1713
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1714defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1715defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1716
1717// Mask setting all 0s or 1s
1718multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1719 let Predicates = [HasAVX512] in
1720 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1721 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1722 [(set KRC:$dst, (VT Val))]>;
1723}
1724
1725multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1726 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1727 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1728}
1729
1730defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1731defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1732
1733// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1734let Predicates = [HasAVX512] in {
1735 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1736 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1737 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1738 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1739 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1740}
1741def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1742 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1743
1744def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1745 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1746
1747def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1748 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1749
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1750let Predicates = [HasVLX] in {
1751 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1752 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1753 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1754 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1755 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1756 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1757 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1758 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1759}
1760
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1761def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1762 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1763
1764def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1765 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1766//===----------------------------------------------------------------------===//
1767// AVX-512 - Aligned and unaligned load and store
1768//
1769
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1770multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1771 RegisterClass KRC, RegisterClass RC,
1772 ValueType vt, ValueType zvt, X86MemOperand memop,
1773 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1774let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1775 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1776 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1777 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1778 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1779 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1780 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1781 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1782 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1783 SchedRW = [WriteLoad] in
1784 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1786 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1787 d>, EVEX;
1788
1789 let AddedComplexity = 20 in {
1790 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1791 let hasSideEffects = 0 in
1792 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1793 (ins RC:$src0, KRC:$mask, RC:$src1),
1794 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1795 "${dst} {${mask}}, $src1}"),
1796 [(set RC:$dst, (vt (vselect KRC:$mask,
1797 (vt RC:$src1),
1798 (vt RC:$src0))))],
1799 d>, EVEX, EVEX_K;
1800 let mayLoad = 1, SchedRW = [WriteLoad] in
1801 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1802 (ins RC:$src0, KRC:$mask, memop:$src1),
1803 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1804 "${dst} {${mask}}, $src1}"),
1805 [(set RC:$dst, (vt
1806 (vselect KRC:$mask,
1807 (vt (bitconvert (ld_frag addr:$src1))),
1808 (vt RC:$src0))))],
1809 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1810 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1811 let mayLoad = 1, SchedRW = [WriteLoad] in
1812 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1813 (ins KRC:$mask, memop:$src),
1814 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1815 "${dst} {${mask}} {z}, $src}"),
1816 [(set RC:$dst, (vt
1817 (vselect KRC:$mask,
1818 (vt (bitconvert (ld_frag addr:$src))),
1819 (vt (bitconvert (zvt immAllZerosV))))))],
1820 d>, EVEX, EVEX_KZ;
1821 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1822}
1823
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1824multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1825 string elty, string elsz, string vsz512,
1826 string vsz256, string vsz128, Domain d,
1827 Predicate prd, bit IsReMaterializable = 1> {
1828 let Predicates = [prd] in
1829 defm Z : avx512_load<opc, OpcodeStr,
1830 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1831 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1832 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1833 !cast<X86MemOperand>(elty##"512mem"), d,
1834 IsReMaterializable>, EVEX_V512;
1835
1836 let Predicates = [prd, HasVLX] in {
1837 defm Z256 : avx512_load<opc, OpcodeStr,
1838 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1839 "v"##vsz256##elty##elsz, "v4i64")),
1840 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1841 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1842 !cast<X86MemOperand>(elty##"256mem"), d,
1843 IsReMaterializable>, EVEX_V256;
1844
1845 defm Z128 : avx512_load<opc, OpcodeStr,
1846 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1847 "v"##vsz128##elty##elsz, "v2i64")),
1848 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1849 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1850 !cast<X86MemOperand>(elty##"128mem"), d,
1851 IsReMaterializable>, EVEX_V128;
1852 }
1853}
1854
1855
1856multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1857 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1858 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1859 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1860 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1862 EVEX;
1863 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1864 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1865 (ins RC:$src1, KRC:$mask, RC:$src2),
1866 !strconcat(OpcodeStr,
1867 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1868 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1869 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1870 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1871 !strconcat(OpcodeStr,
1872 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1873 [], d>, EVEX, EVEX_KZ;
1874 }
1875 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1876 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1878 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1879 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1880 (ins memop:$dst, KRC:$mask, RC:$src),
1881 !strconcat(OpcodeStr,
1882 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1883 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1884 }
1885}
1886
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1887
1888multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1889 string st_suff_512, string st_suff_256,
1890 string st_suff_128, string elty, string elsz,
1891 string vsz512, string vsz256, string vsz128,
1892 Domain d, Predicate prd> {
1893 let Predicates = [prd] in
1894 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1895 !cast<ValueType>("v"##vsz512##elty##elsz),
1896 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1897 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1898
1899 let Predicates = [prd, HasVLX] in {
1900 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1901 !cast<ValueType>("v"##vsz256##elty##elsz),
1902 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1903 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1904
1905 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1906 !cast<ValueType>("v"##vsz128##elty##elsz),
1907 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1908 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1909 }
1910}
1911
1912defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1913 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1914 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1915 "512", "256", "", "f", "32", "16", "8", "4",
1916 SSEPackedSingle, HasAVX512>,
1917 PS, EVEX_CD8<32, CD8VF>;
1918
1919defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1920 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1921 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1922 "512", "256", "", "f", "64", "8", "4", "2",
1923 SSEPackedDouble, HasAVX512>,
1924 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1925
1926defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1927 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1928 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1929 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1930 PS, EVEX_CD8<32, CD8VF>;
1931
1932defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1933 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1934 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1935 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1936 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1937
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1938def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1939 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1940 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1941
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1942def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1943 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1944 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1945
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1946def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1947 GR16:$mask),
1948 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1949 VR512:$src)>;
1950def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1951 GR8:$mask),
1952 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1953 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1954
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1955defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1956 "16", "8", "4", SSEPackedInt, HasAVX512>,
1957 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1958 "512", "256", "", "i", "32", "16", "8", "4",
1959 SSEPackedInt, HasAVX512>,
1960 PD, EVEX_CD8<32, CD8VF>;
1961
1962defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1963 "8", "4", "2", SSEPackedInt, HasAVX512>,
1964 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1965 "512", "256", "", "i", "64", "8", "4", "2",
1966 SSEPackedInt, HasAVX512>,
1967 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1968
1969defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1970 "64", "32", "16", SSEPackedInt, HasBWI>,
1971 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1972 "i", "8", "64", "32", "16", SSEPackedInt,
1973 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1974
1975defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1976 "32", "16", "8", SSEPackedInt, HasBWI>,
1977 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1978 "i", "16", "32", "16", "8", SSEPackedInt,
1979 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1980
1981defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1982 "16", "8", "4", SSEPackedInt, HasAVX512>,
1983 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1984 "i", "32", "16", "8", "4", SSEPackedInt,
1985 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1986
1987defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1988 "8", "4", "2", SSEPackedInt, HasAVX512>,
1989 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1990 "i", "64", "8", "4", "2", SSEPackedInt,
1991 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1992
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1993def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1994 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1995 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1996
1997def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1998 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1999 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2000
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2001def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2002 GR16:$mask),
2003 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2004 VR512:$src)>;
2005def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2006 GR8:$mask),
2007 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2008 VR512:$src)>;
2009
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2010let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2011def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2012 (bc_v8i64 (v16i32 immAllZerosV)))),
2013 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2014
2015def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2016 (v8i64 VR512:$src))),
2017 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2018 VK8), VR512:$src)>;
2019
2020def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2021 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2022 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2023
2024def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2025 (v16i32 VR512:$src))),
2026 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2027}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2028
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2029// Move Int Doubleword to Packed Double Int
2030//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2031def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2032 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2033 [(set VR128X:$dst,
2034 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2035 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2036def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2037 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2038 [(set VR128X:$dst,
2039 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2040 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2041def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2042 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2043 [(set VR128X:$dst,
2044 (v2i64 (scalar_to_vector GR64:$src)))],
2045 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2046let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2047def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2048 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2049 [(set FR64:$dst, (bitconvert GR64:$src))],
2050 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2051def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2052 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2053 [(set GR64:$dst, (bitconvert FR64:$src))],
2054 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2055}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2056def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2057 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2058 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2059 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2060 EVEX_CD8<64, CD8VT1>;
2061
2062// Move Int Doubleword to Single Scalar
2063//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2064let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2065def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2066 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2067 [(set FR32X:$dst, (bitconvert GR32:$src))],
2068 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2069
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2070def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2071 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2072 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2073 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2074}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2075
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2076// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2077//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2078def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2079 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2080 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2081 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2082 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2083def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2084 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2085 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2086 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2087 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2088 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2089
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2090// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2091//
2092def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2093 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2094 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2095 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2096 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2097 Requires<[HasAVX512, In64BitMode]>;
2098
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2099def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2100 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2101 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2102 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2103 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2104 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2105 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2106
2107// Move Scalar Single to Double Int
2108//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2109let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2110def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2111 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2112 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2113 [(set GR32:$dst, (bitconvert FR32X:$src))],
2114 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2115def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2116 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2117 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2118 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2119 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2120}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2121
2122// Move Quadword Int to Packed Quadword Int
2123//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2124def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2125 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2126 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2127 [(set VR128X:$dst,
2128 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2129 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2130
2131//===----------------------------------------------------------------------===//
2132// AVX-512 MOVSS, MOVSD
2133//===----------------------------------------------------------------------===//
2134
2135multiclass avx512_move_scalar <string asm, RegisterClass RC,
2136 SDNode OpNode, ValueType vt,
2137 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2138 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2139 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2140 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2141 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2142 (scalar_to_vector RC:$src2))))],
2143 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2144 let Constraints = "$src1 = $dst" in
2145 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2146 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2147 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2148 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2149 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2150 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2151 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2152 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2153 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2154 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2155 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2156 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2157 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2158 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2159 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2160 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2161 [], IIC_SSE_MOV_S_MR>,
2162 EVEX, VEX_LIG, EVEX_K;
2163 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2164 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2165}
2166
2167let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2168defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2169 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2170
2171let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2172defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2173 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2174
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2175def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2176 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2177 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2178
2179def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2180 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2181 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2182
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2183def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2184 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2185 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2186
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2187// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2188let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2189 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2190 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2191 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2192 IIC_SSE_MOV_S_RR>,
2193 XS, EVEX_4V, VEX_LIG;
2194 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2195 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2196 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2197 IIC_SSE_MOV_S_RR>,
2198 XD, EVEX_4V, VEX_LIG, VEX_W;
2199}
2200
2201let Predicates = [HasAVX512] in {
2202 let AddedComplexity = 15 in {
2203 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2204 // MOVS{S,D} to the lower bits.
2205 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2206 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2207 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2208 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2209 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2210 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2211 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2212 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2213
2214 // Move low f32 and clear high bits.
2215 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2216 (SUBREG_TO_REG (i32 0),
2217 (VMOVSSZrr (v4f32 (V_SET0)),
2218 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2219 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2220 (SUBREG_TO_REG (i32 0),
2221 (VMOVSSZrr (v4i32 (V_SET0)),
2222 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2223 }
2224
2225 let AddedComplexity = 20 in {
2226 // MOVSSrm zeros the high parts of the register; represent this
2227 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2229 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2231 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2233 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2234
2235 // MOVSDrm zeros the high parts of the register; represent this
2236 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2237 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2238 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2239 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2240 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2241 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2242 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2243 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2244 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2245 def : Pat<(v2f64 (X86vzload addr:$src)),
2246 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2247
2248 // Represent the same patterns above but in the form they appear for
2249 // 256-bit types
2250 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2251 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2252 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2253 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2254 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2255 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2256 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2257 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2258 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2259 }
2260 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2261 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2262 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2263 FR32X:$src)), sub_xmm)>;
2264 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2265 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2266 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2267 FR64X:$src)), sub_xmm)>;
2268 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2269 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2270 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2271
2272 // Move low f64 and clear high bits.
2273 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2274 (SUBREG_TO_REG (i32 0),
2275 (VMOVSDZrr (v2f64 (V_SET0)),
2276 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2277
2278 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2279 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2280 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2281
2282 // Extract and store.
2283 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2284 addr:$dst),
2285 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2286 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2287 addr:$dst),
2288 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2289
2290 // Shuffle with VMOVSS
2291 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2292 (VMOVSSZrr (v4i32 VR128X:$src1),
2293 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2294 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2295 (VMOVSSZrr (v4f32 VR128X:$src1),
2296 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2297
2298 // 256-bit variants
2299 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2300 (SUBREG_TO_REG (i32 0),
2301 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2302 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2303 sub_xmm)>;
2304 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2305 (SUBREG_TO_REG (i32 0),
2306 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2307 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2308 sub_xmm)>;
2309
2310 // Shuffle with VMOVSD
2311 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2312 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2313 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2314 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2315 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2316 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2317 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2318 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2319
2320 // 256-bit variants
2321 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2322 (SUBREG_TO_REG (i32 0),
2323 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2324 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2325 sub_xmm)>;
2326 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2327 (SUBREG_TO_REG (i32 0),
2328 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2329 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2330 sub_xmm)>;
2331
2332 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2333 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2334 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2335 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2336 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2337 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2338 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2339 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2340}
2341
2342let AddedComplexity = 15 in
2343def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2344 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2345 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2346 [(set VR128X:$dst, (v2i64 (X86vzmovl
2347 (v2i64 VR128X:$src))))],
2348 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2349
2350let AddedComplexity = 20 in
2351def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2352 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2353 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2354 [(set VR128X:$dst, (v2i64 (X86vzmovl
2355 (loadv2i64 addr:$src))))],
2356 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2357 EVEX_CD8<8, CD8VT8>;
2358
2359let Predicates = [HasAVX512] in {
2360 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2361 let AddedComplexity = 20 in {
2362 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2363 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2364 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2365 (VMOV64toPQIZrr GR64:$src)>;
2366 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2367 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2368
2369 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2370 (VMOVDI2PDIZrm addr:$src)>;
2371 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2372 (VMOVDI2PDIZrm addr:$src)>;
2373 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2374 (VMOVZPQILo2PQIZrm addr:$src)>;
2375 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2376 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2377 def : Pat<(v2i64 (X86vzload addr:$src)),
2378 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2379 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2380
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2381 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2382 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2383 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2384 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2385 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2386 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2387 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2388}
2389
2390def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2391 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2392
2393def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2394 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2395
2396def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2397 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2398
2399def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2400 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2401
2402//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2403// AVX-512 - Non-temporals
2404//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2405let SchedRW = [WriteLoad] in {
2406 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2407 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2408 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2409 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2410 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2411
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2412 let Predicates = [HasAVX512, HasVLX] in {
2413 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2414 (ins i256mem:$src),
2415 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2416 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2417 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2418
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2419 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2420 (ins i128mem:$src),
2421 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2422 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2423 EVEX_CD8<64, CD8VF>;
2424 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2425}
2426
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2427multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2428 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2429 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2430 let SchedRW = [WriteStore], mayStore = 1,
2431 AddedComplexity = 400 in
2432 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2434 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2435}
2436
2437multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2438 string elty, string elsz, string vsz512,
2439 string vsz256, string vsz128, Domain d,
2440 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2441 let Predicates = [prd] in
2442 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2443 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2444 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2445 EVEX_V512;
2446
2447 let Predicates = [prd, HasVLX] in {
2448 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2449 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2450 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2451 EVEX_V256;
2452
2453 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2454 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2455 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2456 EVEX_V128;
2457 }
2458}
2459
2460defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2461 "i", "64", "8", "4", "2", SSEPackedInt,
2462 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2463
2464defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2465 "f", "64", "8", "4", "2", SSEPackedDouble,
2466 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2467
2468defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2469 "f", "32", "16", "8", "4", SSEPackedSingle,
2470 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2471
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2472//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2473// AVX-512 - Integer arithmetic
2474//
2475multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2476 X86VectorVTInfo _, OpndItins itins,
2477 bit IsCommutable = 0> {
2478 defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
2479 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2480 "$src2, $src1", "$src1, $src2",
2481 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2482 itins.rr, IsCommutable>,
2483 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2484
2485 let mayLoad = 1 in {
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2486 defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2487 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2488 "$src2, $src1", "$src1, $src2",
2489 (_.VT (OpNode _.RC:$src1,
2490 (bitconvert (_.LdFrag addr:$src2)))),
2491 itins.rm>,
2492 AVX512BIBase, EVEX_4V;
2493 defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2494 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2495 "${src2}"##_.BroadcastStr##", $src1",
2496 "$src1, ${src2}"##_.BroadcastStr,
2497 (_.VT (OpNode _.RC:$src1,
2498 (X86VBroadcast
2499 (_.ScalarLdFrag addr:$src2)))),
2500 itins.rm>,
2501 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2502 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2503}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2504
2505multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2506 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2507 PatFrag memop_frag, X86MemOperand x86memop,
2508 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2509 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2510 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2511 {
2512 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2513 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2514 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2515 []>, EVEX_4V;
2516 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2517 (ins KRC:$mask, RC:$src1, RC:$src2),
2518 !strconcat(OpcodeStr,
2519 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2520 [], itins.rr>, EVEX_4V, EVEX_K;
2521 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2522 (ins KRC:$mask, RC:$src1, RC:$src2),
2523 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2524 "|$dst {${mask}} {z}, $src1, $src2}"),
2525 [], itins.rr>, EVEX_4V, EVEX_KZ;
2526 }
2527 let mayLoad = 1 in {
2528 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2529 (ins RC:$src1, x86memop:$src2),
2530 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2531 []>, EVEX_4V;
2532 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2533 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2534 !strconcat(OpcodeStr,
2535 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2536 [], itins.rm>, EVEX_4V, EVEX_K;
2537 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2538 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2539 !strconcat(OpcodeStr,
2540 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2541 [], itins.rm>, EVEX_4V, EVEX_KZ;
2542 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2543 (ins RC:$src1, x86scalar_mop:$src2),
2544 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2545 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2546 [], itins.rm>, EVEX_4V, EVEX_B;
2547 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2548 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2549 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2550 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2551 BrdcstStr, "}"),
2552 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2553 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2554 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2555 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2556 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2557 BrdcstStr, "}"),
2558 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2559 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2560}
2561
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2562defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2563 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2564
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2565defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2566 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2567
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2568defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2569 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2570
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2571defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2572 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2573
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2574defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2575 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2576
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2577defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2578 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2579 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2580 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2581
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2582defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2583 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2584 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2585
2586def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2587 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2588
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2589def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2590 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2591 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2592def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2593 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2594 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2595
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2596defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2597 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2598 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2599defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2600 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2601 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2602
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2603defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2604 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2605 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2606defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2607 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2608 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2609
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2610defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2611 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2612 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2613defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2614 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2615 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2616
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2617defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2618 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2619 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2620defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2621 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2622 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2623
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2624def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2625 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2626 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2627def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2628 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2629 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2630def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2631 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2632 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2633def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2634 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2635 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2636def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2637 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2638 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2639def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2640 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2641 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2642def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2643 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2644 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2645def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2646 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2647 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2648//===----------------------------------------------------------------------===//
2649// AVX-512 - Unpack Instructions
2650//===----------------------------------------------------------------------===//
2651
2652multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2653 PatFrag mem_frag, RegisterClass RC,
2654 X86MemOperand x86memop, string asm,
2655 Domain d> {
2656 def rr : AVX512PI<opc, MRMSrcReg,
2657 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2658 asm, [(set RC:$dst,
2659 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2660 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2661 def rm : AVX512PI<opc, MRMSrcMem,
2662 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2663 asm, [(set RC:$dst,
2664 (vt (OpNode RC:$src1,
2665 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2666 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2667}
2668
2669defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2670 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2671 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2672defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2673 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2674 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2675defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2676 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2677 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2678defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2679 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2680 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2681
2682multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2683 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2684 X86MemOperand x86memop> {
2685 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2686 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2687 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2688 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2689 IIC_SSE_UNPCK>, EVEX_4V;
2690 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2691 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2692 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2693 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2694 (bitconvert (memop_frag addr:$src2)))))],
2695 IIC_SSE_UNPCK>, EVEX_4V;
2696}
2697defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2698 VR512, memopv16i32, i512mem>, EVEX_V512,
2699 EVEX_CD8<32, CD8VF>;
2700defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2701 VR512, memopv8i64, i512mem>, EVEX_V512,
2702 VEX_W, EVEX_CD8<64, CD8VF>;
2703defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2704 VR512, memopv16i32, i512mem>, EVEX_V512,
2705 EVEX_CD8<32, CD8VF>;
2706defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2707 VR512, memopv8i64, i512mem>, EVEX_V512,
2708 VEX_W, EVEX_CD8<64, CD8VF>;
2709//===----------------------------------------------------------------------===//
2710// AVX-512 - PSHUFD
2711//
2712
2713multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2714 SDNode OpNode, PatFrag mem_frag,
2715 X86MemOperand x86memop, ValueType OpVT> {
2716 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2717 (ins RC:$src1, i8imm:$src2),
2718 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2719 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2720 [(set RC:$dst,
2721 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2722 EVEX;
2723 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2724 (ins x86memop:$src1, i8imm:$src2),
2725 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2726 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2727 [(set RC:$dst,
2728 (OpVT (OpNode (mem_frag addr:$src1),
2729 (i8 imm:$src2))))]>, EVEX;
2730}
2731
2732defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2733 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2734
2735let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2736defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2737 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2738 EVEX_CD8<32, CD8VF>;
2739let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2740defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2741 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2742 VEX_W, EVEX_CD8<32, CD8VF>;
2743
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2744def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2745 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2746def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2747 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2748
2749//===----------------------------------------------------------------------===//
2750// AVX-512 Logical Instructions
2751//===----------------------------------------------------------------------===//
2752
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2753defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2754 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2755defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2756 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2757defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2758 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2759defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2760 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2761defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2762 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2763defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2764 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2765defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2766 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2767defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2768 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2769
2770//===----------------------------------------------------------------------===//
2771// AVX-512 FP arithmetic
2772//===----------------------------------------------------------------------===//
2773
2774multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2775 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2776 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2777 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2778 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2779 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2780 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2781 EVEX_CD8<64, CD8VT1>;
2782}
2783
2784let isCommutable = 1 in {
2785defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2786defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2787defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2788defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2789}
2790let isCommutable = 0 in {
2791defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2792defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2793}
2794
2795multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2796 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2797 RegisterClass RC, ValueType vt,
2798 X86MemOperand x86memop, PatFrag mem_frag,
2799 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2800 string BrdcstStr,
2801 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2802 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2803 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2804 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2805 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2806 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2807
2808 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2809 !strconcat(OpcodeStr,
2810 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2811 [], itins.rr, d>, EVEX_4V, EVEX_K;
2812
2813 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2814 !strconcat(OpcodeStr,
2815 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2816 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2817 }
2818
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2819 let mayLoad = 1 in {
2820 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2821 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2822 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2823 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2824
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2825 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2826 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2827 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2828 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2829 [(set RC:$dst, (OpNode RC:$src1,
2830 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2831 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2832
2833 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2834 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2835 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2836 [], itins.rm, d>, EVEX_4V, EVEX_K;
2837
2838 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2839 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2840 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2841 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2842
2843 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2844 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2845 " \t{${src2}", BrdcstStr,
2846 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2847 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2848
2849 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2850 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2851 " \t{${src2}", BrdcstStr,
2852 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2853 BrdcstStr, "}"),
2854 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2855 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2856}
2857
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2858defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2859 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2860 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2861
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2862defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2863 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2864 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2865 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2866
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2867defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2868 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2869 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2870defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2871 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2872 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2873 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2874
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2875defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2876 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2877 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2878 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2879defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2881 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2882 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2883
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2884defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2885 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2886 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2887 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2888defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2889 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2890 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2891 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2892
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2893defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2894 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2895 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2896defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2897 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2898 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2899
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2900defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2901 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2902 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2903 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2904defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2905 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2906 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2907 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2908
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]2909def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2910 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2911 (i16 -1), FROUND_CURRENT)),
2912 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2913
2914def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2915 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2916 (i8 -1), FROUND_CURRENT)),
2917 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2918
2919def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2920 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2921 (i16 -1), FROUND_CURRENT)),
2922 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2923
2924def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2925 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2926 (i8 -1), FROUND_CURRENT)),
2927 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2928//===----------------------------------------------------------------------===//
2929// AVX-512 VPTESTM instructions
2930//===----------------------------------------------------------------------===//
2931
2932multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2933 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2934 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2935 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2936 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2937 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2938 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2939 SSEPackedInt>, EVEX_4V;
2940 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2941 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2942 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2943 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2944 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2945}
2946
2947defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2948 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2949 EVEX_CD8<32, CD8VF>;
2950defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2951 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2952 EVEX_CD8<64, CD8VF>;
2953
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2954let Predicates = [HasCDI] in {
2955defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2956 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2957 EVEX_CD8<32, CD8VF>;
2958defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2959 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2960 EVEX_CD8<64, CD8VF>;
2961}
2962
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]2963def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2964 (v16i32 VR512:$src2), (i16 -1))),
2965 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2966
2967def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2968 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2969 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2970//===----------------------------------------------------------------------===//
2971// AVX-512 Shift instructions
2972//===----------------------------------------------------------------------===//
2973multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2974 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2975 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2976 RegisterClass KRC> {
2977 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2978 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2979 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2980 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2981 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2982 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2983 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2984 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2985 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2986 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2987 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2988 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2989 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2990 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2991 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2992 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2993 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2994 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2995 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2996 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2997}
2998
2999multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3000 RegisterClass RC, ValueType vt, ValueType SrcVT,
3001 PatFrag bc_frag, RegisterClass KRC> {
3002 // src2 is always 128-bit
3003 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3004 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3005 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3006 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3007 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3008 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3009 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3010 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3011 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3012 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3013 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3014 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3015 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3016 [(set RC:$dst, (vt (OpNode RC:$src1,
3017 (bc_frag (memopv2i64 addr:$src2)))))],
3018 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3019 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3020 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3021 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3022 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3023 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3024}
3025
3026defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3027 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3028 EVEX_V512, EVEX_CD8<32, CD8VF>;
3029defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3030 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3031 EVEX_CD8<32, CD8VQ>;
3032
3033defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3034 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3035 EVEX_CD8<64, CD8VF>, VEX_W;
3036defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3037 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3038 EVEX_CD8<64, CD8VQ>, VEX_W;
3039
3040defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3041 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3042 EVEX_CD8<32, CD8VF>;
3043defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3044 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3045 EVEX_CD8<32, CD8VQ>;
3046
3047defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3048 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3049 EVEX_CD8<64, CD8VF>, VEX_W;
3050defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3051 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3052 EVEX_CD8<64, CD8VQ>, VEX_W;
3053
3054defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3055 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3056 EVEX_V512, EVEX_CD8<32, CD8VF>;
3057defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3058 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3059 EVEX_CD8<32, CD8VQ>;
3060
3061defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3062 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3063 EVEX_CD8<64, CD8VF>, VEX_W;
3064defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3065 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3066 EVEX_CD8<64, CD8VQ>, VEX_W;
3067
3068//===-------------------------------------------------------------------===//
3069// Variable Bit Shifts
3070//===-------------------------------------------------------------------===//
3071multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3072 RegisterClass RC, ValueType vt,
3073 X86MemOperand x86memop, PatFrag mem_frag> {
3074 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3075 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3076 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3077 [(set RC:$dst,
3078 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3079 EVEX_4V;
3080 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3081 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3082 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3083 [(set RC:$dst,
3084 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3085 EVEX_4V;
3086}
3087
3088defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3089 i512mem, memopv16i32>, EVEX_V512,
3090 EVEX_CD8<32, CD8VF>;
3091defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3092 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3093 EVEX_CD8<64, CD8VF>;
3094defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3095 i512mem, memopv16i32>, EVEX_V512,
3096 EVEX_CD8<32, CD8VF>;
3097defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3098 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3099 EVEX_CD8<64, CD8VF>;
3100defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3101 i512mem, memopv16i32>, EVEX_V512,
3102 EVEX_CD8<32, CD8VF>;
3103defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3104 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3105 EVEX_CD8<64, CD8VF>;
3106
3107//===----------------------------------------------------------------------===//
3108// AVX-512 - MOVDDUP
3109//===----------------------------------------------------------------------===//
3110
3111multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3112 X86MemOperand x86memop, PatFrag memop_frag> {
3113def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3114 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3115 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3116def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3117 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3118 [(set RC:$dst,
3119 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3120}
3121
3122defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3123 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3124def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3125 (VMOVDDUPZrm addr:$src)>;
3126
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3127//===---------------------------------------------------------------------===//
3128// Replicate Single FP - MOVSHDUP and MOVSLDUP
3129//===---------------------------------------------------------------------===//
3130multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3131 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3132 X86MemOperand x86memop> {
3133 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3134 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3135 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3136 let mayLoad = 1 in
3137 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3138 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3139 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3140}
3141
3142defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3143 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3144 EVEX_CD8<32, CD8VF>;
3145defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3146 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3147 EVEX_CD8<32, CD8VF>;
3148
3149def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3150def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3151 (VMOVSHDUPZrm addr:$src)>;
3152def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3153def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3154 (VMOVSLDUPZrm addr:$src)>;
3155
3156//===----------------------------------------------------------------------===//
3157// Move Low to High and High to Low packed FP Instructions
3158//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3159def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3160 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3161 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3162 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3163 IIC_SSE_MOV_LH>, EVEX_4V;
3164def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3165 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3166 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3167 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3168 IIC_SSE_MOV_LH>, EVEX_4V;
3169
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3170let Predicates = [HasAVX512] in {
3171 // MOVLHPS patterns
3172 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3173 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3174 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3175 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3176
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3177 // MOVHLPS patterns
3178 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3179 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3180}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3181
3182//===----------------------------------------------------------------------===//
3183// FMA - Fused Multiply Operations
3184//
3185let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3186multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 X86VectorVTInfo _> {
3188 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3189 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3190 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3191 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3192 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3193
3194 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3195 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3196 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3197 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3198 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3199 (_.MemOpFrag addr:$src3))))]>;
3200 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3201 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3202 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3203 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3204 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3205 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3206}
3207} // Constraints = "$src1 = $dst"
3208
3209let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3210 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3211 v16f32_info>,
3212 EVEX_V512, EVEX_CD8<32, CD8VF>;
3213 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3214 v16f32_info>,
3215 EVEX_V512, EVEX_CD8<32, CD8VF>;
3216 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3217 v16f32_info>,
3218 EVEX_V512, EVEX_CD8<32, CD8VF>;
3219 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3220 v16f32_info>,
3221 EVEX_V512, EVEX_CD8<32, CD8VF>;
3222 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3223 v16f32_info>,
3224 EVEX_V512, EVEX_CD8<32, CD8VF>;
3225 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3226 v16f32_info>,
3227 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3228}
3229let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3230 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3231 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3232 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3233 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3234 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3235 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3236 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3237 v8f64_info>,
3238 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3239 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3240 v8f64_info>,
3241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3242 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3243 v8f64_info>,
3244 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3245 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3246 v8f64_info>,
3247 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3248}
3249
3250let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3251multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3252 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3253 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3254 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3255 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3256 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3257 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3258 _.RC:$src3)))]>;
3259 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3260 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3261 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3262 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3263 [(set _.RC:$dst,
3264 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3265 (_.ScalarLdFrag addr:$src2))),
3266 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3267}
3268} // Constraints = "$src1 = $dst"
3269
3270
3271let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3272 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3273 v16f32_info>,
3274 EVEX_V512, EVEX_CD8<32, CD8VF>;
3275 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3276 v16f32_info>,
3277 EVEX_V512, EVEX_CD8<32, CD8VF>;
3278 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3279 v16f32_info>,
3280 EVEX_V512, EVEX_CD8<32, CD8VF>;
3281 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3282 v16f32_info>,
3283 EVEX_V512, EVEX_CD8<32, CD8VF>;
3284 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3285 v16f32_info>,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3288 v16f32_info>,
3289 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3290}
3291let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3292 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3293 v8f64_info>,
3294 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3295 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3296 v8f64_info>,
3297 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3298 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3299 v8f64_info>,
3300 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3301 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3302 v8f64_info>,
3303 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3304 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3305 v8f64_info>,
3306 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3307 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3308 v8f64_info>,
3309 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3310}
3311
3312// Scalar FMA
3313let Constraints = "$src1 = $dst" in {
3314multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3315 RegisterClass RC, ValueType OpVT,
3316 X86MemOperand x86memop, Operand memop,
3317 PatFrag mem_frag> {
3318 let isCommutable = 1 in
3319 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3320 (ins RC:$src1, RC:$src2, RC:$src3),
3321 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3322 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3323 [(set RC:$dst,
3324 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3325 let mayLoad = 1 in
3326 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3327 (ins RC:$src1, RC:$src2, f128mem:$src3),
3328 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3329 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3330 [(set RC:$dst,
3331 (OpVT (OpNode RC:$src2, RC:$src1,
3332 (mem_frag addr:$src3))))]>;
3333}
3334
3335} // Constraints = "$src1 = $dst"
3336
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3337defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3338 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3339defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3340 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3341defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3342 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3343defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3344 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3345defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3346 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3347defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3348 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3349defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3350 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3351defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3352 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3353
3354//===----------------------------------------------------------------------===//
3355// AVX-512 Scalar convert from sign integer to float/double
3356//===----------------------------------------------------------------------===//
3357
3358multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3359 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3360let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3361 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3362 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3363 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3364 let mayLoad = 1 in
3365 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3366 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3367 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3368 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3369} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3370}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3371let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3372defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3373 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3374defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3375 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3376defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3377 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3378defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3379 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3380
3381def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3382 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3383def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3384 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3385def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3386 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3387def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3388 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3389
3390def : Pat<(f32 (sint_to_fp GR32:$src)),
3391 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3392def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3393 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3394def : Pat<(f64 (sint_to_fp GR32:$src)),
3395 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3396def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3397 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3398
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3399defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3400 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3401defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3402 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3403defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3404 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3405defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3406 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3407
3408def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3409 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3410def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3411 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3412def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3413 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3414def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3415 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3416
3417def : Pat<(f32 (uint_to_fp GR32:$src)),
3418 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3419def : Pat<(f32 (uint_to_fp GR64:$src)),
3420 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3421def : Pat<(f64 (uint_to_fp GR32:$src)),
3422 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3423def : Pat<(f64 (uint_to_fp GR64:$src)),
3424 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3425}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3426
3427//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3428// AVX-512 Scalar convert from float/double to integer
3429//===----------------------------------------------------------------------===//
3430multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3431 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3432 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3433let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3434 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3435 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3436 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3437 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3438 let mayLoad = 1 in
3439 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3440 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3441 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3442} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3443}
3444let Predicates = [HasAVX512] in {
3445// Convert float/double to signed/unsigned int 32/64
3446defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3447 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3448 XS, EVEX_CD8<32, CD8VT1>;
3449defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3450 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3451 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3452defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3453 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3454 XS, EVEX_CD8<32, CD8VT1>;
3455defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3456 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3457 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3458 EVEX_CD8<32, CD8VT1>;
3459defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3460 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3461 XD, EVEX_CD8<64, CD8VT1>;
3462defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3463 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3464 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3465defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3466 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3467 XD, EVEX_CD8<64, CD8VT1>;
3468defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3469 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3470 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3471 EVEX_CD8<64, CD8VT1>;
3472
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3473let isCodeGenOnly = 1 in {
3474 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3475 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3476 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3477 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3478 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3479 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3480 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3481 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3482 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3483 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3484 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3485 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3486
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3487 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3488 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3489 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3490 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3491 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3492 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3493 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3494 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3495 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3496 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3497 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3498 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3499} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3500
3501// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3502let isCodeGenOnly = 1 in {
3503 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3504 ssmem, sse_load_f32, "cvttss2si">,
3505 XS, EVEX_CD8<32, CD8VT1>;
3506 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3507 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3508 "cvttss2si">, XS, VEX_W,
3509 EVEX_CD8<32, CD8VT1>;
3510 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3511 sdmem, sse_load_f64, "cvttsd2si">, XD,
3512 EVEX_CD8<64, CD8VT1>;
3513 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3514 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3515 "cvttsd2si">, XD, VEX_W,
3516 EVEX_CD8<64, CD8VT1>;
3517 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3518 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3519 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3520 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3521 int_x86_avx512_cvttss2usi64, ssmem,
3522 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3523 EVEX_CD8<32, CD8VT1>;
3524 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3525 int_x86_avx512_cvttsd2usi,
3526 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3527 EVEX_CD8<64, CD8VT1>;
3528 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3529 int_x86_avx512_cvttsd2usi64, sdmem,
3530 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3531 EVEX_CD8<64, CD8VT1>;
3532} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3533
3534multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3535 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3536 string asm> {
3537 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3538 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3539 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3540 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3541 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3542 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3543}
3544
3545defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3546 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3547 EVEX_CD8<32, CD8VT1>;
3548defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3549 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3550 EVEX_CD8<32, CD8VT1>;
3551defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3552 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3553 EVEX_CD8<32, CD8VT1>;
3554defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3555 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3556 EVEX_CD8<32, CD8VT1>;
3557defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3558 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3559 EVEX_CD8<64, CD8VT1>;
3560defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3562 EVEX_CD8<64, CD8VT1>;
3563defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3564 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3565 EVEX_CD8<64, CD8VT1>;
3566defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3567 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3568 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3569} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3570//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3571// AVX-512 Convert form float to double and back
3572//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3573let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3574def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3575 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3576 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3577 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3578let mayLoad = 1 in
3579def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3580 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3581 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3582 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3583 EVEX_CD8<32, CD8VT1>;
3584
3585// Convert scalar double to scalar single
3586def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3587 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3588 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3589 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3590let mayLoad = 1 in
3591def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3592 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3593 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3594 []>, EVEX_4V, VEX_LIG, VEX_W,
3595 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3596}
3597
3598def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3599 Requires<[HasAVX512]>;
3600def : Pat<(fextend (loadf32 addr:$src)),
3601 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3602
3603def : Pat<(extloadf32 addr:$src),
3604 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3605 Requires<[HasAVX512, OptForSize]>;
3606
3607def : Pat<(extloadf32 addr:$src),
3608 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3609 Requires<[HasAVX512, OptForSpeed]>;
3610
3611def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3612 Requires<[HasAVX512]>;
3613
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3614multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3615 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3616 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3617 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3618let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3619 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3620 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3621 [(set DstRC:$dst,
3622 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3623 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3624 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3625 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3626 let mayLoad = 1 in
3627 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3628 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3629 [(set DstRC:$dst,
3630 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3631} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3632}
3633
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3634multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3635 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3636 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3637 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3638let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3639 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3640 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3641 [(set DstRC:$dst,
3642 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3643 let mayLoad = 1 in
3644 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3645 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3646 [(set DstRC:$dst,
3647 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3648} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3649}
3650
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3651defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3652 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3653 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3654 EVEX_CD8<64, CD8VF>;
3655
3656defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3657 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3658 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3659 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3660def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3661 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3662
3663def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3664 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3665 (VCVTPD2PSZrr VR512:$src)>;
3666
3667def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3668 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3669 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3670
3671//===----------------------------------------------------------------------===//
3672// AVX-512 Vector convert from sign integer to float/double
3673//===----------------------------------------------------------------------===//
3674
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3675defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3676 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3677 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3678 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3679
3680defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3681 memopv4i64, i256mem, v8f64, v8i32,
3682 SSEPackedDouble>, EVEX_V512, XS,
3683 EVEX_CD8<32, CD8VH>;
3684
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3685defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3686 memopv16f32, f512mem, v16i32, v16f32,
3687 SSEPackedSingle>, EVEX_V512, XS,
3688 EVEX_CD8<32, CD8VF>;
3689
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3690defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3691 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3692 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3693 EVEX_CD8<64, CD8VF>;
3694
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3695defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3696 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3697 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3698 EVEX_CD8<32, CD8VF>;
3699
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3700// cvttps2udq (src, 0, mask-all-ones, sae-current)
3701def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3702 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3703 (VCVTTPS2UDQZrr VR512:$src)>;
3704
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3705defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3706 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3707 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3708 EVEX_CD8<64, CD8VF>;
3709
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3710// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3711def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3712 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3713 (VCVTTPD2UDQZrr VR512:$src)>;
3714
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3715defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3716 memopv4i64, f256mem, v8f64, v8i32,
3717 SSEPackedDouble>, EVEX_V512, XS,
3718 EVEX_CD8<32, CD8VH>;
3719
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3720defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3721 memopv16i32, f512mem, v16f32, v16i32,
3722 SSEPackedSingle>, EVEX_V512, XD,
3723 EVEX_CD8<32, CD8VF>;
3724
3725def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3726 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3727 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3728
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3729def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3730 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3731 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3732
3733def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3734 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3735 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3736
3737def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3738 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3739 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3740
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3741def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3742 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3743 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3744
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3745def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3746 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3747 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3748def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3749 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3750 (VCVTDQ2PDZrr VR256X:$src)>;
3751def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3752 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3753 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3754def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3755 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3756 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3757
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3758multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3759 RegisterClass DstRC, PatFrag mem_frag,
3760 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3761let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3762 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3763 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3764 [], d>, EVEX;
3765 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3766 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3767 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3768 let mayLoad = 1 in
3769 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3770 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3771 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3772} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3773}
3774
3775defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3776 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3777 EVEX_V512, EVEX_CD8<32, CD8VF>;
3778defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3779 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3780 EVEX_V512, EVEX_CD8<64, CD8VF>;
3781
3782def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3783 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3784 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3785
3786def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3787 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3788 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3789
3790defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3791 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3792 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3793defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3794 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3795 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3796
3797def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3798 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3799 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3800
3801def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3802 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3803 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3804
3805let Predicates = [HasAVX512] in {
3806 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3807 (VCVTPD2PSZrm addr:$src)>;
3808 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3809 (VCVTPS2PDZrm addr:$src)>;
3810}
3811
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3812//===----------------------------------------------------------------------===//
3813// Half precision conversion instructions
3814//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3815multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3816 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3817 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3818 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3819 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3820 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3821 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3822 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3823}
3824
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3825multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3826 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3827 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3828 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3829 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3830 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3831 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3832 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3833 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3834 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3835}
3836
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3837defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3838 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3839defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3840 EVEX_CD8<32, CD8VH>;
3841
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3842def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3843 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3844 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3845
3846def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3847 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3848 (VCVTPH2PSZrr VR256X:$src)>;
3849
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3850let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3851 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3852 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3853 EVEX_CD8<32, CD8VT1>;
3854 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3855 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3856 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3857 let Pattern = []<dag> in {
3858 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3859 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3860 EVEX_CD8<32, CD8VT1>;
3861 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3862 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3863 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3864 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3865 let isCodeGenOnly = 1 in {
3866 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3867 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3868 EVEX_CD8<32, CD8VT1>;
3869 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3870 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3871 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3872
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3873 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3874 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3875 EVEX_CD8<32, CD8VT1>;
3876 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3877 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3878 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3879 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3880}
3881
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3882/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3883multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3884 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3885 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3886 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3887 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3888 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3889 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3890 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3891 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3892 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3893 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3894 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3895 }
3896}
3897}
3898
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3899defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3900 EVEX_CD8<32, CD8VT1>;
3901defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3902 VEX_W, EVEX_CD8<64, CD8VT1>;
3903defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3904 EVEX_CD8<32, CD8VT1>;
3905defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3906 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3907
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3908def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3909 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3910 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3911 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3912
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3913def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3914 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3915 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3916 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3917
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3918def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3919 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3920 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3921 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3922
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3923def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3924 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3925 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3926 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3927
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3928/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3929multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3930 RegisterClass RC, X86MemOperand x86memop,
3931 PatFrag mem_frag, ValueType OpVt> {
3932 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3933 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3934 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3935 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3936 EVEX;
3937 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3939 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3940 EVEX;
3941}
3942defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3943 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3944defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3945 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3946defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3947 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3948defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3949 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3950
3951def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3952 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3953 (VRSQRT14PSZr VR512:$src)>;
3954def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3955 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3956 (VRSQRT14PDZr VR512:$src)>;
3957
3958def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3959 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3960 (VRCP14PSZr VR512:$src)>;
3961def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3962 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3963 (VRCP14PDZr VR512:$src)>;
3964
3965/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3966multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3967 X86MemOperand x86memop> {
3968 let hasSideEffects = 0, Predicates = [HasERI] in {
3969 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3970 (ins RC:$src1, RC:$src2),
3971 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3972 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3973 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3974 (ins RC:$src1, RC:$src2),
3975 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3976 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3977 []>, EVEX_4V, EVEX_B;
3978 let mayLoad = 1 in {
3979 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3980 (ins RC:$src1, x86memop:$src2),
3981 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3982 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3983 }
3984}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3985}
3986
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3987defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3988 EVEX_CD8<32, CD8VT1>;
3989defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3990 VEX_W, EVEX_CD8<64, CD8VT1>;
3991defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3992 EVEX_CD8<32, CD8VT1>;
3993defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3994 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3995
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3996def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3997 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3998 FROUND_NO_EXC)),
3999 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4000 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4001
4002def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4003 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4004 FROUND_NO_EXC)),
4005 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4006 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4007
4008def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4009 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4010 FROUND_NO_EXC)),
4011 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4012 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4013
4014def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4015 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4016 FROUND_NO_EXC)),
4017 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4018 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4019
4020/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4021multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4022 RegisterClass RC, X86MemOperand x86memop> {
4023 let hasSideEffects = 0, Predicates = [HasERI] in {
4024 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4025 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4026 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4027 []>, EVEX;
4028 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4029 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4030 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4031 []>, EVEX, EVEX_B;
4032 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4033 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4034 []>, EVEX;
4035 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4036}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4037defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4038 EVEX_V512, EVEX_CD8<32, CD8VF>;
4039defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4040 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4041defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4042 EVEX_V512, EVEX_CD8<32, CD8VF>;
4043defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4044 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4045
4046def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4047 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4048 (VRSQRT28PSZrb VR512:$src)>;
4049def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4050 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4051 (VRSQRT28PDZrb VR512:$src)>;
4052
4053def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4054 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4055 (VRCP28PSZrb VR512:$src)>;
4056def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4057 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4058 (VRCP28PDZrb VR512:$src)>;
4059
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4060multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4061 OpndItins itins_s, OpndItins itins_d> {
4062 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4063 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4064 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4065 EVEX, EVEX_V512;
4066
4067 let mayLoad = 1 in
4068 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4069 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4070 [(set VR512:$dst,
4071 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4072 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4073
4074 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4075 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4076 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4077 EVEX, EVEX_V512;
4078
4079 let mayLoad = 1 in
4080 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4081 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4082 [(set VR512:$dst, (OpNode
4083 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4084 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4085
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4086}
4087
4088multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4089 Intrinsic F32Int, Intrinsic F64Int,
4090 OpndItins itins_s, OpndItins itins_d> {
4091 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4092 (ins FR32X:$src1, FR32X:$src2),
4093 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4094 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4095 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4096 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4097 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4098 (ins VR128X:$src1, VR128X:$src2),
4099 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4100 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4101 [(set VR128X:$dst,
4102 (F32Int VR128X:$src1, VR128X:$src2))],
4103 itins_s.rr>, XS, EVEX_4V;
4104 let mayLoad = 1 in {
4105 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4106 (ins FR32X:$src1, f32mem:$src2),
4107 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4108 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4109 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4110 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4111 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4112 (ins VR128X:$src1, ssmem:$src2),
4113 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4114 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4115 [(set VR128X:$dst,
4116 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4117 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4118 }
4119 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4120 (ins FR64X:$src1, FR64X:$src2),
4121 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4122 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4123 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4124 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4125 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4126 (ins VR128X:$src1, VR128X:$src2),
4127 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4128 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4129 [(set VR128X:$dst,
4130 (F64Int VR128X:$src1, VR128X:$src2))],
4131 itins_s.rr>, XD, EVEX_4V, VEX_W;
4132 let mayLoad = 1 in {
4133 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4134 (ins FR64X:$src1, f64mem:$src2),
4135 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4136 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4137 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4138 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4139 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4140 (ins VR128X:$src1, sdmem:$src2),
4141 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4142 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4143 [(set VR128X:$dst,
4144 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4145 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4146 }
4147}
4148
4149
4150defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4151 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4152 SSE_SQRTSS, SSE_SQRTSD>,
4153 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4154 SSE_SQRTPS, SSE_SQRTPD>;
4155
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4156let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4157 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4158 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4159 (VSQRTPSZrr VR512:$src1)>;
4160 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4161 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4162 (VSQRTPDZrr VR512:$src1)>;
4163
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4164 def : Pat<(f32 (fsqrt FR32X:$src)),
4165 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4166 def : Pat<(f32 (fsqrt (load addr:$src))),
4167 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4168 Requires<[OptForSize]>;
4169 def : Pat<(f64 (fsqrt FR64X:$src)),
4170 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4171 def : Pat<(f64 (fsqrt (load addr:$src))),
4172 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4173 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4174
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4175 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4176 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4177 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4178 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4179 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4180
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4181 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4182 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4183 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4184 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4185 Requires<[OptForSize]>;
4186
4187 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4188 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4189 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4190 VR128X)>;
4191 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4192 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4193
4194 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4195 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4196 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4197 VR128X)>;
4198 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4199 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4200}
4201
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4202
4203multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4204 X86MemOperand x86memop, RegisterClass RC,
4205 PatFrag mem_frag32, PatFrag mem_frag64,
4206 Intrinsic V4F32Int, Intrinsic V2F64Int,
4207 CD8VForm VForm> {
4208let ExeDomain = SSEPackedSingle in {
4209 // Intrinsic operation, reg.
4210 // Vector intrinsic operation, reg
4211 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4212 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4213 !strconcat(OpcodeStr,
4214 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4215 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4216
4217 // Vector intrinsic operation, mem
4218 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4219 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4220 !strconcat(OpcodeStr,
4221 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4222 [(set RC:$dst,
4223 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4224 EVEX_CD8<32, VForm>;
4225} // ExeDomain = SSEPackedSingle
4226
4227let ExeDomain = SSEPackedDouble in {
4228 // Vector intrinsic operation, reg
4229 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4230 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4231 !strconcat(OpcodeStr,
4232 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4233 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4234
4235 // Vector intrinsic operation, mem
4236 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4237 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4238 !strconcat(OpcodeStr,
4239 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4240 [(set RC:$dst,
4241 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4242 EVEX_CD8<64, VForm>;
4243} // ExeDomain = SSEPackedDouble
4244}
4245
4246multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4247 string OpcodeStr,
4248 Intrinsic F32Int,
4249 Intrinsic F64Int> {
4250let ExeDomain = GenericDomain in {
4251 // Operation, reg.
4252 let hasSideEffects = 0 in
4253 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4254 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4255 !strconcat(OpcodeStr,
4256 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4257 []>;
4258
4259 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4260 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4261 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4262 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4263 !strconcat(OpcodeStr,
4264 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4265 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4266
4267 // Intrinsic operation, mem.
4268 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4269 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4270 !strconcat(OpcodeStr,
4271 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4272 [(set VR128X:$dst, (F32Int VR128X:$src1,
4273 sse_load_f32:$src2, imm:$src3))]>,
4274 EVEX_CD8<32, CD8VT1>;
4275
4276 // Operation, reg.
4277 let hasSideEffects = 0 in
4278 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4279 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4280 !strconcat(OpcodeStr,
4281 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4282 []>, VEX_W;
4283
4284 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4285 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4286 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4287 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4288 !strconcat(OpcodeStr,
4289 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4290 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4291 VEX_W;
4292
4293 // Intrinsic operation, mem.
4294 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4295 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4296 !strconcat(OpcodeStr,
4297 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4298 [(set VR128X:$dst,
4299 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4300 VEX_W, EVEX_CD8<64, CD8VT1>;
4301} // ExeDomain = GenericDomain
4302}
4303
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4304multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4305 X86MemOperand x86memop, RegisterClass RC,
4306 PatFrag mem_frag, Domain d> {
4307let ExeDomain = d in {
4308 // Intrinsic operation, reg.
4309 // Vector intrinsic operation, reg
4310 def r : AVX512AIi8<opc, MRMSrcReg,
4311 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4312 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4313 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4314 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4315
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4316 // Vector intrinsic operation, mem
4317 def m : AVX512AIi8<opc, MRMSrcMem,
4318 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4319 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4320 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4321 []>, EVEX;
4322} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4323}
4324
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4325
4326defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4327 memopv16f32, SSEPackedSingle>, EVEX_V512,
4328 EVEX_CD8<32, CD8VF>;
4329
4330def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4331 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4332 FROUND_CURRENT)),
4333 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4334
4335
4336defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4337 memopv8f64, SSEPackedDouble>, EVEX_V512,
4338 VEX_W, EVEX_CD8<64, CD8VF>;
4339
4340def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4341 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4342 FROUND_CURRENT)),
4343 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4344
4345multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4346 Operand x86memop, RegisterClass RC, Domain d> {
4347let ExeDomain = d in {
4348 def r : AVX512AIi8<opc, MRMSrcReg,
4349 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4350 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4351 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4352 []>, EVEX_4V;
4353
4354 def m : AVX512AIi8<opc, MRMSrcMem,
4355 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4356 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4357 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4358 []>, EVEX_4V;
4359} // ExeDomain
4360}
4361
4362defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4363 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4364
4365defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4366 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4367
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4368def : Pat<(ffloor FR32X:$src),
4369 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4370def : Pat<(f64 (ffloor FR64X:$src)),
4371 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4372def : Pat<(f32 (fnearbyint FR32X:$src)),
4373 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4374def : Pat<(f64 (fnearbyint FR64X:$src)),
4375 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4376def : Pat<(f32 (fceil FR32X:$src)),
4377 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4378def : Pat<(f64 (fceil FR64X:$src)),
4379 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4380def : Pat<(f32 (frint FR32X:$src)),
4381 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4382def : Pat<(f64 (frint FR64X:$src)),
4383 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4384def : Pat<(f32 (ftrunc FR32X:$src)),
4385 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4386def : Pat<(f64 (ftrunc FR64X:$src)),
4387 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4388
4389def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4390 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4391def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4392 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4393def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4394 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4395def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4396 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4397def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4398 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4399
4400def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4401 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4402def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4403 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4404def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4405 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4406def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4407 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4408def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4409 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4410
4411//-------------------------------------------------
4412// Integer truncate and extend operations
4413//-------------------------------------------------
4414
4415multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4416 RegisterClass dstRC, RegisterClass srcRC,
4417 RegisterClass KRC, X86MemOperand x86memop> {
4418 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4419 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4420 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4421 []>, EVEX;
4422
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4423 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4424 (ins KRC:$mask, srcRC:$src),
4425 !strconcat(OpcodeStr,
4426 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4427 []>, EVEX, EVEX_K;
4428
4429 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4430 (ins KRC:$mask, srcRC:$src),
4431 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4432 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4433 []>, EVEX, EVEX_KZ;
4434
4435 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4436 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4437 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4438
4439 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4440 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4441 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4442 []>, EVEX, EVEX_K;
4443
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4444}
4445defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4446 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4447defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4448 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4449defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4450 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4451defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4452 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4453defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4454 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4455defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4456 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4457defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4458 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4459defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4460 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4461defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4462 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4463defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4464 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4465defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4466 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4467defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4468 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4469defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4470 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4471defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4472 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4473defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4474 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4475
4476def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4477def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4478def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4479def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4480def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4481
4482def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4483 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4484def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4485 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4486def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4487 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4488def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4489 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4490
4491
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4492multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4493 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4494 PatFrag mem_frag, X86MemOperand x86memop,
4495 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4496
4497 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4498 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4499 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4500 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4501
4502 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4503 (ins KRC:$mask, SrcRC:$src),
4504 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4505 []>, EVEX, EVEX_K;
4506
4507 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4508 (ins KRC:$mask, SrcRC:$src),
4509 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4510 []>, EVEX, EVEX_KZ;
4511
4512 let mayLoad = 1 in {
4513 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4514 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4515 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4516 [(set DstRC:$dst,
4517 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4518 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4519
4520 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4521 (ins KRC:$mask, x86memop:$src),
4522 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4523 []>,
4524 EVEX, EVEX_K;
4525
4526 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4527 (ins KRC:$mask, x86memop:$src),
4528 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4529 []>,
4530 EVEX, EVEX_KZ;
4531 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4532}
4533
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4534defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4535 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4536 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4537defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4538 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4539 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4540defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4541 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4542 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4543defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4544 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4545 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4546defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4547 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4548 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4549
4550defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4551 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4552 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4553defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4554 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4555 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4556defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4557 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4558 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4559defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4560 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4561 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4562defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4563 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4564 EVEX_CD8<32, CD8VH>;
4565
4566//===----------------------------------------------------------------------===//
4567// GATHER - SCATTER Operations
4568
4569multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4570 RegisterClass RC, X86MemOperand memop> {
4571let mayLoad = 1,
4572 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4573 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4574 (ins RC:$src1, KRC:$mask, memop:$src2),
4575 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4576 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4577 []>, EVEX, EVEX_K;
4578}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4579
4580let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4581defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4582 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4583defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4585}
4586
4587let ExeDomain = SSEPackedSingle in {
4588defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4589 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4590defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4591 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4592}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593
4594defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4595 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4596defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4597 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4598
4599defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4600 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4601defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4602 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4603
4604multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4605 RegisterClass RC, X86MemOperand memop> {
4606let mayStore = 1, Constraints = "$mask = $mask_wb" in
4607 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4608 (ins memop:$dst, KRC:$mask, RC:$src2),
4609 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4610 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4611 []>, EVEX, EVEX_K;
4612}
4613
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4614let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4615defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4616 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4617defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4618 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4619}
4620
4621let ExeDomain = SSEPackedSingle in {
4622defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4623 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4624defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4625 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4626}
4627
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4628defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4629 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4630defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4631 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4632
4633defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4634 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4635defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4636 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4637
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4638// prefetch
4639multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4640 RegisterClass KRC, X86MemOperand memop> {
4641 let Predicates = [HasPFI], hasSideEffects = 1 in
4642 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4643 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4644 []>, EVEX, EVEX_K;
4645}
4646
4647defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4648 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4649
4650defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4651 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4652
4653defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4654 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4655
4656defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4657 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4658
4659defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4660 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4661
4662defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4663 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4664
4665defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4666 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4667
4668defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4669 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4670
4671defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4672 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4673
4674defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4675 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4676
4677defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4678 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4679
4680defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4681 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4682
4683defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4684 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4685
4686defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4687 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4688
4689defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4690 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4691
4692defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4693 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4694//===----------------------------------------------------------------------===//
4695// VSHUFPS - VSHUFPD Operations
4696
4697multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4698 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4699 Domain d> {
4700 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4701 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4702 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4703 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4704 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4705 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4706 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4707 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4708 (ins RC:$src1, RC:$src2, i8imm:$src3),
4709 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4710 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4711 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4712 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4713 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4714}
4715
4716defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4717 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4718defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4719 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4720
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4721def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4722 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4723def : Pat<(v16i32 (X86Shufp VR512:$src1,
4724 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4725 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4726
4727def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4728 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4729def : Pat<(v8i64 (X86Shufp VR512:$src1,
4730 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4731 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4732
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4733multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4734 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4735 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4736 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4737 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4738 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4739 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4740 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4741
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4742 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4743 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4744 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4745
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4746 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4747 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4748 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4749 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4750 " \t{$src3, $src2, $src1, $dst|"
4751 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4752 []>, EVEX_4V;
4753}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4754defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4755defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4756
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4757// Helper fragments to match sext vXi1 to vXiY.
4758def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4759def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4760
4761multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4762 RegisterClass KRC, RegisterClass RC,
4763 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4764 string BrdcstStr> {
4765 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4766 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4767 []>, EVEX;
4768 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4769 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4770 []>, EVEX, EVEX_K;
4771 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4772 !strconcat(OpcodeStr,
4773 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4774 []>, EVEX, EVEX_KZ;
4775 let mayLoad = 1 in {
4776 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4777 (ins x86memop:$src),
4778 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4779 []>, EVEX;
4780 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4781 (ins KRC:$mask, x86memop:$src),
4782 !strconcat(OpcodeStr,
4783 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4784 []>, EVEX, EVEX_K;
4785 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4786 (ins KRC:$mask, x86memop:$src),
4787 !strconcat(OpcodeStr,
4788 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4789 []>, EVEX, EVEX_KZ;
4790 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4791 (ins x86scalar_mop:$src),
4792 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4793 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4794 []>, EVEX, EVEX_B;
4795 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4796 (ins KRC:$mask, x86scalar_mop:$src),
4797 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4798 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4799 []>, EVEX, EVEX_B, EVEX_K;
4800 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4801 (ins KRC:$mask, x86scalar_mop:$src),
4802 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4803 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4804 BrdcstStr, "}"),
4805 []>, EVEX, EVEX_B, EVEX_KZ;
4806 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4807}
4808
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4809defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4810 i512mem, i32mem, "{1to16}">, EVEX_V512,
4811 EVEX_CD8<32, CD8VF>;
4812defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4813 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4814 EVEX_CD8<64, CD8VF>;
4815
4816def : Pat<(xor
4817 (bc_v16i32 (v16i1sextv16i32)),
4818 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4819 (VPABSDZrr VR512:$src)>;
4820def : Pat<(xor
4821 (bc_v8i64 (v8i1sextv8i64)),
4822 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4823 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4824
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4825def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4826 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4827 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4828def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4829 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4830 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4831
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4832multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4833 RegisterClass RC, RegisterClass KRC,
4834 X86MemOperand x86memop,
4835 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4836 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4837 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4838 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4839 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4840 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4841 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4842 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4843 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4844 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4845 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4846 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4847 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4848 []>, EVEX, EVEX_B;
4849 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4850 (ins KRC:$mask, RC:$src),
4851 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4852 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4853 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4854 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4855 (ins KRC:$mask, x86memop:$src),
4856 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4857 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4858 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4859 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4860 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4861 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4862 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4863 BrdcstStr, "}"),
4864 []>, EVEX, EVEX_KZ, EVEX_B;
4865
4866 let Constraints = "$src1 = $dst" in {
4867 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4868 (ins RC:$src1, KRC:$mask, RC:$src2),
4869 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4870 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4871 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4872 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4873 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4874 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4875 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4876 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4877 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4878 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4879 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4880 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4881 []>, EVEX, EVEX_K, EVEX_B;
4882 }
4883}
4884
4885let Predicates = [HasCDI] in {
4886defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4887 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4888 EVEX_V512, EVEX_CD8<32, CD8VF>;
4889
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4890
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4891defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4892 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4893 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4894
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4895}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4896
4897def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4898 GR16:$mask),
4899 (VPCONFLICTDrrk VR512:$src1,
4900 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4901
4902def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4903 GR8:$mask),
4904 (VPCONFLICTQrrk VR512:$src1,
4905 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4906
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4907let Predicates = [HasCDI] in {
4908defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4909 i512mem, i32mem, "{1to16}">,
4910 EVEX_V512, EVEX_CD8<32, CD8VF>;
4911
4912
4913defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4914 i512mem, i64mem, "{1to8}">,
4915 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4916
4917}
4918
4919def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4920 GR16:$mask),
4921 (VPLZCNTDrrk VR512:$src1,
4922 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4923
4924def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4925 GR8:$mask),
4926 (VPLZCNTQrrk VR512:$src1,
4927 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4928
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]4929def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4930 (VPLZCNTDrm addr:$src)>;
4931def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4932 (VPLZCNTDrr VR512:$src)>;
4933def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4934 (VPLZCNTQrm addr:$src)>;
4935def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4936 (VPLZCNTQrr VR512:$src)>;
4937
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4938def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4939def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4940def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]4941
4942def : Pat<(store VK1:$src, addr:$dst),
4943 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4944
4945def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4946 (truncstore node:$val, node:$ptr), [{
4947 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4948}]>;
4949
4950def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4951 (MOV8mr addr:$dst, GR8:$src)>;
4952
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]4953multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4954def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4955 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4956 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4957}
4958
4959multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4960 string OpcodeStr, Predicate prd> {
4961let Predicates = [prd] in
4962 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4963
4964 let Predicates = [prd, HasVLX] in {
4965 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
4966 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
4967 }
4968}
4969
4970multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
4971 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
4972 HasBWI>;
4973 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
4974 HasBWI>, VEX_W;
4975 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
4976 HasDQI>;
4977 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
4978 HasDQI>, VEX_W;
4979}
4980
4981defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;