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gerrit-public.fairphone.software / toolchain / llvm-project / 52bb6cfad613a23824d01313ff4bf488d9c73dbb / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: c7126296c30b13200c281d63fc0961b7cfee74d7 [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]82}
83
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]84def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
85def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]86def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
87def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]88def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
89def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]90
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]91// "x" in v32i8x_info means RC = VR256X
92def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
93def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
94def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
95def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
96
97def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
98def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
99def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
100def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
101
102class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
103 X86VectorVTInfo i128> {
104 X86VectorVTInfo info512 = i512;
105 X86VectorVTInfo info256 = i256;
106 X86VectorVTInfo info128 = i128;
107}
108
109def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
110 v16i8x_info>;
111def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
112 v8i16x_info>;
113def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
114 v4i32x_info>;
115def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
116 v2i64x_info>;
117
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame^]118// This multiclass generates the masking variants from the non-masking
119// variant. It only provides the assembly pieces for the masking variants.
120// It assumes custom ISel patterns for masking which can be provided as
121// template arguments.
122multiclass AVX512_masking_custom<bits<8> O, Format F,
123 dag Outs,
124 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
125 string OpcodeStr,
126 string AttSrcAsm, string IntelSrcAsm,
127 list<dag> Pattern,
128 list<dag> MaskingPattern,
129 list<dag> ZeroMaskingPattern,
130 string MaskingConstraint = "",
131 InstrItinClass itin = NoItinerary,
132 bit IsCommutable = 0> {
133 let isCommutable = IsCommutable in
134 def NAME: AVX512<O, F, Outs, Ins,
135 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
136 "$dst, "#IntelSrcAsm#"}",
137 Pattern, itin>;
138
139 // Prefer over VMOV*rrk Pat<>
140 let AddedComplexity = 20 in
141 def NAME#k: AVX512<O, F, Outs, MaskingIns,
142 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
143 "$dst {${mask}}, "#IntelSrcAsm#"}",
144 MaskingPattern, itin>,
145 EVEX_K {
146 // In case of the 3src subclass this is overridden with a let.
147 string Constraints = MaskingConstraint;
148 }
149 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
150 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
151 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
152 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
153 ZeroMaskingPattern,
154 itin>,
155 EVEX_KZ;
156}
157
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]158
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]159// Common base class of AVX512_masking and AVX512_masking_3src.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]160multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
161 dag Outs,
162 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]163 string OpcodeStr,
164 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]165 dag RHS, dag MaskingRHS,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]166 string MaskingConstraint = "",
167 InstrItinClass itin = NoItinerary,
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame^]168 bit IsCommutable = 0> :
169 AVX512_masking_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
170 AttSrcAsm, IntelSrcAsm,
171 [(set _.RC:$dst, RHS)],
172 [(set _.RC:$dst, MaskingRHS)],
173 [(set _.RC:$dst,
174 (vselect _.KRCWM:$mask, RHS,
175 (_.VT (bitconvert
176 (v16i32 immAllZerosV)))))],
177 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]178
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]179// This multiclass generates the unconditional/non-masking, the masking and
180// the zero-masking variant of the instruction. In the masking case, the
181// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]182multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
183 dag Outs, dag Ins, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]184 string AttSrcAsm, string IntelSrcAsm,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]185 dag RHS, InstrItinClass itin = NoItinerary,
186 bit IsCommutable = 0> :
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]187 AVX512_masking_common<O, F, _, Outs, Ins,
188 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
189 !con((ins _.KRCWM:$mask), Ins),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]190 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]191 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]192 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]193
194// Similar to AVX512_masking but in this case one of the source operands
195// ($src1) is already tied to $dst so we just use that for the preserved
196// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
197// $src1.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]198multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
199 dag Outs, dag NonTiedIns, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]200 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]201 dag RHS> :
202 AVX512_masking_common<O, F, _, Outs,
203 !con((ins _.RC:$src1), NonTiedIns),
204 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
205 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]206 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]207 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]208
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]209// Bitcasts between 512-bit vector types. Return the original type since
210// no instruction is needed for the conversion
211let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]212 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]213 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]214 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
215 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
216 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]217 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]218 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
219 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
220 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]221 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]222 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]223 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
224 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]225 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]226 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
227 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]228 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]229 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
230 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]231 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]232 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
233 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
234 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
235 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
236 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
237 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
238 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
239 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
240 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
241 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
242 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]243
244 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
245 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
246 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
247 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
248 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
249 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
250 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
251 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
252 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
253 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
254 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
255 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
256 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
257 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
258 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
259 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
260 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
261 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
262 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
263 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
264 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
265 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
266 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
267 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
268 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
269 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
270 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
271 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
272 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
273 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
274
275// Bitcasts between 256-bit vector types. Return the original type since
276// no instruction is needed for the conversion
277 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
278 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
279 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
280 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
281 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
282 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
283 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
284 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
285 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
286 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
287 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
288 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
289 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
290 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
291 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
292 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
293 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
294 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
295 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
296 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
297 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
298 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
299 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
300 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
301 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
302 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
303 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
304 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
305 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
306 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
307}
308
309//
310// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
311//
312
313let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
314 isPseudo = 1, Predicates = [HasAVX512] in {
315def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
316 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
317}
318
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]319let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]320def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
321def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
322def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]323}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]324
325//===----------------------------------------------------------------------===//
326// AVX-512 - VECTOR INSERT
327//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]328
329multiclass vinsert_for_size<int Opcode,
330 X86VectorVTInfo From, X86VectorVTInfo To,
331 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
332 PatFrag vinsert_insert,
333 SDNodeXForm INSERT_get_vinsert_imm> {
334 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
335 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
336 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
337 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
338 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]339 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
340 (From.VT From.RC:$src2),
341 (iPTR imm)))]>,
342 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]343
344 let mayLoad = 1 in
345 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
346 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
347 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
348 "$dst, $src1, $src2, $src3}",
349 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
350 }
351
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]352 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
353 // vinserti32x4
354 def : Pat<(vinsert_insert:$ins
355 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
356 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
357 VR512:$src1, From.RC:$src2,
358 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]359}
360
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]361multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
362 ValueType EltVT64, int Opcode64> {
363 defm NAME # "32x4" : vinsert_for_size<Opcode32,
364 X86VectorVTInfo< 4, EltVT32, VR128X>,
365 X86VectorVTInfo<16, EltVT32, VR512>,
366 X86VectorVTInfo< 2, EltVT64, VR128X>,
367 X86VectorVTInfo< 8, EltVT64, VR512>,
368 vinsert128_insert,
369 INSERT_get_vinsert128_imm>;
370 defm NAME # "64x4" : vinsert_for_size<Opcode64,
371 X86VectorVTInfo< 4, EltVT64, VR256X>,
372 X86VectorVTInfo< 8, EltVT64, VR512>,
373 X86VectorVTInfo< 8, EltVT32, VR256>,
374 X86VectorVTInfo<16, EltVT32, VR512>,
375 vinsert256_insert,
376 INSERT_get_vinsert256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]377}
378
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]379defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
380defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]381
382// vinsertps - insert f32 to XMM
383def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]384 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]385 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]386 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]387 EVEX_4V;
388def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]389 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]390 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]391 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]392 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
393 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
394
395//===----------------------------------------------------------------------===//
396// AVX-512 VECTOR EXTRACT
397//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]398
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]399multiclass vextract_for_size<int Opcode,
400 X86VectorVTInfo From, X86VectorVTInfo To,
401 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
402 PatFrag vextract_extract,
403 SDNodeXForm EXTRACT_get_vextract_imm> {
404 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
405 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
Adam Nemetf7988d72014-09-25 23:48:49 +0000[diff] [blame]406 (ins VR512:$src1, i8imm:$idx),
407 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
408 "$dst, $src1, $idx}",
409 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
410 (iPTR imm)))]>,
411 EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]412 let mayStore = 1 in
413 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
414 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
415 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
416 "$dst, $src1, $src2}",
417 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
418 }
419
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]420 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
421 // vextracti32x4
422 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
423 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
424 VR512:$src1,
425 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
426
427 // A 128/256-bit subvector extract from the first 512-bit vector position is
428 // a subregister copy that needs no instruction.
429 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
430 (To.VT
431 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
432
433 // And for the alternative types.
434 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
435 (AltTo.VT
436 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]437}
438
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]439multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
440 ValueType EltVT64, int Opcode64> {
441 defm NAME # "32x4" : vextract_for_size<Opcode32,
442 X86VectorVTInfo<16, EltVT32, VR512>,
443 X86VectorVTInfo< 4, EltVT32, VR128X>,
444 X86VectorVTInfo< 8, EltVT64, VR512>,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 vextract128_extract,
447 EXTRACT_get_vextract128_imm>;
448 defm NAME # "64x4" : vextract_for_size<Opcode64,
449 X86VectorVTInfo< 8, EltVT64, VR512>,
450 X86VectorVTInfo< 4, EltVT64, VR256X>,
451 X86VectorVTInfo<16, EltVT32, VR512>,
452 X86VectorVTInfo< 8, EltVT32, VR256>,
453 vextract256_extract,
454 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]455}
456
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]457defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
458defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]459
460// A 128-bit subvector insert to the first 512-bit vector position
461// is a subregister copy that needs no instruction.
462def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
463 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
464 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
465 sub_ymm)>;
466def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
467 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
468 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
469 sub_ymm)>;
470def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
471 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
472 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
473 sub_ymm)>;
474def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
475 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
476 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
477 sub_ymm)>;
478
479def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
480 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
481def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
482 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
483def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
484 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
485def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
486 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
487
488// vextractps - extract 32 bits from XMM
489def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]490 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]491 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]492 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
493 EVEX;
494
495def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]496 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]497 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]498 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]499 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]500
501//===---------------------------------------------------------------------===//
502// AVX-512 BROADCAST
503//---
504multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DestRC,
506 RegisterClass SrcRC, X86MemOperand x86memop> {
507 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]508 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]509 []>, EVEX;
510 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]511 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]512}
513let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]514 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]515 VR128X, f32mem>,
516 EVEX_V512, EVEX_CD8<32, CD8VT1>;
517}
518
519let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]520 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]521 VR128X, f64mem>,
522 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
523}
524
525def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
526 (VBROADCASTSSZrm addr:$src)>;
527def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
528 (VBROADCASTSDZrm addr:$src)>;
529
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]530def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
531 (VBROADCASTSSZrm addr:$src)>;
532def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
533 (VBROADCASTSDZrm addr:$src)>;
534
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]535multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
536 RegisterClass SrcRC, RegisterClass KRC> {
537 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]538 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]539 []>, EVEX, EVEX_V512;
540 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
541 (ins KRC:$mask, SrcRC:$src),
542 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]543 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]544 []>, EVEX, EVEX_V512, EVEX_KZ;
545}
546
547defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
548defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
549 VEX_W;
550
551def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
552 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
553
554def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
555 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
556
557def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
558 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]559def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
560 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]561def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
562 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]563def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
564 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]565
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]566def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
567 (VPBROADCASTDrZrr GR32:$src)>;
568def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
569 (VPBROADCASTQrZrr GR64:$src)>;
570
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]571def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
572 (v16i32 immAllZerosV), (i16 GR16:$mask))),
573 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
574def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
575 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
576 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
577
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]578multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
579 X86MemOperand x86memop, PatFrag ld_frag,
580 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
581 RegisterClass KRC> {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]583 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]584 [(set DstRC:$dst,
585 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
586 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
587 VR128X:$src),
588 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]589 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]590 [(set DstRC:$dst,
591 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
592 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]593 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]594 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]595 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]596 [(set DstRC:$dst,
597 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
598 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
599 x86memop:$src),
600 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]601 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]602 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
603 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]604 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]605}
606
607defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
608 loadi32, VR512, v16i32, v4i32, VK16WM>,
609 EVEX_V512, EVEX_CD8<32, CD8VT1>;
610defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
611 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
612 EVEX_CD8<64, CD8VT1>;
613
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]614multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
615 X86MemOperand x86memop, PatFrag ld_frag,
616 RegisterClass KRC> {
617 let mayLoad = 1 in {
618 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
619 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
620 []>, EVEX;
621 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
622 x86memop:$src),
623 !strconcat(OpcodeStr,
624 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
625 []>, EVEX, EVEX_KZ;
626 }
627}
628
629defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
630 i128mem, loadv2i64, VK16WM>,
631 EVEX_V512, EVEX_CD8<32, CD8VT4>;
632defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
633 i256mem, loadv4i64, VK16WM>, VEX_W,
634 EVEX_V512, EVEX_CD8<64, CD8VT4>;
635
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]636def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
637 (VPBROADCASTDZrr VR128X:$src)>;
638def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
639 (VPBROADCASTQZrr VR128X:$src)>;
640
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]641def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
642 (VBROADCASTSSZrr VR128X:$src)>;
643def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
644 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]645
646def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
647 (VBROADCASTSSZrr VR128X:$src)>;
648def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
649 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]650
651// Provide fallback in case the load node that is used in the patterns above
652// is used by additional users, which prevents the pattern selection.
653def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
654 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
655def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
656 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
657
658
659let Predicates = [HasAVX512] in {
660def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
661 (EXTRACT_SUBREG
662 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
663 addr:$src)), sub_ymm)>;
664}
665//===----------------------------------------------------------------------===//
666// AVX-512 BROADCAST MASK TO VECTOR REGISTER
667//---
668
669multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
670 RegisterClass DstRC, RegisterClass KRC,
671 ValueType OpVT, ValueType SrcVT> {
672def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]673 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]674 []>, EVEX;
675}
676
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]677let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]678defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
679 VK16, v16i32, v16i1>, EVEX_V512;
680defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
681 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]682}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]683
684//===----------------------------------------------------------------------===//
685// AVX-512 - VPERM
686//
687// -- immediate form --
688multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
689 SDNode OpNode, PatFrag mem_frag,
690 X86MemOperand x86memop, ValueType OpVT> {
691 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
692 (ins RC:$src1, i8imm:$src2),
693 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]694 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]695 [(set RC:$dst,
696 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
697 EVEX;
698 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
699 (ins x86memop:$src1, i8imm:$src2),
700 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]701 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]702 [(set RC:$dst,
703 (OpVT (OpNode (mem_frag addr:$src1),
704 (i8 imm:$src2))))]>, EVEX;
705}
706
707defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
708 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
709let ExeDomain = SSEPackedDouble in
710defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
711 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
712
713// -- VPERM - register form --
714multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
715 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
716
717 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
718 (ins RC:$src1, RC:$src2),
719 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]720 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]721 [(set RC:$dst,
722 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
723
724 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
725 (ins RC:$src1, x86memop:$src2),
726 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]727 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]728 [(set RC:$dst,
729 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
730 EVEX_4V;
731}
732
733defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
734 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
735defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
736 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
737let ExeDomain = SSEPackedSingle in
738defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
739 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
740let ExeDomain = SSEPackedDouble in
741defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
742 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
743
744// -- VPERM2I - 3 source operands form --
745multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
746 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]747 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]748let Constraints = "$src1 = $dst" in {
749 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
750 (ins RC:$src1, RC:$src2, RC:$src3),
751 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]752 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]753 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]754 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]755 EVEX_4V;
756
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]757 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
758 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
759 !strconcat(OpcodeStr,
760 " \t{$src3, $src2, $dst {${mask}}|"
761 "$dst {${mask}}, $src2, $src3}"),
762 [(set RC:$dst, (OpVT (vselect KRC:$mask,
763 (OpNode RC:$src1, RC:$src2,
764 RC:$src3),
765 RC:$src1)))]>,
766 EVEX_4V, EVEX_K;
767
768 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
769 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
770 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
771 !strconcat(OpcodeStr,
772 " \t{$src3, $src2, $dst {${mask}} {z} |",
773 "$dst {${mask}} {z}, $src2, $src3}"),
774 [(set RC:$dst, (OpVT (vselect KRC:$mask,
775 (OpNode RC:$src1, RC:$src2,
776 RC:$src3),
777 (OpVT (bitconvert
778 (v16i32 immAllZerosV))))))]>,
779 EVEX_4V, EVEX_KZ;
780
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]781 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
782 (ins RC:$src1, RC:$src2, x86memop:$src3),
783 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]784 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]785 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]786 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]787 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]788
789 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
790 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
791 !strconcat(OpcodeStr,
792 " \t{$src3, $src2, $dst {${mask}}|"
793 "$dst {${mask}}, $src2, $src3}"),
794 [(set RC:$dst,
795 (OpVT (vselect KRC:$mask,
796 (OpNode RC:$src1, RC:$src2,
797 (mem_frag addr:$src3)),
798 RC:$src1)))]>,
799 EVEX_4V, EVEX_K;
800
801 let AddedComplexity = 10 in // Prefer over the rrkz variant
802 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
803 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
804 !strconcat(OpcodeStr,
805 " \t{$src3, $src2, $dst {${mask}} {z}|"
806 "$dst {${mask}} {z}, $src2, $src3}"),
807 [(set RC:$dst,
808 (OpVT (vselect KRC:$mask,
809 (OpNode RC:$src1, RC:$src2,
810 (mem_frag addr:$src3)),
811 (OpVT (bitconvert
812 (v16i32 immAllZerosV))))))]>,
813 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]814 }
815}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]816defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
817 i512mem, X86VPermiv3, v16i32, VK16WM>,
818 EVEX_V512, EVEX_CD8<32, CD8VF>;
819defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
820 i512mem, X86VPermiv3, v8i64, VK8WM>,
821 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
822defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
823 i512mem, X86VPermiv3, v16f32, VK16WM>,
824 EVEX_V512, EVEX_CD8<32, CD8VF>;
825defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
826 i512mem, X86VPermiv3, v8f64, VK8WM>,
827 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]828
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]829multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
830 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]831 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
832 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]833 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
834 OpVT, KRC> {
835 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
836 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
837 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]838
839 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
840 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
841 (!cast<Instruction>(NAME#rrk) VR512:$src1,
842 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]843}
844
845defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]846 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
847 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]848defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]849 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
850 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]851defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]852 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
853 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]854defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]855 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
856 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]857
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]858//===----------------------------------------------------------------------===//
859// AVX-512 - BLEND using mask
860//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]861multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]862 RegisterClass KRC, RegisterClass RC,
863 X86MemOperand x86memop, PatFrag mem_frag,
864 SDNode OpNode, ValueType vt> {
865 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]866 (ins KRC:$mask, RC:$src1, RC:$src2),
867 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]868 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]869 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]870 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]871 let mayLoad = 1 in
872 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
873 (ins KRC:$mask, RC:$src1, x86memop:$src2),
874 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]875 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]876 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]877}
878
879let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]880defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]881 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]882 memopv16f32, vselect, v16f32>,
883 EVEX_CD8<32, CD8VF>, EVEX_V512;
884let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]885defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]886 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]887 memopv8f64, vselect, v8f64>,
888 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
889
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]890def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
891 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]892 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]893 VR512:$src1, VR512:$src2)>;
894
895def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
896 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]897 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]898 VR512:$src1, VR512:$src2)>;
899
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]900defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]901 VK16WM, VR512, f512mem,
902 memopv16i32, vselect, v16i32>,
903 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]904
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]905defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]906 VK8WM, VR512, f512mem,
907 memopv8i64, vselect, v8i64>,
908 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]909
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]910def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
911 (v16i32 VR512:$src2), (i16 GR16:$mask))),
912 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
913 VR512:$src1, VR512:$src2)>;
914
915def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
916 (v8i64 VR512:$src2), (i8 GR8:$mask))),
917 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
918 VR512:$src1, VR512:$src2)>;
919
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]920let Predicates = [HasAVX512] in {
921def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
922 (v8f32 VR256X:$src2))),
923 (EXTRACT_SUBREG
924 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
925 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
926 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
927
928def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
929 (v8i32 VR256X:$src2))),
930 (EXTRACT_SUBREG
931 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
932 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
933 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
934}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]935//===----------------------------------------------------------------------===//
936// Compare Instructions
937//===----------------------------------------------------------------------===//
938
939// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
940multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
941 Operand CC, SDNode OpNode, ValueType VT,
942 PatFrag ld_frag, string asm, string asm_alt> {
943 def rr : AVX512Ii8<0xC2, MRMSrcReg,
944 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
945 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
946 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
947 def rm : AVX512Ii8<0xC2, MRMSrcMem,
948 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
949 [(set VK1:$dst, (OpNode (VT RC:$src1),
950 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]951 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]952 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
953 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
954 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
955 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
956 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
957 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
958 }
959}
960
961let Predicates = [HasAVX512] in {
962defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
963 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
964 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
965 XS;
966defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
967 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
968 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
969 XD, VEX_W;
970}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]971
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]972multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
973 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]974 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]975 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
976 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
977 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]978 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]979 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]980 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]981 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
983 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
984 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]985 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]986 def rrk : AVX512BI<opc, MRMSrcReg,
987 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
989 "$dst {${mask}}, $src1, $src2}"),
990 [(set _.KRC:$dst, (and _.KRCWM:$mask,
991 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
992 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
993 let mayLoad = 1 in
994 def rmk : AVX512BI<opc, MRMSrcMem,
995 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
996 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
997 "$dst {${mask}}, $src1, $src2}"),
998 [(set _.KRC:$dst, (and _.KRCWM:$mask,
999 (OpNode (_.VT _.RC:$src1),
1000 (_.VT (bitconvert
1001 (_.LdFrag addr:$src2))))))],
1002 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1003}
1004
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1005multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1006 X86VectorVTInfo _> :
1007 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1008 let mayLoad = 1 in {
1009 def rmb : AVX512BI<opc, MRMSrcMem,
1010 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1011 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1012 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1013 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1014 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1015 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1016 def rmbk : AVX512BI<opc, MRMSrcMem,
1017 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1018 _.ScalarMemOp:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1021 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1022 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1023 (OpNode (_.VT _.RC:$src1),
1024 (X86VBroadcast
1025 (_.ScalarLdFrag addr:$src2)))))],
1026 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1027 }
1028}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1029
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1030multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1031 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1032 let Predicates = [prd] in
1033 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1034 EVEX_V512;
1035
1036 let Predicates = [prd, HasVLX] in {
1037 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1038 EVEX_V256;
1039 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1040 EVEX_V128;
1041 }
1042}
1043
1044multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1045 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1046 Predicate prd> {
1047 let Predicates = [prd] in
1048 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1049 EVEX_V512;
1050
1051 let Predicates = [prd, HasVLX] in {
1052 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1053 EVEX_V256;
1054 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1055 EVEX_V128;
1056 }
1057}
1058
1059defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1060 avx512vl_i8_info, HasBWI>,
1061 EVEX_CD8<8, CD8VF>;
1062
1063defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1064 avx512vl_i16_info, HasBWI>,
1065 EVEX_CD8<16, CD8VF>;
1066
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1067defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1068 avx512vl_i32_info, HasAVX512>,
1069 EVEX_CD8<32, CD8VF>;
1070
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1071defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1072 avx512vl_i64_info, HasAVX512>,
1073 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1074
1075defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1076 avx512vl_i8_info, HasBWI>,
1077 EVEX_CD8<8, CD8VF>;
1078
1079defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1080 avx512vl_i16_info, HasBWI>,
1081 EVEX_CD8<16, CD8VF>;
1082
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1083defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1084 avx512vl_i32_info, HasAVX512>,
1085 EVEX_CD8<32, CD8VF>;
1086
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1087defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1088 avx512vl_i64_info, HasAVX512>,
1089 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1090
1091def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1092 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1093 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1094 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1095
1096def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1097 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1098 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1099 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1100
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1101multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1102 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1103 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1104 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1105 !strconcat("vpcmp${cc}", Suffix,
1106 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1107 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1108 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1109 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1110 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1111 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1112 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1113 !strconcat("vpcmp${cc}", Suffix,
1114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1115 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1116 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1117 imm:$cc))],
1118 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1119 def rrik : AVX512AIi8<opc, MRMSrcReg,
1120 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1121 AVXCC:$cc),
1122 !strconcat("vpcmp${cc}", Suffix,
1123 "\t{$src2, $src1, $dst {${mask}}|",
1124 "$dst {${mask}}, $src1, $src2}"),
1125 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1126 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1127 imm:$cc)))],
1128 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1129 let mayLoad = 1 in
1130 def rmik : AVX512AIi8<opc, MRMSrcMem,
1131 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1132 AVXCC:$cc),
1133 !strconcat("vpcmp${cc}", Suffix,
1134 "\t{$src2, $src1, $dst {${mask}}|",
1135 "$dst {${mask}}, $src1, $src2}"),
1136 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1137 (OpNode (_.VT _.RC:$src1),
1138 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1139 imm:$cc)))],
1140 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1141
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1142 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1143 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1144 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1145 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1146 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1147 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1148 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1149 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1150 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1151 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1152 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1153 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1154 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1155 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1156 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1157 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1158 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1159 "$dst {${mask}}, $src1, $src2, $cc}"),
1160 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1161 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1162 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1163 i8imm:$cc),
1164 !strconcat("vpcmp", Suffix,
1165 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1166 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1167 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1168 }
1169}
1170
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1171multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1172 X86VectorVTInfo _> :
1173 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1174 let mayLoad = 1 in {
1175 def rmib : AVX512AIi8<opc, MRMSrcMem,
1176 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1177 AVXCC:$cc),
1178 !strconcat("vpcmp${cc}", Suffix,
1179 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1180 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1181 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1182 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1183 imm:$cc))],
1184 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1185 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1186 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1187 _.ScalarMemOp:$src2, AVXCC:$cc),
1188 !strconcat("vpcmp${cc}", Suffix,
1189 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1190 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1191 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1192 (OpNode (_.VT _.RC:$src1),
1193 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1194 imm:$cc)))],
1195 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1196 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1197
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1198 // Accept explicit immediate argument form instead of comparison code.
1199 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1200 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1201 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1202 i8imm:$cc),
1203 !strconcat("vpcmp", Suffix,
1204 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1205 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1206 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1207 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1208 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1209 _.ScalarMemOp:$src2, i8imm:$cc),
1210 !strconcat("vpcmp", Suffix,
1211 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1212 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1213 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1214 }
1215}
1216
1217multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1218 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1219 let Predicates = [prd] in
1220 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1221
1222 let Predicates = [prd, HasVLX] in {
1223 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1224 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1225 }
1226}
1227
1228multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1229 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1230 let Predicates = [prd] in
1231 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1232 EVEX_V512;
1233
1234 let Predicates = [prd, HasVLX] in {
1235 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1236 EVEX_V256;
1237 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1238 EVEX_V128;
1239 }
1240}
1241
1242defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1243 HasBWI>, EVEX_CD8<8, CD8VF>;
1244defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1245 HasBWI>, EVEX_CD8<8, CD8VF>;
1246
1247defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1248 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1249defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1250 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1251
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1252defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1253 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1254defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1255 HasAVX512>, EVEX_CD8<32, CD8VF>;
1256
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1257defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1258 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1259defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1260 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1261
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1262// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1263multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1264 X86MemOperand x86memop, ValueType vt,
1265 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1266 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1267 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1268 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1269 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1270 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1271 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1272 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1273 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1274 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1275 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1276 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1277 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1278 !strconcat("vcmp${cc}", suffix,
1279 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1280 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1281 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1282
1283 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1284 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1285 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1286 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1287 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1288 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1289 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1290 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1291 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1292 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1293 }
1294}
1295
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1296defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1297 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1298 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1299defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1300 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1301 EVEX_CD8<64, CD8VF>;
1302
1303def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1304 (COPY_TO_REGCLASS (VCMPPSZrri
1305 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1306 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1307 imm:$cc), VK8)>;
1308def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1309 (COPY_TO_REGCLASS (VPCMPDZrri
1310 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1311 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1312 imm:$cc), VK8)>;
1313def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1314 (COPY_TO_REGCLASS (VPCMPUDZrri
1315 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1316 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1317 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1318
1319def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1320 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1321 FROUND_NO_EXC)),
1322 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1323 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1324
1325def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1326 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1327 FROUND_NO_EXC)),
1328 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1329 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1330
1331def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1332 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1333 FROUND_CURRENT)),
1334 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1335 (I8Imm imm:$cc)), GR16)>;
1336
1337def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1338 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1339 FROUND_CURRENT)),
1340 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1341 (I8Imm imm:$cc)), GR8)>;
1342
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1343// Mask register copy, including
1344// - copy between mask registers
1345// - load/store mask registers
1346// - copy from GPR to mask register and vice versa
1347//
1348multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1349 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1350 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1351 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1352 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1353 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1354 let mayLoad = 1 in
1355 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1356 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1357 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1358 let mayStore = 1 in
1359 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1360 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1361 }
1362}
1363
1364multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1365 string OpcodeStr,
1366 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1367 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1368 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1369 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1370 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1371 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1372 }
1373}
1374
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1375let Predicates = [HasDQI] in
1376 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1377 i8mem>,
1378 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1379 VEX, PD;
1380
1381let Predicates = [HasAVX512] in
1382 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1383 i16mem>,
1384 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1385 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1386
1387let Predicates = [HasBWI] in {
1388 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1389 i32mem>, VEX, PD, VEX_W;
1390 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1391 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1392}
1393
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1394let Predicates = [HasBWI] in {
1395 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1396 i64mem>, VEX, PS, VEX_W;
1397 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1398 VEX, XD, VEX_W;
1399}
1400
1401// GR from/to mask register
1402let Predicates = [HasDQI] in {
1403 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1404 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1405 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1406 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1407}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1408let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1409 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1410 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1411 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1412 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1413}
1414let Predicates = [HasBWI] in {
1415 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1416 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1417}
1418let Predicates = [HasBWI] in {
1419 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1420 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1421}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1422
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1423// Load/store kreg
1424let Predicates = [HasDQI] in {
1425 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1426 (KMOVBmk addr:$dst, VK8:$src)>;
1427}
1428let Predicates = [HasAVX512] in {
1429 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1430 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1431 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1432 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1433 def : Pat<(i1 (load addr:$src)),
1434 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1435 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1436 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1437}
1438let Predicates = [HasBWI] in {
1439 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1440 (KMOVDmk addr:$dst, VK32:$src)>;
1441}
1442let Predicates = [HasBWI] in {
1443 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1444 (KMOVQmk addr:$dst, VK64:$src)>;
1445}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1446
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1447let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1448 def : Pat<(i1 (trunc (i64 GR64:$src))),
1449 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1450 (i32 1))), VK1)>;
1451
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1452 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1453 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1454
1455 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1456 (COPY_TO_REGCLASS
1457 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1458 VK1)>;
1459 def : Pat<(i1 (trunc (i16 GR16:$src))),
1460 (COPY_TO_REGCLASS
1461 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1462 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1463
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1464 def : Pat<(i32 (zext VK1:$src)),
1465 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1466 def : Pat<(i8 (zext VK1:$src)),
1467 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1468 (AND32ri (KMOVWrk
1469 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1470 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1471 (AND64ri8 (SUBREG_TO_REG (i64 0),
1472 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1473 def : Pat<(i16 (zext VK1:$src)),
1474 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1475 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1476 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1477 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1478 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1479 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1480 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1481}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1482let Predicates = [HasBWI] in {
1483 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1484 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1485 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1486 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1487}
1488
1489
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1490// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1491let Predicates = [HasAVX512] in {
1492 // GR from/to 8-bit mask without native support
1493 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1494 (COPY_TO_REGCLASS
1495 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1496 VK8)>;
1497 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1498 (EXTRACT_SUBREG
1499 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1500 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1501
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1502 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1503 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1504 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1505 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1506}
1507let Predicates = [HasBWI] in {
1508 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1509 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1510 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1511 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1512}
1513
1514// Mask unary operation
1515// - KNOT
1516multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1517 RegisterClass KRC, SDPatternOperator OpNode,
1518 Predicate prd> {
1519 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1520 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1521 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1522 [(set KRC:$dst, (OpNode KRC:$src))]>;
1523}
1524
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1525multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1526 SDPatternOperator OpNode> {
1527 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1528 HasDQI>, VEX, PD;
1529 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1530 HasAVX512>, VEX, PS;
1531 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1532 HasBWI>, VEX, PD, VEX_W;
1533 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1534 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1535}
1536
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1537defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1538
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1539multiclass avx512_mask_unop_int<string IntName, string InstName> {
1540 let Predicates = [HasAVX512] in
1541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1542 (i16 GR16:$src)),
1543 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1544 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1545}
1546defm : avx512_mask_unop_int<"knot", "KNOT">;
1547
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1548let Predicates = [HasDQI] in
1549def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1550let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1551def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1552let Predicates = [HasBWI] in
1553def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1554let Predicates = [HasBWI] in
1555def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1556
1557// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1558let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1559def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1560 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1561
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1562def : Pat<(not VK8:$src),
1563 (COPY_TO_REGCLASS
1564 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1565}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1566
1567// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1568// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1569multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1570 RegisterClass KRC, SDPatternOperator OpNode,
1571 Predicate prd> {
1572 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1573 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1574 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1575 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1576 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1577}
1578
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1579multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1580 SDPatternOperator OpNode> {
1581 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1582 HasDQI>, VEX_4V, VEX_L, PD;
1583 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1584 HasAVX512>, VEX_4V, VEX_L, PS;
1585 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1586 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1587 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1588 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1589}
1590
1591def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1592def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1593
1594let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1595 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1596 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1597 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1598 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1599}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1600let isCommutable = 0 in
1601 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1602
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1603def : Pat<(xor VK1:$src1, VK1:$src2),
1604 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1605 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1606
1607def : Pat<(or VK1:$src1, VK1:$src2),
1608 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1609 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1610
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1611def : Pat<(and VK1:$src1, VK1:$src2),
1612 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1613 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1614
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1615multiclass avx512_mask_binop_int<string IntName, string InstName> {
1616 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1617 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1618 (i16 GR16:$src1), (i16 GR16:$src2)),
1619 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1620 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1621 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1622}
1623
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1624defm : avx512_mask_binop_int<"kand", "KAND">;
1625defm : avx512_mask_binop_int<"kandn", "KANDN">;
1626defm : avx512_mask_binop_int<"kor", "KOR">;
1627defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1628defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1629
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1630// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1631multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1632 let Predicates = [HasAVX512] in
1633 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1634 (COPY_TO_REGCLASS
1635 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1636 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1637}
1638
1639defm : avx512_binop_pat<and, KANDWrr>;
1640defm : avx512_binop_pat<andn, KANDNWrr>;
1641defm : avx512_binop_pat<or, KORWrr>;
1642defm : avx512_binop_pat<xnor, KXNORWrr>;
1643defm : avx512_binop_pat<xor, KXORWrr>;
1644
1645// Mask unpacking
1646multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1647 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1648 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1649 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1650 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1651 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1652}
1653
1654multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1655 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1656 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1657}
1658
1659defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1660def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1661 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1662 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1663
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1664
1665multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1666 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1667 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1668 (i16 GR16:$src1), (i16 GR16:$src2)),
1669 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1670 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1671 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1672}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1673defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1674
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1675// Mask bit testing
1676multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1677 SDNode OpNode> {
1678 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1679 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1680 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1681 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1682}
1683
1684multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1685 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1686 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1687}
1688
1689defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1690
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1691def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1692 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1693 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1694
1695// Mask shift
1696multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1697 SDNode OpNode> {
1698 let Predicates = [HasAVX512] in
1699 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1700 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1701 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1702 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1703}
1704
1705multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1706 SDNode OpNode> {
1707 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1708 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1709}
1710
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1711defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1712defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1713
1714// Mask setting all 0s or 1s
1715multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1716 let Predicates = [HasAVX512] in
1717 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1718 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1719 [(set KRC:$dst, (VT Val))]>;
1720}
1721
1722multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1723 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1724 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1725}
1726
1727defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1728defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1729
1730// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1731let Predicates = [HasAVX512] in {
1732 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1733 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1734 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1735 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1736 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1737}
1738def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1739 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1740
1741def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1742 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1743
1744def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1745 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1746
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1747let Predicates = [HasVLX] in {
1748 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1749 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1750 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1751 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1752 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1753 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1754 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1755 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1756}
1757
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1758def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1759 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1760
1761def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1762 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1763//===----------------------------------------------------------------------===//
1764// AVX-512 - Aligned and unaligned load and store
1765//
1766
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1767multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1768 RegisterClass KRC, RegisterClass RC,
1769 ValueType vt, ValueType zvt, X86MemOperand memop,
1770 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1771let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1772 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1773 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1774 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1775 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1776 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1777 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1778 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1779 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1780 SchedRW = [WriteLoad] in
1781 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1782 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1783 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1784 d>, EVEX;
1785
1786 let AddedComplexity = 20 in {
1787 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1788 let hasSideEffects = 0 in
1789 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1790 (ins RC:$src0, KRC:$mask, RC:$src1),
1791 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1792 "${dst} {${mask}}, $src1}"),
1793 [(set RC:$dst, (vt (vselect KRC:$mask,
1794 (vt RC:$src1),
1795 (vt RC:$src0))))],
1796 d>, EVEX, EVEX_K;
1797 let mayLoad = 1, SchedRW = [WriteLoad] in
1798 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1799 (ins RC:$src0, KRC:$mask, memop:$src1),
1800 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1801 "${dst} {${mask}}, $src1}"),
1802 [(set RC:$dst, (vt
1803 (vselect KRC:$mask,
1804 (vt (bitconvert (ld_frag addr:$src1))),
1805 (vt RC:$src0))))],
1806 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1807 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1808 let mayLoad = 1, SchedRW = [WriteLoad] in
1809 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1810 (ins KRC:$mask, memop:$src),
1811 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1812 "${dst} {${mask}} {z}, $src}"),
1813 [(set RC:$dst, (vt
1814 (vselect KRC:$mask,
1815 (vt (bitconvert (ld_frag addr:$src))),
1816 (vt (bitconvert (zvt immAllZerosV))))))],
1817 d>, EVEX, EVEX_KZ;
1818 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1819}
1820
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1821multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1822 string elty, string elsz, string vsz512,
1823 string vsz256, string vsz128, Domain d,
1824 Predicate prd, bit IsReMaterializable = 1> {
1825 let Predicates = [prd] in
1826 defm Z : avx512_load<opc, OpcodeStr,
1827 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1828 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1829 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1830 !cast<X86MemOperand>(elty##"512mem"), d,
1831 IsReMaterializable>, EVEX_V512;
1832
1833 let Predicates = [prd, HasVLX] in {
1834 defm Z256 : avx512_load<opc, OpcodeStr,
1835 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1836 "v"##vsz256##elty##elsz, "v4i64")),
1837 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1838 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1839 !cast<X86MemOperand>(elty##"256mem"), d,
1840 IsReMaterializable>, EVEX_V256;
1841
1842 defm Z128 : avx512_load<opc, OpcodeStr,
1843 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1844 "v"##vsz128##elty##elsz, "v2i64")),
1845 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1846 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1847 !cast<X86MemOperand>(elty##"128mem"), d,
1848 IsReMaterializable>, EVEX_V128;
1849 }
1850}
1851
1852
1853multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1854 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1855 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1856 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1857 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1858 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1859 EVEX;
1860 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1861 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1862 (ins RC:$src1, KRC:$mask, RC:$src2),
1863 !strconcat(OpcodeStr,
1864 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1865 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1866 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1867 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1868 !strconcat(OpcodeStr,
1869 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1870 [], d>, EVEX, EVEX_KZ;
1871 }
1872 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1873 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1874 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1875 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1876 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1877 (ins memop:$dst, KRC:$mask, RC:$src),
1878 !strconcat(OpcodeStr,
1879 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1880 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1881 }
1882}
1883
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1884
1885multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1886 string st_suff_512, string st_suff_256,
1887 string st_suff_128, string elty, string elsz,
1888 string vsz512, string vsz256, string vsz128,
1889 Domain d, Predicate prd> {
1890 let Predicates = [prd] in
1891 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1892 !cast<ValueType>("v"##vsz512##elty##elsz),
1893 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1894 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1895
1896 let Predicates = [prd, HasVLX] in {
1897 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1898 !cast<ValueType>("v"##vsz256##elty##elsz),
1899 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1900 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1901
1902 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1903 !cast<ValueType>("v"##vsz128##elty##elsz),
1904 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1905 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1906 }
1907}
1908
1909defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1910 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1911 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1912 "512", "256", "", "f", "32", "16", "8", "4",
1913 SSEPackedSingle, HasAVX512>,
1914 PS, EVEX_CD8<32, CD8VF>;
1915
1916defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1917 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1918 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1919 "512", "256", "", "f", "64", "8", "4", "2",
1920 SSEPackedDouble, HasAVX512>,
1921 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1922
1923defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1924 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1925 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1926 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1927 PS, EVEX_CD8<32, CD8VF>;
1928
1929defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1930 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1931 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1932 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1933 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1934
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1935def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1936 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1937 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1938
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1939def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1940 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1941 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1942
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1943def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1944 GR16:$mask),
1945 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1946 VR512:$src)>;
1947def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1948 GR8:$mask),
1949 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1950 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1951
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1952defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1953 "16", "8", "4", SSEPackedInt, HasAVX512>,
1954 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1955 "512", "256", "", "i", "32", "16", "8", "4",
1956 SSEPackedInt, HasAVX512>,
1957 PD, EVEX_CD8<32, CD8VF>;
1958
1959defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1960 "8", "4", "2", SSEPackedInt, HasAVX512>,
1961 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1962 "512", "256", "", "i", "64", "8", "4", "2",
1963 SSEPackedInt, HasAVX512>,
1964 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1965
1966defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1967 "64", "32", "16", SSEPackedInt, HasBWI>,
1968 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1969 "i", "8", "64", "32", "16", SSEPackedInt,
1970 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1971
1972defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1973 "32", "16", "8", SSEPackedInt, HasBWI>,
1974 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1975 "i", "16", "32", "16", "8", SSEPackedInt,
1976 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1977
1978defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1979 "16", "8", "4", SSEPackedInt, HasAVX512>,
1980 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1981 "i", "32", "16", "8", "4", SSEPackedInt,
1982 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1983
1984defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1985 "8", "4", "2", SSEPackedInt, HasAVX512>,
1986 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1987 "i", "64", "8", "4", "2", SSEPackedInt,
1988 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1989
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1990def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1991 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1992 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1993
1994def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1995 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1996 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1997
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]1998def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1999 GR16:$mask),
2000 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2001 VR512:$src)>;
2002def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2003 GR8:$mask),
2004 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2005 VR512:$src)>;
2006
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2007let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2008def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2009 (bc_v8i64 (v16i32 immAllZerosV)))),
2010 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2011
2012def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2013 (v8i64 VR512:$src))),
2014 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2015 VK8), VR512:$src)>;
2016
2017def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2018 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2019 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2020
2021def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2022 (v16i32 VR512:$src))),
2023 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2024}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2025
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2026// Move Int Doubleword to Packed Double Int
2027//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2028def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2029 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2030 [(set VR128X:$dst,
2031 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2032 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2033def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2034 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2035 [(set VR128X:$dst,
2036 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2037 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2038def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2039 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2040 [(set VR128X:$dst,
2041 (v2i64 (scalar_to_vector GR64:$src)))],
2042 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2043let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2044def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2045 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2046 [(set FR64:$dst, (bitconvert GR64:$src))],
2047 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2048def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2049 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2050 [(set GR64:$dst, (bitconvert FR64:$src))],
2051 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2052}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2053def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2054 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2055 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2056 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2057 EVEX_CD8<64, CD8VT1>;
2058
2059// Move Int Doubleword to Single Scalar
2060//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2061let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2062def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2063 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2064 [(set FR32X:$dst, (bitconvert GR32:$src))],
2065 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2066
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2067def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2068 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2069 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2070 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2071}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2072
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2073// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2074//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2075def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2076 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2077 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2078 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2079 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2080def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2081 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2082 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2083 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2084 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2085 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2086
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2087// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2088//
2089def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2090 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2091 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2092 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2093 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2094 Requires<[HasAVX512, In64BitMode]>;
2095
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2096def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2097 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2098 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2099 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2100 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2101 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2102 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2103
2104// Move Scalar Single to Double Int
2105//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2106let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2107def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2108 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2109 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2110 [(set GR32:$dst, (bitconvert FR32X:$src))],
2111 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2112def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2113 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2114 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2115 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2116 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2117}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2118
2119// Move Quadword Int to Packed Quadword Int
2120//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2121def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2122 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2123 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2124 [(set VR128X:$dst,
2125 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2126 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2127
2128//===----------------------------------------------------------------------===//
2129// AVX-512 MOVSS, MOVSD
2130//===----------------------------------------------------------------------===//
2131
2132multiclass avx512_move_scalar <string asm, RegisterClass RC,
2133 SDNode OpNode, ValueType vt,
2134 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2135 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2136 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2137 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2138 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2139 (scalar_to_vector RC:$src2))))],
2140 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2141 let Constraints = "$src1 = $dst" in
2142 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2143 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2144 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2145 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2146 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2147 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2148 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2149 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2150 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2151 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2152 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2153 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2154 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2155 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2156 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2157 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2158 [], IIC_SSE_MOV_S_MR>,
2159 EVEX, VEX_LIG, EVEX_K;
2160 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2161 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2162}
2163
2164let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2165defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2166 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2167
2168let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2169defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2170 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2171
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2172def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2173 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2174 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2175
2176def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2177 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2178 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2179
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2180def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2181 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2182 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2183
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2184// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2185let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2186 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2187 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2188 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2189 IIC_SSE_MOV_S_RR>,
2190 XS, EVEX_4V, VEX_LIG;
2191 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2192 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2193 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2194 IIC_SSE_MOV_S_RR>,
2195 XD, EVEX_4V, VEX_LIG, VEX_W;
2196}
2197
2198let Predicates = [HasAVX512] in {
2199 let AddedComplexity = 15 in {
2200 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2201 // MOVS{S,D} to the lower bits.
2202 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2203 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2204 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2205 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2206 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2207 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2208 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2209 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2210
2211 // Move low f32 and clear high bits.
2212 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2213 (SUBREG_TO_REG (i32 0),
2214 (VMOVSSZrr (v4f32 (V_SET0)),
2215 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2216 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2217 (SUBREG_TO_REG (i32 0),
2218 (VMOVSSZrr (v4i32 (V_SET0)),
2219 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2220 }
2221
2222 let AddedComplexity = 20 in {
2223 // MOVSSrm zeros the high parts of the register; represent this
2224 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2225 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2226 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2227 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2228 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2229 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2230 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2231
2232 // MOVSDrm zeros the high parts of the register; represent this
2233 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2234 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2235 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2236 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2237 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2238 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2239 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2240 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2241 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2242 def : Pat<(v2f64 (X86vzload addr:$src)),
2243 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2244
2245 // Represent the same patterns above but in the form they appear for
2246 // 256-bit types
2247 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2248 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2249 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2250 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2251 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2252 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2253 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2254 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2255 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2256 }
2257 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2258 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2259 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2260 FR32X:$src)), sub_xmm)>;
2261 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2262 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2263 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2264 FR64X:$src)), sub_xmm)>;
2265 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2266 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2267 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2268
2269 // Move low f64 and clear high bits.
2270 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2271 (SUBREG_TO_REG (i32 0),
2272 (VMOVSDZrr (v2f64 (V_SET0)),
2273 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2274
2275 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2276 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2277 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2278
2279 // Extract and store.
2280 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2281 addr:$dst),
2282 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2283 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2284 addr:$dst),
2285 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2286
2287 // Shuffle with VMOVSS
2288 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2289 (VMOVSSZrr (v4i32 VR128X:$src1),
2290 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2291 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2292 (VMOVSSZrr (v4f32 VR128X:$src1),
2293 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2294
2295 // 256-bit variants
2296 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2297 (SUBREG_TO_REG (i32 0),
2298 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2299 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2300 sub_xmm)>;
2301 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2302 (SUBREG_TO_REG (i32 0),
2303 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2304 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2305 sub_xmm)>;
2306
2307 // Shuffle with VMOVSD
2308 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2309 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2310 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2311 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2312 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2313 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2314 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2315 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2316
2317 // 256-bit variants
2318 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2319 (SUBREG_TO_REG (i32 0),
2320 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2321 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2322 sub_xmm)>;
2323 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2324 (SUBREG_TO_REG (i32 0),
2325 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2326 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2327 sub_xmm)>;
2328
2329 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2330 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2331 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2332 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2333 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2334 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2335 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2336 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2337}
2338
2339let AddedComplexity = 15 in
2340def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2341 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2342 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2343 [(set VR128X:$dst, (v2i64 (X86vzmovl
2344 (v2i64 VR128X:$src))))],
2345 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2346
2347let AddedComplexity = 20 in
2348def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2349 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2350 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2351 [(set VR128X:$dst, (v2i64 (X86vzmovl
2352 (loadv2i64 addr:$src))))],
2353 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2354 EVEX_CD8<8, CD8VT8>;
2355
2356let Predicates = [HasAVX512] in {
2357 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2358 let AddedComplexity = 20 in {
2359 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2360 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2361 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2362 (VMOV64toPQIZrr GR64:$src)>;
2363 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2364 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2365
2366 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2367 (VMOVDI2PDIZrm addr:$src)>;
2368 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2369 (VMOVDI2PDIZrm addr:$src)>;
2370 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2371 (VMOVZPQILo2PQIZrm addr:$src)>;
2372 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2373 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2374 def : Pat<(v2i64 (X86vzload addr:$src)),
2375 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2376 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2377
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2378 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2379 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2380 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2381 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2382 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2383 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2384 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2385}
2386
2387def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2388 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2389
2390def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2391 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2392
2393def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2394 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2395
2396def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2397 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2398
2399//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2400// AVX-512 - Non-temporals
2401//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2402let SchedRW = [WriteLoad] in {
2403 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2404 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2405 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2406 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2407 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2408
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2409 let Predicates = [HasAVX512, HasVLX] in {
2410 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2411 (ins i256mem:$src),
2412 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2413 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2414 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2415
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2416 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2417 (ins i128mem:$src),
2418 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2419 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2420 EVEX_CD8<64, CD8VF>;
2421 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2422}
2423
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2424multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2425 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2426 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2427 let SchedRW = [WriteStore], mayStore = 1,
2428 AddedComplexity = 400 in
2429 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2430 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2431 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2432}
2433
2434multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2435 string elty, string elsz, string vsz512,
2436 string vsz256, string vsz128, Domain d,
2437 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2438 let Predicates = [prd] in
2439 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2440 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2441 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2442 EVEX_V512;
2443
2444 let Predicates = [prd, HasVLX] in {
2445 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2446 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2447 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2448 EVEX_V256;
2449
2450 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2451 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2452 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2453 EVEX_V128;
2454 }
2455}
2456
2457defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2458 "i", "64", "8", "4", "2", SSEPackedInt,
2459 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2460
2461defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2462 "f", "64", "8", "4", "2", SSEPackedDouble,
2463 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2464
2465defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2466 "f", "32", "16", "8", "4", SSEPackedSingle,
2467 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2468
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2469//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2470// AVX-512 - Integer arithmetic
2471//
2472multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2473 X86VectorVTInfo _, OpndItins itins,
2474 bit IsCommutable = 0> {
2475 defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
2476 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2477 "$src2, $src1", "$src1, $src2",
2478 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2479 itins.rr, IsCommutable>,
2480 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2481
2482 let mayLoad = 1 in {
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2483 defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2484 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2485 "$src2, $src1", "$src1, $src2",
2486 (_.VT (OpNode _.RC:$src1,
2487 (bitconvert (_.LdFrag addr:$src2)))),
2488 itins.rm>,
2489 AVX512BIBase, EVEX_4V;
2490 defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2491 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2492 "${src2}"##_.BroadcastStr##", $src1",
2493 "$src1, ${src2}"##_.BroadcastStr,
2494 (_.VT (OpNode _.RC:$src1,
2495 (X86VBroadcast
2496 (_.ScalarLdFrag addr:$src2)))),
2497 itins.rm>,
2498 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2499 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2500}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2501
2502multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2503 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2504 PatFrag memop_frag, X86MemOperand x86memop,
2505 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2506 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2507 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2508 {
2509 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2510 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2511 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2512 []>, EVEX_4V;
2513 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2514 (ins KRC:$mask, RC:$src1, RC:$src2),
2515 !strconcat(OpcodeStr,
2516 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2517 [], itins.rr>, EVEX_4V, EVEX_K;
2518 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2519 (ins KRC:$mask, RC:$src1, RC:$src2),
2520 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2521 "|$dst {${mask}} {z}, $src1, $src2}"),
2522 [], itins.rr>, EVEX_4V, EVEX_KZ;
2523 }
2524 let mayLoad = 1 in {
2525 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins RC:$src1, x86memop:$src2),
2527 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2528 []>, EVEX_4V;
2529 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2530 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2531 !strconcat(OpcodeStr,
2532 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2533 [], itins.rm>, EVEX_4V, EVEX_K;
2534 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2535 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2536 !strconcat(OpcodeStr,
2537 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2538 [], itins.rm>, EVEX_4V, EVEX_KZ;
2539 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2540 (ins RC:$src1, x86scalar_mop:$src2),
2541 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2542 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2543 [], itins.rm>, EVEX_4V, EVEX_B;
2544 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2545 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2546 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2547 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2548 BrdcstStr, "}"),
2549 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2550 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2551 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2552 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2553 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2554 BrdcstStr, "}"),
2555 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2556 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2557}
2558
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2559defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2560 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2561
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2562defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2563 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2564
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2565defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2566 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2567
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2568defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2569 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2570
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2571defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2572 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2573
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2574defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2575 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2576 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2577 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2578
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2579defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2580 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2581 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2582
2583def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2584 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2585
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2586def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2587 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2588 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2589def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2590 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2591 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2592
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2593defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2594 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2595 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2596defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2597 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2598 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2599
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2600defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2601 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2602 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2603defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2604 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2605 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2606
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2607defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2608 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2609 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2610defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2611 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2612 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2613
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2614defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2615 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2616 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2617defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2618 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2619 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2620
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2621def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2622 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2623 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2624def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2625 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2626 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2627def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2628 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2629 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2630def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2631 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2632 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2633def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2634 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2635 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2636def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2637 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2638 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2639def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2640 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2641 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2642def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2643 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2644 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2645//===----------------------------------------------------------------------===//
2646// AVX-512 - Unpack Instructions
2647//===----------------------------------------------------------------------===//
2648
2649multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2650 PatFrag mem_frag, RegisterClass RC,
2651 X86MemOperand x86memop, string asm,
2652 Domain d> {
2653 def rr : AVX512PI<opc, MRMSrcReg,
2654 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2655 asm, [(set RC:$dst,
2656 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2657 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2658 def rm : AVX512PI<opc, MRMSrcMem,
2659 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2660 asm, [(set RC:$dst,
2661 (vt (OpNode RC:$src1,
2662 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2663 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2664}
2665
2666defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2667 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2668 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2669defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2670 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2671 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2672defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2673 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2674 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2675defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2676 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2677 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2678
2679multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2680 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2681 X86MemOperand x86memop> {
2682 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2683 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2684 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2685 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2686 IIC_SSE_UNPCK>, EVEX_4V;
2687 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2688 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2689 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2690 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2691 (bitconvert (memop_frag addr:$src2)))))],
2692 IIC_SSE_UNPCK>, EVEX_4V;
2693}
2694defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2695 VR512, memopv16i32, i512mem>, EVEX_V512,
2696 EVEX_CD8<32, CD8VF>;
2697defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2698 VR512, memopv8i64, i512mem>, EVEX_V512,
2699 VEX_W, EVEX_CD8<64, CD8VF>;
2700defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2701 VR512, memopv16i32, i512mem>, EVEX_V512,
2702 EVEX_CD8<32, CD8VF>;
2703defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2704 VR512, memopv8i64, i512mem>, EVEX_V512,
2705 VEX_W, EVEX_CD8<64, CD8VF>;
2706//===----------------------------------------------------------------------===//
2707// AVX-512 - PSHUFD
2708//
2709
2710multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2711 SDNode OpNode, PatFrag mem_frag,
2712 X86MemOperand x86memop, ValueType OpVT> {
2713 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2714 (ins RC:$src1, i8imm:$src2),
2715 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2716 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2717 [(set RC:$dst,
2718 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2719 EVEX;
2720 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2721 (ins x86memop:$src1, i8imm:$src2),
2722 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2724 [(set RC:$dst,
2725 (OpVT (OpNode (mem_frag addr:$src1),
2726 (i8 imm:$src2))))]>, EVEX;
2727}
2728
2729defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2730 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2731
2732let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2733defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2734 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2735 EVEX_CD8<32, CD8VF>;
2736let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2737defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2738 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2739 VEX_W, EVEX_CD8<32, CD8VF>;
2740
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2741def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2742 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2743def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2744 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2745
2746//===----------------------------------------------------------------------===//
2747// AVX-512 Logical Instructions
2748//===----------------------------------------------------------------------===//
2749
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2750defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2751 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2752defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2753 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2754defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2755 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2756defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2757 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2758defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2759 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2760defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2761 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2762defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2763 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2764defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2765 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2766
2767//===----------------------------------------------------------------------===//
2768// AVX-512 FP arithmetic
2769//===----------------------------------------------------------------------===//
2770
2771multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2772 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2773 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2774 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2775 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2776 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2777 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2778 EVEX_CD8<64, CD8VT1>;
2779}
2780
2781let isCommutable = 1 in {
2782defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2783defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2784defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2785defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2786}
2787let isCommutable = 0 in {
2788defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2789defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2790}
2791
2792multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2793 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2794 RegisterClass RC, ValueType vt,
2795 X86MemOperand x86memop, PatFrag mem_frag,
2796 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2797 string BrdcstStr,
2798 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2799 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2800 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2801 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2802 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2803 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2804
2805 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2806 !strconcat(OpcodeStr,
2807 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2808 [], itins.rr, d>, EVEX_4V, EVEX_K;
2809
2810 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2811 !strconcat(OpcodeStr,
2812 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2813 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2814 }
2815
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2816 let mayLoad = 1 in {
2817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2818 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2819 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2820 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2821
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2822 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2823 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2824 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2825 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2826 [(set RC:$dst, (OpNode RC:$src1,
2827 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2828 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2829
2830 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2831 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2832 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2833 [], itins.rm, d>, EVEX_4V, EVEX_K;
2834
2835 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2836 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2837 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2838 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2839
2840 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2841 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2842 " \t{${src2}", BrdcstStr,
2843 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2844 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2845
2846 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2847 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2848 " \t{${src2}", BrdcstStr,
2849 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2850 BrdcstStr, "}"),
2851 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2852 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2853}
2854
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2855defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2856 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2857 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2858
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2859defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2860 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2861 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2862 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2863
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2864defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2865 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2866 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2867defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2868 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2869 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2870 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2871
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2872defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2873 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2874 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2875 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2876defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2877 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2878 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2879 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2881defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2882 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2883 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2884 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2885defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2886 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2887 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2888 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2889
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2890defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2891 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2892 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2893defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2894 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2895 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2896
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2897defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2898 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2899 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2900 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2901defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2902 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2903 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2904 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2905
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]2906def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2907 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2908 (i16 -1), FROUND_CURRENT)),
2909 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2910
2911def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2912 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2913 (i8 -1), FROUND_CURRENT)),
2914 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2915
2916def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2917 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2918 (i16 -1), FROUND_CURRENT)),
2919 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2920
2921def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2922 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2923 (i8 -1), FROUND_CURRENT)),
2924 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2925//===----------------------------------------------------------------------===//
2926// AVX-512 VPTESTM instructions
2927//===----------------------------------------------------------------------===//
2928
2929multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2930 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2931 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2932 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2933 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2934 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2935 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2936 SSEPackedInt>, EVEX_4V;
2937 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2938 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2939 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2940 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2941 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2942}
2943
2944defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2945 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2946 EVEX_CD8<32, CD8VF>;
2947defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2948 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2949 EVEX_CD8<64, CD8VF>;
2950
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2951let Predicates = [HasCDI] in {
2952defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2953 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2954 EVEX_CD8<32, CD8VF>;
2955defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2956 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2957 EVEX_CD8<64, CD8VF>;
2958}
2959
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]2960def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2961 (v16i32 VR512:$src2), (i16 -1))),
2962 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2963
2964def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2965 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2966 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2967//===----------------------------------------------------------------------===//
2968// AVX-512 Shift instructions
2969//===----------------------------------------------------------------------===//
2970multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2971 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2972 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2973 RegisterClass KRC> {
2974 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2975 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2976 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2977 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2978 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2979 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2980 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2981 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2982 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2983 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2984 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2985 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2986 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2987 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2988 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2989 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2990 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2991 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2992 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2993 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2994}
2995
2996multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2997 RegisterClass RC, ValueType vt, ValueType SrcVT,
2998 PatFrag bc_frag, RegisterClass KRC> {
2999 // src2 is always 128-bit
3000 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3001 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3002 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3003 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3004 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3005 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3006 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3007 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3008 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3009 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3010 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3011 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3012 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3013 [(set RC:$dst, (vt (OpNode RC:$src1,
3014 (bc_frag (memopv2i64 addr:$src2)))))],
3015 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3016 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3017 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3018 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3019 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3020 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3021}
3022
3023defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3024 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3025 EVEX_V512, EVEX_CD8<32, CD8VF>;
3026defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3027 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3028 EVEX_CD8<32, CD8VQ>;
3029
3030defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3031 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3032 EVEX_CD8<64, CD8VF>, VEX_W;
3033defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3034 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3035 EVEX_CD8<64, CD8VQ>, VEX_W;
3036
3037defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3038 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3039 EVEX_CD8<32, CD8VF>;
3040defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3041 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3042 EVEX_CD8<32, CD8VQ>;
3043
3044defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3045 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3046 EVEX_CD8<64, CD8VF>, VEX_W;
3047defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3048 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3049 EVEX_CD8<64, CD8VQ>, VEX_W;
3050
3051defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3052 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3053 EVEX_V512, EVEX_CD8<32, CD8VF>;
3054defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3055 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3056 EVEX_CD8<32, CD8VQ>;
3057
3058defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3059 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3060 EVEX_CD8<64, CD8VF>, VEX_W;
3061defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3062 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3063 EVEX_CD8<64, CD8VQ>, VEX_W;
3064
3065//===-------------------------------------------------------------------===//
3066// Variable Bit Shifts
3067//===-------------------------------------------------------------------===//
3068multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3069 RegisterClass RC, ValueType vt,
3070 X86MemOperand x86memop, PatFrag mem_frag> {
3071 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3072 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3073 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3074 [(set RC:$dst,
3075 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3076 EVEX_4V;
3077 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3078 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3079 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3080 [(set RC:$dst,
3081 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3082 EVEX_4V;
3083}
3084
3085defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3086 i512mem, memopv16i32>, EVEX_V512,
3087 EVEX_CD8<32, CD8VF>;
3088defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3089 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3090 EVEX_CD8<64, CD8VF>;
3091defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3092 i512mem, memopv16i32>, EVEX_V512,
3093 EVEX_CD8<32, CD8VF>;
3094defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3095 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3096 EVEX_CD8<64, CD8VF>;
3097defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3098 i512mem, memopv16i32>, EVEX_V512,
3099 EVEX_CD8<32, CD8VF>;
3100defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3101 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3102 EVEX_CD8<64, CD8VF>;
3103
3104//===----------------------------------------------------------------------===//
3105// AVX-512 - MOVDDUP
3106//===----------------------------------------------------------------------===//
3107
3108multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3109 X86MemOperand x86memop, PatFrag memop_frag> {
3110def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3111 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3112 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3113def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3114 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3115 [(set RC:$dst,
3116 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3117}
3118
3119defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3120 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3121def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3122 (VMOVDDUPZrm addr:$src)>;
3123
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3124//===---------------------------------------------------------------------===//
3125// Replicate Single FP - MOVSHDUP and MOVSLDUP
3126//===---------------------------------------------------------------------===//
3127multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3128 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3129 X86MemOperand x86memop> {
3130 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3131 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3132 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3133 let mayLoad = 1 in
3134 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3135 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3136 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3137}
3138
3139defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3140 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3141 EVEX_CD8<32, CD8VF>;
3142defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3143 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3144 EVEX_CD8<32, CD8VF>;
3145
3146def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3147def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3148 (VMOVSHDUPZrm addr:$src)>;
3149def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3150def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3151 (VMOVSLDUPZrm addr:$src)>;
3152
3153//===----------------------------------------------------------------------===//
3154// Move Low to High and High to Low packed FP Instructions
3155//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3156def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3157 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3158 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3159 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3160 IIC_SSE_MOV_LH>, EVEX_4V;
3161def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3162 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3163 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3164 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3165 IIC_SSE_MOV_LH>, EVEX_4V;
3166
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3167let Predicates = [HasAVX512] in {
3168 // MOVLHPS patterns
3169 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3170 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3171 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3172 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3173
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3174 // MOVHLPS patterns
3175 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3176 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3177}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3178
3179//===----------------------------------------------------------------------===//
3180// FMA - Fused Multiply Operations
3181//
3182let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3183multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3184 X86VectorVTInfo _> {
3185 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3186 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3187 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3188 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3189 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3190
3191 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3192 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3193 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3194 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3195 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3196 (_.MemOpFrag addr:$src3))))]>;
3197 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3198 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3199 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3200 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3201 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3202 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3203}
3204} // Constraints = "$src1 = $dst"
3205
3206let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3207 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3208 v16f32_info>,
3209 EVEX_V512, EVEX_CD8<32, CD8VF>;
3210 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3211 v16f32_info>,
3212 EVEX_V512, EVEX_CD8<32, CD8VF>;
3213 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3214 v16f32_info>,
3215 EVEX_V512, EVEX_CD8<32, CD8VF>;
3216 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3217 v16f32_info>,
3218 EVEX_V512, EVEX_CD8<32, CD8VF>;
3219 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3220 v16f32_info>,
3221 EVEX_V512, EVEX_CD8<32, CD8VF>;
3222 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3223 v16f32_info>,
3224 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3225}
3226let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3227 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3228 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3229 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3230 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3231 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3232 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3233 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3234 v8f64_info>,
3235 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3236 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3237 v8f64_info>,
3238 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3239 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3240 v8f64_info>,
3241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3242 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3243 v8f64_info>,
3244 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3245}
3246
3247let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3248multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3249 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3250 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3251 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3252 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3253 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3254 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3255 _.RC:$src3)))]>;
3256 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3257 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3258 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3259 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3260 [(set _.RC:$dst,
3261 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3262 (_.ScalarLdFrag addr:$src2))),
3263 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3264}
3265} // Constraints = "$src1 = $dst"
3266
3267
3268let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3269 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3270 v16f32_info>,
3271 EVEX_V512, EVEX_CD8<32, CD8VF>;
3272 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3273 v16f32_info>,
3274 EVEX_V512, EVEX_CD8<32, CD8VF>;
3275 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3276 v16f32_info>,
3277 EVEX_V512, EVEX_CD8<32, CD8VF>;
3278 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3279 v16f32_info>,
3280 EVEX_V512, EVEX_CD8<32, CD8VF>;
3281 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3282 v16f32_info>,
3283 EVEX_V512, EVEX_CD8<32, CD8VF>;
3284 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3285 v16f32_info>,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3287}
3288let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3289 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3290 v8f64_info>,
3291 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3292 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3293 v8f64_info>,
3294 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3295 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3296 v8f64_info>,
3297 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3298 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3299 v8f64_info>,
3300 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3301 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3302 v8f64_info>,
3303 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3304 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3305 v8f64_info>,
3306 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3307}
3308
3309// Scalar FMA
3310let Constraints = "$src1 = $dst" in {
3311multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3312 RegisterClass RC, ValueType OpVT,
3313 X86MemOperand x86memop, Operand memop,
3314 PatFrag mem_frag> {
3315 let isCommutable = 1 in
3316 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3317 (ins RC:$src1, RC:$src2, RC:$src3),
3318 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3319 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3320 [(set RC:$dst,
3321 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3322 let mayLoad = 1 in
3323 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3324 (ins RC:$src1, RC:$src2, f128mem:$src3),
3325 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3326 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3327 [(set RC:$dst,
3328 (OpVT (OpNode RC:$src2, RC:$src1,
3329 (mem_frag addr:$src3))))]>;
3330}
3331
3332} // Constraints = "$src1 = $dst"
3333
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3334defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3335 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3336defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3337 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3338defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3339 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3340defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3341 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3342defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3343 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3344defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3345 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3346defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3347 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3348defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3349 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3350
3351//===----------------------------------------------------------------------===//
3352// AVX-512 Scalar convert from sign integer to float/double
3353//===----------------------------------------------------------------------===//
3354
3355multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3356 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3357let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3358 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3359 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3360 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3361 let mayLoad = 1 in
3362 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3363 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3364 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3365 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3366} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3367}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3368let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3369defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3370 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3371defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3372 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3373defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3374 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3375defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3376 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3377
3378def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3379 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3380def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3381 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3382def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3383 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3384def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3385 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3386
3387def : Pat<(f32 (sint_to_fp GR32:$src)),
3388 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3389def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3390 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3391def : Pat<(f64 (sint_to_fp GR32:$src)),
3392 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3393def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3394 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3395
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3396defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3397 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3398defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3399 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3400defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3401 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3402defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3403 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3404
3405def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3406 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3407def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3408 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3409def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3410 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3411def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3412 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3413
3414def : Pat<(f32 (uint_to_fp GR32:$src)),
3415 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3416def : Pat<(f32 (uint_to_fp GR64:$src)),
3417 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3418def : Pat<(f64 (uint_to_fp GR32:$src)),
3419 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3420def : Pat<(f64 (uint_to_fp GR64:$src)),
3421 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3422}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3423
3424//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3425// AVX-512 Scalar convert from float/double to integer
3426//===----------------------------------------------------------------------===//
3427multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3428 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3429 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3430let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3431 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3432 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3433 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3434 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3435 let mayLoad = 1 in
3436 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3437 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3438 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3439} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3440}
3441let Predicates = [HasAVX512] in {
3442// Convert float/double to signed/unsigned int 32/64
3443defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3444 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3445 XS, EVEX_CD8<32, CD8VT1>;
3446defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3447 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3448 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3449defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3450 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3451 XS, EVEX_CD8<32, CD8VT1>;
3452defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3453 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3454 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3455 EVEX_CD8<32, CD8VT1>;
3456defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3457 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3458 XD, EVEX_CD8<64, CD8VT1>;
3459defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3460 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3461 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3462defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3463 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3464 XD, EVEX_CD8<64, CD8VT1>;
3465defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3466 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3467 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3468 EVEX_CD8<64, CD8VT1>;
3469
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3470let isCodeGenOnly = 1 in {
3471 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3472 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3473 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3474 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3475 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3476 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3477 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3478 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3479 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3480 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3481 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3482 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3483
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3484 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3485 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3486 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3487 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3488 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3489 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3490 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3491 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3492 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3493 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3494 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3495 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3496} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3497
3498// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3499let isCodeGenOnly = 1 in {
3500 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3501 ssmem, sse_load_f32, "cvttss2si">,
3502 XS, EVEX_CD8<32, CD8VT1>;
3503 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3504 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3505 "cvttss2si">, XS, VEX_W,
3506 EVEX_CD8<32, CD8VT1>;
3507 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3508 sdmem, sse_load_f64, "cvttsd2si">, XD,
3509 EVEX_CD8<64, CD8VT1>;
3510 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3511 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3512 "cvttsd2si">, XD, VEX_W,
3513 EVEX_CD8<64, CD8VT1>;
3514 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3515 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3516 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3517 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3518 int_x86_avx512_cvttss2usi64, ssmem,
3519 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3520 EVEX_CD8<32, CD8VT1>;
3521 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3522 int_x86_avx512_cvttsd2usi,
3523 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3524 EVEX_CD8<64, CD8VT1>;
3525 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3526 int_x86_avx512_cvttsd2usi64, sdmem,
3527 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3528 EVEX_CD8<64, CD8VT1>;
3529} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3530
3531multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3532 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3533 string asm> {
3534 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3535 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3536 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3537 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3538 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3539 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3540}
3541
3542defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3543 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3544 EVEX_CD8<32, CD8VT1>;
3545defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3546 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3547 EVEX_CD8<32, CD8VT1>;
3548defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3549 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3550 EVEX_CD8<32, CD8VT1>;
3551defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3552 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3553 EVEX_CD8<32, CD8VT1>;
3554defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3555 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3556 EVEX_CD8<64, CD8VT1>;
3557defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3558 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3559 EVEX_CD8<64, CD8VT1>;
3560defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3562 EVEX_CD8<64, CD8VT1>;
3563defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3564 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3565 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3566} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3567//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3568// AVX-512 Convert form float to double and back
3569//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3570let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3571def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3572 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3573 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3574 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3575let mayLoad = 1 in
3576def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3577 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3578 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3579 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3580 EVEX_CD8<32, CD8VT1>;
3581
3582// Convert scalar double to scalar single
3583def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3584 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3585 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3586 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3587let mayLoad = 1 in
3588def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3589 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3590 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3591 []>, EVEX_4V, VEX_LIG, VEX_W,
3592 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3593}
3594
3595def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3596 Requires<[HasAVX512]>;
3597def : Pat<(fextend (loadf32 addr:$src)),
3598 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3599
3600def : Pat<(extloadf32 addr:$src),
3601 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3602 Requires<[HasAVX512, OptForSize]>;
3603
3604def : Pat<(extloadf32 addr:$src),
3605 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3606 Requires<[HasAVX512, OptForSpeed]>;
3607
3608def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3609 Requires<[HasAVX512]>;
3610
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3611multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3612 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3613 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3614 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3615let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3616 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3617 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3618 [(set DstRC:$dst,
3619 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3620 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3621 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3622 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3623 let mayLoad = 1 in
3624 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3625 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3626 [(set DstRC:$dst,
3627 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3628} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3629}
3630
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3631multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3632 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3633 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3634 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3635let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3636 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3637 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3638 [(set DstRC:$dst,
3639 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3640 let mayLoad = 1 in
3641 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3642 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3643 [(set DstRC:$dst,
3644 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3645} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3646}
3647
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3648defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3649 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3650 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3651 EVEX_CD8<64, CD8VF>;
3652
3653defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3654 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3655 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3656 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3657def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3658 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3659
3660def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3661 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3662 (VCVTPD2PSZrr VR512:$src)>;
3663
3664def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3665 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3666 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3667
3668//===----------------------------------------------------------------------===//
3669// AVX-512 Vector convert from sign integer to float/double
3670//===----------------------------------------------------------------------===//
3671
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3672defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3673 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3674 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3675 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3676
3677defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3678 memopv4i64, i256mem, v8f64, v8i32,
3679 SSEPackedDouble>, EVEX_V512, XS,
3680 EVEX_CD8<32, CD8VH>;
3681
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3682defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3683 memopv16f32, f512mem, v16i32, v16f32,
3684 SSEPackedSingle>, EVEX_V512, XS,
3685 EVEX_CD8<32, CD8VF>;
3686
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3687defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3688 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3689 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3690 EVEX_CD8<64, CD8VF>;
3691
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3692defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3693 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3694 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3695 EVEX_CD8<32, CD8VF>;
3696
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3697// cvttps2udq (src, 0, mask-all-ones, sae-current)
3698def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3699 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3700 (VCVTTPS2UDQZrr VR512:$src)>;
3701
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3702defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3703 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3704 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3705 EVEX_CD8<64, CD8VF>;
3706
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3707// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3708def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3709 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3710 (VCVTTPD2UDQZrr VR512:$src)>;
3711
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3712defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3713 memopv4i64, f256mem, v8f64, v8i32,
3714 SSEPackedDouble>, EVEX_V512, XS,
3715 EVEX_CD8<32, CD8VH>;
3716
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3717defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3718 memopv16i32, f512mem, v16f32, v16i32,
3719 SSEPackedSingle>, EVEX_V512, XD,
3720 EVEX_CD8<32, CD8VF>;
3721
3722def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3723 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3724 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3725
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3726def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3727 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3728 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3729
3730def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3731 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3732 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3733
3734def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3735 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3736 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3737
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3738def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3739 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3740 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3741
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3742def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3743 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3744 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3745def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3746 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3747 (VCVTDQ2PDZrr VR256X:$src)>;
3748def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3749 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3750 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3751def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3752 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3753 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3754
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3755multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3756 RegisterClass DstRC, PatFrag mem_frag,
3757 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3758let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3759 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3760 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3761 [], d>, EVEX;
3762 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3763 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3764 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3765 let mayLoad = 1 in
3766 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3767 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3768 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3769} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3770}
3771
3772defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3773 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3774 EVEX_V512, EVEX_CD8<32, CD8VF>;
3775defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3776 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3777 EVEX_V512, EVEX_CD8<64, CD8VF>;
3778
3779def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3780 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3781 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3782
3783def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3784 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3785 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3786
3787defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3788 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3789 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3790defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3791 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3792 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3793
3794def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3795 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3796 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3797
3798def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3799 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3800 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3801
3802let Predicates = [HasAVX512] in {
3803 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3804 (VCVTPD2PSZrm addr:$src)>;
3805 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3806 (VCVTPS2PDZrm addr:$src)>;
3807}
3808
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3809//===----------------------------------------------------------------------===//
3810// Half precision conversion instructions
3811//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3812multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3813 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3814 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3815 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3816 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3817 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3818 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3819 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3820}
3821
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3822multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3823 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3824 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3825 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3826 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3827 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3828 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3829 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3830 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3831 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3832}
3833
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3834defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3835 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3836defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3837 EVEX_CD8<32, CD8VH>;
3838
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3839def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3840 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3841 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3842
3843def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3844 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3845 (VCVTPH2PSZrr VR256X:$src)>;
3846
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3847let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3848 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3849 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3850 EVEX_CD8<32, CD8VT1>;
3851 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3852 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3853 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3854 let Pattern = []<dag> in {
3855 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3856 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3857 EVEX_CD8<32, CD8VT1>;
3858 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3859 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3860 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3861 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3862 let isCodeGenOnly = 1 in {
3863 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3864 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3865 EVEX_CD8<32, CD8VT1>;
3866 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3867 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3868 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3869
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3870 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3871 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3872 EVEX_CD8<32, CD8VT1>;
3873 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3874 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3875 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3876 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3877}
3878
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3879/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3880multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3881 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3882 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3883 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3884 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3885 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3886 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3887 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3888 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3889 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3890 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3891 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3892 }
3893}
3894}
3895
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3896defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3897 EVEX_CD8<32, CD8VT1>;
3898defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3899 VEX_W, EVEX_CD8<64, CD8VT1>;
3900defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3901 EVEX_CD8<32, CD8VT1>;
3902defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3903 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3904
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3905def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3906 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3907 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3908 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3909
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3910def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3911 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3912 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3913 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3914
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3915def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3916 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3917 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3918 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3919
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3920def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3921 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3922 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3923 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3924
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3925/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3926multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3927 RegisterClass RC, X86MemOperand x86memop,
3928 PatFrag mem_frag, ValueType OpVt> {
3929 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3930 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3931 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3932 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3933 EVEX;
3934 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3935 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3936 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3937 EVEX;
3938}
3939defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3940 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3941defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3942 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3943defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3944 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3945defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3946 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3947
3948def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3949 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3950 (VRSQRT14PSZr VR512:$src)>;
3951def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3952 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3953 (VRSQRT14PDZr VR512:$src)>;
3954
3955def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3956 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3957 (VRCP14PSZr VR512:$src)>;
3958def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3959 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3960 (VRCP14PDZr VR512:$src)>;
3961
3962/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3963multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3964 X86MemOperand x86memop> {
3965 let hasSideEffects = 0, Predicates = [HasERI] in {
3966 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3967 (ins RC:$src1, RC:$src2),
3968 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3969 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3970 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3971 (ins RC:$src1, RC:$src2),
3972 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3973 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3974 []>, EVEX_4V, EVEX_B;
3975 let mayLoad = 1 in {
3976 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3977 (ins RC:$src1, x86memop:$src2),
3978 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3979 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3980 }
3981}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3982}
3983
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3984defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3985 EVEX_CD8<32, CD8VT1>;
3986defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3987 VEX_W, EVEX_CD8<64, CD8VT1>;
3988defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3989 EVEX_CD8<32, CD8VT1>;
3990defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3991 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3992
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3993def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3994 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3995 FROUND_NO_EXC)),
3996 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3997 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3998
3999def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4000 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4001 FROUND_NO_EXC)),
4002 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4003 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4004
4005def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4006 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4007 FROUND_NO_EXC)),
4008 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4009 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4010
4011def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4012 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4013 FROUND_NO_EXC)),
4014 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4015 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4016
4017/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4018multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4019 RegisterClass RC, X86MemOperand x86memop> {
4020 let hasSideEffects = 0, Predicates = [HasERI] in {
4021 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4022 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4023 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4024 []>, EVEX;
4025 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4026 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4027 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4028 []>, EVEX, EVEX_B;
4029 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4030 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4031 []>, EVEX;
4032 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4033}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4034defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4035 EVEX_V512, EVEX_CD8<32, CD8VF>;
4036defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4037 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4038defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4039 EVEX_V512, EVEX_CD8<32, CD8VF>;
4040defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4041 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4042
4043def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4044 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4045 (VRSQRT28PSZrb VR512:$src)>;
4046def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4047 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4048 (VRSQRT28PDZrb VR512:$src)>;
4049
4050def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4051 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4052 (VRCP28PSZrb VR512:$src)>;
4053def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4054 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4055 (VRCP28PDZrb VR512:$src)>;
4056
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4057multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4058 OpndItins itins_s, OpndItins itins_d> {
4059 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4060 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4061 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4062 EVEX, EVEX_V512;
4063
4064 let mayLoad = 1 in
4065 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4066 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4067 [(set VR512:$dst,
4068 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4069 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4070
4071 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4072 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4073 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4074 EVEX, EVEX_V512;
4075
4076 let mayLoad = 1 in
4077 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4078 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4079 [(set VR512:$dst, (OpNode
4080 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4081 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4082
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4083}
4084
4085multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4086 Intrinsic F32Int, Intrinsic F64Int,
4087 OpndItins itins_s, OpndItins itins_d> {
4088 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4089 (ins FR32X:$src1, FR32X:$src2),
4090 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4091 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4092 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4093 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4094 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4095 (ins VR128X:$src1, VR128X:$src2),
4096 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4097 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4098 [(set VR128X:$dst,
4099 (F32Int VR128X:$src1, VR128X:$src2))],
4100 itins_s.rr>, XS, EVEX_4V;
4101 let mayLoad = 1 in {
4102 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4103 (ins FR32X:$src1, f32mem:$src2),
4104 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4105 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4106 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4107 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4108 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4109 (ins VR128X:$src1, ssmem:$src2),
4110 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4111 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4112 [(set VR128X:$dst,
4113 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4114 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4115 }
4116 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4117 (ins FR64X:$src1, FR64X:$src2),
4118 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4119 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4120 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4121 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4122 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4123 (ins VR128X:$src1, VR128X:$src2),
4124 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4125 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4126 [(set VR128X:$dst,
4127 (F64Int VR128X:$src1, VR128X:$src2))],
4128 itins_s.rr>, XD, EVEX_4V, VEX_W;
4129 let mayLoad = 1 in {
4130 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4131 (ins FR64X:$src1, f64mem:$src2),
4132 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4133 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4134 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4135 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4136 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4137 (ins VR128X:$src1, sdmem:$src2),
4138 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4139 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4140 [(set VR128X:$dst,
4141 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4142 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4143 }
4144}
4145
4146
4147defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4148 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4149 SSE_SQRTSS, SSE_SQRTSD>,
4150 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4151 SSE_SQRTPS, SSE_SQRTPD>;
4152
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4153let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4154 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4155 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4156 (VSQRTPSZrr VR512:$src1)>;
4157 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4158 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4159 (VSQRTPDZrr VR512:$src1)>;
4160
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4161 def : Pat<(f32 (fsqrt FR32X:$src)),
4162 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4163 def : Pat<(f32 (fsqrt (load addr:$src))),
4164 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4165 Requires<[OptForSize]>;
4166 def : Pat<(f64 (fsqrt FR64X:$src)),
4167 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4168 def : Pat<(f64 (fsqrt (load addr:$src))),
4169 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4170 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4171
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4172 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4173 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4174 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4175 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4176 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4177
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4178 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4179 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4180 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4181 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4182 Requires<[OptForSize]>;
4183
4184 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4185 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4186 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4187 VR128X)>;
4188 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4189 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4190
4191 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4192 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4193 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4194 VR128X)>;
4195 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4196 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4197}
4198
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4199
4200multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4201 X86MemOperand x86memop, RegisterClass RC,
4202 PatFrag mem_frag32, PatFrag mem_frag64,
4203 Intrinsic V4F32Int, Intrinsic V2F64Int,
4204 CD8VForm VForm> {
4205let ExeDomain = SSEPackedSingle in {
4206 // Intrinsic operation, reg.
4207 // Vector intrinsic operation, reg
4208 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4209 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4210 !strconcat(OpcodeStr,
4211 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4212 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4213
4214 // Vector intrinsic operation, mem
4215 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4216 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4217 !strconcat(OpcodeStr,
4218 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4219 [(set RC:$dst,
4220 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4221 EVEX_CD8<32, VForm>;
4222} // ExeDomain = SSEPackedSingle
4223
4224let ExeDomain = SSEPackedDouble in {
4225 // Vector intrinsic operation, reg
4226 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4227 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4228 !strconcat(OpcodeStr,
4229 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4230 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4231
4232 // Vector intrinsic operation, mem
4233 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4234 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4235 !strconcat(OpcodeStr,
4236 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4237 [(set RC:$dst,
4238 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4239 EVEX_CD8<64, VForm>;
4240} // ExeDomain = SSEPackedDouble
4241}
4242
4243multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4244 string OpcodeStr,
4245 Intrinsic F32Int,
4246 Intrinsic F64Int> {
4247let ExeDomain = GenericDomain in {
4248 // Operation, reg.
4249 let hasSideEffects = 0 in
4250 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4251 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4252 !strconcat(OpcodeStr,
4253 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4254 []>;
4255
4256 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4257 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4258 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4259 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4260 !strconcat(OpcodeStr,
4261 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4262 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4263
4264 // Intrinsic operation, mem.
4265 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4266 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4267 !strconcat(OpcodeStr,
4268 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4269 [(set VR128X:$dst, (F32Int VR128X:$src1,
4270 sse_load_f32:$src2, imm:$src3))]>,
4271 EVEX_CD8<32, CD8VT1>;
4272
4273 // Operation, reg.
4274 let hasSideEffects = 0 in
4275 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4276 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4277 !strconcat(OpcodeStr,
4278 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4279 []>, VEX_W;
4280
4281 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4282 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4283 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4284 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4285 !strconcat(OpcodeStr,
4286 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4287 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4288 VEX_W;
4289
4290 // Intrinsic operation, mem.
4291 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4292 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4293 !strconcat(OpcodeStr,
4294 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4295 [(set VR128X:$dst,
4296 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4297 VEX_W, EVEX_CD8<64, CD8VT1>;
4298} // ExeDomain = GenericDomain
4299}
4300
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4301multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4302 X86MemOperand x86memop, RegisterClass RC,
4303 PatFrag mem_frag, Domain d> {
4304let ExeDomain = d in {
4305 // Intrinsic operation, reg.
4306 // Vector intrinsic operation, reg
4307 def r : AVX512AIi8<opc, MRMSrcReg,
4308 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4309 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4310 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4311 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4312
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4313 // Vector intrinsic operation, mem
4314 def m : AVX512AIi8<opc, MRMSrcMem,
4315 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4316 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4317 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4318 []>, EVEX;
4319} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4320}
4321
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4322
4323defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4324 memopv16f32, SSEPackedSingle>, EVEX_V512,
4325 EVEX_CD8<32, CD8VF>;
4326
4327def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4328 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4329 FROUND_CURRENT)),
4330 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4331
4332
4333defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4334 memopv8f64, SSEPackedDouble>, EVEX_V512,
4335 VEX_W, EVEX_CD8<64, CD8VF>;
4336
4337def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4338 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4339 FROUND_CURRENT)),
4340 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4341
4342multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4343 Operand x86memop, RegisterClass RC, Domain d> {
4344let ExeDomain = d in {
4345 def r : AVX512AIi8<opc, MRMSrcReg,
4346 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4347 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4348 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4349 []>, EVEX_4V;
4350
4351 def m : AVX512AIi8<opc, MRMSrcMem,
4352 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4353 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4354 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4355 []>, EVEX_4V;
4356} // ExeDomain
4357}
4358
4359defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4360 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4361
4362defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4363 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4364
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4365def : Pat<(ffloor FR32X:$src),
4366 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4367def : Pat<(f64 (ffloor FR64X:$src)),
4368 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4369def : Pat<(f32 (fnearbyint FR32X:$src)),
4370 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4371def : Pat<(f64 (fnearbyint FR64X:$src)),
4372 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4373def : Pat<(f32 (fceil FR32X:$src)),
4374 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4375def : Pat<(f64 (fceil FR64X:$src)),
4376 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4377def : Pat<(f32 (frint FR32X:$src)),
4378 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4379def : Pat<(f64 (frint FR64X:$src)),
4380 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4381def : Pat<(f32 (ftrunc FR32X:$src)),
4382 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4383def : Pat<(f64 (ftrunc FR64X:$src)),
4384 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4385
4386def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4387 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4388def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4389 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4390def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4391 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4392def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4393 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4394def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4395 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4396
4397def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4398 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4399def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4400 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4401def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4402 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4403def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4404 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4405def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4406 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4407
4408//-------------------------------------------------
4409// Integer truncate and extend operations
4410//-------------------------------------------------
4411
4412multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4413 RegisterClass dstRC, RegisterClass srcRC,
4414 RegisterClass KRC, X86MemOperand x86memop> {
4415 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4416 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4417 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4418 []>, EVEX;
4419
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4420 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4421 (ins KRC:$mask, srcRC:$src),
4422 !strconcat(OpcodeStr,
4423 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4424 []>, EVEX, EVEX_K;
4425
4426 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4427 (ins KRC:$mask, srcRC:$src),
4428 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4429 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4430 []>, EVEX, EVEX_KZ;
4431
4432 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4433 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4434 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4435
4436 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4437 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4438 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4439 []>, EVEX, EVEX_K;
4440
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4441}
4442defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4443 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4444defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4445 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4446defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4447 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4448defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4449 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4450defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4451 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4452defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4453 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4454defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4455 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4456defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4457 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4458defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4459 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4460defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4461 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4462defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4463 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4464defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4465 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4466defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4467 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4468defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4469 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4470defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4471 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4472
4473def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4474def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4475def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4476def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4477def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4478
4479def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4480 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4481def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4482 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4483def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4484 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4485def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4486 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4487
4488
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4489multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4490 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4491 PatFrag mem_frag, X86MemOperand x86memop,
4492 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4493
4494 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4495 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4496 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4497 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4498
4499 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4500 (ins KRC:$mask, SrcRC:$src),
4501 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4502 []>, EVEX, EVEX_K;
4503
4504 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4505 (ins KRC:$mask, SrcRC:$src),
4506 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4507 []>, EVEX, EVEX_KZ;
4508
4509 let mayLoad = 1 in {
4510 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4511 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4512 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4513 [(set DstRC:$dst,
4514 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4515 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4516
4517 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4518 (ins KRC:$mask, x86memop:$src),
4519 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4520 []>,
4521 EVEX, EVEX_K;
4522
4523 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4524 (ins KRC:$mask, x86memop:$src),
4525 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4526 []>,
4527 EVEX, EVEX_KZ;
4528 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4529}
4530
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4531defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4532 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4533 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4534defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4535 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4536 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4537defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4538 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4539 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4540defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4541 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4542 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4543defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4544 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4545 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4546
4547defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4548 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4549 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4550defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4551 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4552 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4553defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4554 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4555 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4556defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4557 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4558 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4559defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4560 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4561 EVEX_CD8<32, CD8VH>;
4562
4563//===----------------------------------------------------------------------===//
4564// GATHER - SCATTER Operations
4565
4566multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4567 RegisterClass RC, X86MemOperand memop> {
4568let mayLoad = 1,
4569 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4570 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4571 (ins RC:$src1, KRC:$mask, memop:$src2),
4572 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4573 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4574 []>, EVEX, EVEX_K;
4575}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4576
4577let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4578defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4579 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4580defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4581 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4582}
4583
4584let ExeDomain = SSEPackedSingle in {
4585defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4586 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4587defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4588 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4589}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4590
4591defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4592 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4593defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4594 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4595
4596defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4597 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4598defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4599 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4600
4601multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4602 RegisterClass RC, X86MemOperand memop> {
4603let mayStore = 1, Constraints = "$mask = $mask_wb" in
4604 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4605 (ins memop:$dst, KRC:$mask, RC:$src2),
4606 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4607 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4608 []>, EVEX, EVEX_K;
4609}
4610
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4611let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4612defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4613 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4614defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4615 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4616}
4617
4618let ExeDomain = SSEPackedSingle in {
4619defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4620 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4621defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4622 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4623}
4624
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4625defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4626 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4627defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4628 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4629
4630defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4631 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4632defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4633 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4634
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4635// prefetch
4636multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4637 RegisterClass KRC, X86MemOperand memop> {
4638 let Predicates = [HasPFI], hasSideEffects = 1 in
4639 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4640 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4641 []>, EVEX, EVEX_K;
4642}
4643
4644defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4645 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4646
4647defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4648 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4649
4650defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4651 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4652
4653defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4654 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4655
4656defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4657 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4658
4659defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4660 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4661
4662defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4663 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4664
4665defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4666 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4667
4668defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4669 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4670
4671defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4672 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4673
4674defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4675 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4676
4677defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4678 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4679
4680defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4681 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4682
4683defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4684 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4685
4686defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4687 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4688
4689defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4690 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4691//===----------------------------------------------------------------------===//
4692// VSHUFPS - VSHUFPD Operations
4693
4694multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4695 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4696 Domain d> {
4697 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4698 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4699 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4700 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4701 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4702 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4703 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4704 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4705 (ins RC:$src1, RC:$src2, i8imm:$src3),
4706 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4707 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4708 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4709 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4710 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4711}
4712
4713defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4714 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4715defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4716 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4717
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4718def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4719 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4720def : Pat<(v16i32 (X86Shufp VR512:$src1,
4721 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4722 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4723
4724def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4725 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4726def : Pat<(v8i64 (X86Shufp VR512:$src1,
4727 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4728 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4729
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4730multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4731 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4732 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4733 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4734 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4735 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4736 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4737 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4738
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4739 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4740 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4741 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4742
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4743 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4744 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4745 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4746 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4747 " \t{$src3, $src2, $src1, $dst|"
4748 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4749 []>, EVEX_4V;
4750}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4751defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4752defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4753
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4754// Helper fragments to match sext vXi1 to vXiY.
4755def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4756def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4757
4758multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4759 RegisterClass KRC, RegisterClass RC,
4760 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4761 string BrdcstStr> {
4762 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4763 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4764 []>, EVEX;
4765 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4766 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4767 []>, EVEX, EVEX_K;
4768 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4769 !strconcat(OpcodeStr,
4770 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4771 []>, EVEX, EVEX_KZ;
4772 let mayLoad = 1 in {
4773 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4774 (ins x86memop:$src),
4775 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4776 []>, EVEX;
4777 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4778 (ins KRC:$mask, x86memop:$src),
4779 !strconcat(OpcodeStr,
4780 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4781 []>, EVEX, EVEX_K;
4782 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4783 (ins KRC:$mask, x86memop:$src),
4784 !strconcat(OpcodeStr,
4785 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4786 []>, EVEX, EVEX_KZ;
4787 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4788 (ins x86scalar_mop:$src),
4789 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4790 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4791 []>, EVEX, EVEX_B;
4792 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4793 (ins KRC:$mask, x86scalar_mop:$src),
4794 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4795 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4796 []>, EVEX, EVEX_B, EVEX_K;
4797 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4798 (ins KRC:$mask, x86scalar_mop:$src),
4799 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4800 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4801 BrdcstStr, "}"),
4802 []>, EVEX, EVEX_B, EVEX_KZ;
4803 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4804}
4805
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4806defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4807 i512mem, i32mem, "{1to16}">, EVEX_V512,
4808 EVEX_CD8<32, CD8VF>;
4809defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4810 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4811 EVEX_CD8<64, CD8VF>;
4812
4813def : Pat<(xor
4814 (bc_v16i32 (v16i1sextv16i32)),
4815 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4816 (VPABSDZrr VR512:$src)>;
4817def : Pat<(xor
4818 (bc_v8i64 (v8i1sextv8i64)),
4819 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4820 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4821
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4822def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4823 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4824 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4825def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4826 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4827 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4828
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4829multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4830 RegisterClass RC, RegisterClass KRC,
4831 X86MemOperand x86memop,
4832 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4833 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4834 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4835 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4836 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4837 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4838 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4839 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4840 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4841 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4842 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4843 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4844 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4845 []>, EVEX, EVEX_B;
4846 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4847 (ins KRC:$mask, RC:$src),
4848 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4849 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4850 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4851 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4852 (ins KRC:$mask, x86memop:$src),
4853 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4854 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4855 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4856 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4857 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4858 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4859 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4860 BrdcstStr, "}"),
4861 []>, EVEX, EVEX_KZ, EVEX_B;
4862
4863 let Constraints = "$src1 = $dst" in {
4864 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4865 (ins RC:$src1, KRC:$mask, RC:$src2),
4866 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4867 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4868 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4869 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4870 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4871 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4872 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4873 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4874 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4875 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4876 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4877 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4878 []>, EVEX, EVEX_K, EVEX_B;
4879 }
4880}
4881
4882let Predicates = [HasCDI] in {
4883defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4884 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4885 EVEX_V512, EVEX_CD8<32, CD8VF>;
4886
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4887
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4888defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4889 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4890 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4891
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4892}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4893
4894def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4895 GR16:$mask),
4896 (VPCONFLICTDrrk VR512:$src1,
4897 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4898
4899def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4900 GR8:$mask),
4901 (VPCONFLICTQrrk VR512:$src1,
4902 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4903
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4904let Predicates = [HasCDI] in {
4905defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4906 i512mem, i32mem, "{1to16}">,
4907 EVEX_V512, EVEX_CD8<32, CD8VF>;
4908
4909
4910defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4911 i512mem, i64mem, "{1to8}">,
4912 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4913
4914}
4915
4916def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4917 GR16:$mask),
4918 (VPLZCNTDrrk VR512:$src1,
4919 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4920
4921def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4922 GR8:$mask),
4923 (VPLZCNTQrrk VR512:$src1,
4924 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4925
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]4926def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4927 (VPLZCNTDrm addr:$src)>;
4928def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4929 (VPLZCNTDrr VR512:$src)>;
4930def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4931 (VPLZCNTQrm addr:$src)>;
4932def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4933 (VPLZCNTQrr VR512:$src)>;
4934
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4935def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4936def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4937def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]4938
4939def : Pat<(store VK1:$src, addr:$dst),
4940 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4941
4942def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4943 (truncstore node:$val, node:$ptr), [{
4944 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4945}]>;
4946
4947def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4948 (MOV8mr addr:$dst, GR8:$src)>;
4949
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]4950multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4951def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4952 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4953 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4954}
4955
4956multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4957 string OpcodeStr, Predicate prd> {
4958let Predicates = [prd] in
4959 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4960
4961 let Predicates = [prd, HasVLX] in {
4962 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
4963 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
4964 }
4965}
4966
4967multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
4968 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
4969 HasBWI>;
4970 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
4971 HasBWI>, VEX_W;
4972 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
4973 HasDQI>;
4974 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
4975 HasDQI>, VEX_W;
4976}
4977
4978defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;