Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 1 | //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 9 | def isCI : Predicate<"Subtarget->getGeneration() " |
| 10 | ">= AMDGPUSubtarget::SEA_ISLANDS">; |
| 11 | def isVI : Predicate < |
| 12 | "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, |
| 13 | AssemblerPredicate<"FeatureGCN3Encoding">; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 14 | |
Tom Stellard | d1f0f02 | 2015-04-23 19:33:54 +0000 | [diff] [blame] | 15 | def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">; |
| 16 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 17 | class vop { |
| 18 | field bits<9> SI3; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 19 | field bits<10> VI3; |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 20 | } |
| 21 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 22 | class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop { |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 23 | field bits<8> SI = si; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 24 | field bits<8> VI = vi; |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 25 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 26 | field bits<9> SI3 = {0, si{7-0}}; |
| 27 | field bits<10> VI3 = {0, 0, vi{7-0}}; |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 28 | } |
| 29 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 30 | class vop1 <bits<8> si, bits<8> vi = si> : vop { |
| 31 | field bits<8> SI = si; |
| 32 | field bits<8> VI = vi; |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 33 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 34 | field bits<9> SI3 = {1, 1, si{6-0}}; |
| 35 | field bits<10> VI3 = !add(0x140, vi); |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 36 | } |
| 37 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 38 | class vop2 <bits<6> si, bits<6> vi = si> : vop { |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 39 | field bits<6> SI = si; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 40 | field bits<6> VI = vi; |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 41 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 42 | field bits<9> SI3 = {1, 0, 0, si{5-0}}; |
| 43 | field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}}; |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 44 | } |
| 45 | |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 46 | // Specify a VOP2 opcode for SI and VOP3 opcode for VI |
| 47 | // that doesn't have VOP2 encoding on VI |
| 48 | class vop23 <bits<6> si, bits<10> vi> : vop2 <si> { |
| 49 | let VI3 = vi; |
| 50 | } |
| 51 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 52 | class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop { |
| 53 | let SI3 = si; |
| 54 | let VI3 = vi; |
| 55 | } |
| 56 | |
| 57 | class sop1 <bits<8> si, bits<8> vi = si> { |
| 58 | field bits<8> SI = si; |
| 59 | field bits<8> VI = vi; |
| 60 | } |
| 61 | |
| 62 | class sop2 <bits<7> si, bits<7> vi = si> { |
| 63 | field bits<7> SI = si; |
| 64 | field bits<7> VI = vi; |
| 65 | } |
| 66 | |
| 67 | class sopk <bits<5> si, bits<5> vi = si> { |
| 68 | field bits<5> SI = si; |
| 69 | field bits<5> VI = vi; |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 70 | } |
| 71 | |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 72 | // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum |
Marek Olsak | a93603d | 2015-01-15 18:42:51 +0000 | [diff] [blame] | 73 | // in AMDGPUInstrInfo.cpp |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 74 | def SISubtarget { |
| 75 | int NONE = -1; |
| 76 | int SI = 0; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 77 | int VI = 1; |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 78 | } |
| 79 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 80 | //===----------------------------------------------------------------------===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 81 | // SI DAG Nodes |
| 82 | //===----------------------------------------------------------------------===// |
| 83 | |
Tom Stellard | 9fa1791 | 2013-08-14 23:24:45 +0000 | [diff] [blame] | 84 | def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT", |
Tom Stellard | 868fd92 | 2014-04-17 21:00:11 +0000 | [diff] [blame] | 85 | SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>, |
Tom Stellard | 9fa1791 | 2013-08-14 23:24:45 +0000 | [diff] [blame] | 86 | [SDNPMayLoad, SDNPMemOperand] |
| 87 | >; |
| 88 | |
Tom Stellard | afcf12f | 2013-09-12 02:55:14 +0000 | [diff] [blame] | 89 | def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", |
| 90 | SDTypeProfile<0, 13, |
Tom Stellard | 868fd92 | 2014-04-17 21:00:11 +0000 | [diff] [blame] | 91 | [SDTCisVT<0, v4i32>, // rsrc(SGPR) |
Tom Stellard | afcf12f | 2013-09-12 02:55:14 +0000 | [diff] [blame] | 92 | SDTCisVT<1, iAny>, // vdata(VGPR) |
| 93 | SDTCisVT<2, i32>, // num_channels(imm) |
| 94 | SDTCisVT<3, i32>, // vaddr(VGPR) |
| 95 | SDTCisVT<4, i32>, // soffset(SGPR) |
| 96 | SDTCisVT<5, i32>, // inst_offset(imm) |
| 97 | SDTCisVT<6, i32>, // dfmt(imm) |
| 98 | SDTCisVT<7, i32>, // nfmt(imm) |
| 99 | SDTCisVT<8, i32>, // offen(imm) |
| 100 | SDTCisVT<9, i32>, // idxen(imm) |
| 101 | SDTCisVT<10, i32>, // glc(imm) |
| 102 | SDTCisVT<11, i32>, // slc(imm) |
| 103 | SDTCisVT<12, i32> // tfe(imm) |
| 104 | ]>, |
| 105 | [SDNPMayStore, SDNPMemOperand, SDNPHasChain] |
| 106 | >; |
| 107 | |
Tom Stellard | 9fa1791 | 2013-08-14 23:24:45 +0000 | [diff] [blame] | 108 | def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT", |
Tom Stellard | 868fd92 | 2014-04-17 21:00:11 +0000 | [diff] [blame] | 109 | SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>, |
Tom Stellard | 9fa1791 | 2013-08-14 23:24:45 +0000 | [diff] [blame] | 110 | SDTCisVT<3, i32>]> |
| 111 | >; |
| 112 | |
| 113 | class SDSample<string opcode> : SDNode <opcode, |
Tom Stellard | 6785065 | 2013-08-14 23:24:53 +0000 | [diff] [blame] | 114 | SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>, |
Tom Stellard | 868fd92 | 2014-04-17 21:00:11 +0000 | [diff] [blame] | 115 | SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]> |
Tom Stellard | 9fa1791 | 2013-08-14 23:24:45 +0000 | [diff] [blame] | 116 | >; |
| 117 | |
| 118 | def SIsample : SDSample<"AMDGPUISD::SAMPLE">; |
| 119 | def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">; |
| 120 | def SIsampled : SDSample<"AMDGPUISD::SAMPLED">; |
| 121 | def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">; |
| 122 | |
Tom Stellard | 067c815 | 2014-07-21 14:01:14 +0000 | [diff] [blame] | 123 | def SIconstdata_ptr : SDNode< |
| 124 | "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]> |
| 125 | >; |
| 126 | |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 127 | //===----------------------------------------------------------------------===// |
| 128 | // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1 |
| 129 | // to be glued to the memory instructions. |
| 130 | //===----------------------------------------------------------------------===// |
| 131 | |
| 132 | def SIld_local : SDNode <"ISD::LOAD", SDTLoad, |
| 133 | [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue] |
| 134 | >; |
| 135 | |
| 136 | def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{ |
| 137 | return isLocalLoad(cast<LoadSDNode>(N)); |
| 138 | }]>; |
| 139 | |
| 140 | def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{ |
| 141 | return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED && |
| 142 | cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; |
| 143 | }]>; |
| 144 | |
| 145 | def si_load_local_align8 : Aligned8Bytes < |
| 146 | (ops node:$ptr), (si_load_local node:$ptr) |
| 147 | >; |
| 148 | |
| 149 | def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{ |
| 150 | return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; |
| 151 | }]>; |
| 152 | def si_az_extload_local : AZExtLoadBase <si_ld_local>; |
| 153 | |
| 154 | multiclass SIExtLoadLocal <PatFrag ld_node> { |
| 155 | |
| 156 | def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr), |
| 157 | [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}] |
| 158 | >; |
| 159 | |
| 160 | def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr), |
| 161 | [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}] |
| 162 | >; |
| 163 | } |
| 164 | |
| 165 | defm si_sextload_local : SIExtLoadLocal <si_sextload_local>; |
| 166 | defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>; |
| 167 | |
| 168 | def SIst_local : SDNode <"ISD::STORE", SDTStore, |
| 169 | [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue] |
| 170 | >; |
| 171 | |
| 172 | def si_st_local : PatFrag < |
| 173 | (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{ |
| 174 | return isLocalStore(cast<StoreSDNode>(N)); |
| 175 | }]>; |
| 176 | |
| 177 | def si_store_local : PatFrag < |
| 178 | (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{ |
| 179 | return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED && |
| 180 | !cast<StoreSDNode>(N)->isTruncatingStore(); |
| 181 | }]>; |
| 182 | |
| 183 | def si_store_local_align8 : Aligned8Bytes < |
| 184 | (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr) |
| 185 | >; |
| 186 | |
| 187 | def si_truncstore_local : PatFrag < |
| 188 | (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{ |
| 189 | return cast<StoreSDNode>(N)->isTruncatingStore(); |
| 190 | }]>; |
| 191 | |
| 192 | def si_truncstore_local_i8 : PatFrag < |
| 193 | (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{ |
| 194 | return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; |
| 195 | }]>; |
| 196 | |
| 197 | def si_truncstore_local_i16 : PatFrag < |
| 198 | (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{ |
| 199 | return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; |
| 200 | }]>; |
| 201 | |
| 202 | multiclass SIAtomicM0Glue2 <string op_name> { |
| 203 | |
| 204 | def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2, |
| 205 | [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue] |
| 206 | >; |
| 207 | |
| 208 | def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>; |
| 209 | } |
| 210 | |
| 211 | defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">; |
| 212 | defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">; |
| 213 | defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">; |
| 214 | defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">; |
| 215 | defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">; |
| 216 | defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">; |
| 217 | defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">; |
| 218 | defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">; |
| 219 | defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">; |
| 220 | defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">; |
| 221 | |
| 222 | def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3, |
| 223 | [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue] |
| 224 | >; |
| 225 | |
| 226 | defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>; |
| 227 | |
Tom Stellard | 26075d5 | 2013-02-07 19:39:38 +0000 | [diff] [blame] | 228 | // Transformation function, extract the lower 32bit of a 64bit immediate |
| 229 | def LO32 : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 230 | return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N), |
| 231 | MVT::i32); |
Tom Stellard | 26075d5 | 2013-02-07 19:39:38 +0000 | [diff] [blame] | 232 | }]>; |
| 233 | |
Tom Stellard | ab8a8c8 | 2013-07-12 18:15:02 +0000 | [diff] [blame] | 234 | def LO32f : SDNodeXForm<fpimm, [{ |
Benjamin Kramer | c22c790 | 2013-07-12 20:18:05 +0000 | [diff] [blame] | 235 | APInt V = N->getValueAPF().bitcastToAPInt().trunc(32); |
| 236 | return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32); |
Tom Stellard | ab8a8c8 | 2013-07-12 18:15:02 +0000 | [diff] [blame] | 237 | }]>; |
| 238 | |
Tom Stellard | 26075d5 | 2013-02-07 19:39:38 +0000 | [diff] [blame] | 239 | // Transformation function, extract the upper 32bit of a 64bit immediate |
| 240 | def HI32 : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 241 | return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32); |
Tom Stellard | 26075d5 | 2013-02-07 19:39:38 +0000 | [diff] [blame] | 242 | }]>; |
| 243 | |
Tom Stellard | ab8a8c8 | 2013-07-12 18:15:02 +0000 | [diff] [blame] | 244 | def HI32f : SDNodeXForm<fpimm, [{ |
Benjamin Kramer | c22c790 | 2013-07-12 20:18:05 +0000 | [diff] [blame] | 245 | APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32); |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 246 | return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N), |
| 247 | MVT::f32); |
Tom Stellard | ab8a8c8 | 2013-07-12 18:15:02 +0000 | [diff] [blame] | 248 | }]>; |
| 249 | |
Tom Stellard | 044e418 | 2014-02-06 18:36:34 +0000 | [diff] [blame] | 250 | def IMM8bitDWORD : PatLeaf <(imm), |
| 251 | [{return (N->getZExtValue() & ~0x3FC) == 0;}] |
Tom Stellard | 8909380 | 2013-02-07 19:39:40 +0000 | [diff] [blame] | 252 | >; |
| 253 | |
Tom Stellard | 044e418 | 2014-02-06 18:36:34 +0000 | [diff] [blame] | 254 | def as_dword_i32imm : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 255 | return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32); |
Tom Stellard | 044e418 | 2014-02-06 18:36:34 +0000 | [diff] [blame] | 256 | }]>; |
| 257 | |
Tom Stellard | afcf12f | 2013-09-12 02:55:14 +0000 | [diff] [blame] | 258 | def as_i1imm : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 259 | return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1); |
Tom Stellard | afcf12f | 2013-09-12 02:55:14 +0000 | [diff] [blame] | 260 | }]>; |
| 261 | |
| 262 | def as_i8imm : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 263 | return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8); |
Tom Stellard | afcf12f | 2013-09-12 02:55:14 +0000 | [diff] [blame] | 264 | }]>; |
| 265 | |
Tom Stellard | 07a10a3 | 2013-06-03 17:39:43 +0000 | [diff] [blame] | 266 | def as_i16imm : SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 267 | return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16); |
Tom Stellard | 07a10a3 | 2013-06-03 17:39:43 +0000 | [diff] [blame] | 268 | }]>; |
| 269 | |
Tom Stellard | 044e418 | 2014-02-06 18:36:34 +0000 | [diff] [blame] | 270 | def as_i32imm: SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 271 | return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); |
Tom Stellard | 044e418 | 2014-02-06 18:36:34 +0000 | [diff] [blame] | 272 | }]>; |
| 273 | |
Matt Arsenault | becd656 | 2014-12-03 05:22:35 +0000 | [diff] [blame] | 274 | def as_i64imm: SDNodeXForm<imm, [{ |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 275 | return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64); |
Matt Arsenault | becd656 | 2014-12-03 05:22:35 +0000 | [diff] [blame] | 276 | }]>; |
| 277 | |
Tom Stellard | fb77f00 | 2015-01-13 22:59:41 +0000 | [diff] [blame] | 278 | // Copied from the AArch64 backend: |
| 279 | def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ |
| 280 | return CurDAG->getTargetConstant( |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 281 | N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); |
Tom Stellard | fb77f00 | 2015-01-13 22:59:41 +0000 | [diff] [blame] | 282 | }]>; |
| 283 | |
| 284 | // Copied from the AArch64 backend: |
| 285 | def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ |
| 286 | return CurDAG->getTargetConstant( |
Sergey Dmitrouk | 842a51b | 2015-04-28 14:05:47 +0000 | [diff] [blame] | 287 | N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); |
Tom Stellard | fb77f00 | 2015-01-13 22:59:41 +0000 | [diff] [blame] | 288 | }]>; |
| 289 | |
Matt Arsenault | 99ed789 | 2014-03-19 22:19:49 +0000 | [diff] [blame] | 290 | def IMM8bit : PatLeaf <(imm), |
| 291 | [{return isUInt<8>(N->getZExtValue());}] |
| 292 | >; |
| 293 | |
Tom Stellard | 07a10a3 | 2013-06-03 17:39:43 +0000 | [diff] [blame] | 294 | def IMM12bit : PatLeaf <(imm), |
| 295 | [{return isUInt<12>(N->getZExtValue());}] |
Tom Stellard | 8909380 | 2013-02-07 19:39:40 +0000 | [diff] [blame] | 296 | >; |
| 297 | |
Matt Arsenault | 99ed789 | 2014-03-19 22:19:49 +0000 | [diff] [blame] | 298 | def IMM16bit : PatLeaf <(imm), |
| 299 | [{return isUInt<16>(N->getZExtValue());}] |
| 300 | >; |
| 301 | |
Marek Olsak | 58f61a8 | 2014-12-07 17:17:38 +0000 | [diff] [blame] | 302 | def IMM20bit : PatLeaf <(imm), |
| 303 | [{return isUInt<20>(N->getZExtValue());}] |
| 304 | >; |
| 305 | |
Tom Stellard | d6cb8e8 | 2014-05-09 16:42:21 +0000 | [diff] [blame] | 306 | def IMM32bit : PatLeaf <(imm), |
| 307 | [{return isUInt<32>(N->getZExtValue());}] |
| 308 | >; |
| 309 | |
Tom Stellard | e236794 | 2014-02-06 18:36:41 +0000 | [diff] [blame] | 310 | def mubuf_vaddr_offset : PatFrag< |
| 311 | (ops node:$ptr, node:$offset, node:$imm_offset), |
| 312 | (add (add node:$ptr, node:$offset), node:$imm_offset) |
| 313 | >; |
| 314 | |
Christian Konig | f82901a | 2013-02-26 17:52:23 +0000 | [diff] [blame] | 315 | class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{ |
Tom Stellard | 7ed0b52 | 2014-04-03 20:19:27 +0000 | [diff] [blame] | 316 | return isInlineImmediate(N); |
Christian Konig | b559b07 | 2013-02-16 11:28:36 +0000 | [diff] [blame] | 317 | }]>; |
| 318 | |
Matt Arsenault | 303011a | 2014-12-17 21:04:08 +0000 | [diff] [blame] | 319 | class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{ |
| 320 | return isInlineImmediate(N); |
| 321 | }]>; |
| 322 | |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 323 | class SGPRImm <dag frag> : PatLeaf<frag, [{ |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 324 | if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) { |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 325 | return false; |
| 326 | } |
| 327 | const SIRegisterInfo *SIRI = |
Eric Christopher | 7792e32 | 2015-01-30 23:24:40 +0000 | [diff] [blame] | 328 | static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo()); |
Tom Stellard | df94dc3 | 2013-08-14 23:24:24 +0000 | [diff] [blame] | 329 | for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end(); |
| 330 | U != E; ++U) { |
| 331 | if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) { |
| 332 | return true; |
| 333 | } |
| 334 | } |
| 335 | return false; |
| 336 | }]>; |
| 337 | |
Tom Stellard | 01825af | 2014-07-21 14:01:08 +0000 | [diff] [blame] | 338 | //===----------------------------------------------------------------------===// |
| 339 | // Custom Operands |
| 340 | //===----------------------------------------------------------------------===// |
| 341 | |
Matt Arsenault | a98cd6a | 2013-12-19 05:32:55 +0000 | [diff] [blame] | 342 | def FRAMEri32 : Operand<iPTR> { |
Matt Arsenault | 06028dd | 2014-05-01 16:37:52 +0000 | [diff] [blame] | 343 | let MIOperandInfo = (ops i32:$ptr, i32imm:$index); |
Tom Stellard | 81d871d | 2013-11-13 23:36:50 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 346 | def SoppBrTarget : AsmOperandClass { |
| 347 | let Name = "SoppBrTarget"; |
| 348 | let ParserMethod = "parseSOppBrTarget"; |
| 349 | } |
| 350 | |
Tom Stellard | 01825af | 2014-07-21 14:01:08 +0000 | [diff] [blame] | 351 | def sopp_brtarget : Operand<OtherVT> { |
| 352 | let EncoderMethod = "getSOPPBrEncoding"; |
| 353 | let OperandType = "OPERAND_PCREL"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 354 | let ParserMatchClass = SoppBrTarget; |
Tom Stellard | 01825af | 2014-07-21 14:01:08 +0000 | [diff] [blame] | 355 | } |
| 356 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 357 | include "SIInstrFormats.td" |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 358 | include "VIInstrFormats.td" |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 359 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 360 | def MubufOffsetMatchClass : AsmOperandClass { |
| 361 | let Name = "MubufOffset"; |
| 362 | let ParserMethod = "parseMubufOptionalOps"; |
| 363 | let RenderMethod = "addImmOperands"; |
| 364 | } |
| 365 | |
| 366 | class DSOffsetBaseMatchClass <string parser> : AsmOperandClass { |
| 367 | let Name = "DSOffset"#parser; |
| 368 | let ParserMethod = parser; |
| 369 | let RenderMethod = "addImmOperands"; |
| 370 | let PredicateMethod = "isDSOffset"; |
| 371 | } |
| 372 | |
| 373 | def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">; |
| 374 | def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">; |
| 375 | |
| 376 | def DSOffset01MatchClass : AsmOperandClass { |
| 377 | let Name = "DSOffset1"; |
| 378 | let ParserMethod = "parseDSOff01OptionalOps"; |
| 379 | let RenderMethod = "addImmOperands"; |
| 380 | let PredicateMethod = "isDSOffset01"; |
| 381 | } |
| 382 | |
| 383 | class GDSBaseMatchClass <string parser> : AsmOperandClass { |
| 384 | let Name = "GDS"#parser; |
| 385 | let PredicateMethod = "isImm"; |
| 386 | let ParserMethod = parser; |
| 387 | let RenderMethod = "addImmOperands"; |
| 388 | } |
| 389 | |
| 390 | def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">; |
| 391 | def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">; |
| 392 | |
| 393 | def GLCMatchClass : AsmOperandClass { |
| 394 | let Name = "GLC"; |
| 395 | let PredicateMethod = "isImm"; |
| 396 | let ParserMethod = "parseMubufOptionalOps"; |
| 397 | let RenderMethod = "addImmOperands"; |
| 398 | } |
| 399 | |
| 400 | def SLCMatchClass : AsmOperandClass { |
| 401 | let Name = "SLC"; |
| 402 | let PredicateMethod = "isImm"; |
| 403 | let ParserMethod = "parseMubufOptionalOps"; |
| 404 | let RenderMethod = "addImmOperands"; |
| 405 | } |
| 406 | |
| 407 | def TFEMatchClass : AsmOperandClass { |
| 408 | let Name = "TFE"; |
| 409 | let PredicateMethod = "isImm"; |
| 410 | let ParserMethod = "parseMubufOptionalOps"; |
| 411 | let RenderMethod = "addImmOperands"; |
| 412 | } |
| 413 | |
| 414 | def OModMatchClass : AsmOperandClass { |
| 415 | let Name = "OMod"; |
| 416 | let PredicateMethod = "isImm"; |
| 417 | let ParserMethod = "parseVOP3OptionalOps"; |
| 418 | let RenderMethod = "addImmOperands"; |
| 419 | } |
| 420 | |
| 421 | def ClampMatchClass : AsmOperandClass { |
| 422 | let Name = "Clamp"; |
| 423 | let PredicateMethod = "isImm"; |
| 424 | let ParserMethod = "parseVOP3OptionalOps"; |
| 425 | let RenderMethod = "addImmOperands"; |
| 426 | } |
| 427 | |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 428 | let OperandType = "OPERAND_IMMEDIATE" in { |
| 429 | |
| 430 | def offen : Operand<i1> { |
| 431 | let PrintMethod = "printOffen"; |
| 432 | } |
| 433 | def idxen : Operand<i1> { |
| 434 | let PrintMethod = "printIdxen"; |
| 435 | } |
| 436 | def addr64 : Operand<i1> { |
| 437 | let PrintMethod = "printAddr64"; |
| 438 | } |
| 439 | def mbuf_offset : Operand<i16> { |
| 440 | let PrintMethod = "printMBUFOffset"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 441 | let ParserMatchClass = MubufOffsetMatchClass; |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 442 | } |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 443 | class ds_offset_base <AsmOperandClass mc> : Operand<i16> { |
Matt Arsenault | 61cc908 | 2014-10-10 22:16:07 +0000 | [diff] [blame] | 444 | let PrintMethod = "printDSOffset"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 445 | let ParserMatchClass = mc; |
Matt Arsenault | 61cc908 | 2014-10-10 22:16:07 +0000 | [diff] [blame] | 446 | } |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 447 | def ds_offset : ds_offset_base <DSOffsetMatchClass>; |
| 448 | def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>; |
| 449 | |
Matt Arsenault | 61cc908 | 2014-10-10 22:16:07 +0000 | [diff] [blame] | 450 | def ds_offset0 : Operand<i8> { |
| 451 | let PrintMethod = "printDSOffset0"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 452 | let ParserMatchClass = DSOffset01MatchClass; |
Matt Arsenault | 61cc908 | 2014-10-10 22:16:07 +0000 | [diff] [blame] | 453 | } |
| 454 | def ds_offset1 : Operand<i8> { |
| 455 | let PrintMethod = "printDSOffset1"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 456 | let ParserMatchClass = DSOffset01MatchClass; |
Matt Arsenault | 61cc908 | 2014-10-10 22:16:07 +0000 | [diff] [blame] | 457 | } |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 458 | class gds_base <AsmOperandClass mc> : Operand <i1> { |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 459 | let PrintMethod = "printGDS"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 460 | let ParserMatchClass = mc; |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 461 | } |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 462 | def gds : gds_base <GDSMatchClass>; |
| 463 | |
| 464 | def gds01 : gds_base <GDS01MatchClass>; |
| 465 | |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 466 | def glc : Operand <i1> { |
| 467 | let PrintMethod = "printGLC"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 468 | let ParserMatchClass = GLCMatchClass; |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 469 | } |
| 470 | def slc : Operand <i1> { |
| 471 | let PrintMethod = "printSLC"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 472 | let ParserMatchClass = SLCMatchClass; |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 473 | } |
| 474 | def tfe : Operand <i1> { |
| 475 | let PrintMethod = "printTFE"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 476 | let ParserMatchClass = TFEMatchClass; |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 477 | } |
| 478 | |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 479 | def omod : Operand <i32> { |
| 480 | let PrintMethod = "printOModSI"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 481 | let ParserMatchClass = OModMatchClass; |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | def ClampMod : Operand <i1> { |
| 485 | let PrintMethod = "printClampSI"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 486 | let ParserMatchClass = ClampMatchClass; |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 487 | } |
| 488 | |
Tom Stellard | 229d5e6 | 2014-08-05 14:48:12 +0000 | [diff] [blame] | 489 | } // End OperandType = "OPERAND_IMMEDIATE" |
| 490 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 491 | def VOPDstS64 : VOPDstOperand <SReg_64>; |
| 492 | |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 493 | //===----------------------------------------------------------------------===// |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 494 | // Complex patterns |
| 495 | //===----------------------------------------------------------------------===// |
| 496 | |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 497 | def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">; |
Tom Stellard | f3fc555 | 2014-08-22 18:49:35 +0000 | [diff] [blame] | 498 | def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">; |
Tom Stellard | 85e8b6d | 2014-08-22 18:49:33 +0000 | [diff] [blame] | 499 | |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 500 | def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">; |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 501 | def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">; |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 502 | def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">; |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame] | 503 | def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 504 | def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 505 | def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">; |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 506 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 507 | def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">; |
Matt Arsenault | 1cffa4c | 2014-11-13 19:49:04 +0000 | [diff] [blame] | 508 | def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">; |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 509 | def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 510 | def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">; |
| 511 | |
Tom Stellard | b02c268 | 2014-06-24 23:33:07 +0000 | [diff] [blame] | 512 | //===----------------------------------------------------------------------===// |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 513 | // SI assembler operands |
| 514 | //===----------------------------------------------------------------------===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 515 | |
Christian Konig | eabf833 | 2013-02-21 15:16:49 +0000 | [diff] [blame] | 516 | def SIOperand { |
| 517 | int ZERO = 0x80; |
Christian Konig | d303996 | 2013-02-26 17:52:09 +0000 | [diff] [blame] | 518 | int VCC = 0x6A; |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 519 | int FLAT_SCR = 0x68; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 520 | } |
| 521 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 522 | def SRCMODS { |
| 523 | int NONE = 0; |
Marek Olsak | 7d77728 | 2015-03-24 13:40:15 +0000 | [diff] [blame] | 524 | int NEG = 1; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 525 | } |
| 526 | |
| 527 | def DSTCLAMP { |
| 528 | int NONE = 0; |
| 529 | } |
| 530 | |
| 531 | def DSTOMOD { |
| 532 | int NONE = 0; |
| 533 | } |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 534 | |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 535 | //===----------------------------------------------------------------------===// |
| 536 | // |
| 537 | // SI Instruction multiclass helpers. |
| 538 | // |
| 539 | // Instructions with _32 take 32-bit operands. |
| 540 | // Instructions with _64 take 64-bit operands. |
| 541 | // |
| 542 | // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit |
| 543 | // encoding is the standard encoding, but instruction that make use of |
| 544 | // any of the instruction modifiers must use the 64-bit encoding. |
| 545 | // |
| 546 | // Instructions with _e32 use the 32-bit encoding. |
| 547 | // Instructions with _e64 use the 64-bit encoding. |
| 548 | // |
| 549 | //===----------------------------------------------------------------------===// |
| 550 | |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 551 | class SIMCInstr <string pseudo, int subtarget> { |
| 552 | string PseudoInstr = pseudo; |
| 553 | int Subtarget = subtarget; |
| 554 | } |
| 555 | |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 556 | //===----------------------------------------------------------------------===// |
Tom Stellard | 3a35d8f | 2014-10-01 14:44:45 +0000 | [diff] [blame] | 557 | // EXP classes |
| 558 | //===----------------------------------------------------------------------===// |
| 559 | |
| 560 | class EXPCommon : InstSI< |
| 561 | (outs), |
| 562 | (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 563 | VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3), |
Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 564 | "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", |
Tom Stellard | 3a35d8f | 2014-10-01 14:44:45 +0000 | [diff] [blame] | 565 | [] > { |
| 566 | |
| 567 | let EXP_CNT = 1; |
| 568 | let Uses = [EXEC]; |
| 569 | } |
| 570 | |
| 571 | multiclass EXP_m { |
| 572 | |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 573 | let isPseudo = 1, isCodeGenOnly = 1 in { |
Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 574 | def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ; |
Tom Stellard | 3a35d8f | 2014-10-01 14:44:45 +0000 | [diff] [blame] | 575 | } |
| 576 | |
Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 577 | def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 578 | |
| 579 | def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi; |
Tom Stellard | 3a35d8f | 2014-10-01 14:44:45 +0000 | [diff] [blame] | 580 | } |
| 581 | |
| 582 | //===----------------------------------------------------------------------===// |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 583 | // Scalar classes |
| 584 | //===----------------------------------------------------------------------===// |
| 585 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 586 | class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 587 | SOP1 <outs, ins, "", pattern>, |
| 588 | SIMCInstr<opName, SISubtarget.NONE> { |
| 589 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 590 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 591 | } |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 592 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 593 | class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> : |
| 594 | SOP1 <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 595 | SOP1e <op.SI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 596 | SIMCInstr<opName, SISubtarget.SI> { |
| 597 | let isCodeGenOnly = 0; |
| 598 | let AssemblerPredicates = [isSICI]; |
| 599 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 600 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 601 | class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> : |
| 602 | SOP1 <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 603 | SOP1e <op.VI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 604 | SIMCInstr<opName, SISubtarget.VI> { |
| 605 | let isCodeGenOnly = 0; |
| 606 | let AssemblerPredicates = [isVI]; |
| 607 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 608 | |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 609 | multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm, |
| 610 | list<dag> pattern> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 611 | |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 612 | def "" : SOP1_Pseudo <opName, outs, ins, pattern>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 613 | |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 614 | def _si : SOP1_Real_si <op, opName, outs, ins, asm>; |
| 615 | |
| 616 | def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>; |
| 617 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 618 | } |
| 619 | |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 620 | multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m < |
| 621 | op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0), |
| 622 | opName#" $dst, $src0", pattern |
| 623 | >; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 624 | |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 625 | multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m < |
| 626 | op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0), |
| 627 | opName#" $dst, $src0", pattern |
| 628 | >; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 629 | |
| 630 | // no input, 64-bit output. |
| 631 | multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> { |
| 632 | def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>; |
| 633 | |
| 634 | def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 635 | opName#" $dst"> { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 636 | let ssrc0 = 0; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 640 | opName#" $dst"> { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 641 | let ssrc0 = 0; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 642 | } |
| 643 | } |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 644 | |
Tom Stellard | ce449ad | 2015-02-18 16:08:11 +0000 | [diff] [blame] | 645 | // 64-bit input, no output |
| 646 | multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> { |
| 647 | def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>; |
| 648 | |
| 649 | def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0), |
| 650 | opName#" $src0"> { |
| 651 | let sdst = 0; |
| 652 | } |
| 653 | |
| 654 | def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0), |
| 655 | opName#" $src0"> { |
| 656 | let sdst = 0; |
| 657 | } |
| 658 | } |
| 659 | |
Matt Arsenault | 8333e43 | 2014-06-10 19:18:24 +0000 | [diff] [blame] | 660 | // 64-bit input, 32-bit output. |
Tom Stellard | e1e4a2d3 | 2015-02-13 21:02:37 +0000 | [diff] [blame] | 661 | multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m < |
| 662 | op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0), |
| 663 | opName#" $dst, $src0", pattern |
| 664 | >; |
Matt Arsenault | 1a179e8 | 2014-11-13 20:23:36 +0000 | [diff] [blame] | 665 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 666 | class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> : |
| 667 | SOP2<outs, ins, "", pattern>, |
| 668 | SIMCInstr<opName, SISubtarget.NONE> { |
| 669 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 670 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 671 | let Size = 4; |
Tom Stellard | 0c0008c | 2015-02-18 16:08:13 +0000 | [diff] [blame] | 672 | |
| 673 | // Pseudo instructions have no encodings, but adding this field here allows |
| 674 | // us to do: |
| 675 | // let sdst = xxx in { |
| 676 | // for multiclasses that include both real and pseudo instructions. |
| 677 | field bits<7> sdst = 0; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 678 | } |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 679 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 680 | class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> : |
| 681 | SOP2<outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 682 | SOP2e<op.SI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 683 | SIMCInstr<opName, SISubtarget.SI> { |
| 684 | let AssemblerPredicates = [isSICI]; |
| 685 | } |
Matt Arsenault | 9481221 | 2014-11-14 18:18:16 +0000 | [diff] [blame] | 686 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 687 | class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> : |
| 688 | SOP2<outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 689 | SOP2e<op.VI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 690 | SIMCInstr<opName, SISubtarget.VI> { |
| 691 | let AssemblerPredicates = [isVI]; |
| 692 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 693 | |
| 694 | multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> { |
| 695 | def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst), |
| 696 | (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>; |
| 697 | |
| 698 | def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst), |
| 699 | (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 700 | opName#" $dst, $src0, $src1 [$scc]">; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 701 | |
| 702 | def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst), |
| 703 | (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 704 | opName#" $dst, $src0, $src1 [$scc]">; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 705 | } |
| 706 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 707 | multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm, |
| 708 | list<dag> pattern> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 709 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 710 | def "" : SOP2_Pseudo <opName, outs, ins, pattern>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 711 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 712 | def _si : SOP2_Real_si <op, opName, outs, ins, asm>; |
| 713 | |
| 714 | def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>; |
| 715 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 716 | } |
| 717 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 718 | multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m < |
| 719 | op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), |
| 720 | opName#" $dst, $src0, $src1", pattern |
| 721 | >; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 722 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 723 | multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m < |
| 724 | op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), |
| 725 | opName#" $dst, $src0, $src1", pattern |
| 726 | >; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 727 | |
Tom Stellard | ee21faa | 2015-02-18 16:08:09 +0000 | [diff] [blame] | 728 | multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m < |
| 729 | op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1), |
| 730 | opName#" $dst, $src0, $src1", pattern |
| 731 | >; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 732 | |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 733 | class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt, |
Matt Arsenault | 0cb92e1 | 2014-04-11 19:25:18 +0000 | [diff] [blame] | 734 | string opName, PatLeaf cond> : SOPC < |
| 735 | op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1), |
Tom Stellard | e2f5b41 | 2015-03-12 21:34:28 +0000 | [diff] [blame] | 736 | opName#" $src0, $src1", []>; |
Matt Arsenault | 0cb92e1 | 2014-04-11 19:25:18 +0000 | [diff] [blame] | 737 | |
| 738 | class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL> |
| 739 | : SOPC_Helper<op, SSrc_32, i32, opName, cond>; |
| 740 | |
| 741 | class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL> |
| 742 | : SOPC_Helper<op, SSrc_64, i64, opName, cond>; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 743 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 744 | class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 745 | SOPK <outs, ins, "", pattern>, |
| 746 | SIMCInstr<opName, SISubtarget.NONE> { |
| 747 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 748 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 749 | } |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 750 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 751 | class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> : |
| 752 | SOPK <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 753 | SOPKe <op.SI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 754 | SIMCInstr<opName, SISubtarget.SI> { |
| 755 | let AssemblerPredicates = [isSICI]; |
| 756 | let isCodeGenOnly = 0; |
| 757 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 758 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 759 | class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> : |
| 760 | SOPK <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 761 | SOPKe <op.VI>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 762 | SIMCInstr<opName, SISubtarget.VI> { |
| 763 | let AssemblerPredicates = [isVI]; |
| 764 | let isCodeGenOnly = 0; |
| 765 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 766 | |
Tom Stellard | 8980dc3 | 2015-04-08 01:09:22 +0000 | [diff] [blame] | 767 | multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm, |
| 768 | string asm = opName#opAsm> { |
| 769 | def "" : SOPK_Pseudo <opName, outs, ins, []>; |
| 770 | |
| 771 | def _si : SOPK_Real_si <op, opName, outs, ins, asm>; |
| 772 | |
| 773 | def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>; |
| 774 | |
| 775 | } |
| 776 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 777 | multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> { |
| 778 | def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0), |
| 779 | pattern>; |
| 780 | |
| 781 | def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 782 | opName#" $dst, $src0">; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 783 | |
| 784 | def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0), |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 785 | opName#" $dst, $src0">; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> { |
| 789 | def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst), |
| 790 | (ins SReg_32:$src0, u16imm:$src1), pattern>; |
| 791 | |
Tom Stellard | 8980dc3 | 2015-04-08 01:09:22 +0000 | [diff] [blame] | 792 | let DisableEncoding = "$dst" in { |
| 793 | def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst), |
| 794 | (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 795 | |
Tom Stellard | 8980dc3 | 2015-04-08 01:09:22 +0000 | [diff] [blame] | 796 | def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst), |
| 797 | (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">; |
| 798 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 799 | } |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 800 | |
Tom Stellard | 8980dc3 | 2015-04-08 01:09:22 +0000 | [diff] [blame] | 801 | multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m < |
| 802 | op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16), |
| 803 | " $sdst, $simm16" |
| 804 | >; |
| 805 | |
| 806 | multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins, |
| 807 | string argAsm, string asm = opName#argAsm> { |
| 808 | |
| 809 | def "" : SOPK_Pseudo <opName, outs, ins, []>; |
| 810 | |
| 811 | def _si : SOPK <outs, ins, asm, []>, |
| 812 | SOPK64e <op.SI>, |
| 813 | SIMCInstr<opName, SISubtarget.SI> { |
| 814 | let AssemblerPredicates = [isSICI]; |
| 815 | let isCodeGenOnly = 0; |
| 816 | } |
| 817 | |
| 818 | def _vi : SOPK <outs, ins, asm, []>, |
| 819 | SOPK64e <op.VI>, |
| 820 | SIMCInstr<opName, SISubtarget.VI> { |
| 821 | let AssemblerPredicates = [isVI]; |
| 822 | let isCodeGenOnly = 0; |
| 823 | } |
| 824 | } |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 825 | //===----------------------------------------------------------------------===// |
| 826 | // SMRD classes |
| 827 | //===----------------------------------------------------------------------===// |
| 828 | |
| 829 | class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 830 | SMRD <outs, ins, "", pattern>, |
| 831 | SIMCInstr<opName, SISubtarget.NONE> { |
| 832 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 833 | let isCodeGenOnly = 1; |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins, |
| 837 | string asm> : |
| 838 | SMRD <outs, ins, asm, []>, |
| 839 | SMRDe <op, imm>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 840 | SIMCInstr<opName, SISubtarget.SI> { |
| 841 | let AssemblerPredicates = [isSICI]; |
| 842 | } |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 843 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 844 | class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins, |
| 845 | string asm> : |
| 846 | SMRD <outs, ins, asm, []>, |
| 847 | SMEMe_vi <op, imm>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 848 | SIMCInstr<opName, SISubtarget.VI> { |
| 849 | let AssemblerPredicates = [isVI]; |
| 850 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 851 | |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 852 | multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins, |
| 853 | string asm, list<dag> pattern> { |
| 854 | |
| 855 | def "" : SMRD_Pseudo <opName, outs, ins, pattern>; |
| 856 | |
| 857 | def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>; |
| 858 | |
Matt Arsenault | 1991f5e | 2015-02-18 02:10:40 +0000 | [diff] [blame] | 859 | // glc is only applicable to scalar stores, which are not yet |
| 860 | // implemented. |
| 861 | let glc = 0 in { |
| 862 | def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>; |
| 863 | } |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass, |
Christian Konig | 9c7afd1 | 2013-03-18 11:33:50 +0000 | [diff] [blame] | 867 | RegisterClass dstClass> { |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 868 | defm _IMM : SMRD_m < |
| 869 | op, opName#"_IMM", 1, (outs dstClass:$dst), |
Matt Arsenault | 4d7d383 | 2014-04-15 22:32:49 +0000 | [diff] [blame] | 870 | (ins baseClass:$sbase, u32imm:$offset), |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 871 | opName#" $dst, $sbase, $offset", [] |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 872 | >; |
| 873 | |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 874 | defm _SGPR : SMRD_m < |
| 875 | op, opName#"_SGPR", 0, (outs dstClass:$dst), |
Christian Konig | 9c7afd1 | 2013-03-18 11:33:50 +0000 | [diff] [blame] | 876 | (ins baseClass:$sbase, SReg_32:$soff), |
Tom Stellard | c470c96 | 2014-10-01 14:44:42 +0000 | [diff] [blame] | 877 | opName#" $dst, $sbase, $soff", [] |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 878 | >; |
| 879 | } |
| 880 | |
| 881 | //===----------------------------------------------------------------------===// |
| 882 | // Vector ALU classes |
| 883 | //===----------------------------------------------------------------------===// |
| 884 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 885 | // This must always be right before the operand being input modified. |
| 886 | def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> { |
| 887 | let PrintMethod = "printOperandAndMods"; |
| 888 | } |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 889 | |
| 890 | def InputModsMatchClass : AsmOperandClass { |
| 891 | let Name = "RegWithInputMods"; |
| 892 | } |
| 893 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 894 | def InputModsNoDefault : Operand <i32> { |
| 895 | let PrintMethod = "printOperandAndMods"; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 896 | let ParserMatchClass = InputModsMatchClass; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 897 | } |
| 898 | |
| 899 | class getNumSrcArgs<ValueType Src1, ValueType Src2> { |
| 900 | int ret = |
| 901 | !if (!eq(Src1.Value, untyped.Value), 1, // VOP1 |
| 902 | !if (!eq(Src2.Value, untyped.Value), 2, // VOP2 |
| 903 | 3)); // VOP3 |
| 904 | } |
| 905 | |
| 906 | // Returns the register class to use for the destination of VOP[123C] |
| 907 | // instructions for the given VT. |
| 908 | class getVALUDstForVT<ValueType VT> { |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 909 | RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>, |
| 910 | !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>, |
| 911 | VOPDstOperand<SReg_64>)); // else VT == i1 |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | // Returns the register class to use for source 0 of VOP[12C] |
| 915 | // instructions for the given VT. |
| 916 | class getVOPSrc0ForVT<ValueType VT> { |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 917 | RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 918 | } |
| 919 | |
| 920 | // Returns the register class to use for source 1 of VOP[12C] for the |
| 921 | // given VT. |
| 922 | class getVOPSrc1ForVT<ValueType VT> { |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 923 | RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 924 | } |
| 925 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 926 | // Returns the register class to use for sources of VOP3 instructions for the |
| 927 | // given VT. |
| 928 | class getVOP3SrcForVT<ValueType VT> { |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 929 | RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 930 | } |
| 931 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 932 | // Returns 1 if the source arguments have modifiers, 0 if they do not. |
| 933 | class hasModifiers<ValueType SrcVT> { |
| 934 | bit ret = !if(!eq(SrcVT.Value, f32.Value), 1, |
| 935 | !if(!eq(SrcVT.Value, f64.Value), 1, 0)); |
| 936 | } |
| 937 | |
| 938 | // Returns the input arguments for VOP[12C] instructions for the given SrcVT. |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 939 | class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> { |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 940 | dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1 |
| 941 | !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2 |
| 942 | (ins))); |
| 943 | } |
| 944 | |
| 945 | // Returns the input arguments for VOP3 instructions for the given SrcVT. |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 946 | class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, |
| 947 | RegisterOperand Src2RC, int NumSrcArgs, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 948 | bit HasModifiers> { |
| 949 | |
| 950 | dag ret = |
| 951 | !if (!eq(NumSrcArgs, 1), |
| 952 | !if (!eq(HasModifiers, 1), |
| 953 | // VOP1 with modifiers |
| 954 | (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 955 | ClampMod:$clamp, omod:$omod) |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 956 | /* else */, |
| 957 | // VOP1 without modifiers |
| 958 | (ins Src0RC:$src0) |
| 959 | /* endif */ ), |
| 960 | !if (!eq(NumSrcArgs, 2), |
| 961 | !if (!eq(HasModifiers, 1), |
| 962 | // VOP 2 with modifiers |
| 963 | (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, |
| 964 | InputModsNoDefault:$src1_modifiers, Src1RC:$src1, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 965 | ClampMod:$clamp, omod:$omod) |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 966 | /* else */, |
| 967 | // VOP2 without modifiers |
| 968 | (ins Src0RC:$src0, Src1RC:$src1) |
| 969 | /* endif */ ) |
| 970 | /* NumSrcArgs == 3 */, |
| 971 | !if (!eq(HasModifiers, 1), |
| 972 | // VOP3 with modifiers |
| 973 | (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, |
| 974 | InputModsNoDefault:$src1_modifiers, Src1RC:$src1, |
| 975 | InputModsNoDefault:$src2_modifiers, Src2RC:$src2, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 976 | ClampMod:$clamp, omod:$omod) |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 977 | /* else */, |
| 978 | // VOP3 without modifiers |
| 979 | (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2) |
| 980 | /* endif */ ))); |
| 981 | } |
| 982 | |
| 983 | // Returns the assembly string for the inputs and outputs of a VOP[12C] |
| 984 | // instruction. This does not add the _e32 suffix, so it can be reused |
| 985 | // by getAsm64. |
| 986 | class getAsm32 <int NumSrcArgs> { |
| 987 | string src1 = ", $src1"; |
| 988 | string src2 = ", $src2"; |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 989 | string ret = "$dst, $src0"# |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 990 | !if(!eq(NumSrcArgs, 1), "", src1)# |
| 991 | !if(!eq(NumSrcArgs, 3), src2, ""); |
| 992 | } |
| 993 | |
| 994 | // Returns the assembly string for the inputs and outputs of a VOP3 |
| 995 | // instruction. |
| 996 | class getAsm64 <int NumSrcArgs, bit HasModifiers> { |
Matt Arsenault | 268757b | 2015-01-15 23:17:03 +0000 | [diff] [blame] | 997 | string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 998 | string src1 = !if(!eq(NumSrcArgs, 1), "", |
| 999 | !if(!eq(NumSrcArgs, 2), " $src1_modifiers", |
| 1000 | " $src1_modifiers,")); |
| 1001 | string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", ""); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1002 | string ret = |
| 1003 | !if(!eq(HasModifiers, 0), |
| 1004 | getAsm32<NumSrcArgs>.ret, |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1005 | "$dst, "#src0#src1#src2#"$clamp"#"$omod"); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1006 | } |
| 1007 | |
| 1008 | |
| 1009 | class VOPProfile <list<ValueType> _ArgVT> { |
| 1010 | |
| 1011 | field list<ValueType> ArgVT = _ArgVT; |
| 1012 | |
| 1013 | field ValueType DstVT = ArgVT[0]; |
| 1014 | field ValueType Src0VT = ArgVT[1]; |
| 1015 | field ValueType Src1VT = ArgVT[2]; |
| 1016 | field ValueType Src2VT = ArgVT[3]; |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1017 | field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret; |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 1018 | field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1019 | field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret; |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 1020 | field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret; |
| 1021 | field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret; |
| 1022 | field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1023 | |
| 1024 | field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret; |
| 1025 | field bit HasModifiers = hasModifiers<Src0VT>.ret; |
| 1026 | |
| 1027 | field dag Outs = (outs DstRC:$dst); |
| 1028 | |
| 1029 | field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret; |
| 1030 | field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, |
| 1031 | HasModifiers>.ret; |
| 1032 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1033 | field string Asm32 = getAsm32<NumSrcArgs>.ret; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1034 | field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret; |
| 1035 | } |
| 1036 | |
Tom Stellard | d1f0f02 | 2015-04-23 19:33:54 +0000 | [diff] [blame] | 1037 | // FIXME: I think these F16 profiles will need to use f16 types in order |
| 1038 | // for the instruction patterns to work. |
| 1039 | def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>; |
| 1040 | def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>; |
| 1041 | def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>; |
| 1042 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1043 | def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>; |
| 1044 | def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>; |
| 1045 | def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>; |
| 1046 | def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>; |
| 1047 | def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>; |
| 1048 | def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>; |
| 1049 | def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>; |
| 1050 | def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>; |
| 1051 | def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>; |
| 1052 | |
| 1053 | def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>; |
| 1054 | def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>; |
| 1055 | def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>; |
| 1056 | def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>; |
| 1057 | def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>; |
Marek Olsak | 11057ee | 2015-02-03 17:38:01 +0000 | [diff] [blame] | 1058 | def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1059 | def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>; |
| 1060 | def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> { |
Tom Stellard | 73ae1cb | 2014-09-23 21:26:25 +0000 | [diff] [blame] | 1061 | let Src0RC32 = VCSrc_32; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1062 | } |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1063 | |
| 1064 | def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> { |
| 1065 | let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1066 | let Asm64 = "$dst, $src0_modifiers, $src1"; |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1067 | } |
| 1068 | |
| 1069 | def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> { |
| 1070 | let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1071 | let Asm64 = "$dst, $src0_modifiers, $src1"; |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1072 | } |
| 1073 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1074 | def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>; |
Marek Olsak | 707a6d0 | 2015-02-03 21:53:01 +0000 | [diff] [blame] | 1075 | def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1076 | def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>; |
Tom Stellard | 5224df3 | 2015-03-10 16:16:44 +0000 | [diff] [blame] | 1077 | def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> { |
| 1078 | let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2); |
| 1079 | let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2); |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1080 | let Asm64 = "$dst, $src0, $src1, $src2"; |
Tom Stellard | 5224df3 | 2015-03-10 16:16:44 +0000 | [diff] [blame] | 1081 | } |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1082 | |
| 1083 | def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; |
Matt Arsenault | 70120fa | 2015-02-21 21:29:00 +0000 | [diff] [blame] | 1084 | def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> { |
| 1085 | field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2); |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1086 | field string Asm = "$dst, $src0, $vsrc1, $src2"; |
Matt Arsenault | 70120fa | 2015-02-21 21:29:00 +0000 | [diff] [blame] | 1087 | } |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1088 | def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; |
| 1089 | def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>; |
| 1090 | def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>; |
| 1091 | |
| 1092 | |
Christian Konig | f741fbf | 2013-02-26 17:52:42 +0000 | [diff] [blame] | 1093 | class VOP <string opName> { |
| 1094 | string OpName = opName; |
| 1095 | } |
| 1096 | |
Christian Konig | 3c14580 | 2013-03-27 09:12:59 +0000 | [diff] [blame] | 1097 | class VOP2_REV <string revOp, bit isOrig> { |
| 1098 | string RevOp = revOp; |
| 1099 | bit IsOrig = isOrig; |
| 1100 | } |
| 1101 | |
Matt Arsenault | 9903ccf | 2014-09-08 15:07:27 +0000 | [diff] [blame] | 1102 | class AtomicNoRet <string noRetOp, bit isRet> { |
| 1103 | string NoRetOp = noRetOp; |
| 1104 | bit IsRet = isRet; |
| 1105 | } |
| 1106 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1107 | class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : |
| 1108 | VOP1Common <outs, ins, "", pattern>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1109 | VOP <opName>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1110 | SIMCInstr <opName#"_e32", SISubtarget.NONE>, |
| 1111 | MnemonicAlias<opName#"_e32", opName> { |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1112 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1113 | let isCodeGenOnly = 1; |
Tom Stellard | c34c37a | 2015-02-18 16:08:15 +0000 | [diff] [blame] | 1114 | |
| 1115 | field bits<8> vdst; |
| 1116 | field bits<9> src0; |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1117 | } |
| 1118 | |
Tom Stellard | 23c2c3d | 2015-03-20 15:14:21 +0000 | [diff] [blame] | 1119 | class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> : |
| 1120 | VOP1<op.SI, outs, ins, asm, []>, |
Tom Stellard | d1f0f02 | 2015-04-23 19:33:54 +0000 | [diff] [blame] | 1121 | SIMCInstr <opName#"_e32", SISubtarget.SI> { |
| 1122 | let AssemblerPredicate = SIAssemblerPredicate; |
| 1123 | } |
Tom Stellard | 23c2c3d | 2015-03-20 15:14:21 +0000 | [diff] [blame] | 1124 | |
| 1125 | class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> : |
| 1126 | VOP1<op.VI, outs, ins, asm, []>, |
Tom Stellard | d1f0f02 | 2015-04-23 19:33:54 +0000 | [diff] [blame] | 1127 | SIMCInstr <opName#"_e32", SISubtarget.VI> { |
| 1128 | let AssemblerPredicates = [isVI]; |
| 1129 | } |
Tom Stellard | 23c2c3d | 2015-03-20 15:14:21 +0000 | [diff] [blame] | 1130 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1131 | multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern, |
| 1132 | string opName> { |
| 1133 | def "" : VOP1_Pseudo <outs, ins, pattern, opName>; |
| 1134 | |
Tom Stellard | 23c2c3d | 2015-03-20 15:14:21 +0000 | [diff] [blame] | 1135 | def _si : VOP1_Real_si <opName, op, outs, ins, asm>; |
| 1136 | |
| 1137 | def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1138 | } |
| 1139 | |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1140 | multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern, |
| 1141 | string opName> { |
| 1142 | def "" : VOP1_Pseudo <outs, ins, pattern, opName>; |
| 1143 | |
Tom Stellard | 23c2c3d | 2015-03-20 15:14:21 +0000 | [diff] [blame] | 1144 | def _si : VOP1_Real_si <opName, op, outs, ins, asm>; |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1145 | } |
| 1146 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1147 | class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : |
| 1148 | VOP2Common <outs, ins, "", pattern>, |
| 1149 | VOP <opName>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1150 | SIMCInstr<opName#"_e32", SISubtarget.NONE>, |
| 1151 | MnemonicAlias<opName#"_e32", opName> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1152 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1153 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1154 | } |
| 1155 | |
Tom Stellard | 3b0dab9 | 2015-03-20 15:14:23 +0000 | [diff] [blame] | 1156 | class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> : |
| 1157 | VOP2 <op.SI, outs, ins, opName#asm, []>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1158 | SIMCInstr <opName#"_e32", SISubtarget.SI> { |
| 1159 | let AssemblerPredicates = [isSICI]; |
| 1160 | } |
Tom Stellard | 3b0dab9 | 2015-03-20 15:14:23 +0000 | [diff] [blame] | 1161 | |
| 1162 | class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> : |
Marek Olsak | 2a1c9d0 | 2015-03-27 19:10:06 +0000 | [diff] [blame] | 1163 | VOP2 <op.VI, outs, ins, opName#asm, []>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1164 | SIMCInstr <opName#"_e32", SISubtarget.VI> { |
| 1165 | let AssemblerPredicates = [isVI]; |
| 1166 | } |
Tom Stellard | 3b0dab9 | 2015-03-20 15:14:23 +0000 | [diff] [blame] | 1167 | |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1168 | multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1169 | string opName, string revOp> { |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1170 | def "" : VOP2_Pseudo <outs, ins, pattern, opName>, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1171 | VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1172 | |
Tom Stellard | 3b0dab9 | 2015-03-20 15:14:23 +0000 | [diff] [blame] | 1173 | def _si : VOP2_Real_si <opName, op, outs, ins, asm>; |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1174 | } |
| 1175 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1176 | multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1177 | string opName, string revOp> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1178 | def "" : VOP2_Pseudo <outs, ins, pattern, opName>, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1179 | VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1180 | |
Tom Stellard | 3b0dab9 | 2015-03-20 15:14:23 +0000 | [diff] [blame] | 1181 | def _si : VOP2_Real_si <opName, op, outs, ins, asm>; |
| 1182 | |
| 1183 | def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>; |
| 1184 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1185 | } |
| 1186 | |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1187 | class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> { |
| 1188 | |
| 1189 | bits<2> src0_modifiers = !if(HasModifiers, ?, 0); |
| 1190 | bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0); |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1191 | bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0); |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1192 | bits<2> omod = !if(HasModifiers, ?, 0); |
| 1193 | bits<1> clamp = !if(HasModifiers, ?, 0); |
| 1194 | bits<9> src1 = !if(HasSrc1, ?, 0); |
| 1195 | bits<9> src2 = !if(HasSrc2, ?, 0); |
| 1196 | } |
| 1197 | |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1198 | class VOP3DisableModFields <bit HasSrc0Mods, |
| 1199 | bit HasSrc1Mods = 0, |
| 1200 | bit HasSrc2Mods = 0, |
| 1201 | bit HasOutputMods = 0> { |
| 1202 | bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0); |
| 1203 | bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0); |
| 1204 | bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0); |
| 1205 | bits<2> omod = !if(HasOutputMods, ?, 0); |
| 1206 | bits<1> clamp = !if(HasOutputMods, ?, 0); |
| 1207 | } |
| 1208 | |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1209 | class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : |
| 1210 | VOP3Common <outs, ins, "", pattern>, |
| 1211 | VOP <opName>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1212 | SIMCInstr<opName#"_e64", SISubtarget.NONE>, |
| 1213 | MnemonicAlias<opName#"_e64", opName> { |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1214 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1215 | let isCodeGenOnly = 1; |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1216 | } |
| 1217 | |
| 1218 | class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> : |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1219 | VOP3Common <outs, ins, asm, []>, |
| 1220 | VOP3e <op>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1221 | SIMCInstr<opName#"_e64", SISubtarget.SI> { |
| 1222 | let AssemblerPredicates = [isSICI]; |
| 1223 | } |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1224 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1225 | class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> : |
| 1226 | VOP3Common <outs, ins, asm, []>, |
| 1227 | VOP3e_vi <op>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1228 | SIMCInstr <opName#"_e64", SISubtarget.VI> { |
| 1229 | let AssemblerPredicates = [isVI]; |
| 1230 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1231 | |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1232 | class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> : |
| 1233 | VOP3Common <outs, ins, asm, []>, |
| 1234 | VOP3be <op>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1235 | SIMCInstr<opName#"_e64", SISubtarget.SI> { |
| 1236 | let AssemblerPredicates = [isSICI]; |
| 1237 | } |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1238 | |
| 1239 | class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> : |
| 1240 | VOP3Common <outs, ins, asm, []>, |
| 1241 | VOP3be_vi <op>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1242 | SIMCInstr <opName#"_e64", SISubtarget.VI> { |
| 1243 | let AssemblerPredicates = [isVI]; |
| 1244 | } |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1245 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1246 | multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1247 | string opName, int NumSrcArgs, bit HasMods = 1> { |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 1248 | |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1249 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>; |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 1250 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1251 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1252 | VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1), |
| 1253 | !if(!eq(NumSrcArgs, 2), 0, 1), |
| 1254 | HasMods>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1255 | def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, |
| 1256 | VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1), |
| 1257 | !if(!eq(NumSrcArgs, 2), 0, 1), |
| 1258 | HasMods>; |
| 1259 | } |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 1260 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1261 | // VOP3_m without source modifiers |
Matt Arsenault | 65fa1c4 | 2015-02-18 02:15:27 +0000 | [diff] [blame] | 1262 | multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1263 | string opName, int NumSrcArgs, bit HasMods = 1> { |
| 1264 | |
| 1265 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>; |
| 1266 | |
| 1267 | let src0_modifiers = 0, |
| 1268 | src1_modifiers = 0, |
Matt Arsenault | 65fa1c4 | 2015-02-18 02:15:27 +0000 | [diff] [blame] | 1269 | src2_modifiers = 0, |
| 1270 | clamp = 0, |
| 1271 | omod = 0 in { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1272 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>; |
| 1273 | def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>; |
| 1274 | } |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 1275 | } |
| 1276 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1277 | multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1278 | list<dag> pattern, string opName, bit HasMods = 1> { |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1279 | |
| 1280 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>; |
| 1281 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1282 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1283 | VOP3DisableFields<0, 0, HasMods>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1284 | |
| 1285 | def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, |
| 1286 | VOP3DisableFields<0, 0, HasMods>; |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1287 | } |
| 1288 | |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1289 | multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm, |
| 1290 | list<dag> pattern, string opName, bit HasMods = 1> { |
| 1291 | |
| 1292 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>; |
| 1293 | |
| 1294 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
| 1295 | VOP3DisableFields<0, 0, HasMods>; |
| 1296 | // No VI instruction. This class is for SI only. |
| 1297 | } |
| 1298 | |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 1299 | multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1300 | list<dag> pattern, string opName, string revOp, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1301 | bit HasMods = 1, bit UseFullOp = 0> { |
| 1302 | |
| 1303 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1304 | VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1305 | |
Marek Olsak | 191507e | 2015-02-03 17:38:12 +0000 | [diff] [blame] | 1306 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1307 | VOP3DisableFields<1, 0, HasMods>; |
| 1308 | |
Marek Olsak | 191507e | 2015-02-03 17:38:12 +0000 | [diff] [blame] | 1309 | def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1310 | VOP3DisableFields<1, 0, HasMods>; |
| 1311 | } |
| 1312 | |
Marek Olsak | 191507e | 2015-02-03 17:38:12 +0000 | [diff] [blame] | 1313 | multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm, |
| 1314 | list<dag> pattern, string opName, string revOp, |
| 1315 | bit HasMods = 1, bit UseFullOp = 0> { |
| 1316 | |
| 1317 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>, |
| 1318 | VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; |
| 1319 | |
| 1320 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
| 1321 | VOP3DisableFields<1, 0, HasMods>; |
| 1322 | |
| 1323 | // No VI instruction. This class is for SI only. |
| 1324 | } |
| 1325 | |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1326 | // XXX - Is v_div_scale_{f32|f64} only available in vop3b without |
| 1327 | // option of implicit vcc use? |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1328 | multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1329 | list<dag> pattern, string opName, string revOp, |
| 1330 | bit HasMods = 1, bit UseFullOp = 0> { |
| 1331 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>, |
| 1332 | VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; |
| 1333 | |
| 1334 | // The VOP2 variant puts the carry out into VCC, the VOP3 variant |
| 1335 | // can write it into any SGPR. We currently don't use the carry out, |
| 1336 | // so for now hardcode it to VCC as well. |
| 1337 | let sdst = SIOperand.VCC, Defs = [VCC] in { |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1338 | def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>, |
| 1339 | VOP3DisableFields<1, 0, HasMods>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1340 | |
Matt Arsenault | 692acf1 | 2015-02-14 03:02:23 +0000 | [diff] [blame] | 1341 | def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>, |
| 1342 | VOP3DisableFields<1, 0, HasMods>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1343 | } // End sdst = SIOperand.VCC, Defs = [VCC] |
| 1344 | } |
| 1345 | |
Matt Arsenault | 31ec598 | 2015-02-14 03:40:35 +0000 | [diff] [blame] | 1346 | multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm, |
| 1347 | list<dag> pattern, string opName, string revOp, |
| 1348 | bit HasMods = 1, bit UseFullOp = 0> { |
| 1349 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>; |
| 1350 | |
| 1351 | |
| 1352 | def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>, |
| 1353 | VOP3DisableFields<1, 1, HasMods>; |
| 1354 | |
| 1355 | def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>, |
| 1356 | VOP3DisableFields<1, 1, HasMods>; |
| 1357 | } |
| 1358 | |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1359 | multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1360 | list<dag> pattern, string opName, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1361 | bit HasMods, bit defExec, string revOp> { |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1362 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1363 | def "" : VOP3_Pseudo <outs, ins, pattern, opName>, |
Matt Arsenault | 88a13c6 | 2015-03-23 18:45:41 +0000 | [diff] [blame] | 1364 | VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; |
Tom Stellard | bda32c9 | 2014-07-21 17:44:29 +0000 | [diff] [blame] | 1365 | |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1366 | def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1367 | VOP3DisableFields<1, 0, HasMods> { |
| 1368 | let Defs = !if(defExec, [EXEC], []); |
| 1369 | } |
| 1370 | |
| 1371 | def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, |
| 1372 | VOP3DisableFields<1, 0, HasMods> { |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1373 | let Defs = !if(defExec, [EXEC], []); |
Christian Konig | d303996 | 2013-02-26 17:52:09 +0000 | [diff] [blame] | 1374 | } |
| 1375 | } |
| 1376 | |
Marek Olsak | 15e4a59 | 2015-01-15 18:42:55 +0000 | [diff] [blame] | 1377 | // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers. |
| 1378 | multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins, |
| 1379 | string asm, list<dag> pattern = []> { |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1380 | let isPseudo = 1, isCodeGenOnly = 1 in { |
Marek Olsak | 15e4a59 | 2015-01-15 18:42:55 +0000 | [diff] [blame] | 1381 | def "" : VOPAnyCommon <outs, ins, "", pattern>, |
| 1382 | SIMCInstr<opName, SISubtarget.NONE>; |
| 1383 | } |
| 1384 | |
| 1385 | def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1386 | SIMCInstr <opName, SISubtarget.SI> { |
| 1387 | let AssemblerPredicates = [isSICI]; |
| 1388 | } |
Marek Olsak | 15e4a59 | 2015-01-15 18:42:55 +0000 | [diff] [blame] | 1389 | |
| 1390 | def _vi : VOP3Common <outs, ins, asm, []>, |
| 1391 | VOP3e_vi <op.VI3>, |
| 1392 | VOP3DisableFields <1, 0, 0>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1393 | SIMCInstr <opName, SISubtarget.VI> { |
| 1394 | let AssemblerPredicates = [isVI]; |
| 1395 | } |
Marek Olsak | 15e4a59 | 2015-01-15 18:42:55 +0000 | [diff] [blame] | 1396 | } |
| 1397 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1398 | multiclass VOP1_Helper <vop1 op, string opName, dag outs, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1399 | dag ins32, string asm32, list<dag> pat32, |
| 1400 | dag ins64, string asm64, list<dag> pat64, |
| 1401 | bit HasMods> { |
Christian Konig | b19849a | 2013-02-21 15:17:04 +0000 | [diff] [blame] | 1402 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1403 | defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1404 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1405 | defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 1406 | } |
| 1407 | |
Tom Stellard | 94d2e99 | 2014-10-07 23:51:34 +0000 | [diff] [blame] | 1408 | multiclass VOP1Inst <vop1 op, string opName, VOPProfile P, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1409 | SDPatternOperator node = null_frag> : VOP1_Helper < |
| 1410 | op, opName, P.Outs, |
| 1411 | P.Ins32, P.Asm32, [], |
| 1412 | P.Ins64, P.Asm64, |
| 1413 | !if(P.HasModifiers, |
| 1414 | [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1415 | i32:$src0_modifiers, i1:$clamp, i32:$omod))))], |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1416 | [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), |
| 1417 | P.HasModifiers |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 1418 | >; |
Christian Konig | f5754a0 | 2013-02-21 15:17:09 +0000 | [diff] [blame] | 1419 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1420 | multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P, |
| 1421 | SDPatternOperator node = null_frag> { |
| 1422 | |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1423 | defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1424 | |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1425 | defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1426 | !if(P.HasModifiers, |
| 1427 | [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, |
| 1428 | i32:$src0_modifiers, i1:$clamp, i32:$omod))))], |
Marek Olsak | 3ecf508 | 2015-02-03 21:53:05 +0000 | [diff] [blame] | 1429 | [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), |
| 1430 | opName, P.HasModifiers>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1431 | } |
Tom Stellard | 1cfd7a5 | 2013-05-20 15:02:12 +0000 | [diff] [blame] | 1432 | |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 1433 | multiclass VOP2_Helper <vop2 op, string opName, dag outs, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1434 | dag ins32, string asm32, list<dag> pat32, |
| 1435 | dag ins64, string asm64, list<dag> pat64, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1436 | string revOp, bit HasMods> { |
| 1437 | defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1438 | |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 1439 | defm _e64 : VOP3_2_m <op, |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1440 | outs, ins64, opName#asm64, pat64, opName, revOp, HasMods |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1441 | >; |
Tom Stellard | 1cfd7a5 | 2013-05-20 15:02:12 +0000 | [diff] [blame] | 1442 | } |
| 1443 | |
Tom Stellard | bec5a24 | 2014-10-07 23:51:38 +0000 | [diff] [blame] | 1444 | multiclass VOP2Inst <vop2 op, string opName, VOPProfile P, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1445 | SDPatternOperator node = null_frag, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1446 | string revOp = opName> : VOP2_Helper < |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1447 | op, opName, P.Outs, |
| 1448 | P.Ins32, P.Asm32, [], |
| 1449 | P.Ins64, P.Asm64, |
| 1450 | !if(P.HasModifiers, |
| 1451 | [(set P.DstVT:$dst, |
| 1452 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1453 | i1:$clamp, i32:$omod)), |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1454 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], |
| 1455 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1456 | revOp, P.HasModifiers |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1457 | >; |
| 1458 | |
Marek Olsak | 191507e | 2015-02-03 17:38:12 +0000 | [diff] [blame] | 1459 | multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P, |
| 1460 | SDPatternOperator node = null_frag, |
| 1461 | string revOp = opName> { |
| 1462 | defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>; |
| 1463 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1464 | defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64, |
Marek Olsak | 191507e | 2015-02-03 17:38:12 +0000 | [diff] [blame] | 1465 | !if(P.HasModifiers, |
| 1466 | [(set P.DstVT:$dst, |
| 1467 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
| 1468 | i1:$clamp, i32:$omod)), |
| 1469 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], |
| 1470 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), |
| 1471 | opName, revOp, P.HasModifiers>; |
| 1472 | } |
| 1473 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1474 | multiclass VOP2b_Helper <vop2 op, string opName, dag outs, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1475 | dag ins32, string asm32, list<dag> pat32, |
| 1476 | dag ins64, string asm64, list<dag> pat64, |
| 1477 | string revOp, bit HasMods> { |
| 1478 | |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1479 | defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1480 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1481 | defm _e64 : VOP3b_2_m <op, |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1482 | outs, ins64, opName#asm64, pat64, opName, revOp, HasMods |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1483 | >; |
| 1484 | } |
| 1485 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1486 | multiclass VOP2bInst <vop2 op, string opName, VOPProfile P, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1487 | SDPatternOperator node = null_frag, |
| 1488 | string revOp = opName> : VOP2b_Helper < |
| 1489 | op, opName, P.Outs, |
| 1490 | P.Ins32, P.Asm32, [], |
| 1491 | P.Ins64, P.Asm64, |
| 1492 | !if(P.HasModifiers, |
| 1493 | [(set P.DstVT:$dst, |
| 1494 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1495 | i1:$clamp, i32:$omod)), |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1496 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], |
| 1497 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), |
| 1498 | revOp, P.HasModifiers |
| 1499 | >; |
| 1500 | |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1501 | // A VOP2 instruction that is VOP3-only on VI. |
| 1502 | multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs, |
| 1503 | dag ins32, string asm32, list<dag> pat32, |
| 1504 | dag ins64, string asm64, list<dag> pat64, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1505 | string revOp, bit HasMods> { |
| 1506 | defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>; |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1507 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1508 | defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1509 | revOp, HasMods>; |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1510 | } |
| 1511 | |
| 1512 | multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P, |
| 1513 | SDPatternOperator node = null_frag, |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1514 | string revOp = opName> |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1515 | : VOP2_VI3_Helper < |
| 1516 | op, opName, P.Outs, |
| 1517 | P.Ins32, P.Asm32, [], |
| 1518 | P.Ins64, P.Asm64, |
| 1519 | !if(P.HasModifiers, |
| 1520 | [(set P.DstVT:$dst, |
| 1521 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
| 1522 | i1:$clamp, i32:$omod)), |
| 1523 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], |
| 1524 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), |
Marek Olsak | 7585a29 | 2015-02-03 17:38:05 +0000 | [diff] [blame] | 1525 | revOp, P.HasModifiers |
Marek Olsak | f0b130a | 2015-01-15 18:43:06 +0000 | [diff] [blame] | 1526 | >; |
| 1527 | |
Matt Arsenault | 70120fa | 2015-02-21 21:29:00 +0000 | [diff] [blame] | 1528 | multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> { |
| 1529 | |
| 1530 | def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>; |
| 1531 | |
| 1532 | let isCodeGenOnly = 0 in { |
| 1533 | def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins, |
| 1534 | !strconcat(opName, VOP_MADK.Asm), []>, |
| 1535 | SIMCInstr <opName#"_e32", SISubtarget.SI>, |
| 1536 | VOP2_MADKe <op.SI>; |
| 1537 | |
| 1538 | def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins, |
| 1539 | !strconcat(opName, VOP_MADK.Asm), []>, |
| 1540 | SIMCInstr <opName#"_e32", SISubtarget.VI>, |
| 1541 | VOP2_MADKe <op.VI>; |
| 1542 | } // End isCodeGenOnly = 0 |
| 1543 | } |
| 1544 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1545 | class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : |
| 1546 | VOPCCommon <ins, "", pattern>, |
| 1547 | VOP <opName>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1548 | SIMCInstr<opName#"_e32", SISubtarget.NONE>, |
| 1549 | MnemonicAlias<opName#"_e32", opName> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1550 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1551 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1552 | } |
| 1553 | |
| 1554 | multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1555 | string opName, bit DefExec, string revOpName = ""> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1556 | def "" : VOPC_Pseudo <outs, ins, pattern, opName>; |
| 1557 | |
| 1558 | def _si : VOPC<op.SI, ins, asm, []>, |
| 1559 | SIMCInstr <opName#"_e32", SISubtarget.SI> { |
| 1560 | let Defs = !if(DefExec, [EXEC], []); |
Matt Arsenault | 42f39e1 | 2015-03-23 18:45:35 +0000 | [diff] [blame] | 1561 | let hasSideEffects = DefExec; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1562 | } |
| 1563 | |
| 1564 | def _vi : VOPC<op.VI, ins, asm, []>, |
| 1565 | SIMCInstr <opName#"_e32", SISubtarget.VI> { |
| 1566 | let Defs = !if(DefExec, [EXEC], []); |
Matt Arsenault | 42f39e1 | 2015-03-23 18:45:35 +0000 | [diff] [blame] | 1567 | let hasSideEffects = DefExec; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1568 | } |
| 1569 | } |
| 1570 | |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1571 | multiclass VOPC_Helper <vopc op, string opName, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1572 | dag ins32, string asm32, list<dag> pat32, |
| 1573 | dag out64, dag ins64, string asm64, list<dag> pat64, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1574 | bit HasMods, bit DefExec, string revOp> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1575 | defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1576 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1577 | defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1578 | opName, HasMods, DefExec, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1579 | } |
| 1580 | |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1581 | // Special case for class instructions which only have modifiers on |
| 1582 | // the 1st source operand. |
| 1583 | multiclass VOPC_Class_Helper <vopc op, string opName, |
| 1584 | dag ins32, string asm32, list<dag> pat32, |
| 1585 | dag out64, dag ins64, string asm64, list<dag> pat64, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1586 | bit HasMods, bit DefExec, string revOp> { |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1587 | defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>; |
| 1588 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1589 | defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1590 | opName, HasMods, DefExec, revOp>, |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1591 | VOP3DisableModFields<1, 0, 0>; |
| 1592 | } |
| 1593 | |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1594 | multiclass VOPCInst <vopc op, string opName, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1595 | VOPProfile P, PatLeaf cond = COND_NULL, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1596 | string revOp = opName, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1597 | bit DefExec = 0> : VOPC_Helper < |
| 1598 | op, opName, |
| 1599 | P.Ins32, P.Asm32, [], |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1600 | (outs VOPDstS64:$dst), P.Ins64, P.Asm64, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1601 | !if(P.HasModifiers, |
| 1602 | [(set i1:$dst, |
| 1603 | (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1604 | i1:$clamp, i32:$omod)), |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1605 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), |
| 1606 | cond))], |
| 1607 | [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1608 | P.HasModifiers, DefExec, revOp |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1609 | >; |
| 1610 | |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1611 | multiclass VOPCClassInst <vopc op, string opName, VOPProfile P, |
Matt Arsenault | 096ec1e | 2015-02-18 02:15:30 +0000 | [diff] [blame] | 1612 | bit DefExec = 0> : VOPC_Class_Helper < |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1613 | op, opName, |
| 1614 | P.Ins32, P.Asm32, [], |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1615 | (outs VOPDstS64:$dst), P.Ins64, P.Asm64, |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1616 | !if(P.HasModifiers, |
| 1617 | [(set i1:$dst, |
| 1618 | (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))], |
| 1619 | [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1620 | P.HasModifiers, DefExec, opName |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1621 | >; |
| 1622 | |
| 1623 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1624 | multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 1625 | VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1626 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1627 | multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 1628 | VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1629 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1630 | multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 1631 | VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1632 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1633 | multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 1634 | VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>; |
Christian Konig | f5754a0 | 2013-02-21 15:17:09 +0000 | [diff] [blame] | 1635 | |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 1636 | |
Tom Stellard | 0aec587 | 2014-10-07 23:51:39 +0000 | [diff] [blame] | 1637 | multiclass VOPCX <vopc op, string opName, VOPProfile P, |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1638 | PatLeaf cond = COND_NULL, |
| 1639 | string revOp = ""> |
| 1640 | : VOPCInst <op, opName, P, cond, revOp, 1>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1641 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1642 | multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> : |
| 1643 | VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1644 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1645 | multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> : |
| 1646 | VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1647 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1648 | multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> : |
| 1649 | VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1650 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 1651 | multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> : |
| 1652 | VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>; |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1653 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1654 | multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1655 | list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m < |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1656 | op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1657 | >; |
| 1658 | |
Matt Arsenault | 4831ce5 | 2015-01-06 23:00:37 +0000 | [diff] [blame] | 1659 | multiclass VOPC_CLASS_F32 <vopc op, string opName> : |
| 1660 | VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>; |
| 1661 | |
| 1662 | multiclass VOPCX_CLASS_F32 <vopc op, string opName> : |
| 1663 | VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>; |
| 1664 | |
| 1665 | multiclass VOPC_CLASS_F64 <vopc op, string opName> : |
| 1666 | VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>; |
| 1667 | |
| 1668 | multiclass VOPCX_CLASS_F64 <vopc op, string opName> : |
| 1669 | VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>; |
| 1670 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1671 | multiclass VOP3Inst <vop3 op, string opName, VOPProfile P, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1672 | SDPatternOperator node = null_frag> : VOP3_Helper < |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1673 | op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1674 | !if(!eq(P.NumSrcArgs, 3), |
| 1675 | !if(P.HasModifiers, |
| 1676 | [(set P.DstVT:$dst, |
| 1677 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1678 | i1:$clamp, i32:$omod)), |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1679 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), |
| 1680 | (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], |
| 1681 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, |
| 1682 | P.Src2VT:$src2))]), |
| 1683 | !if(!eq(P.NumSrcArgs, 2), |
| 1684 | !if(P.HasModifiers, |
| 1685 | [(set P.DstVT:$dst, |
| 1686 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1687 | i1:$clamp, i32:$omod)), |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1688 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], |
| 1689 | [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) |
| 1690 | /* P.NumSrcArgs == 1 */, |
| 1691 | !if(P.HasModifiers, |
| 1692 | [(set P.DstVT:$dst, |
| 1693 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1694 | i1:$clamp, i32:$omod))))], |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1695 | [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), |
| 1696 | P.NumSrcArgs, P.HasModifiers |
| 1697 | >; |
| 1698 | |
Matt Arsenault | 1bc9d95 | 2015-02-14 04:22:00 +0000 | [diff] [blame] | 1699 | // Special case for v_div_fmas_{f32|f64}, since it seems to be the |
| 1700 | // only VOP instruction that implicitly reads VCC. |
| 1701 | multiclass VOP3_VCC_Inst <vop3 op, string opName, |
| 1702 | VOPProfile P, |
| 1703 | SDPatternOperator node = null_frag> : VOP3_Helper < |
| 1704 | op, opName, |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 1705 | (outs P.DstRC.RegClass:$dst), |
Matt Arsenault | 1bc9d95 | 2015-02-14 04:22:00 +0000 | [diff] [blame] | 1706 | (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0, |
| 1707 | InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1, |
| 1708 | InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2, |
| 1709 | ClampMod:$clamp, |
| 1710 | omod:$omod), |
| 1711 | " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", |
| 1712 | [(set P.DstVT:$dst, |
| 1713 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
| 1714 | i1:$clamp, i32:$omod)), |
| 1715 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), |
| 1716 | (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)), |
| 1717 | (i1 VCC)))], |
| 1718 | 3, 1 |
| 1719 | >; |
| 1720 | |
Tom Stellard | b655052 | 2015-01-12 19:33:18 +0000 | [diff] [blame] | 1721 | multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1722 | string opName, list<dag> pattern> : |
Matt Arsenault | 31ec598 | 2015-02-14 03:40:35 +0000 | [diff] [blame] | 1723 | VOP3b_3_m < |
Matt Arsenault | a95f5a0 | 2014-11-04 20:29:20 +0000 | [diff] [blame] | 1724 | op, (outs vrc:$vdst, SReg_64:$sdst), |
Matt Arsenault | 272c50a | 2014-09-30 19:49:43 +0000 | [diff] [blame] | 1725 | (ins InputModsNoDefault:$src0_modifiers, arc:$src0, |
| 1726 | InputModsNoDefault:$src1_modifiers, arc:$src1, |
| 1727 | InputModsNoDefault:$src2_modifiers, arc:$src2, |
Matt Arsenault | f2676a5 | 2014-11-05 19:35:00 +0000 | [diff] [blame] | 1728 | ClampMod:$clamp, omod:$omod), |
Matt Arsenault | a95f5a0 | 2014-11-04 20:29:20 +0000 | [diff] [blame] | 1729 | opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern, |
Tom Stellard | b4a313a | 2014-08-01 00:32:39 +0000 | [diff] [blame] | 1730 | opName, opName, 1, 1 |
| 1731 | >; |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 1732 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1733 | multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> : |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 1734 | VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>; |
| 1735 | |
Tom Stellard | 845bb3c | 2014-10-07 23:51:41 +0000 | [diff] [blame] | 1736 | multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> : |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 1737 | VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>; |
Matt Arsenault | f2b0aeb | 2014-06-23 18:28:28 +0000 | [diff] [blame] | 1738 | |
Matt Arsenault | 8675db1 | 2014-08-29 16:01:14 +0000 | [diff] [blame] | 1739 | |
| 1740 | class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat< |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1741 | (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), |
Matt Arsenault | 8675db1 | 2014-08-29 16:01:14 +0000 | [diff] [blame] | 1742 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), |
| 1743 | (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))), |
| 1744 | (Inst i32:$src0_modifiers, P.Src0VT:$src0, |
| 1745 | i32:$src1_modifiers, P.Src1VT:$src1, |
| 1746 | i32:$src2_modifiers, P.Src2VT:$src2, |
Matt Arsenault | 9706978 | 2014-09-30 19:49:48 +0000 | [diff] [blame] | 1747 | i1:$clamp, |
Matt Arsenault | 8675db1 | 2014-08-29 16:01:14 +0000 | [diff] [blame] | 1748 | i32:$omod)>; |
| 1749 | |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 1750 | //===----------------------------------------------------------------------===// |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1751 | // Interpolation opcodes |
| 1752 | //===----------------------------------------------------------------------===// |
| 1753 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1754 | class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 1755 | VINTRPCommon <outs, ins, "", pattern>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1756 | SIMCInstr<opName, SISubtarget.NONE> { |
| 1757 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1758 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1759 | } |
| 1760 | |
| 1761 | class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins, |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1762 | string asm> : |
| 1763 | VINTRPCommon <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1764 | VINTRPe <op>, |
| 1765 | SIMCInstr<opName, SISubtarget.SI>; |
| 1766 | |
| 1767 | class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1768 | string asm> : |
| 1769 | VINTRPCommon <outs, ins, asm, []>, |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1770 | VINTRPe_vi <op>, |
| 1771 | SIMCInstr<opName, SISubtarget.VI>; |
| 1772 | |
| 1773 | multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm, |
Tom Stellard | 2a9d947 | 2015-05-12 15:00:46 +0000 | [diff] [blame] | 1774 | list<dag> pattern = [], |
| 1775 | string disableEncoding = "", string constraints = ""> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1776 | let DisableEncoding = disableEncoding, |
| 1777 | Constraints = constraints in { |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1778 | def "" : VINTRP_Pseudo <opName, outs, ins, pattern>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1779 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1780 | def _si : VINTRP_Real_si <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1781 | |
Marek Olsak | 367447c | 2015-01-27 17:25:11 +0000 | [diff] [blame] | 1782 | def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1783 | } |
| 1784 | } |
| 1785 | |
| 1786 | //===----------------------------------------------------------------------===// |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 1787 | // Vector I/O classes |
| 1788 | //===----------------------------------------------------------------------===// |
| 1789 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1790 | class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 1791 | DS <outs, ins, "", pattern>, |
| 1792 | SIMCInstr <opName, SISubtarget.NONE> { |
| 1793 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1794 | let isCodeGenOnly = 1; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1795 | } |
| 1796 | |
| 1797 | class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> : |
| 1798 | DS <outs, ins, asm, []>, |
| 1799 | DSe <op>, |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1800 | SIMCInstr <opName, SISubtarget.SI> { |
| 1801 | let isCodeGenOnly = 0; |
| 1802 | } |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1803 | |
| 1804 | class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> : |
| 1805 | DS <outs, ins, asm, []>, |
| 1806 | DSe_vi <op>, |
| 1807 | SIMCInstr <opName, SISubtarget.VI>; |
| 1808 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1809 | class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> : |
| 1810 | DS_Real_si <op,opName, outs, ins, asm> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1811 | |
| 1812 | // Single load interpret the 2 i8imm operands as a single i16 offset. |
| 1813 | bits<16> offset; |
| 1814 | let offset0 = offset{7-0}; |
| 1815 | let offset1 = offset{15-8}; |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1816 | let isCodeGenOnly = 0; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1817 | } |
| 1818 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1819 | class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> : |
| 1820 | DS_Real_vi <op, opName, outs, ins, asm> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1821 | |
| 1822 | // Single load interpret the 2 i8imm operands as a single i16 offset. |
| 1823 | bits<16> offset; |
| 1824 | let offset0 = offset{7-0}; |
| 1825 | let offset1 = offset{15-8}; |
| 1826 | } |
| 1827 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1828 | multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc, |
| 1829 | dag outs = (outs rc:$vdst), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1830 | dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1831 | string asm = opName#" $vdst, $addr"#"$offset$gds"> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1832 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1833 | def "" : DS_Pseudo <opName, outs, ins, []>; |
| 1834 | |
| 1835 | let data0 = 0, data1 = 0 in { |
| 1836 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1837 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1838 | } |
| 1839 | } |
| 1840 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1841 | multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc, |
| 1842 | dag outs = (outs rc:$vdst), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1843 | dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1, |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1844 | gds01:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1845 | string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1846 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1847 | def "" : DS_Pseudo <opName, outs, ins, []>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1848 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1849 | let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in { |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1850 | def _si : DS_Real_si <op, opName, outs, ins, asm>; |
| 1851 | def _vi : DS_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1852 | } |
| 1853 | } |
| 1854 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1855 | multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc, |
| 1856 | dag outs = (outs), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1857 | dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1858 | string asm = opName#" $addr, $data0"#"$offset$gds"> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1859 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1860 | def "" : DS_Pseudo <opName, outs, ins, []>, |
| 1861 | AtomicNoRet<opName, 0>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1862 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1863 | let data1 = 0, vdst = 0 in { |
| 1864 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1865 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1866 | } |
| 1867 | } |
| 1868 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1869 | multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, |
| 1870 | dag outs = (outs), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1871 | dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1872 | ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1873 | string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1874 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1875 | def "" : DS_Pseudo <opName, outs, ins, []>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1876 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 1877 | let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in { |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1878 | def _si : DS_Real_si <op, opName, outs, ins, asm>; |
| 1879 | def _vi : DS_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1880 | } |
| 1881 | } |
| 1882 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1883 | multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc, |
| 1884 | string noRetOp = "", |
| 1885 | dag outs = (outs rc:$vdst), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1886 | dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1887 | string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> { |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 1888 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1889 | def "" : DS_Pseudo <opName, outs, ins, []>, |
| 1890 | AtomicNoRet<noRetOp, 1>; |
Matt Arsenault | 9cd8c38 | 2014-03-19 22:19:39 +0000 | [diff] [blame] | 1891 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1892 | let data1 = 0 in { |
| 1893 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1894 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 0c1f881 | 2015-01-27 17:25:07 +0000 | [diff] [blame] | 1895 | } |
Matt Arsenault | 9cd8c38 | 2014-03-19 22:19:39 +0000 | [diff] [blame] | 1896 | } |
| 1897 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1898 | multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc, |
| 1899 | string noRetOp = "", dag ins, |
| 1900 | dag outs = (outs rc:$vdst), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1901 | string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> { |
Tom Stellard | 13c68ef | 2013-09-05 18:38:09 +0000 | [diff] [blame] | 1902 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1903 | def "" : DS_Pseudo <opName, outs, ins, []>, |
| 1904 | AtomicNoRet<noRetOp, 1>; |
Marek Olsak | 0c1f881 | 2015-01-27 17:25:07 +0000 | [diff] [blame] | 1905 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1906 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1907 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 0c1f881 | 2015-01-27 17:25:07 +0000 | [diff] [blame] | 1908 | } |
| 1909 | |
| 1910 | multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1911 | string noRetOp = "", RegisterClass src = rc> : |
| 1912 | DS_1A2D_RET_m <op, asm, rc, noRetOp, |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1913 | (ins VGPR_32:$addr, src:$data0, src:$data1, |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1914 | ds_offset:$offset, gds:$gds) |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1915 | >; |
Matt Arsenault | 8c6613d | 2014-06-11 18:08:39 +0000 | [diff] [blame] | 1916 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1917 | multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc, |
| 1918 | string noRetOp = opName, |
| 1919 | dag outs = (outs), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1920 | dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1921 | ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1922 | string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> { |
Marek Olsak | 0c1f881 | 2015-01-27 17:25:07 +0000 | [diff] [blame] | 1923 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1924 | def "" : DS_Pseudo <opName, outs, ins, []>, |
| 1925 | AtomicNoRet<noRetOp, 0>; |
| 1926 | |
| 1927 | let vdst = 0 in { |
| 1928 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1929 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 0c1f881 | 2015-01-27 17:25:07 +0000 | [diff] [blame] | 1930 | } |
| 1931 | } |
| 1932 | |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1933 | multiclass DS_0A_RET <bits<8> op, string opName, |
| 1934 | dag outs = (outs VGPR_32:$vdst), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1935 | dag ins = (ins ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1936 | string asm = opName#" $vdst"#"$offset"#"$gds"> { |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1937 | |
| 1938 | let mayLoad = 1, mayStore = 1 in { |
| 1939 | def "" : DS_Pseudo <opName, outs, ins, []>; |
| 1940 | |
| 1941 | let addr = 0, data0 = 0, data1 = 0 in { |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1942 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1943 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1944 | } // end addr = 0, data0 = 0, data1 = 0 |
| 1945 | } // end mayLoad = 1, mayStore = 1 |
| 1946 | } |
| 1947 | |
| 1948 | multiclass DS_1A_RET_GDS <bits<8> op, string opName, |
| 1949 | dag outs = (outs VGPR_32:$vdst), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1950 | dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1951 | string asm = opName#" $vdst, $addr"#"$offset gds"> { |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1952 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1953 | def "" : DS_Pseudo <opName, outs, ins, []>; |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1954 | |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1955 | let data0 = 0, data1 = 0, gds = 1 in { |
| 1956 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1957 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
| 1958 | } // end data0 = 0, data1 = 0, gds = 1 |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1959 | } |
| 1960 | |
| 1961 | multiclass DS_1A_GDS <bits<8> op, string opName, |
| 1962 | dag outs = (outs), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1963 | dag ins = (ins VGPR_32:$addr), |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1964 | string asm = opName#" $addr gds"> { |
| 1965 | |
| 1966 | def "" : DS_Pseudo <opName, outs, ins, []>; |
| 1967 | |
| 1968 | let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in { |
| 1969 | def _si : DS_Real_si <op, opName, outs, ins, asm>; |
| 1970 | def _vi : DS_Real_vi <op, opName, outs, ins, asm>; |
| 1971 | } // end vdst = 0, data = 0, data1 = 0, gds = 1 |
| 1972 | } |
| 1973 | |
| 1974 | multiclass DS_1A <bits<8> op, string opName, |
| 1975 | dag outs = (outs), |
Tom Stellard | 381a94a | 2015-05-12 15:00:49 +0000 | [diff] [blame^] | 1976 | dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), |
Tom Stellard | 065e3d4 | 2015-03-09 18:49:54 +0000 | [diff] [blame] | 1977 | string asm = opName#" $addr"#"$offset"#"$gds"> { |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1978 | |
| 1979 | let mayLoad = 1, mayStore = 1 in { |
| 1980 | def "" : DS_Pseudo <opName, outs, ins, []>; |
| 1981 | |
| 1982 | let vdst = 0, data0 = 0, data1 = 0 in { |
Tom Stellard | cf051f4 | 2015-03-09 18:49:45 +0000 | [diff] [blame] | 1983 | def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>; |
| 1984 | def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>; |
Tom Stellard | db4995a | 2015-03-09 16:03:45 +0000 | [diff] [blame] | 1985 | } // let vdst = 0, data0 = 0, data1 = 0 |
| 1986 | } // end mayLoad = 1, mayStore = 1 |
| 1987 | } |
| 1988 | |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 1989 | //===----------------------------------------------------------------------===// |
| 1990 | // MTBUF classes |
| 1991 | //===----------------------------------------------------------------------===// |
| 1992 | |
| 1993 | class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 1994 | MTBUF <outs, ins, "", pattern>, |
| 1995 | SIMCInstr<opName, SISubtarget.NONE> { |
| 1996 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 1997 | let isCodeGenOnly = 1; |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 1998 | } |
| 1999 | |
| 2000 | class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins, |
| 2001 | string asm> : |
| 2002 | MTBUF <outs, ins, asm, []>, |
| 2003 | MTBUFe <op>, |
| 2004 | SIMCInstr<opName, SISubtarget.SI>; |
| 2005 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2006 | class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> : |
| 2007 | MTBUF <outs, ins, asm, []>, |
| 2008 | MTBUFe_vi <op>, |
| 2009 | SIMCInstr <opName, SISubtarget.VI>; |
| 2010 | |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 2011 | multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm, |
| 2012 | list<dag> pattern> { |
| 2013 | |
| 2014 | def "" : MTBUF_Pseudo <opName, outs, ins, pattern>; |
| 2015 | |
| 2016 | def _si : MTBUF_Real_si <op, opName, outs, ins, asm>; |
| 2017 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2018 | def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>; |
| 2019 | |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 2020 | } |
| 2021 | |
| 2022 | let mayStore = 1, mayLoad = 0 in { |
| 2023 | |
| 2024 | multiclass MTBUF_Store_Helper <bits<3> op, string opName, |
| 2025 | RegisterClass regClass> : MTBUF_m < |
| 2026 | op, opName, (outs), |
| 2027 | (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 2028 | i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, |
Tom Stellard | c3d7eeb | 2014-12-19 22:15:30 +0000 | [diff] [blame] | 2029 | SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset), |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 2030 | opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt," |
| 2031 | #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", [] |
| 2032 | >; |
| 2033 | |
| 2034 | } // mayStore = 1, mayLoad = 0 |
| 2035 | |
| 2036 | let mayLoad = 1, mayStore = 0 in { |
| 2037 | |
| 2038 | multiclass MTBUF_Load_Helper <bits<3> op, string opName, |
| 2039 | RegisterClass regClass> : MTBUF_m < |
| 2040 | op, opName, (outs regClass:$dst), |
| 2041 | (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 2042 | i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc, |
Tom Stellard | c3d7eeb | 2014-12-19 22:15:30 +0000 | [diff] [blame] | 2043 | i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset), |
Tom Stellard | 0c238c2 | 2014-10-01 14:44:43 +0000 | [diff] [blame] | 2044 | opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt," |
| 2045 | #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", [] |
| 2046 | >; |
| 2047 | |
| 2048 | } // mayLoad = 1, mayStore = 0 |
| 2049 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2050 | //===----------------------------------------------------------------------===// |
| 2051 | // MUBUF classes |
| 2052 | //===----------------------------------------------------------------------===// |
| 2053 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2054 | class mubuf <bits<7> si, bits<7> vi = si> { |
| 2055 | field bits<7> SI = si; |
| 2056 | field bits<7> VI = vi; |
| 2057 | } |
| 2058 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 2059 | let isCodeGenOnly = 0 in { |
| 2060 | |
| 2061 | class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : |
| 2062 | MUBUF <outs, ins, asm, pattern>, MUBUFe <op> { |
| 2063 | let lds = 0; |
| 2064 | } |
| 2065 | |
| 2066 | } // End let isCodeGenOnly = 0 |
| 2067 | |
| 2068 | class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : |
| 2069 | MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> { |
| 2070 | let lds = 0; |
| 2071 | } |
| 2072 | |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2073 | class MUBUFAddr64Table <bit is_addr64, string suffix = ""> { |
| 2074 | bit IsAddr64 = is_addr64; |
| 2075 | string OpName = NAME # suffix; |
| 2076 | } |
| 2077 | |
| 2078 | class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : |
| 2079 | MUBUF <outs, ins, "", pattern>, |
| 2080 | SIMCInstr<opName, SISubtarget.NONE> { |
| 2081 | let isPseudo = 1; |
Tom Stellard | 1ca873b | 2015-02-18 16:08:17 +0000 | [diff] [blame] | 2082 | let isCodeGenOnly = 1; |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2083 | |
| 2084 | // dummy fields, so that we can use let statements around multiclasses |
| 2085 | bits<1> offen; |
| 2086 | bits<1> idxen; |
| 2087 | bits<8> vaddr; |
| 2088 | bits<1> glc; |
| 2089 | bits<1> slc; |
| 2090 | bits<1> tfe; |
| 2091 | bits<8> soffset; |
| 2092 | } |
| 2093 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2094 | class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2095 | string asm> : |
| 2096 | MUBUF <outs, ins, asm, []>, |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2097 | MUBUFe <op.SI>, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2098 | SIMCInstr<opName, SISubtarget.SI> { |
| 2099 | let lds = 0; |
| 2100 | } |
| 2101 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2102 | class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2103 | string asm> : |
| 2104 | MUBUF <outs, ins, asm, []>, |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2105 | MUBUFe_vi <op.VI>, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2106 | SIMCInstr<opName, SISubtarget.VI> { |
| 2107 | let lds = 0; |
| 2108 | } |
| 2109 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2110 | multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2111 | list<dag> pattern> { |
| 2112 | |
| 2113 | def "" : MUBUF_Pseudo <opName, outs, ins, pattern>, |
| 2114 | MUBUFAddr64Table <0>; |
| 2115 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 2116 | let addr64 = 0, isCodeGenOnly = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2117 | def _si : MUBUF_Real_si <op, opName, outs, ins, asm>; |
| 2118 | } |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2119 | |
| 2120 | def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>; |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2121 | } |
| 2122 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2123 | multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2124 | dag ins, string asm, list<dag> pattern> { |
| 2125 | |
| 2126 | def "" : MUBUF_Pseudo <opName, outs, ins, pattern>, |
| 2127 | MUBUFAddr64Table <1>; |
| 2128 | |
Tom Stellard | d7e6f13 | 2015-04-08 01:09:26 +0000 | [diff] [blame] | 2129 | let addr64 = 1, isCodeGenOnly = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2130 | def _si : MUBUF_Real_si <op, opName, outs, ins, asm>; |
| 2131 | } |
| 2132 | |
| 2133 | // There is no VI version. If the pseudo is selected, it should be lowered |
| 2134 | // for VI appropriately. |
| 2135 | } |
| 2136 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2137 | multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins, |
| 2138 | string asm, list<dag> pattern, bit is_return> { |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2139 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2140 | def "" : MUBUF_Pseudo <opName, outs, ins, pattern>, |
| 2141 | MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>, |
| 2142 | AtomicNoRet<NAME#"_OFFSET", is_return>; |
| 2143 | |
| 2144 | let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in { |
| 2145 | let addr64 = 0 in { |
| 2146 | def _si : MUBUF_Real_si <op, opName, outs, ins, asm>; |
| 2147 | } |
| 2148 | |
| 2149 | def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>; |
| 2150 | } |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2151 | } |
| 2152 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2153 | multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins, |
| 2154 | string asm, list<dag> pattern, bit is_return> { |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2155 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2156 | def "" : MUBUF_Pseudo <opName, outs, ins, pattern>, |
| 2157 | MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>, |
| 2158 | AtomicNoRet<NAME#"_ADDR64", is_return>; |
| 2159 | |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 2160 | let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in { |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2161 | def _si : MUBUF_Real_si <op, opName, outs, ins, asm>; |
| 2162 | } |
| 2163 | |
| 2164 | // There is no VI version. If the pseudo is selected, it should be lowered |
| 2165 | // for VI appropriately. |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2166 | } |
| 2167 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2168 | multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2169 | ValueType vt, SDPatternOperator atomic> { |
| 2170 | |
| 2171 | let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in { |
| 2172 | |
| 2173 | // No return variants |
| 2174 | let glc = 0 in { |
| 2175 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2176 | defm _ADDR64 : MUBUFAtomicAddr64_m < |
| 2177 | op, name#"_addr64", (outs), |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2178 | (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2179 | SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), |
Matt Arsenault | 2ad8bab | 2015-02-18 02:04:35 +0000 | [diff] [blame] | 2180 | name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0 |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2181 | >; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2182 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2183 | defm _OFFSET : MUBUFAtomicOffset_m < |
| 2184 | op, name#"_offset", (outs), |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2185 | (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset, |
| 2186 | slc:$slc), |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2187 | name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0 |
| 2188 | >; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2189 | } // glc = 0 |
| 2190 | |
| 2191 | // Variant that return values |
| 2192 | let glc = 1, Constraints = "$vdata = $vdata_in", |
| 2193 | DisableEncoding = "$vdata_in" in { |
| 2194 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2195 | defm _RTN_ADDR64 : MUBUFAtomicAddr64_m < |
| 2196 | op, name#"_rtn_addr64", (outs rc:$vdata), |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2197 | (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr, |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2198 | SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 2199 | name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc", |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2200 | [(set vt:$vdata, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 2201 | (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, |
| 2202 | i16:$offset, i1:$slc), vt:$vdata_in))], 1 |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2203 | >; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2204 | |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2205 | defm _RTN_OFFSET : MUBUFAtomicOffset_m < |
| 2206 | op, name#"_rtn_offset", (outs rc:$vdata), |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2207 | (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset, |
| 2208 | mbuf_offset:$offset, slc:$slc), |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2209 | name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc", |
| 2210 | [(set vt:$vdata, |
| 2211 | (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, |
Marek Olsak | 19d9e1f | 2015-01-27 17:25:02 +0000 | [diff] [blame] | 2212 | i1:$slc), vt:$vdata_in))], 1 |
| 2213 | >; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2214 | |
| 2215 | } // glc = 1 |
| 2216 | |
| 2217 | } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1 |
| 2218 | } |
| 2219 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2220 | multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, |
Tom Stellard | 7c1838d | 2014-07-02 20:53:56 +0000 | [diff] [blame] | 2221 | ValueType load_vt = i32, |
| 2222 | SDPatternOperator ld = null_frag> { |
Tom Stellard | f1ee716 | 2013-05-20 15:02:31 +0000 | [diff] [blame] | 2223 | |
Tom Stellard | 3e41dc4 | 2014-12-09 00:03:54 +0000 | [diff] [blame] | 2224 | let mayLoad = 1, mayStore = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2225 | let offen = 0, idxen = 0, vaddr = 0 in { |
| 2226 | defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata), |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2227 | (ins SReg_128:$srsrc, SCSrc_32:$soffset, |
| 2228 | mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2229 | name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", |
| 2230 | [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc, |
| 2231 | i32:$soffset, i16:$offset, |
| 2232 | i1:$glc, i1:$slc, i1:$tfe)))]>; |
Michel Danzer | 1373622 | 2014-01-27 07:20:51 +0000 | [diff] [blame] | 2233 | } |
| 2234 | |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2235 | let offen = 1, idxen = 0 in { |
| 2236 | defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2237 | (ins VGPR_32:$vaddr, SReg_128:$srsrc, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2238 | SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, |
| 2239 | tfe:$tfe), |
| 2240 | name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; |
| 2241 | } |
| 2242 | |
| 2243 | let offen = 0, idxen = 1 in { |
| 2244 | defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2245 | (ins VGPR_32:$vaddr, SReg_128:$srsrc, |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2246 | SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2247 | slc:$slc, tfe:$tfe), |
| 2248 | name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; |
| 2249 | } |
| 2250 | |
| 2251 | let offen = 1, idxen = 1 in { |
| 2252 | defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2253 | (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2254 | mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), |
Matt Arsenault | caa1288 | 2015-02-18 02:04:38 +0000 | [diff] [blame] | 2255 | name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2256 | } |
| 2257 | |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2258 | let offen = 0, idxen = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2259 | defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2260 | (ins VReg_64:$vaddr, SReg_128:$srsrc, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2261 | SCSrc_32:$soffset, mbuf_offset:$offset, |
| 2262 | glc:$glc, slc:$slc, tfe:$tfe), |
| 2263 | name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"# |
| 2264 | "$glc"#"$slc"#"$tfe", |
Tom Stellard | 7c1838d | 2014-07-02 20:53:56 +0000 | [diff] [blame] | 2265 | [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 2266 | i64:$vaddr, i32:$soffset, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2267 | i16:$offset, i1:$glc, i1:$slc, |
| 2268 | i1:$tfe)))]>; |
Michel Danzer | 1373622 | 2014-01-27 07:20:51 +0000 | [diff] [blame] | 2269 | } |
Tom Stellard | f1ee716 | 2013-05-20 15:02:31 +0000 | [diff] [blame] | 2270 | } |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2271 | } |
| 2272 | |
Marek Olsak | ee98b11 | 2015-01-27 17:24:58 +0000 | [diff] [blame] | 2273 | multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass, |
Tom Stellard | aec94b3 | 2015-02-27 14:59:46 +0000 | [diff] [blame] | 2274 | ValueType store_vt = i32, SDPatternOperator st = null_frag> { |
Tom Stellard | 42fb60e | 2015-01-14 15:42:31 +0000 | [diff] [blame] | 2275 | let mayLoad = 0, mayStore = 1 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2276 | defm : MUBUF_m <op, name, (outs), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2277 | (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2278 | mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc, |
| 2279 | tfe:$tfe), |
| 2280 | name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"# |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2281 | "$glc"#"$slc"#"$tfe", []>; |
Tom Stellard | ddea486 | 2014-08-11 22:18:14 +0000 | [diff] [blame] | 2282 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 2283 | let offen = 0, idxen = 0, vaddr = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2284 | defm _OFFSET : MUBUF_m <op, name#"_offset",(outs), |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2285 | (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, |
| 2286 | mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2287 | name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", |
| 2288 | [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, |
| 2289 | i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 2290 | } // offen = 0, idxen = 0, vaddr = 0 |
| 2291 | |
Tom Stellard | ddea486 | 2014-08-11 22:18:14 +0000 | [diff] [blame] | 2292 | let offen = 1, idxen = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2293 | defm _OFFEN : MUBUF_m <op, name#"_offen", (outs), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2294 | (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, |
Tom Stellard | 49282c9 | 2015-02-27 14:59:44 +0000 | [diff] [blame] | 2295 | SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, |
| 2296 | slc:$slc, tfe:$tfe), |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2297 | name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"# |
| 2298 | "$glc"#"$slc"#"$tfe", []>; |
Tom Stellard | ddea486 | 2014-08-11 22:18:14 +0000 | [diff] [blame] | 2299 | } // end offen = 1, idxen = 0 |
| 2300 | |
Tom Stellard | a14b011 | 2015-03-10 16:16:51 +0000 | [diff] [blame] | 2301 | let offen = 0, idxen = 1 in { |
| 2302 | defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs), |
| 2303 | (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, |
| 2304 | SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, |
| 2305 | slc:$slc, tfe:$tfe), |
| 2306 | name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; |
| 2307 | } |
| 2308 | |
| 2309 | let offen = 1, idxen = 1 in { |
| 2310 | defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs), |
| 2311 | (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, |
| 2312 | mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), |
| 2313 | name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; |
| 2314 | } |
| 2315 | |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2316 | let offen = 0, idxen = 0 in { |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2317 | defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs), |
Tom Stellard | c229baa | 2015-03-10 16:16:49 +0000 | [diff] [blame] | 2318 | (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, |
| 2319 | SCSrc_32:$soffset, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2320 | mbuf_offset:$offset, glc:$glc, slc:$slc, |
| 2321 | tfe:$tfe), |
| 2322 | name#" $vdata, $vaddr, $srsrc, $soffset addr64"# |
| 2323 | "$offset"#"$glc"#"$slc"#"$tfe", |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2324 | [(st store_vt:$vdata, |
Tom Stellard | c53861a | 2015-02-11 00:34:32 +0000 | [diff] [blame] | 2325 | (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, |
Tom Stellard | 1f9939f | 2015-02-27 14:59:41 +0000 | [diff] [blame] | 2326 | i32:$soffset, i16:$offset, |
| 2327 | i1:$glc, i1:$slc, i1:$tfe))]>; |
Marek Olsak | 7ef6db4 | 2015-01-27 17:24:54 +0000 | [diff] [blame] | 2328 | } |
| 2329 | } // End mayLoad = 0, mayStore = 1 |
Tom Stellard | 754f80f | 2013-04-05 23:31:51 +0000 | [diff] [blame] | 2330 | } |
| 2331 | |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 2332 | class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : |
Matt Arsenault | e6c5241 | 2015-02-18 02:10:37 +0000 | [diff] [blame] | 2333 | FLAT <op, (outs regClass:$vdst), |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 2334 | (ins VReg_64:$addr), |
Matt Arsenault | e6c5241 | 2015-02-18 02:10:37 +0000 | [diff] [blame] | 2335 | asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> { |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 2336 | let glc = 0; |
| 2337 | let slc = 0; |
| 2338 | let tfe = 0; |
Matt Arsenault | e6c5241 | 2015-02-18 02:10:37 +0000 | [diff] [blame] | 2339 | let data = 0; |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 2340 | let mayLoad = 1; |
| 2341 | } |
| 2342 | |
| 2343 | class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> : |
| 2344 | FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr), |
| 2345 | name#" $data, $addr, [M0, FLAT_SCRATCH]", |
| 2346 | []> { |
| 2347 | |
| 2348 | let mayLoad = 0; |
| 2349 | let mayStore = 1; |
| 2350 | |
| 2351 | // Encoding |
| 2352 | let glc = 0; |
| 2353 | let slc = 0; |
| 2354 | let tfe = 0; |
Matt Arsenault | e6c5241 | 2015-02-18 02:10:37 +0000 | [diff] [blame] | 2355 | let vdst = 0; |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 2356 | } |
| 2357 | |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2358 | class MIMG_Mask <string op, int channels> { |
| 2359 | string Op = op; |
| 2360 | int Channels = channels; |
| 2361 | } |
| 2362 | |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2363 | class MIMG_NoSampler_Helper <bits<7> op, string asm, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2364 | RegisterClass dst_rc, |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2365 | RegisterClass src_rc> : MIMG < |
Tom Stellard | 353b336 | 2013-05-06 23:02:12 +0000 | [diff] [blame] | 2366 | op, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2367 | (outs dst_rc:$vdata), |
Tom Stellard | 353b336 | 2013-05-06 23:02:12 +0000 | [diff] [blame] | 2368 | (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2369 | i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, |
Tom Stellard | 353b336 | 2013-05-06 23:02:12 +0000 | [diff] [blame] | 2370 | SReg_256:$srsrc), |
| 2371 | asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," |
| 2372 | #" $tfe, $lwe, $slc, $vaddr, $srsrc", |
| 2373 | []> { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 2374 | let ssamp = 0; |
Tom Stellard | 353b336 | 2013-05-06 23:02:12 +0000 | [diff] [blame] | 2375 | let mayLoad = 1; |
| 2376 | let mayStore = 0; |
| 2377 | let hasPostISelHook = 1; |
| 2378 | } |
| 2379 | |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2380 | multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm, |
| 2381 | RegisterClass dst_rc, |
| 2382 | int channels> { |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 2383 | def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2384 | MIMG_Mask<asm#"_V1", channels>; |
| 2385 | def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>, |
| 2386 | MIMG_Mask<asm#"_V2", channels>; |
| 2387 | def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>, |
| 2388 | MIMG_Mask<asm#"_V4", channels>; |
| 2389 | } |
| 2390 | |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2391 | multiclass MIMG_NoSampler <bits<7> op, string asm> { |
Tom Stellard | 45c0b3a | 2015-01-07 20:59:25 +0000 | [diff] [blame] | 2392 | defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2393 | defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>; |
| 2394 | defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>; |
| 2395 | defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>; |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2396 | } |
| 2397 | |
| 2398 | class MIMG_Sampler_Helper <bits<7> op, string asm, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2399 | RegisterClass dst_rc, |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2400 | RegisterClass src_rc, int wqm> : MIMG < |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 2401 | op, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2402 | (outs dst_rc:$vdata), |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 2403 | (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2404 | i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, |
Christian Konig | 8465296 | 2013-03-01 09:46:17 +0000 | [diff] [blame] | 2405 | SReg_256:$srsrc, SReg_128:$ssamp), |
Christian Konig | 08e768b | 2013-02-21 15:17:17 +0000 | [diff] [blame] | 2406 | asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," |
| 2407 | #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp", |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 2408 | []> { |
| 2409 | let mayLoad = 1; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2410 | let mayStore = 0; |
Christian Konig | 8b1ed28 | 2013-04-10 08:39:16 +0000 | [diff] [blame] | 2411 | let hasPostISelHook = 1; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2412 | let WQM = wqm; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2413 | } |
| 2414 | |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2415 | multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, |
| 2416 | RegisterClass dst_rc, |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2417 | int channels, int wqm> { |
| 2418 | def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2419 | MIMG_Mask<asm#"_V1", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2420 | def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2421 | MIMG_Mask<asm#"_V2", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2422 | def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2423 | MIMG_Mask<asm#"_V4", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2424 | def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2425 | MIMG_Mask<asm#"_V8", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2426 | def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>, |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2427 | MIMG_Mask<asm#"_V16", channels>; |
| 2428 | } |
| 2429 | |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2430 | multiclass MIMG_Sampler <bits<7> op, string asm> { |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2431 | defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>; |
| 2432 | defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>; |
| 2433 | defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>; |
| 2434 | defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>; |
| 2435 | } |
| 2436 | |
| 2437 | multiclass MIMG_Sampler_WQM <bits<7> op, string asm> { |
| 2438 | defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>; |
| 2439 | defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>; |
| 2440 | defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>; |
| 2441 | defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>; |
Tom Stellard | 16a9a20 | 2013-08-14 23:24:17 +0000 | [diff] [blame] | 2442 | } |
| 2443 | |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2444 | class MIMG_Gather_Helper <bits<7> op, string asm, |
| 2445 | RegisterClass dst_rc, |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2446 | RegisterClass src_rc, int wqm> : MIMG < |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2447 | op, |
| 2448 | (outs dst_rc:$vdata), |
| 2449 | (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, |
| 2450 | i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, |
| 2451 | SReg_256:$srsrc, SReg_128:$ssamp), |
| 2452 | asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," |
| 2453 | #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp", |
| 2454 | []> { |
| 2455 | let mayLoad = 1; |
| 2456 | let mayStore = 0; |
| 2457 | |
| 2458 | // DMASK was repurposed for GATHER4. 4 components are always |
| 2459 | // returned and DMASK works like a swizzle - it selects |
| 2460 | // the component to fetch. The only useful DMASK values are |
| 2461 | // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns |
| 2462 | // (red,red,red,red) etc.) The ISA document doesn't mention |
| 2463 | // this. |
| 2464 | // Therefore, disable all code which updates DMASK by setting these two: |
| 2465 | let MIMG = 0; |
| 2466 | let hasPostISelHook = 0; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2467 | let WQM = wqm; |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2468 | } |
| 2469 | |
| 2470 | multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm, |
| 2471 | RegisterClass dst_rc, |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2472 | int channels, int wqm> { |
| 2473 | def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>, |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2474 | MIMG_Mask<asm#"_V1", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2475 | def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>, |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2476 | MIMG_Mask<asm#"_V2", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2477 | def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>, |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2478 | MIMG_Mask<asm#"_V4", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2479 | def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>, |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2480 | MIMG_Mask<asm#"_V8", channels>; |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2481 | def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>, |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2482 | MIMG_Mask<asm#"_V16", channels>; |
| 2483 | } |
| 2484 | |
| 2485 | multiclass MIMG_Gather <bits<7> op, string asm> { |
Michel Danzer | 494391b | 2015-02-06 02:51:20 +0000 | [diff] [blame] | 2486 | defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>; |
| 2487 | defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>; |
| 2488 | defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>; |
| 2489 | defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>; |
| 2490 | } |
| 2491 | |
| 2492 | multiclass MIMG_Gather_WQM <bits<7> op, string asm> { |
| 2493 | defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>; |
| 2494 | defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>; |
| 2495 | defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>; |
| 2496 | defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>; |
Marek Olsak | 51b8e7b | 2014-06-18 22:00:29 +0000 | [diff] [blame] | 2497 | } |
| 2498 | |
Christian Konig | f741fbf | 2013-02-26 17:52:42 +0000 | [diff] [blame] | 2499 | //===----------------------------------------------------------------------===// |
| 2500 | // Vector instruction mappings |
| 2501 | //===----------------------------------------------------------------------===// |
| 2502 | |
| 2503 | // Maps an opcode in e32 form to its e64 equivalent |
| 2504 | def getVOPe64 : InstrMapping { |
| 2505 | let FilterClass = "VOP"; |
| 2506 | let RowFields = ["OpName"]; |
| 2507 | let ColFields = ["Size"]; |
| 2508 | let KeyCol = ["4"]; |
| 2509 | let ValueCols = [["8"]]; |
| 2510 | } |
| 2511 | |
Tom Stellard | 1aaad69 | 2014-07-21 16:55:33 +0000 | [diff] [blame] | 2512 | // Maps an opcode in e64 form to its e32 equivalent |
| 2513 | def getVOPe32 : InstrMapping { |
| 2514 | let FilterClass = "VOP"; |
| 2515 | let RowFields = ["OpName"]; |
| 2516 | let ColFields = ["Size"]; |
| 2517 | let KeyCol = ["8"]; |
| 2518 | let ValueCols = [["4"]]; |
| 2519 | } |
| 2520 | |
Tom Stellard | 682bfbc | 2013-10-10 17:11:24 +0000 | [diff] [blame] | 2521 | def getMaskedMIMGOp : InstrMapping { |
| 2522 | let FilterClass = "MIMG_Mask"; |
| 2523 | let RowFields = ["Op"]; |
| 2524 | let ColFields = ["Channels"]; |
| 2525 | let KeyCol = ["4"]; |
| 2526 | let ValueCols = [["1"], ["2"], ["3"] ]; |
| 2527 | } |
| 2528 | |
Christian Konig | 3c14580 | 2013-03-27 09:12:59 +0000 | [diff] [blame] | 2529 | // Maps an commuted opcode to its original version |
| 2530 | def getCommuteOrig : InstrMapping { |
| 2531 | let FilterClass = "VOP2_REV"; |
| 2532 | let RowFields = ["RevOp"]; |
| 2533 | let ColFields = ["IsOrig"]; |
| 2534 | let KeyCol = ["0"]; |
| 2535 | let ValueCols = [["1"]]; |
| 2536 | } |
| 2537 | |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 2538 | // Maps an original opcode to its commuted version |
| 2539 | def getCommuteRev : InstrMapping { |
| 2540 | let FilterClass = "VOP2_REV"; |
| 2541 | let RowFields = ["RevOp"]; |
| 2542 | let ColFields = ["IsOrig"]; |
| 2543 | let KeyCol = ["1"]; |
| 2544 | let ValueCols = [["0"]]; |
| 2545 | } |
| 2546 | |
| 2547 | def getCommuteCmpOrig : InstrMapping { |
Matt Arsenault | 88a13c6 | 2015-03-23 18:45:41 +0000 | [diff] [blame] | 2548 | let FilterClass = "VOP2_REV"; |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 2549 | let RowFields = ["RevOp"]; |
| 2550 | let ColFields = ["IsOrig"]; |
| 2551 | let KeyCol = ["0"]; |
| 2552 | let ValueCols = [["1"]]; |
| 2553 | } |
| 2554 | |
| 2555 | // Maps an original opcode to its commuted version |
| 2556 | def getCommuteCmpRev : InstrMapping { |
Matt Arsenault | 88a13c6 | 2015-03-23 18:45:41 +0000 | [diff] [blame] | 2557 | let FilterClass = "VOP2_REV"; |
Matt Arsenault | f5b2cd8 | 2015-03-23 18:45:30 +0000 | [diff] [blame] | 2558 | let RowFields = ["RevOp"]; |
| 2559 | let ColFields = ["IsOrig"]; |
| 2560 | let KeyCol = ["1"]; |
| 2561 | let ValueCols = [["0"]]; |
| 2562 | } |
| 2563 | |
| 2564 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2565 | def getMCOpcodeGen : InstrMapping { |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 2566 | let FilterClass = "SIMCInstr"; |
| 2567 | let RowFields = ["PseudoInstr"]; |
| 2568 | let ColFields = ["Subtarget"]; |
| 2569 | let KeyCol = [!cast<string>(SISubtarget.NONE)]; |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2570 | let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]]; |
Tom Stellard | c721a23 | 2014-05-16 20:56:47 +0000 | [diff] [blame] | 2571 | } |
| 2572 | |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 2573 | def getAddr64Inst : InstrMapping { |
| 2574 | let FilterClass = "MUBUFAddr64Table"; |
Tom Stellard | 7980fc8 | 2014-09-25 18:30:26 +0000 | [diff] [blame] | 2575 | let RowFields = ["OpName"]; |
Tom Stellard | 155bbb7 | 2014-08-11 22:18:17 +0000 | [diff] [blame] | 2576 | let ColFields = ["IsAddr64"]; |
| 2577 | let KeyCol = ["0"]; |
| 2578 | let ValueCols = [["1"]]; |
| 2579 | } |
| 2580 | |
Matt Arsenault | 9903ccf | 2014-09-08 15:07:27 +0000 | [diff] [blame] | 2581 | // Maps an atomic opcode to its version with a return value. |
| 2582 | def getAtomicRetOp : InstrMapping { |
| 2583 | let FilterClass = "AtomicNoRet"; |
| 2584 | let RowFields = ["NoRetOp"]; |
| 2585 | let ColFields = ["IsRet"]; |
| 2586 | let KeyCol = ["0"]; |
| 2587 | let ValueCols = [["1"]]; |
| 2588 | } |
| 2589 | |
| 2590 | // Maps an atomic opcode to its returnless version. |
| 2591 | def getAtomicNoRetOp : InstrMapping { |
| 2592 | let FilterClass = "AtomicNoRet"; |
| 2593 | let RowFields = ["NoRetOp"]; |
| 2594 | let ColFields = ["IsRet"]; |
| 2595 | let KeyCol = ["1"]; |
| 2596 | let ValueCols = [["0"]]; |
| 2597 | } |
| 2598 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2599 | include "SIInstructions.td" |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 2600 | include "CIInstructions.td" |
| 2601 | include "VIInstructions.td" |