blob: c154bb660ab42989720b4052fefe8c9f4bca4fe9 [file] [log] [blame]
Christian Konig72d5d5c2013-02-21 15:16:44 +00001//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Tom Stellardd7e6f132015-04-08 01:09:26 +00009def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
Tom Stellard75aadc22012-12-11 21:25:42 +000014
Tom Stellardd1f0f022015-04-23 19:33:54 +000015def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
16
Tom Stellard94d2e992014-10-07 23:51:34 +000017class vop {
18 field bits<9> SI3;
Marek Olsak5df00d62014-12-07 12:18:57 +000019 field bits<10> VI3;
Tom Stellard94d2e992014-10-07 23:51:34 +000020}
21
Marek Olsak5df00d62014-12-07 12:18:57 +000022class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
Tom Stellard0aec5872014-10-07 23:51:39 +000023 field bits<8> SI = si;
Marek Olsak5df00d62014-12-07 12:18:57 +000024 field bits<8> VI = vi;
Tom Stellard0aec5872014-10-07 23:51:39 +000025
Marek Olsak5df00d62014-12-07 12:18:57 +000026 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
Tom Stellard0aec5872014-10-07 23:51:39 +000028}
29
Marek Olsak5df00d62014-12-07 12:18:57 +000030class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
Tom Stellard94d2e992014-10-07 23:51:34 +000033
Marek Olsak5df00d62014-12-07 12:18:57 +000034 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
Tom Stellard94d2e992014-10-07 23:51:34 +000036}
37
Marek Olsak5df00d62014-12-07 12:18:57 +000038class vop2 <bits<6> si, bits<6> vi = si> : vop {
Tom Stellardbec5a242014-10-07 23:51:38 +000039 field bits<6> SI = si;
Marek Olsak5df00d62014-12-07 12:18:57 +000040 field bits<6> VI = vi;
Tom Stellardbec5a242014-10-07 23:51:38 +000041
Marek Olsak5df00d62014-12-07 12:18:57 +000042 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
Tom Stellardbec5a242014-10-07 23:51:38 +000044}
45
Marek Olsakf0b130a2015-01-15 18:43:06 +000046// Specify a VOP2 opcode for SI and VOP3 opcode for VI
47// that doesn't have VOP2 encoding on VI
48class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
49 let VI3 = vi;
50}
51
Marek Olsak5df00d62014-12-07 12:18:57 +000052class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
53 let SI3 = si;
54 let VI3 = vi;
55}
56
57class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
60}
61
62class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
65}
66
67class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
Tom Stellard845bb3c2014-10-07 23:51:41 +000070}
71
Tom Stellardc721a232014-05-16 20:56:47 +000072// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
Marek Olsaka93603d2015-01-15 18:42:51 +000073// in AMDGPUInstrInfo.cpp
Tom Stellardc721a232014-05-16 20:56:47 +000074def SISubtarget {
75 int NONE = -1;
76 int SI = 0;
Marek Olsak5df00d62014-12-07 12:18:57 +000077 int VI = 1;
Tom Stellardc721a232014-05-16 20:56:47 +000078}
79
Tom Stellard75aadc22012-12-11 21:25:42 +000080//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +000081// SI DAG Nodes
82//===----------------------------------------------------------------------===//
83
Tom Stellard9fa17912013-08-14 23:24:45 +000084def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
Tom Stellard868fd922014-04-17 21:00:11 +000085 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
Tom Stellard9fa17912013-08-14 23:24:45 +000086 [SDNPMayLoad, SDNPMemOperand]
87>;
88
Tom Stellardafcf12f2013-09-12 02:55:14 +000089def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
90 SDTypeProfile<0, 13,
Tom Stellard868fd922014-04-17 21:00:11 +000091 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
Tom Stellardafcf12f2013-09-12 02:55:14 +000092 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
104 ]>,
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
106>;
107
Tom Stellard9fa17912013-08-14 23:24:45 +0000108def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
Tom Stellard868fd922014-04-17 21:00:11 +0000109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
Tom Stellard9fa17912013-08-14 23:24:45 +0000110 SDTCisVT<3, i32>]>
111>;
112
113class SDSample<string opcode> : SDNode <opcode,
Tom Stellard67850652013-08-14 23:24:53 +0000114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
Tom Stellard868fd922014-04-17 21:00:11 +0000115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
Tom Stellard9fa17912013-08-14 23:24:45 +0000116>;
117
118def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
122
Tom Stellard067c8152014-07-21 14:01:14 +0000123def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
125>;
126
Tom Stellard381a94a2015-05-12 15:00:49 +0000127//===----------------------------------------------------------------------===//
128// SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
129// to be glued to the memory instructions.
130//===----------------------------------------------------------------------===//
131
132def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
134>;
135
136def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
137 return isLocalLoad(cast<LoadSDNode>(N));
138}]>;
139
140def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
142 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
143}]>;
144
145def si_load_local_align8 : Aligned8Bytes <
146 (ops node:$ptr), (si_load_local node:$ptr)
147>;
148
149def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
150 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
151}]>;
152def si_az_extload_local : AZExtLoadBase <si_ld_local>;
153
154multiclass SIExtLoadLocal <PatFrag ld_node> {
155
156 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
157 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
158 >;
159
160 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
161 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
162 >;
163}
164
165defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
166defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
167
168def SIst_local : SDNode <"ISD::STORE", SDTStore,
169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
170>;
171
172def si_st_local : PatFrag <
173 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
174 return isLocalStore(cast<StoreSDNode>(N));
175}]>;
176
177def si_store_local : PatFrag <
178 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
180 !cast<StoreSDNode>(N)->isTruncatingStore();
181}]>;
182
183def si_store_local_align8 : Aligned8Bytes <
184 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
185>;
186
187def si_truncstore_local : PatFrag <
188 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
189 return cast<StoreSDNode>(N)->isTruncatingStore();
190}]>;
191
192def si_truncstore_local_i8 : PatFrag <
193 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
194 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
195}]>;
196
197def si_truncstore_local_i16 : PatFrag <
198 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
200}]>;
201
202multiclass SIAtomicM0Glue2 <string op_name> {
203
204 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
205 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
206 >;
207
208 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
209}
210
211defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
212defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
213defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
214defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
215defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
216defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
217defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
221
222def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
224>;
225
226defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
227
Tom Stellard26075d52013-02-07 19:39:38 +0000228// Transformation function, extract the lower 32bit of a 64bit immediate
229def LO32 : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000230 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
231 MVT::i32);
Tom Stellard26075d52013-02-07 19:39:38 +0000232}]>;
233
Tom Stellardab8a8c82013-07-12 18:15:02 +0000234def LO32f : SDNodeXForm<fpimm, [{
Benjamin Kramerc22c7902013-07-12 20:18:05 +0000235 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
236 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
Tom Stellardab8a8c82013-07-12 18:15:02 +0000237}]>;
238
Tom Stellard26075d52013-02-07 19:39:38 +0000239// Transformation function, extract the upper 32bit of a 64bit immediate
240def HI32 : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000241 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
Tom Stellard26075d52013-02-07 19:39:38 +0000242}]>;
243
Tom Stellardab8a8c82013-07-12 18:15:02 +0000244def HI32f : SDNodeXForm<fpimm, [{
Benjamin Kramerc22c7902013-07-12 20:18:05 +0000245 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000246 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
247 MVT::f32);
Tom Stellardab8a8c82013-07-12 18:15:02 +0000248}]>;
249
Tom Stellard044e4182014-02-06 18:36:34 +0000250def IMM8bitDWORD : PatLeaf <(imm),
251 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
Tom Stellard89093802013-02-07 19:39:40 +0000252>;
253
Tom Stellard044e4182014-02-06 18:36:34 +0000254def as_dword_i32imm : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000255 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
Tom Stellard044e4182014-02-06 18:36:34 +0000256}]>;
257
Tom Stellardafcf12f2013-09-12 02:55:14 +0000258def as_i1imm : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000259 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
Tom Stellardafcf12f2013-09-12 02:55:14 +0000260}]>;
261
262def as_i8imm : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000263 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
Tom Stellardafcf12f2013-09-12 02:55:14 +0000264}]>;
265
Tom Stellard07a10a32013-06-03 17:39:43 +0000266def as_i16imm : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000267 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
Tom Stellard07a10a32013-06-03 17:39:43 +0000268}]>;
269
Tom Stellard044e4182014-02-06 18:36:34 +0000270def as_i32imm: SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000271 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
Tom Stellard044e4182014-02-06 18:36:34 +0000272}]>;
273
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000274def as_i64imm: SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000275 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000276}]>;
277
Tom Stellardfb77f002015-01-13 22:59:41 +0000278// Copied from the AArch64 backend:
279def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
280return CurDAG->getTargetConstant(
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000281 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
Tom Stellardfb77f002015-01-13 22:59:41 +0000282}]>;
283
284// Copied from the AArch64 backend:
285def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
286return CurDAG->getTargetConstant(
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000287 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
Tom Stellardfb77f002015-01-13 22:59:41 +0000288}]>;
289
Matt Arsenault99ed7892014-03-19 22:19:49 +0000290def IMM8bit : PatLeaf <(imm),
291 [{return isUInt<8>(N->getZExtValue());}]
292>;
293
Tom Stellard07a10a32013-06-03 17:39:43 +0000294def IMM12bit : PatLeaf <(imm),
295 [{return isUInt<12>(N->getZExtValue());}]
Tom Stellard89093802013-02-07 19:39:40 +0000296>;
297
Matt Arsenault99ed7892014-03-19 22:19:49 +0000298def IMM16bit : PatLeaf <(imm),
299 [{return isUInt<16>(N->getZExtValue());}]
300>;
301
Marek Olsak58f61a82014-12-07 17:17:38 +0000302def IMM20bit : PatLeaf <(imm),
303 [{return isUInt<20>(N->getZExtValue());}]
304>;
305
Tom Stellardd6cb8e82014-05-09 16:42:21 +0000306def IMM32bit : PatLeaf <(imm),
307 [{return isUInt<32>(N->getZExtValue());}]
308>;
309
Tom Stellarde2367942014-02-06 18:36:41 +0000310def mubuf_vaddr_offset : PatFrag<
311 (ops node:$ptr, node:$offset, node:$imm_offset),
312 (add (add node:$ptr, node:$offset), node:$imm_offset)
313>;
314
Christian Konigf82901a2013-02-26 17:52:23 +0000315class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
Tom Stellard7ed0b522014-04-03 20:19:27 +0000316 return isInlineImmediate(N);
Christian Konigb559b072013-02-16 11:28:36 +0000317}]>;
318
Matt Arsenault303011a2014-12-17 21:04:08 +0000319class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
320 return isInlineImmediate(N);
321}]>;
322
Tom Stellarddf94dc32013-08-14 23:24:24 +0000323class SGPRImm <dag frag> : PatLeaf<frag, [{
Eric Christopher7792e322015-01-30 23:24:40 +0000324 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
Tom Stellarddf94dc32013-08-14 23:24:24 +0000325 return false;
326 }
327 const SIRegisterInfo *SIRI =
Eric Christopher7792e322015-01-30 23:24:40 +0000328 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
Tom Stellarddf94dc32013-08-14 23:24:24 +0000329 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
330 U != E; ++U) {
331 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
332 return true;
333 }
334 }
335 return false;
336}]>;
337
Tom Stellard01825af2014-07-21 14:01:08 +0000338//===----------------------------------------------------------------------===//
339// Custom Operands
340//===----------------------------------------------------------------------===//
341
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +0000342def FRAMEri32 : Operand<iPTR> {
Matt Arsenault06028dd2014-05-01 16:37:52 +0000343 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
Tom Stellard81d871d2013-11-13 23:36:50 +0000344}
345
Tom Stellardd7e6f132015-04-08 01:09:26 +0000346def SoppBrTarget : AsmOperandClass {
347 let Name = "SoppBrTarget";
348 let ParserMethod = "parseSOppBrTarget";
349}
350
Tom Stellard01825af2014-07-21 14:01:08 +0000351def sopp_brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getSOPPBrEncoding";
353 let OperandType = "OPERAND_PCREL";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000354 let ParserMatchClass = SoppBrTarget;
Tom Stellard01825af2014-07-21 14:01:08 +0000355}
356
Tom Stellardb4a313a2014-08-01 00:32:39 +0000357include "SIInstrFormats.td"
Marek Olsak5df00d62014-12-07 12:18:57 +0000358include "VIInstrFormats.td"
Tom Stellardb4a313a2014-08-01 00:32:39 +0000359
Tom Stellardd7e6f132015-04-08 01:09:26 +0000360def MubufOffsetMatchClass : AsmOperandClass {
361 let Name = "MubufOffset";
362 let ParserMethod = "parseMubufOptionalOps";
363 let RenderMethod = "addImmOperands";
364}
365
366class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
367 let Name = "DSOffset"#parser;
368 let ParserMethod = parser;
369 let RenderMethod = "addImmOperands";
370 let PredicateMethod = "isDSOffset";
371}
372
373def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
374def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
375
376def DSOffset01MatchClass : AsmOperandClass {
377 let Name = "DSOffset1";
378 let ParserMethod = "parseDSOff01OptionalOps";
379 let RenderMethod = "addImmOperands";
380 let PredicateMethod = "isDSOffset01";
381}
382
383class GDSBaseMatchClass <string parser> : AsmOperandClass {
384 let Name = "GDS"#parser;
385 let PredicateMethod = "isImm";
386 let ParserMethod = parser;
387 let RenderMethod = "addImmOperands";
388}
389
390def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
391def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
392
393def GLCMatchClass : AsmOperandClass {
394 let Name = "GLC";
395 let PredicateMethod = "isImm";
396 let ParserMethod = "parseMubufOptionalOps";
397 let RenderMethod = "addImmOperands";
398}
399
400def SLCMatchClass : AsmOperandClass {
401 let Name = "SLC";
402 let PredicateMethod = "isImm";
403 let ParserMethod = "parseMubufOptionalOps";
404 let RenderMethod = "addImmOperands";
405}
406
407def TFEMatchClass : AsmOperandClass {
408 let Name = "TFE";
409 let PredicateMethod = "isImm";
410 let ParserMethod = "parseMubufOptionalOps";
411 let RenderMethod = "addImmOperands";
412}
413
414def OModMatchClass : AsmOperandClass {
415 let Name = "OMod";
416 let PredicateMethod = "isImm";
417 let ParserMethod = "parseVOP3OptionalOps";
418 let RenderMethod = "addImmOperands";
419}
420
421def ClampMatchClass : AsmOperandClass {
422 let Name = "Clamp";
423 let PredicateMethod = "isImm";
424 let ParserMethod = "parseVOP3OptionalOps";
425 let RenderMethod = "addImmOperands";
426}
427
Tom Stellard229d5e62014-08-05 14:48:12 +0000428let OperandType = "OPERAND_IMMEDIATE" in {
429
430def offen : Operand<i1> {
431 let PrintMethod = "printOffen";
432}
433def idxen : Operand<i1> {
434 let PrintMethod = "printIdxen";
435}
436def addr64 : Operand<i1> {
437 let PrintMethod = "printAddr64";
438}
439def mbuf_offset : Operand<i16> {
440 let PrintMethod = "printMBUFOffset";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000441 let ParserMatchClass = MubufOffsetMatchClass;
Tom Stellard229d5e62014-08-05 14:48:12 +0000442}
Tom Stellardd7e6f132015-04-08 01:09:26 +0000443class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
Matt Arsenault61cc9082014-10-10 22:16:07 +0000444 let PrintMethod = "printDSOffset";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000445 let ParserMatchClass = mc;
Matt Arsenault61cc9082014-10-10 22:16:07 +0000446}
Tom Stellardd7e6f132015-04-08 01:09:26 +0000447def ds_offset : ds_offset_base <DSOffsetMatchClass>;
448def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
449
Matt Arsenault61cc9082014-10-10 22:16:07 +0000450def ds_offset0 : Operand<i8> {
451 let PrintMethod = "printDSOffset0";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000452 let ParserMatchClass = DSOffset01MatchClass;
Matt Arsenault61cc9082014-10-10 22:16:07 +0000453}
454def ds_offset1 : Operand<i8> {
455 let PrintMethod = "printDSOffset1";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000456 let ParserMatchClass = DSOffset01MatchClass;
Matt Arsenault61cc9082014-10-10 22:16:07 +0000457}
Tom Stellardd7e6f132015-04-08 01:09:26 +0000458class gds_base <AsmOperandClass mc> : Operand <i1> {
Tom Stellard065e3d42015-03-09 18:49:54 +0000459 let PrintMethod = "printGDS";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000460 let ParserMatchClass = mc;
Tom Stellard065e3d42015-03-09 18:49:54 +0000461}
Tom Stellardd7e6f132015-04-08 01:09:26 +0000462def gds : gds_base <GDSMatchClass>;
463
464def gds01 : gds_base <GDS01MatchClass>;
465
Tom Stellard229d5e62014-08-05 14:48:12 +0000466def glc : Operand <i1> {
467 let PrintMethod = "printGLC";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000468 let ParserMatchClass = GLCMatchClass;
Tom Stellard229d5e62014-08-05 14:48:12 +0000469}
470def slc : Operand <i1> {
471 let PrintMethod = "printSLC";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000472 let ParserMatchClass = SLCMatchClass;
Tom Stellard229d5e62014-08-05 14:48:12 +0000473}
474def tfe : Operand <i1> {
475 let PrintMethod = "printTFE";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000476 let ParserMatchClass = TFEMatchClass;
Tom Stellard229d5e62014-08-05 14:48:12 +0000477}
478
Matt Arsenault97069782014-09-30 19:49:48 +0000479def omod : Operand <i32> {
480 let PrintMethod = "printOModSI";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000481 let ParserMatchClass = OModMatchClass;
Matt Arsenault97069782014-09-30 19:49:48 +0000482}
483
484def ClampMod : Operand <i1> {
485 let PrintMethod = "printClampSI";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000486 let ParserMatchClass = ClampMatchClass;
Matt Arsenault97069782014-09-30 19:49:48 +0000487}
488
Tom Stellard229d5e62014-08-05 14:48:12 +0000489} // End OperandType = "OPERAND_IMMEDIATE"
490
Tom Stellardc0503922015-03-12 21:34:22 +0000491def VOPDstS64 : VOPDstOperand <SReg_64>;
492
Christian Konig72d5d5c2013-02-21 15:16:44 +0000493//===----------------------------------------------------------------------===//
Tom Stellardb02c2682014-06-24 23:33:07 +0000494// Complex patterns
495//===----------------------------------------------------------------------===//
496
Tom Stellard85e8b6d2014-08-22 18:49:33 +0000497def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
Tom Stellardf3fc5552014-08-22 18:49:35 +0000498def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
Tom Stellard85e8b6d2014-08-22 18:49:33 +0000499
Tom Stellardb02094e2014-07-21 15:45:01 +0000500def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
Tom Stellard1f9939f2015-02-27 14:59:41 +0000501def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
Tom Stellardc53861a2015-02-11 00:34:32 +0000502def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
Tom Stellardb02094e2014-07-21 15:45:01 +0000503def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
Tom Stellard155bbb72014-08-11 22:18:17 +0000504def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
Tom Stellard7980fc82014-09-25 18:30:26 +0000505def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
Tom Stellardb02c2682014-06-24 23:33:07 +0000506
Tom Stellardb4a313a2014-08-01 00:32:39 +0000507def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
Matt Arsenault1cffa4c2014-11-13 19:49:04 +0000508def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
Matt Arsenault4831ce52015-01-06 23:00:37 +0000509def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000510def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
511
Tom Stellardb02c2682014-06-24 23:33:07 +0000512//===----------------------------------------------------------------------===//
Christian Konig72d5d5c2013-02-21 15:16:44 +0000513// SI assembler operands
514//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000515
Christian Konigeabf8332013-02-21 15:16:49 +0000516def SIOperand {
517 int ZERO = 0x80;
Christian Konigd3039962013-02-26 17:52:09 +0000518 int VCC = 0x6A;
Matt Arsenault3f981402014-09-15 15:41:53 +0000519 int FLAT_SCR = 0x68;
Tom Stellard75aadc22012-12-11 21:25:42 +0000520}
521
Tom Stellardb4a313a2014-08-01 00:32:39 +0000522def SRCMODS {
523 int NONE = 0;
Marek Olsak7d777282015-03-24 13:40:15 +0000524 int NEG = 1;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000525}
526
527def DSTCLAMP {
528 int NONE = 0;
529}
530
531def DSTOMOD {
532 int NONE = 0;
533}
Tom Stellard75aadc22012-12-11 21:25:42 +0000534
Christian Konig72d5d5c2013-02-21 15:16:44 +0000535//===----------------------------------------------------------------------===//
536//
537// SI Instruction multiclass helpers.
538//
539// Instructions with _32 take 32-bit operands.
540// Instructions with _64 take 64-bit operands.
541//
542// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
543// encoding is the standard encoding, but instruction that make use of
544// any of the instruction modifiers must use the 64-bit encoding.
545//
546// Instructions with _e32 use the 32-bit encoding.
547// Instructions with _e64 use the 64-bit encoding.
548//
549//===----------------------------------------------------------------------===//
550
Tom Stellardc470c962014-10-01 14:44:42 +0000551class SIMCInstr <string pseudo, int subtarget> {
552 string PseudoInstr = pseudo;
553 int Subtarget = subtarget;
554}
555
Christian Konig72d5d5c2013-02-21 15:16:44 +0000556//===----------------------------------------------------------------------===//
Tom Stellard3a35d8f2014-10-01 14:44:45 +0000557// EXP classes
558//===----------------------------------------------------------------------===//
559
560class EXPCommon : InstSI<
561 (outs),
562 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000563 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
Tom Stellard326d6ec2014-11-05 14:50:53 +0000564 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
Tom Stellard3a35d8f2014-10-01 14:44:45 +0000565 [] > {
566
567 let EXP_CNT = 1;
568 let Uses = [EXEC];
569}
570
571multiclass EXP_m {
572
Tom Stellard1ca873b2015-02-18 16:08:17 +0000573 let isPseudo = 1, isCodeGenOnly = 1 in {
Tom Stellard326d6ec2014-11-05 14:50:53 +0000574 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
Tom Stellard3a35d8f2014-10-01 14:44:45 +0000575 }
576
Tom Stellard326d6ec2014-11-05 14:50:53 +0000577 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
Marek Olsak5df00d62014-12-07 12:18:57 +0000578
579 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
Tom Stellard3a35d8f2014-10-01 14:44:45 +0000580}
581
582//===----------------------------------------------------------------------===//
Christian Konig72d5d5c2013-02-21 15:16:44 +0000583// Scalar classes
584//===----------------------------------------------------------------------===//
585
Marek Olsak5df00d62014-12-07 12:18:57 +0000586class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
587 SOP1 <outs, ins, "", pattern>,
588 SIMCInstr<opName, SISubtarget.NONE> {
589 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +0000590 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +0000591}
Christian Konig72d5d5c2013-02-21 15:16:44 +0000592
Marek Olsak367447c2015-01-27 17:25:11 +0000593class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
594 SOP1 <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000595 SOP1e <op.SI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000596 SIMCInstr<opName, SISubtarget.SI> {
597 let isCodeGenOnly = 0;
598 let AssemblerPredicates = [isSICI];
599}
Marek Olsak5df00d62014-12-07 12:18:57 +0000600
Marek Olsak367447c2015-01-27 17:25:11 +0000601class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
602 SOP1 <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000603 SOP1e <op.VI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000604 SIMCInstr<opName, SISubtarget.VI> {
605 let isCodeGenOnly = 0;
606 let AssemblerPredicates = [isVI];
607}
Marek Olsak5df00d62014-12-07 12:18:57 +0000608
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000609multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
610 list<dag> pattern> {
Marek Olsak5df00d62014-12-07 12:18:57 +0000611
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000612 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000613
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000614 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
615
616 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
617
Marek Olsak5df00d62014-12-07 12:18:57 +0000618}
619
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000620multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
621 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
622 opName#" $dst, $src0", pattern
623>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000624
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000625multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
626 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
627 opName#" $dst, $src0", pattern
628>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000629
630// no input, 64-bit output.
631multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
632 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
633
634 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
Marek Olsak367447c2015-01-27 17:25:11 +0000635 opName#" $dst"> {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000636 let ssrc0 = 0;
Marek Olsak5df00d62014-12-07 12:18:57 +0000637 }
638
639 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
Marek Olsak367447c2015-01-27 17:25:11 +0000640 opName#" $dst"> {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000641 let ssrc0 = 0;
Marek Olsak5df00d62014-12-07 12:18:57 +0000642 }
643}
Christian Konig72d5d5c2013-02-21 15:16:44 +0000644
Tom Stellardce449ad2015-02-18 16:08:11 +0000645// 64-bit input, no output
646multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
647 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
648
649 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
650 opName#" $src0"> {
651 let sdst = 0;
652 }
653
654 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
655 opName#" $src0"> {
656 let sdst = 0;
657 }
658}
659
Matt Arsenault8333e432014-06-10 19:18:24 +0000660// 64-bit input, 32-bit output.
Tom Stellarde1e4a2d32015-02-13 21:02:37 +0000661multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
662 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
663 opName#" $dst, $src0", pattern
664>;
Matt Arsenault1a179e82014-11-13 20:23:36 +0000665
Marek Olsak5df00d62014-12-07 12:18:57 +0000666class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
667 SOP2<outs, ins, "", pattern>,
668 SIMCInstr<opName, SISubtarget.NONE> {
669 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +0000670 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +0000671 let Size = 4;
Tom Stellard0c0008c2015-02-18 16:08:13 +0000672
673 // Pseudo instructions have no encodings, but adding this field here allows
674 // us to do:
675 // let sdst = xxx in {
676 // for multiclasses that include both real and pseudo instructions.
677 field bits<7> sdst = 0;
Marek Olsak5df00d62014-12-07 12:18:57 +0000678}
Christian Konig72d5d5c2013-02-21 15:16:44 +0000679
Marek Olsak367447c2015-01-27 17:25:11 +0000680class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
681 SOP2<outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000682 SOP2e<op.SI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000683 SIMCInstr<opName, SISubtarget.SI> {
684 let AssemblerPredicates = [isSICI];
685}
Matt Arsenault94812212014-11-14 18:18:16 +0000686
Marek Olsak367447c2015-01-27 17:25:11 +0000687class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
688 SOP2<outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000689 SOP2e<op.VI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000690 SIMCInstr<opName, SISubtarget.VI> {
691 let AssemblerPredicates = [isVI];
692}
Marek Olsak5df00d62014-12-07 12:18:57 +0000693
694multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
695 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
696 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
697
698 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
699 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
Marek Olsak367447c2015-01-27 17:25:11 +0000700 opName#" $dst, $src0, $src1 [$scc]">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000701
702 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
703 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
Marek Olsak367447c2015-01-27 17:25:11 +0000704 opName#" $dst, $src0, $src1 [$scc]">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000705}
706
Tom Stellardee21faa2015-02-18 16:08:09 +0000707multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
708 list<dag> pattern> {
Marek Olsak5df00d62014-12-07 12:18:57 +0000709
Tom Stellardee21faa2015-02-18 16:08:09 +0000710 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000711
Tom Stellardee21faa2015-02-18 16:08:09 +0000712 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
713
714 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
715
Marek Olsak5df00d62014-12-07 12:18:57 +0000716}
717
Tom Stellardee21faa2015-02-18 16:08:09 +0000718multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
719 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
720 opName#" $dst, $src0, $src1", pattern
721>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000722
Tom Stellardee21faa2015-02-18 16:08:09 +0000723multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
724 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
725 opName#" $dst, $src0, $src1", pattern
726>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000727
Tom Stellardee21faa2015-02-18 16:08:09 +0000728multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
729 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
730 opName#" $dst, $src0, $src1", pattern
731>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000732
Tom Stellardb6550522015-01-12 19:33:18 +0000733class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
Matt Arsenault0cb92e12014-04-11 19:25:18 +0000734 string opName, PatLeaf cond> : SOPC <
735 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
Tom Stellarde2f5b412015-03-12 21:34:28 +0000736 opName#" $src0, $src1", []>;
Matt Arsenault0cb92e12014-04-11 19:25:18 +0000737
738class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
739 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
740
741class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
742 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000743
Marek Olsak5df00d62014-12-07 12:18:57 +0000744class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
745 SOPK <outs, ins, "", pattern>,
746 SIMCInstr<opName, SISubtarget.NONE> {
747 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +0000748 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +0000749}
Christian Konig72d5d5c2013-02-21 15:16:44 +0000750
Marek Olsak367447c2015-01-27 17:25:11 +0000751class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
752 SOPK <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000753 SOPKe <op.SI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000754 SIMCInstr<opName, SISubtarget.SI> {
755 let AssemblerPredicates = [isSICI];
756 let isCodeGenOnly = 0;
757}
Marek Olsak5df00d62014-12-07 12:18:57 +0000758
Marek Olsak367447c2015-01-27 17:25:11 +0000759class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
760 SOPK <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +0000761 SOPKe <op.VI>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000762 SIMCInstr<opName, SISubtarget.VI> {
763 let AssemblerPredicates = [isVI];
764 let isCodeGenOnly = 0;
765}
Marek Olsak5df00d62014-12-07 12:18:57 +0000766
Tom Stellard8980dc32015-04-08 01:09:22 +0000767multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
768 string asm = opName#opAsm> {
769 def "" : SOPK_Pseudo <opName, outs, ins, []>;
770
771 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
772
773 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
774
775}
776
Marek Olsak5df00d62014-12-07 12:18:57 +0000777multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
778 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
779 pattern>;
780
781 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
Marek Olsak367447c2015-01-27 17:25:11 +0000782 opName#" $dst, $src0">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000783
784 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
Marek Olsak367447c2015-01-27 17:25:11 +0000785 opName#" $dst, $src0">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000786}
787
788multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
789 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
790 (ins SReg_32:$src0, u16imm:$src1), pattern>;
791
Tom Stellard8980dc32015-04-08 01:09:22 +0000792 let DisableEncoding = "$dst" in {
793 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
794 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000795
Tom Stellard8980dc32015-04-08 01:09:22 +0000796 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
797 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
798 }
Marek Olsak5df00d62014-12-07 12:18:57 +0000799}
Christian Konig72d5d5c2013-02-21 15:16:44 +0000800
Tom Stellard8980dc32015-04-08 01:09:22 +0000801multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
802 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
803 " $sdst, $simm16"
804>;
805
806multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
807 string argAsm, string asm = opName#argAsm> {
808
809 def "" : SOPK_Pseudo <opName, outs, ins, []>;
810
811 def _si : SOPK <outs, ins, asm, []>,
812 SOPK64e <op.SI>,
813 SIMCInstr<opName, SISubtarget.SI> {
814 let AssemblerPredicates = [isSICI];
815 let isCodeGenOnly = 0;
816 }
817
818 def _vi : SOPK <outs, ins, asm, []>,
819 SOPK64e <op.VI>,
820 SIMCInstr<opName, SISubtarget.VI> {
821 let AssemblerPredicates = [isVI];
822 let isCodeGenOnly = 0;
823 }
824}
Tom Stellardc470c962014-10-01 14:44:42 +0000825//===----------------------------------------------------------------------===//
826// SMRD classes
827//===----------------------------------------------------------------------===//
828
829class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
830 SMRD <outs, ins, "", pattern>,
831 SIMCInstr<opName, SISubtarget.NONE> {
832 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +0000833 let isCodeGenOnly = 1;
Tom Stellardc470c962014-10-01 14:44:42 +0000834}
835
836class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
837 string asm> :
838 SMRD <outs, ins, asm, []>,
839 SMRDe <op, imm>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000840 SIMCInstr<opName, SISubtarget.SI> {
841 let AssemblerPredicates = [isSICI];
842}
Tom Stellardc470c962014-10-01 14:44:42 +0000843
Marek Olsak5df00d62014-12-07 12:18:57 +0000844class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
845 string asm> :
846 SMRD <outs, ins, asm, []>,
847 SMEMe_vi <op, imm>,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000848 SIMCInstr<opName, SISubtarget.VI> {
849 let AssemblerPredicates = [isVI];
850}
Marek Olsak5df00d62014-12-07 12:18:57 +0000851
Tom Stellardc470c962014-10-01 14:44:42 +0000852multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
853 string asm, list<dag> pattern> {
854
855 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
856
857 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
858
Matt Arsenault1991f5e2015-02-18 02:10:40 +0000859 // glc is only applicable to scalar stores, which are not yet
860 // implemented.
861 let glc = 0 in {
862 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
863 }
Tom Stellardc470c962014-10-01 14:44:42 +0000864}
865
866multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
Christian Konig9c7afd12013-03-18 11:33:50 +0000867 RegisterClass dstClass> {
Tom Stellardc470c962014-10-01 14:44:42 +0000868 defm _IMM : SMRD_m <
869 op, opName#"_IMM", 1, (outs dstClass:$dst),
Matt Arsenault4d7d3832014-04-15 22:32:49 +0000870 (ins baseClass:$sbase, u32imm:$offset),
Tom Stellardc470c962014-10-01 14:44:42 +0000871 opName#" $dst, $sbase, $offset", []
Christian Konig72d5d5c2013-02-21 15:16:44 +0000872 >;
873
Tom Stellardc470c962014-10-01 14:44:42 +0000874 defm _SGPR : SMRD_m <
875 op, opName#"_SGPR", 0, (outs dstClass:$dst),
Christian Konig9c7afd12013-03-18 11:33:50 +0000876 (ins baseClass:$sbase, SReg_32:$soff),
Tom Stellardc470c962014-10-01 14:44:42 +0000877 opName#" $dst, $sbase, $soff", []
Christian Konig72d5d5c2013-02-21 15:16:44 +0000878 >;
879}
880
881//===----------------------------------------------------------------------===//
882// Vector ALU classes
883//===----------------------------------------------------------------------===//
884
Tom Stellardb4a313a2014-08-01 00:32:39 +0000885// This must always be right before the operand being input modified.
886def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
887 let PrintMethod = "printOperandAndMods";
888}
Tom Stellardd7e6f132015-04-08 01:09:26 +0000889
890def InputModsMatchClass : AsmOperandClass {
891 let Name = "RegWithInputMods";
892}
893
Tom Stellardb4a313a2014-08-01 00:32:39 +0000894def InputModsNoDefault : Operand <i32> {
895 let PrintMethod = "printOperandAndMods";
Tom Stellardd7e6f132015-04-08 01:09:26 +0000896 let ParserMatchClass = InputModsMatchClass;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000897}
898
899class getNumSrcArgs<ValueType Src1, ValueType Src2> {
900 int ret =
901 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
902 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
903 3)); // VOP3
904}
905
906// Returns the register class to use for the destination of VOP[123C]
907// instructions for the given VT.
908class getVALUDstForVT<ValueType VT> {
Tom Stellardc0503922015-03-12 21:34:22 +0000909 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
910 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
911 VOPDstOperand<SReg_64>)); // else VT == i1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000912}
913
914// Returns the register class to use for source 0 of VOP[12C]
915// instructions for the given VT.
916class getVOPSrc0ForVT<ValueType VT> {
Tom Stellardb6550522015-01-12 19:33:18 +0000917 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
Tom Stellardb4a313a2014-08-01 00:32:39 +0000918}
919
920// Returns the register class to use for source 1 of VOP[12C] for the
921// given VT.
922class getVOPSrc1ForVT<ValueType VT> {
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000923 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
Tom Stellardb4a313a2014-08-01 00:32:39 +0000924}
925
Tom Stellardb4a313a2014-08-01 00:32:39 +0000926// Returns the register class to use for sources of VOP3 instructions for the
927// given VT.
928class getVOP3SrcForVT<ValueType VT> {
Tom Stellardb6550522015-01-12 19:33:18 +0000929 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
Tom Stellardb4a313a2014-08-01 00:32:39 +0000930}
931
Tom Stellardb4a313a2014-08-01 00:32:39 +0000932// Returns 1 if the source arguments have modifiers, 0 if they do not.
933class hasModifiers<ValueType SrcVT> {
934 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
935 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
936}
937
938// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
Tom Stellardb6550522015-01-12 19:33:18 +0000939class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
Tom Stellardb4a313a2014-08-01 00:32:39 +0000940 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
941 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
942 (ins)));
943}
944
945// Returns the input arguments for VOP3 instructions for the given SrcVT.
Tom Stellardb6550522015-01-12 19:33:18 +0000946class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
947 RegisterOperand Src2RC, int NumSrcArgs,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000948 bit HasModifiers> {
949
950 dag ret =
951 !if (!eq(NumSrcArgs, 1),
952 !if (!eq(HasModifiers, 1),
953 // VOP1 with modifiers
954 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
Matt Arsenault97069782014-09-30 19:49:48 +0000955 ClampMod:$clamp, omod:$omod)
Tom Stellardb4a313a2014-08-01 00:32:39 +0000956 /* else */,
957 // VOP1 without modifiers
958 (ins Src0RC:$src0)
959 /* endif */ ),
960 !if (!eq(NumSrcArgs, 2),
961 !if (!eq(HasModifiers, 1),
962 // VOP 2 with modifiers
963 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
964 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
Matt Arsenault97069782014-09-30 19:49:48 +0000965 ClampMod:$clamp, omod:$omod)
Tom Stellardb4a313a2014-08-01 00:32:39 +0000966 /* else */,
967 // VOP2 without modifiers
968 (ins Src0RC:$src0, Src1RC:$src1)
969 /* endif */ )
970 /* NumSrcArgs == 3 */,
971 !if (!eq(HasModifiers, 1),
972 // VOP3 with modifiers
973 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
974 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
975 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
Matt Arsenault97069782014-09-30 19:49:48 +0000976 ClampMod:$clamp, omod:$omod)
Tom Stellardb4a313a2014-08-01 00:32:39 +0000977 /* else */,
978 // VOP3 without modifiers
979 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
980 /* endif */ )));
981}
982
983// Returns the assembly string for the inputs and outputs of a VOP[12C]
984// instruction. This does not add the _e32 suffix, so it can be reused
985// by getAsm64.
986class getAsm32 <int NumSrcArgs> {
987 string src1 = ", $src1";
988 string src2 = ", $src2";
Tom Stellardc0503922015-03-12 21:34:22 +0000989 string ret = "$dst, $src0"#
Tom Stellardb4a313a2014-08-01 00:32:39 +0000990 !if(!eq(NumSrcArgs, 1), "", src1)#
991 !if(!eq(NumSrcArgs, 3), src2, "");
992}
993
994// Returns the assembly string for the inputs and outputs of a VOP3
995// instruction.
996class getAsm64 <int NumSrcArgs, bit HasModifiers> {
Matt Arsenault268757b2015-01-15 23:17:03 +0000997 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
Matt Arsenault97069782014-09-30 19:49:48 +0000998 string src1 = !if(!eq(NumSrcArgs, 1), "",
999 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1000 " $src1_modifiers,"));
1001 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
Tom Stellardb4a313a2014-08-01 00:32:39 +00001002 string ret =
1003 !if(!eq(HasModifiers, 0),
1004 getAsm32<NumSrcArgs>.ret,
Tom Stellardc0503922015-03-12 21:34:22 +00001005 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
Tom Stellardb4a313a2014-08-01 00:32:39 +00001006}
1007
1008
1009class VOPProfile <list<ValueType> _ArgVT> {
1010
1011 field list<ValueType> ArgVT = _ArgVT;
1012
1013 field ValueType DstVT = ArgVT[0];
1014 field ValueType Src0VT = ArgVT[1];
1015 field ValueType Src1VT = ArgVT[2];
1016 field ValueType Src2VT = ArgVT[3];
Tom Stellardc0503922015-03-12 21:34:22 +00001017 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
Tom Stellardb6550522015-01-12 19:33:18 +00001018 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001019 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
Tom Stellardb6550522015-01-12 19:33:18 +00001020 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1021 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1022 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001023
1024 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1025 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1026
1027 field dag Outs = (outs DstRC:$dst);
1028
1029 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1030 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1031 HasModifiers>.ret;
1032
Tom Stellardc0503922015-03-12 21:34:22 +00001033 field string Asm32 = getAsm32<NumSrcArgs>.ret;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001034 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1035}
1036
Tom Stellardd1f0f022015-04-23 19:33:54 +00001037// FIXME: I think these F16 profiles will need to use f16 types in order
1038// for the instruction patterns to work.
1039def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1040def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1041def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1042
Tom Stellardb4a313a2014-08-01 00:32:39 +00001043def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1044def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1045def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1046def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1047def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1048def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1049def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1050def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1051def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1052
1053def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1054def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1055def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1056def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1057def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
Marek Olsak11057ee2015-02-03 17:38:01 +00001058def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001059def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1060def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
Tom Stellard73ae1cb2014-09-23 21:26:25 +00001061 let Src0RC32 = VCSrc_32;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001062}
Matt Arsenault4831ce52015-01-06 23:00:37 +00001063
1064def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1065 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
Tom Stellardc0503922015-03-12 21:34:22 +00001066 let Asm64 = "$dst, $src0_modifiers, $src1";
Matt Arsenault4831ce52015-01-06 23:00:37 +00001067}
1068
1069def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1070 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
Tom Stellardc0503922015-03-12 21:34:22 +00001071 let Asm64 = "$dst, $src0_modifiers, $src1";
Matt Arsenault4831ce52015-01-06 23:00:37 +00001072}
1073
Tom Stellardb4a313a2014-08-01 00:32:39 +00001074def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
Marek Olsak707a6d02015-02-03 21:53:01 +00001075def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001076def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
Tom Stellard5224df32015-03-10 16:16:44 +00001077def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1078 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1079 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
Tom Stellardc0503922015-03-12 21:34:22 +00001080 let Asm64 = "$dst, $src0, $src1, $src2";
Tom Stellard5224df32015-03-10 16:16:44 +00001081}
Tom Stellardb4a313a2014-08-01 00:32:39 +00001082
1083def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
Matt Arsenault70120fa2015-02-21 21:29:00 +00001084def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1085 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
Tom Stellardc0503922015-03-12 21:34:22 +00001086 field string Asm = "$dst, $src0, $vsrc1, $src2";
Matt Arsenault70120fa2015-02-21 21:29:00 +00001087}
Tom Stellardb4a313a2014-08-01 00:32:39 +00001088def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1089def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1090def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1091
1092
Christian Konigf741fbf2013-02-26 17:52:42 +00001093class VOP <string opName> {
1094 string OpName = opName;
1095}
1096
Christian Konig3c145802013-03-27 09:12:59 +00001097class VOP2_REV <string revOp, bit isOrig> {
1098 string RevOp = revOp;
1099 bit IsOrig = isOrig;
1100}
1101
Matt Arsenault9903ccf2014-09-08 15:07:27 +00001102class AtomicNoRet <string noRetOp, bit isRet> {
1103 string NoRetOp = noRetOp;
1104 bit IsRet = isRet;
1105}
1106
Tom Stellard94d2e992014-10-07 23:51:34 +00001107class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1108 VOP1Common <outs, ins, "", pattern>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001109 VOP <opName>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001110 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1111 MnemonicAlias<opName#"_e32", opName> {
Tom Stellard94d2e992014-10-07 23:51:34 +00001112 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001113 let isCodeGenOnly = 1;
Tom Stellardc34c37a2015-02-18 16:08:15 +00001114
1115 field bits<8> vdst;
1116 field bits<9> src0;
Tom Stellard94d2e992014-10-07 23:51:34 +00001117}
1118
Tom Stellard23c2c3d2015-03-20 15:14:21 +00001119class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1120 VOP1<op.SI, outs, ins, asm, []>,
Tom Stellardd1f0f022015-04-23 19:33:54 +00001121 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1122 let AssemblerPredicate = SIAssemblerPredicate;
1123}
Tom Stellard23c2c3d2015-03-20 15:14:21 +00001124
1125class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1126 VOP1<op.VI, outs, ins, asm, []>,
Tom Stellardd1f0f022015-04-23 19:33:54 +00001127 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1128 let AssemblerPredicates = [isVI];
1129}
Tom Stellard23c2c3d2015-03-20 15:14:21 +00001130
Tom Stellard94d2e992014-10-07 23:51:34 +00001131multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1132 string opName> {
1133 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1134
Tom Stellard23c2c3d2015-03-20 15:14:21 +00001135 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1136
1137 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001138}
1139
Marek Olsak3ecf5082015-02-03 21:53:05 +00001140multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1141 string opName> {
1142 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1143
Tom Stellard23c2c3d2015-03-20 15:14:21 +00001144 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
Marek Olsak3ecf5082015-02-03 21:53:05 +00001145}
1146
Marek Olsak5df00d62014-12-07 12:18:57 +00001147class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1148 VOP2Common <outs, ins, "", pattern>,
1149 VOP <opName>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001150 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1151 MnemonicAlias<opName#"_e32", opName> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001152 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001153 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +00001154}
1155
Tom Stellard3b0dab92015-03-20 15:14:23 +00001156class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1157 VOP2 <op.SI, outs, ins, opName#asm, []>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001158 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1159 let AssemblerPredicates = [isSICI];
1160}
Tom Stellard3b0dab92015-03-20 15:14:23 +00001161
1162class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
Marek Olsak2a1c9d02015-03-27 19:10:06 +00001163 VOP2 <op.VI, outs, ins, opName#asm, []>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001164 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1165 let AssemblerPredicates = [isVI];
1166}
Tom Stellard3b0dab92015-03-20 15:14:23 +00001167
Marek Olsakf0b130a2015-01-15 18:43:06 +00001168multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
Marek Olsak7585a292015-02-03 17:38:05 +00001169 string opName, string revOp> {
Marek Olsakf0b130a2015-01-15 18:43:06 +00001170 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
Marek Olsak7585a292015-02-03 17:38:05 +00001171 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
Marek Olsakf0b130a2015-01-15 18:43:06 +00001172
Tom Stellard3b0dab92015-03-20 15:14:23 +00001173 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
Marek Olsakf0b130a2015-01-15 18:43:06 +00001174}
1175
Marek Olsak5df00d62014-12-07 12:18:57 +00001176multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
Marek Olsak7585a292015-02-03 17:38:05 +00001177 string opName, string revOp> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001178 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
Marek Olsak7585a292015-02-03 17:38:05 +00001179 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001180
Tom Stellard3b0dab92015-03-20 15:14:23 +00001181 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1182
1183 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1184
Tom Stellard94d2e992014-10-07 23:51:34 +00001185}
1186
Tom Stellardb4a313a2014-08-01 00:32:39 +00001187class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1188
1189 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1190 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001191 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
Tom Stellardb4a313a2014-08-01 00:32:39 +00001192 bits<2> omod = !if(HasModifiers, ?, 0);
1193 bits<1> clamp = !if(HasModifiers, ?, 0);
1194 bits<9> src1 = !if(HasSrc1, ?, 0);
1195 bits<9> src2 = !if(HasSrc2, ?, 0);
1196}
1197
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001198class VOP3DisableModFields <bit HasSrc0Mods,
1199 bit HasSrc1Mods = 0,
1200 bit HasSrc2Mods = 0,
1201 bit HasOutputMods = 0> {
1202 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1203 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1204 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1205 bits<2> omod = !if(HasOutputMods, ?, 0);
1206 bits<1> clamp = !if(HasOutputMods, ?, 0);
1207}
1208
Tom Stellardbda32c92014-07-21 17:44:29 +00001209class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1210 VOP3Common <outs, ins, "", pattern>,
1211 VOP <opName>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001212 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1213 MnemonicAlias<opName#"_e64", opName> {
Tom Stellardbda32c92014-07-21 17:44:29 +00001214 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001215 let isCodeGenOnly = 1;
Tom Stellardbda32c92014-07-21 17:44:29 +00001216}
1217
1218class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
Marek Olsak5df00d62014-12-07 12:18:57 +00001219 VOP3Common <outs, ins, asm, []>,
1220 VOP3e <op>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001221 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1222 let AssemblerPredicates = [isSICI];
1223}
Tom Stellardbda32c92014-07-21 17:44:29 +00001224
Marek Olsak5df00d62014-12-07 12:18:57 +00001225class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1226 VOP3Common <outs, ins, asm, []>,
1227 VOP3e_vi <op>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001228 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1229 let AssemblerPredicates = [isVI];
1230}
Marek Olsak5df00d62014-12-07 12:18:57 +00001231
Matt Arsenault692acf12015-02-14 03:02:23 +00001232class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1233 VOP3Common <outs, ins, asm, []>,
1234 VOP3be <op>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001235 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1236 let AssemblerPredicates = [isSICI];
1237}
Matt Arsenault692acf12015-02-14 03:02:23 +00001238
1239class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1240 VOP3Common <outs, ins, asm, []>,
1241 VOP3be_vi <op>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001242 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1243 let AssemblerPredicates = [isVI];
1244}
Matt Arsenault692acf12015-02-14 03:02:23 +00001245
Marek Olsak5df00d62014-12-07 12:18:57 +00001246multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001247 string opName, int NumSrcArgs, bit HasMods = 1> {
Tom Stellardc721a232014-05-16 20:56:47 +00001248
Tom Stellardbda32c92014-07-21 17:44:29 +00001249 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
Tom Stellardc721a232014-05-16 20:56:47 +00001250
Tom Stellard845bb3c2014-10-07 23:51:41 +00001251 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001252 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1253 !if(!eq(NumSrcArgs, 2), 0, 1),
1254 HasMods>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001255 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1256 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1257 !if(!eq(NumSrcArgs, 2), 0, 1),
1258 HasMods>;
1259}
Tom Stellardc721a232014-05-16 20:56:47 +00001260
Marek Olsak5df00d62014-12-07 12:18:57 +00001261// VOP3_m without source modifiers
Matt Arsenault65fa1c42015-02-18 02:15:27 +00001262multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
Marek Olsak5df00d62014-12-07 12:18:57 +00001263 string opName, int NumSrcArgs, bit HasMods = 1> {
1264
1265 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1266
1267 let src0_modifiers = 0,
1268 src1_modifiers = 0,
Matt Arsenault65fa1c42015-02-18 02:15:27 +00001269 src2_modifiers = 0,
1270 clamp = 0,
1271 omod = 0 in {
Marek Olsak5df00d62014-12-07 12:18:57 +00001272 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1273 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1274 }
Tom Stellardc721a232014-05-16 20:56:47 +00001275}
1276
Tom Stellard94d2e992014-10-07 23:51:34 +00001277multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001278 list<dag> pattern, string opName, bit HasMods = 1> {
Tom Stellardbda32c92014-07-21 17:44:29 +00001279
1280 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1281
Tom Stellard94d2e992014-10-07 23:51:34 +00001282 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001283 VOP3DisableFields<0, 0, HasMods>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001284
1285 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1286 VOP3DisableFields<0, 0, HasMods>;
Tom Stellardbda32c92014-07-21 17:44:29 +00001287}
1288
Marek Olsak3ecf5082015-02-03 21:53:05 +00001289multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1290 list<dag> pattern, string opName, bit HasMods = 1> {
1291
1292 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1293
1294 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1295 VOP3DisableFields<0, 0, HasMods>;
1296 // No VI instruction. This class is for SI only.
1297}
1298
Tom Stellardbec5a242014-10-07 23:51:38 +00001299multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
Marek Olsak7585a292015-02-03 17:38:05 +00001300 list<dag> pattern, string opName, string revOp,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001301 bit HasMods = 1, bit UseFullOp = 0> {
1302
1303 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
Marek Olsak7585a292015-02-03 17:38:05 +00001304 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001305
Marek Olsak191507e2015-02-03 17:38:12 +00001306 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001307 VOP3DisableFields<1, 0, HasMods>;
1308
Marek Olsak191507e2015-02-03 17:38:12 +00001309 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001310 VOP3DisableFields<1, 0, HasMods>;
1311}
1312
Marek Olsak191507e2015-02-03 17:38:12 +00001313multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1314 list<dag> pattern, string opName, string revOp,
1315 bit HasMods = 1, bit UseFullOp = 0> {
1316
1317 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1318 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1319
1320 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1321 VOP3DisableFields<1, 0, HasMods>;
1322
1323 // No VI instruction. This class is for SI only.
1324}
1325
Matt Arsenault692acf12015-02-14 03:02:23 +00001326// XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1327// option of implicit vcc use?
Tom Stellard845bb3c2014-10-07 23:51:41 +00001328multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001329 list<dag> pattern, string opName, string revOp,
1330 bit HasMods = 1, bit UseFullOp = 0> {
1331 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1332 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1333
1334 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1335 // can write it into any SGPR. We currently don't use the carry out,
1336 // so for now hardcode it to VCC as well.
1337 let sdst = SIOperand.VCC, Defs = [VCC] in {
Matt Arsenault692acf12015-02-14 03:02:23 +00001338 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1339 VOP3DisableFields<1, 0, HasMods>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001340
Matt Arsenault692acf12015-02-14 03:02:23 +00001341 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1342 VOP3DisableFields<1, 0, HasMods>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001343 } // End sdst = SIOperand.VCC, Defs = [VCC]
1344}
1345
Matt Arsenault31ec5982015-02-14 03:40:35 +00001346multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1347 list<dag> pattern, string opName, string revOp,
1348 bit HasMods = 1, bit UseFullOp = 0> {
1349 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1350
1351
1352 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1353 VOP3DisableFields<1, 1, HasMods>;
1354
1355 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1356 VOP3DisableFields<1, 1, HasMods>;
1357}
1358
Tom Stellard0aec5872014-10-07 23:51:39 +00001359multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001360 list<dag> pattern, string opName,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001361 bit HasMods, bit defExec, string revOp> {
Tom Stellardbda32c92014-07-21 17:44:29 +00001362
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001363 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
Matt Arsenault88a13c62015-03-23 18:45:41 +00001364 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
Tom Stellardbda32c92014-07-21 17:44:29 +00001365
Tom Stellard0aec5872014-10-07 23:51:39 +00001366 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001367 VOP3DisableFields<1, 0, HasMods> {
1368 let Defs = !if(defExec, [EXEC], []);
1369 }
1370
1371 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1372 VOP3DisableFields<1, 0, HasMods> {
Tom Stellard0aec5872014-10-07 23:51:39 +00001373 let Defs = !if(defExec, [EXEC], []);
Christian Konigd3039962013-02-26 17:52:09 +00001374 }
1375}
1376
Marek Olsak15e4a592015-01-15 18:42:55 +00001377// An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1378multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1379 string asm, list<dag> pattern = []> {
Tom Stellard1ca873b2015-02-18 16:08:17 +00001380 let isPseudo = 1, isCodeGenOnly = 1 in {
Marek Olsak15e4a592015-01-15 18:42:55 +00001381 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1382 SIMCInstr<opName, SISubtarget.NONE>;
1383 }
1384
1385 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001386 SIMCInstr <opName, SISubtarget.SI> {
1387 let AssemblerPredicates = [isSICI];
1388 }
Marek Olsak15e4a592015-01-15 18:42:55 +00001389
1390 def _vi : VOP3Common <outs, ins, asm, []>,
1391 VOP3e_vi <op.VI3>,
1392 VOP3DisableFields <1, 0, 0>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001393 SIMCInstr <opName, SISubtarget.VI> {
1394 let AssemblerPredicates = [isVI];
1395 }
Marek Olsak15e4a592015-01-15 18:42:55 +00001396}
1397
Tom Stellard94d2e992014-10-07 23:51:34 +00001398multiclass VOP1_Helper <vop1 op, string opName, dag outs,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001399 dag ins32, string asm32, list<dag> pat32,
1400 dag ins64, string asm64, list<dag> pat64,
1401 bit HasMods> {
Christian Konigb19849a2013-02-21 15:17:04 +00001402
Marek Olsak5df00d62014-12-07 12:18:57 +00001403 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001404
Tom Stellardc0503922015-03-12 21:34:22 +00001405 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
Christian Konig72d5d5c2013-02-21 15:16:44 +00001406}
1407
Tom Stellard94d2e992014-10-07 23:51:34 +00001408multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001409 SDPatternOperator node = null_frag> : VOP1_Helper <
1410 op, opName, P.Outs,
1411 P.Ins32, P.Asm32, [],
1412 P.Ins64, P.Asm64,
1413 !if(P.HasModifiers,
1414 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
Matt Arsenault97069782014-09-30 19:49:48 +00001415 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
Tom Stellardb4a313a2014-08-01 00:32:39 +00001416 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1417 P.HasModifiers
Tom Stellardc721a232014-05-16 20:56:47 +00001418>;
Christian Konigf5754a02013-02-21 15:17:09 +00001419
Marek Olsak5df00d62014-12-07 12:18:57 +00001420multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1421 SDPatternOperator node = null_frag> {
1422
Marek Olsak3ecf5082015-02-03 21:53:05 +00001423 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001424
Marek Olsak3ecf5082015-02-03 21:53:05 +00001425 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
Marek Olsak5df00d62014-12-07 12:18:57 +00001426 !if(P.HasModifiers,
1427 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1428 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
Marek Olsak3ecf5082015-02-03 21:53:05 +00001429 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1430 opName, P.HasModifiers>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001431}
Tom Stellard1cfd7a52013-05-20 15:02:12 +00001432
Tom Stellardbec5a242014-10-07 23:51:38 +00001433multiclass VOP2_Helper <vop2 op, string opName, dag outs,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001434 dag ins32, string asm32, list<dag> pat32,
1435 dag ins64, string asm64, list<dag> pat64,
Marek Olsak7585a292015-02-03 17:38:05 +00001436 string revOp, bit HasMods> {
1437 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001438
Tom Stellardbec5a242014-10-07 23:51:38 +00001439 defm _e64 : VOP3_2_m <op,
Tom Stellardc0503922015-03-12 21:34:22 +00001440 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
Tom Stellardb4a313a2014-08-01 00:32:39 +00001441 >;
Tom Stellard1cfd7a52013-05-20 15:02:12 +00001442}
1443
Tom Stellardbec5a242014-10-07 23:51:38 +00001444multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001445 SDPatternOperator node = null_frag,
Marek Olsak7585a292015-02-03 17:38:05 +00001446 string revOp = opName> : VOP2_Helper <
Tom Stellardb4a313a2014-08-01 00:32:39 +00001447 op, opName, P.Outs,
1448 P.Ins32, P.Asm32, [],
1449 P.Ins64, P.Asm64,
1450 !if(P.HasModifiers,
1451 [(set P.DstVT:$dst,
1452 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001453 i1:$clamp, i32:$omod)),
Tom Stellardb4a313a2014-08-01 00:32:39 +00001454 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1455 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
Marek Olsak7585a292015-02-03 17:38:05 +00001456 revOp, P.HasModifiers
Tom Stellardb4a313a2014-08-01 00:32:39 +00001457>;
1458
Marek Olsak191507e2015-02-03 17:38:12 +00001459multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1460 SDPatternOperator node = null_frag,
1461 string revOp = opName> {
1462 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1463
Tom Stellardc0503922015-03-12 21:34:22 +00001464 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
Marek Olsak191507e2015-02-03 17:38:12 +00001465 !if(P.HasModifiers,
1466 [(set P.DstVT:$dst,
1467 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1468 i1:$clamp, i32:$omod)),
1469 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1470 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1471 opName, revOp, P.HasModifiers>;
1472}
1473
Tom Stellard845bb3c2014-10-07 23:51:41 +00001474multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001475 dag ins32, string asm32, list<dag> pat32,
1476 dag ins64, string asm64, list<dag> pat64,
1477 string revOp, bit HasMods> {
1478
Marek Olsak7585a292015-02-03 17:38:05 +00001479 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001480
Tom Stellard845bb3c2014-10-07 23:51:41 +00001481 defm _e64 : VOP3b_2_m <op,
Tom Stellardc0503922015-03-12 21:34:22 +00001482 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
Tom Stellardb4a313a2014-08-01 00:32:39 +00001483 >;
1484}
1485
Tom Stellard845bb3c2014-10-07 23:51:41 +00001486multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001487 SDPatternOperator node = null_frag,
1488 string revOp = opName> : VOP2b_Helper <
1489 op, opName, P.Outs,
1490 P.Ins32, P.Asm32, [],
1491 P.Ins64, P.Asm64,
1492 !if(P.HasModifiers,
1493 [(set P.DstVT:$dst,
1494 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001495 i1:$clamp, i32:$omod)),
Tom Stellardb4a313a2014-08-01 00:32:39 +00001496 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1497 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1498 revOp, P.HasModifiers
1499>;
1500
Marek Olsakf0b130a2015-01-15 18:43:06 +00001501// A VOP2 instruction that is VOP3-only on VI.
1502multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1503 dag ins32, string asm32, list<dag> pat32,
1504 dag ins64, string asm64, list<dag> pat64,
Marek Olsak7585a292015-02-03 17:38:05 +00001505 string revOp, bit HasMods> {
1506 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
Marek Olsakf0b130a2015-01-15 18:43:06 +00001507
Tom Stellardc0503922015-03-12 21:34:22 +00001508 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
Marek Olsak7585a292015-02-03 17:38:05 +00001509 revOp, HasMods>;
Marek Olsakf0b130a2015-01-15 18:43:06 +00001510}
1511
1512multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1513 SDPatternOperator node = null_frag,
Marek Olsak7585a292015-02-03 17:38:05 +00001514 string revOp = opName>
Marek Olsakf0b130a2015-01-15 18:43:06 +00001515 : VOP2_VI3_Helper <
1516 op, opName, P.Outs,
1517 P.Ins32, P.Asm32, [],
1518 P.Ins64, P.Asm64,
1519 !if(P.HasModifiers,
1520 [(set P.DstVT:$dst,
1521 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1522 i1:$clamp, i32:$omod)),
1523 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1524 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
Marek Olsak7585a292015-02-03 17:38:05 +00001525 revOp, P.HasModifiers
Marek Olsakf0b130a2015-01-15 18:43:06 +00001526>;
1527
Matt Arsenault70120fa2015-02-21 21:29:00 +00001528multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1529
1530 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1531
1532let isCodeGenOnly = 0 in {
1533 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1534 !strconcat(opName, VOP_MADK.Asm), []>,
1535 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1536 VOP2_MADKe <op.SI>;
1537
1538 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1539 !strconcat(opName, VOP_MADK.Asm), []>,
1540 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1541 VOP2_MADKe <op.VI>;
1542} // End isCodeGenOnly = 0
1543}
1544
Marek Olsak5df00d62014-12-07 12:18:57 +00001545class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1546 VOPCCommon <ins, "", pattern>,
1547 VOP <opName>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001548 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1549 MnemonicAlias<opName#"_e32", opName> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001550 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001551 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +00001552}
1553
1554multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001555 string opName, bit DefExec, string revOpName = ""> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001556 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1557
1558 def _si : VOPC<op.SI, ins, asm, []>,
1559 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1560 let Defs = !if(DefExec, [EXEC], []);
Matt Arsenault42f39e12015-03-23 18:45:35 +00001561 let hasSideEffects = DefExec;
Marek Olsak5df00d62014-12-07 12:18:57 +00001562 }
1563
1564 def _vi : VOPC<op.VI, ins, asm, []>,
1565 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1566 let Defs = !if(DefExec, [EXEC], []);
Matt Arsenault42f39e12015-03-23 18:45:35 +00001567 let hasSideEffects = DefExec;
Marek Olsak5df00d62014-12-07 12:18:57 +00001568 }
1569}
1570
Tom Stellard0aec5872014-10-07 23:51:39 +00001571multiclass VOPC_Helper <vopc op, string opName,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001572 dag ins32, string asm32, list<dag> pat32,
1573 dag out64, dag ins64, string asm64, list<dag> pat64,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001574 bit HasMods, bit DefExec, string revOp> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001575 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001576
Tom Stellardc0503922015-03-12 21:34:22 +00001577 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001578 opName, HasMods, DefExec, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001579}
1580
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001581// Special case for class instructions which only have modifiers on
1582// the 1st source operand.
1583multiclass VOPC_Class_Helper <vopc op, string opName,
1584 dag ins32, string asm32, list<dag> pat32,
1585 dag out64, dag ins64, string asm64, list<dag> pat64,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001586 bit HasMods, bit DefExec, string revOp> {
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001587 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1588
Tom Stellardc0503922015-03-12 21:34:22 +00001589 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001590 opName, HasMods, DefExec, revOp>,
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001591 VOP3DisableModFields<1, 0, 0>;
1592}
1593
Tom Stellard0aec5872014-10-07 23:51:39 +00001594multiclass VOPCInst <vopc op, string opName,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001595 VOPProfile P, PatLeaf cond = COND_NULL,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001596 string revOp = opName,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001597 bit DefExec = 0> : VOPC_Helper <
1598 op, opName,
1599 P.Ins32, P.Asm32, [],
Tom Stellardc0503922015-03-12 21:34:22 +00001600 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001601 !if(P.HasModifiers,
1602 [(set i1:$dst,
1603 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001604 i1:$clamp, i32:$omod)),
Tom Stellardb4a313a2014-08-01 00:32:39 +00001605 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1606 cond))],
1607 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001608 P.HasModifiers, DefExec, revOp
Tom Stellardb4a313a2014-08-01 00:32:39 +00001609>;
1610
Matt Arsenault4831ce52015-01-06 23:00:37 +00001611multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
Matt Arsenault096ec1e2015-02-18 02:15:30 +00001612 bit DefExec = 0> : VOPC_Class_Helper <
Matt Arsenault4831ce52015-01-06 23:00:37 +00001613 op, opName,
1614 P.Ins32, P.Asm32, [],
Tom Stellardc0503922015-03-12 21:34:22 +00001615 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
Matt Arsenault4831ce52015-01-06 23:00:37 +00001616 !if(P.HasModifiers,
1617 [(set i1:$dst,
1618 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1619 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001620 P.HasModifiers, DefExec, opName
Matt Arsenault4831ce52015-01-06 23:00:37 +00001621>;
1622
1623
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001624multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1625 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001626
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001627multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1628 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001629
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001630multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1631 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001632
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001633multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1634 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
Christian Konigf5754a02013-02-21 15:17:09 +00001635
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +00001636
Tom Stellard0aec5872014-10-07 23:51:39 +00001637multiclass VOPCX <vopc op, string opName, VOPProfile P,
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001638 PatLeaf cond = COND_NULL,
1639 string revOp = "">
1640 : VOPCInst <op, opName, P, cond, revOp, 1>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001641
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001642multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1643 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001644
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001645multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1646 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001647
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001648multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1649 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001650
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00001651multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1652 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
Tom Stellardb4a313a2014-08-01 00:32:39 +00001653
Tom Stellard845bb3c2014-10-07 23:51:41 +00001654multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001655 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
Tom Stellardc0503922015-03-12 21:34:22 +00001656 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
Tom Stellardb4a313a2014-08-01 00:32:39 +00001657>;
1658
Matt Arsenault4831ce52015-01-06 23:00:37 +00001659multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1660 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1661
1662multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1663 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1664
1665multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1666 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1667
1668multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1669 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1670
Tom Stellard845bb3c2014-10-07 23:51:41 +00001671multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001672 SDPatternOperator node = null_frag> : VOP3_Helper <
Tom Stellardc0503922015-03-12 21:34:22 +00001673 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001674 !if(!eq(P.NumSrcArgs, 3),
1675 !if(P.HasModifiers,
1676 [(set P.DstVT:$dst,
1677 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001678 i1:$clamp, i32:$omod)),
Tom Stellardb4a313a2014-08-01 00:32:39 +00001679 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1680 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1681 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1682 P.Src2VT:$src2))]),
1683 !if(!eq(P.NumSrcArgs, 2),
1684 !if(P.HasModifiers,
1685 [(set P.DstVT:$dst,
1686 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001687 i1:$clamp, i32:$omod)),
Tom Stellardb4a313a2014-08-01 00:32:39 +00001688 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1689 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1690 /* P.NumSrcArgs == 1 */,
1691 !if(P.HasModifiers,
1692 [(set P.DstVT:$dst,
1693 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
Matt Arsenault97069782014-09-30 19:49:48 +00001694 i1:$clamp, i32:$omod))))],
Tom Stellardb4a313a2014-08-01 00:32:39 +00001695 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1696 P.NumSrcArgs, P.HasModifiers
1697>;
1698
Matt Arsenault1bc9d952015-02-14 04:22:00 +00001699// Special case for v_div_fmas_{f32|f64}, since it seems to be the
1700// only VOP instruction that implicitly reads VCC.
1701multiclass VOP3_VCC_Inst <vop3 op, string opName,
1702 VOPProfile P,
1703 SDPatternOperator node = null_frag> : VOP3_Helper <
1704 op, opName,
Tom Stellardc0503922015-03-12 21:34:22 +00001705 (outs P.DstRC.RegClass:$dst),
Matt Arsenault1bc9d952015-02-14 04:22:00 +00001706 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1707 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1708 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1709 ClampMod:$clamp,
1710 omod:$omod),
1711 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1712 [(set P.DstVT:$dst,
1713 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1714 i1:$clamp, i32:$omod)),
1715 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1716 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1717 (i1 VCC)))],
1718 3, 1
1719>;
1720
Tom Stellardb6550522015-01-12 19:33:18 +00001721multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001722 string opName, list<dag> pattern> :
Matt Arsenault31ec5982015-02-14 03:40:35 +00001723 VOP3b_3_m <
Matt Arsenaulta95f5a02014-11-04 20:29:20 +00001724 op, (outs vrc:$vdst, SReg_64:$sdst),
Matt Arsenault272c50a2014-09-30 19:49:43 +00001725 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1726 InputModsNoDefault:$src1_modifiers, arc:$src1,
1727 InputModsNoDefault:$src2_modifiers, arc:$src2,
Matt Arsenaultf2676a52014-11-05 19:35:00 +00001728 ClampMod:$clamp, omod:$omod),
Matt Arsenaulta95f5a02014-11-04 20:29:20 +00001729 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
Tom Stellardb4a313a2014-08-01 00:32:39 +00001730 opName, opName, 1, 1
1731>;
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +00001732
Tom Stellard845bb3c2014-10-07 23:51:41 +00001733multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +00001734 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1735
Tom Stellard845bb3c2014-10-07 23:51:41 +00001736multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
Tom Stellard45c0b3a2015-01-07 20:59:25 +00001737 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +00001738
Matt Arsenault8675db12014-08-29 16:01:14 +00001739
1740class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
Matt Arsenault97069782014-09-30 19:49:48 +00001741 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
Matt Arsenault8675db12014-08-29 16:01:14 +00001742 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1743 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1744 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1745 i32:$src1_modifiers, P.Src1VT:$src1,
1746 i32:$src2_modifiers, P.Src2VT:$src2,
Matt Arsenault97069782014-09-30 19:49:48 +00001747 i1:$clamp,
Matt Arsenault8675db12014-08-29 16:01:14 +00001748 i32:$omod)>;
1749
Christian Konig72d5d5c2013-02-21 15:16:44 +00001750//===----------------------------------------------------------------------===//
Marek Olsak5df00d62014-12-07 12:18:57 +00001751// Interpolation opcodes
1752//===----------------------------------------------------------------------===//
1753
Marek Olsak367447c2015-01-27 17:25:11 +00001754class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1755 VINTRPCommon <outs, ins, "", pattern>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001756 SIMCInstr<opName, SISubtarget.NONE> {
1757 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001758 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +00001759}
1760
1761class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
Marek Olsak367447c2015-01-27 17:25:11 +00001762 string asm> :
1763 VINTRPCommon <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001764 VINTRPe <op>,
1765 SIMCInstr<opName, SISubtarget.SI>;
1766
1767class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
Marek Olsak367447c2015-01-27 17:25:11 +00001768 string asm> :
1769 VINTRPCommon <outs, ins, asm, []>,
Marek Olsak5df00d62014-12-07 12:18:57 +00001770 VINTRPe_vi <op>,
1771 SIMCInstr<opName, SISubtarget.VI>;
1772
1773multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
Tom Stellard2a9d9472015-05-12 15:00:46 +00001774 list<dag> pattern = [],
1775 string disableEncoding = "", string constraints = ""> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001776 let DisableEncoding = disableEncoding,
1777 Constraints = constraints in {
Marek Olsak367447c2015-01-27 17:25:11 +00001778 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001779
Marek Olsak367447c2015-01-27 17:25:11 +00001780 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001781
Marek Olsak367447c2015-01-27 17:25:11 +00001782 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001783 }
1784}
1785
1786//===----------------------------------------------------------------------===//
Christian Konig72d5d5c2013-02-21 15:16:44 +00001787// Vector I/O classes
1788//===----------------------------------------------------------------------===//
1789
Marek Olsak5df00d62014-12-07 12:18:57 +00001790class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1791 DS <outs, ins, "", pattern>,
1792 SIMCInstr <opName, SISubtarget.NONE> {
1793 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001794 let isCodeGenOnly = 1;
Marek Olsak5df00d62014-12-07 12:18:57 +00001795}
1796
1797class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1798 DS <outs, ins, asm, []>,
1799 DSe <op>,
Tom Stellardd7e6f132015-04-08 01:09:26 +00001800 SIMCInstr <opName, SISubtarget.SI> {
1801 let isCodeGenOnly = 0;
1802}
Marek Olsak5df00d62014-12-07 12:18:57 +00001803
1804class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1805 DS <outs, ins, asm, []>,
1806 DSe_vi <op>,
1807 SIMCInstr <opName, SISubtarget.VI>;
1808
Tom Stellardcf051f42015-03-09 18:49:45 +00001809class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1810 DS_Real_si <op,opName, outs, ins, asm> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001811
1812 // Single load interpret the 2 i8imm operands as a single i16 offset.
1813 bits<16> offset;
1814 let offset0 = offset{7-0};
1815 let offset1 = offset{15-8};
Tom Stellardd7e6f132015-04-08 01:09:26 +00001816 let isCodeGenOnly = 0;
Marek Olsak5df00d62014-12-07 12:18:57 +00001817}
1818
Tom Stellardcf051f42015-03-09 18:49:45 +00001819class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1820 DS_Real_vi <op, opName, outs, ins, asm> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001821
1822 // Single load interpret the 2 i8imm operands as a single i16 offset.
1823 bits<16> offset;
1824 let offset0 = offset{7-0};
1825 let offset1 = offset{15-8};
1826}
1827
Tom Stellardcf051f42015-03-09 18:49:45 +00001828multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1829 dag outs = (outs rc:$vdst),
Tom Stellard381a94a2015-05-12 15:00:49 +00001830 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001831 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001832
Tom Stellardcf051f42015-03-09 18:49:45 +00001833 def "" : DS_Pseudo <opName, outs, ins, []>;
1834
1835 let data0 = 0, data1 = 0 in {
1836 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1837 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001838 }
1839}
1840
Tom Stellardcf051f42015-03-09 18:49:45 +00001841multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1842 dag outs = (outs rc:$vdst),
Tom Stellard065e3d42015-03-09 18:49:54 +00001843 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
Tom Stellard381a94a2015-05-12 15:00:49 +00001844 gds01:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001845 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001846
Tom Stellardcf051f42015-03-09 18:49:45 +00001847 def "" : DS_Pseudo <opName, outs, ins, []>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001848
Tom Stellardd7e6f132015-04-08 01:09:26 +00001849 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
Tom Stellardcf051f42015-03-09 18:49:45 +00001850 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1851 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001852 }
1853}
1854
Tom Stellardcf051f42015-03-09 18:49:45 +00001855multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1856 dag outs = (outs),
Tom Stellard381a94a2015-05-12 15:00:49 +00001857 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001858 string asm = opName#" $addr, $data0"#"$offset$gds"> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001859
Tom Stellardcf051f42015-03-09 18:49:45 +00001860 def "" : DS_Pseudo <opName, outs, ins, []>,
1861 AtomicNoRet<opName, 0>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001862
Tom Stellardcf051f42015-03-09 18:49:45 +00001863 let data1 = 0, vdst = 0 in {
1864 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1865 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001866 }
1867}
1868
Tom Stellardcf051f42015-03-09 18:49:45 +00001869multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1870 dag outs = (outs),
Tom Stellard065e3d42015-03-09 18:49:54 +00001871 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
Tom Stellard381a94a2015-05-12 15:00:49 +00001872 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001873 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001874
Tom Stellardcf051f42015-03-09 18:49:45 +00001875 def "" : DS_Pseudo <opName, outs, ins, []>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001876
Tom Stellardd7e6f132015-04-08 01:09:26 +00001877 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
Tom Stellardcf051f42015-03-09 18:49:45 +00001878 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1879 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak5df00d62014-12-07 12:18:57 +00001880 }
1881}
1882
Tom Stellardcf051f42015-03-09 18:49:45 +00001883multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1884 string noRetOp = "",
1885 dag outs = (outs rc:$vdst),
Tom Stellard381a94a2015-05-12 15:00:49 +00001886 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001887 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
Marek Olsak5df00d62014-12-07 12:18:57 +00001888
Tom Stellardcf051f42015-03-09 18:49:45 +00001889 def "" : DS_Pseudo <opName, outs, ins, []>,
1890 AtomicNoRet<noRetOp, 1>;
Matt Arsenault9cd8c382014-03-19 22:19:39 +00001891
Tom Stellardcf051f42015-03-09 18:49:45 +00001892 let data1 = 0 in {
1893 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1894 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak0c1f8812015-01-27 17:25:07 +00001895 }
Matt Arsenault9cd8c382014-03-19 22:19:39 +00001896}
1897
Tom Stellardcf051f42015-03-09 18:49:45 +00001898multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1899 string noRetOp = "", dag ins,
1900 dag outs = (outs rc:$vdst),
Tom Stellard065e3d42015-03-09 18:49:54 +00001901 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
Tom Stellard13c68ef2013-09-05 18:38:09 +00001902
Tom Stellardcf051f42015-03-09 18:49:45 +00001903 def "" : DS_Pseudo <opName, outs, ins, []>,
1904 AtomicNoRet<noRetOp, 1>;
Marek Olsak0c1f8812015-01-27 17:25:07 +00001905
Tom Stellardcf051f42015-03-09 18:49:45 +00001906 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1907 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak0c1f8812015-01-27 17:25:07 +00001908}
1909
1910multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
Tom Stellardcf051f42015-03-09 18:49:45 +00001911 string noRetOp = "", RegisterClass src = rc> :
1912 DS_1A2D_RET_m <op, asm, rc, noRetOp,
Tom Stellard065e3d42015-03-09 18:49:54 +00001913 (ins VGPR_32:$addr, src:$data0, src:$data1,
Tom Stellard381a94a2015-05-12 15:00:49 +00001914 ds_offset:$offset, gds:$gds)
Tom Stellardcf051f42015-03-09 18:49:45 +00001915>;
Matt Arsenault8c6613d2014-06-11 18:08:39 +00001916
Tom Stellardcf051f42015-03-09 18:49:45 +00001917multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1918 string noRetOp = opName,
1919 dag outs = (outs),
Tom Stellard065e3d42015-03-09 18:49:54 +00001920 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
Tom Stellard381a94a2015-05-12 15:00:49 +00001921 ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001922 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
Marek Olsak0c1f8812015-01-27 17:25:07 +00001923
Tom Stellardcf051f42015-03-09 18:49:45 +00001924 def "" : DS_Pseudo <opName, outs, ins, []>,
1925 AtomicNoRet<noRetOp, 0>;
1926
1927 let vdst = 0 in {
1928 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1929 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak0c1f8812015-01-27 17:25:07 +00001930 }
1931}
1932
Tom Stellarddb4995a2015-03-09 16:03:45 +00001933multiclass DS_0A_RET <bits<8> op, string opName,
1934 dag outs = (outs VGPR_32:$vdst),
Tom Stellard381a94a2015-05-12 15:00:49 +00001935 dag ins = (ins ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001936 string asm = opName#" $vdst"#"$offset"#"$gds"> {
Tom Stellarddb4995a2015-03-09 16:03:45 +00001937
1938 let mayLoad = 1, mayStore = 1 in {
1939 def "" : DS_Pseudo <opName, outs, ins, []>;
1940
1941 let addr = 0, data0 = 0, data1 = 0 in {
Tom Stellardcf051f42015-03-09 18:49:45 +00001942 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1943 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Tom Stellarddb4995a2015-03-09 16:03:45 +00001944 } // end addr = 0, data0 = 0, data1 = 0
1945 } // end mayLoad = 1, mayStore = 1
1946}
1947
1948multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1949 dag outs = (outs VGPR_32:$vdst),
Tom Stellard381a94a2015-05-12 15:00:49 +00001950 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
Tom Stellard065e3d42015-03-09 18:49:54 +00001951 string asm = opName#" $vdst, $addr"#"$offset gds"> {
Tom Stellarddb4995a2015-03-09 16:03:45 +00001952
Tom Stellardcf051f42015-03-09 18:49:45 +00001953 def "" : DS_Pseudo <opName, outs, ins, []>;
Tom Stellarddb4995a2015-03-09 16:03:45 +00001954
Tom Stellardcf051f42015-03-09 18:49:45 +00001955 let data0 = 0, data1 = 0, gds = 1 in {
1956 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1957 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1958 } // end data0 = 0, data1 = 0, gds = 1
Tom Stellarddb4995a2015-03-09 16:03:45 +00001959}
1960
1961multiclass DS_1A_GDS <bits<8> op, string opName,
1962 dag outs = (outs),
Tom Stellard381a94a2015-05-12 15:00:49 +00001963 dag ins = (ins VGPR_32:$addr),
Tom Stellarddb4995a2015-03-09 16:03:45 +00001964 string asm = opName#" $addr gds"> {
1965
1966 def "" : DS_Pseudo <opName, outs, ins, []>;
1967
1968 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1969 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1970 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1971 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1972}
1973
1974multiclass DS_1A <bits<8> op, string opName,
1975 dag outs = (outs),
Tom Stellard381a94a2015-05-12 15:00:49 +00001976 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
Tom Stellard065e3d42015-03-09 18:49:54 +00001977 string asm = opName#" $addr"#"$offset"#"$gds"> {
Tom Stellarddb4995a2015-03-09 16:03:45 +00001978
1979 let mayLoad = 1, mayStore = 1 in {
1980 def "" : DS_Pseudo <opName, outs, ins, []>;
1981
1982 let vdst = 0, data0 = 0, data1 = 0 in {
Tom Stellardcf051f42015-03-09 18:49:45 +00001983 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1984 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
Tom Stellarddb4995a2015-03-09 16:03:45 +00001985 } // let vdst = 0, data0 = 0, data1 = 0
1986 } // end mayLoad = 1, mayStore = 1
1987}
1988
Tom Stellard0c238c22014-10-01 14:44:43 +00001989//===----------------------------------------------------------------------===//
1990// MTBUF classes
1991//===----------------------------------------------------------------------===//
1992
1993class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1994 MTBUF <outs, ins, "", pattern>,
1995 SIMCInstr<opName, SISubtarget.NONE> {
1996 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00001997 let isCodeGenOnly = 1;
Tom Stellard0c238c22014-10-01 14:44:43 +00001998}
1999
2000class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2001 string asm> :
2002 MTBUF <outs, ins, asm, []>,
2003 MTBUFe <op>,
2004 SIMCInstr<opName, SISubtarget.SI>;
2005
Marek Olsak5df00d62014-12-07 12:18:57 +00002006class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2007 MTBUF <outs, ins, asm, []>,
2008 MTBUFe_vi <op>,
2009 SIMCInstr <opName, SISubtarget.VI>;
2010
Tom Stellard0c238c22014-10-01 14:44:43 +00002011multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2012 list<dag> pattern> {
2013
2014 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2015
2016 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2017
Marek Olsak5df00d62014-12-07 12:18:57 +00002018 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2019
Tom Stellard0c238c22014-10-01 14:44:43 +00002020}
2021
2022let mayStore = 1, mayLoad = 0 in {
2023
2024multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2025 RegisterClass regClass> : MTBUF_m <
2026 op, opName, (outs),
2027 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002028 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
Tom Stellardc3d7eeb2014-12-19 22:15:30 +00002029 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
Tom Stellard0c238c22014-10-01 14:44:43 +00002030 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2031 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2032>;
2033
2034} // mayStore = 1, mayLoad = 0
2035
2036let mayLoad = 1, mayStore = 0 in {
2037
2038multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2039 RegisterClass regClass> : MTBUF_m <
2040 op, opName, (outs regClass:$dst),
2041 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002042 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
Tom Stellardc3d7eeb2014-12-19 22:15:30 +00002043 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
Tom Stellard0c238c22014-10-01 14:44:43 +00002044 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2045 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2046>;
2047
2048} // mayLoad = 1, mayStore = 0
2049
Marek Olsak5df00d62014-12-07 12:18:57 +00002050//===----------------------------------------------------------------------===//
2051// MUBUF classes
2052//===----------------------------------------------------------------------===//
2053
Marek Olsakee98b112015-01-27 17:24:58 +00002054class mubuf <bits<7> si, bits<7> vi = si> {
2055 field bits<7> SI = si;
2056 field bits<7> VI = vi;
2057}
2058
Tom Stellardd7e6f132015-04-08 01:09:26 +00002059let isCodeGenOnly = 0 in {
2060
2061class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2062 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2063 let lds = 0;
2064}
2065
2066} // End let isCodeGenOnly = 0
2067
2068class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2069 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2070 let lds = 0;
2071}
2072
Marek Olsak7ef6db42015-01-27 17:24:54 +00002073class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2074 bit IsAddr64 = is_addr64;
2075 string OpName = NAME # suffix;
2076}
2077
2078class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2079 MUBUF <outs, ins, "", pattern>,
2080 SIMCInstr<opName, SISubtarget.NONE> {
2081 let isPseudo = 1;
Tom Stellard1ca873b2015-02-18 16:08:17 +00002082 let isCodeGenOnly = 1;
Marek Olsak7ef6db42015-01-27 17:24:54 +00002083
2084 // dummy fields, so that we can use let statements around multiclasses
2085 bits<1> offen;
2086 bits<1> idxen;
2087 bits<8> vaddr;
2088 bits<1> glc;
2089 bits<1> slc;
2090 bits<1> tfe;
2091 bits<8> soffset;
2092}
2093
Marek Olsakee98b112015-01-27 17:24:58 +00002094class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002095 string asm> :
2096 MUBUF <outs, ins, asm, []>,
Marek Olsakee98b112015-01-27 17:24:58 +00002097 MUBUFe <op.SI>,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002098 SIMCInstr<opName, SISubtarget.SI> {
2099 let lds = 0;
2100}
2101
Marek Olsakee98b112015-01-27 17:24:58 +00002102class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002103 string asm> :
2104 MUBUF <outs, ins, asm, []>,
Marek Olsakee98b112015-01-27 17:24:58 +00002105 MUBUFe_vi <op.VI>,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002106 SIMCInstr<opName, SISubtarget.VI> {
2107 let lds = 0;
2108}
2109
Marek Olsakee98b112015-01-27 17:24:58 +00002110multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002111 list<dag> pattern> {
2112
2113 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2114 MUBUFAddr64Table <0>;
2115
Tom Stellardd7e6f132015-04-08 01:09:26 +00002116 let addr64 = 0, isCodeGenOnly = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002117 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2118 }
Marek Olsakee98b112015-01-27 17:24:58 +00002119
2120 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
Marek Olsak7ef6db42015-01-27 17:24:54 +00002121}
2122
Marek Olsakee98b112015-01-27 17:24:58 +00002123multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002124 dag ins, string asm, list<dag> pattern> {
2125
2126 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2127 MUBUFAddr64Table <1>;
2128
Tom Stellardd7e6f132015-04-08 01:09:26 +00002129 let addr64 = 1, isCodeGenOnly = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002130 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2131 }
2132
2133 // There is no VI version. If the pseudo is selected, it should be lowered
2134 // for VI appropriately.
2135}
2136
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002137multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2138 string asm, list<dag> pattern, bit is_return> {
Tom Stellard7980fc82014-09-25 18:30:26 +00002139
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002140 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2141 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2142 AtomicNoRet<NAME#"_OFFSET", is_return>;
2143
2144 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2145 let addr64 = 0 in {
2146 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2147 }
2148
2149 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2150 }
Tom Stellard7980fc82014-09-25 18:30:26 +00002151}
2152
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002153multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2154 string asm, list<dag> pattern, bit is_return> {
Tom Stellard7980fc82014-09-25 18:30:26 +00002155
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002156 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2157 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2158 AtomicNoRet<NAME#"_ADDR64", is_return>;
2159
Tom Stellardc53861a2015-02-11 00:34:32 +00002160 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002161 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2162 }
2163
2164 // There is no VI version. If the pseudo is selected, it should be lowered
2165 // for VI appropriately.
Tom Stellard7980fc82014-09-25 18:30:26 +00002166}
2167
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002168multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
Tom Stellard7980fc82014-09-25 18:30:26 +00002169 ValueType vt, SDPatternOperator atomic> {
2170
2171 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2172
2173 // No return variants
2174 let glc = 0 in {
2175
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002176 defm _ADDR64 : MUBUFAtomicAddr64_m <
2177 op, name#"_addr64", (outs),
Tom Stellard7980fc82014-09-25 18:30:26 +00002178 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
Tom Stellard49282c92015-02-27 14:59:44 +00002179 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
Matt Arsenault2ad8bab2015-02-18 02:04:35 +00002180 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002181 >;
Tom Stellard7980fc82014-09-25 18:30:26 +00002182
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002183 defm _OFFSET : MUBUFAtomicOffset_m <
2184 op, name#"_offset", (outs),
Tom Stellard49282c92015-02-27 14:59:44 +00002185 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2186 slc:$slc),
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002187 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2188 >;
Tom Stellard7980fc82014-09-25 18:30:26 +00002189 } // glc = 0
2190
2191 // Variant that return values
2192 let glc = 1, Constraints = "$vdata = $vdata_in",
2193 DisableEncoding = "$vdata_in" in {
2194
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002195 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2196 op, name#"_rtn_addr64", (outs rc:$vdata),
Tom Stellard7980fc82014-09-25 18:30:26 +00002197 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
Tom Stellard49282c92015-02-27 14:59:44 +00002198 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
Tom Stellardc53861a2015-02-11 00:34:32 +00002199 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
Tom Stellard7980fc82014-09-25 18:30:26 +00002200 [(set vt:$vdata,
Tom Stellardc53861a2015-02-11 00:34:32 +00002201 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2202 i16:$offset, i1:$slc), vt:$vdata_in))], 1
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002203 >;
Tom Stellard7980fc82014-09-25 18:30:26 +00002204
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002205 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2206 op, name#"_rtn_offset", (outs rc:$vdata),
Tom Stellard49282c92015-02-27 14:59:44 +00002207 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2208 mbuf_offset:$offset, slc:$slc),
Tom Stellard7980fc82014-09-25 18:30:26 +00002209 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2210 [(set vt:$vdata,
2211 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
Marek Olsak19d9e1f2015-01-27 17:25:02 +00002212 i1:$slc), vt:$vdata_in))], 1
2213 >;
Tom Stellard7980fc82014-09-25 18:30:26 +00002214
2215 } // glc = 1
2216
2217 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2218}
2219
Marek Olsakee98b112015-01-27 17:24:58 +00002220multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
Tom Stellard7c1838d2014-07-02 20:53:56 +00002221 ValueType load_vt = i32,
2222 SDPatternOperator ld = null_frag> {
Tom Stellardf1ee7162013-05-20 15:02:31 +00002223
Tom Stellard3e41dc42014-12-09 00:03:54 +00002224 let mayLoad = 1, mayStore = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002225 let offen = 0, idxen = 0, vaddr = 0 in {
2226 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
Tom Stellard49282c92015-02-27 14:59:44 +00002227 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2228 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
Marek Olsak7ef6db42015-01-27 17:24:54 +00002229 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2230 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2231 i32:$soffset, i16:$offset,
2232 i1:$glc, i1:$slc, i1:$tfe)))]>;
Michel Danzer13736222014-01-27 07:20:51 +00002233 }
2234
Marek Olsak7ef6db42015-01-27 17:24:54 +00002235 let offen = 1, idxen = 0 in {
2236 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
Tom Stellardc229baa2015-03-10 16:16:49 +00002237 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002238 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2239 tfe:$tfe),
2240 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2241 }
2242
2243 let offen = 0, idxen = 1 in {
2244 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
Tom Stellardc229baa2015-03-10 16:16:49 +00002245 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
Tom Stellard49282c92015-02-27 14:59:44 +00002246 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002247 slc:$slc, tfe:$tfe),
2248 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2249 }
2250
2251 let offen = 1, idxen = 1 in {
2252 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
Tom Stellardc229baa2015-03-10 16:16:49 +00002253 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
Tom Stellard49282c92015-02-27 14:59:44 +00002254 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
Matt Arsenaultcaa12882015-02-18 02:04:38 +00002255 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
Marek Olsak7ef6db42015-01-27 17:24:54 +00002256 }
2257
Tom Stellard1f9939f2015-02-27 14:59:41 +00002258 let offen = 0, idxen = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002259 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
Tom Stellardc229baa2015-03-10 16:16:49 +00002260 (ins VReg_64:$vaddr, SReg_128:$srsrc,
Tom Stellard1f9939f2015-02-27 14:59:41 +00002261 SCSrc_32:$soffset, mbuf_offset:$offset,
2262 glc:$glc, slc:$slc, tfe:$tfe),
2263 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2264 "$glc"#"$slc"#"$tfe",
Tom Stellard7c1838d2014-07-02 20:53:56 +00002265 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
Tom Stellardc53861a2015-02-11 00:34:32 +00002266 i64:$vaddr, i32:$soffset,
Tom Stellard1f9939f2015-02-27 14:59:41 +00002267 i16:$offset, i1:$glc, i1:$slc,
2268 i1:$tfe)))]>;
Michel Danzer13736222014-01-27 07:20:51 +00002269 }
Tom Stellardf1ee7162013-05-20 15:02:31 +00002270 }
Tom Stellard75aadc22012-12-11 21:25:42 +00002271}
2272
Marek Olsakee98b112015-01-27 17:24:58 +00002273multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
Tom Stellardaec94b32015-02-27 14:59:46 +00002274 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
Tom Stellard42fb60e2015-01-14 15:42:31 +00002275 let mayLoad = 0, mayStore = 1 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002276 defm : MUBUF_m <op, name, (outs),
Tom Stellardc229baa2015-03-10 16:16:49 +00002277 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
Marek Olsak7ef6db42015-01-27 17:24:54 +00002278 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2279 tfe:$tfe),
2280 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
Tom Stellard1f9939f2015-02-27 14:59:41 +00002281 "$glc"#"$slc"#"$tfe", []>;
Tom Stellardddea4862014-08-11 22:18:14 +00002282
Tom Stellard155bbb72014-08-11 22:18:17 +00002283 let offen = 0, idxen = 0, vaddr = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002284 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
Tom Stellard49282c92015-02-27 14:59:44 +00002285 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2286 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
Marek Olsak7ef6db42015-01-27 17:24:54 +00002287 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2288 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2289 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
Tom Stellard155bbb72014-08-11 22:18:17 +00002290 } // offen = 0, idxen = 0, vaddr = 0
2291
Tom Stellardddea4862014-08-11 22:18:14 +00002292 let offen = 1, idxen = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002293 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
Tom Stellardc229baa2015-03-10 16:16:49 +00002294 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
Tom Stellard49282c92015-02-27 14:59:44 +00002295 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2296 slc:$slc, tfe:$tfe),
Marek Olsak7ef6db42015-01-27 17:24:54 +00002297 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2298 "$glc"#"$slc"#"$tfe", []>;
Tom Stellardddea4862014-08-11 22:18:14 +00002299 } // end offen = 1, idxen = 0
2300
Tom Stellarda14b0112015-03-10 16:16:51 +00002301 let offen = 0, idxen = 1 in {
2302 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2303 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2304 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2305 slc:$slc, tfe:$tfe),
2306 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2307 }
2308
2309 let offen = 1, idxen = 1 in {
2310 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2311 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2312 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2313 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2314 }
2315
Tom Stellard1f9939f2015-02-27 14:59:41 +00002316 let offen = 0, idxen = 0 in {
Marek Olsak7ef6db42015-01-27 17:24:54 +00002317 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
Tom Stellardc229baa2015-03-10 16:16:49 +00002318 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2319 SCSrc_32:$soffset,
Tom Stellard1f9939f2015-02-27 14:59:41 +00002320 mbuf_offset:$offset, glc:$glc, slc:$slc,
2321 tfe:$tfe),
2322 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2323 "$offset"#"$glc"#"$slc"#"$tfe",
Marek Olsak7ef6db42015-01-27 17:24:54 +00002324 [(st store_vt:$vdata,
Tom Stellardc53861a2015-02-11 00:34:32 +00002325 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
Tom Stellard1f9939f2015-02-27 14:59:41 +00002326 i32:$soffset, i16:$offset,
2327 i1:$glc, i1:$slc, i1:$tfe))]>;
Marek Olsak7ef6db42015-01-27 17:24:54 +00002328 }
2329 } // End mayLoad = 0, mayStore = 1
Tom Stellard754f80f2013-04-05 23:31:51 +00002330}
2331
Matt Arsenault3f981402014-09-15 15:41:53 +00002332class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
Matt Arsenaulte6c52412015-02-18 02:10:37 +00002333 FLAT <op, (outs regClass:$vdst),
Matt Arsenault3f981402014-09-15 15:41:53 +00002334 (ins VReg_64:$addr),
Matt Arsenaulte6c52412015-02-18 02:10:37 +00002335 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
Matt Arsenault3f981402014-09-15 15:41:53 +00002336 let glc = 0;
2337 let slc = 0;
2338 let tfe = 0;
Matt Arsenaulte6c52412015-02-18 02:10:37 +00002339 let data = 0;
Matt Arsenault3f981402014-09-15 15:41:53 +00002340 let mayLoad = 1;
2341}
2342
2343class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2344 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2345 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2346 []> {
2347
2348 let mayLoad = 0;
2349 let mayStore = 1;
2350
2351 // Encoding
2352 let glc = 0;
2353 let slc = 0;
2354 let tfe = 0;
Matt Arsenaulte6c52412015-02-18 02:10:37 +00002355 let vdst = 0;
Matt Arsenault3f981402014-09-15 15:41:53 +00002356}
2357
Tom Stellard682bfbc2013-10-10 17:11:24 +00002358class MIMG_Mask <string op, int channels> {
2359 string Op = op;
2360 int Channels = channels;
2361}
2362
Tom Stellard16a9a202013-08-14 23:24:17 +00002363class MIMG_NoSampler_Helper <bits<7> op, string asm,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002364 RegisterClass dst_rc,
Tom Stellard16a9a202013-08-14 23:24:17 +00002365 RegisterClass src_rc> : MIMG <
Tom Stellard353b3362013-05-06 23:02:12 +00002366 op,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002367 (outs dst_rc:$vdata),
Tom Stellard353b3362013-05-06 23:02:12 +00002368 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
Tom Stellard16a9a202013-08-14 23:24:17 +00002369 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
Tom Stellard353b3362013-05-06 23:02:12 +00002370 SReg_256:$srsrc),
2371 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2372 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2373 []> {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +00002374 let ssamp = 0;
Tom Stellard353b3362013-05-06 23:02:12 +00002375 let mayLoad = 1;
2376 let mayStore = 0;
2377 let hasPostISelHook = 1;
2378}
2379
Tom Stellard682bfbc2013-10-10 17:11:24 +00002380multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2381 RegisterClass dst_rc,
2382 int channels> {
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002383 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002384 MIMG_Mask<asm#"_V1", channels>;
2385 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2386 MIMG_Mask<asm#"_V2", channels>;
2387 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2388 MIMG_Mask<asm#"_V4", channels>;
2389}
2390
Tom Stellard16a9a202013-08-14 23:24:17 +00002391multiclass MIMG_NoSampler <bits<7> op, string asm> {
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002392 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
Tom Stellard682bfbc2013-10-10 17:11:24 +00002393 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2394 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2395 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
Tom Stellard16a9a202013-08-14 23:24:17 +00002396}
2397
2398class MIMG_Sampler_Helper <bits<7> op, string asm,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002399 RegisterClass dst_rc,
Michel Danzer494391b2015-02-06 02:51:20 +00002400 RegisterClass src_rc, int wqm> : MIMG <
Christian Konig72d5d5c2013-02-21 15:16:44 +00002401 op,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002402 (outs dst_rc:$vdata),
Christian Konig72d5d5c2013-02-21 15:16:44 +00002403 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
Tom Stellard16a9a202013-08-14 23:24:17 +00002404 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
Christian Konig84652962013-03-01 09:46:17 +00002405 SReg_256:$srsrc, SReg_128:$ssamp),
Christian Konig08e768b2013-02-21 15:17:17 +00002406 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2407 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
Christian Konig72d5d5c2013-02-21 15:16:44 +00002408 []> {
2409 let mayLoad = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +00002410 let mayStore = 0;
Christian Konig8b1ed282013-04-10 08:39:16 +00002411 let hasPostISelHook = 1;
Michel Danzer494391b2015-02-06 02:51:20 +00002412 let WQM = wqm;
Tom Stellard75aadc22012-12-11 21:25:42 +00002413}
2414
Tom Stellard682bfbc2013-10-10 17:11:24 +00002415multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2416 RegisterClass dst_rc,
Michel Danzer494391b2015-02-06 02:51:20 +00002417 int channels, int wqm> {
2418 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002419 MIMG_Mask<asm#"_V1", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002420 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002421 MIMG_Mask<asm#"_V2", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002422 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002423 MIMG_Mask<asm#"_V4", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002424 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002425 MIMG_Mask<asm#"_V8", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002426 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
Tom Stellard682bfbc2013-10-10 17:11:24 +00002427 MIMG_Mask<asm#"_V16", channels>;
2428}
2429
Tom Stellard16a9a202013-08-14 23:24:17 +00002430multiclass MIMG_Sampler <bits<7> op, string asm> {
Michel Danzer494391b2015-02-06 02:51:20 +00002431 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2432 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2433 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2434 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2435}
2436
2437multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2438 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2439 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2440 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2441 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
Tom Stellard16a9a202013-08-14 23:24:17 +00002442}
2443
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002444class MIMG_Gather_Helper <bits<7> op, string asm,
2445 RegisterClass dst_rc,
Michel Danzer494391b2015-02-06 02:51:20 +00002446 RegisterClass src_rc, int wqm> : MIMG <
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002447 op,
2448 (outs dst_rc:$vdata),
2449 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2450 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2451 SReg_256:$srsrc, SReg_128:$ssamp),
2452 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2453 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2454 []> {
2455 let mayLoad = 1;
2456 let mayStore = 0;
2457
2458 // DMASK was repurposed for GATHER4. 4 components are always
2459 // returned and DMASK works like a swizzle - it selects
2460 // the component to fetch. The only useful DMASK values are
2461 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2462 // (red,red,red,red) etc.) The ISA document doesn't mention
2463 // this.
2464 // Therefore, disable all code which updates DMASK by setting these two:
2465 let MIMG = 0;
2466 let hasPostISelHook = 0;
Michel Danzer494391b2015-02-06 02:51:20 +00002467 let WQM = wqm;
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002468}
2469
2470multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2471 RegisterClass dst_rc,
Michel Danzer494391b2015-02-06 02:51:20 +00002472 int channels, int wqm> {
2473 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002474 MIMG_Mask<asm#"_V1", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002475 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002476 MIMG_Mask<asm#"_V2", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002477 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002478 MIMG_Mask<asm#"_V4", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002479 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002480 MIMG_Mask<asm#"_V8", channels>;
Michel Danzer494391b2015-02-06 02:51:20 +00002481 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002482 MIMG_Mask<asm#"_V16", channels>;
2483}
2484
2485multiclass MIMG_Gather <bits<7> op, string asm> {
Michel Danzer494391b2015-02-06 02:51:20 +00002486 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2487 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2488 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2489 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2490}
2491
2492multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2493 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2494 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2495 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2496 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
Marek Olsak51b8e7b2014-06-18 22:00:29 +00002497}
2498
Christian Konigf741fbf2013-02-26 17:52:42 +00002499//===----------------------------------------------------------------------===//
2500// Vector instruction mappings
2501//===----------------------------------------------------------------------===//
2502
2503// Maps an opcode in e32 form to its e64 equivalent
2504def getVOPe64 : InstrMapping {
2505 let FilterClass = "VOP";
2506 let RowFields = ["OpName"];
2507 let ColFields = ["Size"];
2508 let KeyCol = ["4"];
2509 let ValueCols = [["8"]];
2510}
2511
Tom Stellard1aaad692014-07-21 16:55:33 +00002512// Maps an opcode in e64 form to its e32 equivalent
2513def getVOPe32 : InstrMapping {
2514 let FilterClass = "VOP";
2515 let RowFields = ["OpName"];
2516 let ColFields = ["Size"];
2517 let KeyCol = ["8"];
2518 let ValueCols = [["4"]];
2519}
2520
Tom Stellard682bfbc2013-10-10 17:11:24 +00002521def getMaskedMIMGOp : InstrMapping {
2522 let FilterClass = "MIMG_Mask";
2523 let RowFields = ["Op"];
2524 let ColFields = ["Channels"];
2525 let KeyCol = ["4"];
2526 let ValueCols = [["1"], ["2"], ["3"] ];
2527}
2528
Christian Konig3c145802013-03-27 09:12:59 +00002529// Maps an commuted opcode to its original version
2530def getCommuteOrig : InstrMapping {
2531 let FilterClass = "VOP2_REV";
2532 let RowFields = ["RevOp"];
2533 let ColFields = ["IsOrig"];
2534 let KeyCol = ["0"];
2535 let ValueCols = [["1"]];
2536}
2537
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00002538// Maps an original opcode to its commuted version
2539def getCommuteRev : InstrMapping {
2540 let FilterClass = "VOP2_REV";
2541 let RowFields = ["RevOp"];
2542 let ColFields = ["IsOrig"];
2543 let KeyCol = ["1"];
2544 let ValueCols = [["0"]];
2545}
2546
2547def getCommuteCmpOrig : InstrMapping {
Matt Arsenault88a13c62015-03-23 18:45:41 +00002548 let FilterClass = "VOP2_REV";
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00002549 let RowFields = ["RevOp"];
2550 let ColFields = ["IsOrig"];
2551 let KeyCol = ["0"];
2552 let ValueCols = [["1"]];
2553}
2554
2555// Maps an original opcode to its commuted version
2556def getCommuteCmpRev : InstrMapping {
Matt Arsenault88a13c62015-03-23 18:45:41 +00002557 let FilterClass = "VOP2_REV";
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +00002558 let RowFields = ["RevOp"];
2559 let ColFields = ["IsOrig"];
2560 let KeyCol = ["1"];
2561 let ValueCols = [["0"]];
2562}
2563
2564
Marek Olsak5df00d62014-12-07 12:18:57 +00002565def getMCOpcodeGen : InstrMapping {
Tom Stellardc721a232014-05-16 20:56:47 +00002566 let FilterClass = "SIMCInstr";
2567 let RowFields = ["PseudoInstr"];
2568 let ColFields = ["Subtarget"];
2569 let KeyCol = [!cast<string>(SISubtarget.NONE)];
Marek Olsak5df00d62014-12-07 12:18:57 +00002570 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
Tom Stellardc721a232014-05-16 20:56:47 +00002571}
2572
Tom Stellard155bbb72014-08-11 22:18:17 +00002573def getAddr64Inst : InstrMapping {
2574 let FilterClass = "MUBUFAddr64Table";
Tom Stellard7980fc82014-09-25 18:30:26 +00002575 let RowFields = ["OpName"];
Tom Stellard155bbb72014-08-11 22:18:17 +00002576 let ColFields = ["IsAddr64"];
2577 let KeyCol = ["0"];
2578 let ValueCols = [["1"]];
2579}
2580
Matt Arsenault9903ccf2014-09-08 15:07:27 +00002581// Maps an atomic opcode to its version with a return value.
2582def getAtomicRetOp : InstrMapping {
2583 let FilterClass = "AtomicNoRet";
2584 let RowFields = ["NoRetOp"];
2585 let ColFields = ["IsRet"];
2586 let KeyCol = ["0"];
2587 let ValueCols = [["1"]];
2588}
2589
2590// Maps an atomic opcode to its returnless version.
2591def getAtomicNoRetOp : InstrMapping {
2592 let FilterClass = "AtomicNoRet";
2593 let RowFields = ["NoRetOp"];
2594 let ColFields = ["IsRet"];
2595 let KeyCol = ["1"];
2596 let ValueCols = [["0"]];
2597}
2598
Tom Stellard75aadc22012-12-11 21:25:42 +00002599include "SIInstructions.td"
Marek Olsak5df00d62014-12-07 12:18:57 +00002600include "CIInstructions.td"
2601include "VIInstructions.td"