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gerrit-public.fairphone.software / toolchain / llvm-project / 4e2ef472d21deece3aac11bd9076ab87023bb9c0 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: f3c87ccc8ebf7d65350605eeb9e6b3a8582253a8 [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]82}
83
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]84def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
85def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]86def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
87def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]88def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
89def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]90
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]91// "x" in v32i8x_info means RC = VR256X
92def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
93def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
94def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
95def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
96
97def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
98def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
99def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
100def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
101
102class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
103 X86VectorVTInfo i128> {
104 X86VectorVTInfo info512 = i512;
105 X86VectorVTInfo info256 = i256;
106 X86VectorVTInfo info128 = i128;
107}
108
109def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
110 v16i8x_info>;
111def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
112 v8i16x_info>;
113def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
114 v4i32x_info>;
115def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
116 v2i64x_info>;
117
118
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]119// Common base class of AVX512_masking and AVX512_masking_3src.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]120multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
121 dag Outs,
122 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]123 string OpcodeStr,
124 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]125 dag RHS, dag MaskingRHS,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]126 string MaskingConstraint = ""> {
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]127 def NAME: AVX512<O, F, Outs, Ins,
Adam Nemet05d8c8e2014-10-01 00:41:32 +0000[diff] [blame]128 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
129 "$dst, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]130 [(set _.RC:$dst, RHS)]>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]131
Adam Nemetfa1f7202014-08-07 23:18:18 +0000[diff] [blame]132 // Prefer over VMOV*rrk Pat<>
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]133 let AddedComplexity = 20 in
134 def NAME#k: AVX512<O, F, Outs, MaskingIns,
Adam Nemet05d8c8e2014-10-01 00:41:32 +0000[diff] [blame]135 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
136 "$dst {${mask}}, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]137 [(set _.RC:$dst, MaskingRHS)]>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]138 EVEX_K {
139 // In case of the 3src subclass this is overridden with a let.
140 string Constraints = MaskingConstraint;
141 }
Adam Nemet7d498622014-08-07 23:53:38 +0000[diff] [blame]142 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]143 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
Adam Nemet05d8c8e2014-10-01 00:41:32 +0000[diff] [blame]144 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
145 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]146 [(set _.RC:$dst,
147 (vselect _.KRCWM:$mask, RHS,
148 (_.VT (bitconvert
Adam Nemet7d498622014-08-07 23:53:38 +0000[diff] [blame]149 (v16i32 immAllZerosV)))))]>,
150 EVEX_KZ;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]151}
152
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]153// This multiclass generates the unconditional/non-masking, the masking and
154// the zero-masking variant of the instruction. In the masking case, the
155// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]156multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
157 dag Outs, dag Ins, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]158 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]159 dag RHS> :
160 AVX512_masking_common<O, F, _, Outs, Ins,
161 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
162 !con((ins _.KRCWM:$mask), Ins),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]163 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]164 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]165 "$src0 = $dst">;
166
167// Similar to AVX512_masking but in this case one of the source operands
168// ($src1) is already tied to $dst so we just use that for the preserved
169// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
170// $src1.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]171multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
172 dag Outs, dag NonTiedIns, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]173 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]174 dag RHS> :
175 AVX512_masking_common<O, F, _, Outs,
176 !con((ins _.RC:$src1), NonTiedIns),
177 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
178 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]179 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]180 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]181
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]182// Bitcasts between 512-bit vector types. Return the original type since
183// no instruction is needed for the conversion
184let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]185 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]186 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]187 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
188 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
189 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]190 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]191 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
192 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
193 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]194 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]195 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]196 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
197 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]198 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]199 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
200 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]201 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]202 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
203 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]204 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]205 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
206 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
207 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
208 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
209 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
210 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
211 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
212 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
213 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
214 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
215 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]216
217 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
218 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
219 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
220 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
221 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
222 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
223 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
224 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
225 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
226 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
227 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
228 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
229 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
230 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
231 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
232 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
233 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
234 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
235 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
236 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
237 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
238 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
239 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
240 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
241 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
242 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
243 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
244 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
245 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
246 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
247
248// Bitcasts between 256-bit vector types. Return the original type since
249// no instruction is needed for the conversion
250 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
251 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
252 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
253 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
254 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
255 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
256 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
257 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
258 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
259 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
260 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
261 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
262 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
263 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
264 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
265 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
266 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
267 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
268 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
269 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
270 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
271 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
272 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
273 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
274 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
275 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
276 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
277 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
278 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
279 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
280}
281
282//
283// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
284//
285
286let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
287 isPseudo = 1, Predicates = [HasAVX512] in {
288def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
289 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
290}
291
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]292let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]293def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
294def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
295def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]296}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]297
298//===----------------------------------------------------------------------===//
299// AVX-512 - VECTOR INSERT
300//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame^]301
302multiclass vinsert_for_size<int Opcode,
303 X86VectorVTInfo From, X86VectorVTInfo To,
304 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
305 PatFrag vinsert_insert,
306 SDNodeXForm INSERT_get_vinsert_imm> {
307 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
308 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
309 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
310 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
311 "$dst, $src1, $src2, $src3}",
312 []>, EVEX_4V, EVEX_V512;
313
314 let mayLoad = 1 in
315 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
316 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
317 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
318 "$dst, $src1, $src2, $src3}",
319 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
320 }
321
322 // Codegen pattern, e.g. v4i32 -> v16i32 for vinserti32x4
323 def : Pat<(vinsert_insert:$ins
324 (To.VT VR512:$src1), (From.VT From.RC:$src2), (iPTR imm)),
325 (To.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
326 VR512:$src1, From.RC:$src2,
327 (INSERT_get_vinsert_imm VR512:$ins)))>;
328
329 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
330 // vinserti32x4
331 def : Pat<(vinsert_insert:$ins
332 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
333 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
334 VR512:$src1, From.RC:$src2,
335 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]336}
337
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame^]338multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
339 ValueType EltVT64, int Opcode64> {
340 defm NAME # "32x4" : vinsert_for_size<Opcode32,
341 X86VectorVTInfo< 4, EltVT32, VR128X>,
342 X86VectorVTInfo<16, EltVT32, VR512>,
343 X86VectorVTInfo< 2, EltVT64, VR128X>,
344 X86VectorVTInfo< 8, EltVT64, VR512>,
345 vinsert128_insert,
346 INSERT_get_vinsert128_imm>;
347 defm NAME # "64x4" : vinsert_for_size<Opcode64,
348 X86VectorVTInfo< 4, EltVT64, VR256X>,
349 X86VectorVTInfo< 8, EltVT64, VR512>,
350 X86VectorVTInfo< 8, EltVT32, VR256>,
351 X86VectorVTInfo<16, EltVT32, VR512>,
352 vinsert256_insert,
353 INSERT_get_vinsert256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]354}
355
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame^]356defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
357defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]358
359// vinsertps - insert f32 to XMM
360def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]361 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]362 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]363 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]364 EVEX_4V;
365def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]366 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]367 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]368 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]369 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
370 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
371
372//===----------------------------------------------------------------------===//
373// AVX-512 VECTOR EXTRACT
374//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]375
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]376multiclass vextract_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vextract_extract,
380 SDNodeXForm EXTRACT_get_vextract_imm> {
381 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
382 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
Adam Nemetf7988d72014-09-25 23:48:49 +0000[diff] [blame]383 (ins VR512:$src1, i8imm:$idx),
384 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
385 "$dst, $src1, $idx}",
386 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
387 (iPTR imm)))]>,
388 EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]389 let mayStore = 1 in
390 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
391 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
392 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
393 "$dst, $src1, $src2}",
394 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
395 }
396
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]397 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
398 // vextracti32x4
399 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
400 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
401 VR512:$src1,
402 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
403
404 // A 128/256-bit subvector extract from the first 512-bit vector position is
405 // a subregister copy that needs no instruction.
406 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
407 (To.VT
408 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
409
410 // And for the alternative types.
411 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
412 (AltTo.VT
413 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]414}
415
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]416multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
417 ValueType EltVT64, int Opcode64> {
418 defm NAME # "32x4" : vextract_for_size<Opcode32,
419 X86VectorVTInfo<16, EltVT32, VR512>,
420 X86VectorVTInfo< 4, EltVT32, VR128X>,
421 X86VectorVTInfo< 8, EltVT64, VR512>,
422 X86VectorVTInfo< 2, EltVT64, VR128X>,
423 vextract128_extract,
424 EXTRACT_get_vextract128_imm>;
425 defm NAME # "64x4" : vextract_for_size<Opcode64,
426 X86VectorVTInfo< 8, EltVT64, VR512>,
427 X86VectorVTInfo< 4, EltVT64, VR256X>,
428 X86VectorVTInfo<16, EltVT32, VR512>,
429 X86VectorVTInfo< 8, EltVT32, VR256>,
430 vextract256_extract,
431 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]432}
433
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]434defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
435defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]436
437// A 128-bit subvector insert to the first 512-bit vector position
438// is a subregister copy that needs no instruction.
439def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
440 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
441 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
442 sub_ymm)>;
443def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
444 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
445 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
446 sub_ymm)>;
447def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
448 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
449 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
450 sub_ymm)>;
451def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
452 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
453 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
454 sub_ymm)>;
455
456def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
457 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
458def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
459 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
460def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
461 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
462def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
463 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
464
465// vextractps - extract 32 bits from XMM
466def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]467 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]468 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]469 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
470 EVEX;
471
472def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]473 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]474 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]475 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]476 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]477
478//===---------------------------------------------------------------------===//
479// AVX-512 BROADCAST
480//---
481multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
482 RegisterClass DestRC,
483 RegisterClass SrcRC, X86MemOperand x86memop> {
484 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]485 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]486 []>, EVEX;
487 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]488 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]489}
490let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]491 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]492 VR128X, f32mem>,
493 EVEX_V512, EVEX_CD8<32, CD8VT1>;
494}
495
496let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]497 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]498 VR128X, f64mem>,
499 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
500}
501
502def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
503 (VBROADCASTSSZrm addr:$src)>;
504def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
505 (VBROADCASTSDZrm addr:$src)>;
506
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]507def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
508 (VBROADCASTSSZrm addr:$src)>;
509def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
510 (VBROADCASTSDZrm addr:$src)>;
511
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]512multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
513 RegisterClass SrcRC, RegisterClass KRC> {
514 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]515 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]516 []>, EVEX, EVEX_V512;
517 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
518 (ins KRC:$mask, SrcRC:$src),
519 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]520 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]521 []>, EVEX, EVEX_V512, EVEX_KZ;
522}
523
524defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
525defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
526 VEX_W;
527
528def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
529 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
530
531def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
532 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
533
534def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
535 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]536def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
537 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]538def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
539 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]540def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
541 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]542
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]543def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
544 (VPBROADCASTDrZrr GR32:$src)>;
545def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
546 (VPBROADCASTQrZrr GR64:$src)>;
547
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]548def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
549 (v16i32 immAllZerosV), (i16 GR16:$mask))),
550 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
551def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
552 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
553 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
554
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]555multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
556 X86MemOperand x86memop, PatFrag ld_frag,
557 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
558 RegisterClass KRC> {
559 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]560 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]561 [(set DstRC:$dst,
562 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
563 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
564 VR128X:$src),
565 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]566 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]567 [(set DstRC:$dst,
568 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
569 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]570 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]571 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]572 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]573 [(set DstRC:$dst,
574 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
575 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
576 x86memop:$src),
577 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]578 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]579 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
580 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]581 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]582}
583
584defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
585 loadi32, VR512, v16i32, v4i32, VK16WM>,
586 EVEX_V512, EVEX_CD8<32, CD8VT1>;
587defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
588 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
589 EVEX_CD8<64, CD8VT1>;
590
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]591multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
592 X86MemOperand x86memop, PatFrag ld_frag,
593 RegisterClass KRC> {
594 let mayLoad = 1 in {
595 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
596 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
597 []>, EVEX;
598 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
599 x86memop:$src),
600 !strconcat(OpcodeStr,
601 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
602 []>, EVEX, EVEX_KZ;
603 }
604}
605
606defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
607 i128mem, loadv2i64, VK16WM>,
608 EVEX_V512, EVEX_CD8<32, CD8VT4>;
609defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
610 i256mem, loadv4i64, VK16WM>, VEX_W,
611 EVEX_V512, EVEX_CD8<64, CD8VT4>;
612
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]613def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
614 (VPBROADCASTDZrr VR128X:$src)>;
615def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
616 (VPBROADCASTQZrr VR128X:$src)>;
617
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]618def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
619 (VBROADCASTSSZrr VR128X:$src)>;
620def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
621 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]622
623def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
624 (VBROADCASTSSZrr VR128X:$src)>;
625def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
626 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]627
628// Provide fallback in case the load node that is used in the patterns above
629// is used by additional users, which prevents the pattern selection.
630def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
631 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
632def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
633 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
634
635
636let Predicates = [HasAVX512] in {
637def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
638 (EXTRACT_SUBREG
639 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
640 addr:$src)), sub_ymm)>;
641}
642//===----------------------------------------------------------------------===//
643// AVX-512 BROADCAST MASK TO VECTOR REGISTER
644//---
645
646multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
647 RegisterClass DstRC, RegisterClass KRC,
648 ValueType OpVT, ValueType SrcVT> {
649def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]650 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]651 []>, EVEX;
652}
653
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]654let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]655defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
656 VK16, v16i32, v16i1>, EVEX_V512;
657defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
658 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]659}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]660
661//===----------------------------------------------------------------------===//
662// AVX-512 - VPERM
663//
664// -- immediate form --
665multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
666 SDNode OpNode, PatFrag mem_frag,
667 X86MemOperand x86memop, ValueType OpVT> {
668 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
669 (ins RC:$src1, i8imm:$src2),
670 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]671 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]672 [(set RC:$dst,
673 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
674 EVEX;
675 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
676 (ins x86memop:$src1, i8imm:$src2),
677 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]678 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]679 [(set RC:$dst,
680 (OpVT (OpNode (mem_frag addr:$src1),
681 (i8 imm:$src2))))]>, EVEX;
682}
683
684defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
685 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
686let ExeDomain = SSEPackedDouble in
687defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
688 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
689
690// -- VPERM - register form --
691multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
692 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
693
694 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
695 (ins RC:$src1, RC:$src2),
696 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]697 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]698 [(set RC:$dst,
699 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
700
701 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
702 (ins RC:$src1, x86memop:$src2),
703 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]704 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]705 [(set RC:$dst,
706 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
707 EVEX_4V;
708}
709
710defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
711 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
712defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
713 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
714let ExeDomain = SSEPackedSingle in
715defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
716 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
717let ExeDomain = SSEPackedDouble in
718defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
719 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
720
721// -- VPERM2I - 3 source operands form --
722multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
723 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]724 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]725let Constraints = "$src1 = $dst" in {
726 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
727 (ins RC:$src1, RC:$src2, RC:$src3),
728 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]729 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]730 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]731 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]732 EVEX_4V;
733
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]734 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
735 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
736 !strconcat(OpcodeStr,
737 " \t{$src3, $src2, $dst {${mask}}|"
738 "$dst {${mask}}, $src2, $src3}"),
739 [(set RC:$dst, (OpVT (vselect KRC:$mask,
740 (OpNode RC:$src1, RC:$src2,
741 RC:$src3),
742 RC:$src1)))]>,
743 EVEX_4V, EVEX_K;
744
745 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
746 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
748 !strconcat(OpcodeStr,
749 " \t{$src3, $src2, $dst {${mask}} {z} |",
750 "$dst {${mask}} {z}, $src2, $src3}"),
751 [(set RC:$dst, (OpVT (vselect KRC:$mask,
752 (OpNode RC:$src1, RC:$src2,
753 RC:$src3),
754 (OpVT (bitconvert
755 (v16i32 immAllZerosV))))))]>,
756 EVEX_4V, EVEX_KZ;
757
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]758 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
759 (ins RC:$src1, RC:$src2, x86memop:$src3),
760 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]761 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]762 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]763 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]764 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]765
766 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
767 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
768 !strconcat(OpcodeStr,
769 " \t{$src3, $src2, $dst {${mask}}|"
770 "$dst {${mask}}, $src2, $src3}"),
771 [(set RC:$dst,
772 (OpVT (vselect KRC:$mask,
773 (OpNode RC:$src1, RC:$src2,
774 (mem_frag addr:$src3)),
775 RC:$src1)))]>,
776 EVEX_4V, EVEX_K;
777
778 let AddedComplexity = 10 in // Prefer over the rrkz variant
779 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
780 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
781 !strconcat(OpcodeStr,
782 " \t{$src3, $src2, $dst {${mask}} {z}|"
783 "$dst {${mask}} {z}, $src2, $src3}"),
784 [(set RC:$dst,
785 (OpVT (vselect KRC:$mask,
786 (OpNode RC:$src1, RC:$src2,
787 (mem_frag addr:$src3)),
788 (OpVT (bitconvert
789 (v16i32 immAllZerosV))))))]>,
790 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]791 }
792}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]793defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
794 i512mem, X86VPermiv3, v16i32, VK16WM>,
795 EVEX_V512, EVEX_CD8<32, CD8VF>;
796defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
797 i512mem, X86VPermiv3, v8i64, VK8WM>,
798 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
799defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
800 i512mem, X86VPermiv3, v16f32, VK16WM>,
801 EVEX_V512, EVEX_CD8<32, CD8VF>;
802defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
803 i512mem, X86VPermiv3, v8f64, VK8WM>,
804 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]805
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]806multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
807 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]808 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
809 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]810 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
811 OpVT, KRC> {
812 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
813 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
814 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]815
816 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
817 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
818 (!cast<Instruction>(NAME#rrk) VR512:$src1,
819 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]820}
821
822defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]823 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
824 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]825defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]826 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
827 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]828defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]829 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
830 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]831defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]832 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
833 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]834
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]835//===----------------------------------------------------------------------===//
836// AVX-512 - BLEND using mask
837//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]838multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]839 RegisterClass KRC, RegisterClass RC,
840 X86MemOperand x86memop, PatFrag mem_frag,
841 SDNode OpNode, ValueType vt> {
842 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]843 (ins KRC:$mask, RC:$src1, RC:$src2),
844 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]845 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]846 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]847 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]848 let mayLoad = 1 in
849 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
850 (ins KRC:$mask, RC:$src1, x86memop:$src2),
851 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]852 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]853 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]854}
855
856let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]857defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]858 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]859 memopv16f32, vselect, v16f32>,
860 EVEX_CD8<32, CD8VF>, EVEX_V512;
861let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]862defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]863 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]864 memopv8f64, vselect, v8f64>,
865 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
866
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]867def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
868 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]869 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]870 VR512:$src1, VR512:$src2)>;
871
872def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
873 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]874 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]875 VR512:$src1, VR512:$src2)>;
876
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]877defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]878 VK16WM, VR512, f512mem,
879 memopv16i32, vselect, v16i32>,
880 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]881
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]882defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]883 VK8WM, VR512, f512mem,
884 memopv8i64, vselect, v8i64>,
885 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]886
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]887def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
888 (v16i32 VR512:$src2), (i16 GR16:$mask))),
889 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
890 VR512:$src1, VR512:$src2)>;
891
892def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
893 (v8i64 VR512:$src2), (i8 GR8:$mask))),
894 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
895 VR512:$src1, VR512:$src2)>;
896
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]897let Predicates = [HasAVX512] in {
898def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
899 (v8f32 VR256X:$src2))),
900 (EXTRACT_SUBREG
901 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
902 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
903 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
904
905def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
906 (v8i32 VR256X:$src2))),
907 (EXTRACT_SUBREG
908 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
909 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
910 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
911}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]912//===----------------------------------------------------------------------===//
913// Compare Instructions
914//===----------------------------------------------------------------------===//
915
916// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
917multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
918 Operand CC, SDNode OpNode, ValueType VT,
919 PatFrag ld_frag, string asm, string asm_alt> {
920 def rr : AVX512Ii8<0xC2, MRMSrcReg,
921 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
922 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
923 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
924 def rm : AVX512Ii8<0xC2, MRMSrcMem,
925 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
926 [(set VK1:$dst, (OpNode (VT RC:$src1),
927 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]928 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]929 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
930 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
931 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
932 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
933 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
934 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
935 }
936}
937
938let Predicates = [HasAVX512] in {
939defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
940 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
941 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
942 XS;
943defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
944 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
945 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
946 XD, VEX_W;
947}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]948
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]949multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
950 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]951 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]952 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
953 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]955 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]956 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]957 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]958 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
959 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
960 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
961 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]962 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]963 def rrk : AVX512BI<opc, MRMSrcReg,
964 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
965 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
966 "$dst {${mask}}, $src1, $src2}"),
967 [(set _.KRC:$dst, (and _.KRCWM:$mask,
968 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
969 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
970 let mayLoad = 1 in
971 def rmk : AVX512BI<opc, MRMSrcMem,
972 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
974 "$dst {${mask}}, $src1, $src2}"),
975 [(set _.KRC:$dst, (and _.KRCWM:$mask,
976 (OpNode (_.VT _.RC:$src1),
977 (_.VT (bitconvert
978 (_.LdFrag addr:$src2))))))],
979 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]980}
981
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]982multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]983 X86VectorVTInfo _> :
984 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]985 let mayLoad = 1 in {
986 def rmb : AVX512BI<opc, MRMSrcMem,
987 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
988 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
989 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
990 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
991 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
992 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
993 def rmbk : AVX512BI<opc, MRMSrcMem,
994 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
995 _.ScalarMemOp:$src2),
996 !strconcat(OpcodeStr,
997 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
998 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
999 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1000 (OpNode (_.VT _.RC:$src1),
1001 (X86VBroadcast
1002 (_.ScalarLdFrag addr:$src2)))))],
1003 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1004 }
1005}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1006
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1007multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1009 let Predicates = [prd] in
1010 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1011 EVEX_V512;
1012
1013 let Predicates = [prd, HasVLX] in {
1014 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1015 EVEX_V256;
1016 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1017 EVEX_V128;
1018 }
1019}
1020
1021multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1022 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1023 Predicate prd> {
1024 let Predicates = [prd] in
1025 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1026 EVEX_V512;
1027
1028 let Predicates = [prd, HasVLX] in {
1029 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1030 EVEX_V256;
1031 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1032 EVEX_V128;
1033 }
1034}
1035
1036defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1037 avx512vl_i8_info, HasBWI>,
1038 EVEX_CD8<8, CD8VF>;
1039
1040defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1041 avx512vl_i16_info, HasBWI>,
1042 EVEX_CD8<16, CD8VF>;
1043
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1044defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1045 avx512vl_i32_info, HasAVX512>,
1046 EVEX_CD8<32, CD8VF>;
1047
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1048defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1049 avx512vl_i64_info, HasAVX512>,
1050 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1051
1052defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1053 avx512vl_i8_info, HasBWI>,
1054 EVEX_CD8<8, CD8VF>;
1055
1056defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1057 avx512vl_i16_info, HasBWI>,
1058 EVEX_CD8<16, CD8VF>;
1059
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1060defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1061 avx512vl_i32_info, HasAVX512>,
1062 EVEX_CD8<32, CD8VF>;
1063
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1064defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1065 avx512vl_i64_info, HasAVX512>,
1066 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1067
1068def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1069 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1070 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1071 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1072
1073def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1074 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1075 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1076 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1077
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1078multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1079 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1080 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1081 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1082 !strconcat("vpcmp${cc}", Suffix,
1083 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1084 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1085 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1086 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1087 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1088 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1089 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1090 !strconcat("vpcmp${cc}", Suffix,
1091 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1092 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1093 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1094 imm:$cc))],
1095 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1096 def rrik : AVX512AIi8<opc, MRMSrcReg,
1097 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1098 AVXCC:$cc),
1099 !strconcat("vpcmp${cc}", Suffix,
1100 "\t{$src2, $src1, $dst {${mask}}|",
1101 "$dst {${mask}}, $src1, $src2}"),
1102 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1103 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1104 imm:$cc)))],
1105 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1106 let mayLoad = 1 in
1107 def rmik : AVX512AIi8<opc, MRMSrcMem,
1108 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1109 AVXCC:$cc),
1110 !strconcat("vpcmp${cc}", Suffix,
1111 "\t{$src2, $src1, $dst {${mask}}|",
1112 "$dst {${mask}}, $src1, $src2}"),
1113 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1114 (OpNode (_.VT _.RC:$src1),
1115 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1116 imm:$cc)))],
1117 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1118
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1119 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1120 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1121 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1122 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1123 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1124 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1125 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1126 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1127 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1128 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1129 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1130 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1131 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1132 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1133 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1134 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1135 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1136 "$dst {${mask}}, $src1, $src2, $cc}"),
1137 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1138 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1139 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1140 i8imm:$cc),
1141 !strconcat("vpcmp", Suffix,
1142 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1143 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1144 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1145 }
1146}
1147
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1148multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1149 X86VectorVTInfo _> :
1150 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1151 let mayLoad = 1 in {
1152 def rmib : AVX512AIi8<opc, MRMSrcMem,
1153 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1154 AVXCC:$cc),
1155 !strconcat("vpcmp${cc}", Suffix,
1156 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1157 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1158 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1159 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1160 imm:$cc))],
1161 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1162 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1163 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1164 _.ScalarMemOp:$src2, AVXCC:$cc),
1165 !strconcat("vpcmp${cc}", Suffix,
1166 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1167 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1168 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1169 (OpNode (_.VT _.RC:$src1),
1170 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1171 imm:$cc)))],
1172 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1173 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1174
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1175 // Accept explicit immediate argument form instead of comparison code.
1176 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1177 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1178 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1179 i8imm:$cc),
1180 !strconcat("vpcmp", Suffix,
1181 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1182 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1183 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1184 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1185 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1186 _.ScalarMemOp:$src2, i8imm:$cc),
1187 !strconcat("vpcmp", Suffix,
1188 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1189 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1190 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1191 }
1192}
1193
1194multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1195 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1196 let Predicates = [prd] in
1197 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1198
1199 let Predicates = [prd, HasVLX] in {
1200 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1201 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1202 }
1203}
1204
1205multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1206 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1207 let Predicates = [prd] in
1208 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1209 EVEX_V512;
1210
1211 let Predicates = [prd, HasVLX] in {
1212 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1213 EVEX_V256;
1214 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1215 EVEX_V128;
1216 }
1217}
1218
1219defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1220 HasBWI>, EVEX_CD8<8, CD8VF>;
1221defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1222 HasBWI>, EVEX_CD8<8, CD8VF>;
1223
1224defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1225 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1226defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1227 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1228
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1229defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1230 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1231defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1232 HasAVX512>, EVEX_CD8<32, CD8VF>;
1233
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1234defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1235 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1236defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1237 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1238
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1239// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1240multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1241 X86MemOperand x86memop, ValueType vt,
1242 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1243 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1244 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1245 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1246 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1247 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1248 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1249 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1250 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1251 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1252 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1254 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1255 !strconcat("vcmp${cc}", suffix,
1256 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1257 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1258 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1259
1260 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1261 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1262 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1263 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1264 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1265 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1266 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1267 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1268 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1269 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1270 }
1271}
1272
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1273defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1274 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1275 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1276defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1277 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1278 EVEX_CD8<64, CD8VF>;
1279
1280def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1281 (COPY_TO_REGCLASS (VCMPPSZrri
1282 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1283 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1284 imm:$cc), VK8)>;
1285def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1286 (COPY_TO_REGCLASS (VPCMPDZrri
1287 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1288 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1289 imm:$cc), VK8)>;
1290def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1291 (COPY_TO_REGCLASS (VPCMPUDZrri
1292 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1293 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1294 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1295
1296def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1297 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1298 FROUND_NO_EXC)),
1299 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1300 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1301
1302def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1303 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1304 FROUND_NO_EXC)),
1305 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1306 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1307
1308def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1309 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1310 FROUND_CURRENT)),
1311 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1312 (I8Imm imm:$cc)), GR16)>;
1313
1314def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1315 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1316 FROUND_CURRENT)),
1317 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1318 (I8Imm imm:$cc)), GR8)>;
1319
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1320// Mask register copy, including
1321// - copy between mask registers
1322// - load/store mask registers
1323// - copy from GPR to mask register and vice versa
1324//
1325multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1326 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1327 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1328 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1329 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1330 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1331 let mayLoad = 1 in
1332 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1333 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1334 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1335 let mayStore = 1 in
1336 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1337 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1338 }
1339}
1340
1341multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1342 string OpcodeStr,
1343 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1344 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1345 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1346 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1347 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1348 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1349 }
1350}
1351
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1352let Predicates = [HasDQI] in
1353 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1354 i8mem>,
1355 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1356 VEX, PD;
1357
1358let Predicates = [HasAVX512] in
1359 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1360 i16mem>,
1361 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1362 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1363
1364let Predicates = [HasBWI] in {
1365 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1366 i32mem>, VEX, PD, VEX_W;
1367 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1368 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1369}
1370
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1371let Predicates = [HasBWI] in {
1372 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1373 i64mem>, VEX, PS, VEX_W;
1374 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1375 VEX, XD, VEX_W;
1376}
1377
1378// GR from/to mask register
1379let Predicates = [HasDQI] in {
1380 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1381 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1382 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1383 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1384}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1385let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1386 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1387 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1388 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1389 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1390}
1391let Predicates = [HasBWI] in {
1392 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1393 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1394}
1395let Predicates = [HasBWI] in {
1396 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1397 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1398}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1399
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1400// Load/store kreg
1401let Predicates = [HasDQI] in {
1402 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1403 (KMOVBmk addr:$dst, VK8:$src)>;
1404}
1405let Predicates = [HasAVX512] in {
1406 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1407 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1408 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1409 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1410 def : Pat<(i1 (load addr:$src)),
1411 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1412 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1413 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1414}
1415let Predicates = [HasBWI] in {
1416 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1417 (KMOVDmk addr:$dst, VK32:$src)>;
1418}
1419let Predicates = [HasBWI] in {
1420 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1421 (KMOVQmk addr:$dst, VK64:$src)>;
1422}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1423
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1424let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1425 def : Pat<(i1 (trunc (i64 GR64:$src))),
1426 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1427 (i32 1))), VK1)>;
1428
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1429 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1430 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1431
1432 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1433 (COPY_TO_REGCLASS
1434 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1435 VK1)>;
1436 def : Pat<(i1 (trunc (i16 GR16:$src))),
1437 (COPY_TO_REGCLASS
1438 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1439 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1440
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1441 def : Pat<(i32 (zext VK1:$src)),
1442 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1443 def : Pat<(i8 (zext VK1:$src)),
1444 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1445 (AND32ri (KMOVWrk
1446 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1447 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1448 (AND64ri8 (SUBREG_TO_REG (i64 0),
1449 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1450 def : Pat<(i16 (zext VK1:$src)),
1451 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1452 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1453 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1454 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1455 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1456 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1457 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1458}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1459let Predicates = [HasBWI] in {
1460 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1461 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1462 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1463 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1464}
1465
1466
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1467// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1468let Predicates = [HasAVX512] in {
1469 // GR from/to 8-bit mask without native support
1470 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1471 (COPY_TO_REGCLASS
1472 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1473 VK8)>;
1474 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1475 (EXTRACT_SUBREG
1476 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1477 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1478
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1479 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1480 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1481 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1482 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1483}
1484let Predicates = [HasBWI] in {
1485 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1486 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1487 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1488 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1489}
1490
1491// Mask unary operation
1492// - KNOT
1493multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1494 RegisterClass KRC, SDPatternOperator OpNode,
1495 Predicate prd> {
1496 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1497 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1498 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1499 [(set KRC:$dst, (OpNode KRC:$src))]>;
1500}
1501
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1502multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1503 SDPatternOperator OpNode> {
1504 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1505 HasDQI>, VEX, PD;
1506 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1507 HasAVX512>, VEX, PS;
1508 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1509 HasBWI>, VEX, PD, VEX_W;
1510 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1511 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1512}
1513
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1514defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1515
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1516multiclass avx512_mask_unop_int<string IntName, string InstName> {
1517 let Predicates = [HasAVX512] in
1518 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1519 (i16 GR16:$src)),
1520 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1521 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1522}
1523defm : avx512_mask_unop_int<"knot", "KNOT">;
1524
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1525let Predicates = [HasDQI] in
1526def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1527let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1528def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1529let Predicates = [HasBWI] in
1530def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1531let Predicates = [HasBWI] in
1532def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1533
1534// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1535let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1536def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1537 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1538
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1539def : Pat<(not VK8:$src),
1540 (COPY_TO_REGCLASS
1541 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1542}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1543
1544// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1545// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1546multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1547 RegisterClass KRC, SDPatternOperator OpNode,
1548 Predicate prd> {
1549 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1550 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1551 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1552 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1553 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1554}
1555
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1556multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1557 SDPatternOperator OpNode> {
1558 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1559 HasDQI>, VEX_4V, VEX_L, PD;
1560 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1561 HasAVX512>, VEX_4V, VEX_L, PS;
1562 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1563 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1564 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1565 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1566}
1567
1568def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1569def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1570
1571let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1572 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1573 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1574 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1575 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1576}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1577let isCommutable = 0 in
1578 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1579
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1580def : Pat<(xor VK1:$src1, VK1:$src2),
1581 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1582 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1583
1584def : Pat<(or VK1:$src1, VK1:$src2),
1585 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1586 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1587
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1588def : Pat<(and VK1:$src1, VK1:$src2),
1589 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1590 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1591
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1592multiclass avx512_mask_binop_int<string IntName, string InstName> {
1593 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1594 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1595 (i16 GR16:$src1), (i16 GR16:$src2)),
1596 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1597 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1598 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1599}
1600
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1601defm : avx512_mask_binop_int<"kand", "KAND">;
1602defm : avx512_mask_binop_int<"kandn", "KANDN">;
1603defm : avx512_mask_binop_int<"kor", "KOR">;
1604defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1605defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1606
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1607// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1608multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1609 let Predicates = [HasAVX512] in
1610 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1611 (COPY_TO_REGCLASS
1612 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1613 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1614}
1615
1616defm : avx512_binop_pat<and, KANDWrr>;
1617defm : avx512_binop_pat<andn, KANDNWrr>;
1618defm : avx512_binop_pat<or, KORWrr>;
1619defm : avx512_binop_pat<xnor, KXNORWrr>;
1620defm : avx512_binop_pat<xor, KXORWrr>;
1621
1622// Mask unpacking
1623multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1624 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1625 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1626 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1627 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1628 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1629}
1630
1631multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1632 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1633 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1634}
1635
1636defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1637def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1638 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1639 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1640
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1641
1642multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1643 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1644 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1645 (i16 GR16:$src1), (i16 GR16:$src2)),
1646 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1647 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1648 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1649}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1650defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1651
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1652// Mask bit testing
1653multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1654 SDNode OpNode> {
1655 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1656 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1657 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1658 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1659}
1660
1661multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1662 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1663 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1664}
1665
1666defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1667
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1668def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1669 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1670 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1671
1672// Mask shift
1673multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1674 SDNode OpNode> {
1675 let Predicates = [HasAVX512] in
1676 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1677 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1678 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1679 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1680}
1681
1682multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1683 SDNode OpNode> {
1684 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1685 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1686}
1687
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1688defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1689defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1690
1691// Mask setting all 0s or 1s
1692multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1693 let Predicates = [HasAVX512] in
1694 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1695 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1696 [(set KRC:$dst, (VT Val))]>;
1697}
1698
1699multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1700 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1701 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1702}
1703
1704defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1705defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1706
1707// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1708let Predicates = [HasAVX512] in {
1709 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1710 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1711 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1712 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1713 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1714}
1715def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1716 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1717
1718def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1719 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1720
1721def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1722 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1723
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1724let Predicates = [HasVLX] in {
1725 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1726 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1727 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1728 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1729 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1730 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1731 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1732 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1733}
1734
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1735def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1736 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1737
1738def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1739 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1740//===----------------------------------------------------------------------===//
1741// AVX-512 - Aligned and unaligned load and store
1742//
1743
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1744multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1745 RegisterClass KRC, RegisterClass RC,
1746 ValueType vt, ValueType zvt, X86MemOperand memop,
1747 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1748let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1749 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1751 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1752 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1753 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1754 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1755 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1756 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1757 SchedRW = [WriteLoad] in
1758 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1760 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1761 d>, EVEX;
1762
1763 let AddedComplexity = 20 in {
1764 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1765 let hasSideEffects = 0 in
1766 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1767 (ins RC:$src0, KRC:$mask, RC:$src1),
1768 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1769 "${dst} {${mask}}, $src1}"),
1770 [(set RC:$dst, (vt (vselect KRC:$mask,
1771 (vt RC:$src1),
1772 (vt RC:$src0))))],
1773 d>, EVEX, EVEX_K;
1774 let mayLoad = 1, SchedRW = [WriteLoad] in
1775 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1776 (ins RC:$src0, KRC:$mask, memop:$src1),
1777 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1778 "${dst} {${mask}}, $src1}"),
1779 [(set RC:$dst, (vt
1780 (vselect KRC:$mask,
1781 (vt (bitconvert (ld_frag addr:$src1))),
1782 (vt RC:$src0))))],
1783 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1784 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1785 let mayLoad = 1, SchedRW = [WriteLoad] in
1786 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1787 (ins KRC:$mask, memop:$src),
1788 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1789 "${dst} {${mask}} {z}, $src}"),
1790 [(set RC:$dst, (vt
1791 (vselect KRC:$mask,
1792 (vt (bitconvert (ld_frag addr:$src))),
1793 (vt (bitconvert (zvt immAllZerosV))))))],
1794 d>, EVEX, EVEX_KZ;
1795 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1796}
1797
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1798multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1799 string elty, string elsz, string vsz512,
1800 string vsz256, string vsz128, Domain d,
1801 Predicate prd, bit IsReMaterializable = 1> {
1802 let Predicates = [prd] in
1803 defm Z : avx512_load<opc, OpcodeStr,
1804 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1805 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1806 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1807 !cast<X86MemOperand>(elty##"512mem"), d,
1808 IsReMaterializable>, EVEX_V512;
1809
1810 let Predicates = [prd, HasVLX] in {
1811 defm Z256 : avx512_load<opc, OpcodeStr,
1812 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1813 "v"##vsz256##elty##elsz, "v4i64")),
1814 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1815 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1816 !cast<X86MemOperand>(elty##"256mem"), d,
1817 IsReMaterializable>, EVEX_V256;
1818
1819 defm Z128 : avx512_load<opc, OpcodeStr,
1820 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1821 "v"##vsz128##elty##elsz, "v2i64")),
1822 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1823 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1824 !cast<X86MemOperand>(elty##"128mem"), d,
1825 IsReMaterializable>, EVEX_V128;
1826 }
1827}
1828
1829
1830multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1831 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1832 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1833 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1834 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1835 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1836 EVEX;
1837 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1838 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1839 (ins RC:$src1, KRC:$mask, RC:$src2),
1840 !strconcat(OpcodeStr,
1841 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1842 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1843 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1844 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1845 !strconcat(OpcodeStr,
1846 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1847 [], d>, EVEX, EVEX_KZ;
1848 }
1849 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1850 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1851 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1852 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1853 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1854 (ins memop:$dst, KRC:$mask, RC:$src),
1855 !strconcat(OpcodeStr,
1856 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1857 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1858 }
1859}
1860
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1861
1862multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1863 string st_suff_512, string st_suff_256,
1864 string st_suff_128, string elty, string elsz,
1865 string vsz512, string vsz256, string vsz128,
1866 Domain d, Predicate prd> {
1867 let Predicates = [prd] in
1868 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1869 !cast<ValueType>("v"##vsz512##elty##elsz),
1870 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1871 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1872
1873 let Predicates = [prd, HasVLX] in {
1874 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1875 !cast<ValueType>("v"##vsz256##elty##elsz),
1876 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1877 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1878
1879 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1880 !cast<ValueType>("v"##vsz128##elty##elsz),
1881 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1882 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1883 }
1884}
1885
1886defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1887 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1888 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1889 "512", "256", "", "f", "32", "16", "8", "4",
1890 SSEPackedSingle, HasAVX512>,
1891 PS, EVEX_CD8<32, CD8VF>;
1892
1893defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1894 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1895 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1896 "512", "256", "", "f", "64", "8", "4", "2",
1897 SSEPackedDouble, HasAVX512>,
1898 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1899
1900defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1901 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1902 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1903 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1904 PS, EVEX_CD8<32, CD8VF>;
1905
1906defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1907 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1908 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1909 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1910 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1911
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1912def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1913 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1914 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1915
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1916def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1917 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1918 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1919
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1920def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1921 GR16:$mask),
1922 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1923 VR512:$src)>;
1924def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1925 GR8:$mask),
1926 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1927 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1928
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1929defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1930 "16", "8", "4", SSEPackedInt, HasAVX512>,
1931 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1932 "512", "256", "", "i", "32", "16", "8", "4",
1933 SSEPackedInt, HasAVX512>,
1934 PD, EVEX_CD8<32, CD8VF>;
1935
1936defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1937 "8", "4", "2", SSEPackedInt, HasAVX512>,
1938 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1939 "512", "256", "", "i", "64", "8", "4", "2",
1940 SSEPackedInt, HasAVX512>,
1941 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1942
1943defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1944 "64", "32", "16", SSEPackedInt, HasBWI>,
1945 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1946 "i", "8", "64", "32", "16", SSEPackedInt,
1947 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1948
1949defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1950 "32", "16", "8", SSEPackedInt, HasBWI>,
1951 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1952 "i", "16", "32", "16", "8", SSEPackedInt,
1953 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1954
1955defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1956 "16", "8", "4", SSEPackedInt, HasAVX512>,
1957 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1958 "i", "32", "16", "8", "4", SSEPackedInt,
1959 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1960
1961defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1962 "8", "4", "2", SSEPackedInt, HasAVX512>,
1963 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1964 "i", "64", "8", "4", "2", SSEPackedInt,
1965 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1966
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1967def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1968 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1969 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1970
1971def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1972 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1973 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1974
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]1975def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1976 GR16:$mask),
1977 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]1978 VR512:$src)>;
1979def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1980 GR8:$mask),
1981 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]1982 VR512:$src)>;
1983
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1984let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]1985def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1986 (bc_v8i64 (v16i32 immAllZerosV)))),
1987 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]1988
1989def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1990 (v8i64 VR512:$src))),
1991 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]1992 VK8), VR512:$src)>;
1993
1994def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1995 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1996 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]1997
1998def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1999 (v16i32 VR512:$src))),
2000 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2001}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2002
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2003// Move Int Doubleword to Packed Double Int
2004//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2005def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2006 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2007 [(set VR128X:$dst,
2008 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2009 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2010def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2011 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2012 [(set VR128X:$dst,
2013 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2014 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2015def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2016 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2017 [(set VR128X:$dst,
2018 (v2i64 (scalar_to_vector GR64:$src)))],
2019 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2020let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2021def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2022 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2023 [(set FR64:$dst, (bitconvert GR64:$src))],
2024 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2025def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2026 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2027 [(set GR64:$dst, (bitconvert FR64:$src))],
2028 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2029}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2030def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2031 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2032 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2033 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2034 EVEX_CD8<64, CD8VT1>;
2035
2036// Move Int Doubleword to Single Scalar
2037//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2038let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2039def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2040 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2041 [(set FR32X:$dst, (bitconvert GR32:$src))],
2042 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2043
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2044def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2045 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2046 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2047 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2048}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2049
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2050// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2051//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2052def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2053 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2054 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2055 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2056 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2057def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2058 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2059 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2060 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2061 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2062 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2063
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2064// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2065//
2066def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2067 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2068 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2069 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2070 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2071 Requires<[HasAVX512, In64BitMode]>;
2072
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2073def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2074 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2075 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2076 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2077 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2078 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2079 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2080
2081// Move Scalar Single to Double Int
2082//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2083let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2084def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2085 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2086 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2087 [(set GR32:$dst, (bitconvert FR32X:$src))],
2088 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2089def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2090 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2091 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2092 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2093 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2094}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2095
2096// Move Quadword Int to Packed Quadword Int
2097//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2098def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2099 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2100 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2101 [(set VR128X:$dst,
2102 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2103 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2104
2105//===----------------------------------------------------------------------===//
2106// AVX-512 MOVSS, MOVSD
2107//===----------------------------------------------------------------------===//
2108
2109multiclass avx512_move_scalar <string asm, RegisterClass RC,
2110 SDNode OpNode, ValueType vt,
2111 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2112 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2113 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2114 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2115 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2116 (scalar_to_vector RC:$src2))))],
2117 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2118 let Constraints = "$src1 = $dst" in
2119 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2120 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2121 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2122 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2123 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2124 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2125 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2126 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2127 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2128 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2129 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2130 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2131 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2132 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2133 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2134 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2135 [], IIC_SSE_MOV_S_MR>,
2136 EVEX, VEX_LIG, EVEX_K;
2137 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2138 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2139}
2140
2141let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2142defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2143 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2144
2145let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2146defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2147 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2148
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2149def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2150 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2151 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2152
2153def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2154 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2155 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2156
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2157def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2158 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2159 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2160
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2161// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2162let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2163 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2164 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2165 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2166 IIC_SSE_MOV_S_RR>,
2167 XS, EVEX_4V, VEX_LIG;
2168 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2169 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2170 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2171 IIC_SSE_MOV_S_RR>,
2172 XD, EVEX_4V, VEX_LIG, VEX_W;
2173}
2174
2175let Predicates = [HasAVX512] in {
2176 let AddedComplexity = 15 in {
2177 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2178 // MOVS{S,D} to the lower bits.
2179 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2180 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2181 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2182 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2183 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2184 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2185 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2186 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2187
2188 // Move low f32 and clear high bits.
2189 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2190 (SUBREG_TO_REG (i32 0),
2191 (VMOVSSZrr (v4f32 (V_SET0)),
2192 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2193 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2194 (SUBREG_TO_REG (i32 0),
2195 (VMOVSSZrr (v4i32 (V_SET0)),
2196 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2197 }
2198
2199 let AddedComplexity = 20 in {
2200 // MOVSSrm zeros the high parts of the register; represent this
2201 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2202 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2203 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2204 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2205 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2206 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2207 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2208
2209 // MOVSDrm zeros the high parts of the register; represent this
2210 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2211 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2212 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2213 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2214 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2215 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2216 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2217 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2218 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2219 def : Pat<(v2f64 (X86vzload addr:$src)),
2220 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2221
2222 // Represent the same patterns above but in the form they appear for
2223 // 256-bit types
2224 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2225 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2226 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2227 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2228 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2229 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2230 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2231 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2232 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2233 }
2234 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2235 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2236 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2237 FR32X:$src)), sub_xmm)>;
2238 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2239 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2240 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2241 FR64X:$src)), sub_xmm)>;
2242 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2243 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2244 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2245
2246 // Move low f64 and clear high bits.
2247 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2248 (SUBREG_TO_REG (i32 0),
2249 (VMOVSDZrr (v2f64 (V_SET0)),
2250 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2251
2252 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2253 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2254 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2255
2256 // Extract and store.
2257 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2258 addr:$dst),
2259 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2260 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2261 addr:$dst),
2262 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2263
2264 // Shuffle with VMOVSS
2265 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2266 (VMOVSSZrr (v4i32 VR128X:$src1),
2267 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2268 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2269 (VMOVSSZrr (v4f32 VR128X:$src1),
2270 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2271
2272 // 256-bit variants
2273 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2274 (SUBREG_TO_REG (i32 0),
2275 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2276 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2277 sub_xmm)>;
2278 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2279 (SUBREG_TO_REG (i32 0),
2280 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2281 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2282 sub_xmm)>;
2283
2284 // Shuffle with VMOVSD
2285 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2286 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2287 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2288 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2289 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2290 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2291 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2292 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2293
2294 // 256-bit variants
2295 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2296 (SUBREG_TO_REG (i32 0),
2297 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2298 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2299 sub_xmm)>;
2300 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2301 (SUBREG_TO_REG (i32 0),
2302 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2303 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2304 sub_xmm)>;
2305
2306 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2307 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2308 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2309 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2310 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2311 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2312 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2313 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2314}
2315
2316let AddedComplexity = 15 in
2317def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2318 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2319 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2320 [(set VR128X:$dst, (v2i64 (X86vzmovl
2321 (v2i64 VR128X:$src))))],
2322 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2323
2324let AddedComplexity = 20 in
2325def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2326 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2327 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2328 [(set VR128X:$dst, (v2i64 (X86vzmovl
2329 (loadv2i64 addr:$src))))],
2330 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2331 EVEX_CD8<8, CD8VT8>;
2332
2333let Predicates = [HasAVX512] in {
2334 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2335 let AddedComplexity = 20 in {
2336 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2337 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2338 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2339 (VMOV64toPQIZrr GR64:$src)>;
2340 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2341 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2342
2343 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2344 (VMOVDI2PDIZrm addr:$src)>;
2345 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2346 (VMOVDI2PDIZrm addr:$src)>;
2347 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2348 (VMOVZPQILo2PQIZrm addr:$src)>;
2349 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2350 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2351 def : Pat<(v2i64 (X86vzload addr:$src)),
2352 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2353 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2354
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2355 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2357 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2358 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2359 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2360 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2361 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2362}
2363
2364def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2365 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2366
2367def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2368 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2369
2370def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2371 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2372
2373def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2374 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2375
2376//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2377// AVX-512 - Non-temporals
2378//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2379let SchedRW = [WriteLoad] in {
2380 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2381 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2382 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2383 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2384 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2385
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2386 let Predicates = [HasAVX512, HasVLX] in {
2387 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2388 (ins i256mem:$src),
2389 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2390 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2391 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2392
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2393 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2394 (ins i128mem:$src),
2395 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2396 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2397 EVEX_CD8<64, CD8VF>;
2398 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2399}
2400
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2401multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2402 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2403 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2404 let SchedRW = [WriteStore], mayStore = 1,
2405 AddedComplexity = 400 in
2406 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2407 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2408 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2409}
2410
2411multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2412 string elty, string elsz, string vsz512,
2413 string vsz256, string vsz128, Domain d,
2414 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2415 let Predicates = [prd] in
2416 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2417 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2418 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2419 EVEX_V512;
2420
2421 let Predicates = [prd, HasVLX] in {
2422 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2423 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2424 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2425 EVEX_V256;
2426
2427 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2428 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2429 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2430 EVEX_V128;
2431 }
2432}
2433
2434defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2435 "i", "64", "8", "4", "2", SSEPackedInt,
2436 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2437
2438defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2439 "f", "64", "8", "4", "2", SSEPackedDouble,
2440 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2441
2442defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2443 "f", "32", "16", "8", "4", SSEPackedSingle,
2444 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2445
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2446//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2447// AVX-512 - Integer arithmetic
2448//
2449multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2450 ValueType OpVT, RegisterClass KRC,
2451 RegisterClass RC, PatFrag memop_frag,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2452 X86MemOperand x86memop, PatFrag scalar_mfrag,
2453 X86MemOperand x86scalar_mop, string BrdcstStr,
2454 OpndItins itins, bit IsCommutable = 0> {
2455 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2456 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2457 (ins RC:$src1, RC:$src2),
2458 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2459 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2460 itins.rr>, EVEX_4V;
2461 let AddedComplexity = 30 in {
2462 let Constraints = "$src0 = $dst" in
2463 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2464 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2465 !strconcat(OpcodeStr,
2466 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2467 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2468 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2469 RC:$src0)))],
2470 itins.rr>, EVEX_4V, EVEX_K;
2471 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2472 (ins KRC:$mask, RC:$src1, RC:$src2),
2473 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2474 "|$dst {${mask}} {z}, $src1, $src2}"),
2475 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2476 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2477 (OpVT immAllZerosV))))],
2478 itins.rr>, EVEX_4V, EVEX_KZ;
2479 }
2480
2481 let mayLoad = 1 in {
2482 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2483 (ins RC:$src1, x86memop:$src2),
2484 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2485 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2486 itins.rm>, EVEX_4V;
2487 let AddedComplexity = 30 in {
2488 let Constraints = "$src0 = $dst" in
2489 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2490 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2491 !strconcat(OpcodeStr,
2492 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2493 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2494 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2495 RC:$src0)))],
2496 itins.rm>, EVEX_4V, EVEX_K;
2497 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2498 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2499 !strconcat(OpcodeStr,
2500 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2501 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2502 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2503 (OpVT immAllZerosV))))],
2504 itins.rm>, EVEX_4V, EVEX_KZ;
2505 }
2506 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2507 (ins RC:$src1, x86scalar_mop:$src2),
2508 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2509 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2510 [(set RC:$dst, (OpNode RC:$src1,
2511 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2512 itins.rm>, EVEX_4V, EVEX_B;
2513 let AddedComplexity = 30 in {
2514 let Constraints = "$src0 = $dst" in
2515 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2516 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2517 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2518 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2519 BrdcstStr, "}"),
2520 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2521 (OpNode (OpVT RC:$src1),
2522 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2523 RC:$src0)))],
2524 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2525 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2527 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2528 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2529 BrdcstStr, "}"),
2530 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2531 (OpNode (OpVT RC:$src1),
2532 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2533 (OpVT immAllZerosV))))],
2534 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2535 }
2536 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2537}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2538
2539multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2540 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2541 PatFrag memop_frag, X86MemOperand x86memop,
2542 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2543 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2544 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2545 {
2546 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2547 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2548 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2549 []>, EVEX_4V;
2550 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2551 (ins KRC:$mask, RC:$src1, RC:$src2),
2552 !strconcat(OpcodeStr,
2553 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2554 [], itins.rr>, EVEX_4V, EVEX_K;
2555 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2556 (ins KRC:$mask, RC:$src1, RC:$src2),
2557 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2558 "|$dst {${mask}} {z}, $src1, $src2}"),
2559 [], itins.rr>, EVEX_4V, EVEX_KZ;
2560 }
2561 let mayLoad = 1 in {
2562 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2563 (ins RC:$src1, x86memop:$src2),
2564 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2565 []>, EVEX_4V;
2566 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2567 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2568 !strconcat(OpcodeStr,
2569 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2570 [], itins.rm>, EVEX_4V, EVEX_K;
2571 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2572 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2573 !strconcat(OpcodeStr,
2574 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2575 [], itins.rm>, EVEX_4V, EVEX_KZ;
2576 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2577 (ins RC:$src1, x86scalar_mop:$src2),
2578 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2579 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2580 [], itins.rm>, EVEX_4V, EVEX_B;
2581 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2582 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2583 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2584 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2585 BrdcstStr, "}"),
2586 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2587 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2588 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2589 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2590 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2591 BrdcstStr, "}"),
2592 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2593 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2594}
2595
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2596defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2597 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2598 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2599
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2600defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2601 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2602 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2603
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2604defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2605 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2606 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2607
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2608defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2609 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2610 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2611
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2612defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2613 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2614 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2615
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2616defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2617 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2618 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2619 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2620
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2621defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2622 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2623 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2624
2625def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2626 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2627
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2628def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2629 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2630 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2631def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2632 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2633 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2634
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2635defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2636 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2637 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2638 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2639defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2640 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2641 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2642 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2643
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2644defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2645 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2646 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2647 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2648defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2649 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2650 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2651 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2652
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2653defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2654 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2655 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2656 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2657defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2658 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2659 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2660 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2661
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2662defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2663 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2664 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2665 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2666defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2667 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2668 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2669 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2670
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2671def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2672 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2673 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2674def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2675 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2676 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2677def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2678 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2679 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2680def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2681 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2682 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2683def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2684 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2685 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2686def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2687 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2688 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2689def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2690 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2691 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2692def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2693 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2694 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2695//===----------------------------------------------------------------------===//
2696// AVX-512 - Unpack Instructions
2697//===----------------------------------------------------------------------===//
2698
2699multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2700 PatFrag mem_frag, RegisterClass RC,
2701 X86MemOperand x86memop, string asm,
2702 Domain d> {
2703 def rr : AVX512PI<opc, MRMSrcReg,
2704 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2705 asm, [(set RC:$dst,
2706 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2707 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2708 def rm : AVX512PI<opc, MRMSrcMem,
2709 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2710 asm, [(set RC:$dst,
2711 (vt (OpNode RC:$src1,
2712 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2713 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2714}
2715
2716defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2717 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2718 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2719defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2720 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2721 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2722defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2723 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2724 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2725defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2726 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2727 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2728
2729multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2730 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2731 X86MemOperand x86memop> {
2732 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2733 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2734 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2735 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2736 IIC_SSE_UNPCK>, EVEX_4V;
2737 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2738 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2739 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2740 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2741 (bitconvert (memop_frag addr:$src2)))))],
2742 IIC_SSE_UNPCK>, EVEX_4V;
2743}
2744defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2745 VR512, memopv16i32, i512mem>, EVEX_V512,
2746 EVEX_CD8<32, CD8VF>;
2747defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2748 VR512, memopv8i64, i512mem>, EVEX_V512,
2749 VEX_W, EVEX_CD8<64, CD8VF>;
2750defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2751 VR512, memopv16i32, i512mem>, EVEX_V512,
2752 EVEX_CD8<32, CD8VF>;
2753defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2754 VR512, memopv8i64, i512mem>, EVEX_V512,
2755 VEX_W, EVEX_CD8<64, CD8VF>;
2756//===----------------------------------------------------------------------===//
2757// AVX-512 - PSHUFD
2758//
2759
2760multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2761 SDNode OpNode, PatFrag mem_frag,
2762 X86MemOperand x86memop, ValueType OpVT> {
2763 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2764 (ins RC:$src1, i8imm:$src2),
2765 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2766 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2767 [(set RC:$dst,
2768 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2769 EVEX;
2770 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2771 (ins x86memop:$src1, i8imm:$src2),
2772 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2773 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2774 [(set RC:$dst,
2775 (OpVT (OpNode (mem_frag addr:$src1),
2776 (i8 imm:$src2))))]>, EVEX;
2777}
2778
2779defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2780 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2781
2782let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2783defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2784 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2785 EVEX_CD8<32, CD8VF>;
2786let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2787defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2788 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2789 VEX_W, EVEX_CD8<32, CD8VF>;
2790
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2791def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2792 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2793def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2794 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2795
2796//===----------------------------------------------------------------------===//
2797// AVX-512 Logical Instructions
2798//===----------------------------------------------------------------------===//
2799
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2800defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2801 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2802 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2803defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2804 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2806defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2807 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2808 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2809defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2810 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2811 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2812defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2813 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2814 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2815defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2816 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2817 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2818defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2819 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2820 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2821defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2822 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2823 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2824
2825//===----------------------------------------------------------------------===//
2826// AVX-512 FP arithmetic
2827//===----------------------------------------------------------------------===//
2828
2829multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2830 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2831 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2832 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2833 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2834 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2835 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2836 EVEX_CD8<64, CD8VT1>;
2837}
2838
2839let isCommutable = 1 in {
2840defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2841defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2842defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2843defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2844}
2845let isCommutable = 0 in {
2846defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2847defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2848}
2849
2850multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2851 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2852 RegisterClass RC, ValueType vt,
2853 X86MemOperand x86memop, PatFrag mem_frag,
2854 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2855 string BrdcstStr,
2856 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2857 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2858 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2859 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2860 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2861 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2862
2863 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2864 !strconcat(OpcodeStr,
2865 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2866 [], itins.rr, d>, EVEX_4V, EVEX_K;
2867
2868 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2869 !strconcat(OpcodeStr,
2870 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2871 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2872 }
2873
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2874 let mayLoad = 1 in {
2875 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2876 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2877 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2878 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2879
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2881 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2882 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2883 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2884 [(set RC:$dst, (OpNode RC:$src1,
2885 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2886 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2887
2888 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2889 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2890 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2891 [], itins.rm, d>, EVEX_4V, EVEX_K;
2892
2893 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2894 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2895 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2896 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2897
2898 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2899 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2900 " \t{${src2}", BrdcstStr,
2901 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2902 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2903
2904 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2905 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2906 " \t{${src2}", BrdcstStr,
2907 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2908 BrdcstStr, "}"),
2909 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2910 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2911}
2912
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2913defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2914 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2915 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2916
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2917defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2918 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2919 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2920 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2921
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2922defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2923 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2924 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2925defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2926 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2927 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2928 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2929
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2930defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2931 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2932 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2933 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2934defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2935 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2936 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2937 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2938
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2939defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2940 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2941 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2942 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2943defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2944 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2945 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2946 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2947
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2948defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2949 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2950 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2951defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2952 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2953 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2954
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2955defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2956 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2957 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2958 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2959defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2960 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2961 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2962 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2963
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]2964def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2965 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2966 (i16 -1), FROUND_CURRENT)),
2967 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2968
2969def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2970 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2971 (i8 -1), FROUND_CURRENT)),
2972 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2973
2974def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2975 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2976 (i16 -1), FROUND_CURRENT)),
2977 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2978
2979def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2980 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2981 (i8 -1), FROUND_CURRENT)),
2982 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2983//===----------------------------------------------------------------------===//
2984// AVX-512 VPTESTM instructions
2985//===----------------------------------------------------------------------===//
2986
2987multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2988 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2989 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2990 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2991 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2992 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2993 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2994 SSEPackedInt>, EVEX_4V;
2995 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2996 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2997 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2998 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2999 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3000}
3001
3002defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3003 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3004 EVEX_CD8<32, CD8VF>;
3005defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3006 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3007 EVEX_CD8<64, CD8VF>;
3008
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3009let Predicates = [HasCDI] in {
3010defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3011 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3012 EVEX_CD8<32, CD8VF>;
3013defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3014 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3015 EVEX_CD8<64, CD8VF>;
3016}
3017
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3018def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3019 (v16i32 VR512:$src2), (i16 -1))),
3020 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3021
3022def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3023 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3024 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3025//===----------------------------------------------------------------------===//
3026// AVX-512 Shift instructions
3027//===----------------------------------------------------------------------===//
3028multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3029 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3030 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3031 RegisterClass KRC> {
3032 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3033 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3034 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3035 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3036 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3037 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3038 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3039 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3040 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3041 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3042 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3043 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3044 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3045 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3046 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3047 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3048 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3049 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3050 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3051 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3052}
3053
3054multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3055 RegisterClass RC, ValueType vt, ValueType SrcVT,
3056 PatFrag bc_frag, RegisterClass KRC> {
3057 // src2 is always 128-bit
3058 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3059 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3060 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3061 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3062 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3063 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3064 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3065 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3066 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3067 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3068 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3069 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3070 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3071 [(set RC:$dst, (vt (OpNode RC:$src1,
3072 (bc_frag (memopv2i64 addr:$src2)))))],
3073 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3074 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3075 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3076 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3077 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3078 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3079}
3080
3081defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3082 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3083 EVEX_V512, EVEX_CD8<32, CD8VF>;
3084defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3085 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3086 EVEX_CD8<32, CD8VQ>;
3087
3088defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3089 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3090 EVEX_CD8<64, CD8VF>, VEX_W;
3091defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3092 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3093 EVEX_CD8<64, CD8VQ>, VEX_W;
3094
3095defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3096 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3097 EVEX_CD8<32, CD8VF>;
3098defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3099 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3100 EVEX_CD8<32, CD8VQ>;
3101
3102defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3103 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3104 EVEX_CD8<64, CD8VF>, VEX_W;
3105defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3106 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3107 EVEX_CD8<64, CD8VQ>, VEX_W;
3108
3109defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3110 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3111 EVEX_V512, EVEX_CD8<32, CD8VF>;
3112defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3113 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3114 EVEX_CD8<32, CD8VQ>;
3115
3116defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3117 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3118 EVEX_CD8<64, CD8VF>, VEX_W;
3119defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3120 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3121 EVEX_CD8<64, CD8VQ>, VEX_W;
3122
3123//===-------------------------------------------------------------------===//
3124// Variable Bit Shifts
3125//===-------------------------------------------------------------------===//
3126multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3127 RegisterClass RC, ValueType vt,
3128 X86MemOperand x86memop, PatFrag mem_frag> {
3129 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3130 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3131 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3132 [(set RC:$dst,
3133 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3134 EVEX_4V;
3135 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3136 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3137 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3138 [(set RC:$dst,
3139 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3140 EVEX_4V;
3141}
3142
3143defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3144 i512mem, memopv16i32>, EVEX_V512,
3145 EVEX_CD8<32, CD8VF>;
3146defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3147 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3148 EVEX_CD8<64, CD8VF>;
3149defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3150 i512mem, memopv16i32>, EVEX_V512,
3151 EVEX_CD8<32, CD8VF>;
3152defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3153 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3154 EVEX_CD8<64, CD8VF>;
3155defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3156 i512mem, memopv16i32>, EVEX_V512,
3157 EVEX_CD8<32, CD8VF>;
3158defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3159 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3160 EVEX_CD8<64, CD8VF>;
3161
3162//===----------------------------------------------------------------------===//
3163// AVX-512 - MOVDDUP
3164//===----------------------------------------------------------------------===//
3165
3166multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3167 X86MemOperand x86memop, PatFrag memop_frag> {
3168def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3169 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3170 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3171def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3172 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3173 [(set RC:$dst,
3174 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3175}
3176
3177defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3178 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3179def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3180 (VMOVDDUPZrm addr:$src)>;
3181
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3182//===---------------------------------------------------------------------===//
3183// Replicate Single FP - MOVSHDUP and MOVSLDUP
3184//===---------------------------------------------------------------------===//
3185multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3186 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3187 X86MemOperand x86memop> {
3188 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3189 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3190 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3191 let mayLoad = 1 in
3192 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3193 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3194 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3195}
3196
3197defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3198 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3199 EVEX_CD8<32, CD8VF>;
3200defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3201 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3202 EVEX_CD8<32, CD8VF>;
3203
3204def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3205def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3206 (VMOVSHDUPZrm addr:$src)>;
3207def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3208def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3209 (VMOVSLDUPZrm addr:$src)>;
3210
3211//===----------------------------------------------------------------------===//
3212// Move Low to High and High to Low packed FP Instructions
3213//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3214def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3215 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3216 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3217 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3218 IIC_SSE_MOV_LH>, EVEX_4V;
3219def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3220 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3221 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3222 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3223 IIC_SSE_MOV_LH>, EVEX_4V;
3224
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3225let Predicates = [HasAVX512] in {
3226 // MOVLHPS patterns
3227 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3228 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3229 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3230 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3231
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3232 // MOVHLPS patterns
3233 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3234 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3235}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3236
3237//===----------------------------------------------------------------------===//
3238// FMA - Fused Multiply Operations
3239//
3240let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3241multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3242 X86VectorVTInfo _> {
3243 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3244 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3245 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3246 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3247 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3248
3249 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3250 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3251 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3252 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3253 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3254 (_.MemOpFrag addr:$src3))))]>;
3255 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3256 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3257 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3258 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3259 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3260 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3261}
3262} // Constraints = "$src1 = $dst"
3263
3264let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3265 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3266 v16f32_info>,
3267 EVEX_V512, EVEX_CD8<32, CD8VF>;
3268 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3269 v16f32_info>,
3270 EVEX_V512, EVEX_CD8<32, CD8VF>;
3271 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3272 v16f32_info>,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3275 v16f32_info>,
3276 EVEX_V512, EVEX_CD8<32, CD8VF>;
3277 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3278 v16f32_info>,
3279 EVEX_V512, EVEX_CD8<32, CD8VF>;
3280 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3281 v16f32_info>,
3282 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3283}
3284let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3285 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3286 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3287 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3288 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3289 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3290 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3291 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3292 v8f64_info>,
3293 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3294 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3295 v8f64_info>,
3296 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3297 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3298 v8f64_info>,
3299 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3300 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3301 v8f64_info>,
3302 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3303}
3304
3305let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3306multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3307 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3308 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3309 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3310 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3311 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3312 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3313 _.RC:$src3)))]>;
3314 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3315 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3316 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3317 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3318 [(set _.RC:$dst,
3319 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3320 (_.ScalarLdFrag addr:$src2))),
3321 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3322}
3323} // Constraints = "$src1 = $dst"
3324
3325
3326let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3327 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3328 v16f32_info>,
3329 EVEX_V512, EVEX_CD8<32, CD8VF>;
3330 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3331 v16f32_info>,
3332 EVEX_V512, EVEX_CD8<32, CD8VF>;
3333 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3334 v16f32_info>,
3335 EVEX_V512, EVEX_CD8<32, CD8VF>;
3336 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3337 v16f32_info>,
3338 EVEX_V512, EVEX_CD8<32, CD8VF>;
3339 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3340 v16f32_info>,
3341 EVEX_V512, EVEX_CD8<32, CD8VF>;
3342 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3343 v16f32_info>,
3344 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3345}
3346let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3347 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3348 v8f64_info>,
3349 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3350 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3351 v8f64_info>,
3352 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3353 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3354 v8f64_info>,
3355 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3356 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3357 v8f64_info>,
3358 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3359 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3360 v8f64_info>,
3361 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3362 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3363 v8f64_info>,
3364 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3365}
3366
3367// Scalar FMA
3368let Constraints = "$src1 = $dst" in {
3369multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3370 RegisterClass RC, ValueType OpVT,
3371 X86MemOperand x86memop, Operand memop,
3372 PatFrag mem_frag> {
3373 let isCommutable = 1 in
3374 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3375 (ins RC:$src1, RC:$src2, RC:$src3),
3376 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3377 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3378 [(set RC:$dst,
3379 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3380 let mayLoad = 1 in
3381 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3382 (ins RC:$src1, RC:$src2, f128mem:$src3),
3383 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3384 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3385 [(set RC:$dst,
3386 (OpVT (OpNode RC:$src2, RC:$src1,
3387 (mem_frag addr:$src3))))]>;
3388}
3389
3390} // Constraints = "$src1 = $dst"
3391
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3392defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3393 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3394defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3395 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3396defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3397 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3398defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3399 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3400defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3401 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3402defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3403 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3404defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3405 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3406defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3407 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3408
3409//===----------------------------------------------------------------------===//
3410// AVX-512 Scalar convert from sign integer to float/double
3411//===----------------------------------------------------------------------===//
3412
3413multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3414 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3415let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3416 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3417 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3418 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3419 let mayLoad = 1 in
3420 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3421 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3422 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3423 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3424} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3425}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3426let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3427defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3428 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3429defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3430 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3431defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3432 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3433defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3434 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3435
3436def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3437 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3438def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3439 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3440def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3441 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3442def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3443 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3444
3445def : Pat<(f32 (sint_to_fp GR32:$src)),
3446 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3447def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3448 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3449def : Pat<(f64 (sint_to_fp GR32:$src)),
3450 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3451def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3452 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3453
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3454defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3455 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3456defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3457 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3458defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3459 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3460defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3461 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3462
3463def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3464 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3465def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3466 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3467def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3468 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3469def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3470 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3471
3472def : Pat<(f32 (uint_to_fp GR32:$src)),
3473 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3474def : Pat<(f32 (uint_to_fp GR64:$src)),
3475 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3476def : Pat<(f64 (uint_to_fp GR32:$src)),
3477 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3478def : Pat<(f64 (uint_to_fp GR64:$src)),
3479 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3480}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3481
3482//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3483// AVX-512 Scalar convert from float/double to integer
3484//===----------------------------------------------------------------------===//
3485multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3486 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3487 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3488let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3489 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3490 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3491 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3492 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3493 let mayLoad = 1 in
3494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3495 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3496 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3497} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3498}
3499let Predicates = [HasAVX512] in {
3500// Convert float/double to signed/unsigned int 32/64
3501defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3502 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3503 XS, EVEX_CD8<32, CD8VT1>;
3504defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3505 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3506 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3507defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3508 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3509 XS, EVEX_CD8<32, CD8VT1>;
3510defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3511 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3512 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3513 EVEX_CD8<32, CD8VT1>;
3514defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3515 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3516 XD, EVEX_CD8<64, CD8VT1>;
3517defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3518 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3519 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3520defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3521 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3522 XD, EVEX_CD8<64, CD8VT1>;
3523defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3524 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3525 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3526 EVEX_CD8<64, CD8VT1>;
3527
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3528let isCodeGenOnly = 1 in {
3529 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3530 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3531 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3532 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3533 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3534 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3535 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3536 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3537 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3538 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3539 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3540 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3541
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3542 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3543 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3544 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3545 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3546 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3547 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3548 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3549 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3550 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3551 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3552 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3553 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3554} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3555
3556// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3557let isCodeGenOnly = 1 in {
3558 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3559 ssmem, sse_load_f32, "cvttss2si">,
3560 XS, EVEX_CD8<32, CD8VT1>;
3561 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3562 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3563 "cvttss2si">, XS, VEX_W,
3564 EVEX_CD8<32, CD8VT1>;
3565 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3566 sdmem, sse_load_f64, "cvttsd2si">, XD,
3567 EVEX_CD8<64, CD8VT1>;
3568 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3569 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3570 "cvttsd2si">, XD, VEX_W,
3571 EVEX_CD8<64, CD8VT1>;
3572 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3573 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3574 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3575 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3576 int_x86_avx512_cvttss2usi64, ssmem,
3577 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3578 EVEX_CD8<32, CD8VT1>;
3579 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3580 int_x86_avx512_cvttsd2usi,
3581 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3582 EVEX_CD8<64, CD8VT1>;
3583 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3584 int_x86_avx512_cvttsd2usi64, sdmem,
3585 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3586 EVEX_CD8<64, CD8VT1>;
3587} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3588
3589multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3590 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3591 string asm> {
3592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3593 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3594 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3595 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3596 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3597 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3598}
3599
3600defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3601 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3602 EVEX_CD8<32, CD8VT1>;
3603defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3604 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3605 EVEX_CD8<32, CD8VT1>;
3606defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3607 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3608 EVEX_CD8<32, CD8VT1>;
3609defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3610 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3611 EVEX_CD8<32, CD8VT1>;
3612defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3613 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3614 EVEX_CD8<64, CD8VT1>;
3615defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3616 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3617 EVEX_CD8<64, CD8VT1>;
3618defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3619 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3620 EVEX_CD8<64, CD8VT1>;
3621defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3622 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3623 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3624} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3625//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3626// AVX-512 Convert form float to double and back
3627//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3628let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3629def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3630 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3631 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3632 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3633let mayLoad = 1 in
3634def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3635 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3636 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3637 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3638 EVEX_CD8<32, CD8VT1>;
3639
3640// Convert scalar double to scalar single
3641def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3642 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3643 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3644 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3645let mayLoad = 1 in
3646def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3647 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3648 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3649 []>, EVEX_4V, VEX_LIG, VEX_W,
3650 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3651}
3652
3653def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3654 Requires<[HasAVX512]>;
3655def : Pat<(fextend (loadf32 addr:$src)),
3656 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3657
3658def : Pat<(extloadf32 addr:$src),
3659 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3660 Requires<[HasAVX512, OptForSize]>;
3661
3662def : Pat<(extloadf32 addr:$src),
3663 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3664 Requires<[HasAVX512, OptForSpeed]>;
3665
3666def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3667 Requires<[HasAVX512]>;
3668
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3669multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3670 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3671 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3672 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3673let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3674 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3675 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3676 [(set DstRC:$dst,
3677 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3678 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3679 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3680 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3681 let mayLoad = 1 in
3682 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3683 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3684 [(set DstRC:$dst,
3685 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3686} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3687}
3688
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3689multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3690 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3691 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3692 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3693let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3694 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3695 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3696 [(set DstRC:$dst,
3697 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3698 let mayLoad = 1 in
3699 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3700 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3701 [(set DstRC:$dst,
3702 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3703} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3704}
3705
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3706defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3707 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3708 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3709 EVEX_CD8<64, CD8VF>;
3710
3711defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3712 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3713 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3714 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3715def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3716 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3717
3718def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3719 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3720 (VCVTPD2PSZrr VR512:$src)>;
3721
3722def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3723 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3724 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3725
3726//===----------------------------------------------------------------------===//
3727// AVX-512 Vector convert from sign integer to float/double
3728//===----------------------------------------------------------------------===//
3729
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3730defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3731 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3732 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3733 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3734
3735defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3736 memopv4i64, i256mem, v8f64, v8i32,
3737 SSEPackedDouble>, EVEX_V512, XS,
3738 EVEX_CD8<32, CD8VH>;
3739
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3740defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3741 memopv16f32, f512mem, v16i32, v16f32,
3742 SSEPackedSingle>, EVEX_V512, XS,
3743 EVEX_CD8<32, CD8VF>;
3744
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3745defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3746 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3747 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3748 EVEX_CD8<64, CD8VF>;
3749
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3750defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3751 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3752 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3753 EVEX_CD8<32, CD8VF>;
3754
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3755// cvttps2udq (src, 0, mask-all-ones, sae-current)
3756def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3757 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3758 (VCVTTPS2UDQZrr VR512:$src)>;
3759
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3760defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3761 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3762 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3763 EVEX_CD8<64, CD8VF>;
3764
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3765// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3766def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3767 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3768 (VCVTTPD2UDQZrr VR512:$src)>;
3769
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3770defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3771 memopv4i64, f256mem, v8f64, v8i32,
3772 SSEPackedDouble>, EVEX_V512, XS,
3773 EVEX_CD8<32, CD8VH>;
3774
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3775defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3776 memopv16i32, f512mem, v16f32, v16i32,
3777 SSEPackedSingle>, EVEX_V512, XD,
3778 EVEX_CD8<32, CD8VF>;
3779
3780def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3781 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3782 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3783
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3784def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3785 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3786 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3787
3788def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3789 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3790 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3791
3792def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3793 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3794 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3795
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3796def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3797 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3798 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3799
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3800def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3801 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3802 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3803def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3804 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3805 (VCVTDQ2PDZrr VR256X:$src)>;
3806def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3807 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3808 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3809def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3810 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3811 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3812
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3813multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3814 RegisterClass DstRC, PatFrag mem_frag,
3815 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3816let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3817 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3818 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3819 [], d>, EVEX;
3820 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3821 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3822 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3823 let mayLoad = 1 in
3824 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3825 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3826 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3827} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3828}
3829
3830defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3831 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3832 EVEX_V512, EVEX_CD8<32, CD8VF>;
3833defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3834 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3835 EVEX_V512, EVEX_CD8<64, CD8VF>;
3836
3837def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3838 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3839 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3840
3841def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3842 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3843 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3844
3845defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3846 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3847 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3848defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3849 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3850 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3851
3852def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3853 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3854 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3855
3856def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3857 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3858 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3859
3860let Predicates = [HasAVX512] in {
3861 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3862 (VCVTPD2PSZrm addr:$src)>;
3863 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3864 (VCVTPS2PDZrm addr:$src)>;
3865}
3866
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3867//===----------------------------------------------------------------------===//
3868// Half precision conversion instructions
3869//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3870multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3871 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3872 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3873 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3874 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3875 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3876 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3877 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3878}
3879
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3880multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3881 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3882 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3883 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3884 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3885 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3886 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3887 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3888 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3889 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3890}
3891
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3892defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3893 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3894defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3895 EVEX_CD8<32, CD8VH>;
3896
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3897def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3898 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3899 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3900
3901def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3902 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3903 (VCVTPH2PSZrr VR256X:$src)>;
3904
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3905let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3906 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3907 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3908 EVEX_CD8<32, CD8VT1>;
3909 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3910 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3911 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3912 let Pattern = []<dag> in {
3913 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3914 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3915 EVEX_CD8<32, CD8VT1>;
3916 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3917 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3918 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3919 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3920 let isCodeGenOnly = 1 in {
3921 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3922 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3923 EVEX_CD8<32, CD8VT1>;
3924 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3925 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3926 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3927
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3928 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3929 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3930 EVEX_CD8<32, CD8VT1>;
3931 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3932 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3933 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3934 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3935}
3936
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3937/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3938multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3939 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3940 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3941 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3942 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3943 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3944 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3945 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3946 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3947 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3948 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3949 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3950 }
3951}
3952}
3953
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3954defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3955 EVEX_CD8<32, CD8VT1>;
3956defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3957 VEX_W, EVEX_CD8<64, CD8VT1>;
3958defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3959 EVEX_CD8<32, CD8VT1>;
3960defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3961 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3962
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3963def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3964 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3965 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3966 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3967
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3968def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3969 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3970 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3971 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3972
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3973def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3974 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3975 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3976 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3977
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3978def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3979 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3980 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3981 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3982
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3983/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3984multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3985 RegisterClass RC, X86MemOperand x86memop,
3986 PatFrag mem_frag, ValueType OpVt> {
3987 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3988 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3989 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3990 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3991 EVEX;
3992 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3993 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3994 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3995 EVEX;
3996}
3997defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3998 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3999defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4000 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4001defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4002 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4003defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4004 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4005
4006def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4007 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4008 (VRSQRT14PSZr VR512:$src)>;
4009def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4010 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4011 (VRSQRT14PDZr VR512:$src)>;
4012
4013def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4014 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4015 (VRCP14PSZr VR512:$src)>;
4016def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4017 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4018 (VRCP14PDZr VR512:$src)>;
4019
4020/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4021multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4022 X86MemOperand x86memop> {
4023 let hasSideEffects = 0, Predicates = [HasERI] in {
4024 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4025 (ins RC:$src1, RC:$src2),
4026 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4027 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4028 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4029 (ins RC:$src1, RC:$src2),
4030 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4031 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4032 []>, EVEX_4V, EVEX_B;
4033 let mayLoad = 1 in {
4034 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4035 (ins RC:$src1, x86memop:$src2),
4036 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4037 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4038 }
4039}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4040}
4041
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4042defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4043 EVEX_CD8<32, CD8VT1>;
4044defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4045 VEX_W, EVEX_CD8<64, CD8VT1>;
4046defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4047 EVEX_CD8<32, CD8VT1>;
4048defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4049 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4050
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4051def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4052 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4053 FROUND_NO_EXC)),
4054 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4055 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4056
4057def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4058 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4059 FROUND_NO_EXC)),
4060 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4061 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4062
4063def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4064 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4065 FROUND_NO_EXC)),
4066 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4067 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4068
4069def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4070 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4071 FROUND_NO_EXC)),
4072 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4073 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4074
4075/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4076multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4077 RegisterClass RC, X86MemOperand x86memop> {
4078 let hasSideEffects = 0, Predicates = [HasERI] in {
4079 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4080 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4081 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4082 []>, EVEX;
4083 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4084 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4085 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4086 []>, EVEX, EVEX_B;
4087 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4088 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4089 []>, EVEX;
4090 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4091}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4092defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4093 EVEX_V512, EVEX_CD8<32, CD8VF>;
4094defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4095 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4096defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4097 EVEX_V512, EVEX_CD8<32, CD8VF>;
4098defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4099 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4100
4101def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4102 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4103 (VRSQRT28PSZrb VR512:$src)>;
4104def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4105 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4106 (VRSQRT28PDZrb VR512:$src)>;
4107
4108def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4109 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4110 (VRCP28PSZrb VR512:$src)>;
4111def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4112 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4113 (VRCP28PDZrb VR512:$src)>;
4114
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4115multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4116 OpndItins itins_s, OpndItins itins_d> {
4117 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4118 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4119 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4120 EVEX, EVEX_V512;
4121
4122 let mayLoad = 1 in
4123 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4124 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4125 [(set VR512:$dst,
4126 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4127 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4128
4129 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4130 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4131 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4132 EVEX, EVEX_V512;
4133
4134 let mayLoad = 1 in
4135 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4137 [(set VR512:$dst, (OpNode
4138 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4139 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4140
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4141}
4142
4143multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4144 Intrinsic F32Int, Intrinsic F64Int,
4145 OpndItins itins_s, OpndItins itins_d> {
4146 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4147 (ins FR32X:$src1, FR32X:$src2),
4148 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4149 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4150 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4151 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4152 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4153 (ins VR128X:$src1, VR128X:$src2),
4154 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4155 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4156 [(set VR128X:$dst,
4157 (F32Int VR128X:$src1, VR128X:$src2))],
4158 itins_s.rr>, XS, EVEX_4V;
4159 let mayLoad = 1 in {
4160 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4161 (ins FR32X:$src1, f32mem:$src2),
4162 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4163 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4164 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4165 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4166 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4167 (ins VR128X:$src1, ssmem:$src2),
4168 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4169 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4170 [(set VR128X:$dst,
4171 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4172 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4173 }
4174 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4175 (ins FR64X:$src1, FR64X:$src2),
4176 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4177 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4178 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4179 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4180 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4181 (ins VR128X:$src1, VR128X:$src2),
4182 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4183 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4184 [(set VR128X:$dst,
4185 (F64Int VR128X:$src1, VR128X:$src2))],
4186 itins_s.rr>, XD, EVEX_4V, VEX_W;
4187 let mayLoad = 1 in {
4188 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4189 (ins FR64X:$src1, f64mem:$src2),
4190 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4191 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4192 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4193 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4194 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4195 (ins VR128X:$src1, sdmem:$src2),
4196 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4197 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4198 [(set VR128X:$dst,
4199 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4200 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4201 }
4202}
4203
4204
4205defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4206 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4207 SSE_SQRTSS, SSE_SQRTSD>,
4208 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4209 SSE_SQRTPS, SSE_SQRTPD>;
4210
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4211let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4212 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4213 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4214 (VSQRTPSZrr VR512:$src1)>;
4215 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4216 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4217 (VSQRTPDZrr VR512:$src1)>;
4218
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4219 def : Pat<(f32 (fsqrt FR32X:$src)),
4220 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4221 def : Pat<(f32 (fsqrt (load addr:$src))),
4222 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4223 Requires<[OptForSize]>;
4224 def : Pat<(f64 (fsqrt FR64X:$src)),
4225 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4226 def : Pat<(f64 (fsqrt (load addr:$src))),
4227 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4228 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4229
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4230 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4231 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4232 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4233 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4234 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4235
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4236 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4237 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4238 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4239 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4240 Requires<[OptForSize]>;
4241
4242 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4243 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4244 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4245 VR128X)>;
4246 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4247 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4248
4249 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4250 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4251 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4252 VR128X)>;
4253 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4254 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4255}
4256
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4257
4258multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4259 X86MemOperand x86memop, RegisterClass RC,
4260 PatFrag mem_frag32, PatFrag mem_frag64,
4261 Intrinsic V4F32Int, Intrinsic V2F64Int,
4262 CD8VForm VForm> {
4263let ExeDomain = SSEPackedSingle in {
4264 // Intrinsic operation, reg.
4265 // Vector intrinsic operation, reg
4266 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4267 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4268 !strconcat(OpcodeStr,
4269 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4270 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4271
4272 // Vector intrinsic operation, mem
4273 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4274 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4275 !strconcat(OpcodeStr,
4276 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4277 [(set RC:$dst,
4278 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4279 EVEX_CD8<32, VForm>;
4280} // ExeDomain = SSEPackedSingle
4281
4282let ExeDomain = SSEPackedDouble in {
4283 // Vector intrinsic operation, reg
4284 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4285 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4286 !strconcat(OpcodeStr,
4287 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4288 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4289
4290 // Vector intrinsic operation, mem
4291 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4292 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4293 !strconcat(OpcodeStr,
4294 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4295 [(set RC:$dst,
4296 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4297 EVEX_CD8<64, VForm>;
4298} // ExeDomain = SSEPackedDouble
4299}
4300
4301multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4302 string OpcodeStr,
4303 Intrinsic F32Int,
4304 Intrinsic F64Int> {
4305let ExeDomain = GenericDomain in {
4306 // Operation, reg.
4307 let hasSideEffects = 0 in
4308 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4309 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4310 !strconcat(OpcodeStr,
4311 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4312 []>;
4313
4314 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4315 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4316 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4317 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4318 !strconcat(OpcodeStr,
4319 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4320 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4321
4322 // Intrinsic operation, mem.
4323 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4324 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4325 !strconcat(OpcodeStr,
4326 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4327 [(set VR128X:$dst, (F32Int VR128X:$src1,
4328 sse_load_f32:$src2, imm:$src3))]>,
4329 EVEX_CD8<32, CD8VT1>;
4330
4331 // Operation, reg.
4332 let hasSideEffects = 0 in
4333 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4334 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4335 !strconcat(OpcodeStr,
4336 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4337 []>, VEX_W;
4338
4339 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4340 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4341 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4342 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4343 !strconcat(OpcodeStr,
4344 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4345 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4346 VEX_W;
4347
4348 // Intrinsic operation, mem.
4349 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4350 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4351 !strconcat(OpcodeStr,
4352 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4353 [(set VR128X:$dst,
4354 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4355 VEX_W, EVEX_CD8<64, CD8VT1>;
4356} // ExeDomain = GenericDomain
4357}
4358
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4359multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4360 X86MemOperand x86memop, RegisterClass RC,
4361 PatFrag mem_frag, Domain d> {
4362let ExeDomain = d in {
4363 // Intrinsic operation, reg.
4364 // Vector intrinsic operation, reg
4365 def r : AVX512AIi8<opc, MRMSrcReg,
4366 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4367 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4368 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4369 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4370
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4371 // Vector intrinsic operation, mem
4372 def m : AVX512AIi8<opc, MRMSrcMem,
4373 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4374 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4375 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4376 []>, EVEX;
4377} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4378}
4379
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4380
4381defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4382 memopv16f32, SSEPackedSingle>, EVEX_V512,
4383 EVEX_CD8<32, CD8VF>;
4384
4385def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4386 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4387 FROUND_CURRENT)),
4388 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4389
4390
4391defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4392 memopv8f64, SSEPackedDouble>, EVEX_V512,
4393 VEX_W, EVEX_CD8<64, CD8VF>;
4394
4395def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4396 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4397 FROUND_CURRENT)),
4398 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4399
4400multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4401 Operand x86memop, RegisterClass RC, Domain d> {
4402let ExeDomain = d in {
4403 def r : AVX512AIi8<opc, MRMSrcReg,
4404 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4405 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4406 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4407 []>, EVEX_4V;
4408
4409 def m : AVX512AIi8<opc, MRMSrcMem,
4410 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4411 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4412 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4413 []>, EVEX_4V;
4414} // ExeDomain
4415}
4416
4417defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4418 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4419
4420defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4421 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4422
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4423def : Pat<(ffloor FR32X:$src),
4424 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4425def : Pat<(f64 (ffloor FR64X:$src)),
4426 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4427def : Pat<(f32 (fnearbyint FR32X:$src)),
4428 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4429def : Pat<(f64 (fnearbyint FR64X:$src)),
4430 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4431def : Pat<(f32 (fceil FR32X:$src)),
4432 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4433def : Pat<(f64 (fceil FR64X:$src)),
4434 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4435def : Pat<(f32 (frint FR32X:$src)),
4436 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4437def : Pat<(f64 (frint FR64X:$src)),
4438 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4439def : Pat<(f32 (ftrunc FR32X:$src)),
4440 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4441def : Pat<(f64 (ftrunc FR64X:$src)),
4442 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4443
4444def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4445 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4446def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4447 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4448def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4449 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4450def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4451 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4452def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4453 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4454
4455def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4456 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4457def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4458 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4459def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4460 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4461def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4462 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4463def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4464 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4465
4466//-------------------------------------------------
4467// Integer truncate and extend operations
4468//-------------------------------------------------
4469
4470multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4471 RegisterClass dstRC, RegisterClass srcRC,
4472 RegisterClass KRC, X86MemOperand x86memop> {
4473 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4474 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4475 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4476 []>, EVEX;
4477
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4478 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4479 (ins KRC:$mask, srcRC:$src),
4480 !strconcat(OpcodeStr,
4481 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4482 []>, EVEX, EVEX_K;
4483
4484 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4485 (ins KRC:$mask, srcRC:$src),
4486 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4487 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4488 []>, EVEX, EVEX_KZ;
4489
4490 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4491 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4492 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4493
4494 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4495 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4496 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4497 []>, EVEX, EVEX_K;
4498
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4499}
4500defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4501 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4502defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4503 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4504defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4505 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4506defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4507 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4508defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4509 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4510defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4511 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4512defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4513 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4514defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4515 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4516defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4517 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4518defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4519 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4520defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4521 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4522defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4523 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4524defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4525 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4526defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4527 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4528defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4529 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4530
4531def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4532def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4533def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4534def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4535def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4536
4537def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4538 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4539def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4540 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4541def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4542 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4543def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4544 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4545
4546
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4547multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4548 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4549 PatFrag mem_frag, X86MemOperand x86memop,
4550 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4551
4552 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4553 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4555 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4556
4557 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4558 (ins KRC:$mask, SrcRC:$src),
4559 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4560 []>, EVEX, EVEX_K;
4561
4562 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4563 (ins KRC:$mask, SrcRC:$src),
4564 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4565 []>, EVEX, EVEX_KZ;
4566
4567 let mayLoad = 1 in {
4568 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4569 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4570 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4571 [(set DstRC:$dst,
4572 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4573 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4574
4575 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4576 (ins KRC:$mask, x86memop:$src),
4577 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4578 []>,
4579 EVEX, EVEX_K;
4580
4581 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4582 (ins KRC:$mask, x86memop:$src),
4583 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4584 []>,
4585 EVEX, EVEX_KZ;
4586 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4587}
4588
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4589defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4590 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4591 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4592defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4594 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4595defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4596 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4597 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4598defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4599 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4600 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4601defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4602 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4603 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4604
4605defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4606 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4607 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4608defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4609 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4610 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4611defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4612 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4613 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4614defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4615 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4616 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4617defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4618 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4619 EVEX_CD8<32, CD8VH>;
4620
4621//===----------------------------------------------------------------------===//
4622// GATHER - SCATTER Operations
4623
4624multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4625 RegisterClass RC, X86MemOperand memop> {
4626let mayLoad = 1,
4627 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4628 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4629 (ins RC:$src1, KRC:$mask, memop:$src2),
4630 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4631 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4632 []>, EVEX, EVEX_K;
4633}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4634
4635let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4636defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4637 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4638defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4639 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4640}
4641
4642let ExeDomain = SSEPackedSingle in {
4643defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4644 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4645defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4646 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4647}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4648
4649defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4650 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4651defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4652 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4653
4654defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4655 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4656defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4657 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4658
4659multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4660 RegisterClass RC, X86MemOperand memop> {
4661let mayStore = 1, Constraints = "$mask = $mask_wb" in
4662 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4663 (ins memop:$dst, KRC:$mask, RC:$src2),
4664 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4665 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4666 []>, EVEX, EVEX_K;
4667}
4668
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4669let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4670defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4671 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4672defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4673 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4674}
4675
4676let ExeDomain = SSEPackedSingle in {
4677defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4678 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4679defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4680 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4681}
4682
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4683defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4684 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4685defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4686 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4687
4688defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4689 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4690defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4691 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4692
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4693// prefetch
4694multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4695 RegisterClass KRC, X86MemOperand memop> {
4696 let Predicates = [HasPFI], hasSideEffects = 1 in
4697 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4698 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4699 []>, EVEX, EVEX_K;
4700}
4701
4702defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4703 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4704
4705defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4706 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4707
4708defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4709 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4710
4711defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4712 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4713
4714defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4715 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4716
4717defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4718 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4719
4720defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4721 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4722
4723defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4724 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4725
4726defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4727 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4728
4729defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4730 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4731
4732defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4733 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4734
4735defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4736 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4737
4738defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4739 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4740
4741defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4742 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4743
4744defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4745 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4746
4747defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4748 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4749//===----------------------------------------------------------------------===//
4750// VSHUFPS - VSHUFPD Operations
4751
4752multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4753 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4754 Domain d> {
4755 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4756 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4757 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4758 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4759 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4760 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4761 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4762 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4763 (ins RC:$src1, RC:$src2, i8imm:$src3),
4764 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4765 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4766 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4767 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4768 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4769}
4770
4771defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4772 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4773defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4774 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4775
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4776def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4777 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4778def : Pat<(v16i32 (X86Shufp VR512:$src1,
4779 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4780 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4781
4782def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4783 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4784def : Pat<(v8i64 (X86Shufp VR512:$src1,
4785 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4786 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4787
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4788multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4789 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4790 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4791 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4792 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4793 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4794 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4795 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4796
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4797 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4798 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4799 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4800
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4801 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4802 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4803 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4804 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4805 " \t{$src3, $src2, $src1, $dst|"
4806 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4807 []>, EVEX_4V;
4808}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4809defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4810defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4811
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4812// Helper fragments to match sext vXi1 to vXiY.
4813def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4814def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4815
4816multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4817 RegisterClass KRC, RegisterClass RC,
4818 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4819 string BrdcstStr> {
4820 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4821 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4822 []>, EVEX;
4823 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4824 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4825 []>, EVEX, EVEX_K;
4826 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4827 !strconcat(OpcodeStr,
4828 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4829 []>, EVEX, EVEX_KZ;
4830 let mayLoad = 1 in {
4831 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4832 (ins x86memop:$src),
4833 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4834 []>, EVEX;
4835 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4836 (ins KRC:$mask, x86memop:$src),
4837 !strconcat(OpcodeStr,
4838 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4839 []>, EVEX, EVEX_K;
4840 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4841 (ins KRC:$mask, x86memop:$src),
4842 !strconcat(OpcodeStr,
4843 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4844 []>, EVEX, EVEX_KZ;
4845 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4846 (ins x86scalar_mop:$src),
4847 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4848 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4849 []>, EVEX, EVEX_B;
4850 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4851 (ins KRC:$mask, x86scalar_mop:$src),
4852 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4853 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4854 []>, EVEX, EVEX_B, EVEX_K;
4855 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4856 (ins KRC:$mask, x86scalar_mop:$src),
4857 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4858 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4859 BrdcstStr, "}"),
4860 []>, EVEX, EVEX_B, EVEX_KZ;
4861 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4862}
4863
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4864defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4865 i512mem, i32mem, "{1to16}">, EVEX_V512,
4866 EVEX_CD8<32, CD8VF>;
4867defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4868 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4869 EVEX_CD8<64, CD8VF>;
4870
4871def : Pat<(xor
4872 (bc_v16i32 (v16i1sextv16i32)),
4873 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4874 (VPABSDZrr VR512:$src)>;
4875def : Pat<(xor
4876 (bc_v8i64 (v8i1sextv8i64)),
4877 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4878 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4879
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4880def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4881 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4882 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4883def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4884 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4885 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4886
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4887multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4888 RegisterClass RC, RegisterClass KRC,
4889 X86MemOperand x86memop,
4890 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4891 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4892 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4893 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4894 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4895 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4896 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4897 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4898 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4899 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4900 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4901 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4902 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4903 []>, EVEX, EVEX_B;
4904 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4905 (ins KRC:$mask, RC:$src),
4906 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4907 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4908 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4909 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4910 (ins KRC:$mask, x86memop:$src),
4911 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4912 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4913 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4914 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4915 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4916 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4917 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4918 BrdcstStr, "}"),
4919 []>, EVEX, EVEX_KZ, EVEX_B;
4920
4921 let Constraints = "$src1 = $dst" in {
4922 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4923 (ins RC:$src1, KRC:$mask, RC:$src2),
4924 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4925 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4926 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4927 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4928 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4929 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4930 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4931 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4932 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4933 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4934 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4935 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4936 []>, EVEX, EVEX_K, EVEX_B;
4937 }
4938}
4939
4940let Predicates = [HasCDI] in {
4941defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4942 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4943 EVEX_V512, EVEX_CD8<32, CD8VF>;
4944
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4945
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4946defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4947 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4949
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4950}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4951
4952def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4953 GR16:$mask),
4954 (VPCONFLICTDrrk VR512:$src1,
4955 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4956
4957def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4958 GR8:$mask),
4959 (VPCONFLICTQrrk VR512:$src1,
4960 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4961
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4962let Predicates = [HasCDI] in {
4963defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4964 i512mem, i32mem, "{1to16}">,
4965 EVEX_V512, EVEX_CD8<32, CD8VF>;
4966
4967
4968defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4969 i512mem, i64mem, "{1to8}">,
4970 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4971
4972}
4973
4974def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4975 GR16:$mask),
4976 (VPLZCNTDrrk VR512:$src1,
4977 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4978
4979def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4980 GR8:$mask),
4981 (VPLZCNTQrrk VR512:$src1,
4982 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4983
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]4984def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4985 (VPLZCNTDrm addr:$src)>;
4986def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4987 (VPLZCNTDrr VR512:$src)>;
4988def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4989 (VPLZCNTQrm addr:$src)>;
4990def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4991 (VPLZCNTQrr VR512:$src)>;
4992
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4993def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4994def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4995def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]4996
4997def : Pat<(store VK1:$src, addr:$dst),
4998 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4999
5000def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5001 (truncstore node:$val, node:$ptr), [{
5002 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5003}]>;
5004
5005def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5006 (MOV8mr addr:$dst, GR8:$src)>;
5007