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gerrit-public.fairphone.software / toolchain / llvm-project / 52266388f8941adff5f7ca6c246d14a40a6ddbc0 / . / llvm / lib / Target / X86 / X86InstrFragmentsSIMD.td
blob: 0a9f9d88251c2bc2b278b586a90136166725d9f9 [file] [log] [blame]
Jia Liue1d61962012-02-19 02:03:36 +0000[diff] [blame]1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file provides pattern fragments useful for SIMD instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
Bruno Cardoso Lopese446aef2015-02-05 13:22:50 +0000[diff] [blame]15// MMX specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18// Low word of MMX to GPR.
19def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
Bruno Cardoso Lopesab9ae872015-02-05 13:23:07 +0000[diff] [blame]21// GPR to low word of MMX.
22def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
Bruno Cardoso Lopese446aef2015-02-05 13:22:50 +0000[diff] [blame]24
25//===----------------------------------------------------------------------===//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]26// MMX Pattern Fragments
27//===----------------------------------------------------------------------===//
28
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]29def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
Bruno Cardoso Lopes9e1c4c12015-02-23 15:23:14 +0000[diff] [blame]30def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]32def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]33
34//===----------------------------------------------------------------------===//
35// SSE specific DAG Nodes.
36//===----------------------------------------------------------------------===//
37
38def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
39 SDTCisFP<0>, SDTCisInt<2> ]>;
40def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]41 SDTCisFP<1>, SDTCisVT<3, i8>,
42 SDTCisVec<1>]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]43
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]44def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
45def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
46def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
47def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
48
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]49def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
50def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
Nadav Rotem178250a2012-08-19 13:06:16 +0000[diff] [blame]51
52// Commutative and Associative FMIN and FMAX.
53def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]58def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
Benjamin Kramer5bc180c2013-08-04 12:05:16 +0000[diff] [blame]64def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
65 [SDNPCommutative, SDNPAssociative]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]66def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
67def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
68def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
Stuart Hastings9f208042011-06-01 04:39:42 +0000[diff] [blame]69def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
Duncan Sands0e4fcb82011-09-22 20:15:48 +0000[diff] [blame]70def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
71def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
Craig Topperf984efb2011-11-19 09:02:40 +0000[diff] [blame]72def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
73def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]74def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
75def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]76def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
77//def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]78def X86pshufb : SDNode<"X86ISD::PSHUFB",
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]80 SDTCisSameAs<0,2>]>>;
Bruno Cardoso Lopes7ba479d2011-07-13 21:36:47 +0000[diff] [blame]81def X86andnp : SDNode<"X86ISD::ANDNP",
Bruno Cardoso Lopes9613b642011-07-13 21:36:51 +0000[diff] [blame]82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Nate Begeman97b72c92010-12-17 22:55:37 +0000[diff] [blame]83 SDTCisSameAs<0,2>]>>;
Craig Topper81390be2011-11-19 07:33:10 +0000[diff] [blame]84def X86psign : SDNode<"X86ISD::PSIGN",
Craig Topperde6b73b2011-11-19 07:07:26 +0000[diff] [blame]85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Nate Begeman97b72c92010-12-17 22:55:37 +0000[diff] [blame]86 SDTCisSameAs<0,2>]>>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]87def X86pextrb : SDNode<"X86ISD::PEXTRB",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89def X86pextrw : SDNode<"X86ISD::PEXTRW",
90 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
91def X86pinsrb : SDNode<"X86ISD::PINSRB",
92 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
93 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
94def X86pinsrw : SDNode<"X86ISD::PINSRW",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]97def X86insertps : SDNode<"X86ISD::INSERTPS",
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]98 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]99 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]100def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
101 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
Elena Demikhovsky8d7e56c2012-04-22 09:39:03 +0000[diff] [blame]102
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]103def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
Chris Lattner54e53292010-09-22 00:34:38 +0000[diff] [blame]104 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]105
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]106def X86vzext : SDNode<"X86ISD::VZEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]110
111def X86vsext : SDNode<"X86ISD::VSEXT",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]115
Elena Demikhovsky980c6b02013-08-29 11:56:53 +0000[diff] [blame]116def X86vtrunc : SDNode<"X86ISD::VTRUNC",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<0, 1>]>>;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]120def X86trunc : SDNode<"X86ISD::TRUNC",
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]121 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
123
Elena Demikhovsky980c6b02013-08-29 11:56:53 +0000[diff] [blame]124def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
125 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
126 SDTCisInt<0>, SDTCisInt<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]127 SDTCisVec<2>, SDTCisInt<2>,
128 SDTCisOpSmallerThanOp<0, 2>]>>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]129def X86vfpext : SDNode<"X86ISD::VFPEXT",
130 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]131 SDTCisFP<0>, SDTCisFP<1>,
132 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liaoe999b862012-10-10 16:53:28 +0000[diff] [blame]133def X86vfpround: SDNode<"X86ISD::VFPROUND",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<0, 1>]>>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]137
Craig Topper09462642012-01-22 19:15:14 +0000[diff] [blame]138def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
139def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
Craig Topper0b7ad762012-01-22 23:36:02 +0000[diff] [blame]140def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
Craig Topperbd4884372012-01-22 22:42:16 +0000[diff] [blame]141def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
142def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]143
Elena Demikhovsky60b1f282013-08-13 13:24:07 +0000[diff] [blame]144def X86IntCmpMask : SDTypeProfile<1, 2,
145 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
146def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
147def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
148
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]149def X86CmpMaskCC :
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]150 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
151 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]152def X86CmpMaskCCScalar :
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
154
Elena Demikhovsky60b1f282013-08-13 13:24:07 +0000[diff] [blame]155def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
156def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]157def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
Elena Demikhovsky60b1f282013-08-13 13:24:07 +0000[diff] [blame]158
Craig Topper09462642012-01-22 19:15:14 +0000[diff] [blame]159def X86vshl : SDNode<"X86ISD::VSHL",
160 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
161 SDTCisVec<2>]>>;
162def X86vsrl : SDNode<"X86ISD::VSRL",
163 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
164 SDTCisVec<2>]>>;
165def X86vsra : SDNode<"X86ISD::VSRA",
166 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
167 SDTCisVec<2>]>>;
168
169def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
170def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
171def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
172
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]173def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
Bruno Cardoso Lopes91d61df2010-08-10 23:25:42 +0000[diff] [blame]174 SDTCisVec<1>,
175 SDTCisSameAs<2, 1>]>;
Elena Demikhovsky52266382015-05-04 12:35:55 +0000[diff] [blame^]176def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
Benjamin Kramerb16ccde2012-12-15 16:47:44 +0000[diff] [blame]177def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
Elena Demikhovsky52266382015-05-04 12:35:55 +0000[diff] [blame^]178def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
179def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]180def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
Bruno Cardoso Lopes91d61df2010-08-10 23:25:42 +0000[diff] [blame]181def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
Elena Demikhovsky40864b62013-08-05 08:52:21 +0000[diff] [blame]182def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]183def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
Elena Demikhovsky431b81e2015-04-21 13:13:46 +0000[diff] [blame]184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCVecEltisVT<0, i1>,
186 SDTCisSameNumEltsAs<0, 1>]>>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]187def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
Elena Demikhovsky431b81e2015-04-21 13:13:46 +0000[diff] [blame]188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCVecEltisVT<0, i1>,
190 SDTCisSameNumEltsAs<0, 1>]>>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]191def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]192
Craig Topper1d471e32012-02-05 03:14:49 +0000[diff] [blame]193def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
194 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
195 SDTCisSameAs<1,2>]>>;
Benjamin Kramer6d2dff62014-04-26 14:12:19 +0000[diff] [blame]196def X86pmuldq : SDNode<"X86ISD::PMULDQ",
197 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
198 SDTCisSameAs<1,2>]>>;
Craig Topper1d471e32012-02-05 03:14:49 +0000[diff] [blame]199
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]200// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
201// translated into one of the target nodes below during lowering.
202// Note: this is a work in progress...
203def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
204def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
205 SDTCisSameAs<0,2>]>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]206def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]208
Chandler Carruth6d5916a2014-09-23 10:08:29 +0000[diff] [blame]209def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 SDTCisVec<2>]>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]211def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
212 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
213def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
215
Elena Demikhovsky45c54ad2013-08-07 12:34:55 +0000[diff] [blame]216def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
217def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
218
Nadav Rotem9bc178a2012-04-11 06:40:27 +0000[diff] [blame]219def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]220 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]221
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]222def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
223 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
224
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]225def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
226 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
Elena Demikhovsky7b0dd392015-01-28 10:21:27 +0000[diff] [blame]227def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
228 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]229def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
230 SDTCisVec<0>, SDTCisInt<2>]>;
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000[diff] [blame]231def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
232 SDTCisVec<0>, SDTCisInt<3>]>;
Elena Demikhovsky52e81bc2015-02-23 15:12:31 +0000[diff] [blame]233def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
234 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]235
Craig Topper8fb09f02013-01-28 06:48:25 +0000[diff] [blame]236def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
Adam Nemet2f10cc62014-08-05 17:22:55 +0000[diff] [blame]237def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]238
239def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
240def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
241def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
242
Craig Topper6e54ba72011-12-31 23:50:21 +0000[diff] [blame]243def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]244
245def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
246def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
247def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
248
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]249def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
250def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
251
252def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]253def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
Bruno Cardoso Lopes03e4c352010-08-31 21:15:21 +0000[diff] [blame]254def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]255
Bruno Cardoso Lopesb3825212010-09-01 05:08:25 +0000[diff] [blame]256def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
257def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]258
Chandler Carruth8366ceb2014-06-20 01:05:28 +0000[diff] [blame]259def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
260def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
261def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
262
Craig Topper8d4ba192011-12-06 08:21:25 +0000[diff] [blame]263def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
264def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]265
Chandler Carruth6d5916a2014-09-23 10:08:29 +0000[diff] [blame]266def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]267def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
268def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
269def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
270def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]271def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
Bruno Cardoso Lopesb878caa2011-07-21 01:55:47 +0000[diff] [blame]272
Craig Topper0a672ea2011-11-30 07:47:51 +0000[diff] [blame]273def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
Bruno Cardoso Lopesf15dfe52011-08-12 21:48:26 +0000[diff] [blame]274
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]275def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
Elena Demikhovsky45c54ad2013-08-07 12:34:55 +0000[diff] [blame]276def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
Elena Demikhovsky89529742013-09-12 08:55:00 +0000[diff] [blame]277def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
278 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]279def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
280 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]281
Elena Demikhovskycd3c1c42012-12-05 09:24:57 +0000[diff] [blame]282def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
Chandler Carruth204ad4c2014-09-15 20:09:47 +0000[diff] [blame]283
284def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
285
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]286def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
287def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
288def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
289def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
Elena Demikhovsky02ffd262015-03-01 07:44:04 +0000[diff] [blame]290def X86fmaxRnd : SDNode<"X86ISD::FMAX", SDTFPBinOpRound>;
291def X86fminRnd : SDNode<"X86ISD::FMIN", SDTFPBinOpRound>;
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]292
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]293def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
294def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
295def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
296def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
Craig Toppera999c662012-08-29 07:18:25 +0000[diff] [blame]297def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
298def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
Nadav Rotem9bc178a2012-04-11 06:40:27 +0000[diff] [blame]299
Elena Demikhovsky7b0dd392015-01-28 10:21:27 +0000[diff] [blame]300def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
301def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
302def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
303def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
304def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
305def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
306
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]307def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
308def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000[diff] [blame]309def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
310
311def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
312def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
Elena Demikhovsky52e81bc2015-02-23 15:12:31 +0000[diff] [blame]313def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]314
Craig Topperab47fe42012-08-06 06:22:36 +0000[diff] [blame]315def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
316 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
317 SDTCisVT<4, i8>]>;
318def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
319 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
320 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
321 SDTCisVT<6, i8>]>;
322
323def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
324def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
325
Elena Demikhovsky908dbf42014-12-11 15:02:24 +0000[diff] [blame]326def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
327 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
328 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
Elena Demikhovsky72860c32014-12-15 10:03:52 +0000[diff] [blame]329def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
330 [SDTCisSameAs<0, 3>,
331 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
Elena Demikhovsky908dbf42014-12-11 15:02:24 +0000[diff] [blame]332
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]333//===----------------------------------------------------------------------===//
334// SSE Complex Patterns
335//===----------------------------------------------------------------------===//
336
337// These are 'extloads' from a scalar to the low element of a vector, zeroing
338// the top elements. These are used for the SSE 'ss' and 'sd' instruction
339// forms.
340def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
Chris Lattner0e023ea2010-09-21 20:31:19 +0000[diff] [blame]341 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
342 SDNPWantRoot]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]343def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
Chris Lattner0e023ea2010-09-21 20:31:19 +0000[diff] [blame]344 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
345 SDNPWantRoot]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]346
347def ssmem : Operand<v4f32> {
348 let PrintMethod = "printf32mem";
349 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
Craig Topper6269f492013-08-26 00:39:04 +0000[diff] [blame]350 let ParserMatchClass = X86Mem32AsmOperand;
Benjamin Kramer9654eef2011-07-14 21:47:22 +0000[diff] [blame]351 let OperandType = "OPERAND_MEMORY";
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]352}
353def sdmem : Operand<v2f64> {
354 let PrintMethod = "printf64mem";
355 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
Craig Topper6269f492013-08-26 00:39:04 +0000[diff] [blame]356 let ParserMatchClass = X86Mem64AsmOperand;
Benjamin Kramer9654eef2011-07-14 21:47:22 +0000[diff] [blame]357 let OperandType = "OPERAND_MEMORY";
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]358}
359
360//===----------------------------------------------------------------------===//
361// SSE pattern fragments
362//===----------------------------------------------------------------------===//
363
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]364// 128-bit load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]365// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]366def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
367def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]368def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
369
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]370// 256-bit load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]371// NOTE: all 256-bit integer vector loads are promoted to v4i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]372def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
373def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]374def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
375
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]376// 512-bit load pattern fragments
377def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
378def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]379def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
380def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]381def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]382def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
383
384// 128-/256-/512-bit extload pattern fragments
Michael Liao400f7ef2012-09-10 18:33:51 +0000[diff] [blame]385def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
386def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]387def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
Michael Liao400f7ef2012-09-10 18:33:51 +0000[diff] [blame]388
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]389// These are needed to match a scalar load that is used in a vector-only
390// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
391// The memory operand is required to be a 128-bit load, so it must be converted
392// from a vector to a scalar.
393def loadf32_128 : PatFrag<(ops node:$ptr),
394 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
395def loadf64_128 : PatFrag<(ops node:$ptr),
396 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
397
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]398// Like 'store', but always requires 128-bit vector alignment.
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]399def alignedstore : PatFrag<(ops node:$val, node:$ptr),
400 (store node:$val, node:$ptr), [{
401 return cast<StoreSDNode>(N)->getAlignment() >= 16;
402}]>;
403
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]404// Like 'store', but always requires 256-bit vector alignment.
405def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
406 (store node:$val, node:$ptr), [{
407 return cast<StoreSDNode>(N)->getAlignment() >= 32;
408}]>;
409
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]410// Like 'store', but always requires 512-bit vector alignment.
411def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() >= 64;
414}]>;
415
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]416// Like 'load', but always requires 128-bit vector alignment.
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]417def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
418 return cast<LoadSDNode>(N)->getAlignment() >= 16;
419}]>;
420
Chad Rosiera281afc2012-03-09 02:00:48 +0000[diff] [blame]421// Like 'X86vzload', but always requires 128-bit vector alignment.
422def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
423 return cast<MemSDNode>(N)->getAlignment() >= 16;
424}]>;
425
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]426// Like 'load', but always requires 256-bit vector alignment.
427def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
428 return cast<LoadSDNode>(N)->getAlignment() >= 32;
429}]>;
430
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]431// Like 'load', but always requires 512-bit vector alignment.
432def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
433 return cast<LoadSDNode>(N)->getAlignment() >= 64;
434}]>;
435
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]436def alignedloadfsf32 : PatFrag<(ops node:$ptr),
437 (f32 (alignedload node:$ptr))>;
438def alignedloadfsf64 : PatFrag<(ops node:$ptr),
439 (f64 (alignedload node:$ptr))>;
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]440
441// 128-bit aligned load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]442// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]443def alignedloadv4f32 : PatFrag<(ops node:$ptr),
444 (v4f32 (alignedload node:$ptr))>;
445def alignedloadv2f64 : PatFrag<(ops node:$ptr),
446 (v2f64 (alignedload node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]447def alignedloadv2i64 : PatFrag<(ops node:$ptr),
448 (v2i64 (alignedload node:$ptr))>;
449
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]450// 256-bit aligned load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]451// NOTE: all 256-bit integer vector loads are promoted to v4i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]452def alignedloadv8f32 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]453 (v8f32 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]454def alignedloadv4f64 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]455 (v4f64 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]456def alignedloadv4i64 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]457 (v4i64 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]458
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]459// 512-bit aligned load pattern fragments
460def alignedloadv16f32 : PatFrag<(ops node:$ptr),
461 (v16f32 (alignedload512 node:$ptr))>;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]462def alignedloadv16i32 : PatFrag<(ops node:$ptr),
463 (v16i32 (alignedload512 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]464def alignedloadv8f64 : PatFrag<(ops node:$ptr),
465 (v8f64 (alignedload512 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]466def alignedloadv8i64 : PatFrag<(ops node:$ptr),
467 (v8i64 (alignedload512 node:$ptr))>;
468
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]469// Like 'load', but uses special alignment checks suitable for use in
470// memory operands in most SSE instructions, which are required to
471// be naturally aligned on some targets but not on others. If the subtarget
472// allows unaligned accesses, match any load, though this may require
473// setting a feature bit in the processor (on startup, for example).
474// Opteron 10h and later implement such a feature.
475def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
Sanjay Patelffd039b2015-02-03 17:13:04 +0000[diff] [blame]476 return Subtarget->hasSSEUnalignedMem()
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]477 || cast<LoadSDNode>(N)->getAlignment() >= 16;
478}]>;
479
480def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
481def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]482
483// 128-bit memop pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]484// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]485def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
486def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]487def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]488
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]489// These are needed to match a scalar memop that is used in a vector-only
490// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
491// The memory operand is required to be a 128-bit load, so it must be converted
492// from a vector to a scalar.
493def memopfsf32_128 : PatFrag<(ops node:$ptr),
494 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
495def memopfsf64_128 : PatFrag<(ops node:$ptr),
496 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
497
498
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]499// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
500// 16-byte boundary.
501// FIXME: 8 byte alignment for mmx reads is not required
502def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
503 return cast<LoadSDNode>(N)->getAlignment() >= 8;
504}]>;
505
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]506def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]507
508// MOVNT Support
509// Like 'store', but requires the non-temporal bit to be set
510def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
511 (st node:$val, node:$ptr), [{
512 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
513 return ST->isNonTemporal();
514 return false;
515}]>;
516
517def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
Bill Wendlingea6397f2012-07-19 00:11:40 +0000[diff] [blame]518 (st node:$val, node:$ptr), [{
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]519 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
520 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
521 ST->getAddressingMode() == ISD::UNINDEXED &&
522 ST->getAlignment() >= 16;
523 return false;
524}]>;
525
526def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
Bill Wendlingea6397f2012-07-19 00:11:40 +0000[diff] [blame]527 (st node:$val, node:$ptr), [{
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]528 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
529 return ST->isNonTemporal() &&
530 ST->getAlignment() < 16;
531 return false;
532}]>;
533
Elena Demikhovskye1eda8a2015-04-30 08:38:48 +0000[diff] [blame]534def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
535 (masked_gather node:$src1, node:$src2, node:$src3) , [{
536 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
537 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
538 Mgt->getBasePtr().getValueType() == MVT::v8i32);
539 return false;
540}]>;
541
542def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
543 (masked_gather node:$src1, node:$src2, node:$src3) , [{
544 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
545 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
546 Mgt->getBasePtr().getValueType() == MVT::v8i64);
547 return false;
548}]>;
549def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
550 (masked_gather node:$src1, node:$src2, node:$src3) , [{
551 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
552 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
553 Mgt->getBasePtr().getValueType() == MVT::v16i32);
554 return false;
555}]>;
556
557def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
558 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
559 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
560 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
561 Sc->getBasePtr().getValueType() == MVT::v8i32);
562 return false;
563}]>;
564
565def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
566 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
567 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
568 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
569 Sc->getBasePtr().getValueType() == MVT::v8i64);
570 return false;
571}]>;
572def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
573 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
574 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
575 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
576 Sc->getBasePtr().getValueType() == MVT::v16i32);
577 return false;
578}]>;
579
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]580// 128-bit bitconvert pattern fragments
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]581def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
582def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
583def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
584def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
585def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
586def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
587
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]588// 256-bit bitconvert pattern fragments
Craig Topper682b8502011-11-02 04:42:13 +0000[diff] [blame]589def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
590def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
Bruno Cardoso Lopese3acfd42010-07-21 23:53:50 +0000[diff] [blame]591def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
Bruno Cardoso Lopes1021b4a2011-07-13 01:15:33 +0000[diff] [blame]592def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]593def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
Bruno Cardoso Lopese3acfd42010-07-21 23:53:50 +0000[diff] [blame]594
Craig Topper8c929622013-08-16 06:07:34 +0000[diff] [blame]595// 512-bit bitconvert pattern fragments
596def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
597def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]598def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
599def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
Craig Topper8c929622013-08-16 06:07:34 +0000[diff] [blame]600
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]601def vzmovl_v2i64 : PatFrag<(ops node:$src),
602 (bitconvert (v2i64 (X86vzmovl
603 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
604def vzmovl_v4i32 : PatFrag<(ops node:$src),
605 (bitconvert (v4i32 (X86vzmovl
606 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
607
608def vzload_v2i64 : PatFrag<(ops node:$src),
609 (bitconvert (v2i64 (X86vzload node:$src)))>;
610
611
612def fp32imm0 : PatLeaf<(f32 fpimm), [{
613 return N->isExactlyValue(+0.0);
614}]>;
615
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]616def I8Imm : SDNodeXForm<imm, [{
617 // Transformation function: get the low 8 bits.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]618 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]619}]>;
620
621def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
Adam Nemet50b83f02014-08-14 17:13:26 +0000[diff] [blame]622def FROUND_CURRENT : ImmLeaf<i32, [{
623 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
624}]>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]625
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]626// BYTE_imm - Transform bit immediates into byte immediates.
627def BYTE_imm : SDNodeXForm<imm, [{
628 // Transformation function: imm >> 3
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]629 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]630}]>;
631
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]632// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
633// to VEXTRACTF128/VEXTRACTI128 imm.
634def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]635 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
David Greenec4da1102011-02-03 15:50:00 +0000[diff] [blame]636}]>;
637
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]638// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
639// VINSERTF128/VINSERTI128 imm.
640def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]641 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]642}]>;
643
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]644// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
645// to VEXTRACTF64x4 imm.
646def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]647 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]648}]>;
649
650// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
651// VINSERTF64x4 imm.
652def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]653 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]654}]>;
655
656def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
David Greenec4da1102011-02-03 15:50:00 +0000[diff] [blame]657 (extract_subvector node:$bigvec,
658 node:$index), [{
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]659 return X86::isVEXTRACT128Index(N);
660}], EXTRACT_get_vextract128_imm>;
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]661
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]662def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]663 node:$index),
664 (insert_subvector node:$bigvec, node:$smallvec,
665 node:$index), [{
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]666 return X86::isVINSERT128Index(N);
667}], INSERT_get_vinsert128_imm>;
668
669
670def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
671 (extract_subvector node:$bigvec,
672 node:$index), [{
673 return X86::isVEXTRACT256Index(N);
674}], EXTRACT_get_vextract256_imm>;
675
676def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
677 node:$index),
678 (insert_subvector node:$bigvec, node:$smallvec,
679 node:$index), [{
680 return X86::isVINSERT256Index(N);
681}], INSERT_get_vinsert256_imm>;
Bruno Cardoso Lopes123dff02011-07-25 23:05:25 +0000[diff] [blame]682
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]683def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
684 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]685 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
686 return Load->getAlignment() >= 16;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]687 return false;
688}]>;
689
690def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
691 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]692 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
693 return Load->getAlignment() >= 32;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]694 return false;
695}]>;
696
697def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
698 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]699 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
700 return Load->getAlignment() >= 64;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]701 return false;
702}]>;
703
704def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
705 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]706 return isa<MaskedLoadSDNode>(N);
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]707}]>;
708
709def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
710 (masked_store node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]711 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
712 return Store->getAlignment() >= 16;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]713 return false;
714}]>;
715
716def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
717 (masked_store node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]718 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
719 return Store->getAlignment() >= 32;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]720 return false;
721}]>;
722
723def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
724 (masked_store node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]725 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
726 return Store->getAlignment() >= 64;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]727 return false;
728}]>;
729
730def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
731 (masked_store node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]732 return isa<MaskedStoreSDNode>(N);
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]733}]>;
734